2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 #include "nouveau_util.h"
61 #include "nouveau_vm.h"
63 #define MAX_NUM_DCB_ENTRIES 16
65 #define NOUVEAU_MAX_CHANNEL_NR 128
66 #define NOUVEAU_MAX_TILE_NR 15
69 struct drm_device *dev;
71 struct nouveau_vma bar_vma;
72 struct nouveau_vma tmp_vma;
75 struct drm_mm_node *tag;
76 struct list_head regions;
83 struct nouveau_tile_reg {
89 struct drm_mm_node *tag_mem;
90 struct nouveau_fence *fence;
94 struct ttm_buffer_object bo;
95 struct ttm_placement placement;
98 u32 busy_placements[3];
99 struct ttm_bo_kmap_obj kmap;
100 struct list_head head;
102 /* protected by ttm_bo_reserve() */
103 struct drm_file *reserved_by;
104 struct list_head entry;
106 bool validate_mapped;
108 struct nouveau_channel *channel;
110 struct nouveau_vma vma;
114 struct nouveau_tile_reg *tile;
116 struct drm_gem_object *gem;
120 #define nouveau_bo_tile_layout(nvbo) \
121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
123 static inline struct nouveau_bo *
124 nouveau_bo(struct ttm_buffer_object *bo)
126 return container_of(bo, struct nouveau_bo, bo);
129 static inline struct nouveau_bo *
130 nouveau_gem_object(struct drm_gem_object *gem)
132 return gem ? gem->driver_private : NULL;
135 /* TODO: submit equivalent to TTM generic API upstream? */
136 static inline void __iomem *
137 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
141 &nvbo->kmap, &is_iomem);
142 WARN_ON_ONCE(ioptr && !is_iomem);
147 NV_NFORCE = 0x10000000,
148 NV_NFORCE2 = 0x20000000
151 #define NVOBJ_ENGINE_SW 0
152 #define NVOBJ_ENGINE_GR 1
153 #define NVOBJ_ENGINE_CRYPT 2
154 #define NVOBJ_ENGINE_DISPLAY 15
155 #define NVOBJ_ENGINE_NR 16
157 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
158 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
159 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
160 #define NVOBJ_FLAG_VM (1 << 3)
161 #define NVOBJ_FLAG_VM_USER (1 << 4)
163 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
165 struct nouveau_gpuobj {
166 struct drm_device *dev;
167 struct kref refcount;
168 struct list_head list;
183 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
187 struct nouveau_page_flip_state {
188 struct list_head head;
189 struct drm_pending_vblank_event *event;
190 int crtc, bpp, pitch, x, y;
194 enum nouveau_channel_mutex_class {
195 NOUVEAU_UCHANNEL_MUTEX,
196 NOUVEAU_KCHANNEL_MUTEX
199 struct nouveau_channel {
200 struct drm_device *dev;
203 /* references to the channel data structure */
205 /* users of the hardware channel resources, the hardware
206 * context will be kicked off when it reaches zero. */
210 /* owner of this fifo */
211 struct drm_file *file_priv;
212 /* mapping of the fifo itself */
213 struct drm_local_map *map;
215 /* mapping of the regs controlling the fifo */
222 /* lock protects the pending list only */
224 struct list_head pending;
226 uint32_t sequence_ack;
227 atomic_t last_sequence_irq;
230 /* DMA push buffer */
231 struct nouveau_gpuobj *pushbuf;
232 struct nouveau_bo *pushbuf_bo;
233 uint32_t pushbuf_base;
235 /* Notifier memory */
236 struct nouveau_bo *notifier_bo;
237 struct drm_mm notifier_heap;
240 struct nouveau_gpuobj *ramfc;
241 struct nouveau_gpuobj *cache;
245 /* XXX may be merge 2 pointers as private data ??? */
246 struct nouveau_gpuobj *ramin_grctx;
248 void *engctx[NVOBJ_ENGINE_NR];
251 struct nouveau_vm *vm;
252 struct nouveau_gpuobj *vm_pd;
255 struct nouveau_gpuobj *ramin; /* Private instmem */
256 struct drm_mm ramin_heap; /* Private PRAMIN heap */
257 struct nouveau_ramht *ramht; /* Hash table */
259 /* GPU object info for stuff used in-kernel (mm_enabled) */
261 uint32_t vram_handle;
262 uint32_t gart_handle;
265 /* Push buffer state (only for drm's channel on !mm_enabled) */
271 /* access via pushbuf_bo */
279 uint32_t sw_subchannel[8];
282 struct nouveau_gpuobj *vblsem;
283 uint32_t vblsem_head;
284 uint32_t vblsem_offset;
285 uint32_t vblsem_rval;
286 struct list_head vbl_wait;
287 struct list_head flip;
293 struct drm_info_list info;
297 struct nouveau_exec_engine {
298 void (*destroy)(struct drm_device *, int engine);
299 int (*init)(struct drm_device *, int engine);
300 int (*fini)(struct drm_device *, int engine);
301 int (*context_new)(struct nouveau_channel *, int engine);
302 void (*context_del)(struct nouveau_channel *, int engine);
303 int (*object_new)(struct nouveau_channel *, int engine,
304 u32 handle, u16 class);
305 void (*tlb_flush)(struct drm_device *, int engine);
308 struct nouveau_instmem_engine {
311 int (*init)(struct drm_device *dev);
312 void (*takedown)(struct drm_device *dev);
313 int (*suspend)(struct drm_device *dev);
314 void (*resume)(struct drm_device *dev);
316 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
317 void (*put)(struct nouveau_gpuobj *);
318 int (*map)(struct nouveau_gpuobj *);
319 void (*unmap)(struct nouveau_gpuobj *);
321 void (*flush)(struct drm_device *);
324 struct nouveau_mc_engine {
325 int (*init)(struct drm_device *dev);
326 void (*takedown)(struct drm_device *dev);
329 struct nouveau_timer_engine {
330 int (*init)(struct drm_device *dev);
331 void (*takedown)(struct drm_device *dev);
332 uint64_t (*read)(struct drm_device *dev);
335 struct nouveau_fb_engine {
337 struct drm_mm tag_heap;
340 int (*init)(struct drm_device *dev);
341 void (*takedown)(struct drm_device *dev);
343 void (*init_tile_region)(struct drm_device *dev, int i,
344 uint32_t addr, uint32_t size,
345 uint32_t pitch, uint32_t flags);
346 void (*set_tile_region)(struct drm_device *dev, int i);
347 void (*free_tile_region)(struct drm_device *dev, int i);
350 struct nouveau_fifo_engine {
354 struct nouveau_gpuobj *playlist[2];
357 int (*init)(struct drm_device *);
358 void (*takedown)(struct drm_device *);
360 void (*disable)(struct drm_device *);
361 void (*enable)(struct drm_device *);
362 bool (*reassign)(struct drm_device *, bool enable);
363 bool (*cache_pull)(struct drm_device *dev, bool enable);
365 int (*channel_id)(struct drm_device *);
367 int (*create_context)(struct nouveau_channel *);
368 void (*destroy_context)(struct nouveau_channel *);
369 int (*load_context)(struct nouveau_channel *);
370 int (*unload_context)(struct drm_device *);
371 void (*tlb_flush)(struct drm_device *dev);
374 struct nouveau_pgraph_engine {
380 /* NV2x/NV3x context table (0x400780) */
381 struct nouveau_gpuobj *ctx_table;
383 int (*init)(struct drm_device *);
384 void (*takedown)(struct drm_device *);
386 void (*fifo_access)(struct drm_device *, bool);
388 struct nouveau_channel *(*channel)(struct drm_device *);
389 int (*create_context)(struct nouveau_channel *);
390 void (*destroy_context)(struct nouveau_channel *);
391 int (*load_context)(struct nouveau_channel *);
392 int (*unload_context)(struct drm_device *);
393 int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class);
394 void (*tlb_flush)(struct drm_device *dev);
396 void (*set_tile_region)(struct drm_device *dev, int i);
399 struct nouveau_display_engine {
401 int (*early_init)(struct drm_device *);
402 void (*late_takedown)(struct drm_device *);
403 int (*create)(struct drm_device *);
404 int (*init)(struct drm_device *);
405 void (*destroy)(struct drm_device *);
408 struct nouveau_gpio_engine {
411 int (*init)(struct drm_device *);
412 void (*takedown)(struct drm_device *);
414 int (*get)(struct drm_device *, enum dcb_gpio_tag);
415 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
417 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
418 void (*)(void *, int), void *);
419 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
420 void (*)(void *, int), void *);
421 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
424 struct nouveau_pm_voltage_level {
429 struct nouveau_pm_voltage {
433 struct nouveau_pm_voltage_level *level;
437 #define NOUVEAU_PM_MAX_LEVEL 8
438 struct nouveau_pm_level {
439 struct device_attribute dev_attr;
454 struct nouveau_pm_temp_sensor_constants {
462 struct nouveau_pm_threshold_temp {
468 struct nouveau_pm_memtiming {
480 struct nouveau_pm_memtimings {
482 struct nouveau_pm_memtiming *timing;
486 struct nouveau_pm_engine {
487 struct nouveau_pm_voltage voltage;
488 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
490 struct nouveau_pm_memtimings memtimings;
491 struct nouveau_pm_temp_sensor_constants sensor_constants;
492 struct nouveau_pm_threshold_temp threshold_temp;
494 struct nouveau_pm_level boot;
495 struct nouveau_pm_level *cur;
497 struct device *hwmon;
498 struct notifier_block acpi_nb;
500 int (*clock_get)(struct drm_device *, u32 id);
501 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
503 void (*clock_set)(struct drm_device *, void *);
504 int (*voltage_get)(struct drm_device *);
505 int (*voltage_set)(struct drm_device *, int voltage);
506 int (*fanspeed_get)(struct drm_device *);
507 int (*fanspeed_set)(struct drm_device *, int fanspeed);
508 int (*temp_get)(struct drm_device *);
511 struct nouveau_vram_engine {
512 int (*init)(struct drm_device *);
513 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
514 u32 type, struct nouveau_mem **);
515 void (*put)(struct drm_device *, struct nouveau_mem **);
517 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
520 struct nouveau_engine {
521 struct nouveau_instmem_engine instmem;
522 struct nouveau_mc_engine mc;
523 struct nouveau_timer_engine timer;
524 struct nouveau_fb_engine fb;
525 struct nouveau_pgraph_engine graph;
526 struct nouveau_fifo_engine fifo;
527 struct nouveau_display_engine display;
528 struct nouveau_gpio_engine gpio;
529 struct nouveau_pm_engine pm;
530 struct nouveau_vram_engine vram;
533 struct nouveau_pll_vals {
537 uint8_t N1, M1, N2, M2;
539 uint8_t M1, N1, M2, N2;
544 } __attribute__((packed));
551 enum nv04_fp_display_regs {
561 struct nv04_crtc_reg {
562 unsigned char MiscOutReg;
565 uint8_t Sequencer[5];
567 uint8_t Attribute[21];
568 unsigned char DAC[768];
578 uint32_t crtc_eng_ctrl;
581 uint32_t nv10_cursync;
582 struct nouveau_pll_vals pllvals;
583 uint32_t ramdac_gen_ctrl;
589 uint32_t tv_vsync_delay;
592 uint32_t tv_hsync_delay;
593 uint32_t tv_hsync_delay2;
594 uint32_t fp_horiz_regs[7];
595 uint32_t fp_vert_regs[7];
598 uint32_t dither_regs[6];
602 uint32_t fp_margin_color;
607 uint32_t ctv_regs[38];
610 struct nv04_output_reg {
615 struct nv04_mode_state {
616 struct nv04_crtc_reg crtc_reg[2];
621 enum nouveau_card_type {
631 struct drm_nouveau_private {
632 struct drm_device *dev;
634 /* the card type, takes NV_* as values */
635 enum nouveau_card_type card_type;
636 /* exact chipset, derived from NV_PMC_BOOT_0 */
643 spinlock_t ramin_lock;
647 bool ramin_available;
648 struct drm_mm ramin_heap;
649 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
650 struct list_head gpuobj_list;
651 struct list_head classes;
653 struct nouveau_bo *vga_ram;
655 /* interrupt handling */
656 void (*irq_handler[32])(struct drm_device *);
659 struct list_head vbl_waiting;
662 struct drm_global_reference mem_global_ref;
663 struct ttm_bo_global_ref bo_global_ref;
664 struct ttm_bo_device bdev;
665 atomic_t validate_sequence;
671 struct nouveau_bo *bo;
676 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
679 struct nouveau_engine engine;
680 struct nouveau_channel *channel;
682 /* For PFIFO and PGRAPH. */
683 spinlock_t context_switch_lock;
685 /* VM/PRAMIN flush, legacy PRAMIN aperture */
688 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
689 struct nouveau_ramht *ramht;
690 struct nouveau_gpuobj *ramfc;
691 struct nouveau_gpuobj *ramro;
693 uint32_t ramin_rsvd_vram;
697 NOUVEAU_GART_NONE = 0,
698 NOUVEAU_GART_AGP, /* AGP */
699 NOUVEAU_GART_PDMA, /* paged dma object */
700 NOUVEAU_GART_HW /* on-chip gart/vm */
706 struct ttm_backend_func *func;
713 struct nouveau_gpuobj *sg_ctxdma;
716 /* nv10-nv40 tiling regions */
718 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
722 /* VRAM/fb configuration */
724 uint64_t vram_sys_base;
725 u32 vram_rblock_size;
728 uint64_t fb_available_size;
729 uint64_t fb_mappable_pages;
730 uint64_t fb_aper_free;
733 /* BAR control (NV50-) */
734 struct nouveau_vm *bar1_vm;
735 struct nouveau_vm *bar3_vm;
737 /* G8x/G9x virtual address space */
738 struct nouveau_vm *chan_vm;
742 struct nv04_mode_state mode_reg;
743 struct nv04_mode_state saved_reg;
744 uint32_t saved_vga_font[4][16384];
746 uint32_t dac_users[4];
748 struct backlight_device *backlight;
751 struct dentry *channel_root;
754 struct nouveau_fbdev *nfbdev;
755 struct apertures_struct *apertures;
758 static inline struct drm_nouveau_private *
759 nouveau_private(struct drm_device *dev)
761 return dev->dev_private;
764 static inline struct drm_nouveau_private *
765 nouveau_bdev(struct ttm_bo_device *bd)
767 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
771 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
773 struct nouveau_bo *prev;
779 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
781 struct ttm_buffer_object *bo = &prev->bo;
790 extern int nouveau_agpmode;
791 extern int nouveau_duallink;
792 extern int nouveau_uscript_lvds;
793 extern int nouveau_uscript_tmds;
794 extern int nouveau_vram_pushbuf;
795 extern int nouveau_vram_notify;
796 extern int nouveau_fbpercrtc;
797 extern int nouveau_tv_disable;
798 extern char *nouveau_tv_norm;
799 extern int nouveau_reg_debug;
800 extern char *nouveau_vbios;
801 extern int nouveau_ignorelid;
802 extern int nouveau_nofbaccel;
803 extern int nouveau_noaccel;
804 extern int nouveau_force_post;
805 extern int nouveau_override_conntype;
806 extern char *nouveau_perflvl;
807 extern int nouveau_perflvl_wr;
808 extern int nouveau_msi;
810 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
811 extern int nouveau_pci_resume(struct pci_dev *pdev);
813 /* nouveau_state.c */
814 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
815 extern int nouveau_load(struct drm_device *, unsigned long flags);
816 extern int nouveau_firstopen(struct drm_device *);
817 extern void nouveau_lastclose(struct drm_device *);
818 extern int nouveau_unload(struct drm_device *);
819 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
821 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
823 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
824 uint32_t reg, uint32_t mask, uint32_t val);
825 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
826 uint32_t reg, uint32_t mask, uint32_t val);
827 extern bool nouveau_wait_for_idle(struct drm_device *);
828 extern int nouveau_card_init(struct drm_device *);
831 extern int nouveau_mem_vram_init(struct drm_device *);
832 extern void nouveau_mem_vram_fini(struct drm_device *);
833 extern int nouveau_mem_gart_init(struct drm_device *);
834 extern void nouveau_mem_gart_fini(struct drm_device *);
835 extern int nouveau_mem_init_agp(struct drm_device *);
836 extern int nouveau_mem_reset_agp(struct drm_device *);
837 extern void nouveau_mem_close(struct drm_device *);
838 extern int nouveau_mem_detect(struct drm_device *);
839 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
840 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
841 struct drm_device *dev, uint32_t addr, uint32_t size,
842 uint32_t pitch, uint32_t flags);
843 extern void nv10_mem_put_tile_region(struct drm_device *dev,
844 struct nouveau_tile_reg *tile,
845 struct nouveau_fence *fence);
846 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
847 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
849 /* nouveau_notifier.c */
850 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
851 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
852 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
853 int cout, uint32_t start, uint32_t end,
855 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
856 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
858 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
861 /* nouveau_channel.c */
862 extern struct drm_ioctl_desc nouveau_ioctls[];
863 extern int nouveau_max_ioctl;
864 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
865 extern int nouveau_channel_alloc(struct drm_device *dev,
866 struct nouveau_channel **chan,
867 struct drm_file *file_priv,
868 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
869 extern struct nouveau_channel *
870 nouveau_channel_get_unlocked(struct nouveau_channel *);
871 extern struct nouveau_channel *
872 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
873 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
874 extern void nouveau_channel_put(struct nouveau_channel **);
875 extern void nouveau_channel_ref(struct nouveau_channel *chan,
876 struct nouveau_channel **pchan);
877 extern void nouveau_channel_idle(struct nouveau_channel *chan);
879 /* nouveau_object.c */
880 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
881 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
882 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
885 #define NVOBJ_ENGINE_DEL(d, e) do { \
886 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
887 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
890 #define NVOBJ_CLASS(d, c, e) do { \
891 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
896 #define NVOBJ_MTHD(d, c, m, e) do { \
897 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
902 extern int nouveau_gpuobj_early_init(struct drm_device *);
903 extern int nouveau_gpuobj_init(struct drm_device *);
904 extern void nouveau_gpuobj_takedown(struct drm_device *);
905 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
906 extern void nouveau_gpuobj_resume(struct drm_device *dev);
907 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
908 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
909 int (*exec)(struct nouveau_channel *,
910 u32 class, u32 mthd, u32 data));
911 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
912 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
913 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
914 uint32_t vram_h, uint32_t tt_h);
915 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
916 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
917 uint32_t size, int align, uint32_t flags,
918 struct nouveau_gpuobj **);
919 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
920 struct nouveau_gpuobj **);
921 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
923 struct nouveau_gpuobj **);
924 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
925 uint64_t offset, uint64_t size, int access,
926 int target, struct nouveau_gpuobj **);
927 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
928 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
929 u64 size, int target, int access, u32 type,
930 u32 comp, struct nouveau_gpuobj **pobj);
931 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
932 int class, u64 base, u64 size, int target,
933 int access, u32 type, u32 comp);
934 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
936 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
940 extern int nouveau_irq_init(struct drm_device *);
941 extern void nouveau_irq_fini(struct drm_device *);
942 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
943 extern void nouveau_irq_register(struct drm_device *, int status_bit,
944 void (*)(struct drm_device *));
945 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
946 extern void nouveau_irq_preinstall(struct drm_device *);
947 extern int nouveau_irq_postinstall(struct drm_device *);
948 extern void nouveau_irq_uninstall(struct drm_device *);
950 /* nouveau_sgdma.c */
951 extern int nouveau_sgdma_init(struct drm_device *);
952 extern void nouveau_sgdma_takedown(struct drm_device *);
953 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
955 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
957 /* nouveau_debugfs.c */
958 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
959 extern int nouveau_debugfs_init(struct drm_minor *);
960 extern void nouveau_debugfs_takedown(struct drm_minor *);
961 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
962 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
965 nouveau_debugfs_init(struct drm_minor *minor)
970 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
975 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
981 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
987 extern void nouveau_dma_pre_init(struct nouveau_channel *);
988 extern int nouveau_dma_init(struct nouveau_channel *);
989 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
992 #define ROM_BIOS_PAGE 4096
993 #if defined(CONFIG_ACPI)
994 void nouveau_register_dsm_handler(void);
995 void nouveau_unregister_dsm_handler(void);
996 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
997 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
998 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1000 static inline void nouveau_register_dsm_handler(void) {}
1001 static inline void nouveau_unregister_dsm_handler(void) {}
1002 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1003 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1004 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1007 /* nouveau_backlight.c */
1008 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1009 extern int nouveau_backlight_init(struct drm_connector *);
1010 extern void nouveau_backlight_exit(struct drm_connector *);
1012 static inline int nouveau_backlight_init(struct drm_connector *dev)
1017 static inline void nouveau_backlight_exit(struct drm_connector *dev) { }
1020 /* nouveau_bios.c */
1021 extern int nouveau_bios_init(struct drm_device *);
1022 extern void nouveau_bios_takedown(struct drm_device *dev);
1023 extern int nouveau_run_vbios_init(struct drm_device *);
1024 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1025 struct dcb_entry *);
1026 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1028 extern struct dcb_connector_table_entry *
1029 nouveau_bios_connector_entry(struct drm_device *, int index);
1030 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1031 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1033 extern int nouveau_bios_run_display_table(struct drm_device *,
1035 uint32_t script, int pxclk);
1036 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1038 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1039 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1040 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1041 bool *dl, bool *if_is_24bit);
1042 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1043 int head, int pxclk);
1044 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1045 enum LVDS_script, int pxclk);
1048 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1049 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1050 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1053 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1054 uint8_t *data, int data_nr);
1055 bool nouveau_dp_detect(struct drm_encoder *);
1056 bool nouveau_dp_link_train(struct drm_encoder *);
1059 extern int nv04_fb_init(struct drm_device *);
1060 extern void nv04_fb_takedown(struct drm_device *);
1063 extern int nv10_fb_init(struct drm_device *);
1064 extern void nv10_fb_takedown(struct drm_device *);
1065 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1066 uint32_t addr, uint32_t size,
1067 uint32_t pitch, uint32_t flags);
1068 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1069 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1072 extern int nv30_fb_init(struct drm_device *);
1073 extern void nv30_fb_takedown(struct drm_device *);
1074 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1075 uint32_t addr, uint32_t size,
1076 uint32_t pitch, uint32_t flags);
1077 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1080 extern int nv40_fb_init(struct drm_device *);
1081 extern void nv40_fb_takedown(struct drm_device *);
1082 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1085 extern int nv50_fb_init(struct drm_device *);
1086 extern void nv50_fb_takedown(struct drm_device *);
1087 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1090 extern int nvc0_fb_init(struct drm_device *);
1091 extern void nvc0_fb_takedown(struct drm_device *);
1094 extern int nv04_fifo_init(struct drm_device *);
1095 extern void nv04_fifo_fini(struct drm_device *);
1096 extern void nv04_fifo_disable(struct drm_device *);
1097 extern void nv04_fifo_enable(struct drm_device *);
1098 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1099 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1100 extern int nv04_fifo_channel_id(struct drm_device *);
1101 extern int nv04_fifo_create_context(struct nouveau_channel *);
1102 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1103 extern int nv04_fifo_load_context(struct nouveau_channel *);
1104 extern int nv04_fifo_unload_context(struct drm_device *);
1105 extern void nv04_fifo_isr(struct drm_device *);
1108 extern int nv10_fifo_init(struct drm_device *);
1109 extern int nv10_fifo_channel_id(struct drm_device *);
1110 extern int nv10_fifo_create_context(struct nouveau_channel *);
1111 extern int nv10_fifo_load_context(struct nouveau_channel *);
1112 extern int nv10_fifo_unload_context(struct drm_device *);
1115 extern int nv40_fifo_init(struct drm_device *);
1116 extern int nv40_fifo_create_context(struct nouveau_channel *);
1117 extern int nv40_fifo_load_context(struct nouveau_channel *);
1118 extern int nv40_fifo_unload_context(struct drm_device *);
1121 extern int nv50_fifo_init(struct drm_device *);
1122 extern void nv50_fifo_takedown(struct drm_device *);
1123 extern int nv50_fifo_channel_id(struct drm_device *);
1124 extern int nv50_fifo_create_context(struct nouveau_channel *);
1125 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1126 extern int nv50_fifo_load_context(struct nouveau_channel *);
1127 extern int nv50_fifo_unload_context(struct drm_device *);
1128 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1131 extern int nvc0_fifo_init(struct drm_device *);
1132 extern void nvc0_fifo_takedown(struct drm_device *);
1133 extern void nvc0_fifo_disable(struct drm_device *);
1134 extern void nvc0_fifo_enable(struct drm_device *);
1135 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1136 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1137 extern int nvc0_fifo_channel_id(struct drm_device *);
1138 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1139 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1140 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1141 extern int nvc0_fifo_unload_context(struct drm_device *);
1144 extern int nv04_graph_init(struct drm_device *);
1145 extern void nv04_graph_takedown(struct drm_device *);
1146 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1147 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1148 extern int nv04_graph_create_context(struct nouveau_channel *);
1149 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1150 extern int nv04_graph_load_context(struct nouveau_channel *);
1151 extern int nv04_graph_unload_context(struct drm_device *);
1152 extern int nv04_graph_object_new(struct nouveau_channel *, u32, u16);
1153 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1154 u32 class, u32 mthd, u32 data);
1155 extern struct nouveau_bitfield nv04_graph_nsource[];
1158 extern int nv10_graph_init(struct drm_device *);
1159 extern void nv10_graph_takedown(struct drm_device *);
1160 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1161 extern int nv10_graph_create_context(struct nouveau_channel *);
1162 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1163 extern int nv10_graph_load_context(struct nouveau_channel *);
1164 extern int nv10_graph_unload_context(struct drm_device *);
1165 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1166 extern struct nouveau_bitfield nv10_graph_intr[];
1167 extern struct nouveau_bitfield nv10_graph_nstatus[];
1170 extern int nv20_graph_create_context(struct nouveau_channel *);
1171 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1172 extern int nv20_graph_load_context(struct nouveau_channel *);
1173 extern int nv20_graph_unload_context(struct drm_device *);
1174 extern int nv20_graph_init(struct drm_device *);
1175 extern void nv20_graph_takedown(struct drm_device *);
1176 extern int nv30_graph_init(struct drm_device *);
1177 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
1180 extern int nv40_graph_init(struct drm_device *);
1181 extern void nv40_graph_takedown(struct drm_device *);
1182 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1183 extern int nv40_graph_create_context(struct nouveau_channel *);
1184 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1185 extern int nv40_graph_load_context(struct nouveau_channel *);
1186 extern int nv40_graph_unload_context(struct drm_device *);
1187 extern int nv40_graph_object_new(struct nouveau_channel *, u32, u16);
1188 extern void nv40_grctx_init(struct nouveau_grctx *);
1189 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
1192 extern int nv50_graph_create(struct drm_device *);
1193 extern int nv50_grctx_init(struct nouveau_grctx *);
1194 extern struct nouveau_enum nv50_data_error_names[];
1197 extern int nvc0_graph_init(struct drm_device *);
1198 extern void nvc0_graph_takedown(struct drm_device *);
1199 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1200 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1201 extern int nvc0_graph_create_context(struct nouveau_channel *);
1202 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1203 extern int nvc0_graph_load_context(struct nouveau_channel *);
1204 extern int nvc0_graph_unload_context(struct drm_device *);
1205 extern int nvc0_graph_object_new(struct nouveau_channel *, u32, u16);
1208 extern int nv84_crypt_create(struct drm_device *);
1210 /* nv04_instmem.c */
1211 extern int nv04_instmem_init(struct drm_device *);
1212 extern void nv04_instmem_takedown(struct drm_device *);
1213 extern int nv04_instmem_suspend(struct drm_device *);
1214 extern void nv04_instmem_resume(struct drm_device *);
1215 extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1216 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1217 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1218 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1219 extern void nv04_instmem_flush(struct drm_device *);
1221 /* nv50_instmem.c */
1222 extern int nv50_instmem_init(struct drm_device *);
1223 extern void nv50_instmem_takedown(struct drm_device *);
1224 extern int nv50_instmem_suspend(struct drm_device *);
1225 extern void nv50_instmem_resume(struct drm_device *);
1226 extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1227 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1228 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1229 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1230 extern void nv50_instmem_flush(struct drm_device *);
1231 extern void nv84_instmem_flush(struct drm_device *);
1233 /* nvc0_instmem.c */
1234 extern int nvc0_instmem_init(struct drm_device *);
1235 extern void nvc0_instmem_takedown(struct drm_device *);
1236 extern int nvc0_instmem_suspend(struct drm_device *);
1237 extern void nvc0_instmem_resume(struct drm_device *);
1240 extern int nv04_mc_init(struct drm_device *);
1241 extern void nv04_mc_takedown(struct drm_device *);
1244 extern int nv40_mc_init(struct drm_device *);
1245 extern void nv40_mc_takedown(struct drm_device *);
1248 extern int nv50_mc_init(struct drm_device *);
1249 extern void nv50_mc_takedown(struct drm_device *);
1252 extern int nv04_timer_init(struct drm_device *);
1253 extern uint64_t nv04_timer_read(struct drm_device *);
1254 extern void nv04_timer_takedown(struct drm_device *);
1256 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1260 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1261 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1262 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1263 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1264 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1267 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1268 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1269 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1271 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1272 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1275 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1276 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1279 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1281 /* nv04_display.c */
1282 extern int nv04_display_early_init(struct drm_device *);
1283 extern void nv04_display_late_takedown(struct drm_device *);
1284 extern int nv04_display_create(struct drm_device *);
1285 extern int nv04_display_init(struct drm_device *);
1286 extern void nv04_display_destroy(struct drm_device *);
1289 extern int nv04_crtc_create(struct drm_device *, int index);
1292 extern struct ttm_bo_driver nouveau_bo_driver;
1293 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1294 int size, int align, uint32_t flags,
1295 uint32_t tile_mode, uint32_t tile_flags,
1296 struct nouveau_bo **);
1297 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1298 extern int nouveau_bo_unpin(struct nouveau_bo *);
1299 extern int nouveau_bo_map(struct nouveau_bo *);
1300 extern void nouveau_bo_unmap(struct nouveau_bo *);
1301 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1303 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1304 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1305 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1306 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1307 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1308 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1309 bool no_wait_reserve, bool no_wait_gpu);
1311 /* nouveau_fence.c */
1312 struct nouveau_fence;
1313 extern int nouveau_fence_init(struct drm_device *);
1314 extern void nouveau_fence_fini(struct drm_device *);
1315 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1316 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1317 extern void nouveau_fence_update(struct nouveau_channel *);
1318 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1320 extern int nouveau_fence_emit(struct nouveau_fence *);
1321 extern void nouveau_fence_work(struct nouveau_fence *fence,
1322 void (*work)(void *priv, bool signalled),
1324 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1326 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1327 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1328 extern int __nouveau_fence_flush(void *obj, void *arg);
1329 extern void __nouveau_fence_unref(void **obj);
1330 extern void *__nouveau_fence_ref(void *obj);
1332 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1334 return __nouveau_fence_signalled(obj, NULL);
1337 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1339 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1341 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1342 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1344 return __nouveau_fence_flush(obj, NULL);
1346 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1348 __nouveau_fence_unref((void **)obj);
1350 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1352 return __nouveau_fence_ref(obj);
1356 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1357 int size, int align, uint32_t domain,
1358 uint32_t tile_mode, uint32_t tile_flags,
1359 struct nouveau_bo **);
1360 extern int nouveau_gem_object_new(struct drm_gem_object *);
1361 extern void nouveau_gem_object_del(struct drm_gem_object *);
1362 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1364 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1366 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1368 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1370 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1373 /* nouveau_display.c */
1374 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1375 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1376 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1377 struct drm_pending_vblank_event *event);
1378 int nouveau_finish_page_flip(struct nouveau_channel *,
1379 struct nouveau_page_flip_state *);
1382 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1383 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1386 int nv50_gpio_init(struct drm_device *dev);
1387 void nv50_gpio_fini(struct drm_device *dev);
1388 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1389 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1390 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1391 void (*)(void *, int), void *);
1392 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1393 void (*)(void *, int), void *);
1394 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1397 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1398 int *N1, int *M1, int *N2, int *M2, int *P);
1399 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1400 int clk, int *N, int *fN, int *M, int *P);
1402 #ifndef ioread32_native
1404 #define ioread16_native ioread16be
1405 #define iowrite16_native iowrite16be
1406 #define ioread32_native ioread32be
1407 #define iowrite32_native iowrite32be
1408 #else /* def __BIG_ENDIAN */
1409 #define ioread16_native ioread16
1410 #define iowrite16_native iowrite16
1411 #define ioread32_native ioread32
1412 #define iowrite32_native iowrite32
1413 #endif /* def __BIG_ENDIAN else */
1414 #endif /* !ioread32_native */
1416 /* channel control reg access */
1417 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1419 return ioread32_native(chan->user + reg);
1422 static inline void nvchan_wr32(struct nouveau_channel *chan,
1423 unsigned reg, u32 val)
1425 iowrite32_native(val, chan->user + reg);
1428 /* register access */
1429 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1431 struct drm_nouveau_private *dev_priv = dev->dev_private;
1432 return ioread32_native(dev_priv->mmio + reg);
1435 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1437 struct drm_nouveau_private *dev_priv = dev->dev_private;
1438 iowrite32_native(val, dev_priv->mmio + reg);
1441 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1443 u32 tmp = nv_rd32(dev, reg);
1444 nv_wr32(dev, reg, (tmp & ~mask) | val);
1448 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1450 struct drm_nouveau_private *dev_priv = dev->dev_private;
1451 return ioread8(dev_priv->mmio + reg);
1454 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1456 struct drm_nouveau_private *dev_priv = dev->dev_private;
1457 iowrite8(val, dev_priv->mmio + reg);
1460 #define nv_wait(dev, reg, mask, val) \
1461 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1462 #define nv_wait_ne(dev, reg, mask, val) \
1463 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1466 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1468 struct drm_nouveau_private *dev_priv = dev->dev_private;
1469 return ioread32_native(dev_priv->ramin + offset);
1472 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1474 struct drm_nouveau_private *dev_priv = dev->dev_private;
1475 iowrite32_native(val, dev_priv->ramin + offset);
1479 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1480 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1484 * Argument d is (struct drm_device *).
1486 #define NV_PRINTK(level, d, fmt, arg...) \
1487 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1488 pci_name(d->pdev), ##arg)
1489 #ifndef NV_DEBUG_NOTRACE
1490 #define NV_DEBUG(d, fmt, arg...) do { \
1491 if (drm_debug & DRM_UT_DRIVER) { \
1492 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1496 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1497 if (drm_debug & DRM_UT_KMS) { \
1498 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1503 #define NV_DEBUG(d, fmt, arg...) do { \
1504 if (drm_debug & DRM_UT_DRIVER) \
1505 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1507 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1508 if (drm_debug & DRM_UT_KMS) \
1509 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1512 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1513 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1514 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1515 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1516 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1518 /* nouveau_reg_debug bitmask */
1520 NOUVEAU_REG_DEBUG_MC = 0x1,
1521 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1522 NOUVEAU_REG_DEBUG_FB = 0x4,
1523 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1524 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1525 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1526 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1527 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1528 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1529 NOUVEAU_REG_DEBUG_EVO = 0x200,
1532 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1533 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1534 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1538 nv_two_heads(struct drm_device *dev)
1540 struct drm_nouveau_private *dev_priv = dev->dev_private;
1541 const int impl = dev->pci_device & 0x0ff0;
1543 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1544 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1551 nv_gf4_disp_arch(struct drm_device *dev)
1553 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1557 nv_two_reg_pll(struct drm_device *dev)
1559 struct drm_nouveau_private *dev_priv = dev->dev_private;
1560 const int impl = dev->pci_device & 0x0ff0;
1562 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1568 nv_match_device(struct drm_device *dev, unsigned device,
1569 unsigned sub_vendor, unsigned sub_device)
1571 return dev->pdev->device == device &&
1572 dev->pdev->subsystem_vendor == sub_vendor &&
1573 dev->pdev->subsystem_device == sub_device;
1576 static inline void *
1577 nv_engine(struct drm_device *dev, int engine)
1579 struct drm_nouveau_private *dev_priv = dev->dev_private;
1580 return (void *)dev_priv->eng[engine];
1583 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1584 * helpful to determine a number of other hardware features
1587 nv44_graph_class(struct drm_device *dev)
1589 struct drm_nouveau_private *dev_priv = dev->dev_private;
1591 if ((dev_priv->chipset & 0xf0) == 0x60)
1594 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1597 /* memory type/access flags, do not match hardware values */
1598 #define NV_MEM_ACCESS_RO 1
1599 #define NV_MEM_ACCESS_WO 2
1600 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1601 #define NV_MEM_ACCESS_SYS 4
1602 #define NV_MEM_ACCESS_VM 8
1604 #define NV_MEM_TARGET_VRAM 0
1605 #define NV_MEM_TARGET_PCI 1
1606 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1607 #define NV_MEM_TARGET_VM 3
1608 #define NV_MEM_TARGET_GART 4
1610 #define NV_MEM_TYPE_VM 0x7f
1611 #define NV_MEM_COMP_VM 0x03
1613 /* NV_SW object class */
1614 #define NV_SW 0x0000506e
1615 #define NV_SW_DMA_SEMAPHORE 0x00000060
1616 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1617 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1618 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1619 #define NV_SW_YIELD 0x00000080
1620 #define NV_SW_DMA_VBLSEM 0x0000018c
1621 #define NV_SW_VBLSEM_OFFSET 0x00000400
1622 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1623 #define NV_SW_VBLSEM_RELEASE 0x00000408
1624 #define NV_SW_PAGE_FLIP 0x00000500
1626 #endif /* __NOUVEAU_DRV_H__ */