2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
50 struct list_head channels;
51 struct nouveau_vm *vm;
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
57 return file_priv ? file_priv->driver_priv : NULL;
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
69 #include "nouveau_vm.h"
71 #define MAX_NUM_DCB_ENTRIES 16
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
77 struct drm_device *dev;
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
83 struct drm_mm_node *tag;
84 struct list_head regions;
91 struct nouveau_tile_reg {
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
114 bool validate_mapped;
116 struct nouveau_channel *channel;
118 struct list_head vma_list;
123 struct nouveau_tile_reg *tile;
125 struct drm_gem_object *gem;
129 #define nouveau_bo_tile_layout(nvbo) \
130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
132 static inline struct nouveau_bo *
133 nouveau_bo(struct ttm_buffer_object *bo)
135 return container_of(bo, struct nouveau_bo, bo);
138 static inline struct nouveau_bo *
139 nouveau_gem_object(struct drm_gem_object *gem)
141 return gem ? gem->driver_private : NULL;
144 /* TODO: submit equivalent to TTM generic API upstream? */
145 static inline void __iomem *
146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
150 &nvbo->kmap, &is_iomem);
151 WARN_ON_ONCE(ioptr && !is_iomem);
156 NV_NFORCE = 0x10000000,
157 NV_NFORCE2 = 0x20000000
160 #define NVOBJ_ENGINE_SW 0
161 #define NVOBJ_ENGINE_GR 1
162 #define NVOBJ_ENGINE_CRYPT 2
163 #define NVOBJ_ENGINE_COPY0 3
164 #define NVOBJ_ENGINE_COPY1 4
165 #define NVOBJ_ENGINE_MPEG 5
166 #define NVOBJ_ENGINE_DISPLAY 15
167 #define NVOBJ_ENGINE_NR 16
169 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
170 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
171 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
172 #define NVOBJ_FLAG_VM (1 << 3)
173 #define NVOBJ_FLAG_VM_USER (1 << 4)
175 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
177 struct nouveau_gpuobj {
178 struct drm_device *dev;
179 struct kref refcount;
180 struct list_head list;
188 u32 pinst; /* PRAMIN BAR offset */
189 u32 cinst; /* Channel offset */
190 u64 vinst; /* VRAM address */
191 u64 linst; /* VM address */
196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
200 struct nouveau_page_flip_state {
201 struct list_head head;
202 struct drm_pending_vblank_event *event;
203 int crtc, bpp, pitch, x, y;
207 enum nouveau_channel_mutex_class {
208 NOUVEAU_UCHANNEL_MUTEX,
209 NOUVEAU_KCHANNEL_MUTEX
212 struct nouveau_channel {
213 struct drm_device *dev;
214 struct list_head list;
217 /* references to the channel data structure */
219 /* users of the hardware channel resources, the hardware
220 * context will be kicked off when it reaches zero. */
224 /* owner of this fifo */
225 struct drm_file *file_priv;
226 /* mapping of the fifo itself */
227 struct drm_local_map *map;
229 /* mapping of the regs controlling the fifo */
236 /* lock protects the pending list only */
238 struct list_head pending;
240 uint32_t sequence_ack;
241 atomic_t last_sequence_irq;
242 struct nouveau_vma vma;
245 /* DMA push buffer */
246 struct nouveau_gpuobj *pushbuf;
247 struct nouveau_bo *pushbuf_bo;
248 struct nouveau_vma pushbuf_vma;
249 uint32_t pushbuf_base;
251 /* Notifier memory */
252 struct nouveau_bo *notifier_bo;
253 struct nouveau_vma notifier_vma;
254 struct drm_mm notifier_heap;
257 struct nouveau_gpuobj *ramfc;
258 struct nouveau_gpuobj *cache;
261 /* Execution engine contexts */
262 void *engctx[NVOBJ_ENGINE_NR];
265 struct nouveau_vm *vm;
266 struct nouveau_gpuobj *vm_pd;
269 struct nouveau_gpuobj *ramin; /* Private instmem */
270 struct drm_mm ramin_heap; /* Private PRAMIN heap */
271 struct nouveau_ramht *ramht; /* Hash table */
273 /* GPU object info for stuff used in-kernel (mm_enabled) */
275 uint32_t vram_handle;
276 uint32_t gart_handle;
279 /* Push buffer state (only for drm's channel on !mm_enabled) */
285 /* access via pushbuf_bo */
293 uint32_t sw_subchannel[8];
295 struct nouveau_vma dispc_vma[2];
297 struct nouveau_gpuobj *vblsem;
298 uint32_t vblsem_head;
299 uint32_t vblsem_offset;
300 uint32_t vblsem_rval;
301 struct list_head vbl_wait;
302 struct list_head flip;
308 struct drm_info_list info;
312 struct nouveau_exec_engine {
313 void (*destroy)(struct drm_device *, int engine);
314 int (*init)(struct drm_device *, int engine);
315 int (*fini)(struct drm_device *, int engine, bool suspend);
316 int (*context_new)(struct nouveau_channel *, int engine);
317 void (*context_del)(struct nouveau_channel *, int engine);
318 int (*object_new)(struct nouveau_channel *, int engine,
319 u32 handle, u16 class);
320 void (*set_tile_region)(struct drm_device *dev, int i);
321 void (*tlb_flush)(struct drm_device *, int engine);
324 struct nouveau_instmem_engine {
327 int (*init)(struct drm_device *dev);
328 void (*takedown)(struct drm_device *dev);
329 int (*suspend)(struct drm_device *dev);
330 void (*resume)(struct drm_device *dev);
332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
333 u32 size, u32 align);
334 void (*put)(struct nouveau_gpuobj *);
335 int (*map)(struct nouveau_gpuobj *);
336 void (*unmap)(struct nouveau_gpuobj *);
338 void (*flush)(struct drm_device *);
341 struct nouveau_mc_engine {
342 int (*init)(struct drm_device *dev);
343 void (*takedown)(struct drm_device *dev);
346 struct nouveau_timer_engine {
347 int (*init)(struct drm_device *dev);
348 void (*takedown)(struct drm_device *dev);
349 uint64_t (*read)(struct drm_device *dev);
352 struct nouveau_fb_engine {
354 struct drm_mm tag_heap;
357 int (*init)(struct drm_device *dev);
358 void (*takedown)(struct drm_device *dev);
360 void (*init_tile_region)(struct drm_device *dev, int i,
361 uint32_t addr, uint32_t size,
362 uint32_t pitch, uint32_t flags);
363 void (*set_tile_region)(struct drm_device *dev, int i);
364 void (*free_tile_region)(struct drm_device *dev, int i);
367 struct nouveau_fifo_engine {
371 struct nouveau_gpuobj *playlist[2];
374 int (*init)(struct drm_device *);
375 void (*takedown)(struct drm_device *);
377 void (*disable)(struct drm_device *);
378 void (*enable)(struct drm_device *);
379 bool (*reassign)(struct drm_device *, bool enable);
380 bool (*cache_pull)(struct drm_device *dev, bool enable);
382 int (*channel_id)(struct drm_device *);
384 int (*create_context)(struct nouveau_channel *);
385 void (*destroy_context)(struct nouveau_channel *);
386 int (*load_context)(struct nouveau_channel *);
387 int (*unload_context)(struct drm_device *);
388 void (*tlb_flush)(struct drm_device *dev);
391 struct nouveau_display_engine {
393 int (*early_init)(struct drm_device *);
394 void (*late_takedown)(struct drm_device *);
395 int (*create)(struct drm_device *);
396 int (*init)(struct drm_device *);
397 void (*destroy)(struct drm_device *);
400 struct nouveau_gpio_engine {
403 int (*init)(struct drm_device *);
404 void (*takedown)(struct drm_device *);
406 int (*get)(struct drm_device *, enum dcb_gpio_tag);
407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
410 void (*)(void *, int), void *);
411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
412 void (*)(void *, int), void *);
413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
416 struct nouveau_pm_voltage_level {
417 u32 voltage; /* microvolts */
421 struct nouveau_pm_voltage {
426 struct nouveau_pm_voltage_level *level;
430 struct nouveau_pm_memtiming {
443 #define NOUVEAU_PM_MAX_LEVEL 8
444 struct nouveau_pm_level {
445 struct device_attribute dev_attr;
456 u32 unk05; /* nv50:nva3, roughly.. */
457 u32 unka0; /* nva3:nvc0 */
458 u32 hub01; /* nvc0- */
459 u32 hub06; /* nvc0- */
460 u32 hub07; /* nvc0- */
462 u32 volt_min; /* microvolts */
467 struct nouveau_pm_memtiming *timing;
470 struct nouveau_pm_temp_sensor_constants {
478 struct nouveau_pm_threshold_temp {
484 struct nouveau_pm_memtimings {
486 struct nouveau_pm_memtiming *timing;
490 struct nouveau_pm_engine {
491 struct nouveau_pm_voltage voltage;
492 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
494 struct nouveau_pm_memtimings memtimings;
495 struct nouveau_pm_temp_sensor_constants sensor_constants;
496 struct nouveau_pm_threshold_temp threshold_temp;
498 struct nouveau_pm_level boot;
499 struct nouveau_pm_level *cur;
501 struct device *hwmon;
502 struct notifier_block acpi_nb;
504 int (*clock_get)(struct drm_device *, u32 id);
505 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
507 void (*clock_set)(struct drm_device *, void *);
509 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
510 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
511 void (*clocks_set)(struct drm_device *, void *);
513 int (*voltage_get)(struct drm_device *);
514 int (*voltage_set)(struct drm_device *, int voltage);
515 int (*fanspeed_get)(struct drm_device *);
516 int (*fanspeed_set)(struct drm_device *, int fanspeed);
517 int (*temp_get)(struct drm_device *);
520 struct nouveau_vram_engine {
521 struct nouveau_mm mm;
523 int (*init)(struct drm_device *);
524 void (*takedown)(struct drm_device *dev);
525 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
526 u32 type, struct nouveau_mem **);
527 void (*put)(struct drm_device *, struct nouveau_mem **);
529 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
532 struct nouveau_engine {
533 struct nouveau_instmem_engine instmem;
534 struct nouveau_mc_engine mc;
535 struct nouveau_timer_engine timer;
536 struct nouveau_fb_engine fb;
537 struct nouveau_fifo_engine fifo;
538 struct nouveau_display_engine display;
539 struct nouveau_gpio_engine gpio;
540 struct nouveau_pm_engine pm;
541 struct nouveau_vram_engine vram;
544 struct nouveau_pll_vals {
548 uint8_t N1, M1, N2, M2;
550 uint8_t M1, N1, M2, N2;
555 } __attribute__((packed));
562 enum nv04_fp_display_regs {
572 struct nv04_crtc_reg {
573 unsigned char MiscOutReg;
576 uint8_t Sequencer[5];
578 uint8_t Attribute[21];
579 unsigned char DAC[768];
589 uint32_t crtc_eng_ctrl;
592 uint32_t nv10_cursync;
593 struct nouveau_pll_vals pllvals;
594 uint32_t ramdac_gen_ctrl;
600 uint32_t tv_vsync_delay;
603 uint32_t tv_hsync_delay;
604 uint32_t tv_hsync_delay2;
605 uint32_t fp_horiz_regs[7];
606 uint32_t fp_vert_regs[7];
609 uint32_t dither_regs[6];
613 uint32_t fp_margin_color;
618 uint32_t ctv_regs[38];
621 struct nv04_output_reg {
626 struct nv04_mode_state {
627 struct nv04_crtc_reg crtc_reg[2];
632 enum nouveau_card_type {
643 struct drm_nouveau_private {
644 struct drm_device *dev;
647 /* the card type, takes NV_* as values */
648 enum nouveau_card_type card_type;
649 /* exact chipset, derived from NV_PMC_BOOT_0 */
656 spinlock_t ramin_lock;
660 bool ramin_available;
661 struct drm_mm ramin_heap;
662 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
663 struct list_head gpuobj_list;
664 struct list_head classes;
666 struct nouveau_bo *vga_ram;
668 /* interrupt handling */
669 void (*irq_handler[32])(struct drm_device *);
672 struct list_head vbl_waiting;
675 struct drm_global_reference mem_global_ref;
676 struct ttm_bo_global_ref bo_global_ref;
677 struct ttm_bo_device bdev;
678 atomic_t validate_sequence;
684 struct nouveau_bo *bo;
689 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
692 struct nouveau_engine engine;
693 struct nouveau_channel *channel;
695 /* For PFIFO and PGRAPH. */
696 spinlock_t context_switch_lock;
698 /* VM/PRAMIN flush, legacy PRAMIN aperture */
701 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
702 struct nouveau_ramht *ramht;
703 struct nouveau_gpuobj *ramfc;
704 struct nouveau_gpuobj *ramro;
706 uint32_t ramin_rsvd_vram;
710 NOUVEAU_GART_NONE = 0,
711 NOUVEAU_GART_AGP, /* AGP */
712 NOUVEAU_GART_PDMA, /* paged dma object */
713 NOUVEAU_GART_HW /* on-chip gart/vm */
719 struct ttm_backend_func *func;
726 struct nouveau_gpuobj *sg_ctxdma;
729 /* nv10-nv40 tiling regions */
731 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
735 /* VRAM/fb configuration */
737 uint64_t vram_sys_base;
739 uint64_t fb_available_size;
740 uint64_t fb_mappable_pages;
741 uint64_t fb_aper_free;
744 /* BAR control (NV50-) */
745 struct nouveau_vm *bar1_vm;
746 struct nouveau_vm *bar3_vm;
748 /* G8x/G9x virtual address space */
749 struct nouveau_vm *chan_vm;
753 struct nv04_mode_state mode_reg;
754 struct nv04_mode_state saved_reg;
755 uint32_t saved_vga_font[4][16384];
757 uint32_t dac_users[4];
759 struct backlight_device *backlight;
762 struct dentry *channel_root;
765 struct nouveau_fbdev *nfbdev;
766 struct apertures_struct *apertures;
769 static inline struct drm_nouveau_private *
770 nouveau_private(struct drm_device *dev)
772 return dev->dev_private;
775 static inline struct drm_nouveau_private *
776 nouveau_bdev(struct ttm_bo_device *bd)
778 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
782 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
784 struct nouveau_bo *prev;
790 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
792 struct ttm_buffer_object *bo = &prev->bo;
801 extern int nouveau_modeset;
802 extern int nouveau_agpmode;
803 extern int nouveau_duallink;
804 extern int nouveau_uscript_lvds;
805 extern int nouveau_uscript_tmds;
806 extern int nouveau_vram_pushbuf;
807 extern int nouveau_vram_notify;
808 extern int nouveau_fbpercrtc;
809 extern int nouveau_tv_disable;
810 extern char *nouveau_tv_norm;
811 extern int nouveau_reg_debug;
812 extern char *nouveau_vbios;
813 extern int nouveau_ignorelid;
814 extern int nouveau_nofbaccel;
815 extern int nouveau_noaccel;
816 extern int nouveau_force_post;
817 extern int nouveau_override_conntype;
818 extern char *nouveau_perflvl;
819 extern int nouveau_perflvl_wr;
820 extern int nouveau_msi;
821 extern int nouveau_ctxfw;
823 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
824 extern int nouveau_pci_resume(struct pci_dev *pdev);
826 /* nouveau_state.c */
827 extern int nouveau_open(struct drm_device *, struct drm_file *);
828 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
829 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
830 extern int nouveau_load(struct drm_device *, unsigned long flags);
831 extern int nouveau_firstopen(struct drm_device *);
832 extern void nouveau_lastclose(struct drm_device *);
833 extern int nouveau_unload(struct drm_device *);
834 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
836 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
838 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
839 uint32_t reg, uint32_t mask, uint32_t val);
840 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
841 uint32_t reg, uint32_t mask, uint32_t val);
842 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
843 bool (*cond)(void *), void *);
844 extern bool nouveau_wait_for_idle(struct drm_device *);
845 extern int nouveau_card_init(struct drm_device *);
848 extern int nouveau_mem_vram_init(struct drm_device *);
849 extern void nouveau_mem_vram_fini(struct drm_device *);
850 extern int nouveau_mem_gart_init(struct drm_device *);
851 extern void nouveau_mem_gart_fini(struct drm_device *);
852 extern int nouveau_mem_init_agp(struct drm_device *);
853 extern int nouveau_mem_reset_agp(struct drm_device *);
854 extern void nouveau_mem_close(struct drm_device *);
855 extern int nouveau_mem_detect(struct drm_device *);
856 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
857 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
858 struct drm_device *dev, uint32_t addr, uint32_t size,
859 uint32_t pitch, uint32_t flags);
860 extern void nv10_mem_put_tile_region(struct drm_device *dev,
861 struct nouveau_tile_reg *tile,
862 struct nouveau_fence *fence);
863 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
864 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
866 /* nouveau_notifier.c */
867 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
868 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
869 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
870 int cout, uint32_t start, uint32_t end,
872 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
873 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
875 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
878 /* nouveau_channel.c */
879 extern struct drm_ioctl_desc nouveau_ioctls[];
880 extern int nouveau_max_ioctl;
881 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
882 extern int nouveau_channel_alloc(struct drm_device *dev,
883 struct nouveau_channel **chan,
884 struct drm_file *file_priv,
885 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
886 extern struct nouveau_channel *
887 nouveau_channel_get_unlocked(struct nouveau_channel *);
888 extern struct nouveau_channel *
889 nouveau_channel_get(struct drm_file *, int id);
890 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
891 extern void nouveau_channel_put(struct nouveau_channel **);
892 extern void nouveau_channel_ref(struct nouveau_channel *chan,
893 struct nouveau_channel **pchan);
894 extern void nouveau_channel_idle(struct nouveau_channel *chan);
896 /* nouveau_object.c */
897 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
898 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
899 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
902 #define NVOBJ_ENGINE_DEL(d, e) do { \
903 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
904 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
907 #define NVOBJ_CLASS(d, c, e) do { \
908 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
913 #define NVOBJ_MTHD(d, c, m, e) do { \
914 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
919 extern int nouveau_gpuobj_early_init(struct drm_device *);
920 extern int nouveau_gpuobj_init(struct drm_device *);
921 extern void nouveau_gpuobj_takedown(struct drm_device *);
922 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
923 extern void nouveau_gpuobj_resume(struct drm_device *dev);
924 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
925 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
926 int (*exec)(struct nouveau_channel *,
927 u32 class, u32 mthd, u32 data));
928 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
929 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
930 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
931 uint32_t vram_h, uint32_t tt_h);
932 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
933 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
934 uint32_t size, int align, uint32_t flags,
935 struct nouveau_gpuobj **);
936 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
937 struct nouveau_gpuobj **);
938 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
940 struct nouveau_gpuobj **);
941 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
942 uint64_t offset, uint64_t size, int access,
943 int target, struct nouveau_gpuobj **);
944 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
945 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
946 u64 size, int target, int access, u32 type,
947 u32 comp, struct nouveau_gpuobj **pobj);
948 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
949 int class, u64 base, u64 size, int target,
950 int access, u32 type, u32 comp);
951 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
953 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
957 extern int nouveau_irq_init(struct drm_device *);
958 extern void nouveau_irq_fini(struct drm_device *);
959 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
960 extern void nouveau_irq_register(struct drm_device *, int status_bit,
961 void (*)(struct drm_device *));
962 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
963 extern void nouveau_irq_preinstall(struct drm_device *);
964 extern int nouveau_irq_postinstall(struct drm_device *);
965 extern void nouveau_irq_uninstall(struct drm_device *);
967 /* nouveau_sgdma.c */
968 extern int nouveau_sgdma_init(struct drm_device *);
969 extern void nouveau_sgdma_takedown(struct drm_device *);
970 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
972 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
974 /* nouveau_debugfs.c */
975 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
976 extern int nouveau_debugfs_init(struct drm_minor *);
977 extern void nouveau_debugfs_takedown(struct drm_minor *);
978 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
979 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
982 nouveau_debugfs_init(struct drm_minor *minor)
987 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
992 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
998 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1004 extern void nouveau_dma_pre_init(struct nouveau_channel *);
1005 extern int nouveau_dma_init(struct nouveau_channel *);
1006 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1008 /* nouveau_acpi.c */
1009 #define ROM_BIOS_PAGE 4096
1010 #if defined(CONFIG_ACPI)
1011 void nouveau_register_dsm_handler(void);
1012 void nouveau_unregister_dsm_handler(void);
1013 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1014 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1015 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1017 static inline void nouveau_register_dsm_handler(void) {}
1018 static inline void nouveau_unregister_dsm_handler(void) {}
1019 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1020 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1021 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1024 /* nouveau_backlight.c */
1025 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1026 extern int nouveau_backlight_init(struct drm_connector *);
1027 extern void nouveau_backlight_exit(struct drm_connector *);
1029 static inline int nouveau_backlight_init(struct drm_connector *dev)
1034 static inline void nouveau_backlight_exit(struct drm_connector *dev) { }
1037 /* nouveau_bios.c */
1038 extern int nouveau_bios_init(struct drm_device *);
1039 extern void nouveau_bios_takedown(struct drm_device *dev);
1040 extern int nouveau_run_vbios_init(struct drm_device *);
1041 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1042 struct dcb_entry *, int crtc);
1043 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1045 extern struct dcb_connector_table_entry *
1046 nouveau_bios_connector_entry(struct drm_device *, int index);
1047 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1048 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1050 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1051 struct dcb_entry *, int crtc);
1052 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1054 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1055 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1056 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1057 bool *dl, bool *if_is_24bit);
1058 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1059 int head, int pxclk);
1060 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1061 enum LVDS_script, int pxclk);
1064 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1065 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1066 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1069 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1070 uint8_t *data, int data_nr);
1071 bool nouveau_dp_detect(struct drm_encoder *);
1072 bool nouveau_dp_link_train(struct drm_encoder *);
1075 extern int nv04_fb_init(struct drm_device *);
1076 extern void nv04_fb_takedown(struct drm_device *);
1079 extern int nv10_fb_init(struct drm_device *);
1080 extern void nv10_fb_takedown(struct drm_device *);
1081 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1082 uint32_t addr, uint32_t size,
1083 uint32_t pitch, uint32_t flags);
1084 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1085 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1088 extern int nv30_fb_init(struct drm_device *);
1089 extern void nv30_fb_takedown(struct drm_device *);
1090 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1091 uint32_t addr, uint32_t size,
1092 uint32_t pitch, uint32_t flags);
1093 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1096 extern int nv40_fb_init(struct drm_device *);
1097 extern void nv40_fb_takedown(struct drm_device *);
1098 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1101 extern int nv50_fb_init(struct drm_device *);
1102 extern void nv50_fb_takedown(struct drm_device *);
1103 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1106 extern int nvc0_fb_init(struct drm_device *);
1107 extern void nvc0_fb_takedown(struct drm_device *);
1110 extern int nv04_fifo_init(struct drm_device *);
1111 extern void nv04_fifo_fini(struct drm_device *);
1112 extern void nv04_fifo_disable(struct drm_device *);
1113 extern void nv04_fifo_enable(struct drm_device *);
1114 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1115 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1116 extern int nv04_fifo_channel_id(struct drm_device *);
1117 extern int nv04_fifo_create_context(struct nouveau_channel *);
1118 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1119 extern int nv04_fifo_load_context(struct nouveau_channel *);
1120 extern int nv04_fifo_unload_context(struct drm_device *);
1121 extern void nv04_fifo_isr(struct drm_device *);
1124 extern int nv10_fifo_init(struct drm_device *);
1125 extern int nv10_fifo_channel_id(struct drm_device *);
1126 extern int nv10_fifo_create_context(struct nouveau_channel *);
1127 extern int nv10_fifo_load_context(struct nouveau_channel *);
1128 extern int nv10_fifo_unload_context(struct drm_device *);
1131 extern int nv40_fifo_init(struct drm_device *);
1132 extern int nv40_fifo_create_context(struct nouveau_channel *);
1133 extern int nv40_fifo_load_context(struct nouveau_channel *);
1134 extern int nv40_fifo_unload_context(struct drm_device *);
1137 extern int nv50_fifo_init(struct drm_device *);
1138 extern void nv50_fifo_takedown(struct drm_device *);
1139 extern int nv50_fifo_channel_id(struct drm_device *);
1140 extern int nv50_fifo_create_context(struct nouveau_channel *);
1141 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1142 extern int nv50_fifo_load_context(struct nouveau_channel *);
1143 extern int nv50_fifo_unload_context(struct drm_device *);
1144 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1147 extern int nvc0_fifo_init(struct drm_device *);
1148 extern void nvc0_fifo_takedown(struct drm_device *);
1149 extern void nvc0_fifo_disable(struct drm_device *);
1150 extern void nvc0_fifo_enable(struct drm_device *);
1151 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1152 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1153 extern int nvc0_fifo_channel_id(struct drm_device *);
1154 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1155 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1156 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1157 extern int nvc0_fifo_unload_context(struct drm_device *);
1160 extern int nv04_graph_create(struct drm_device *);
1161 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1162 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1163 u32 class, u32 mthd, u32 data);
1164 extern struct nouveau_bitfield nv04_graph_nsource[];
1167 extern int nv10_graph_create(struct drm_device *);
1168 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1169 extern struct nouveau_bitfield nv10_graph_intr[];
1170 extern struct nouveau_bitfield nv10_graph_nstatus[];
1173 extern int nv20_graph_create(struct drm_device *);
1176 extern int nv40_graph_create(struct drm_device *);
1177 extern void nv40_grctx_init(struct nouveau_grctx *);
1180 extern int nv50_graph_create(struct drm_device *);
1181 extern int nv50_grctx_init(struct nouveau_grctx *);
1182 extern struct nouveau_enum nv50_data_error_names[];
1183 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1186 extern int nvc0_graph_create(struct drm_device *);
1187 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1190 extern int nv84_crypt_create(struct drm_device *);
1193 extern int nva3_copy_create(struct drm_device *dev);
1196 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1199 extern int nv31_mpeg_create(struct drm_device *dev);
1202 extern int nv50_mpeg_create(struct drm_device *dev);
1204 /* nv04_instmem.c */
1205 extern int nv04_instmem_init(struct drm_device *);
1206 extern void nv04_instmem_takedown(struct drm_device *);
1207 extern int nv04_instmem_suspend(struct drm_device *);
1208 extern void nv04_instmem_resume(struct drm_device *);
1209 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1210 u32 size, u32 align);
1211 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1212 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1213 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1214 extern void nv04_instmem_flush(struct drm_device *);
1216 /* nv50_instmem.c */
1217 extern int nv50_instmem_init(struct drm_device *);
1218 extern void nv50_instmem_takedown(struct drm_device *);
1219 extern int nv50_instmem_suspend(struct drm_device *);
1220 extern void nv50_instmem_resume(struct drm_device *);
1221 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1222 u32 size, u32 align);
1223 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1224 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1225 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1226 extern void nv50_instmem_flush(struct drm_device *);
1227 extern void nv84_instmem_flush(struct drm_device *);
1229 /* nvc0_instmem.c */
1230 extern int nvc0_instmem_init(struct drm_device *);
1231 extern void nvc0_instmem_takedown(struct drm_device *);
1232 extern int nvc0_instmem_suspend(struct drm_device *);
1233 extern void nvc0_instmem_resume(struct drm_device *);
1236 extern int nv04_mc_init(struct drm_device *);
1237 extern void nv04_mc_takedown(struct drm_device *);
1240 extern int nv40_mc_init(struct drm_device *);
1241 extern void nv40_mc_takedown(struct drm_device *);
1244 extern int nv50_mc_init(struct drm_device *);
1245 extern void nv50_mc_takedown(struct drm_device *);
1248 extern int nv04_timer_init(struct drm_device *);
1249 extern uint64_t nv04_timer_read(struct drm_device *);
1250 extern void nv04_timer_takedown(struct drm_device *);
1252 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1256 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1257 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1258 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1259 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1260 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1263 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1264 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1265 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1267 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1268 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1271 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1272 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1275 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1277 /* nv04_display.c */
1278 extern int nv04_display_early_init(struct drm_device *);
1279 extern void nv04_display_late_takedown(struct drm_device *);
1280 extern int nv04_display_create(struct drm_device *);
1281 extern int nv04_display_init(struct drm_device *);
1282 extern void nv04_display_destroy(struct drm_device *);
1285 extern int nv04_crtc_create(struct drm_device *, int index);
1288 extern struct ttm_bo_driver nouveau_bo_driver;
1289 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1290 uint32_t flags, uint32_t tile_mode,
1291 uint32_t tile_flags, struct nouveau_bo **);
1292 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1293 extern int nouveau_bo_unpin(struct nouveau_bo *);
1294 extern int nouveau_bo_map(struct nouveau_bo *);
1295 extern void nouveau_bo_unmap(struct nouveau_bo *);
1296 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1298 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1299 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1300 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1301 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1302 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1303 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1304 bool no_wait_reserve, bool no_wait_gpu);
1306 extern struct nouveau_vma *
1307 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1308 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1309 struct nouveau_vma *);
1310 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1312 /* nouveau_fence.c */
1313 struct nouveau_fence;
1314 extern int nouveau_fence_init(struct drm_device *);
1315 extern void nouveau_fence_fini(struct drm_device *);
1316 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1317 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1318 extern void nouveau_fence_update(struct nouveau_channel *);
1319 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1321 extern int nouveau_fence_emit(struct nouveau_fence *);
1322 extern void nouveau_fence_work(struct nouveau_fence *fence,
1323 void (*work)(void *priv, bool signalled),
1325 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1327 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1328 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1329 extern int __nouveau_fence_flush(void *obj, void *arg);
1330 extern void __nouveau_fence_unref(void **obj);
1331 extern void *__nouveau_fence_ref(void *obj);
1333 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1335 return __nouveau_fence_signalled(obj, NULL);
1338 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1340 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1342 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1343 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1345 return __nouveau_fence_flush(obj, NULL);
1347 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1349 __nouveau_fence_unref((void **)obj);
1351 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1353 return __nouveau_fence_ref(obj);
1357 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1358 uint32_t domain, uint32_t tile_mode,
1359 uint32_t tile_flags, struct nouveau_bo **);
1360 extern int nouveau_gem_object_new(struct drm_gem_object *);
1361 extern void nouveau_gem_object_del(struct drm_gem_object *);
1362 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1363 extern void nouveau_gem_object_close(struct drm_gem_object *,
1365 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1367 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1369 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1371 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1373 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1376 /* nouveau_display.c */
1377 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1378 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1379 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1380 struct drm_pending_vblank_event *event);
1381 int nouveau_finish_page_flip(struct nouveau_channel *,
1382 struct nouveau_page_flip_state *);
1385 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1386 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1389 int nv50_gpio_init(struct drm_device *dev);
1390 void nv50_gpio_fini(struct drm_device *dev);
1391 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1392 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1393 int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1394 int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1395 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1396 void (*)(void *, int), void *);
1397 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1398 void (*)(void *, int), void *);
1399 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1402 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1403 int *N1, int *M1, int *N2, int *M2, int *P);
1404 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1405 int clk, int *N, int *fN, int *M, int *P);
1407 #ifndef ioread32_native
1409 #define ioread16_native ioread16be
1410 #define iowrite16_native iowrite16be
1411 #define ioread32_native ioread32be
1412 #define iowrite32_native iowrite32be
1413 #else /* def __BIG_ENDIAN */
1414 #define ioread16_native ioread16
1415 #define iowrite16_native iowrite16
1416 #define ioread32_native ioread32
1417 #define iowrite32_native iowrite32
1418 #endif /* def __BIG_ENDIAN else */
1419 #endif /* !ioread32_native */
1421 /* channel control reg access */
1422 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1424 return ioread32_native(chan->user + reg);
1427 static inline void nvchan_wr32(struct nouveau_channel *chan,
1428 unsigned reg, u32 val)
1430 iowrite32_native(val, chan->user + reg);
1433 /* register access */
1434 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1436 struct drm_nouveau_private *dev_priv = dev->dev_private;
1437 return ioread32_native(dev_priv->mmio + reg);
1440 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1442 struct drm_nouveau_private *dev_priv = dev->dev_private;
1443 iowrite32_native(val, dev_priv->mmio + reg);
1446 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1448 u32 tmp = nv_rd32(dev, reg);
1449 nv_wr32(dev, reg, (tmp & ~mask) | val);
1453 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1455 struct drm_nouveau_private *dev_priv = dev->dev_private;
1456 return ioread8(dev_priv->mmio + reg);
1459 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1461 struct drm_nouveau_private *dev_priv = dev->dev_private;
1462 iowrite8(val, dev_priv->mmio + reg);
1465 #define nv_wait(dev, reg, mask, val) \
1466 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1467 #define nv_wait_ne(dev, reg, mask, val) \
1468 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1469 #define nv_wait_cb(dev, func, data) \
1470 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1473 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1475 struct drm_nouveau_private *dev_priv = dev->dev_private;
1476 return ioread32_native(dev_priv->ramin + offset);
1479 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1481 struct drm_nouveau_private *dev_priv = dev->dev_private;
1482 iowrite32_native(val, dev_priv->ramin + offset);
1486 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1487 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1491 * Argument d is (struct drm_device *).
1493 #define NV_PRINTK(level, d, fmt, arg...) \
1494 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1495 pci_name(d->pdev), ##arg)
1496 #ifndef NV_DEBUG_NOTRACE
1497 #define NV_DEBUG(d, fmt, arg...) do { \
1498 if (drm_debug & DRM_UT_DRIVER) { \
1499 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1503 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1504 if (drm_debug & DRM_UT_KMS) { \
1505 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1510 #define NV_DEBUG(d, fmt, arg...) do { \
1511 if (drm_debug & DRM_UT_DRIVER) \
1512 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1514 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1515 if (drm_debug & DRM_UT_KMS) \
1516 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1519 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1520 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1521 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1522 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1523 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1525 /* nouveau_reg_debug bitmask */
1527 NOUVEAU_REG_DEBUG_MC = 0x1,
1528 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1529 NOUVEAU_REG_DEBUG_FB = 0x4,
1530 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1531 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1532 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1533 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1534 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1535 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1536 NOUVEAU_REG_DEBUG_EVO = 0x200,
1539 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1540 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1541 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1545 nv_two_heads(struct drm_device *dev)
1547 struct drm_nouveau_private *dev_priv = dev->dev_private;
1548 const int impl = dev->pci_device & 0x0ff0;
1550 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1551 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1558 nv_gf4_disp_arch(struct drm_device *dev)
1560 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1564 nv_two_reg_pll(struct drm_device *dev)
1566 struct drm_nouveau_private *dev_priv = dev->dev_private;
1567 const int impl = dev->pci_device & 0x0ff0;
1569 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1575 nv_match_device(struct drm_device *dev, unsigned device,
1576 unsigned sub_vendor, unsigned sub_device)
1578 return dev->pdev->device == device &&
1579 dev->pdev->subsystem_vendor == sub_vendor &&
1580 dev->pdev->subsystem_device == sub_device;
1583 static inline void *
1584 nv_engine(struct drm_device *dev, int engine)
1586 struct drm_nouveau_private *dev_priv = dev->dev_private;
1587 return (void *)dev_priv->eng[engine];
1590 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1591 * helpful to determine a number of other hardware features
1594 nv44_graph_class(struct drm_device *dev)
1596 struct drm_nouveau_private *dev_priv = dev->dev_private;
1598 if ((dev_priv->chipset & 0xf0) == 0x60)
1601 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1604 /* memory type/access flags, do not match hardware values */
1605 #define NV_MEM_ACCESS_RO 1
1606 #define NV_MEM_ACCESS_WO 2
1607 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1608 #define NV_MEM_ACCESS_SYS 4
1609 #define NV_MEM_ACCESS_VM 8
1611 #define NV_MEM_TARGET_VRAM 0
1612 #define NV_MEM_TARGET_PCI 1
1613 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1614 #define NV_MEM_TARGET_VM 3
1615 #define NV_MEM_TARGET_GART 4
1617 #define NV_MEM_TYPE_VM 0x7f
1618 #define NV_MEM_COMP_VM 0x03
1620 /* NV_SW object class */
1621 #define NV_SW 0x0000506e
1622 #define NV_SW_DMA_SEMAPHORE 0x00000060
1623 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1624 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1625 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1626 #define NV_SW_YIELD 0x00000080
1627 #define NV_SW_DMA_VBLSEM 0x0000018c
1628 #define NV_SW_VBLSEM_OFFSET 0x00000400
1629 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1630 #define NV_SW_VBLSEM_RELEASE 0x00000408
1631 #define NV_SW_PAGE_FLIP 0x00000500
1633 #endif /* __NOUVEAU_DRV_H__ */