2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_fence.h"
32 #include "nouveau_software.h"
35 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
37 u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
38 struct drm_device *dev = chan->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
42 /* allocate buffer object */
43 ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
47 ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
51 ret = nouveau_bo_map(chan->pushbuf_bo);
55 /* create DMA object covering the entire memtype where the push
56 * buffer resides, userspace can submit its own push buffers from
57 * anywhere within the same memtype.
59 chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
60 if (dev_priv->card_type >= NV_50) {
61 ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
66 if (dev_priv->card_type < NV_C0) {
67 ret = nouveau_gpuobj_dma_new(chan,
68 NV_CLASS_DMA_IN_MEMORY, 0,
74 chan->pushbuf_base = chan->pushbuf_vma.offset;
76 if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
77 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
78 dev_priv->gart_info.aper_size,
83 if (dev_priv->card_type != NV_04) {
84 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
85 dev_priv->fb_available_size,
90 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
91 * exact reason for existing :) PCI access to cmdbuf in
94 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
95 pci_resource_start(dev->pdev, 1),
96 dev_priv->fb_available_size,
104 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
105 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
106 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
107 if (chan->pushbuf_bo) {
108 nouveau_bo_unmap(chan->pushbuf_bo);
109 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
116 /* allocates and initializes a fifo for user space consumption */
118 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
119 struct drm_file *file_priv,
120 uint32_t vram_handle, uint32_t gart_handle)
122 struct drm_nouveau_private *dev_priv = dev->dev_private;
123 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
124 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
125 struct nouveau_channel *chan;
129 /* allocate and lock channel structure */
130 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
134 chan->file_priv = file_priv;
135 chan->vram_handle = vram_handle;
136 chan->gart_handle = gart_handle;
138 kref_init(&chan->ref);
139 atomic_set(&chan->users, 1);
140 mutex_init(&chan->mutex);
141 mutex_lock(&chan->mutex);
143 /* allocate hw channel id */
144 spin_lock_irqsave(&dev_priv->channels.lock, flags);
145 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
146 if (!dev_priv->channels.ptr[chan->id]) {
147 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
151 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
153 if (chan->id == pfifo->channels) {
154 mutex_unlock(&chan->mutex);
159 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
160 INIT_LIST_HEAD(&chan->fence.pending);
161 spin_lock_init(&chan->fence.lock);
163 /* setup channel's memory and vm */
164 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
166 NV_ERROR(dev, "gpuobj %d\n", ret);
167 nouveau_channel_put(&chan);
171 /* Allocate space for per-channel fixed notifier memory */
172 ret = nouveau_notifier_init_channel(chan);
174 NV_ERROR(dev, "ntfy %d\n", ret);
175 nouveau_channel_put(&chan);
179 /* Allocate DMA push buffer */
180 ret = nouveau_channel_pushbuf_init(chan);
182 NV_ERROR(dev, "pushbuf %d\n", ret);
183 nouveau_channel_put(&chan);
187 nouveau_dma_init(chan);
188 chan->user_put = 0x40;
189 chan->user_get = 0x44;
190 if (dev_priv->card_type >= NV_50)
191 chan->user_get_hi = 0x60;
193 /* disable the fifo caches */
194 pfifo->reassign(dev, false);
196 /* Construct initial RAMFC for new channel */
197 ret = pfifo->create_context(chan);
199 nouveau_channel_put(&chan);
203 pfifo->reassign(dev, true);
205 /* Insert NOPs for NOUVEAU_DMA_SKIPS */
206 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
208 nouveau_channel_put(&chan);
212 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
213 OUT_RING (chan, 0x00000000);
216 ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
218 nouveau_channel_put(&chan);
222 ret = nouveau_fence_channel_init(chan);
224 nouveau_channel_put(&chan);
228 nouveau_debugfs_channel_init(chan);
230 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
232 spin_lock(&fpriv->lock);
233 list_add(&chan->list, &fpriv->channels);
234 spin_unlock(&fpriv->lock);
240 struct nouveau_channel *
241 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
243 struct nouveau_channel *chan = NULL;
245 if (likely(ref && atomic_inc_not_zero(&ref->users)))
246 nouveau_channel_ref(ref, &chan);
251 struct nouveau_channel *
252 nouveau_channel_get(struct drm_file *file_priv, int id)
254 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
255 struct nouveau_channel *chan;
257 spin_lock(&fpriv->lock);
258 list_for_each_entry(chan, &fpriv->channels, list) {
259 if (chan->id == id) {
260 chan = nouveau_channel_get_unlocked(chan);
261 spin_unlock(&fpriv->lock);
262 mutex_lock(&chan->mutex);
266 spin_unlock(&fpriv->lock);
268 return ERR_PTR(-EINVAL);
272 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
274 struct nouveau_channel *chan = *pchan;
275 struct drm_device *dev = chan->dev;
276 struct drm_nouveau_private *dev_priv = dev->dev_private;
277 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
281 /* decrement the refcount, and we're done if there's still refs */
282 if (likely(!atomic_dec_and_test(&chan->users))) {
283 nouveau_channel_ref(NULL, pchan);
287 /* no one wants the channel anymore */
288 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
289 nouveau_debugfs_channel_fini(chan);
291 /* give it chance to idle */
292 nouveau_channel_idle(chan);
294 /* ensure all outstanding fences are signaled. they should be if the
295 * above attempts at idling were OK, but if we failed this'll tell TTM
296 * we're done with the buffers.
298 nouveau_fence_channel_fini(chan);
300 /* boot it off the hardware */
301 pfifo->reassign(dev, false);
303 /* destroy the engine specific contexts */
304 pfifo->destroy_context(chan);
305 for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
307 dev_priv->eng[i]->context_del(chan, i);
310 pfifo->reassign(dev, true);
312 /* aside from its resources, the channel should now be dead,
313 * remove it from the channel list
315 spin_lock_irqsave(&dev_priv->channels.lock, flags);
316 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
317 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
319 /* destroy any resources the channel owned */
320 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
321 if (chan->pushbuf_bo) {
322 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
323 nouveau_bo_unmap(chan->pushbuf_bo);
324 nouveau_bo_unpin(chan->pushbuf_bo);
325 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
327 nouveau_ramht_ref(NULL, &chan->ramht, chan);
328 nouveau_notifier_takedown_channel(chan);
329 nouveau_gpuobj_channel_takedown(chan);
331 nouveau_channel_ref(NULL, pchan);
335 nouveau_channel_put(struct nouveau_channel **pchan)
337 mutex_unlock(&(*pchan)->mutex);
338 nouveau_channel_put_unlocked(pchan);
342 nouveau_channel_del(struct kref *ref)
344 struct nouveau_channel *chan =
345 container_of(ref, struct nouveau_channel, ref);
351 nouveau_channel_ref(struct nouveau_channel *chan,
352 struct nouveau_channel **pchan)
355 kref_get(&chan->ref);
358 kref_put(&(*pchan)->ref, nouveau_channel_del);
364 nouveau_channel_idle(struct nouveau_channel *chan)
366 struct drm_device *dev = chan->dev;
367 struct nouveau_fence *fence = NULL;
370 nouveau_fence_update(chan);
372 if (chan->fence.sequence != chan->fence.sequence_ack) {
373 ret = nouveau_fence_new(chan, &fence);
375 ret = nouveau_fence_wait(fence, false, false);
376 nouveau_fence_unref(&fence);
380 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
384 /* cleans up all the fifos from file_priv */
386 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
388 struct drm_nouveau_private *dev_priv = dev->dev_private;
389 struct nouveau_engine *engine = &dev_priv->engine;
390 struct nouveau_channel *chan;
393 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
394 for (i = 0; i < engine->fifo.channels; i++) {
395 chan = nouveau_channel_get(file_priv, i);
399 list_del(&chan->list);
400 atomic_dec(&chan->users);
401 nouveau_channel_put(&chan);
406 /***********************************
407 * ioctls wrapping the functions
408 ***********************************/
411 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
412 struct drm_file *file_priv)
414 struct drm_nouveau_private *dev_priv = dev->dev_private;
415 struct drm_nouveau_channel_alloc *init = data;
416 struct nouveau_channel *chan;
419 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
422 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
425 ret = nouveau_channel_alloc(dev, &chan, file_priv,
426 init->fb_ctxdma_handle,
427 init->tt_ctxdma_handle);
430 init->channel = chan->id;
432 if (nouveau_vram_pushbuf == 0) {
433 if (chan->dma.ib_max)
434 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
435 NOUVEAU_GEM_DOMAIN_GART;
436 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
437 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
439 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
441 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
444 if (dev_priv->card_type < NV_C0) {
445 init->subchan[0].handle = 0x00000000;
446 init->subchan[0].grclass = 0x0000;
447 init->subchan[1].handle = NvSw;
448 init->subchan[1].grclass = NV_SW;
449 init->nr_subchan = 2;
452 /* Named memory object area */
453 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
454 &init->notifier_handle);
457 atomic_inc(&chan->users); /* userspace reference */
458 nouveau_channel_put(&chan);
463 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
464 struct drm_file *file_priv)
466 struct drm_nouveau_channel_free *req = data;
467 struct nouveau_channel *chan;
469 chan = nouveau_channel_get(file_priv, req->channel);
471 return PTR_ERR(chan);
473 list_del(&chan->list);
474 atomic_dec(&chan->users);
475 nouveau_channel_put(&chan);
479 /***********************************
480 * finally, the ioctl table
481 ***********************************/
483 struct drm_ioctl_desc nouveau_ioctls[] = {
484 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
485 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
486 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
488 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
490 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
491 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
492 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
493 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
494 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
495 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
498 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);