2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
31 #include <linux/io-mapping.h>
33 /* these defines are made up */
34 #define NV_CIO_CRE_44_HEADA 0x0
35 #define NV_CIO_CRE_44_HEADB 0x3
36 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37 #define LEGACY_I2C_CRT 0x80
38 #define LEGACY_I2C_PANEL 0x81
39 #define LEGACY_I2C_TV 0x82
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44 #define LOG_OLD_VALUE(x)
51 static bool nv_cksum(const uint8_t *data, unsigned int length)
54 * There's a few checksums in the BIOS, so here's a generic checking
60 for (i = 0; i < length; i++)
70 score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
82 NV_TRACE(dev, "... appears to be valid\n");
87 static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
94 if (dev_priv->card_type >= NV_50)
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
131 static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
137 if (dev_priv->card_type >= NV_50) {
138 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
140 addr = (u64)nv_rd32(dev, 0x1700) << 16;
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, addr >> 16);
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
161 static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
163 void __iomem *rom = NULL;
167 ret = pci_enable_rom(dev->pdev);
171 rom = pci_map_rom(dev->pdev, &rom_len);
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
178 pci_disable_rom(dev->pdev);
181 static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
185 int size = 64 * 1024;
187 if (!nouveau_acpi_rom_supported(dev->pdev))
190 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
191 ret = nouveau_acpi_get_bios_chunk(data,
202 void (*loadbios)(struct drm_device *, uint8_t *);
206 static struct methods shadow_methods[] = {
207 { "PRAMIN", load_vbios_pramin, true },
208 { "PROM", load_vbios_prom, false },
209 { "PCIROM", load_vbios_pci, true },
210 { "ACPI", load_vbios_acpi, true },
212 #define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
214 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
216 struct methods *methods = shadow_methods;
218 int scores[NUM_SHADOW_METHODS], i;
221 for (i = 0; i < NUM_SHADOW_METHODS; i++)
222 if (!strcasecmp(nouveau_vbios, methods[i].desc))
225 if (i < NUM_SHADOW_METHODS) {
226 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
229 methods[i].loadbios(dev, data);
230 if (score_vbios(dev, data, methods[i].rw))
234 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
237 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
238 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
240 data[0] = data[1] = 0; /* avoid reuse of previous image */
241 methods[i].loadbios(dev, data);
242 scores[i] = score_vbios(dev, data, methods[i].rw);
243 if (scores[i] == testscore)
247 while (--testscore > 0) {
248 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
249 if (scores[i] == testscore) {
250 NV_TRACE(dev, "Using BIOS image from %s\n",
252 methods[i].loadbios(dev, data);
258 NV_ERROR(dev, "No valid BIOS image found\n");
262 struct init_tbl_entry {
266 * > 0: success, length of opcode
267 * 0: success, but abort further parsing of table (INIT_DONE etc)
268 * < 0: failure, table parsing will be aborted
270 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
273 static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
275 #define MACRO_INDEX_SIZE 2
277 #define CONDITION_SIZE 12
278 #define IO_FLAG_CONDITION_SIZE 9
279 #define IO_CONDITION_SIZE 5
280 #define MEM_INIT_SIZE 66
282 static void still_alive(void)
291 munge_reg(struct nvbios *bios, uint32_t reg)
293 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
294 struct dcb_entry *dcbent = bios->display.output;
296 if (dev_priv->card_type < NV_50)
299 if (reg & 0x80000000) {
300 BUG_ON(bios->display.crtc < 0);
301 reg += bios->display.crtc * 0x800;
304 if (reg & 0x40000000) {
307 reg += (ffs(dcbent->or) - 1) * 0x800;
308 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
317 valid_reg(struct nvbios *bios, uint32_t reg)
319 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
320 struct drm_device *dev = bios->dev;
322 /* C51 has misaligned regs on purpose. Marvellous */
324 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
325 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
327 /* warn on C51 regs that haven't been verified accessible in tracing */
328 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
329 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
330 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
333 if (reg >= (8*1024*1024)) {
334 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
342 valid_idx_port(struct nvbios *bios, uint16_t port)
344 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
345 struct drm_device *dev = bios->dev;
348 * If adding more ports here, the read/write functions below will need
349 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
350 * used for the port in question
352 if (dev_priv->card_type < NV_50) {
353 if (port == NV_CIO_CRX__COLOR)
355 if (port == NV_VIO_SRX)
358 if (port == NV_CIO_CRX__COLOR)
362 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
369 valid_port(struct nvbios *bios, uint16_t port)
371 struct drm_device *dev = bios->dev;
374 * If adding more ports here, the read/write functions below will need
375 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
376 * used for the port in question
378 if (port == NV_VIO_VSE2)
381 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
387 bios_rd32(struct nvbios *bios, uint32_t reg)
391 reg = munge_reg(bios, reg);
392 if (!valid_reg(bios, reg))
396 * C51 sometimes uses regs with bit0 set in the address. For these
397 * cases there should exist a translation in a BIOS table to an IO
398 * port address which the BIOS uses for accessing the reg
400 * These only seem to appear for the power control regs to a flat panel,
401 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
402 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
403 * suspend-resume mmio trace from a C51 will be required to see if this
404 * is true for the power microcode in 0x14.., or whether the direct IO
405 * port access method is needed
410 data = nv_rd32(bios->dev, reg);
412 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
418 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
420 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
422 reg = munge_reg(bios, reg);
423 if (!valid_reg(bios, reg))
426 /* see note in bios_rd32 */
430 LOG_OLD_VALUE(bios_rd32(bios, reg));
431 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
433 if (dev_priv->vbios.execute) {
435 nv_wr32(bios->dev, reg, data);
440 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
442 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
443 struct drm_device *dev = bios->dev;
446 if (!valid_idx_port(bios, port))
449 if (dev_priv->card_type < NV_50) {
450 if (port == NV_VIO_SRX)
451 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
452 else /* assume NV_CIO_CRX__COLOR */
453 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
457 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
458 data = (data32 >> ((index & 3) << 3)) & 0xff;
461 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
462 "Head: 0x%02X, Data: 0x%02X\n",
463 port, index, bios->state.crtchead, data);
468 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
470 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
471 struct drm_device *dev = bios->dev;
473 if (!valid_idx_port(bios, port))
477 * The current head is maintained in the nvbios member state.crtchead.
478 * We trap changes to CR44 and update the head variable and hence the
479 * register set written.
480 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
481 * of the write, and to head1 after the write
483 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
484 data != NV_CIO_CRE_44_HEADB)
485 bios->state.crtchead = 0;
487 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
488 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
489 "Head: 0x%02X, Data: 0x%02X\n",
490 port, index, bios->state.crtchead, data);
492 if (bios->execute && dev_priv->card_type < NV_50) {
494 if (port == NV_VIO_SRX)
495 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
496 else /* assume NV_CIO_CRX__COLOR */
497 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
500 uint32_t data32, shift = (index & 3) << 3;
504 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
505 data32 &= ~(0xff << shift);
506 data32 |= (data << shift);
507 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
510 if (port == NV_CIO_CRX__COLOR &&
511 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
512 bios->state.crtchead = 1;
516 bios_port_rd(struct nvbios *bios, uint16_t port)
518 uint8_t data, head = bios->state.crtchead;
520 if (!valid_port(bios, port))
523 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
525 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
532 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
534 int head = bios->state.crtchead;
536 if (!valid_port(bios, port))
539 LOG_OLD_VALUE(bios_port_rd(bios, port));
540 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
547 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
551 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
554 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
555 * for the CRTC index; 1 byte for the mask to apply to the value
556 * retrieved from the CRTC; 1 byte for the shift right to apply to the
557 * masked CRTC value; 2 bytes for the offset to the flag array, to
558 * which the shifted value is added; 1 byte for the mask applied to the
559 * value read from the flag array; and 1 byte for the value to compare
560 * against the masked byte from the flag table.
563 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
564 uint16_t crtcport = ROM16(bios->data[condptr]);
565 uint8_t crtcindex = bios->data[condptr + 2];
566 uint8_t mask = bios->data[condptr + 3];
567 uint8_t shift = bios->data[condptr + 4];
568 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
569 uint8_t flagarraymask = bios->data[condptr + 7];
570 uint8_t cmpval = bios->data[condptr + 8];
573 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
574 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
576 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
578 data = bios_idxprt_rd(bios, crtcport, crtcindex);
580 data = bios->data[flagarray + ((data & mask) >> shift)];
581 data &= flagarraymask;
583 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
584 offset, data, cmpval);
586 return (data == cmpval);
590 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
593 * The condition table entry has 4 bytes for the address of the
594 * register to check, 4 bytes for a mask to apply to the register and
595 * 4 for a test comparison value
598 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
599 uint32_t reg = ROM32(bios->data[condptr]);
600 uint32_t mask = ROM32(bios->data[condptr + 4]);
601 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
604 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
605 offset, cond, reg, mask);
607 data = bios_rd32(bios, reg) & mask;
609 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
610 offset, data, cmpval);
612 return (data == cmpval);
616 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
619 * The IO condition entry has 2 bytes for the IO port address; 1 byte
620 * for the index to write to io_port; 1 byte for the mask to apply to
621 * the byte read from io_port+1; and 1 byte for the value to compare
622 * against the masked byte.
625 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
626 uint16_t io_port = ROM16(bios->data[condptr]);
627 uint8_t port_index = bios->data[condptr + 2];
628 uint8_t mask = bios->data[condptr + 3];
629 uint8_t cmpval = bios->data[condptr + 4];
631 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
633 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
634 offset, data, cmpval);
636 return (data == cmpval);
640 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
642 struct drm_nouveau_private *dev_priv = dev->dev_private;
643 uint32_t reg0 = nv_rd32(dev, reg + 0);
644 uint32_t reg1 = nv_rd32(dev, reg + 4);
645 struct nouveau_pll_vals pll;
646 struct pll_lims pll_limits;
649 ret = get_pll_limits(dev, reg, &pll_limits);
653 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
657 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
658 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
660 if (dev_priv->vbios.execute) {
662 nv_wr32(dev, reg + 4, reg1);
663 nv_wr32(dev, reg + 0, reg0);
670 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
672 struct drm_device *dev = bios->dev;
673 struct drm_nouveau_private *dev_priv = dev->dev_private;
675 struct pll_lims pll_lim;
676 struct nouveau_pll_vals pllvals;
679 if (dev_priv->card_type >= NV_50)
680 return nv50_pll_set(dev, reg, clk);
682 /* high regs (such as in the mac g5 table) are not -= 4 */
683 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
687 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
693 nouveau_hw_setpll(dev, reg, &pllvals);
699 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
701 struct drm_nouveau_private *dev_priv = dev->dev_private;
702 struct nvbios *bios = &dev_priv->vbios;
705 * For the results of this function to be correct, CR44 must have been
706 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
707 * and the DCB table parsed, before the script calling the function is
708 * run. run_digital_op_script is example of how to do such setup
711 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
713 if (dcb_entry > bios->dcb.entries) {
714 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
715 "(%02X)\n", dcb_entry);
716 dcb_entry = 0x7f; /* unused / invalid marker */
723 read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
725 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
726 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
727 int recordoffset = 0, rdofs = 1, wrofs = 0;
728 uint8_t port_type = 0;
733 if (dcb_version >= 0x30) {
734 if (i2ctable[0] != dcb_version) /* necessary? */
736 "DCB I2C table version mismatch (%02X vs %02X)\n",
737 i2ctable[0], dcb_version);
738 dcb_i2c_ver = i2ctable[0];
739 headerlen = i2ctable[1];
740 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
741 i2c_entries = i2ctable[2];
744 "DCB I2C table has more entries than indexable "
745 "(%d entries, max %d)\n", i2ctable[2],
746 DCB_MAX_NUM_I2C_ENTRIES);
747 entry_len = i2ctable[3];
748 /* [4] is i2c_default_indices, read in parse_dcb_table() */
751 * It's your own fault if you call this function on a DCB 1.1 BIOS --
752 * the test below is for DCB 1.2
754 if (dcb_version < 0x14) {
762 if (index >= i2c_entries) {
763 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
767 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
768 NV_ERROR(dev, "DCB I2C entry invalid\n");
772 if (dcb_i2c_ver >= 0x30) {
773 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
776 * Fixup for chips using same address offset for read and
779 if (port_type == 4) /* seen on C51 */
781 if (port_type >= 5) /* G80+ */
785 if (dcb_i2c_ver >= 0x40) {
786 if (port_type != 5 && port_type != 6)
787 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
789 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
792 i2c->port_type = port_type;
793 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
794 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
799 static struct nouveau_i2c_chan *
800 init_i2c_device_find(struct drm_device *dev, int i2c_index)
802 struct drm_nouveau_private *dev_priv = dev->dev_private;
803 struct dcb_table *dcb = &dev_priv->vbios.dcb;
805 if (i2c_index == 0xff) {
806 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
807 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
808 int default_indices = dcb->i2c_default_indices;
810 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
813 i2c_index = (default_indices >> shift) & 0xf;
815 if (i2c_index == 0x80) /* g80+ */
816 i2c_index = dcb->i2c_default_indices & 0xf;
818 if (i2c_index == 0x81)
819 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
821 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
822 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
826 /* Make sure i2c table entry has been parsed, it may not
827 * have been if this is a bus not referenced by a DCB encoder
829 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
830 i2c_index, &dcb->i2c[i2c_index]);
832 return nouveau_i2c_find(dev, i2c_index);
836 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
839 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
840 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
841 * CR58 for CR57 = 0 to index a table of offsets to the basic
843 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
844 * CR58 for CR57 = 0 to index a table of offsets to the basic
845 * 0x6808b0 address, and then flip the offset by 8.
848 struct drm_nouveau_private *dev_priv = dev->dev_private;
849 struct nvbios *bios = &dev_priv->vbios;
850 const int pramdac_offset[13] = {
851 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
852 const uint32_t pramdac_table[4] = {
853 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
856 int dcb_entry, dacoffset;
858 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
859 dcb_entry = dcb_entry_idx_from_crtchead(dev);
860 if (dcb_entry == 0x7f)
862 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
865 return 0x6808b0 + dacoffset;
867 if (mlv >= ARRAY_SIZE(pramdac_table)) {
868 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
872 return pramdac_table[mlv];
877 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
878 struct init_exec *iexec)
881 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
883 * offset (8 bit): opcode
884 * offset + 1 (16 bit): CRTC port
885 * offset + 3 (8 bit): CRTC index
886 * offset + 4 (8 bit): mask
887 * offset + 5 (8 bit): shift
888 * offset + 6 (8 bit): count
889 * offset + 7 (32 bit): register
890 * offset + 11 (32 bit): configuration 1
893 * Starting at offset + 11 there are "count" 32 bit values.
894 * To find out which value to use read index "CRTC index" on "CRTC
895 * port", AND this value with "mask" and then bit shift right "shift"
896 * bits. Read the appropriate value using this index and write to
900 uint16_t crtcport = ROM16(bios->data[offset + 1]);
901 uint8_t crtcindex = bios->data[offset + 3];
902 uint8_t mask = bios->data[offset + 4];
903 uint8_t shift = bios->data[offset + 5];
904 uint8_t count = bios->data[offset + 6];
905 uint32_t reg = ROM32(bios->data[offset + 7]);
908 int len = 11 + count * 4;
913 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
914 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
915 offset, crtcport, crtcindex, mask, shift, count, reg);
917 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
918 if (config > count) {
920 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
921 offset, config, count);
925 configval = ROM32(bios->data[offset + 11 + config * 4]);
927 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
929 bios_wr32(bios, reg, configval);
935 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
938 * INIT_REPEAT opcode: 0x33 ('3')
940 * offset (8 bit): opcode
941 * offset + 1 (8 bit): count
943 * Execute script following this opcode up to INIT_REPEAT_END
947 uint8_t count = bios->data[offset + 1];
950 /* no iexec->execute check by design */
952 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
955 iexec->repeat = true;
958 * count - 1, as the script block will execute once when we leave this
959 * opcode -- this is compatible with bios behaviour as:
960 * a) the block is always executed at least once, even if count == 0
961 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
964 for (i = 0; i < count - 1; i++)
965 parse_init_table(bios, offset + 2, iexec);
967 iexec->repeat = false;
973 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
974 struct init_exec *iexec)
977 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
979 * offset (8 bit): opcode
980 * offset + 1 (16 bit): CRTC port
981 * offset + 3 (8 bit): CRTC index
982 * offset + 4 (8 bit): mask
983 * offset + 5 (8 bit): shift
984 * offset + 6 (8 bit): IO flag condition index
985 * offset + 7 (8 bit): count
986 * offset + 8 (32 bit): register
987 * offset + 12 (16 bit): frequency 1
990 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
991 * Set PLL register "register" to coefficients for frequency n,
992 * selected by reading index "CRTC index" of "CRTC port" ANDed with
993 * "mask" and shifted right by "shift".
995 * If "IO flag condition index" > 0, and condition met, double
996 * frequency before setting it.
999 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1000 uint8_t crtcindex = bios->data[offset + 3];
1001 uint8_t mask = bios->data[offset + 4];
1002 uint8_t shift = bios->data[offset + 5];
1003 int8_t io_flag_condition_idx = bios->data[offset + 6];
1004 uint8_t count = bios->data[offset + 7];
1005 uint32_t reg = ROM32(bios->data[offset + 8]);
1008 int len = 12 + count * 2;
1010 if (!iexec->execute)
1013 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1014 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1015 "Count: 0x%02X, Reg: 0x%08X\n",
1016 offset, crtcport, crtcindex, mask, shift,
1017 io_flag_condition_idx, count, reg);
1019 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1020 if (config > count) {
1022 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1023 offset, config, count);
1027 freq = ROM16(bios->data[offset + 12 + config * 2]);
1029 if (io_flag_condition_idx > 0) {
1030 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1031 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1032 "frequency doubled\n", offset);
1035 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1036 "frequency unchanged\n", offset);
1039 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1040 offset, reg, config, freq);
1042 setPLL(bios, reg, freq * 10);
1048 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1051 * INIT_END_REPEAT opcode: 0x36 ('6')
1053 * offset (8 bit): opcode
1055 * Marks the end of the block for INIT_REPEAT to repeat
1058 /* no iexec->execute check by design */
1061 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1062 * we're not in repeat mode
1071 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1074 * INIT_COPY opcode: 0x37 ('7')
1076 * offset (8 bit): opcode
1077 * offset + 1 (32 bit): register
1078 * offset + 5 (8 bit): shift
1079 * offset + 6 (8 bit): srcmask
1080 * offset + 7 (16 bit): CRTC port
1081 * offset + 9 (8 bit): CRTC index
1082 * offset + 10 (8 bit): mask
1084 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1085 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1089 uint32_t reg = ROM32(bios->data[offset + 1]);
1090 uint8_t shift = bios->data[offset + 5];
1091 uint8_t srcmask = bios->data[offset + 6];
1092 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1093 uint8_t crtcindex = bios->data[offset + 9];
1094 uint8_t mask = bios->data[offset + 10];
1098 if (!iexec->execute)
1101 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1102 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1103 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1105 data = bios_rd32(bios, reg);
1110 data <<= (0x100 - shift);
1114 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1115 crtcdata |= (uint8_t)data;
1116 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1122 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1125 * INIT_NOT opcode: 0x38 ('8')
1127 * offset (8 bit): opcode
1129 * Invert the current execute / no-execute condition (i.e. "else")
1132 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1134 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1136 iexec->execute = !iexec->execute;
1141 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1142 struct init_exec *iexec)
1145 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1147 * offset (8 bit): opcode
1148 * offset + 1 (8 bit): condition number
1150 * Check condition "condition number" in the IO flag condition table.
1151 * If condition not met skip subsequent opcodes until condition is
1152 * inverted (INIT_NOT), or we hit INIT_RESUME
1155 uint8_t cond = bios->data[offset + 1];
1157 if (!iexec->execute)
1160 if (io_flag_condition_met(bios, offset, cond))
1161 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1163 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1164 iexec->execute = false;
1171 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1174 * INIT_DP_CONDITION opcode: 0x3A ('')
1176 * offset (8 bit): opcode
1177 * offset + 1 (8 bit): "sub" opcode
1178 * offset + 2 (8 bit): unknown
1182 struct bit_displayport_encoder_table *dpe = NULL;
1183 struct dcb_entry *dcb = bios->display.output;
1184 struct drm_device *dev = bios->dev;
1185 uint8_t cond = bios->data[offset + 1];
1188 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1190 if (!iexec->execute)
1193 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1195 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
1202 struct dcb_connector_table_entry *ent =
1203 &bios->dcb.connector.entry[dcb->connector];
1205 if (ent->type != DCB_CONNECTOR_eDP)
1206 iexec->execute = false;
1211 if (!(dpe->unknown & cond))
1212 iexec->execute = false;
1216 struct nouveau_i2c_chan *auxch;
1219 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1221 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1225 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1227 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1232 iexec->execute = false;
1236 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1241 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1243 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1249 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1252 * INIT_3B opcode: 0x3B ('')
1254 * offset (8 bit): opcode
1255 * offset + 1 (8 bit): crtc index
1259 uint8_t or = ffs(bios->display.output->or) - 1;
1260 uint8_t index = bios->data[offset + 1];
1263 if (!iexec->execute)
1266 data = bios_idxprt_rd(bios, 0x3d4, index);
1267 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1272 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1275 * INIT_3C opcode: 0x3C ('')
1277 * offset (8 bit): opcode
1278 * offset + 1 (8 bit): crtc index
1282 uint8_t or = ffs(bios->display.output->or) - 1;
1283 uint8_t index = bios->data[offset + 1];
1286 if (!iexec->execute)
1289 data = bios_idxprt_rd(bios, 0x3d4, index);
1290 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1295 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1296 struct init_exec *iexec)
1299 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1301 * offset (8 bit): opcode
1302 * offset + 1 (32 bit): control register
1303 * offset + 5 (32 bit): data register
1304 * offset + 9 (32 bit): mask
1305 * offset + 13 (32 bit): data
1306 * offset + 17 (8 bit): count
1307 * offset + 18 (8 bit): address 1
1308 * offset + 19 (8 bit): data 1
1311 * For each of "count" address and data pairs, write "data n" to
1312 * "data register", read the current value of "control register",
1313 * and write it back once ANDed with "mask", ORed with "data",
1314 * and ORed with "address n"
1317 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1318 uint32_t datareg = ROM32(bios->data[offset + 5]);
1319 uint32_t mask = ROM32(bios->data[offset + 9]);
1320 uint32_t data = ROM32(bios->data[offset + 13]);
1321 uint8_t count = bios->data[offset + 17];
1322 int len = 18 + count * 2;
1326 if (!iexec->execute)
1329 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1330 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1331 offset, controlreg, datareg, mask, data, count);
1333 for (i = 0; i < count; i++) {
1334 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1335 uint8_t instdata = bios->data[offset + 19 + i * 2];
1337 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1338 offset, instaddress, instdata);
1340 bios_wr32(bios, datareg, instdata);
1341 value = bios_rd32(bios, controlreg) & mask;
1343 value |= instaddress;
1344 bios_wr32(bios, controlreg, value);
1351 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1352 struct init_exec *iexec)
1355 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1357 * offset (8 bit): opcode
1358 * offset + 1 (16 bit): CRTC port
1359 * offset + 3 (8 bit): CRTC index
1360 * offset + 4 (8 bit): mask
1361 * offset + 5 (8 bit): shift
1362 * offset + 6 (8 bit): count
1363 * offset + 7 (32 bit): register
1364 * offset + 11 (32 bit): frequency 1
1367 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1368 * Set PLL register "register" to coefficients for frequency n,
1369 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1370 * "mask" and shifted right by "shift".
1373 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1374 uint8_t crtcindex = bios->data[offset + 3];
1375 uint8_t mask = bios->data[offset + 4];
1376 uint8_t shift = bios->data[offset + 5];
1377 uint8_t count = bios->data[offset + 6];
1378 uint32_t reg = ROM32(bios->data[offset + 7]);
1379 int len = 11 + count * 4;
1383 if (!iexec->execute)
1386 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1387 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1388 offset, crtcport, crtcindex, mask, shift, count, reg);
1393 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1394 if (config > count) {
1396 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1397 offset, config, count);
1401 freq = ROM32(bios->data[offset + 11 + config * 4]);
1403 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1404 offset, reg, config, freq);
1406 setPLL(bios, reg, freq);
1412 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1415 * INIT_PLL2 opcode: 0x4B ('K')
1417 * offset (8 bit): opcode
1418 * offset + 1 (32 bit): register
1419 * offset + 5 (32 bit): freq
1421 * Set PLL register "register" to coefficients for frequency "freq"
1424 uint32_t reg = ROM32(bios->data[offset + 1]);
1425 uint32_t freq = ROM32(bios->data[offset + 5]);
1427 if (!iexec->execute)
1430 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1433 setPLL(bios, reg, freq);
1438 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1441 * INIT_I2C_BYTE opcode: 0x4C ('L')
1443 * offset (8 bit): opcode
1444 * offset + 1 (8 bit): DCB I2C table entry index
1445 * offset + 2 (8 bit): I2C slave address
1446 * offset + 3 (8 bit): count
1447 * offset + 4 (8 bit): I2C register 1
1448 * offset + 5 (8 bit): mask 1
1449 * offset + 6 (8 bit): data 1
1452 * For each of "count" registers given by "I2C register n" on the device
1453 * addressed by "I2C slave address" on the I2C bus given by
1454 * "DCB I2C table entry index", read the register, AND the result with
1455 * "mask n" and OR it with "data n" before writing it back to the device
1458 struct drm_device *dev = bios->dev;
1459 uint8_t i2c_index = bios->data[offset + 1];
1460 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1461 uint8_t count = bios->data[offset + 3];
1462 struct nouveau_i2c_chan *chan;
1463 int len = 4 + count * 3;
1466 if (!iexec->execute)
1469 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1471 offset, i2c_index, i2c_address, count);
1473 chan = init_i2c_device_find(dev, i2c_index);
1475 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1479 for (i = 0; i < count; i++) {
1480 uint8_t reg = bios->data[offset + 4 + i * 3];
1481 uint8_t mask = bios->data[offset + 5 + i * 3];
1482 uint8_t data = bios->data[offset + 6 + i * 3];
1483 union i2c_smbus_data val;
1485 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1486 I2C_SMBUS_READ, reg,
1487 I2C_SMBUS_BYTE_DATA, &val);
1489 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1493 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1494 "Mask: 0x%02X, Data: 0x%02X\n",
1495 offset, reg, val.byte, mask, data);
1502 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1503 I2C_SMBUS_WRITE, reg,
1504 I2C_SMBUS_BYTE_DATA, &val);
1506 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1515 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1518 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1520 * offset (8 bit): opcode
1521 * offset + 1 (8 bit): DCB I2C table entry index
1522 * offset + 2 (8 bit): I2C slave address
1523 * offset + 3 (8 bit): count
1524 * offset + 4 (8 bit): I2C register 1
1525 * offset + 5 (8 bit): data 1
1528 * For each of "count" registers given by "I2C register n" on the device
1529 * addressed by "I2C slave address" on the I2C bus given by
1530 * "DCB I2C table entry index", set the register to "data n"
1533 struct drm_device *dev = bios->dev;
1534 uint8_t i2c_index = bios->data[offset + 1];
1535 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1536 uint8_t count = bios->data[offset + 3];
1537 struct nouveau_i2c_chan *chan;
1538 int len = 4 + count * 2;
1541 if (!iexec->execute)
1544 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1546 offset, i2c_index, i2c_address, count);
1548 chan = init_i2c_device_find(dev, i2c_index);
1550 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1554 for (i = 0; i < count; i++) {
1555 uint8_t reg = bios->data[offset + 4 + i * 2];
1556 union i2c_smbus_data val;
1558 val.byte = bios->data[offset + 5 + i * 2];
1560 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1561 offset, reg, val.byte);
1566 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1567 I2C_SMBUS_WRITE, reg,
1568 I2C_SMBUS_BYTE_DATA, &val);
1570 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1579 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1582 * INIT_ZM_I2C opcode: 0x4E ('N')
1584 * offset (8 bit): opcode
1585 * offset + 1 (8 bit): DCB I2C table entry index
1586 * offset + 2 (8 bit): I2C slave address
1587 * offset + 3 (8 bit): count
1588 * offset + 4 (8 bit): data 1
1591 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1592 * address" on the I2C bus given by "DCB I2C table entry index"
1595 struct drm_device *dev = bios->dev;
1596 uint8_t i2c_index = bios->data[offset + 1];
1597 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1598 uint8_t count = bios->data[offset + 3];
1599 int len = 4 + count;
1600 struct nouveau_i2c_chan *chan;
1605 if (!iexec->execute)
1608 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1610 offset, i2c_index, i2c_address, count);
1612 chan = init_i2c_device_find(dev, i2c_index);
1614 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1618 for (i = 0; i < count; i++) {
1619 data[i] = bios->data[offset + 4 + i];
1621 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1624 if (bios->execute) {
1625 msg.addr = i2c_address;
1629 ret = i2c_transfer(&chan->adapter, &msg, 1);
1631 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1640 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1643 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1645 * offset (8 bit): opcode
1646 * offset + 1 (8 bit): magic lookup value
1647 * offset + 2 (8 bit): TMDS address
1648 * offset + 3 (8 bit): mask
1649 * offset + 4 (8 bit): data
1651 * Read the data reg for TMDS address "TMDS address", AND it with mask
1652 * and OR it with data, then write it back
1653 * "magic lookup value" determines which TMDS base address register is
1654 * used -- see get_tmds_index_reg()
1657 struct drm_device *dev = bios->dev;
1658 uint8_t mlv = bios->data[offset + 1];
1659 uint32_t tmdsaddr = bios->data[offset + 2];
1660 uint8_t mask = bios->data[offset + 3];
1661 uint8_t data = bios->data[offset + 4];
1662 uint32_t reg, value;
1664 if (!iexec->execute)
1667 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1668 "Mask: 0x%02X, Data: 0x%02X\n",
1669 offset, mlv, tmdsaddr, mask, data);
1671 reg = get_tmds_index_reg(bios->dev, mlv);
1673 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1677 bios_wr32(bios, reg,
1678 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1679 value = (bios_rd32(bios, reg + 4) & mask) | data;
1680 bios_wr32(bios, reg + 4, value);
1681 bios_wr32(bios, reg, tmdsaddr);
1687 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1688 struct init_exec *iexec)
1691 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1693 * offset (8 bit): opcode
1694 * offset + 1 (8 bit): magic lookup value
1695 * offset + 2 (8 bit): count
1696 * offset + 3 (8 bit): addr 1
1697 * offset + 4 (8 bit): data 1
1700 * For each of "count" TMDS address and data pairs write "data n" to
1701 * "addr n". "magic lookup value" determines which TMDS base address
1702 * register is used -- see get_tmds_index_reg()
1705 struct drm_device *dev = bios->dev;
1706 uint8_t mlv = bios->data[offset + 1];
1707 uint8_t count = bios->data[offset + 2];
1708 int len = 3 + count * 2;
1712 if (!iexec->execute)
1715 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1716 offset, mlv, count);
1718 reg = get_tmds_index_reg(bios->dev, mlv);
1720 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1724 for (i = 0; i < count; i++) {
1725 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1726 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1728 bios_wr32(bios, reg + 4, tmdsdata);
1729 bios_wr32(bios, reg, tmdsaddr);
1736 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1737 struct init_exec *iexec)
1740 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1742 * offset (8 bit): opcode
1743 * offset + 1 (8 bit): CRTC index1
1744 * offset + 2 (8 bit): CRTC index2
1745 * offset + 3 (8 bit): baseaddr
1746 * offset + 4 (8 bit): count
1747 * offset + 5 (8 bit): data 1
1750 * For each of "count" address and data pairs, write "baseaddr + n" to
1751 * "CRTC index1" and "data n" to "CRTC index2"
1752 * Once complete, restore initial value read from "CRTC index1"
1754 uint8_t crtcindex1 = bios->data[offset + 1];
1755 uint8_t crtcindex2 = bios->data[offset + 2];
1756 uint8_t baseaddr = bios->data[offset + 3];
1757 uint8_t count = bios->data[offset + 4];
1758 int len = 5 + count;
1759 uint8_t oldaddr, data;
1762 if (!iexec->execute)
1765 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1766 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1767 offset, crtcindex1, crtcindex2, baseaddr, count);
1769 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1771 for (i = 0; i < count; i++) {
1772 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1774 data = bios->data[offset + 5 + i];
1775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1778 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1784 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1787 * INIT_CR opcode: 0x52 ('R')
1789 * offset (8 bit): opcode
1790 * offset + 1 (8 bit): CRTC index
1791 * offset + 2 (8 bit): mask
1792 * offset + 3 (8 bit): data
1794 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1795 * data back to "CRTC index"
1798 uint8_t crtcindex = bios->data[offset + 1];
1799 uint8_t mask = bios->data[offset + 2];
1800 uint8_t data = bios->data[offset + 3];
1803 if (!iexec->execute)
1806 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1807 offset, crtcindex, mask, data);
1809 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1811 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1817 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1820 * INIT_ZM_CR opcode: 0x53 ('S')
1822 * offset (8 bit): opcode
1823 * offset + 1 (8 bit): CRTC index
1824 * offset + 2 (8 bit): value
1826 * Assign "value" to CRTC register with index "CRTC index".
1829 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1830 uint8_t data = bios->data[offset + 2];
1832 if (!iexec->execute)
1835 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1841 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1844 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1846 * offset (8 bit): opcode
1847 * offset + 1 (8 bit): count
1848 * offset + 2 (8 bit): CRTC index 1
1849 * offset + 3 (8 bit): value 1
1852 * For "count", assign "value n" to CRTC register with index
1856 uint8_t count = bios->data[offset + 1];
1857 int len = 2 + count * 2;
1860 if (!iexec->execute)
1863 for (i = 0; i < count; i++)
1864 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1870 init_condition_time(struct nvbios *bios, uint16_t offset,
1871 struct init_exec *iexec)
1874 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1876 * offset (8 bit): opcode
1877 * offset + 1 (8 bit): condition number
1878 * offset + 2 (8 bit): retries / 50
1880 * Check condition "condition number" in the condition table.
1881 * Bios code then sleeps for 2ms if the condition is not met, and
1882 * repeats up to "retries" times, but on one C51 this has proved
1883 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1884 * this, and bail after "retries" times, or 2s, whichever is less.
1885 * If still not met after retries, clear execution flag for this table.
1888 uint8_t cond = bios->data[offset + 1];
1889 uint16_t retries = bios->data[offset + 2] * 50;
1892 if (!iexec->execute)
1898 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1899 offset, cond, retries);
1901 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1904 for (cnt = 0; cnt < retries; cnt++) {
1905 if (bios_condition_met(bios, offset, cond)) {
1906 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1910 BIOSLOG(bios, "0x%04X: "
1911 "Condition not met, sleeping for 20ms\n",
1917 if (!bios_condition_met(bios, offset, cond)) {
1919 "0x%04X: Condition still not met after %dms, "
1920 "skipping following opcodes\n", offset, 20 * retries);
1921 iexec->execute = false;
1928 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1931 * INIT_LTIME opcode: 0x57 ('V')
1933 * offset (8 bit): opcode
1934 * offset + 1 (16 bit): time
1936 * Sleep for "time" milliseconds.
1939 unsigned time = ROM16(bios->data[offset + 1]);
1941 if (!iexec->execute)
1944 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1953 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1954 struct init_exec *iexec)
1957 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1959 * offset (8 bit): opcode
1960 * offset + 1 (32 bit): base register
1961 * offset + 5 (8 bit): count
1962 * offset + 6 (32 bit): value 1
1965 * Starting at offset + 6 there are "count" 32 bit values.
1966 * For "count" iterations set "base register" + 4 * current_iteration
1967 * to "value current_iteration"
1970 uint32_t basereg = ROM32(bios->data[offset + 1]);
1971 uint32_t count = bios->data[offset + 5];
1972 int len = 6 + count * 4;
1975 if (!iexec->execute)
1978 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1979 offset, basereg, count);
1981 for (i = 0; i < count; i++) {
1982 uint32_t reg = basereg + i * 4;
1983 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1985 bios_wr32(bios, reg, data);
1992 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1995 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1997 * offset (8 bit): opcode
1998 * offset + 1 (16 bit): subroutine offset (in bios)
2000 * Calls a subroutine that will execute commands until INIT_DONE
2004 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
2006 if (!iexec->execute)
2009 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
2010 offset, sub_offset);
2012 parse_init_table(bios, sub_offset, iexec);
2014 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
2020 init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2023 * INIT_JUMP opcode: 0x5C ('\')
2025 * offset (8 bit): opcode
2026 * offset + 1 (16 bit): offset (in bios)
2028 * Continue execution of init table from 'offset'
2031 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
2033 if (!iexec->execute)
2036 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
2037 return jmp_offset - offset;
2041 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2044 * INIT_I2C_IF opcode: 0x5E ('^')
2046 * offset (8 bit): opcode
2047 * offset + 1 (8 bit): DCB I2C table entry index
2048 * offset + 2 (8 bit): I2C slave address
2049 * offset + 3 (8 bit): I2C register
2050 * offset + 4 (8 bit): mask
2051 * offset + 5 (8 bit): data
2053 * Read the register given by "I2C register" on the device addressed
2054 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2055 * entry index". Compare the result AND "mask" to "data".
2056 * If they're not equal, skip subsequent opcodes until condition is
2057 * inverted (INIT_NOT), or we hit INIT_RESUME
2060 uint8_t i2c_index = bios->data[offset + 1];
2061 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2062 uint8_t reg = bios->data[offset + 3];
2063 uint8_t mask = bios->data[offset + 4];
2064 uint8_t data = bios->data[offset + 5];
2065 struct nouveau_i2c_chan *chan;
2066 union i2c_smbus_data val;
2069 /* no execute check by design */
2071 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2072 offset, i2c_index, i2c_address);
2074 chan = init_i2c_device_find(bios->dev, i2c_index);
2078 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2079 I2C_SMBUS_READ, reg,
2080 I2C_SMBUS_BYTE_DATA, &val);
2082 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2083 "Mask: 0x%02X, Data: 0x%02X\n",
2084 offset, reg, mask, data);
2089 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2090 "Mask: 0x%02X, Data: 0x%02X\n",
2091 offset, reg, val.byte, mask, data);
2093 iexec->execute = ((val.byte & mask) == data);
2099 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2102 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2104 * offset (8 bit): opcode
2105 * offset + 1 (32 bit): src reg
2106 * offset + 5 (8 bit): shift
2107 * offset + 6 (32 bit): src mask
2108 * offset + 10 (32 bit): xor
2109 * offset + 14 (32 bit): dst reg
2110 * offset + 18 (32 bit): dst mask
2112 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2113 * "src mask", then XOR with "xor". Write this OR'd with
2114 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2117 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2118 uint8_t shift = bios->data[offset + 5];
2119 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2120 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2121 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2122 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2123 uint32_t srcvalue, dstvalue;
2125 if (!iexec->execute)
2128 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2129 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2130 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2132 srcvalue = bios_rd32(bios, srcreg);
2137 srcvalue <<= (0x100 - shift);
2139 srcvalue = (srcvalue & srcmask) ^ xor;
2141 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2143 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2149 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2152 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2154 * offset (8 bit): opcode
2155 * offset + 1 (16 bit): CRTC port
2156 * offset + 3 (8 bit): CRTC index
2157 * offset + 4 (8 bit): data
2159 * Write "data" to index "CRTC index" of "CRTC port"
2161 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2162 uint8_t crtcindex = bios->data[offset + 3];
2163 uint8_t data = bios->data[offset + 4];
2165 if (!iexec->execute)
2168 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2174 bios_md32(struct nvbios *bios, uint32_t reg,
2175 uint32_t mask, uint32_t val)
2177 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2181 peek_fb(struct drm_device *dev, struct io_mapping *fb,
2186 if (off < pci_resource_len(dev->pdev, 1)) {
2187 uint8_t __iomem *p =
2188 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2190 val = ioread32(p + (off & ~PAGE_MASK));
2192 io_mapping_unmap_atomic(p);
2199 poke_fb(struct drm_device *dev, struct io_mapping *fb,
2200 uint32_t off, uint32_t val)
2202 if (off < pci_resource_len(dev->pdev, 1)) {
2203 uint8_t __iomem *p =
2204 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2206 iowrite32(val, p + (off & ~PAGE_MASK));
2209 io_mapping_unmap_atomic(p);
2214 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2215 uint32_t off, uint32_t val)
2217 poke_fb(dev, fb, off, val);
2218 return val == peek_fb(dev, fb, off);
2222 nv04_init_compute_mem(struct nvbios *bios)
2224 struct drm_device *dev = bios->dev;
2225 uint32_t patt = 0xdeadbeef;
2226 struct io_mapping *fb;
2229 /* Map the framebuffer aperture */
2230 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2231 pci_resource_len(dev->pdev, 1));
2235 /* Sequencer and refresh off */
2236 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2237 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2239 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2240 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2241 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2242 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2244 for (i = 0; i < 4; i++)
2245 poke_fb(dev, fb, 4 * i, patt);
2247 poke_fb(dev, fb, 0x400000, patt + 1);
2249 if (peek_fb(dev, fb, 0) == patt + 1) {
2250 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2251 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2252 bios_md32(bios, NV04_PFB_DEBUG_0,
2253 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2255 for (i = 0; i < 4; i++)
2256 poke_fb(dev, fb, 4 * i, patt);
2258 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2259 bios_md32(bios, NV04_PFB_BOOT_0,
2260 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2261 NV04_PFB_BOOT_0_RAM_AMOUNT,
2262 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2264 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2265 (patt & 0xffff0000)) {
2266 bios_md32(bios, NV04_PFB_BOOT_0,
2267 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2268 NV04_PFB_BOOT_0_RAM_AMOUNT,
2269 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2271 } else if (peek_fb(dev, fb, 0) != patt) {
2272 if (read_back_fb(dev, fb, 0x800000, patt))
2273 bios_md32(bios, NV04_PFB_BOOT_0,
2274 NV04_PFB_BOOT_0_RAM_AMOUNT,
2275 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2277 bios_md32(bios, NV04_PFB_BOOT_0,
2278 NV04_PFB_BOOT_0_RAM_AMOUNT,
2279 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2281 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2282 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2284 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2285 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2286 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2290 /* Refresh on, sequencer on */
2291 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2292 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2294 io_mapping_free(fb);
2298 static const uint8_t *
2299 nv05_memory_config(struct nvbios *bios)
2301 /* Defaults for BIOSes lacking a memory config table */
2302 static const uint8_t default_config_tab[][2] = {
2312 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2313 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2315 if (bios->legacy.mem_init_tbl_ptr)
2316 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2318 return default_config_tab[i];
2322 nv05_init_compute_mem(struct nvbios *bios)
2324 struct drm_device *dev = bios->dev;
2325 const uint8_t *ramcfg = nv05_memory_config(bios);
2326 uint32_t patt = 0xdeadbeef;
2327 struct io_mapping *fb;
2330 /* Map the framebuffer aperture */
2331 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2332 pci_resource_len(dev->pdev, 1));
2337 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2339 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2342 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2344 /* If present load the hardcoded scrambling table */
2345 if (bios->legacy.mem_init_tbl_ptr) {
2346 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2347 bios->legacy.mem_init_tbl_ptr + 0x10];
2349 for (i = 0; i < 8; i++)
2350 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2351 ROM32(scramble_tab[i]));
2354 /* Set memory type/width/length defaults depending on the straps */
2355 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2357 if (ramcfg[1] & 0x80)
2358 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2360 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2361 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2363 /* Probe memory bus width */
2364 for (i = 0; i < 4; i++)
2365 poke_fb(dev, fb, 4 * i, patt);
2367 if (peek_fb(dev, fb, 0xc) != patt)
2368 bios_md32(bios, NV04_PFB_BOOT_0,
2369 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2371 /* Probe memory length */
2372 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2374 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2375 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2376 !read_back_fb(dev, fb, 0, ++patt)))
2377 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2378 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2380 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2381 !read_back_fb(dev, fb, 0x800000, ++patt))
2382 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2383 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2385 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2386 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2387 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2391 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2393 io_mapping_free(fb);
2398 nv10_init_compute_mem(struct nvbios *bios)
2400 struct drm_device *dev = bios->dev;
2401 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2402 const int mem_width[] = { 0x10, 0x00, 0x20 };
2403 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2404 uint32_t patt = 0xdeadbeef;
2405 struct io_mapping *fb;
2408 /* Map the framebuffer aperture */
2409 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2410 pci_resource_len(dev->pdev, 1));
2414 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2416 /* Probe memory bus width */
2417 for (i = 0; i < mem_width_count; i++) {
2418 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2420 for (j = 0; j < 4; j++) {
2421 for (k = 0; k < 4; k++)
2422 poke_fb(dev, fb, 0x1c, 0);
2424 poke_fb(dev, fb, 0x1c, patt);
2425 poke_fb(dev, fb, 0x3c, 0);
2427 if (peek_fb(dev, fb, 0x1c) == patt)
2428 goto mem_width_found;
2435 /* Probe amount of installed memory */
2436 for (i = 0; i < 4; i++) {
2437 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2439 poke_fb(dev, fb, off, patt);
2440 poke_fb(dev, fb, 0, 0);
2442 peek_fb(dev, fb, 0);
2443 peek_fb(dev, fb, 0);
2444 peek_fb(dev, fb, 0);
2445 peek_fb(dev, fb, 0);
2447 if (peek_fb(dev, fb, off) == patt)
2451 /* IC missing - disable the upper half memory space. */
2452 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2455 io_mapping_free(fb);
2460 nv20_init_compute_mem(struct nvbios *bios)
2462 struct drm_device *dev = bios->dev;
2463 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2464 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2465 uint32_t amount, off;
2466 struct io_mapping *fb;
2468 /* Map the framebuffer aperture */
2469 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2470 pci_resource_len(dev->pdev, 1));
2474 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2476 /* Allow full addressing */
2477 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2479 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2480 for (off = amount; off > 0x2000000; off -= 0x2000000)
2481 poke_fb(dev, fb, off - 4, off);
2483 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2484 if (amount != peek_fb(dev, fb, amount - 4))
2485 /* IC missing - disable the upper half memory space. */
2486 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2488 io_mapping_free(fb);
2493 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2496 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2498 * offset (8 bit): opcode
2500 * This opcode is meant to set the PFB memory config registers
2501 * appropriately so that we can correctly calculate how much VRAM it
2502 * has (on nv10 and better chipsets the amount of installed VRAM is
2503 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2505 * The implementation of this opcode in general consists of several
2508 * 1) Determination of memory type and density. Only necessary for
2509 * really old chipsets, the memory type reported by the strap bits
2510 * (0x101000) is assumed to be accurate on nv05 and newer.
2512 * 2) Determination of the memory bus width. Usually done by a cunning
2513 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2514 * seeing whether the written values are read back correctly.
2516 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2519 * 3) Determination of how many of the card's RAM pads have ICs
2520 * attached, usually done by a cunning combination of writes to an
2521 * offset slightly less than the maximum memory reported by
2522 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2524 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2525 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2526 * card show nothing being done for this opcode. Why is it still listed
2530 /* no iexec->execute check by design */
2532 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2535 if (dev_priv->chipset >= 0x40 ||
2536 dev_priv->chipset == 0x1a ||
2537 dev_priv->chipset == 0x1f)
2539 else if (dev_priv->chipset >= 0x20 &&
2540 dev_priv->chipset != 0x34)
2541 ret = nv20_init_compute_mem(bios);
2542 else if (dev_priv->chipset >= 0x10)
2543 ret = nv10_init_compute_mem(bios);
2544 else if (dev_priv->chipset >= 0x5)
2545 ret = nv05_init_compute_mem(bios);
2547 ret = nv04_init_compute_mem(bios);
2556 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2559 * INIT_RESET opcode: 0x65 ('e')
2561 * offset (8 bit): opcode
2562 * offset + 1 (32 bit): register
2563 * offset + 5 (32 bit): value1
2564 * offset + 9 (32 bit): value2
2566 * Assign "value1" to "register", then assign "value2" to "register"
2569 uint32_t reg = ROM32(bios->data[offset + 1]);
2570 uint32_t value1 = ROM32(bios->data[offset + 5]);
2571 uint32_t value2 = ROM32(bios->data[offset + 9]);
2572 uint32_t pci_nv_19, pci_nv_20;
2574 /* no iexec->execute check by design */
2576 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2577 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2579 bios_wr32(bios, reg, value1);
2583 bios_wr32(bios, reg, value2);
2584 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2586 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2587 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2588 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2594 init_configure_mem(struct nvbios *bios, uint16_t offset,
2595 struct init_exec *iexec)
2598 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2600 * offset (8 bit): opcode
2602 * Equivalent to INIT_DONE on bios version 3 or greater.
2603 * For early bios versions, sets up the memory registers, using values
2604 * taken from the memory init table
2607 /* no iexec->execute check by design */
2609 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2610 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2613 if (bios->major_version > 2)
2616 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2617 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2619 if (bios->data[meminitoffs] & 1)
2620 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2622 for (reg = ROM32(bios->data[seqtbloffs]);
2624 reg = ROM32(bios->data[seqtbloffs += 4])) {
2628 data = NV04_PFB_PRE_CMD_PRECHARGE;
2631 data = NV04_PFB_PAD_CKE_NORMAL;
2634 data = NV04_PFB_REF_CMD_REFRESH;
2637 data = ROM32(bios->data[meminitdata]);
2639 if (data == 0xffffffff)
2643 bios_wr32(bios, reg, data);
2650 init_configure_clk(struct nvbios *bios, uint16_t offset,
2651 struct init_exec *iexec)
2654 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2656 * offset (8 bit): opcode
2658 * Equivalent to INIT_DONE on bios version 3 or greater.
2659 * For early bios versions, sets up the NVClk and MClk PLLs, using
2660 * values taken from the memory init table
2663 /* no iexec->execute check by design */
2665 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2668 if (bios->major_version > 2)
2671 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2672 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2674 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2675 if (bios->data[meminitoffs] & 1) /* DDR */
2677 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2683 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2684 struct init_exec *iexec)
2687 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2689 * offset (8 bit): opcode
2691 * Equivalent to INIT_DONE on bios version 3 or greater.
2692 * For early bios versions, does early init, loading ram and crystal
2693 * configuration from straps into CR3C
2696 /* no iexec->execute check by design */
2698 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2699 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2701 if (bios->major_version > 2)
2704 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2705 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2711 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2714 * INIT_IO opcode: 0x69 ('i')
2716 * offset (8 bit): opcode
2717 * offset + 1 (16 bit): CRTC port
2718 * offset + 3 (8 bit): mask
2719 * offset + 4 (8 bit): data
2721 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2724 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2725 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2726 uint8_t mask = bios->data[offset + 3];
2727 uint8_t data = bios->data[offset + 4];
2729 if (!iexec->execute)
2732 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2733 offset, crtcport, mask, data);
2736 * I have no idea what this does, but NVIDIA do this magic sequence
2737 * in the places where this INIT_IO happens..
2739 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2742 bios_wr32(bios, 0x614100, (bios_rd32(
2743 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2745 bios_wr32(bios, 0x00e18c, bios_rd32(
2746 bios, 0x00e18c) | 0x00020000);
2748 bios_wr32(bios, 0x614900, (bios_rd32(
2749 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2751 bios_wr32(bios, 0x000200, bios_rd32(
2752 bios, 0x000200) & ~0x40000000);
2756 bios_wr32(bios, 0x00e18c, bios_rd32(
2757 bios, 0x00e18c) & ~0x00020000);
2759 bios_wr32(bios, 0x000200, bios_rd32(
2760 bios, 0x000200) | 0x40000000);
2762 bios_wr32(bios, 0x614100, 0x00800018);
2763 bios_wr32(bios, 0x614900, 0x00800018);
2767 bios_wr32(bios, 0x614100, 0x10000018);
2768 bios_wr32(bios, 0x614900, 0x10000018);
2770 for (i = 0; i < 3; i++)
2771 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2772 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2774 for (i = 0; i < 2; i++)
2775 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2776 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2778 for (i = 0; i < 3; i++)
2779 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2780 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2782 for (i = 0; i < 2; i++)
2783 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2784 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2786 for (i = 0; i < 2; i++)
2787 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2788 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2792 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2798 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2801 * INIT_SUB opcode: 0x6B ('k')
2803 * offset (8 bit): opcode
2804 * offset + 1 (8 bit): script number
2806 * Execute script number "script number", as a subroutine
2809 uint8_t sub = bios->data[offset + 1];
2811 if (!iexec->execute)
2814 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2816 parse_init_table(bios,
2817 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2820 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2826 init_ram_condition(struct nvbios *bios, uint16_t offset,
2827 struct init_exec *iexec)
2830 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2832 * offset (8 bit): opcode
2833 * offset + 1 (8 bit): mask
2834 * offset + 2 (8 bit): cmpval
2836 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2837 * If condition not met skip subsequent opcodes until condition is
2838 * inverted (INIT_NOT), or we hit INIT_RESUME
2841 uint8_t mask = bios->data[offset + 1];
2842 uint8_t cmpval = bios->data[offset + 2];
2845 if (!iexec->execute)
2848 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2850 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2851 offset, data, cmpval);
2854 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2856 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2857 iexec->execute = false;
2864 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2867 * INIT_NV_REG opcode: 0x6E ('n')
2869 * offset (8 bit): opcode
2870 * offset + 1 (32 bit): register
2871 * offset + 5 (32 bit): mask
2872 * offset + 9 (32 bit): data
2874 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2877 uint32_t reg = ROM32(bios->data[offset + 1]);
2878 uint32_t mask = ROM32(bios->data[offset + 5]);
2879 uint32_t data = ROM32(bios->data[offset + 9]);
2881 if (!iexec->execute)
2884 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2885 offset, reg, mask, data);
2887 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2893 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2896 * INIT_MACRO opcode: 0x6F ('o')
2898 * offset (8 bit): opcode
2899 * offset + 1 (8 bit): macro number
2901 * Look up macro index "macro number" in the macro index table.
2902 * The macro index table entry has 1 byte for the index in the macro
2903 * table, and 1 byte for the number of times to repeat the macro.
2904 * The macro table entry has 4 bytes for the register address and
2905 * 4 bytes for the value to write to that register
2908 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2909 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2910 uint8_t macro_tbl_idx = bios->data[tmp];
2911 uint8_t count = bios->data[tmp + 1];
2915 if (!iexec->execute)
2918 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2920 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2922 for (i = 0; i < count; i++) {
2923 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2925 reg = ROM32(bios->data[macroentryptr]);
2926 data = ROM32(bios->data[macroentryptr + 4]);
2928 bios_wr32(bios, reg, data);
2935 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2938 * INIT_DONE opcode: 0x71 ('q')
2940 * offset (8 bit): opcode
2942 * End the current script
2945 /* mild retval abuse to stop parsing this table */
2950 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2953 * INIT_RESUME opcode: 0x72 ('r')
2955 * offset (8 bit): opcode
2957 * End the current execute / no-execute condition
2963 iexec->execute = true;
2964 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2970 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2973 * INIT_TIME opcode: 0x74 ('t')
2975 * offset (8 bit): opcode
2976 * offset + 1 (16 bit): time
2978 * Sleep for "time" microseconds.
2981 unsigned time = ROM16(bios->data[offset + 1]);
2983 if (!iexec->execute)
2986 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2992 mdelay((time + 900) / 1000);
2998 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3001 * INIT_CONDITION opcode: 0x75 ('u')
3003 * offset (8 bit): opcode
3004 * offset + 1 (8 bit): condition number
3006 * Check condition "condition number" in the condition table.
3007 * If condition not met skip subsequent opcodes until condition is
3008 * inverted (INIT_NOT), or we hit INIT_RESUME
3011 uint8_t cond = bios->data[offset + 1];
3013 if (!iexec->execute)
3016 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
3018 if (bios_condition_met(bios, offset, cond))
3019 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3021 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3022 iexec->execute = false;
3029 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3032 * INIT_IO_CONDITION opcode: 0x76
3034 * offset (8 bit): opcode
3035 * offset + 1 (8 bit): condition number
3037 * Check condition "condition number" in the io condition table.
3038 * If condition not met skip subsequent opcodes until condition is
3039 * inverted (INIT_NOT), or we hit INIT_RESUME
3042 uint8_t cond = bios->data[offset + 1];
3044 if (!iexec->execute)
3047 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
3049 if (io_condition_met(bios, offset, cond))
3050 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3052 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3053 iexec->execute = false;
3060 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3063 * INIT_INDEX_IO opcode: 0x78 ('x')
3065 * offset (8 bit): opcode
3066 * offset + 1 (16 bit): CRTC port
3067 * offset + 3 (8 bit): CRTC index
3068 * offset + 4 (8 bit): mask
3069 * offset + 5 (8 bit): data
3071 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3072 * OR with "data", write-back
3075 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3076 uint8_t crtcindex = bios->data[offset + 3];
3077 uint8_t mask = bios->data[offset + 4];
3078 uint8_t data = bios->data[offset + 5];
3081 if (!iexec->execute)
3084 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3086 offset, crtcport, crtcindex, mask, data);
3088 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3089 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3095 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3098 * INIT_PLL opcode: 0x79 ('y')
3100 * offset (8 bit): opcode
3101 * offset + 1 (32 bit): register
3102 * offset + 5 (16 bit): freq
3104 * Set PLL register "register" to coefficients for frequency (10kHz)
3108 uint32_t reg = ROM32(bios->data[offset + 1]);
3109 uint16_t freq = ROM16(bios->data[offset + 5]);
3111 if (!iexec->execute)
3114 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3116 setPLL(bios, reg, freq * 10);
3122 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3125 * INIT_ZM_REG opcode: 0x7A ('z')
3127 * offset (8 bit): opcode
3128 * offset + 1 (32 bit): register
3129 * offset + 5 (32 bit): value
3131 * Assign "value" to "register"
3134 uint32_t reg = ROM32(bios->data[offset + 1]);
3135 uint32_t value = ROM32(bios->data[offset + 5]);
3137 if (!iexec->execute)
3140 if (reg == 0x000200)
3143 bios_wr32(bios, reg, value);
3149 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3150 struct init_exec *iexec)
3153 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3155 * offset (8 bit): opcode
3156 * offset + 1 (8 bit): PLL type
3157 * offset + 2 (32 bit): frequency 0
3159 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3160 * ram_restrict_table_ptr. The value read from there is used to select
3161 * a frequency from the table starting at 'frequency 0' to be
3162 * programmed into the PLL corresponding to 'type'.
3164 * The PLL limits table on cards using this opcode has a mapping of
3165 * 'type' to the relevant registers.
3168 struct drm_device *dev = bios->dev;
3169 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3170 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3171 uint8_t type = bios->data[offset + 1];
3172 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3173 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
3174 int len = 2 + bios->ram_restrict_group_count * 4;
3177 if (!iexec->execute)
3180 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3181 NV_ERROR(dev, "PLL limits table not version 3.x\n");
3182 return len; /* deliberate, allow default clocks to remain */
3185 entry = pll_limits + pll_limits[1];
3186 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3187 if (entry[0] == type) {
3188 uint32_t reg = ROM32(entry[3]);
3190 BIOSLOG(bios, "0x%04X: "
3191 "Type %02x Reg 0x%08x Freq %dKHz\n",
3192 offset, type, reg, freq);
3194 setPLL(bios, reg, freq);
3199 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
3204 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3207 * INIT_8C opcode: 0x8C ('')
3217 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3220 * INIT_8D opcode: 0x8D ('')
3230 init_gpio_unknv50(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3232 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3235 /* Not a clue, needs de-magicing */
3236 r = nv50_gpio_ctl[gpio->line >> 4];
3237 s = (gpio->line & 0x0f);
3238 v = bios_rd32(bios, r) & ~(0x00010001 << s);
3239 switch ((gpio->entry & 0x06000000) >> 25) {
3241 v |= (0x00000001 << s);
3244 v |= (0x00010000 << s);
3250 bios_wr32(bios, r, v);
3254 init_gpio_unknvd0(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3258 v = bios_rd32(bios, 0x00d610 + (gpio->line * 4));
3260 v |= (gpio->entry & 0x00ff0000) >> 16;
3261 bios_wr32(bios, 0x00d610 + (gpio->line * 4), v);
3263 i = (gpio->entry & 0x1f000000) >> 24;
3265 v = bios_rd32(bios, 0x00d640 + ((i - 1) * 4));
3268 bios_wr32(bios, 0x00d640 + ((i - 1) * 4), v);
3273 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3276 * INIT_GPIO opcode: 0x8E ('')
3278 * offset (8 bit): opcode
3280 * Loop over all entries in the DCB GPIO table, and initialise
3281 * each GPIO according to various values listed in each entry
3284 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
3285 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
3288 if (dev_priv->card_type < NV_50) {
3289 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
3293 if (!iexec->execute)
3296 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3297 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
3299 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
3301 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3302 offset, gpio->tag, gpio->state_default);
3307 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
3308 if (dev_priv->card_type < NV_D0)
3309 init_gpio_unknv50(bios, gpio);
3311 init_gpio_unknvd0(bios, gpio);
3318 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3319 struct init_exec *iexec)
3322 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3324 * offset (8 bit): opcode
3325 * offset + 1 (32 bit): reg
3326 * offset + 5 (8 bit): regincrement
3327 * offset + 6 (8 bit): count
3328 * offset + 7 (32 bit): value 1,1
3331 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3332 * ram_restrict_table_ptr. The value read from here is 'n', and
3333 * "value 1,n" gets written to "reg". This repeats "count" times and on
3334 * each iteration 'm', "reg" increases by "regincrement" and
3335 * "value m,n" is used. The extent of n is limited by a number read
3336 * from the 'M' BIT table, herein called "blocklen"
3339 uint32_t reg = ROM32(bios->data[offset + 1]);
3340 uint8_t regincrement = bios->data[offset + 5];
3341 uint8_t count = bios->data[offset + 6];
3342 uint32_t strap_ramcfg, data;
3343 /* previously set by 'M' BIT table */
3344 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3345 int len = 7 + count * blocklen;
3349 /* critical! to know the length of the opcode */;
3352 "0x%04X: Zero block length - has the M table "
3353 "been parsed?\n", offset);
3357 if (!iexec->execute)
3360 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3361 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3363 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3364 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3365 offset, reg, regincrement, count, strap_ramcfg, index);
3367 for (i = 0; i < count; i++) {
3368 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3370 bios_wr32(bios, reg, data);
3372 reg += regincrement;
3379 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3382 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3384 * offset (8 bit): opcode
3385 * offset + 1 (32 bit): src reg
3386 * offset + 5 (32 bit): dst reg
3388 * Put contents of "src reg" into "dst reg"
3391 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3392 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3394 if (!iexec->execute)
3397 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3403 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3404 struct init_exec *iexec)
3407 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3409 * offset (8 bit): opcode
3410 * offset + 1 (32 bit): dst reg
3411 * offset + 5 (8 bit): count
3412 * offset + 6 (32 bit): data 1
3415 * For each of "count" values write "data n" to "dst reg"
3418 uint32_t reg = ROM32(bios->data[offset + 1]);
3419 uint8_t count = bios->data[offset + 5];
3420 int len = 6 + count * 4;
3423 if (!iexec->execute)
3426 for (i = 0; i < count; i++) {
3427 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3428 bios_wr32(bios, reg, data);
3435 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3438 * INIT_RESERVED opcode: 0x92 ('')
3440 * offset (8 bit): opcode
3442 * Seemingly does nothing
3449 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3452 * INIT_96 opcode: 0x96 ('')
3454 * offset (8 bit): opcode
3455 * offset + 1 (32 bit): sreg
3456 * offset + 5 (8 bit): sshift
3457 * offset + 6 (8 bit): smask
3458 * offset + 7 (8 bit): index
3459 * offset + 8 (32 bit): reg
3460 * offset + 12 (32 bit): mask
3461 * offset + 16 (8 bit): shift
3465 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3466 uint32_t reg = ROM32(bios->data[offset + 8]);
3467 uint32_t mask = ROM32(bios->data[offset + 12]);
3470 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3471 if (bios->data[offset + 5] < 0x80)
3472 val >>= bios->data[offset + 5];
3474 val <<= (0x100 - bios->data[offset + 5]);
3475 val &= bios->data[offset + 6];
3477 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3478 val <<= bios->data[offset + 16];
3480 if (!iexec->execute)
3483 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3488 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3491 * INIT_97 opcode: 0x97 ('')
3493 * offset (8 bit): opcode
3494 * offset + 1 (32 bit): register
3495 * offset + 5 (32 bit): mask
3496 * offset + 9 (32 bit): value
3498 * Adds "value" to "register" preserving the fields specified
3502 uint32_t reg = ROM32(bios->data[offset + 1]);
3503 uint32_t mask = ROM32(bios->data[offset + 5]);
3504 uint32_t add = ROM32(bios->data[offset + 9]);
3507 val = bios_rd32(bios, reg);
3508 val = (val & mask) | ((val + add) & ~mask);
3510 if (!iexec->execute)
3513 bios_wr32(bios, reg, val);
3518 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3521 * INIT_AUXCH opcode: 0x98 ('')
3523 * offset (8 bit): opcode
3524 * offset + 1 (32 bit): address
3525 * offset + 5 (8 bit): count
3526 * offset + 6 (8 bit): mask 0
3527 * offset + 7 (8 bit): data 0
3532 struct drm_device *dev = bios->dev;
3533 struct nouveau_i2c_chan *auxch;
3534 uint32_t addr = ROM32(bios->data[offset + 1]);
3535 uint8_t count = bios->data[offset + 5];
3536 int len = 6 + count * 2;
3539 if (!bios->display.output) {
3540 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3544 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3546 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3547 bios->display.output->i2c_index);
3551 if (!iexec->execute)
3555 for (i = 0; i < count; i++, offset += 2) {
3558 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3560 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3564 data &= bios->data[offset + 0];
3565 data |= bios->data[offset + 1];
3567 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3569 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3578 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3581 * INIT_ZM_AUXCH opcode: 0x99 ('')
3583 * offset (8 bit): opcode
3584 * offset + 1 (32 bit): address
3585 * offset + 5 (8 bit): count
3586 * offset + 6 (8 bit): data 0
3591 struct drm_device *dev = bios->dev;
3592 struct nouveau_i2c_chan *auxch;
3593 uint32_t addr = ROM32(bios->data[offset + 1]);
3594 uint8_t count = bios->data[offset + 5];
3595 int len = 6 + count;
3598 if (!bios->display.output) {
3599 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3603 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3605 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3606 bios->display.output->i2c_index);
3610 if (!iexec->execute)
3614 for (i = 0; i < count; i++, offset++) {
3615 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3617 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3626 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3629 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3631 * offset (8 bit): opcode
3632 * offset + 1 (8 bit): DCB I2C table entry index
3633 * offset + 2 (8 bit): I2C slave address
3634 * offset + 3 (16 bit): I2C register
3635 * offset + 5 (8 bit): mask
3636 * offset + 6 (8 bit): data
3638 * Read the register given by "I2C register" on the device addressed
3639 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3640 * entry index". Compare the result AND "mask" to "data".
3641 * If they're not equal, skip subsequent opcodes until condition is
3642 * inverted (INIT_NOT), or we hit INIT_RESUME
3645 uint8_t i2c_index = bios->data[offset + 1];
3646 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3647 uint8_t reglo = bios->data[offset + 3];
3648 uint8_t reghi = bios->data[offset + 4];
3649 uint8_t mask = bios->data[offset + 5];
3650 uint8_t data = bios->data[offset + 6];
3651 struct nouveau_i2c_chan *chan;
3652 uint8_t buf0[2] = { reghi, reglo };
3654 struct i2c_msg msg[2] = {
3655 { i2c_address, 0, 1, buf0 },
3656 { i2c_address, I2C_M_RD, 1, buf1 },
3660 /* no execute check by design */
3662 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3663 offset, i2c_index, i2c_address);
3665 chan = init_i2c_device_find(bios->dev, i2c_index);
3670 ret = i2c_transfer(&chan->adapter, msg, 2);
3672 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3673 "Mask: 0x%02X, Data: 0x%02X\n",
3674 offset, reghi, reglo, mask, data);
3679 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3680 "Mask: 0x%02X, Data: 0x%02X\n",
3681 offset, reghi, reglo, buf1[0], mask, data);
3683 iexec->execute = ((buf1[0] & mask) == data);
3688 static struct init_tbl_entry itbl_entry[] = {
3689 /* command name , id , length , offset , mult , command handler */
3690 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3691 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3692 { "INIT_REPEAT" , 0x33, init_repeat },
3693 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3694 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3695 { "INIT_COPY" , 0x37, init_copy },
3696 { "INIT_NOT" , 0x38, init_not },
3697 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3698 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3699 { "INIT_OP_3B" , 0x3B, init_op_3b },
3700 { "INIT_OP_3C" , 0x3C, init_op_3c },
3701 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3702 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3703 { "INIT_PLL2" , 0x4B, init_pll2 },
3704 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3705 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3706 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3707 { "INIT_TMDS" , 0x4F, init_tmds },
3708 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3709 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3710 { "INIT_CR" , 0x52, init_cr },
3711 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3712 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3713 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3714 { "INIT_LTIME" , 0x57, init_ltime },
3715 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3716 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3717 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3718 { "INIT_JUMP" , 0x5C, init_jump },
3719 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3720 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3721 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3722 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3723 { "INIT_RESET" , 0x65, init_reset },
3724 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3725 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3726 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3727 { "INIT_IO" , 0x69, init_io },
3728 { "INIT_SUB" , 0x6B, init_sub },
3729 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3730 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3731 { "INIT_MACRO" , 0x6F, init_macro },
3732 { "INIT_DONE" , 0x71, init_done },
3733 { "INIT_RESUME" , 0x72, init_resume },
3734 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3735 { "INIT_TIME" , 0x74, init_time },
3736 { "INIT_CONDITION" , 0x75, init_condition },
3737 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3738 { "INIT_INDEX_IO" , 0x78, init_index_io },
3739 { "INIT_PLL" , 0x79, init_pll },
3740 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3741 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3742 { "INIT_8C" , 0x8C, init_8c },
3743 { "INIT_8D" , 0x8D, init_8d },
3744 { "INIT_GPIO" , 0x8E, init_gpio },
3745 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3746 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3747 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3748 { "INIT_RESERVED" , 0x92, init_reserved },
3749 { "INIT_96" , 0x96, init_96 },
3750 { "INIT_97" , 0x97, init_97 },
3751 { "INIT_AUXCH" , 0x98, init_auxch },
3752 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3753 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3757 #define MAX_TABLE_OPS 1000
3760 parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3763 * Parses all commands in an init table.
3765 * We start out executing all commands found in the init table. Some
3766 * opcodes may change the status of iexec->execute to SKIP, which will
3767 * cause the following opcodes to perform no operation until the value
3768 * is changed back to EXECUTE.
3771 int count = 0, i, ret;
3775 * Loop until INIT_DONE causes us to break out of the loop
3776 * (or until offset > bios length just in case... )
3777 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3779 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3780 id = bios->data[offset];
3782 /* Find matching id in itbl_entry */
3783 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3786 if (!itbl_entry[i].name) {
3788 "0x%04X: Init table command not found: "
3789 "0x%02X\n", offset, id);
3793 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3794 itbl_entry[i].id, itbl_entry[i].name);
3796 /* execute eventual command handler */
3797 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3799 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3800 "table opcode: %s %d\n", offset,
3801 itbl_entry[i].name, ret);
3808 * Add the offset of the current command including all data
3809 * of that command. The offset will then be pointing on the
3815 if (offset >= bios->length)
3817 "Offset 0x%04X greater than known bios image length. "
3818 "Corrupt image?\n", offset);
3819 if (count >= MAX_TABLE_OPS)
3821 "More than %d opcodes to a table is unlikely, "
3822 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3828 parse_init_tables(struct nvbios *bios)
3830 /* Loops and calls parse_init_table() for each present table. */
3834 struct init_exec iexec = {true, false};
3836 if (bios->old_style_init) {
3837 if (bios->init_script_tbls_ptr)
3838 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3839 if (bios->extra_init_script_tbl_ptr)
3840 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3845 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3847 "Parsing VBIOS init table %d at offset 0x%04X\n",
3849 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3851 parse_init_table(bios, table, &iexec);
3856 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3858 int compare_record_len, i = 0;
3859 uint16_t compareclk, scriptptr = 0;
3861 if (bios->major_version < 5) /* pre BIT */
3862 compare_record_len = 3;
3864 compare_record_len = 4;
3867 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3868 if (pxclk >= compareclk * 10) {
3869 if (bios->major_version < 5) {
3870 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3871 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3873 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3877 } while (compareclk);
3883 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3884 struct dcb_entry *dcbent, int head, bool dl)
3886 struct drm_nouveau_private *dev_priv = dev->dev_private;
3887 struct nvbios *bios = &dev_priv->vbios;
3888 struct init_exec iexec = {true, false};
3890 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3892 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3893 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3894 /* note: if dcb entries have been merged, index may be misleading */
3895 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3896 parse_init_table(bios, scriptptr, &iexec);
3898 nv04_dfp_bind_head(dev, dcbent, head, dl);
3901 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3903 struct drm_nouveau_private *dev_priv = dev->dev_private;
3904 struct nvbios *bios = &dev_priv->vbios;
3905 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3906 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3908 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3911 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3913 if (script == LVDS_PANEL_OFF) {
3914 /* off-on delay in ms */
3915 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3918 /* Powerbook specific quirks */
3919 if (script == LVDS_RESET &&
3920 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3921 dev->pci_device == 0x0329))
3922 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3928 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3931 * The BIT LVDS table's header has the information to setup the
3932 * necessary registers. Following the standard 4 byte header are:
3933 * A bitmask byte and a dual-link transition pxclk value for use in
3934 * selecting the init script when not using straps; 4 script pointers
3935 * for panel power, selected by output and on/off; and 8 table pointers
3936 * for panel init, the needed one determined by output, and bits in the
3937 * conf byte. These tables are similar to the TMDS tables, consisting
3938 * of a list of pxclks and script pointers.
3940 struct drm_nouveau_private *dev_priv = dev->dev_private;
3941 struct nvbios *bios = &dev_priv->vbios;
3942 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3943 uint16_t scriptptr = 0, clktable;
3946 * For now we assume version 3.0 table - g80 support will need some
3953 case LVDS_BACKLIGHT_ON:
3955 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3957 case LVDS_BACKLIGHT_OFF:
3958 case LVDS_PANEL_OFF:
3959 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3962 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3963 if (dcbent->or == 4)
3966 if (dcbent->lvdsconf.use_straps_for_mode) {
3967 if (bios->fp.dual_link)
3969 if (bios->fp.if_is_24bit)
3973 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3975 if (bios->fp.dual_link) {
3980 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3984 clktable = ROM16(bios->data[clktable]);
3986 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3989 scriptptr = clkcmptable(bios, clktable, pxclk);
3993 NV_ERROR(dev, "LVDS output init script not found\n");
3996 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
4001 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
4004 * LVDS operations are multiplexed in an effort to present a single API
4005 * which works with two vastly differing underlying structures.
4006 * This acts as the demux
4009 struct drm_nouveau_private *dev_priv = dev->dev_private;
4010 struct nvbios *bios = &dev_priv->vbios;
4011 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4012 uint32_t sel_clk_binding, sel_clk;
4015 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
4016 (lvds_ver >= 0x30 && script == LVDS_INIT))
4019 if (!bios->fp.lvds_init_run) {
4020 bios->fp.lvds_init_run = true;
4021 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
4024 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
4025 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
4026 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
4027 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
4029 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
4031 /* don't let script change pll->head binding */
4032 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4034 if (lvds_ver < 0x30)
4035 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
4037 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
4039 bios->fp.last_script_invoc = (script << 1 | head);
4041 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4042 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4043 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
4044 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
4049 struct lvdstableheader {
4050 uint8_t lvds_ver, headerlen, recordlen;
4053 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
4056 * BMP version (0xa) LVDS table has a simple header of version and
4057 * record length. The BIT LVDS table has the typical BIT table header:
4058 * version byte, header length byte, record length byte, and a byte for
4059 * the maximum number of records that can be held in the table.
4062 uint8_t lvds_ver, headerlen, recordlen;
4064 memset(lth, 0, sizeof(struct lvdstableheader));
4066 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
4067 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
4071 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4074 case 0x0a: /* pre NV40 */
4076 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4078 case 0x30: /* NV4x */
4079 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4080 if (headerlen < 0x1f) {
4081 NV_ERROR(dev, "LVDS table header not understood\n");
4084 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4086 case 0x40: /* G80/G90 */
4087 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4088 if (headerlen < 0x7) {
4089 NV_ERROR(dev, "LVDS table header not understood\n");
4092 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4096 "LVDS table revision %d.%d not currently supported\n",
4097 lvds_ver >> 4, lvds_ver & 0xf);
4101 lth->lvds_ver = lvds_ver;
4102 lth->headerlen = headerlen;
4103 lth->recordlen = recordlen;
4109 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4111 struct drm_nouveau_private *dev_priv = dev->dev_private;
4114 * The fp strap is normally dictated by the "User Strap" in
4115 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4116 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4117 * by the PCI subsystem ID during POST, but not before the previous user
4118 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4119 * read and used instead
4122 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4123 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4125 if (dev_priv->card_type >= NV_50)
4126 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4128 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4131 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4134 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4135 int ret, ofs, fpstrapping;
4136 struct lvdstableheader lth;
4138 if (bios->fp.fptablepointer == 0x0) {
4139 /* Apple cards don't have the fp table; the laptops use DDC */
4140 /* The table is also missing on some x86 IGPs */
4142 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4144 bios->digital_min_front_porch = 0x4b;
4148 fptable = &bios->data[bios->fp.fptablepointer];
4149 fptable_ver = fptable[0];
4151 switch (fptable_ver) {
4153 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4154 * version field, and miss one of the spread spectrum/PWM bytes.
4155 * This could affect early GF2Go parts (not seen any appropriate ROMs
4156 * though). Here we assume that a version of 0x05 matches this case
4157 * (combining with a BMP version check would be better), as the
4158 * common case for the panel type field is 0x0005, and that is in
4159 * fact what we are reading the first byte of.
4161 case 0x05: /* some NV10, 11, 15, 16 */
4165 case 0x10: /* some NV15/16, and NV11+ */
4169 case 0x20: /* NV40+ */
4170 headerlen = fptable[1];
4171 recordlen = fptable[2];
4172 fpentries = fptable[3];
4174 * fptable[4] is the minimum
4175 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4177 bios->digital_min_front_porch = fptable[4];
4182 "FP table revision %d.%d not currently supported\n",
4183 fptable_ver >> 4, fptable_ver & 0xf);
4187 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4190 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4194 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4195 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4197 bios->fp.xlatwidth = lth.recordlen;
4199 if (bios->fp.fpxlatetableptr == 0x0) {
4200 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4204 fpstrapping = get_fp_strap(dev, bios);
4206 fpindex = bios->data[bios->fp.fpxlatetableptr +
4207 fpstrapping * bios->fp.xlatwidth];
4209 if (fpindex > fpentries) {
4210 NV_ERROR(dev, "Bad flat panel table index\n");
4214 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4215 if (lth.lvds_ver > 0x10)
4216 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
4219 * If either the strap or xlated fpindex value are 0xf there is no
4220 * panel using a strap-derived bios mode present. this condition
4221 * includes, but is different from, the DDC panel indicator above
4223 if (fpstrapping == 0xf || fpindex == 0xf)
4226 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4227 recordlen * fpindex + ofs;
4229 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4230 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4231 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4232 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4237 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4239 struct drm_nouveau_private *dev_priv = dev->dev_private;
4240 struct nvbios *bios = &dev_priv->vbios;
4241 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4243 if (!mode) /* just checking whether we can produce a mode */
4244 return bios->fp.mode_ptr;
4246 memset(mode, 0, sizeof(struct drm_display_mode));
4248 * For version 1.0 (version in byte 0):
4249 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4250 * single/dual link, and type (TFT etc.)
4251 * bytes 3-6 are bits per colour in RGBX
4253 mode->clock = ROM16(mode_entry[7]) * 10;
4254 /* bytes 9-10 is HActive */
4255 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4257 * bytes 13-14 is HValid Start
4258 * bytes 15-16 is HValid End
4260 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4261 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4262 mode->htotal = ROM16(mode_entry[21]) + 1;
4263 /* bytes 23-24, 27-30 similarly, but vertical */
4264 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4265 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4266 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4267 mode->vtotal = ROM16(mode_entry[35]) + 1;
4268 mode->flags |= (mode_entry[37] & 0x10) ?
4269 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4270 mode->flags |= (mode_entry[37] & 0x1) ?
4271 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4273 * bytes 38-39 relate to spread spectrum settings
4274 * bytes 40-43 are something to do with PWM
4277 mode->status = MODE_OK;
4278 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4279 drm_mode_set_name(mode);
4280 return bios->fp.mode_ptr;
4283 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4286 * The LVDS table header is (mostly) described in
4287 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4288 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4289 * straps are not being used for the panel, this specifies the frequency
4290 * at which modes should be set up in the dual link style.
4292 * Following the header, the BMP (ver 0xa) table has several records,
4293 * indexed by a separate xlat table, indexed in turn by the fp strap in
4294 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4295 * numbers for use by INIT_SUB which controlled panel init and power,
4296 * and finally a dword of ms to sleep between power off and on
4299 * In the BIT versions, the table following the header serves as an
4300 * integrated config and xlat table: the records in the table are
4301 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4302 * two bytes - the first as a config byte, the second for indexing the
4303 * fp mode table pointed to by the BIT 'D' table
4305 * DDC is not used until after card init, so selecting the correct table
4306 * entry and setting the dual link flag for EDID equipped panels,
4307 * requiring tests against the native-mode pixel clock, cannot be done
4308 * until later, when this function should be called with non-zero pxclk
4310 struct drm_nouveau_private *dev_priv = dev->dev_private;
4311 struct nvbios *bios = &dev_priv->vbios;
4312 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4313 struct lvdstableheader lth;
4315 int ret, chip_version = bios->chip_version;
4317 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4321 switch (lth.lvds_ver) {
4322 case 0x0a: /* pre NV40 */
4323 lvdsmanufacturerindex = bios->data[
4324 bios->fp.fpxlatemanufacturertableptr +
4327 /* we're done if this isn't the EDID panel case */
4331 if (chip_version < 0x25) {
4334 * It seems the old style lvds script pointer is reused
4335 * to select 18/24 bit colour depth for EDID panels.
4337 lvdsmanufacturerindex =
4338 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4340 if (pxclk >= bios->fp.duallink_transition_clk)
4341 lvdsmanufacturerindex++;
4342 } else if (chip_version < 0x30) {
4343 /* nv28 behaviour (off-chip encoder)
4345 * nv28 does a complex dance of first using byte 121 of
4346 * the EDID to choose the lvdsmanufacturerindex, then
4347 * later attempting to match the EDID manufacturer and
4348 * product IDs in a table (signature 'pidt' (panel id
4349 * table?)), setting an lvdsmanufacturerindex of 0 and
4350 * an fp strap of the match index (or 0xf if none)
4352 lvdsmanufacturerindex = 0;
4354 /* nv31, nv34 behaviour */
4355 lvdsmanufacturerindex = 0;
4356 if (pxclk >= bios->fp.duallink_transition_clk)
4357 lvdsmanufacturerindex = 2;
4358 if (pxclk >= 140000)
4359 lvdsmanufacturerindex = 3;
4363 * nvidia set the high nibble of (cr57=f, cr58) to
4364 * lvdsmanufacturerindex in this case; we don't
4367 case 0x30: /* NV4x */
4368 case 0x40: /* G80/G90 */
4369 lvdsmanufacturerindex = fpstrapping;
4372 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4376 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4377 switch (lth.lvds_ver) {
4379 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4380 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4381 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4382 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4383 *if_is_24bit = bios->data[lvdsofs] & 16;
4388 * No sign of the "power off for reset" or "reset for panel
4389 * on" bits, but it's safer to assume we should
4391 bios->fp.power_off_for_reset = true;
4392 bios->fp.reset_after_pclk_change = true;
4395 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4396 * over-written, and if_is_24bit isn't used
4398 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4399 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4400 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4401 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4405 /* Dell Latitude D620 reports a too-high value for the dual-link
4406 * transition freq, causing us to program the panel incorrectly.
4408 * It doesn't appear the VBIOS actually uses its transition freq
4409 * (90000kHz), instead it uses the "Number of LVDS channels" field
4410 * out of the panel ID structure (http://www.spwg.org/).
4412 * For the moment, a quirk will do :)
4414 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
4415 bios->fp.duallink_transition_clk = 80000;
4417 /* set dual_link flag for EDID case */
4418 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4419 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4421 *dl = bios->fp.dual_link;
4427 bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
4428 uint16_t record, int record_len, int record_nr,
4431 struct drm_nouveau_private *dev_priv = dev->dev_private;
4432 struct nvbios *bios = &dev_priv->vbios;
4437 switch (dcbent->type) {
4447 for (i = 0; i < record_nr; i++, record += record_len) {
4448 table = ROM16(bios->data[record]);
4451 entry = ROM32(bios->data[table]);
4454 v = (entry & 0x00c00000) >> 22;
4455 if (!(v & dcbent->sorconf.link))
4459 v = (entry & 0x000f0000) >> 16;
4460 if (!(v & dcbent->or))
4463 v = (entry & 0x000000f0) >> 4;
4464 if (v != dcbent->location)
4467 v = (entry & 0x0000000f);
4468 if (v != dcbent->type)
4471 return &bios->data[table];
4478 nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
4481 struct drm_nouveau_private *dev_priv = dev->dev_private;
4482 struct nvbios *bios = &dev_priv->vbios;
4485 if (!bios->display.dp_table_ptr) {
4486 NV_ERROR(dev, "No pointer to DisplayPort table\n");
4489 table = &bios->data[bios->display.dp_table_ptr];
4491 if (table[0] != 0x20 && table[0] != 0x21) {
4492 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
4498 return bios_output_config_match(dev, dcbent,
4499 bios->display.dp_table_ptr + table[1],
4500 table[2], table[3], table[0] >= 0x21);
4504 nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4505 struct dcb_entry *dcbent, int crtc)
4508 * The display script table is located by the BIT 'U' table.
4510 * It contains an array of pointers to various tables describing
4511 * a particular output type. The first 32-bits of the output
4512 * tables contains similar information to a DCB entry, and is
4513 * used to decide whether that particular table is suitable for
4514 * the output you want to access.
4516 * The "record header length" field here seems to indicate the
4517 * offset of the first configuration entry in the output tables.
4518 * This is 10 on most cards I've seen, but 12 has been witnessed
4519 * on DP cards, and there's another script pointer within the
4522 * offset + 0 ( 8 bits): version
4523 * offset + 1 ( 8 bits): header length
4524 * offset + 2 ( 8 bits): record length
4525 * offset + 3 ( 8 bits): number of records
4526 * offset + 4 ( 8 bits): record header length
4527 * offset + 5 (16 bits): pointer to first output script table
4530 struct drm_nouveau_private *dev_priv = dev->dev_private;
4531 struct nvbios *bios = &dev_priv->vbios;
4532 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4533 uint8_t *otable = NULL;
4537 if (!bios->display.script_table_ptr) {
4538 NV_ERROR(dev, "No pointer to output script table\n");
4543 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4544 * so until they are, we really don't need to care.
4546 if (table[0] < 0x20)
4549 if (table[0] != 0x20 && table[0] != 0x21) {
4550 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4556 * The output script tables describing a particular output type
4559 * offset + 0 (32 bits): output this table matches (hash of DCB)
4560 * offset + 4 ( 8 bits): unknown
4561 * offset + 5 ( 8 bits): number of configurations
4562 * offset + 6 (16 bits): pointer to some script
4563 * offset + 8 (16 bits): pointer to some script
4566 * offset + 10 : configuration 0
4569 * offset + 10 : pointer to some script
4570 * offset + 12 : configuration 0
4572 * Each config entry is as follows:
4574 * offset + 0 (16 bits): unknown, assumed to be a match value
4575 * offset + 2 (16 bits): pointer to script table (clock set?)
4576 * offset + 4 (16 bits): pointer to script table (reset?)
4578 * There doesn't appear to be a count value to say how many
4579 * entries exist in each script table, instead, a 0 value in
4580 * the first 16-bit word seems to indicate both the end of the
4581 * list and the default entry. The second 16-bit word in the
4582 * script tables is a pointer to the script to execute.
4585 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4586 dcbent->type, dcbent->location, dcbent->or);
4587 otable = bios_output_config_match(dev, dcbent, table[1] +
4588 bios->display.script_table_ptr,
4589 table[2], table[3], table[0] >= 0x21);
4591 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4595 if (pclk < -2 || pclk > 0) {
4596 /* Try to find matching script table entry */
4597 for (i = 0; i < otable[5]; i++) {
4598 if (ROM16(otable[table[4] + i*6]) == type)
4602 if (i == otable[5]) {
4603 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4605 type, dcbent->type, dcbent->or);
4611 script = ROM16(otable[6]);
4613 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4617 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4618 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4621 script = ROM16(otable[8]);
4623 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4627 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4628 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4632 script = ROM16(otable[10]);
4636 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4640 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4641 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4644 script = ROM16(otable[table[4] + i*6 + 2]);
4646 script = clkcmptable(bios, script, pclk);
4648 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4652 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4653 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4656 script = ROM16(otable[table[4] + i*6 + 4]);
4658 script = clkcmptable(bios, script, -pclk);
4660 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4664 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4665 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4672 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4675 * the pxclk parameter is in kHz
4677 * This runs the TMDS regs setting code found on BIT bios cards
4679 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4680 * ffs(or) == 3, use the second.
4683 struct drm_nouveau_private *dev_priv = dev->dev_private;
4684 struct nvbios *bios = &dev_priv->vbios;
4685 int cv = bios->chip_version;
4686 uint16_t clktable = 0, scriptptr;
4687 uint32_t sel_clk_binding, sel_clk;
4689 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4690 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4691 dcbent->location != DCB_LOC_ON_CHIP)
4694 switch (ffs(dcbent->or)) {
4696 clktable = bios->tmds.output0_script_ptr;
4700 clktable = bios->tmds.output1_script_ptr;
4705 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4709 scriptptr = clkcmptable(bios, clktable, pxclk);
4712 NV_ERROR(dev, "TMDS output init script not found\n");
4716 /* don't let script change pll->head binding */
4717 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4718 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4719 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4720 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4725 struct pll_mapping {
4730 static struct pll_mapping nv04_pll_mapping[] = {
4731 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4732 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4733 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4734 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4738 static struct pll_mapping nv40_pll_mapping[] = {
4739 { PLL_CORE , 0x004000 },
4740 { PLL_MEMORY, 0x004020 },
4741 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4742 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4746 static struct pll_mapping nv50_pll_mapping[] = {
4747 { PLL_CORE , 0x004028 },
4748 { PLL_SHADER, 0x004020 },
4749 { PLL_UNK03 , 0x004000 },
4750 { PLL_MEMORY, 0x004008 },
4751 { PLL_UNK40 , 0x00e810 },
4752 { PLL_UNK41 , 0x00e818 },
4753 { PLL_UNK42 , 0x00e824 },
4754 { PLL_VPLL0 , 0x614100 },
4755 { PLL_VPLL1 , 0x614900 },
4759 static struct pll_mapping nv84_pll_mapping[] = {
4760 { PLL_CORE , 0x004028 },
4761 { PLL_SHADER, 0x004020 },
4762 { PLL_MEMORY, 0x004008 },
4763 { PLL_UNK05 , 0x004030 },
4764 { PLL_UNK41 , 0x00e818 },
4765 { PLL_VPLL0 , 0x614100 },
4766 { PLL_VPLL1 , 0x614900 },
4771 get_pll_register(struct drm_device *dev, enum pll_types type)
4773 struct drm_nouveau_private *dev_priv = dev->dev_private;
4774 struct nvbios *bios = &dev_priv->vbios;
4775 struct pll_mapping *map;
4778 if (dev_priv->card_type < NV_40)
4779 map = nv04_pll_mapping;
4781 if (dev_priv->card_type < NV_50)
4782 map = nv40_pll_mapping;
4784 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4786 if (plim[0] >= 0x30) {
4787 u8 *entry = plim + plim[1];
4788 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4789 if (entry[0] == type)
4790 return ROM32(entry[3]);
4796 if (dev_priv->chipset == 0x50)
4797 map = nv50_pll_mapping;
4799 map = nv84_pll_mapping;
4803 if (map->type == type)
4811 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4816 * Version 0x10: NV30, NV31
4817 * One byte header (version), one record of 24 bytes
4818 * Version 0x11: NV36 - Not implemented
4819 * Seems to have same record style as 0x10, but 3 records rather than 1
4820 * Version 0x20: Found on Geforce 6 cards
4821 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4822 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4823 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4824 * length in general, some (integrated) have an extra configuration byte
4825 * Version 0x30: Found on Geforce 8, separates the register mapping
4826 * from the limits tables.
4829 struct drm_nouveau_private *dev_priv = dev->dev_private;
4830 struct nvbios *bios = &dev_priv->vbios;
4831 int cv = bios->chip_version, pllindex = 0;
4832 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4833 uint32_t crystal_strap_mask, crystal_straps;
4835 if (!bios->pll_limit_tbl_ptr) {
4836 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4838 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4842 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4844 crystal_strap_mask = 1 << 6;
4845 /* open coded dev->twoHeads test */
4846 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4847 crystal_strap_mask |= 1 << 22;
4848 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4851 switch (pll_lim_ver) {
4853 * We use version 0 to indicate a pre limit table bios (single stage
4854 * pll) and load the hard coded limits instead.
4861 * Strictly v0x11 has 3 entries, but the last two don't seem
4873 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4874 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4875 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4878 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4879 "supported\n", pll_lim_ver);
4883 /* initialize all members to zero */
4884 memset(pll_lim, 0, sizeof(struct pll_lims));
4886 /* if we were passed a type rather than a register, figure
4887 * out the register and store it
4889 if (limit_match > PLL_MAX)
4890 pll_lim->reg = limit_match;
4892 pll_lim->reg = get_pll_register(dev, limit_match);
4897 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4898 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4900 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4901 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4902 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4903 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4904 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4905 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4906 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4908 /* these values taken from nv30/31/36 */
4909 pll_lim->vco1.min_n = 0x1;
4911 pll_lim->vco1.min_n = 0x5;
4912 pll_lim->vco1.max_n = 0xff;
4913 pll_lim->vco1.min_m = 0x1;
4914 pll_lim->vco1.max_m = 0xd;
4915 pll_lim->vco2.min_n = 0x4;
4917 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4918 * table version (apart from nv35)), N2 is compared to
4919 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4922 pll_lim->vco2.max_n = 0x28;
4923 if (cv == 0x30 || cv == 0x35)
4924 /* only 5 bits available for N2 on nv30/35 */
4925 pll_lim->vco2.max_n = 0x1f;
4926 pll_lim->vco2.min_m = 0x1;
4927 pll_lim->vco2.max_m = 0x4;
4928 pll_lim->max_log2p = 0x7;
4929 pll_lim->max_usable_log2p = 0x6;
4930 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4931 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4936 * First entry is default match, if nothing better. warn if
4939 if (ROM32(bios->data[plloffs]))
4940 NV_WARN(dev, "Default PLL limit entry has non-zero "
4941 "register field\n");
4943 for (i = 1; i < entries; i++)
4944 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4949 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4950 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4951 "limits table", pll_lim->reg);
4955 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4957 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4958 pllindex ? pll_lim->reg : 0);
4961 * Frequencies are stored in tables in MHz, kHz are more
4962 * useful, so we convert.
4965 /* What output frequencies can each VCO generate? */
4966 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4967 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4968 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4969 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4971 /* What input frequencies they accept (past the m-divider)? */
4972 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4973 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4974 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4975 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4977 /* What values are accepted as multiplier and divider? */
4978 pll_lim->vco1.min_n = pll_rec[20];
4979 pll_lim->vco1.max_n = pll_rec[21];
4980 pll_lim->vco1.min_m = pll_rec[22];
4981 pll_lim->vco1.max_m = pll_rec[23];
4982 pll_lim->vco2.min_n = pll_rec[24];
4983 pll_lim->vco2.max_n = pll_rec[25];
4984 pll_lim->vco2.min_m = pll_rec[26];
4985 pll_lim->vco2.max_m = pll_rec[27];
4987 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4988 if (pll_lim->max_log2p > 0x7)
4989 /* pll decoding in nv_hw.c assumes never > 7 */
4990 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4991 pll_lim->max_log2p);
4993 pll_lim->max_usable_log2p = 0x6;
4994 pll_lim->log2p_bias = pll_rec[30];
4996 if (recordlen > 0x22)
4997 pll_lim->refclk = ROM32(pll_rec[31]);
4999 if (recordlen > 0x23 && pll_rec[35])
5001 "Bits set in PLL configuration byte (%x)\n",
5004 /* C51 special not seen elsewhere */
5005 if (cv == 0x51 && !pll_lim->refclk) {
5006 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
5008 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
5009 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
5010 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
5011 pll_lim->refclk = 200000;
5013 pll_lim->refclk = 25000;
5016 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
5017 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
5018 uint8_t *record = NULL;
5021 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
5024 for (i = 0; i < entries; i++, entry += recordlen) {
5025 if (ROM32(entry[3]) == pll_lim->reg) {
5026 record = &bios->data[ROM16(entry[1])];
5032 NV_ERROR(dev, "Register 0x%08x not found in PLL "
5033 "limits table", pll_lim->reg);
5037 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5038 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5039 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
5040 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
5041 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
5042 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
5043 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
5044 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
5045 pll_lim->vco1.min_n = record[16];
5046 pll_lim->vco1.max_n = record[17];
5047 pll_lim->vco1.min_m = record[18];
5048 pll_lim->vco1.max_m = record[19];
5049 pll_lim->vco2.min_n = record[20];
5050 pll_lim->vco2.max_n = record[21];
5051 pll_lim->vco2.min_m = record[22];
5052 pll_lim->vco2.max_m = record[23];
5053 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
5054 pll_lim->log2p_bias = record[27];
5055 pll_lim->refclk = ROM32(record[28]);
5056 } else if (pll_lim_ver) { /* ver 0x40 */
5057 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
5058 uint8_t *record = NULL;
5061 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
5064 for (i = 0; i < entries; i++, entry += recordlen) {
5065 if (ROM32(entry[3]) == pll_lim->reg) {
5066 record = &bios->data[ROM16(entry[1])];
5072 NV_ERROR(dev, "Register 0x%08x not found in PLL "
5073 "limits table", pll_lim->reg);
5077 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5078 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5079 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
5080 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
5081 pll_lim->vco1.min_m = record[8];
5082 pll_lim->vco1.max_m = record[9];
5083 pll_lim->vco1.min_n = record[10];
5084 pll_lim->vco1.max_n = record[11];
5085 pll_lim->min_p = record[12];
5086 pll_lim->max_p = record[13];
5087 pll_lim->refclk = ROM16(entry[9]) * 1000;
5091 * By now any valid limit table ought to have set a max frequency for
5092 * vco1, so if it's zero it's either a pre limit table bios, or one
5093 * with an empty limit table (seen on nv18)
5095 if (!pll_lim->vco1.maxfreq) {
5096 pll_lim->vco1.minfreq = bios->fminvco;
5097 pll_lim->vco1.maxfreq = bios->fmaxvco;
5098 pll_lim->vco1.min_inputfreq = 0;
5099 pll_lim->vco1.max_inputfreq = INT_MAX;
5100 pll_lim->vco1.min_n = 0x1;
5101 pll_lim->vco1.max_n = 0xff;
5102 pll_lim->vco1.min_m = 0x1;
5103 if (crystal_straps == 0) {
5104 /* nv05 does this, nv11 doesn't, nv10 unknown */
5106 pll_lim->vco1.min_m = 0x7;
5107 pll_lim->vco1.max_m = 0xd;
5110 pll_lim->vco1.min_m = 0x8;
5111 pll_lim->vco1.max_m = 0xe;
5113 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
5114 pll_lim->max_log2p = 4;
5116 pll_lim->max_log2p = 5;
5117 pll_lim->max_usable_log2p = pll_lim->max_log2p;
5120 if (!pll_lim->refclk)
5121 switch (crystal_straps) {
5123 pll_lim->refclk = 13500;
5126 pll_lim->refclk = 14318;
5129 pll_lim->refclk = 27000;
5131 case (1 << 22 | 1 << 6):
5132 pll_lim->refclk = 25000;
5136 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
5137 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
5138 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
5139 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
5140 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
5141 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
5142 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
5143 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5144 if (pll_lim->vco2.maxfreq) {
5145 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5146 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5147 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5148 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5149 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5150 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5151 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5152 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5154 if (!pll_lim->max_p) {
5155 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5156 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5158 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5159 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5161 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
5166 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5169 * offset + 0 (8 bits): Micro version
5170 * offset + 1 (8 bits): Minor version
5171 * offset + 2 (8 bits): Chip version
5172 * offset + 3 (8 bits): Major version
5175 bios->major_version = bios->data[offset + 3];
5176 bios->chip_version = bios->data[offset + 2];
5177 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5178 bios->data[offset + 3], bios->data[offset + 2],
5179 bios->data[offset + 1], bios->data[offset]);
5182 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5185 * Parses the init table segment for pointers used in script execution.
5187 * offset + 0 (16 bits): init script tables pointer
5188 * offset + 2 (16 bits): macro index table pointer
5189 * offset + 4 (16 bits): macro table pointer
5190 * offset + 6 (16 bits): condition table pointer
5191 * offset + 8 (16 bits): io condition table pointer
5192 * offset + 10 (16 bits): io flag condition table pointer
5193 * offset + 12 (16 bits): init function table pointer
5196 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5197 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5198 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5199 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5200 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5201 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5202 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5205 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5208 * Parses the load detect values for g80 cards.
5210 * offset + 0 (16 bits): loadval table pointer
5213 uint16_t load_table_ptr;
5214 uint8_t version, headerlen, entrylen, num_entries;
5216 if (bitentry->length != 3) {
5217 NV_ERROR(dev, "Do not understand BIT A table\n");
5221 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5223 if (load_table_ptr == 0x0) {
5224 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
5228 version = bios->data[load_table_ptr];
5230 if (version != 0x10) {
5231 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5232 version >> 4, version & 0xF);
5236 headerlen = bios->data[load_table_ptr + 1];
5237 entrylen = bios->data[load_table_ptr + 2];
5238 num_entries = bios->data[load_table_ptr + 3];
5240 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5241 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5245 /* First entry is normal dac, 2nd tv-out perhaps? */
5246 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
5251 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5254 * offset + 8 (16 bits): PLL limits table pointer
5256 * There's more in here, but that's unknown.
5259 if (bitentry->length < 10) {
5260 NV_ERROR(dev, "Do not understand BIT C table\n");
5264 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5269 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5272 * Parses the flat panel table segment that the bit entry points to.
5273 * Starting at bitentry->offset:
5275 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5276 * records beginning with a freq.
5277 * offset + 2 (16 bits): mode table pointer
5280 if (bitentry->length != 4) {
5281 NV_ERROR(dev, "Do not understand BIT display table\n");
5285 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5290 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5293 * Parses the init table segment that the bit entry points to.
5295 * See parse_script_table_pointers for layout
5298 if (bitentry->length < 14) {
5299 NV_ERROR(dev, "Do not understand init table\n");
5303 parse_script_table_pointers(bios, bitentry->offset);
5305 if (bitentry->length >= 16)
5306 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5307 if (bitentry->length >= 18)
5308 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5313 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5316 * BIT 'i' (info?) table
5318 * offset + 0 (32 bits): BIOS version dword (as in B table)
5319 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5320 * offset + 13 (16 bits): pointer to table containing DAC load
5321 * detection comparison values
5323 * There's other things in the table, purpose unknown
5326 uint16_t daccmpoffset;
5327 uint8_t dacver, dacheaderlen;
5329 if (bitentry->length < 6) {
5330 NV_ERROR(dev, "BIT i table too short for needed information\n");
5334 parse_bios_version(dev, bios, bitentry->offset);
5337 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5338 * Quadro identity crisis), other bits possibly as for BMP feature byte
5340 bios->feature_byte = bios->data[bitentry->offset + 5];
5341 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5343 if (bitentry->length < 15) {
5344 NV_WARN(dev, "BIT i table not long enough for DAC load "
5345 "detection comparison table\n");
5349 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5351 /* doesn't exist on g80 */
5356 * The first value in the table, following the header, is the
5357 * comparison value, the second entry is a comparison value for
5358 * TV load detection.
5361 dacver = bios->data[daccmpoffset];
5362 dacheaderlen = bios->data[daccmpoffset + 1];
5364 if (dacver != 0x00 && dacver != 0x10) {
5365 NV_WARN(dev, "DAC load detection comparison table version "
5366 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5370 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5371 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
5376 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5379 * Parses the LVDS table segment that the bit entry points to.
5380 * Starting at bitentry->offset:
5382 * offset + 0 (16 bits): LVDS strap xlate table pointer
5385 if (bitentry->length != 2) {
5386 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5391 * No idea if it's still called the LVDS manufacturer table, but
5392 * the concept's close enough.
5394 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5400 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5401 struct bit_entry *bitentry)
5404 * offset + 2 (8 bits): number of options in an
5405 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5406 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5407 * restrict option selection
5409 * There's a bunch of bits in this table other than the RAM restrict
5410 * stuff that we don't use - their use currently unknown
5414 * Older bios versions don't have a sufficiently long table for
5417 if (bitentry->length < 0x5)
5420 if (bitentry->version < 2) {
5421 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5422 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5424 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5425 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5431 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5434 * Parses the pointer to the TMDS table
5436 * Starting at bitentry->offset:
5438 * offset + 0 (16 bits): TMDS table pointer
5440 * The TMDS table is typically found just before the DCB table, with a
5441 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5444 * At offset +7 is a pointer to a script, which I don't know how to
5446 * At offset +9 is a pointer to another script, likewise
5447 * Offset +11 has a pointer to a table where the first word is a pxclk
5448 * frequency and the second word a pointer to a script, which should be
5449 * run if the comparison pxclk frequency is less than the pxclk desired.
5450 * This repeats for decreasing comparison frequencies
5451 * Offset +13 has a pointer to a similar table
5452 * The selection of table (and possibly +7/+9 script) is dictated by
5453 * "or" from the DCB.
5456 uint16_t tmdstableptr, script1, script2;
5458 if (bitentry->length != 2) {
5459 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5463 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5464 if (!tmdstableptr) {
5465 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5469 NV_INFO(dev, "TMDS table version %d.%d\n",
5470 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5472 /* nv50+ has v2.0, but we don't parse it atm */
5473 if (bios->data[tmdstableptr] != 0x11)
5477 * These two scripts are odd: they don't seem to get run even when
5478 * they are not stubbed.
5480 script1 = ROM16(bios->data[tmdstableptr + 7]);
5481 script2 = ROM16(bios->data[tmdstableptr + 9]);
5482 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5483 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5485 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5486 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5492 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5493 struct bit_entry *bitentry)
5496 * Parses the pointer to the G80 output script tables
5498 * Starting at bitentry->offset:
5500 * offset + 0 (16 bits): output script table pointer
5503 uint16_t outputscripttableptr;
5505 if (bitentry->length != 3) {
5506 NV_ERROR(dev, "Do not understand BIT U table\n");
5510 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5511 bios->display.script_table_ptr = outputscripttableptr;
5516 parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5517 struct bit_entry *bitentry)
5519 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
5525 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5528 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5531 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5533 struct drm_nouveau_private *dev_priv = dev->dev_private;
5534 struct nvbios *bios = &dev_priv->vbios;
5537 entries = bios->data[bios->offset + 10];
5538 entry = &bios->data[bios->offset + 12];
5540 if (entry[0] == id) {
5542 bit->version = entry[1];
5543 bit->length = ROM16(entry[2]);
5544 bit->offset = ROM16(entry[4]);
5545 bit->data = ROMPTR(bios, entry[4]);
5549 entry += bios->data[bios->offset + 9];
5556 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5557 struct bit_table *table)
5559 struct drm_device *dev = bios->dev;
5560 struct bit_entry bitentry;
5562 if (bit_table(dev, table->id, &bitentry) == 0)
5563 return table->parse_fn(dev, bios, &bitentry);
5565 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5570 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5575 * The only restriction on parsing order currently is having 'i' first
5576 * for use of bios->*_version or bios->feature_byte while parsing;
5577 * functions shouldn't be actually *doing* anything apart from pulling
5578 * data from the image into the bios struct, thus no interdependencies
5580 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5581 if (ret) /* info? */
5583 if (bios->major_version >= 0x60) /* g80+ */
5584 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5585 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5588 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5589 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5592 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5593 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5594 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5595 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5596 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
5601 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5604 * Parses the BMP structure for useful things, but does not act on them
5606 * offset + 5: BMP major version
5607 * offset + 6: BMP minor version
5608 * offset + 9: BMP feature byte
5609 * offset + 10: BCD encoded BIOS version
5611 * offset + 18: init script table pointer (for bios versions < 5.10h)
5612 * offset + 20: extra init script table pointer (for bios
5615 * offset + 24: memory init table pointer (used on early bios versions)
5616 * offset + 26: SDR memory sequencing setup data table
5617 * offset + 28: DDR memory sequencing setup data table
5619 * offset + 54: index of I2C CRTC pair to use for CRT output
5620 * offset + 55: index of I2C CRTC pair to use for TV output
5621 * offset + 56: index of I2C CRTC pair to use for flat panel output
5622 * offset + 58: write CRTC index for I2C pair 0
5623 * offset + 59: read CRTC index for I2C pair 0
5624 * offset + 60: write CRTC index for I2C pair 1
5625 * offset + 61: read CRTC index for I2C pair 1
5627 * offset + 67: maximum internal PLL frequency (single stage PLL)
5628 * offset + 71: minimum internal PLL frequency (single stage PLL)
5630 * offset + 75: script table pointers, as described in
5631 * parse_script_table_pointers
5633 * offset + 89: TMDS single link output A table pointer
5634 * offset + 91: TMDS single link output B table pointer
5635 * offset + 95: LVDS single link output A table pointer
5636 * offset + 105: flat panel timings table pointer
5637 * offset + 107: flat panel strapping translation table pointer
5638 * offset + 117: LVDS manufacturer panel config table pointer
5639 * offset + 119: LVDS manufacturer strapping translation table pointer
5641 * offset + 142: PLL limits table pointer
5643 * offset + 156: minimum pixel clock for LVDS dual link
5646 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5648 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5650 /* load needed defaults in case we can't parse this info */
5651 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5652 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5653 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5654 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
5655 bios->digital_min_front_porch = 0x4b;
5656 bios->fmaxvco = 256000;
5657 bios->fminvco = 128000;
5658 bios->fp.duallink_transition_clk = 90000;
5660 bmp_version_major = bmp[5];
5661 bmp_version_minor = bmp[6];
5663 NV_TRACE(dev, "BMP version %d.%d\n",
5664 bmp_version_major, bmp_version_minor);
5667 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5668 * pointer on early versions
5670 if (bmp_version_major < 5)
5671 *(uint16_t *)&bios->data[0x36] = 0;
5674 * Seems that the minor version was 1 for all major versions prior
5675 * to 5. Version 6 could theoretically exist, but I suspect BIT
5678 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5679 NV_ERROR(dev, "You have an unsupported BMP version. "
5680 "Please send in your bios\n");
5684 if (bmp_version_major == 0)
5685 /* nothing that's currently useful in this version */
5687 else if (bmp_version_major == 1)
5688 bmplength = 44; /* exact for 1.01 */
5689 else if (bmp_version_major == 2)
5690 bmplength = 48; /* exact for 2.01 */
5691 else if (bmp_version_major == 3)
5693 /* guessed - mem init tables added in this version */
5694 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5695 /* don't know if 5.0 exists... */
5697 /* guessed - BMP I2C indices added in version 4*/
5698 else if (bmp_version_minor < 0x6)
5699 bmplength = 67; /* exact for 5.01 */
5700 else if (bmp_version_minor < 0x10)
5701 bmplength = 75; /* exact for 5.06 */
5702 else if (bmp_version_minor == 0x10)
5703 bmplength = 89; /* exact for 5.10h */
5704 else if (bmp_version_minor < 0x14)
5705 bmplength = 118; /* exact for 5.11h */
5706 else if (bmp_version_minor < 0x24)
5708 * Not sure of version where pll limits came in;
5709 * certainly exist by 0x24 though.
5711 /* length not exact: this is long enough to get lvds members */
5713 else if (bmp_version_minor < 0x27)
5715 * Length not exact: this is long enough to get pll limit
5721 * Length not exact: this is long enough to get dual link
5727 if (nv_cksum(bmp, 8)) {
5728 NV_ERROR(dev, "Bad BMP checksum\n");
5733 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5734 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5735 * (not nv10gl), bit 5 that the flat panel tables are present, and
5738 bios->feature_byte = bmp[9];
5740 parse_bios_version(dev, bios, offset + 10);
5742 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5743 bios->old_style_init = true;
5744 legacy_scripts_offset = 18;
5745 if (bmp_version_major < 2)
5746 legacy_scripts_offset -= 4;
5747 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5748 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5750 if (bmp_version_major > 2) { /* appears in BMP 3 */
5751 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5752 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5753 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5756 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5758 legacy_i2c_offset = offset + 54;
5759 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5760 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5761 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5762 if (bios->data[legacy_i2c_offset + 4])
5763 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5764 if (bios->data[legacy_i2c_offset + 5])
5765 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5766 if (bios->data[legacy_i2c_offset + 6])
5767 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5768 if (bios->data[legacy_i2c_offset + 7])
5769 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
5771 if (bmplength > 74) {
5772 bios->fmaxvco = ROM32(bmp[67]);
5773 bios->fminvco = ROM32(bmp[71]);
5776 parse_script_table_pointers(bios, offset + 75);
5777 if (bmplength > 94) {
5778 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5779 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5781 * Never observed in use with lvds scripts, but is reused for
5782 * 18/24 bit panel interface default for EDID equipped panels
5783 * (if_is_24bit not set directly to avoid any oscillation).
5785 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5787 if (bmplength > 108) {
5788 bios->fp.fptablepointer = ROM16(bmp[105]);
5789 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5790 bios->fp.xlatwidth = 1;
5792 if (bmplength > 120) {
5793 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5794 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5796 if (bmplength > 143)
5797 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5799 if (bmplength > 157)
5800 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5805 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5809 for (i = 0; i <= (n - len); i++) {
5810 for (j = 0; j < len; j++)
5811 if (data[i + j] != str[j])
5820 static struct dcb_gpio_entry *
5821 new_gpio_entry(struct nvbios *bios)
5823 struct drm_device *dev = bios->dev;
5824 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
5826 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5827 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5831 return &gpio->entry[gpio->entries++];
5834 struct dcb_gpio_entry *
5835 nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5837 struct drm_nouveau_private *dev_priv = dev->dev_private;
5838 struct nvbios *bios = &dev_priv->vbios;
5841 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5842 if (bios->dcb.gpio.entry[i].tag != tag)
5845 return &bios->dcb.gpio.entry[i];
5852 parse_dcb_gpio_table(struct nvbios *bios)
5854 struct drm_device *dev = bios->dev;
5855 struct dcb_gpio_entry *e;
5856 u8 headerlen, entries, recordlen;
5857 u8 *dcb, *gpio = NULL, *entry;
5860 dcb = ROMPTR(bios, bios->data[0x36]);
5861 if (dcb[0] >= 0x30) {
5862 gpio = ROMPTR(bios, dcb[10]);
5866 headerlen = gpio[1];
5868 recordlen = gpio[3];
5870 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
5871 gpio = ROMPTR(bios, dcb[-15]);
5877 recordlen = gpio[1];
5879 if (dcb[0] >= 0x22) {
5880 /* No GPIO table present, parse the TVDAC GPIO data. */
5881 uint8_t *tvdac_gpio = &dcb[-5];
5883 if (tvdac_gpio[0] & 1) {
5884 e = new_gpio_entry(bios);
5885 e->tag = DCB_GPIO_TVDAC0;
5886 e->line = tvdac_gpio[1] >> 4;
5887 e->invert = tvdac_gpio[0] & 2;
5892 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5896 entry = gpio + headerlen;
5897 for (i = 0; i < entries; i++, entry += recordlen) {
5898 e = new_gpio_entry(bios);
5902 if (gpio[0] < 0x40) {
5903 e->entry = ROM16(entry[0]);
5904 e->tag = (e->entry & 0x07e0) >> 5;
5905 if (e->tag == 0x3f) {
5906 bios->dcb.gpio.entries--;
5910 e->line = (e->entry & 0x001f);
5911 e->invert = ((e->entry & 0xf800) >> 11) != 4;
5913 e->entry = ROM32(entry[0]);
5914 e->tag = (e->entry & 0x0000ff00) >> 8;
5915 if (e->tag == 0xff) {
5916 bios->dcb.gpio.entries--;
5920 e->line = (e->entry & 0x0000001f) >> 0;
5921 if (gpio[0] == 0x40) {
5922 e->state_default = (e->entry & 0x01000000) >> 24;
5923 e->state[0] = (e->entry & 0x18000000) >> 27;
5924 e->state[1] = (e->entry & 0x60000000) >> 29;
5926 e->state_default = (e->entry & 0x00000080) >> 7;
5927 e->state[0] = (entry[4] >> 4) & 3;
5928 e->state[1] = (entry[4] >> 6) & 3;
5934 /* Apple iMac G4 NV18 */
5935 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5936 e = new_gpio_entry(bios);
5938 e->tag = DCB_GPIO_TVDAC0;
5944 struct dcb_connector_table_entry *
5945 nouveau_bios_connector_entry(struct drm_device *dev, int index)
5947 struct drm_nouveau_private *dev_priv = dev->dev_private;
5948 struct nvbios *bios = &dev_priv->vbios;
5949 struct dcb_connector_table_entry *cte;
5951 if (index >= bios->dcb.connector.entries)
5954 cte = &bios->dcb.connector.entry[index];
5955 if (cte->type == 0xff)
5961 static enum dcb_connector_type
5962 divine_connector_type(struct nvbios *bios, int index)
5964 struct dcb_table *dcb = &bios->dcb;
5965 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5968 for (i = 0; i < dcb->entries; i++) {
5969 if (dcb->entry[i].connector == index)
5970 encoders |= (1 << dcb->entry[i].type);
5973 if (encoders & (1 << OUTPUT_DP)) {
5974 if (encoders & (1 << OUTPUT_TMDS))
5975 type = DCB_CONNECTOR_DP;
5977 type = DCB_CONNECTOR_eDP;
5979 if (encoders & (1 << OUTPUT_TMDS)) {
5980 if (encoders & (1 << OUTPUT_ANALOG))
5981 type = DCB_CONNECTOR_DVI_I;
5983 type = DCB_CONNECTOR_DVI_D;
5985 if (encoders & (1 << OUTPUT_ANALOG)) {
5986 type = DCB_CONNECTOR_VGA;
5988 if (encoders & (1 << OUTPUT_LVDS)) {
5989 type = DCB_CONNECTOR_LVDS;
5991 if (encoders & (1 << OUTPUT_TV)) {
5992 type = DCB_CONNECTOR_TV_0;
5999 apply_dcb_connector_quirks(struct nvbios *bios, int idx)
6001 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
6002 struct drm_device *dev = bios->dev;
6004 /* Gigabyte NX85T */
6005 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
6006 if (cte->type == DCB_CONNECTOR_HDMI_1)
6007 cte->type = DCB_CONNECTOR_DVI_I;
6010 /* Gigabyte GV-NX86T512H */
6011 if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) {
6012 if (cte->type == DCB_CONNECTOR_HDMI_1)
6013 cte->type = DCB_CONNECTOR_DVI_I;
6017 static const u8 hpd_gpio[16] = {
6018 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff,
6019 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60,
6023 parse_dcb_connector_table(struct nvbios *bios)
6025 struct drm_device *dev = bios->dev;
6026 struct dcb_connector_table *ct = &bios->dcb.connector;
6027 struct dcb_connector_table_entry *cte;
6028 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6032 if (!bios->dcb.connector_table_ptr) {
6033 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6037 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
6038 conntab[0], conntab[1], conntab[2], conntab[3]);
6039 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
6040 (conntab[3] != 2 && conntab[3] != 4)) {
6041 NV_ERROR(dev, " Unknown! Please report.\n");
6045 ct->entries = conntab[2];
6047 entry = conntab + conntab[1];
6048 cte = &ct->entry[0];
6049 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
6051 if (conntab[3] == 2)
6052 cte->entry = ROM16(entry[0]);
6054 cte->entry = ROM32(entry[0]);
6056 cte->type = (cte->entry & 0x000000ff) >> 0;
6057 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6059 cte->gpio_tag = ffs((cte->entry & 0x07033000) >> 12);
6060 cte->gpio_tag = hpd_gpio[cte->gpio_tag];
6062 if (cte->type == 0xff)
6065 apply_dcb_connector_quirks(bios, i);
6067 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
6068 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
6070 /* check for known types, fallback to guessing the type
6071 * from attached encoders if we hit an unknown.
6073 switch (cte->type) {
6074 case DCB_CONNECTOR_VGA:
6075 case DCB_CONNECTOR_TV_0:
6076 case DCB_CONNECTOR_TV_1:
6077 case DCB_CONNECTOR_TV_3:
6078 case DCB_CONNECTOR_DVI_I:
6079 case DCB_CONNECTOR_DVI_D:
6080 case DCB_CONNECTOR_LVDS:
6081 case DCB_CONNECTOR_LVDS_SPWG:
6082 case DCB_CONNECTOR_DP:
6083 case DCB_CONNECTOR_eDP:
6084 case DCB_CONNECTOR_HDMI_0:
6085 case DCB_CONNECTOR_HDMI_1:
6088 cte->type = divine_connector_type(bios, cte->index);
6089 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
6093 if (nouveau_override_conntype) {
6094 int type = divine_connector_type(bios, cte->index);
6095 if (type != cte->type)
6096 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
6102 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6104 struct dcb_entry *entry = &dcb->entry[dcb->entries];
6106 memset(entry, 0, sizeof(struct dcb_entry));
6107 entry->index = dcb->entries++;
6112 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
6115 struct dcb_entry *entry = new_dcb_entry(dcb);
6118 entry->i2c_index = i2c;
6119 entry->heads = heads;
6120 if (type != OUTPUT_ANALOG)
6121 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
6126 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6127 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6129 entry->type = conn & 0xf;
6130 entry->i2c_index = (conn >> 4) & 0xf;
6131 entry->heads = (conn >> 8) & 0xf;
6132 if (dcb->version >= 0x40)
6133 entry->connector = (conn >> 12) & 0xf;
6134 entry->bus = (conn >> 16) & 0xf;
6135 entry->location = (conn >> 20) & 0x3;
6136 entry->or = (conn >> 24) & 0xf;
6138 switch (entry->type) {
6141 * Although the rest of a CRT conf dword is usually
6142 * zeros, mac biosen have stuff there so we must mask
6144 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6145 (conf & 0xffff) * 10 :
6146 (conf & 0xff) * 10000;
6152 entry->lvdsconf.use_straps_for_mode = true;
6153 if (dcb->version < 0x22) {
6156 * The laptop in bug 14567 lies and claims to not use
6157 * straps when it does, so assume all DCB 2.0 laptops
6158 * use straps, until a broken EDID using one is produced
6160 entry->lvdsconf.use_straps_for_mode = true;
6162 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6163 * mean the same thing (probably wrong, but might work)
6165 if (conf & 0x4 || conf & 0x8)
6166 entry->lvdsconf.use_power_scripts = true;
6170 entry->lvdsconf.use_acpi_for_edid = true;
6172 entry->lvdsconf.use_power_scripts = true;
6173 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6177 * Until we even try to use these on G8x, it's
6178 * useless reporting unknown bits. They all are.
6180 if (dcb->version >= 0x40)
6183 NV_ERROR(dev, "Unknown LVDS configuration bits, "
6190 if (dcb->version >= 0x30)
6191 entry->tvconf.has_component_output = conf & (0x8 << 4);
6193 entry->tvconf.has_component_output = false;
6198 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
6199 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
6200 switch ((conf & 0x0f000000) >> 24) {
6202 entry->dpconf.link_nr = 4;
6205 entry->dpconf.link_nr = 2;
6208 entry->dpconf.link_nr = 1;
6213 if (dcb->version >= 0x40)
6214 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
6215 else if (dcb->version >= 0x30)
6216 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
6217 else if (dcb->version >= 0x22)
6218 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
6222 /* weird g80 mobile type that "nv" treats as a terminator */
6229 if (dcb->version < 0x40) {
6230 /* Normal entries consist of a single bit, but dual link has
6231 * the next most significant bit set too
6233 entry->duallink_possible =
6234 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6236 entry->duallink_possible = (entry->sorconf.link == 3);
6239 /* unsure what DCB version introduces this, 3.0? */
6240 if (conf & 0x100000)
6241 entry->i2c_upper_default = true;
6247 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6248 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6250 switch (conn & 0x0000000f) {
6252 entry->type = OUTPUT_ANALOG;
6255 entry->type = OUTPUT_TV;
6260 entry->type = OUTPUT_LVDS;
6262 entry->type = OUTPUT_TMDS;
6265 entry->type = OUTPUT_LVDS;
6268 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6272 entry->i2c_index = (conn & 0x0003c000) >> 14;
6273 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6274 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6275 entry->location = (conn & 0x01e00000) >> 21;
6276 entry->bus = (conn & 0x0e000000) >> 25;
6277 entry->duallink_possible = false;
6279 switch (entry->type) {
6281 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6284 entry->tvconf.has_component_output = false;
6287 if ((conn & 0x00003f00) >> 8 != 0x10)
6288 entry->lvdsconf.use_straps_for_mode = true;
6289 entry->lvdsconf.use_power_scripts = true;
6298 static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6299 uint32_t conn, uint32_t conf)
6301 struct dcb_entry *entry = new_dcb_entry(dcb);
6304 if (dcb->version >= 0x20)
6305 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6307 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6311 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6312 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6318 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6321 * DCB v2.0 lists each output combination separately.
6322 * Here we merge compatible entries to have fewer outputs, with
6326 int i, newentries = 0;
6328 for (i = 0; i < dcb->entries; i++) {
6329 struct dcb_entry *ient = &dcb->entry[i];
6332 for (j = i + 1; j < dcb->entries; j++) {
6333 struct dcb_entry *jent = &dcb->entry[j];
6335 if (jent->type == 100) /* already merged entry */
6338 /* merge heads field when all other fields the same */
6339 if (jent->i2c_index == ient->i2c_index &&
6340 jent->type == ient->type &&
6341 jent->location == ient->location &&
6342 jent->or == ient->or) {
6343 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6345 ient->heads |= jent->heads;
6346 jent->type = 100; /* dummy value */
6351 /* Compact entries merged into others out of dcb */
6352 for (i = 0; i < dcb->entries; i++) {
6353 if (dcb->entry[i].type == 100)
6356 if (newentries != i) {
6357 dcb->entry[newentries] = dcb->entry[i];
6358 dcb->entry[newentries].index = newentries;
6363 dcb->entries = newentries;
6367 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6369 struct drm_nouveau_private *dev_priv = dev->dev_private;
6370 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6372 /* Dell Precision M6300
6373 * DCB entry 2: 02025312 00000010
6374 * DCB entry 3: 02026312 00000020
6376 * Identical, except apparently a different connector on a
6377 * different SOR link. Not a clue how we're supposed to know
6378 * which one is in use if it even shares an i2c line...
6380 * Ignore the connector on the second SOR link to prevent
6381 * nasty problems until this is sorted (assuming it's not a
6384 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6385 if (*conn == 0x02026312 && *conf == 0x00000020)
6391 * DCB reports an LVDS output that should be TMDS:
6392 * DCB entry 1: f2005014 ffffffff
6394 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6395 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6396 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6403 * So many things wrong here, replace the entire encoder table..
6405 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6407 *conn = 0x02001300; /* VGA, connector 1 */
6411 *conn = 0x01010312; /* DVI, connector 0 */
6415 *conn = 0x01010310; /* VGA, connector 0 */
6419 *conn = 0x02022362; /* HDMI, connector 2 */
6422 *conn = 0x0000000e; /* EOL */
6427 /* Some other twisted XFX board (rhbz#694914)
6429 * The DVI/VGA encoder combo that's supposed to represent the
6430 * DVI-I connector actually point at two different ones, and
6431 * the HDMI connector ends up paired with the VGA instead.
6433 * Connector table is missing anything for VGA at all, pointing it
6434 * an invalid conntab entry 2 so we figure it out ourself.
6436 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6438 *conn = 0x02002300; /* VGA, connector 2 */
6442 *conn = 0x01010312; /* DVI, connector 0 */
6446 *conn = 0x04020310; /* VGA, connector 0 */
6450 *conn = 0x02021322; /* HDMI, connector 1 */
6453 *conn = 0x0000000e; /* EOL */
6462 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6464 struct dcb_table *dcb = &bios->dcb;
6465 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6468 /* Apple iMac G4 NV17 */
6469 if (of_machine_is_compatible("PowerMac4,5")) {
6470 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6471 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6476 /* Make up some sane defaults */
6477 fabricate_dcb_output(dcb, OUTPUT_ANALOG, LEGACY_I2C_CRT, 1, 1);
6479 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6480 fabricate_dcb_output(dcb, OUTPUT_TV, LEGACY_I2C_TV,
6483 else if (bios->tmds.output0_script_ptr ||
6484 bios->tmds.output1_script_ptr)
6485 fabricate_dcb_output(dcb, OUTPUT_TMDS, LEGACY_I2C_PANEL,
6490 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6492 struct drm_nouveau_private *dev_priv = dev->dev_private;
6493 struct dcb_table *dcb = &bios->dcb;
6494 uint16_t dcbptr = 0, i2ctabptr = 0;
6496 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6497 bool configblock = true;
6498 int recordlength = 8, confofs = 4;
6501 /* get the offset from 0x36 */
6502 if (dev_priv->card_type > NV_04) {
6503 dcbptr = ROM16(bios->data[0x36]);
6504 if (dcbptr == 0x0000)
6505 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6508 /* this situation likely means a really old card, pre DCB */
6509 if (dcbptr == 0x0) {
6510 fabricate_dcb_encoder_table(dev, bios);
6514 dcbtable = &bios->data[dcbptr];
6516 /* get DCB version */
6517 dcb->version = dcbtable[0];
6518 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
6519 dcb->version >> 4, dcb->version & 0xf);
6521 if (dcb->version >= 0x20) { /* NV17+ */
6524 if (dcb->version >= 0x30) { /* NV40+ */
6525 headerlen = dcbtable[1];
6526 entries = dcbtable[2];
6527 recordlength = dcbtable[3];
6528 i2ctabptr = ROM16(dcbtable[4]);
6529 sig = ROM32(dcbtable[6]);
6530 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6531 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6533 i2ctabptr = ROM16(dcbtable[2]);
6534 sig = ROM32(dcbtable[4]);
6538 if (sig != 0x4edcbdcb) {
6539 NV_ERROR(dev, "Bad Display Configuration Block "
6540 "signature (%08X)\n", sig);
6543 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6544 char sig[8] = { 0 };
6546 strncpy(sig, (char *)&dcbtable[-7], 7);
6547 i2ctabptr = ROM16(dcbtable[2]);
6551 if (strcmp(sig, "DEV_REC")) {
6552 NV_ERROR(dev, "Bad Display Configuration Block "
6553 "signature (%s)\n", sig);
6558 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6559 * has the same single (crt) entry, even when tv-out present, so
6560 * the conclusion is this version cannot really be used.
6561 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6562 * 5 entries, which are not specific to the card and so no use.
6563 * v1.2 does have an I2C table that read_dcb_i2c_table can
6564 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6565 * pointer, so use the indices parsed in parse_bmp_structure.
6566 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6568 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6569 "adding all possible outputs\n");
6570 fabricate_dcb_encoder_table(dev, bios);
6575 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6577 dcb->i2c_table = &bios->data[i2ctabptr];
6578 if (dcb->version >= 0x30)
6579 dcb->i2c_default_indices = dcb->i2c_table[4];
6582 * Parse the "management" I2C bus, used for hardware
6583 * monitoring and some external TMDS transmitters.
6585 if (dcb->version >= 0x22) {
6586 int idx = (dcb->version >= 0x40 ?
6587 dcb->i2c_default_indices & 0xf :
6590 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6591 idx, &dcb->i2c[idx]);
6595 if (entries > DCB_MAX_NUM_ENTRIES)
6596 entries = DCB_MAX_NUM_ENTRIES;
6598 for (i = 0; i < entries; i++) {
6599 uint32_t connection, config = 0;
6601 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6603 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6605 /* seen on an NV11 with DCB v1.5 */
6606 if (connection == 0x00000000)
6609 /* seen on an NV17 with DCB v2.0 */
6610 if (connection == 0xffffffff)
6613 if ((connection & 0x0000000f) == 0x0000000f)
6616 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6619 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6620 dcb->entries, connection, config);
6622 if (!parse_dcb_entry(dev, dcb, connection, config))
6627 * apart for v2.1+ not being known for requiring merging, this
6628 * guarantees dcbent->index is the index of the entry in the rom image
6630 if (dcb->version < 0x21)
6631 merge_like_dcb_entries(dev, dcb);
6636 parse_dcb_gpio_table(bios);
6637 parse_dcb_connector_table(bios);
6642 fixup_legacy_connector(struct nvbios *bios)
6644 struct dcb_table *dcb = &bios->dcb;
6645 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6648 * DCB 3.0 also has the table in most cases, but there are some cards
6649 * where the table is filled with stub entries, and the DCB entriy
6650 * indices are all 0. We don't need the connector indices on pre-G80
6651 * chips (yet?) so limit the use to DCB 4.0 and above.
6653 if (dcb->version >= 0x40)
6656 dcb->connector.entries = 0;
6659 * No known connector info before v3.0, so make it up. the rule here
6660 * is: anything on the same i2c bus is considered to be on the same
6661 * connector. any output without an associated i2c bus is assigned
6662 * its own unique connector index.
6664 for (i = 0; i < dcb->entries; i++) {
6666 * Ignore the I2C index for on-chip TV-out, as there
6667 * are cards with bogus values (nv31m in bug 23212),
6668 * and it's otherwise useless.
6670 if (dcb->entry[i].type == OUTPUT_TV &&
6671 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6672 dcb->entry[i].i2c_index = 0xf;
6673 i2c = dcb->entry[i].i2c_index;
6675 if (i2c_conn[i2c]) {
6676 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6680 dcb->entry[i].connector = dcb->connector.entries++;
6682 i2c_conn[i2c] = dcb->connector.entries;
6685 /* Fake the connector table as well as just connector indices */
6686 for (i = 0; i < dcb->connector.entries; i++) {
6687 dcb->connector.entry[i].index = i;
6688 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6689 dcb->connector.entry[i].gpio_tag = 0xff;
6694 fixup_legacy_i2c(struct nvbios *bios)
6696 struct dcb_table *dcb = &bios->dcb;
6699 for (i = 0; i < dcb->entries; i++) {
6700 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6701 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6702 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6703 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6704 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6705 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6709 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6712 * The header following the "HWSQ" signature has the number of entries,
6713 * and the entry size
6715 * An entry consists of a dword to write to the sequencer control reg
6716 * (0x00001304), followed by the ucode bytes, written sequentially,
6717 * starting at reg 0x00001400
6720 uint8_t bytes_to_write;
6721 uint16_t hwsq_entry_offset;
6724 if (bios->data[hwsq_offset] <= entry) {
6725 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6726 "requested entry\n");
6730 bytes_to_write = bios->data[hwsq_offset + 1];
6732 if (bytes_to_write != 36) {
6733 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6737 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6739 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6741 /* set sequencer control */
6742 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6743 bytes_to_write -= 4;
6746 for (i = 0; i < bytes_to_write; i += 4)
6747 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6749 /* twiddle NV_PBUS_DEBUG_4 */
6750 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6755 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6756 struct nvbios *bios)
6759 * BMP based cards, from NV17, need a microcode loading to correctly
6760 * control the GPIO etc for LVDS panels
6762 * BIT based cards seem to do this directly in the init scripts
6764 * The microcode entries are found by the "HWSQ" signature.
6767 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6768 const int sz = sizeof(hwsq_signature);
6771 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6775 /* always use entry 0? */
6776 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6779 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6781 struct drm_nouveau_private *dev_priv = dev->dev_private;
6782 struct nvbios *bios = &dev_priv->vbios;
6783 const uint8_t edid_sig[] = {
6784 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6785 uint16_t offset = 0;
6787 int searchlen = NV_PROM_SIZE;
6790 return bios->fp.edid;
6793 newoffset = findstr(&bios->data[offset], searchlen,
6797 offset += newoffset;
6798 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6801 searchlen -= offset;
6805 NV_TRACE(dev, "Found EDID in BIOS\n");
6807 return bios->fp.edid = &bios->data[offset];
6811 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6812 struct dcb_entry *dcbent, int crtc)
6814 struct drm_nouveau_private *dev_priv = dev->dev_private;
6815 struct nvbios *bios = &dev_priv->vbios;
6816 struct init_exec iexec = { true, false };
6818 spin_lock_bh(&bios->lock);
6819 bios->display.output = dcbent;
6820 bios->display.crtc = crtc;
6821 parse_init_table(bios, table, &iexec);
6822 bios->display.output = NULL;
6823 spin_unlock_bh(&bios->lock);
6826 static bool NVInitVBIOS(struct drm_device *dev)
6828 struct drm_nouveau_private *dev_priv = dev->dev_private;
6829 struct nvbios *bios = &dev_priv->vbios;
6831 memset(bios, 0, sizeof(struct nvbios));
6832 spin_lock_init(&bios->lock);
6835 if (!NVShadowVBIOS(dev, bios->data))
6838 bios->length = NV_PROM_SIZE;
6842 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6844 struct drm_nouveau_private *dev_priv = dev->dev_private;
6845 struct nvbios *bios = &dev_priv->vbios;
6846 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6847 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6850 offset = findstr(bios->data, bios->length,
6851 bit_signature, sizeof(bit_signature));
6853 NV_TRACE(dev, "BIT BIOS found\n");
6854 bios->type = NVBIOS_BIT;
6855 bios->offset = offset;
6856 return parse_bit_structure(bios, offset + 6);
6859 offset = findstr(bios->data, bios->length,
6860 bmp_signature, sizeof(bmp_signature));
6862 NV_TRACE(dev, "BMP BIOS found\n");
6863 bios->type = NVBIOS_BMP;
6864 bios->offset = offset;
6865 return parse_bmp_structure(dev, bios, offset);
6868 NV_ERROR(dev, "No known BIOS signature found\n");
6873 nouveau_run_vbios_init(struct drm_device *dev)
6875 struct drm_nouveau_private *dev_priv = dev->dev_private;
6876 struct nvbios *bios = &dev_priv->vbios;
6879 /* Reset the BIOS head to 0. */
6880 bios->state.crtchead = 0;
6882 if (bios->major_version < 5) /* BMP only */
6883 load_nv17_hw_sequencer_ucode(dev, bios);
6885 if (bios->execute) {
6886 bios->fp.last_script_invoc = 0;
6887 bios->fp.lvds_init_run = false;
6890 parse_init_tables(bios);
6893 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6894 * parser will run this right after the init tables, the binary
6895 * driver appears to run it at some point later.
6897 if (bios->some_script_ptr) {
6898 struct init_exec iexec = {true, false};
6900 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6901 bios->some_script_ptr);
6902 parse_init_table(bios, bios->some_script_ptr, &iexec);
6905 if (dev_priv->card_type >= NV_50) {
6906 for (i = 0; i < bios->dcb.entries; i++) {
6907 nouveau_bios_run_display_table(dev, 0, 0,
6908 &bios->dcb.entry[i], -1);
6916 nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6918 struct drm_nouveau_private *dev_priv = dev->dev_private;
6919 struct nvbios *bios = &dev_priv->vbios;
6920 struct dcb_i2c_entry *entry;
6923 entry = &bios->dcb.i2c[0];
6924 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6925 nouveau_i2c_fini(dev, entry);
6929 nouveau_bios_posted(struct drm_device *dev)
6931 struct drm_nouveau_private *dev_priv = dev->dev_private;
6934 if (dev_priv->card_type >= NV_50) {
6935 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6936 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6941 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6942 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6943 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6944 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6945 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6947 return (htotal != 0);
6951 nouveau_bios_init(struct drm_device *dev)
6953 struct drm_nouveau_private *dev_priv = dev->dev_private;
6954 struct nvbios *bios = &dev_priv->vbios;
6957 if (!NVInitVBIOS(dev))
6960 ret = nouveau_parse_vbios_struct(dev);
6964 ret = parse_dcb_table(dev, bios);
6968 fixup_legacy_i2c(bios);
6969 fixup_legacy_connector(bios);
6971 if (!bios->major_version) /* we don't run version 0 bios */
6974 /* init script execution disabled */
6975 bios->execute = false;
6977 /* ... unless card isn't POSTed already */
6978 if (!nouveau_bios_posted(dev)) {
6979 NV_INFO(dev, "Adaptor not initialised, "
6980 "running VBIOS init tables.\n");
6981 bios->execute = true;
6983 if (nouveau_force_post)
6984 bios->execute = true;
6986 ret = nouveau_run_vbios_init(dev);
6990 /* feature_byte on BMP is poor, but init always sets CR4B */
6991 if (bios->major_version < 5)
6992 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6994 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6995 if (bios->is_mobile || bios->major_version >= 5)
6996 ret = parse_fp_mode_table(dev, bios);
6998 /* allow subsequent scripts to execute */
6999 bios->execute = true;
7005 nouveau_bios_takedown(struct drm_device *dev)
7007 nouveau_bios_i2c_devices_takedown(dev);