drivers/gpu/drm/nouveau/core/include/core/class.h

   1 #ifndef __NOUVEAU_CLASS_H__
   2 #define __NOUVEAU_CLASS_H__
   3
   4 #include <nvif/class.h>
   5
   6 /* 0046: NV04_DISP
   7  */
   8
   9 #define NV04_DISP_CLASS                                              0x00000046
  10
  11 #define NV04_DISP_MTHD                                               0x00000000
  12 #define NV04_DISP_MTHD_HEAD                                          0x00000001
  13
  14 #define NV04_DISP_SCANOUTPOS                                         0x00000000
  15
  16 struct nv04_display_class {
  17 };
  18
  19 struct nv04_display_scanoutpos {
  20         s64 time[2];
  21         u32 vblanks;
  22         u32 vblanke;
  23         u32 vtotal;
  24         u32 vline;
  25         u32 hblanks;
  26         u32 hblanke;
  27         u32 htotal;
  28         u32 hline;
  29 };
  30
  31 /* 5070: NV50_DISP
  32  * 8270: NV84_DISP
  33  * 8370: NVA0_DISP
  34  * 8870: NV94_DISP
  35  * 8570: NVA3_DISP
  36  * 9070: NVD0_DISP
  37  * 9170: NVE0_DISP
  38  * 9270: NVF0_DISP
  39  * 9470: GM107_DISP
  40  */
  41
  42 #define NV50_DISP_CLASS                                              0x00005070
  43 #define NV84_DISP_CLASS                                              0x00008270
  44 #define NVA0_DISP_CLASS                                              0x00008370
  45 #define NV94_DISP_CLASS                                              0x00008870
  46 #define NVA3_DISP_CLASS                                              0x00008570
  47 #define NVD0_DISP_CLASS                                              0x00009070
  48 #define NVE0_DISP_CLASS                                              0x00009170
  49 #define NVF0_DISP_CLASS                                              0x00009270
  50 #define GM107_DISP_CLASS                                             0x00009470
  51
  52 #define NV50_DISP_MTHD_HEAD                                          0x00000003
  53
  54 #define NV50_DISP_SCANOUTPOS                                         0x00000000
  55
  56 #define NV50_DISP_SOR_MTHD                                           0x00010000
  57 #define NV50_DISP_SOR_MTHD_TYPE                                      0x0000f000
  58 #define NV50_DISP_SOR_MTHD_HEAD                                      0x00000018
  59 #define NV50_DISP_SOR_MTHD_LINK                                      0x00000004
  60 #define NV50_DISP_SOR_MTHD_OR                                        0x00000003
  61
  62 #define NV94_DISP_SOR_DP_PWR                                         0x00016000
  63 #define NV94_DISP_SOR_DP_PWR_STATE                                   0x00000001
  64 #define NV94_DISP_SOR_DP_PWR_STATE_OFF                               0x00000000
  65 #define NV94_DISP_SOR_DP_PWR_STATE_ON                                0x00000001
  66
  67 #define NV50_DISP_PIOR_MTHD                                          0x00030000
  68 #define NV50_DISP_PIOR_MTHD_TYPE                                     0x0000f000
  69 #define NV50_DISP_PIOR_MTHD_OR                                       0x00000003
  70
  71 #define NV50_DISP_PIOR_PWR                                           0x00030000
  72 #define NV50_DISP_PIOR_PWR_STATE                                     0x00000001
  73 #define NV50_DISP_PIOR_PWR_STATE_ON                                  0x00000001
  74 #define NV50_DISP_PIOR_PWR_STATE_OFF                                 0x00000000
  75 #define NV50_DISP_PIOR_TMDS_PWR                                      0x00032000
  76 #define NV50_DISP_PIOR_TMDS_PWR_STATE                                0x00000001
  77 #define NV50_DISP_PIOR_TMDS_PWR_STATE_ON                             0x00000001
  78 #define NV50_DISP_PIOR_TMDS_PWR_STATE_OFF                            0x00000000
  79 #define NV50_DISP_PIOR_DP_PWR                                        0x00036000
  80 #define NV50_DISP_PIOR_DP_PWR_STATE                                  0x00000001
  81 #define NV50_DISP_PIOR_DP_PWR_STATE_ON                               0x00000001
  82 #define NV50_DISP_PIOR_DP_PWR_STATE_OFF                              0x00000000
  83
  84 struct nv50_display_class {
  85 };
  86
  87 /* 507a: NV50_DISP_CURS
  88  * 827a: NV84_DISP_CURS
  89  * 837a: NVA0_DISP_CURS
  90  * 887a: NV94_DISP_CURS
  91  * 857a: NVA3_DISP_CURS
  92  * 907a: NVD0_DISP_CURS
  93  * 917a: NVE0_DISP_CURS
  94  * 927a: NVF0_DISP_CURS
  95  * 947a: GM107_DISP_CURS
  96  */
  97
  98 #define NV50_DISP_CURS_CLASS                                         0x0000507a
  99 #define NV84_DISP_CURS_CLASS                                         0x0000827a
 100 #define NVA0_DISP_CURS_CLASS                                         0x0000837a
 101 #define NV94_DISP_CURS_CLASS                                         0x0000887a
 102 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
 103 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
 104 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
 105 #define NVF0_DISP_CURS_CLASS                                         0x0000927a
 106 #define GM107_DISP_CURS_CLASS                                        0x0000947a
 107
 108 struct nv50_display_curs_class {
 109         u32 head;
 110 };
 111
 112 /* 507b: NV50_DISP_OIMM
 113  * 827b: NV84_DISP_OIMM
 114  * 837b: NVA0_DISP_OIMM
 115  * 887b: NV94_DISP_OIMM
 116  * 857b: NVA3_DISP_OIMM
 117  * 907b: NVD0_DISP_OIMM
 118  * 917b: NVE0_DISP_OIMM
 119  * 927b: NVE0_DISP_OIMM
 120  * 947b: GM107_DISP_OIMM
 121  */
 122
 123 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
 124 #define NV84_DISP_OIMM_CLASS                                         0x0000827b
 125 #define NVA0_DISP_OIMM_CLASS                                         0x0000837b
 126 #define NV94_DISP_OIMM_CLASS                                         0x0000887b
 127 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
 128 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
 129 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
 130 #define NVF0_DISP_OIMM_CLASS                                         0x0000927b
 131 #define GM107_DISP_OIMM_CLASS                                        0x0000947b
 132
 133 struct nv50_display_oimm_class {
 134         u32 head;
 135 };
 136
 137 /* 507c: NV50_DISP_SYNC
 138  * 827c: NV84_DISP_SYNC
 139  * 837c: NVA0_DISP_SYNC
 140  * 887c: NV94_DISP_SYNC
 141  * 857c: NVA3_DISP_SYNC
 142  * 907c: NVD0_DISP_SYNC
 143  * 917c: NVE0_DISP_SYNC
 144  * 927c: NVF0_DISP_SYNC
 145  * 947c: GM107_DISP_SYNC
 146  */
 147
 148 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
 149 #define NV84_DISP_SYNC_CLASS                                         0x0000827c
 150 #define NVA0_DISP_SYNC_CLASS                                         0x0000837c
 151 #define NV94_DISP_SYNC_CLASS                                         0x0000887c
 152 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 153 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 154 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
 155 #define NVF0_DISP_SYNC_CLASS                                         0x0000927c
 156 #define GM107_DISP_SYNC_CLASS                                        0x0000947c
 157
 158 struct nv50_display_sync_class {
 159         u32 pushbuf;
 160         u32 head;
 161 };
 162
 163 /* 507d: NV50_DISP_MAST
 164  * 827d: NV84_DISP_MAST
 165  * 837d: NVA0_DISP_MAST
 166  * 887d: NV94_DISP_MAST
 167  * 857d: NVA3_DISP_MAST
 168  * 907d: NVD0_DISP_MAST
 169  * 917d: NVE0_DISP_MAST
 170  * 927d: NVF0_DISP_MAST
 171  * 947d: GM107_DISP_MAST
 172  */
 173
 174 #define NV50_DISP_MAST_CLASS                                         0x0000507d
 175 #define NV84_DISP_MAST_CLASS                                         0x0000827d
 176 #define NVA0_DISP_MAST_CLASS                                         0x0000837d
 177 #define NV94_DISP_MAST_CLASS                                         0x0000887d
 178 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 179 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 180 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
 181 #define NVF0_DISP_MAST_CLASS                                         0x0000927d
 182 #define GM107_DISP_MAST_CLASS                                        0x0000947d
 183
 184 struct nv50_display_mast_class {
 185         u32 pushbuf;
 186 };
 187
 188 /* 507e: NV50_DISP_OVLY
 189  * 827e: NV84_DISP_OVLY
 190  * 837e: NVA0_DISP_OVLY
 191  * 887e: NV94_DISP_OVLY
 192  * 857e: NVA3_DISP_OVLY
 193  * 907e: NVD0_DISP_OVLY
 194  * 917e: NVE0_DISP_OVLY
 195  * 927e: NVF0_DISP_OVLY
 196  * 947e: GM107_DISP_OVLY
 197  */
 198
 199 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
 200 #define NV84_DISP_OVLY_CLASS                                         0x0000827e
 201 #define NVA0_DISP_OVLY_CLASS                                         0x0000837e
 202 #define NV94_DISP_OVLY_CLASS                                         0x0000887e
 203 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 204 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 205 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
 206 #define NVF0_DISP_OVLY_CLASS                                         0x0000927e
 207 #define GM107_DISP_OVLY_CLASS                                        0x0000947e
 208
 209 struct nv50_display_ovly_class {
 210         u32 pushbuf;
 211         u32 head;
 212 };
 213
 214 #endif