2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "fuc/hubnvc0.fuc.h"
27 #include "fuc/gpcnvc0.fuc.h"
29 /*******************************************************************************
30 * Graphics object classes
31 ******************************************************************************/
33 static struct nouveau_oclass
34 nvc0_graph_sclass[] = {
35 { 0x902d, &nouveau_object_ofuncs },
36 { 0x9039, &nouveau_object_ofuncs },
37 { 0x9097, &nouveau_object_ofuncs },
38 { 0x90c0, &nouveau_object_ofuncs },
42 static struct nouveau_oclass
43 nvc1_graph_sclass[] = {
44 { 0x902d, &nouveau_object_ofuncs },
45 { 0x9039, &nouveau_object_ofuncs },
46 { 0x9097, &nouveau_object_ofuncs },
47 { 0x90c0, &nouveau_object_ofuncs },
48 { 0x9197, &nouveau_object_ofuncs },
52 static struct nouveau_oclass
53 nvc8_graph_sclass[] = {
54 { 0x902d, &nouveau_object_ofuncs },
55 { 0x9039, &nouveau_object_ofuncs },
56 { 0x9097, &nouveau_object_ofuncs },
57 { 0x90c0, &nouveau_object_ofuncs },
58 { 0x9197, &nouveau_object_ofuncs },
59 { 0x9297, &nouveau_object_ofuncs },
63 /*******************************************************************************
65 ******************************************************************************/
68 nvc0_graph_context_ctor(struct nouveau_object *parent,
69 struct nouveau_object *engine,
70 struct nouveau_oclass *oclass, void *args, u32 size,
71 struct nouveau_object **pobject)
73 struct nouveau_vm *vm = nouveau_client(parent)->vm;
74 struct nvc0_graph_priv *priv = (void *)engine;
75 struct nvc0_graph_data *data = priv->mmio_data;
76 struct nvc0_graph_mmio *mmio = priv->mmio_list;
77 struct nvc0_graph_chan *chan;
80 /* allocate memory for context, and fill with default values */
81 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
83 NVOBJ_FLAG_ZERO_ALLOC, &chan);
84 *pobject = nv_object(chan);
88 /* allocate memory for a "mmio list" buffer that's used by the HUB
89 * fuc to modify some per-context register settings on first load
92 ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0x100, 0, &chan->mmio);
96 ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
97 NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
102 /* allocate buffers referenced by mmio list */
103 for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
104 ret = nouveau_gpuobj_new(parent, NULL, data->size, data->align,
105 0, &chan->data[i].mem);
109 ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
117 /* finally, fill in the mmio list and point the context at it */
118 for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
119 u32 addr = mmio->addr;
120 u32 data = mmio->data;
123 u64 info = chan->data[mmio->buffer].vma.offset;
124 data |= info >> mmio->shift;
127 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
128 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
132 for (i = 0; i < priv->size; i += 4)
133 nv_wo32(chan, i, priv->data[i / 4]);
135 if (!priv->firmware) {
136 nv_wo32(chan, 0x00, chan->mmio_nr / 2);
137 nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);
139 nv_wo32(chan, 0xf4, 0);
140 nv_wo32(chan, 0xf8, 0);
141 nv_wo32(chan, 0x10, chan->mmio_nr / 2);
142 nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset));
143 nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset));
144 nv_wo32(chan, 0x1c, 1);
145 nv_wo32(chan, 0x20, 0);
146 nv_wo32(chan, 0x28, 0);
147 nv_wo32(chan, 0x2c, 0);
154 nvc0_graph_context_dtor(struct nouveau_object *object)
156 struct nvc0_graph_chan *chan = (void *)object;
159 for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
160 nouveau_gpuobj_unmap(&chan->data[i].vma);
161 nouveau_gpuobj_ref(NULL, &chan->data[i].mem);
164 nouveau_gpuobj_unmap(&chan->mmio_vma);
165 nouveau_gpuobj_ref(NULL, &chan->mmio);
167 nouveau_graph_context_destroy(&chan->base);
170 static struct nouveau_oclass
171 nvc0_graph_cclass = {
172 .ofuncs = &(struct nouveau_ofuncs) {
173 .ctor = nvc0_graph_context_ctor,
174 .dtor = nvc0_graph_context_dtor,
175 .init = _nouveau_graph_context_init,
176 .fini = _nouveau_graph_context_fini,
177 .rd32 = _nouveau_graph_context_rd32,
178 .wr32 = _nouveau_graph_context_wr32,
182 /*******************************************************************************
183 * PGRAPH engine/subdev functions
184 ******************************************************************************/
187 nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
189 nv_error(priv, "%06x - done 0x%08x\n", base,
190 nv_rd32(priv, base + 0x400));
191 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
192 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
193 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
194 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
195 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
196 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
200 nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
202 u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
205 nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
206 for (gpc = 0; gpc < gpcnr; gpc++)
207 nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
211 nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
213 u32 ustat = nv_rd32(priv, 0x409c18);
215 if (ustat & 0x00000001)
216 nv_error(priv, "CTXCTRL ucode error\n");
217 if (ustat & 0x00080000)
218 nv_error(priv, "CTXCTRL watchdog timeout\n");
219 if (ustat & ~0x00080001)
220 nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
222 nvc0_graph_ctxctl_debug(priv);
223 nv_wr32(priv, 0x409c20, ustat);
227 nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
229 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
231 if (stat & 0x00000001) {
232 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
233 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
234 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
235 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000001);
239 if (stat & 0x00000002) {
240 u32 trap0 = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0644));
241 u32 trap1 = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x064c));
242 nv_error(priv, "GPC%d/TPC%d/MP: 0x%08x 0x%08x\n",
243 gpc, tpc, trap0, trap1);
244 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0644), 0x001ffffe);
245 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x064c), 0x0000000f);
246 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000002);
250 if (stat & 0x00000004) {
251 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
252 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
253 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
254 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000004);
258 if (stat & 0x00000008) {
259 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
260 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
261 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
262 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000008);
267 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
268 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), stat);
273 nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
275 u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
278 if (stat & 0x00000001) {
279 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
280 nv_error(priv, "GPC%d/PROP: 0x%08x\n", gpc, trap);
281 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
282 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000001);
286 if (stat & 0x00000002) {
287 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
288 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
289 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
290 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000002);
294 if (stat & 0x00000004) {
295 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
296 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
297 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
298 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000004);
302 if (stat & 0x00000008) {
303 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
304 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
305 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
306 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000008);
310 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
311 u32 mask = 0x00010000 << tpc;
313 nvc0_graph_trap_tpc(priv, gpc, tpc);
314 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
320 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
321 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), stat);
326 nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
328 u32 trap = nv_rd32(priv, 0x400108);
331 if (trap & 0x00000001) {
332 u32 stat = nv_rd32(priv, 0x404000);
333 nv_error(priv, "DISPATCH 0x%08x\n", stat);
334 nv_wr32(priv, 0x404000, 0xc0000000);
335 nv_wr32(priv, 0x400108, 0x00000001);
339 if (trap & 0x00000002) {
340 u32 stat = nv_rd32(priv, 0x404600);
341 nv_error(priv, "M2MF 0x%08x\n", stat);
342 nv_wr32(priv, 0x404600, 0xc0000000);
343 nv_wr32(priv, 0x400108, 0x00000002);
347 if (trap & 0x00000008) {
348 u32 stat = nv_rd32(priv, 0x408030);
349 nv_error(priv, "CCACHE 0x%08x\n", stat);
350 nv_wr32(priv, 0x408030, 0xc0000000);
351 nv_wr32(priv, 0x400108, 0x00000008);
355 if (trap & 0x00000010) {
356 u32 stat = nv_rd32(priv, 0x405840);
357 nv_error(priv, "SHADER 0x%08x\n", stat);
358 nv_wr32(priv, 0x405840, 0xc0000000);
359 nv_wr32(priv, 0x400108, 0x00000010);
363 if (trap & 0x00000040) {
364 u32 stat = nv_rd32(priv, 0x40601c);
365 nv_error(priv, "UNK6 0x%08x\n", stat);
366 nv_wr32(priv, 0x40601c, 0xc0000000);
367 nv_wr32(priv, 0x400108, 0x00000040);
371 if (trap & 0x00000080) {
372 u32 stat = nv_rd32(priv, 0x404490);
373 nv_error(priv, "MACRO 0x%08x\n", stat);
374 nv_wr32(priv, 0x404490, 0xc0000000);
375 nv_wr32(priv, 0x400108, 0x00000080);
379 if (trap & 0x01000000) {
380 u32 stat = nv_rd32(priv, 0x400118);
381 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
382 u32 mask = 0x00000001 << gpc;
384 nvc0_graph_trap_gpc(priv, gpc);
385 nv_wr32(priv, 0x400118, mask);
389 nv_wr32(priv, 0x400108, 0x01000000);
393 if (trap & 0x02000000) {
394 for (rop = 0; rop < priv->rop_nr; rop++) {
395 u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
396 u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
397 nv_error(priv, "ROP%d 0x%08x 0x%08x\n",
399 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
400 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
402 nv_wr32(priv, 0x400108, 0x02000000);
407 nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap);
408 nv_wr32(priv, 0x400108, trap);
413 nvc0_graph_intr(struct nouveau_subdev *subdev)
415 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
416 struct nouveau_engine *engine = nv_engine(subdev);
417 struct nouveau_object *engctx;
418 struct nouveau_handle *handle;
419 struct nvc0_graph_priv *priv = (void *)subdev;
420 u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
421 u32 stat = nv_rd32(priv, 0x400100);
422 u32 addr = nv_rd32(priv, 0x400704);
423 u32 mthd = (addr & 0x00003ffc);
424 u32 subc = (addr & 0x00070000) >> 16;
425 u32 data = nv_rd32(priv, 0x400708);
426 u32 code = nv_rd32(priv, 0x400110);
427 u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
430 engctx = nouveau_engctx_get(engine, inst);
431 chid = pfifo->chid(pfifo, engctx);
433 if (stat & 0x00000010) {
434 handle = nouveau_handle_get_class(engctx, class);
435 if (!handle || nv_call(handle->object, mthd, data)) {
436 nv_error(priv, "ILLEGAL_MTHD ch %d [0x%010llx] "
437 "subc %d class 0x%04x mthd 0x%04x "
439 chid, inst << 12, subc, class, mthd, data);
441 nouveau_handle_put(handle);
442 nv_wr32(priv, 0x400100, 0x00000010);
446 if (stat & 0x00000020) {
447 nv_error(priv, "ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
448 "class 0x%04x mthd 0x%04x data 0x%08x\n",
449 chid, inst << 12, subc, class, mthd, data);
450 nv_wr32(priv, 0x400100, 0x00000020);
454 if (stat & 0x00100000) {
455 nv_error(priv, "DATA_ERROR [");
456 nouveau_enum_print(nv50_data_error_names, code);
457 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
458 "mthd 0x%04x data 0x%08x\n",
459 chid, inst << 12, subc, class, mthd, data);
460 nv_wr32(priv, 0x400100, 0x00100000);
464 if (stat & 0x00200000) {
465 nv_error(priv, "TRAP ch %d [0x%010llx]\n", chid, inst << 12);
466 nvc0_graph_trap_intr(priv);
467 nv_wr32(priv, 0x400100, 0x00200000);
471 if (stat & 0x00080000) {
472 nvc0_graph_ctxctl_isr(priv);
473 nv_wr32(priv, 0x400100, 0x00080000);
478 nv_error(priv, "unknown stat 0x%08x\n", stat);
479 nv_wr32(priv, 0x400100, stat);
482 nv_wr32(priv, 0x400500, 0x00010001);
483 nouveau_engctx_put(engctx);
487 nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
488 struct nvc0_graph_fuc *fuc)
490 struct nouveau_device *device = nv_device(priv);
491 const struct firmware *fw;
495 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
496 ret = request_firmware(&fw, f, &device->pdev->dev);
498 snprintf(f, sizeof(f), "nouveau/%s", fwname);
499 ret = request_firmware(&fw, f, &device->pdev->dev);
501 nv_error(priv, "failed to load %s\n", fwname);
506 fuc->size = fw->size;
507 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
508 release_firmware(fw);
509 return (fuc->data != NULL) ? 0 : -ENOMEM;
513 nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
514 struct nouveau_oclass *oclass, void *data, u32 size,
515 struct nouveau_object **pobject)
517 struct nouveau_device *device = nv_device(parent);
518 struct nvc0_graph_priv *priv;
522 switch (device->chipset) {
523 case 0xd9: /* known broken without binary driver firmware */
530 ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
531 *pobject = nv_object(priv);
535 nv_subdev(priv)->unit = 0x18001000;
536 nv_subdev(priv)->intr = nvc0_graph_intr;
537 nv_engine(priv)->cclass = &nvc0_graph_cclass;
539 if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
540 nv_info(priv, "using external firmware\n");
541 if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
542 nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
543 nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
544 nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
546 priv->firmware = true;
549 switch (nvc0_graph_class(priv)) {
551 nv_engine(priv)->sclass = nvc0_graph_sclass;
554 nv_engine(priv)->sclass = nvc1_graph_sclass;
557 nv_engine(priv)->sclass = nvc8_graph_sclass;
561 ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 256, 0, &priv->unk4188b4);
565 ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 256, 0, &priv->unk4188b8);
569 for (i = 0; i < 0x1000; i += 4) {
570 nv_wo32(priv->unk4188b4, i, 0x00000010);
571 nv_wo32(priv->unk4188b8, i, 0x00000010);
574 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
575 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
576 for (i = 0; i < priv->gpc_nr; i++) {
577 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
578 priv->tpc_total += priv->tpc_nr[i];
581 /*XXX: these need figuring out... though it might not even matter */
582 switch (nv_device(priv)->chipset) {
584 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
585 priv->magic_not_rop_nr = 0x07;
587 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
588 priv->magic_not_rop_nr = 0x05;
590 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
591 priv->magic_not_rop_nr = 0x06;
594 case 0xc3: /* 450, 4/0/0/0, 2 */
595 priv->magic_not_rop_nr = 0x03;
597 case 0xc4: /* 460, 3/4/0/0, 4 */
598 priv->magic_not_rop_nr = 0x01;
600 case 0xc1: /* 2/0/0/0, 1 */
601 priv->magic_not_rop_nr = 0x01;
603 case 0xc8: /* 4/4/3/4, 5 */
604 priv->magic_not_rop_nr = 0x06;
606 case 0xce: /* 4/4/0/0, 4 */
607 priv->magic_not_rop_nr = 0x03;
609 case 0xcf: /* 4/0/0/0, 3 */
610 priv->magic_not_rop_nr = 0x03;
612 case 0xd9: /* 1/0/0/0, 1 */
613 priv->magic_not_rop_nr = 0x01;
621 nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
630 nvc0_graph_dtor(struct nouveau_object *object)
632 struct nvc0_graph_priv *priv = (void *)object;
637 nvc0_graph_dtor_fw(&priv->fuc409c);
638 nvc0_graph_dtor_fw(&priv->fuc409d);
639 nvc0_graph_dtor_fw(&priv->fuc41ac);
640 nvc0_graph_dtor_fw(&priv->fuc41ad);
642 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
643 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
645 nouveau_graph_destroy(&priv->base);
649 nvc0_graph_init_obj418880(struct nvc0_graph_priv *priv)
653 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
654 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
655 for (i = 0; i < 4; i++)
656 nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
657 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
658 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
662 nvc0_graph_init_regs(struct nvc0_graph_priv *priv)
664 nv_wr32(priv, 0x400080, 0x003083c2);
665 nv_wr32(priv, 0x400088, 0x00006fe7);
666 nv_wr32(priv, 0x40008c, 0x00000000);
667 nv_wr32(priv, 0x400090, 0x00000030);
668 nv_wr32(priv, 0x40013c, 0x013901f7);
669 nv_wr32(priv, 0x400140, 0x00000100);
670 nv_wr32(priv, 0x400144, 0x00000000);
671 nv_wr32(priv, 0x400148, 0x00000110);
672 nv_wr32(priv, 0x400138, 0x00000000);
673 nv_wr32(priv, 0x400130, 0x00000000);
674 nv_wr32(priv, 0x400134, 0x00000000);
675 nv_wr32(priv, 0x400124, 0x00000002);
679 nvc0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
681 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
682 u32 data[TPC_MAX / 8];
686 nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
689 * TP ROP UNKVAL(magic_not_rop_nr)
697 memset(data, 0x00, sizeof(data));
698 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
699 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
701 gpc = (gpc + 1) % priv->gpc_nr;
702 } while (!tpcnr[gpc]);
703 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
705 data[i / 8] |= tpc << ((i % 8) * 4);
708 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
709 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
710 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
711 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
713 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
714 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
716 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
717 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
720 nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
721 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
725 nvc0_graph_init_units(struct nvc0_graph_priv *priv)
727 nv_wr32(priv, 0x409c24, 0x000f0000);
728 nv_wr32(priv, 0x404000, 0xc0000000); /* DISPATCH */
729 nv_wr32(priv, 0x404600, 0xc0000000); /* M2MF */
730 nv_wr32(priv, 0x408030, 0xc0000000);
731 nv_wr32(priv, 0x40601c, 0xc0000000);
732 nv_wr32(priv, 0x404490, 0xc0000000); /* MACRO */
733 nv_wr32(priv, 0x406018, 0xc0000000);
734 nv_wr32(priv, 0x405840, 0xc0000000);
735 nv_wr32(priv, 0x405844, 0x00ffffff);
736 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
737 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
741 nvc0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
745 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
746 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
747 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
748 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
749 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
750 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
751 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
752 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
753 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
754 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
755 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
756 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
757 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
759 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
760 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
765 nvc0_graph_init_rop(struct nvc0_graph_priv *priv)
769 for (rop = 0; rop < priv->rop_nr; rop++) {
770 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
771 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
772 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
773 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
778 nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
779 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
783 nv_wr32(priv, fuc_base + 0x01c0, 0x01000000);
784 for (i = 0; i < data->size / 4; i++)
785 nv_wr32(priv, fuc_base + 0x01c4, data->data[i]);
787 nv_wr32(priv, fuc_base + 0x0180, 0x01000000);
788 for (i = 0; i < code->size / 4; i++) {
790 nv_wr32(priv, fuc_base + 0x0188, i >> 6);
791 nv_wr32(priv, fuc_base + 0x0184, code->data[i]);
796 nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
801 if (priv->firmware) {
802 /* load fuc microcode */
803 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
804 nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c,
806 nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac,
808 nv_wr32(priv, 0x000260, r000260);
810 /* start both of them running */
811 nv_wr32(priv, 0x409840, 0xffffffff);
812 nv_wr32(priv, 0x41a10c, 0x00000000);
813 nv_wr32(priv, 0x40910c, 0x00000000);
814 nv_wr32(priv, 0x41a100, 0x00000002);
815 nv_wr32(priv, 0x409100, 0x00000002);
816 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
817 nv_warn(priv, "0x409800 wait failed\n");
819 nv_wr32(priv, 0x409840, 0xffffffff);
820 nv_wr32(priv, 0x409500, 0x7fffffff);
821 nv_wr32(priv, 0x409504, 0x00000021);
823 nv_wr32(priv, 0x409840, 0xffffffff);
824 nv_wr32(priv, 0x409500, 0x00000000);
825 nv_wr32(priv, 0x409504, 0x00000010);
826 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
827 nv_error(priv, "fuc09 req 0x10 timeout\n");
830 priv->size = nv_rd32(priv, 0x409800);
832 nv_wr32(priv, 0x409840, 0xffffffff);
833 nv_wr32(priv, 0x409500, 0x00000000);
834 nv_wr32(priv, 0x409504, 0x00000016);
835 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
836 nv_error(priv, "fuc09 req 0x16 timeout\n");
840 nv_wr32(priv, 0x409840, 0xffffffff);
841 nv_wr32(priv, 0x409500, 0x00000000);
842 nv_wr32(priv, 0x409504, 0x00000025);
843 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
844 nv_error(priv, "fuc09 req 0x25 timeout\n");
848 if (priv->data == NULL) {
849 int ret = nvc0_grctx_generate(priv);
851 nv_error(priv, "failed to construct context\n");
859 /* load HUB microcode */
860 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
861 nv_wr32(priv, 0x4091c0, 0x01000000);
862 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
863 nv_wr32(priv, 0x4091c4, nvc0_grhub_data[i]);
865 nv_wr32(priv, 0x409180, 0x01000000);
866 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
868 nv_wr32(priv, 0x409188, i >> 6);
869 nv_wr32(priv, 0x409184, nvc0_grhub_code[i]);
872 /* load GPC microcode */
873 nv_wr32(priv, 0x41a1c0, 0x01000000);
874 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
875 nv_wr32(priv, 0x41a1c4, nvc0_grgpc_data[i]);
877 nv_wr32(priv, 0x41a180, 0x01000000);
878 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
880 nv_wr32(priv, 0x41a188, i >> 6);
881 nv_wr32(priv, 0x41a184, nvc0_grgpc_code[i]);
883 nv_wr32(priv, 0x000260, r000260);
885 /* start HUB ucode running, it'll init the GPCs */
886 nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
887 nv_wr32(priv, 0x40910c, 0x00000000);
888 nv_wr32(priv, 0x409100, 0x00000002);
889 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
890 nv_error(priv, "HUB_INIT timed out\n");
891 nvc0_graph_ctxctl_debug(priv);
895 priv->size = nv_rd32(priv, 0x409804);
896 if (priv->data == NULL) {
897 int ret = nvc0_grctx_generate(priv);
899 nv_error(priv, "failed to construct context\n");
908 nvc0_graph_init(struct nouveau_object *object)
910 struct nvc0_graph_priv *priv = (void *)object;
913 ret = nouveau_graph_init(&priv->base);
917 nvc0_graph_init_obj418880(priv);
918 nvc0_graph_init_regs(priv);
919 /*nvc0_graph_init_unitplemented_magics(priv);*/
920 nvc0_graph_init_gpc_0(priv);
921 /*nvc0_graph_init_unitplemented_c242(priv);*/
923 nv_wr32(priv, 0x400500, 0x00010001);
924 nv_wr32(priv, 0x400100, 0xffffffff);
925 nv_wr32(priv, 0x40013c, 0xffffffff);
927 nvc0_graph_init_units(priv);
928 nvc0_graph_init_gpc_1(priv);
929 nvc0_graph_init_rop(priv);
931 nv_wr32(priv, 0x400108, 0xffffffff);
932 nv_wr32(priv, 0x400138, 0xffffffff);
933 nv_wr32(priv, 0x400118, 0xffffffff);
934 nv_wr32(priv, 0x400130, 0xffffffff);
935 nv_wr32(priv, 0x40011c, 0xffffffff);
936 nv_wr32(priv, 0x400134, 0xffffffff);
937 nv_wr32(priv, 0x400054, 0x34ce3464);
939 ret = nvc0_graph_init_ctxctl(priv);
946 struct nouveau_oclass
947 nvc0_graph_oclass = {
948 .handle = NV_ENGINE(GR, 0xc0),
949 .ofuncs = &(struct nouveau_ofuncs) {
950 .ctor = nvc0_graph_ctor,
951 .dtor = nvc0_graph_dtor,
952 .init = nvc0_graph_init,
953 .fini = _nouveau_graph_fini,