1 /* fuc microcode for nve0 PGRAPH/GPC
3 * Copyright 2011 Red Hat Inc.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 * m4 nve0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nve0_grgpc.fuc.h
31 * - bracket certain functions with scratch writes, useful for debugging
32 * - watchdog timer around ctx operations
35 .section #nve0_grgpc_data
38 gpc_mmio_list_head: .b32 0
39 gpc_mmio_list_tail: .b32 0
43 tpc_mmio_list_head: .b32 0
44 tpc_mmio_list_tail: .b32 0
48 // chipset descriptions
51 .b16 #nve4_gpc_mmio_head
52 .b16 #nve4_gpc_mmio_tail
53 .b16 #nve4_tpc_mmio_head
54 .b16 #nve4_tpc_mmio_tail
56 .b16 #nve4_gpc_mmio_head
57 .b16 #nve4_gpc_mmio_tail
58 .b16 #nve4_tpc_mmio_head
59 .b16 #nve4_tpc_mmio_tail
64 mmctx_data(0x000380, 1)
65 mmctx_data(0x000400, 2)
66 mmctx_data(0x00040c, 3)
67 mmctx_data(0x000450, 9)
68 mmctx_data(0x000600, 1)
69 mmctx_data(0x000684, 1)
70 mmctx_data(0x000700, 5)
71 mmctx_data(0x000800, 1)
72 mmctx_data(0x000808, 3)
73 mmctx_data(0x000828, 1)
74 mmctx_data(0x000830, 1)
75 mmctx_data(0x0008d8, 1)
76 mmctx_data(0x0008e0, 1)
77 mmctx_data(0x0008e8, 6)
78 mmctx_data(0x00091c, 1)
79 mmctx_data(0x000924, 3)
80 mmctx_data(0x000b00, 1)
81 mmctx_data(0x000b08, 6)
82 mmctx_data(0x000bb8, 1)
83 mmctx_data(0x000c08, 1)
84 mmctx_data(0x000c10, 8)
85 mmctx_data(0x000c40, 1)
86 mmctx_data(0x000c6c, 1)
87 mmctx_data(0x000c80, 1)
88 mmctx_data(0x000c8c, 1)
89 mmctx_data(0x001000, 3)
90 mmctx_data(0x001014, 1)
91 mmctx_data(0x003024, 1)
92 mmctx_data(0x0030c0, 2)
93 mmctx_data(0x0030e4, 1)
94 mmctx_data(0x003100, 6)
95 mmctx_data(0x0031d0, 1)
96 mmctx_data(0x0031e0, 2)
101 mmctx_data(0x000048, 1)
102 mmctx_data(0x000064, 1)
103 mmctx_data(0x000088, 1)
104 mmctx_data(0x000200, 6)
105 mmctx_data(0x00021c, 2)
106 mmctx_data(0x000230, 1)
107 mmctx_data(0x0002c4, 1)
108 mmctx_data(0x000400, 3)
109 mmctx_data(0x000420, 3)
110 mmctx_data(0x0004e8, 1)
111 mmctx_data(0x0004f4, 1)
112 mmctx_data(0x000604, 4)
113 mmctx_data(0x000644, 22)
114 mmctx_data(0x0006ac, 2)
115 mmctx_data(0x0006c8, 1)
116 mmctx_data(0x000730, 8)
117 mmctx_data(0x000758, 1)
118 mmctx_data(0x000778, 1)
121 .section #nve0_grgpc_code
123 define(`include_code')
126 // reports an exception to the host
128 // In: $r15 error code (see nve0.fuc)
132 mov $r14 -0x67ec // 0x9814
134 call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
137 call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET
141 // GPC fuc initialisation, executed by triggering ucode start, will
142 // fall through to main loop after completion.
145 // CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
146 // CC_SCRATCH[1]: context base
150 // 31:31: set to signal completion
152 // 31:0: GPC context size
158 // enable fifo access
161 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
163 // setup i0 handler, and route all interrupts to it
167 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
169 // enable fifo interrupt
171 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
176 // figure out which GPC we are, and how many TPCs we have
179 iord $r2 I[$r1 + 0x000] // UNITS
184 st b32 D[$r0 + #tpc_count] $r2
185 st b32 D[$r0 + #tpc_mask] $r3
187 iord $r2 I[$r1 + 0x000] // MYINDEX
188 st b32 D[$r0 + #gpc_id] $r2
190 // find context data for this chipset
193 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
194 mov $r1 #chipsets - 12
197 ld b32 $r3 D[$r1 + 0x00]
201 bra ne #init_find_chipset
205 // initialise context base, and size tracking
209 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
210 clear b32 $r3 // track GPC context size here
212 // set mmctx base addresses now so we don't have to do it later,
213 // they don't currently ever change
217 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
218 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
220 // calculate GPC mmio context size, store the chipset-specific
221 // mmio list pointers somewhere we can get at them later without
222 // re-parsing the chipset list
225 ld b16 $r14 D[$r1 + 4]
226 ld b16 $r15 D[$r1 + 6]
227 st b16 D[$r0 + #gpc_mmio_list_head] $r14
228 st b16 D[$r0 + #gpc_mmio_list_tail] $r15
233 // calculate per-TPC mmio context size, store the list pointers
234 ld b16 $r14 D[$r1 + 8]
235 ld b16 $r15 D[$r1 + 10]
236 st b16 D[$r0 + #tpc_mmio_list_head] $r14
237 st b16 D[$r0 + #tpc_mmio_list_tail] $r15
239 ld b32 $r14 D[$r0 + #tpc_count]
244 // round up base/size to 256 byte boundary (for strand SWBASE)
247 iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
255 // calculate size of strand context data
257 call #strand_ctx_init
260 // save context size, and tell HUB we're done
263 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
267 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
269 // Main program loop, very simple, sleeps until woken up by the interrupt
270 // handler, pulls a command from the queue and executes its handler
279 // 0x0000-0x0003 are all context transfers
281 bra nc #main_not_ctx_xfer
282 // fetch $flags and mask off $p1/$p2
287 // set $p1/$p2 according to transfer type
291 // transfer context data
297 or $r15 E_BAD_COMMAND
313 // incoming fifo command?
314 iord $r10 I[$r0 + 0x200] // INTR
315 and $r11 $r10 0x00000004
317 // queue incoming fifo command for later processing
320 iord $r14 I[$r11 + 0x100] // FIFO_CMD
321 iord $r15 I[$r11 + 0x000] // FIFO_DATA
325 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
327 // ack, and wake up main()
329 iowr I[$r0 + 0x100] $r10 // INTR_ACK
343 // Set this GPC's bit in HUB_BAR, used to signal completion of various
344 // activities to the HUB fuc
348 ld b32 $r14 D[$r0 + #gpc_id]
350 mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
355 // Disables various things, waits a bit, and re-enables them..
357 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
358 // good description for the bits we turn off? Anyways, without this,
359 // funny things happen.
365 iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
369 bra ne #ctx_redswitch_delay
371 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
374 // Transfer GPC context data between GPU and storage area
376 // In: $r15 context base address
377 // $p1 clear on save, set on load
378 // $p2 set if opposite direction done/will be done, so:
379 // on save it means: "a load will follow this save"
380 // on load it means: "a save preceeded this load"
383 // set context base address
386 iowr I[$r1 + 0x000] $r15// MEM_BASE
387 bra not $p1 #ctx_xfer_not_load
395 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
399 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
402 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
405 xbit $r10 $flags $p1 // direction
409 ld b32 $r12 D[$r0 + #gpc_id]
411 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
412 ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
413 ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
414 mov $r14 0 // not multi
417 // per-TPC mmio context
418 xbit $r10 $flags $p1 // direction
421 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
422 ld b32 $r12 D[$r0 + #gpc_id]
424 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
425 ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
426 ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
427 ld b32 $r15 D[$r0 + #tpc_mask]
428 mov $r14 0x800 // stride = 0x800
431 // wait for strands to finish
434 // if load, or a save without a load following, do some
435 // unknown stuff that's done after finishing a block of
437 bra $p1 #ctx_xfer_post
438 bra not $p2 #ctx_xfer_done
443 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
446 // mark completion in HUB's barrier
448 call #hub_barrier_done