drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/object.h>
  26 #include <core/parent.h>
  27 #include <core/handle.h>
  28 #include <core/class.h>
  29
  30 #include <engine/software.h>
  31 #include <engine/disp.h>
  32
  33 #include <subdev/bios.h>
  34 #include <subdev/bios/dcb.h>
  35 #include <subdev/bios/disp.h>
  36 #include <subdev/bios/init.h>
  37 #include <subdev/bios/pll.h>
  38 #include <subdev/timer.h>
  39 #include <subdev/fb.h>
  40 #include <subdev/bar.h>
  41 #include <subdev/clock.h>
  42
  43 #include "nv50.h"
  44
  45 /*******************************************************************************
  46  * EVO channel base class
  47  ******************************************************************************/
  48
  49 int
  50 nv50_disp_chan_create_(struct nouveau_object *parent,
  51                        struct nouveau_object *engine,
  52                        struct nouveau_oclass *oclass, int chid,
  53                        int length, void **pobject)
  54 {
  55         struct nv50_disp_base *base = (void *)parent;
  56         struct nv50_disp_chan *chan;
  57         int ret;
  58
  59         if (base->chan & (1 << chid))
  60                 return -EBUSY;
  61         base->chan |= (1 << chid);
  62
  63         ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
  64                                      (1ULL << NVDEV_ENGINE_DMAOBJ),
  65                                      length, pobject);
  66         chan = *pobject;
  67         if (ret)
  68                 return ret;
  69
  70         chan->chid = chid;
  71         return 0;
  72 }
  73
  74 void
  75 nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
  76 {
  77         struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
  78         base->chan &= ~(1 << chan->chid);
  79         nouveau_namedb_destroy(&chan->base);
  80 }
  81
  82 u32
  83 nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
  84 {
  85         struct nv50_disp_priv *priv = (void *)object->engine;
  86         struct nv50_disp_chan *chan = (void *)object;
  87         return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);
  88 }
  89
  90 void
  91 nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
  92 {
  93         struct nv50_disp_priv *priv = (void *)object->engine;
  94         struct nv50_disp_chan *chan = (void *)object;
  95         nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);
  96 }
  97
  98 /*******************************************************************************
  99  * EVO DMA channel base class
 100  ******************************************************************************/
 101
 102 static int
 103 nv50_disp_dmac_object_attach(struct nouveau_object *parent,
 104                              struct nouveau_object *object, u32 name)
 105 {
 106         struct nv50_disp_base *base = (void *)parent->parent;
 107         struct nv50_disp_chan *chan = (void *)parent;
 108         u32 addr = nv_gpuobj(object)->node->offset;
 109         u32 chid = chan->chid;
 110         u32 data = (chid << 28) | (addr << 10) | chid;
 111         return nouveau_ramht_insert(base->ramht, chid, name, data);
 112 }
 113
 114 static void
 115 nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
 116 {
 117         struct nv50_disp_base *base = (void *)parent->parent;
 118         nouveau_ramht_remove(base->ramht, cookie);
 119 }
 120
 121 int
 122 nv50_disp_dmac_create_(struct nouveau_object *parent,
 123                        struct nouveau_object *engine,
 124                        struct nouveau_oclass *oclass, u32 pushbuf, int chid,
 125                        int length, void **pobject)
 126 {
 127         struct nv50_disp_dmac *dmac;
 128         int ret;
 129
 130         ret = nv50_disp_chan_create_(parent, engine, oclass, chid,
 131                                      length, pobject);
 132         dmac = *pobject;
 133         if (ret)
 134                 return ret;
 135
 136         dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
 137         if (!dmac->pushdma)
 138                 return -ENOENT;
 139
 140         switch (nv_mclass(dmac->pushdma)) {
 141         case 0x0002:
 142         case 0x003d:
 143                 if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff)
 144                         return -EINVAL;
 145
 146                 switch (dmac->pushdma->target) {
 147                 case NV_MEM_TARGET_VRAM:
 148                         dmac->push = 0x00000000 | dmac->pushdma->start >> 8;
 149                         break;
 150                 case NV_MEM_TARGET_PCI_NOSNOOP:
 151                         dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
 152                         break;
 153                 default:
 154                         return -EINVAL;
 155                 }
 156                 break;
 157         default:
 158                 return -EINVAL;
 159         }
 160
 161         return 0;
 162 }
 163
 164 void
 165 nv50_disp_dmac_dtor(struct nouveau_object *object)
 166 {
 167         struct nv50_disp_dmac *dmac = (void *)object;
 168         nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
 169         nv50_disp_chan_destroy(&dmac->base);
 170 }
 171
 172 static int
 173 nv50_disp_dmac_init(struct nouveau_object *object)
 174 {
 175         struct nv50_disp_priv *priv = (void *)object->engine;
 176         struct nv50_disp_dmac *dmac = (void *)object;
 177         int chid = dmac->base.chid;
 178         int ret;
 179
 180         ret = nv50_disp_chan_init(&dmac->base);
 181         if (ret)
 182                 return ret;
 183
 184         /* enable error reporting */
 185         nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
 186
 187         /* initialise channel for dma command submission */
 188         nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
 189         nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
 190         nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
 191         nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
 192         nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
 193         nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
 194
 195         /* wait for it to go inactive */
 196         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
 197                 nv_error(dmac, "init timeout, 0x%08x\n",
 198                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 199                 return -EBUSY;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int
 206 nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
 207 {
 208         struct nv50_disp_priv *priv = (void *)object->engine;
 209         struct nv50_disp_dmac *dmac = (void *)object;
 210         int chid = dmac->base.chid;
 211
 212         /* deactivate channel */
 213         nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
 214         nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
 215         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {
 216                 nv_error(dmac, "fini timeout, 0x%08x\n",
 217                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 218                 if (suspend)
 219                         return -EBUSY;
 220         }
 221
 222         /* disable error reporting */
 223         nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
 224
 225         return nv50_disp_chan_fini(&dmac->base, suspend);
 226 }
 227
 228 /*******************************************************************************
 229  * EVO master channel object
 230  ******************************************************************************/
 231
 232 static int
 233 nv50_disp_mast_ctor(struct nouveau_object *parent,
 234                     struct nouveau_object *engine,
 235                     struct nouveau_oclass *oclass, void *data, u32 size,
 236                     struct nouveau_object **pobject)
 237 {
 238         struct nv50_display_mast_class *args = data;
 239         struct nv50_disp_dmac *mast;
 240         int ret;
 241
 242         if (size < sizeof(*args))
 243                 return -EINVAL;
 244
 245         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 246                                      0, sizeof(*mast), (void **)&mast);
 247         *pobject = nv_object(mast);
 248         if (ret)
 249                 return ret;
 250
 251         nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach;
 252         nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach;
 253         return 0;
 254 }
 255
 256 static int
 257 nv50_disp_mast_init(struct nouveau_object *object)
 258 {
 259         struct nv50_disp_priv *priv = (void *)object->engine;
 260         struct nv50_disp_dmac *mast = (void *)object;
 261         int ret;
 262
 263         ret = nv50_disp_chan_init(&mast->base);
 264         if (ret)
 265                 return ret;
 266
 267         /* enable error reporting */
 268         nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
 269
 270         /* attempt to unstick channel from some unknown state */
 271         if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
 272                 nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
 273         if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
 274                 nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
 275
 276         /* initialise channel for dma command submission */
 277         nv_wr32(priv, 0x610204, mast->push);
 278         nv_wr32(priv, 0x610208, 0x00010000);
 279         nv_wr32(priv, 0x61020c, 0x00000000);
 280         nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
 281         nv_wr32(priv, 0x640000, 0x00000000);
 282         nv_wr32(priv, 0x610200, 0x01000013);
 283
 284         /* wait for it to go inactive */
 285         if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
 286                 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
 287                 return -EBUSY;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int
 294 nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
 295 {
 296         struct nv50_disp_priv *priv = (void *)object->engine;
 297         struct nv50_disp_dmac *mast = (void *)object;
 298
 299         /* deactivate channel */
 300         nv_mask(priv, 0x610200, 0x00000010, 0x00000000);
 301         nv_mask(priv, 0x610200, 0x00000003, 0x00000000);
 302         if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) {
 303                 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200));
 304                 if (suspend)
 305                         return -EBUSY;
 306         }
 307
 308         /* disable error reporting */
 309         nv_mask(priv, 0x610028, 0x00010001, 0x00000000);
 310
 311         return nv50_disp_chan_fini(&mast->base, suspend);
 312 }
 313
 314 struct nouveau_ofuncs
 315 nv50_disp_mast_ofuncs = {
 316         .ctor = nv50_disp_mast_ctor,
 317         .dtor = nv50_disp_dmac_dtor,
 318         .init = nv50_disp_mast_init,
 319         .fini = nv50_disp_mast_fini,
 320         .rd32 = nv50_disp_chan_rd32,
 321         .wr32 = nv50_disp_chan_wr32,
 322 };
 323
 324 /*******************************************************************************
 325  * EVO sync channel objects
 326  ******************************************************************************/
 327
 328 static int
 329 nv50_disp_sync_ctor(struct nouveau_object *parent,
 330                     struct nouveau_object *engine,
 331                     struct nouveau_oclass *oclass, void *data, u32 size,
 332                     struct nouveau_object **pobject)
 333 {
 334         struct nv50_display_sync_class *args = data;
 335         struct nv50_disp_dmac *dmac;
 336         int ret;
 337
 338         if (size < sizeof(*data) || args->head > 1)
 339                 return -EINVAL;
 340
 341         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 342                                      1 + args->head, sizeof(*dmac),
 343                                      (void **)&dmac);
 344         *pobject = nv_object(dmac);
 345         if (ret)
 346                 return ret;
 347
 348         nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
 349         nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
 350         return 0;
 351 }
 352
 353 struct nouveau_ofuncs
 354 nv50_disp_sync_ofuncs = {
 355         .ctor = nv50_disp_sync_ctor,
 356         .dtor = nv50_disp_dmac_dtor,
 357         .init = nv50_disp_dmac_init,
 358         .fini = nv50_disp_dmac_fini,
 359         .rd32 = nv50_disp_chan_rd32,
 360         .wr32 = nv50_disp_chan_wr32,
 361 };
 362
 363 /*******************************************************************************
 364  * EVO overlay channel objects
 365  ******************************************************************************/
 366
 367 static int
 368 nv50_disp_ovly_ctor(struct nouveau_object *parent,
 369                     struct nouveau_object *engine,
 370                     struct nouveau_oclass *oclass, void *data, u32 size,
 371                     struct nouveau_object **pobject)
 372 {
 373         struct nv50_display_ovly_class *args = data;
 374         struct nv50_disp_dmac *dmac;
 375         int ret;
 376
 377         if (size < sizeof(*data) || args->head > 1)
 378                 return -EINVAL;
 379
 380         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 381                                      3 + args->head, sizeof(*dmac),
 382                                      (void **)&dmac);
 383         *pobject = nv_object(dmac);
 384         if (ret)
 385                 return ret;
 386
 387         nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
 388         nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
 389         return 0;
 390 }
 391
 392 struct nouveau_ofuncs
 393 nv50_disp_ovly_ofuncs = {
 394         .ctor = nv50_disp_ovly_ctor,
 395         .dtor = nv50_disp_dmac_dtor,
 396         .init = nv50_disp_dmac_init,
 397         .fini = nv50_disp_dmac_fini,
 398         .rd32 = nv50_disp_chan_rd32,
 399         .wr32 = nv50_disp_chan_wr32,
 400 };
 401
 402 /*******************************************************************************
 403  * EVO PIO channel base class
 404  ******************************************************************************/
 405
 406 static int
 407 nv50_disp_pioc_create_(struct nouveau_object *parent,
 408                        struct nouveau_object *engine,
 409                        struct nouveau_oclass *oclass, int chid,
 410                        int length, void **pobject)
 411 {
 412         return nv50_disp_chan_create_(parent, engine, oclass, chid,
 413                                       length, pobject);
 414 }
 415
 416 static void
 417 nv50_disp_pioc_dtor(struct nouveau_object *object)
 418 {
 419         struct nv50_disp_pioc *pioc = (void *)object;
 420         nv50_disp_chan_destroy(&pioc->base);
 421 }
 422
 423 static int
 424 nv50_disp_pioc_init(struct nouveau_object *object)
 425 {
 426         struct nv50_disp_priv *priv = (void *)object->engine;
 427         struct nv50_disp_pioc *pioc = (void *)object;
 428         int chid = pioc->base.chid;
 429         int ret;
 430
 431         ret = nv50_disp_chan_init(&pioc->base);
 432         if (ret)
 433                 return ret;
 434
 435         nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
 436         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
 437                 nv_error(pioc, "timeout0: 0x%08x\n",
 438                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 439                 return -EBUSY;
 440         }
 441
 442         nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
 443         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
 444                 nv_error(pioc, "timeout1: 0x%08x\n",
 445                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 446                 return -EBUSY;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int
 453 nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
 454 {
 455         struct nv50_disp_priv *priv = (void *)object->engine;
 456         struct nv50_disp_pioc *pioc = (void *)object;
 457         int chid = pioc->base.chid;
 458
 459         nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
 460         if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {
 461                 nv_error(pioc, "timeout: 0x%08x\n",
 462                          nv_rd32(priv, 0x610200 + (chid * 0x10)));
 463                 if (suspend)
 464                         return -EBUSY;
 465         }
 466
 467         return nv50_disp_chan_fini(&pioc->base, suspend);
 468 }
 469
 470 /*******************************************************************************
 471  * EVO immediate overlay channel objects
 472  ******************************************************************************/
 473
 474 static int
 475 nv50_disp_oimm_ctor(struct nouveau_object *parent,
 476                     struct nouveau_object *engine,
 477                     struct nouveau_oclass *oclass, void *data, u32 size,
 478                     struct nouveau_object **pobject)
 479 {
 480         struct nv50_display_oimm_class *args = data;
 481         struct nv50_disp_pioc *pioc;
 482         int ret;
 483
 484         if (size < sizeof(*args) || args->head > 1)
 485                 return -EINVAL;
 486
 487         ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head,
 488                                      sizeof(*pioc), (void **)&pioc);
 489         *pobject = nv_object(pioc);
 490         if (ret)
 491                 return ret;
 492
 493         return 0;
 494 }
 495
 496 struct nouveau_ofuncs
 497 nv50_disp_oimm_ofuncs = {
 498         .ctor = nv50_disp_oimm_ctor,
 499         .dtor = nv50_disp_pioc_dtor,
 500         .init = nv50_disp_pioc_init,
 501         .fini = nv50_disp_pioc_fini,
 502         .rd32 = nv50_disp_chan_rd32,
 503         .wr32 = nv50_disp_chan_wr32,
 504 };
 505
 506 /*******************************************************************************
 507  * EVO cursor channel objects
 508  ******************************************************************************/
 509
 510 static int
 511 nv50_disp_curs_ctor(struct nouveau_object *parent,
 512                     struct nouveau_object *engine,
 513                     struct nouveau_oclass *oclass, void *data, u32 size,
 514                     struct nouveau_object **pobject)
 515 {
 516         struct nv50_display_curs_class *args = data;
 517         struct nv50_disp_pioc *pioc;
 518         int ret;
 519
 520         if (size < sizeof(*args) || args->head > 1)
 521                 return -EINVAL;
 522
 523         ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head,
 524                                      sizeof(*pioc), (void **)&pioc);
 525         *pobject = nv_object(pioc);
 526         if (ret)
 527                 return ret;
 528
 529         return 0;
 530 }
 531
 532 struct nouveau_ofuncs
 533 nv50_disp_curs_ofuncs = {
 534         .ctor = nv50_disp_curs_ctor,
 535         .dtor = nv50_disp_pioc_dtor,
 536         .init = nv50_disp_pioc_init,
 537         .fini = nv50_disp_pioc_fini,
 538         .rd32 = nv50_disp_chan_rd32,
 539         .wr32 = nv50_disp_chan_wr32,
 540 };
 541
 542 /*******************************************************************************
 543  * Base display object
 544  ******************************************************************************/
 545
 546 static int
 547 nv50_disp_base_ctor(struct nouveau_object *parent,
 548                     struct nouveau_object *engine,
 549                     struct nouveau_oclass *oclass, void *data, u32 size,
 550                     struct nouveau_object **pobject)
 551 {
 552         struct nv50_disp_priv *priv = (void *)engine;
 553         struct nv50_disp_base *base;
 554         int ret;
 555
 556         ret = nouveau_parent_create(parent, engine, oclass, 0,
 557                                     priv->sclass, 0, &base);
 558         *pobject = nv_object(base);
 559         if (ret)
 560                 return ret;
 561
 562         return nouveau_ramht_new(parent, parent, 0x1000, 0, &base->ramht);
 563 }
 564
 565 static void
 566 nv50_disp_base_dtor(struct nouveau_object *object)
 567 {
 568         struct nv50_disp_base *base = (void *)object;
 569         nouveau_ramht_ref(NULL, &base->ramht);
 570         nouveau_parent_destroy(&base->base);
 571 }
 572
 573 static int
 574 nv50_disp_base_init(struct nouveau_object *object)
 575 {
 576         struct nv50_disp_priv *priv = (void *)object->engine;
 577         struct nv50_disp_base *base = (void *)object;
 578         int ret, i;
 579         u32 tmp;
 580
 581         ret = nouveau_parent_init(&base->base);
 582         if (ret)
 583                 return ret;
 584
 585         /* The below segments of code copying values from one register to
 586          * another appear to inform EVO of the display capabilities or
 587          * something similar.  NFI what the 0x614004 caps are for..
 588          */
 589         tmp = nv_rd32(priv, 0x614004);
 590         nv_wr32(priv, 0x610184, tmp);
 591
 592         /* ... CRTC caps */
 593         for (i = 0; i < priv->head.nr; i++) {
 594                 tmp = nv_rd32(priv, 0x616100 + (i * 0x800));
 595                 nv_wr32(priv, 0x610190 + (i * 0x10), tmp);
 596                 tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
 597                 nv_wr32(priv, 0x610194 + (i * 0x10), tmp);
 598                 tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
 599                 nv_wr32(priv, 0x610198 + (i * 0x10), tmp);
 600                 tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
 601                 nv_wr32(priv, 0x61019c + (i * 0x10), tmp);
 602         }
 603
 604         /* ... DAC caps */
 605         for (i = 0; i < priv->dac.nr; i++) {
 606                 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
 607                 nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp);
 608         }
 609
 610         /* ... SOR caps */
 611         for (i = 0; i < priv->sor.nr; i++) {
 612                 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
 613                 nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp);
 614         }
 615
 616         /* ... EXT caps */
 617         for (i = 0; i < 3; i++) {
 618                 tmp = nv_rd32(priv, 0x61e000 + (i * 0x800));
 619                 nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp);
 620         }
 621
 622         /* steal display away from vbios, or something like that */
 623         if (nv_rd32(priv, 0x610024) & 0x00000100) {
 624                 nv_wr32(priv, 0x610024, 0x00000100);
 625                 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
 626                 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
 627                         nv_error(priv, "timeout acquiring display\n");
 628                         return -EBUSY;
 629                 }
 630         }
 631
 632         /* point at display engine memory area (hash table, objects) */
 633         nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9);
 634
 635         /* enable supervisor interrupts, disable everything else */
 636         nv_wr32(priv, 0x61002c, 0x00000370);
 637         nv_wr32(priv, 0x610028, 0x00000000);
 638         return 0;
 639 }
 640
 641 static int
 642 nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
 643 {
 644         struct nv50_disp_priv *priv = (void *)object->engine;
 645         struct nv50_disp_base *base = (void *)object;
 646
 647         /* disable all interrupts */
 648         nv_wr32(priv, 0x610024, 0x00000000);
 649         nv_wr32(priv, 0x610020, 0x00000000);
 650
 651         return nouveau_parent_fini(&base->base, suspend);
 652 }
 653
 654 struct nouveau_ofuncs
 655 nv50_disp_base_ofuncs = {
 656         .ctor = nv50_disp_base_ctor,
 657         .dtor = nv50_disp_base_dtor,
 658         .init = nv50_disp_base_init,
 659         .fini = nv50_disp_base_fini,
 660 };
 661
 662 static struct nouveau_omthds
 663 nv50_disp_base_omthds[] = {
 664         { SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },
 665         { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
 666         { DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },
 667         { DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },
 668         {},
 669 };
 670
 671 static struct nouveau_oclass
 672 nv50_disp_base_oclass[] = {
 673         { NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds },
 674         {}
 675 };
 676
 677 static struct nouveau_oclass
 678 nv50_disp_sclass[] = {
 679         { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
 680         { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
 681         { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
 682         { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
 683         { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
 684         {}
 685 };
 686
 687 /*******************************************************************************
 688  * Display context, tracks instmem allocation and prevents more than one
 689  * client using the display hardware at any time.
 690  ******************************************************************************/
 691
 692 static int
 693 nv50_disp_data_ctor(struct nouveau_object *parent,
 694                     struct nouveau_object *engine,
 695                     struct nouveau_oclass *oclass, void *data, u32 size,
 696                     struct nouveau_object **pobject)
 697 {
 698         struct nv50_disp_priv *priv = (void *)engine;
 699         struct nouveau_engctx *ectx;
 700         int ret = -EBUSY;
 701
 702         /* no context needed for channel objects... */
 703         if (nv_mclass(parent) != NV_DEVICE_CLASS) {
 704                 atomic_inc(&parent->refcount);
 705                 *pobject = parent;
 706                 return 0;
 707         }
 708
 709         /* allocate display hardware to client */
 710         mutex_lock(&nv_subdev(priv)->mutex);
 711         if (list_empty(&nv_engine(priv)->contexts)) {
 712                 ret = nouveau_engctx_create(parent, engine, oclass, NULL,
 713                                             0x10000, 0x10000,
 714                                             NVOBJ_FLAG_HEAP, &ectx);
 715                 *pobject = nv_object(ectx);
 716         }
 717         mutex_unlock(&nv_subdev(priv)->mutex);
 718         return ret;
 719 }
 720
 721 struct nouveau_oclass
 722 nv50_disp_cclass = {
 723         .handle = NV_ENGCTX(DISP, 0x50),
 724         .ofuncs = &(struct nouveau_ofuncs) {
 725                 .ctor = nv50_disp_data_ctor,
 726                 .dtor = _nouveau_engctx_dtor,
 727                 .init = _nouveau_engctx_init,
 728                 .fini = _nouveau_engctx_fini,
 729                 .rd32 = _nouveau_engctx_rd32,
 730                 .wr32 = _nouveau_engctx_wr32,
 731         },
 732 };
 733
 734 /*******************************************************************************
 735  * Display engine implementation
 736  ******************************************************************************/
 737
 738 static void
 739 nv50_disp_intr_error(struct nv50_disp_priv *priv)
 740 {
 741         u32 channels = (nv_rd32(priv, 0x610020) & 0x001f0000) >> 16;
 742         u32 addr, data;
 743         int chid;
 744
 745         for (chid = 0; chid < 5; chid++) {
 746                 if (!(channels & (1 << chid)))
 747                         continue;
 748
 749                 nv_wr32(priv, 0x610020, 0x00010000 << chid);
 750                 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
 751                 data = nv_rd32(priv, 0x610084 + (chid * 0x08));
 752                 nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
 753
 754                 nv_error(priv, "chid %d mthd 0x%04x data 0x%08x 0x%08x\n",
 755                          chid, addr & 0xffc, data, addr);
 756         }
 757 }
 758
 759 static void
 760 nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
 761 {
 762         struct nouveau_bar *bar = nouveau_bar(priv);
 763         struct nouveau_disp *disp = &priv->base;
 764         struct nouveau_software_chan *chan, *temp;
 765         unsigned long flags;
 766
 767         spin_lock_irqsave(&disp->vblank.lock, flags);
 768         list_for_each_entry_safe(chan, temp, &disp->vblank.list, vblank.head) {
 769                 if (chan->vblank.crtc != crtc)
 770                         continue;
 771
 772                 if (nv_device(priv)->chipset >= 0xc0) {
 773                         nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
 774                         bar->flush(bar);
 775                         nv_wr32(priv, 0x06000c,
 776                                 upper_32_bits(chan->vblank.offset));
 777                         nv_wr32(priv, 0x060010,
 778                                 lower_32_bits(chan->vblank.offset));
 779                         nv_wr32(priv, 0x060014, chan->vblank.value);
 780                 } else {
 781                         nv_wr32(priv, 0x001704, chan->vblank.channel);
 782                         nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
 783                         bar->flush(bar);
 784                         if (nv_device(priv)->chipset == 0x50) {
 785                                 nv_wr32(priv, 0x001570, chan->vblank.offset);
 786                                 nv_wr32(priv, 0x001574, chan->vblank.value);
 787                         } else {
 788                                 nv_wr32(priv, 0x060010, chan->vblank.offset);
 789                                 nv_wr32(priv, 0x060014, chan->vblank.value);
 790                         }
 791                 }
 792
 793                 list_del(&chan->vblank.head);
 794                 if (disp->vblank.put)
 795                         disp->vblank.put(disp->vblank.data, crtc);
 796         }
 797         spin_unlock_irqrestore(&disp->vblank.lock, flags);
 798
 799         if (disp->vblank.notify)
 800                 disp->vblank.notify(disp->vblank.data, crtc);
 801 }
 802
 803 static u16
 804 exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
 805             struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 806             struct nvbios_outp *info)
 807 {
 808         struct nouveau_bios *bios = nouveau_bios(priv);
 809         u16 mask, type, data;
 810
 811         if (outp < 4) {
 812                 type = DCB_OUTPUT_ANALOG;
 813                 mask = 0;
 814         } else {
 815                 outp -= 4;
 816                 switch (ctrl & 0x00000f00) {
 817                 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
 818                 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
 819                 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
 820                 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
 821                 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
 822                 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
 823                 default:
 824                         nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
 825                         return 0x0000;
 826                 }
 827         }
 828
 829         mask  = 0x00c0 & (mask << 6);
 830         mask |= 0x0001 << outp;
 831         mask |= 0x0100 << head;
 832
 833         data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
 834         if (!data)
 835                 return 0x0000;
 836
 837         return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
 838 }
 839
 840 static bool
 841 exec_script(struct nv50_disp_priv *priv, int head, int id)
 842 {
 843         struct nouveau_bios *bios = nouveau_bios(priv);
 844         struct nvbios_outp info;
 845         struct dcb_output dcb;
 846         u8  ver, hdr, cnt, len;
 847         u16 data;
 848         u32 ctrl = 0x00000000;
 849         int i;
 850
 851         for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
 852                 ctrl = nv_rd32(priv, 0x610b5c + (i * 8));
 853
 854         if (!(ctrl & (1 << head))) {
 855                 if (nv_device(priv)->chipset  < 0x90 ||
 856                     nv_device(priv)->chipset == 0x92 ||
 857                     nv_device(priv)->chipset == 0xa0) {
 858                         for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
 859                                 ctrl = nv_rd32(priv, 0x610b74 + (i * 8));
 860                         i += 4;
 861                 } else {
 862                         for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
 863                                 ctrl = nv_rd32(priv, 0x610798 + (i * 8));
 864                         i += 4;
 865                 }
 866         }
 867
 868         if (!(ctrl & (1 << head)))
 869                 return false;
 870         i--;
 871
 872         data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
 873         if (data) {
 874                 struct nvbios_init init = {
 875                         .subdev = nv_subdev(priv),
 876                         .bios = bios,
 877                         .offset = info.script[id],
 878                         .outp = &dcb,
 879                         .crtc = head,
 880                         .execute = 1,
 881                 };
 882
 883                 return nvbios_exec(&init) == 0;
 884         }
 885
 886         return false;
 887 }
 888
 889 static u32
 890 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk,
 891             struct dcb_output *outp)
 892 {
 893         struct nouveau_bios *bios = nouveau_bios(priv);
 894         struct nvbios_outp info1;
 895         struct nvbios_ocfg info2;
 896         u8  ver, hdr, cnt, len;
 897         u16 data, conf;
 898         u32 ctrl = 0x00000000;
 899         int i;
 900
 901         for (i = 0; !(ctrl & (1 << head)) && i < 3; i++)
 902                 ctrl = nv_rd32(priv, 0x610b58 + (i * 8));
 903
 904         if (!(ctrl & (1 << head))) {
 905                 if (nv_device(priv)->chipset  < 0x90 ||
 906                     nv_device(priv)->chipset == 0x92 ||
 907                     nv_device(priv)->chipset == 0xa0) {
 908                         for (i = 0; !(ctrl & (1 << head)) && i < 2; i++)
 909                                 ctrl = nv_rd32(priv, 0x610b70 + (i * 8));
 910                         i += 4;
 911                 } else {
 912                         for (i = 0; !(ctrl & (1 << head)) && i < 4; i++)
 913                                 ctrl = nv_rd32(priv, 0x610794 + (i * 8));
 914                         i += 4;
 915                 }
 916         }
 917
 918         if (!(ctrl & (1 << head)))
 919                 return 0x0000;
 920         i--;
 921
 922         data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1);
 923         if (!data)
 924                 return 0x0000;
 925
 926         switch (outp->type) {
 927         case DCB_OUTPUT_TMDS:
 928                 conf = (ctrl & 0x00000f00) >> 8;
 929                 if (pclk >= 165000)
 930                         conf |= 0x0100;
 931                 break;
 932         case DCB_OUTPUT_LVDS:
 933                 conf = priv->sor.lvdsconf;
 934                 break;
 935         case DCB_OUTPUT_DP:
 936                 conf = (ctrl & 0x00000f00) >> 8;
 937                 break;
 938         case DCB_OUTPUT_ANALOG:
 939         default:
 940                 conf = 0x00ff;
 941                 break;
 942         }
 943
 944         data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
 945         if (data) {
 946                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
 947                 if (data) {
 948                         struct nvbios_init init = {
 949                                 .subdev = nv_subdev(priv),
 950                                 .bios = bios,
 951                                 .offset = data,
 952                                 .outp = outp,
 953                                 .crtc = head,
 954                                 .execute = 1,
 955                         };
 956
 957                         if (nvbios_exec(&init))
 958                                 return 0x0000;
 959                         return conf;
 960                 }
 961         }
 962
 963         return 0x0000;
 964 }
 965
 966 static void
 967 nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super)
 968 {
 969         int head = ffs((super & 0x00000060) >> 5) - 1;
 970         if (head >= 0) {
 971                 head = ffs((super & 0x00000180) >> 7) - 1;
 972                 if (head >= 0)
 973                         exec_script(priv, head, 1);
 974         }
 975
 976         nv_wr32(priv, 0x610024, 0x00000010);
 977         nv_wr32(priv, 0x610030, 0x80000000);
 978 }
 979
 980 static void
 981 nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv,
 982                         struct dcb_output *outp, u32 pclk)
 983 {
 984         const int link = !(outp->sorconf.link & 1);
 985         const int   or = ffs(outp->or) - 1;
 986         const u32 soff = (  or * 0x800);
 987         const u32 loff = (link * 0x080) + soff;
 988         const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8));
 989         const u32 symbol = 100000;
 990         u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000;
 991         u32 clksor = nv_rd32(priv, 0x614300 + soff);
 992         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
 993         int TU, VTUi, VTUf, VTUa;
 994         u64 link_data_rate, link_ratio, unk;
 995         u32 best_diff = 64 * symbol;
 996         u32 link_nr, link_bw, bits, r;
 997
 998         /* calculate packed data rate for each lane */
 999         if      (dpctrl > 0x00030000) link_nr = 4;
1000         else if (dpctrl > 0x00010000) link_nr = 2;
1001         else                          link_nr = 1;
1002
1003         if (clksor & 0x000c0000)
1004                 link_bw = 270000;
1005         else
1006                 link_bw = 162000;
1007
1008         if      ((ctrl & 0xf0000) == 0x60000) bits = 30;
1009         else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
1010         else                                  bits = 18;
1011
1012         link_data_rate = (pclk * bits / 8) / link_nr;
1013
1014         /* calculate ratio of packed data rate to link symbol rate */
1015         link_ratio = link_data_rate * symbol;
1016         r = do_div(link_ratio, link_bw);
1017
1018         for (TU = 64; TU >= 32; TU--) {
1019                 /* calculate average number of valid symbols in each TU */
1020                 u32 tu_valid = link_ratio * TU;
1021                 u32 calc, diff;
1022
1023                 /* find a hw representation for the fraction.. */
1024                 VTUi = tu_valid / symbol;
1025                 calc = VTUi * symbol;
1026                 diff = tu_valid - calc;
1027                 if (diff) {
1028                         if (diff >= (symbol / 2)) {
1029                                 VTUf = symbol / (symbol - diff);
1030                                 if (symbol - (VTUf * diff))
1031                                         VTUf++;
1032
1033                                 if (VTUf <= 15) {
1034                                         VTUa  = 1;
1035                                         calc += symbol - (symbol / VTUf);
1036                                 } else {
1037                                         VTUa  = 0;
1038                                         VTUf  = 1;
1039                                         calc += symbol;
1040                                 }
1041                         } else {
1042                                 VTUa  = 0;
1043                                 VTUf  = min((int)(symbol / diff), 15);
1044                                 calc += symbol / VTUf;
1045                         }
1046
1047                         diff = calc - tu_valid;
1048                 } else {
1049                         /* no remainder, but the hw doesn't like the fractional
1050                          * part to be zero.  decrement the integer part and
1051                          * have the fraction add a whole symbol back
1052                          */
1053                         VTUa = 0;
1054                         VTUf = 1;
1055                         VTUi--;
1056                 }
1057
1058                 if (diff < best_diff) {
1059                         best_diff = diff;
1060                         bestTU = TU;
1061                         bestVTUa = VTUa;
1062                         bestVTUf = VTUf;
1063                         bestVTUi = VTUi;
1064                         if (diff == 0)
1065                                 break;
1066                 }
1067         }
1068
1069         if (!bestTU) {
1070                 nv_error(priv, "unable to find suitable dp config\n");
1071                 return;
1072         }
1073
1074         /* XXX close to vbios numbers, but not right */
1075         unk  = (symbol - link_ratio) * bestTU;
1076         unk *= link_ratio;
1077         r = do_div(unk, symbol);
1078         r = do_div(unk, symbol);
1079         unk += 6;
1080
1081         nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2);
1082         nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
1083                                                    bestVTUf << 16 |
1084                                                    bestVTUi << 8 | unk);
1085 }
1086
1087 static void
1088 nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super)
1089 {
1090         struct dcb_output outp;
1091         u32 addr, mask, data;
1092         int head;
1093
1094         /* finish detaching encoder? */
1095         head = ffs((super & 0x00000180) >> 7) - 1;
1096         if (head >= 0)
1097                 exec_script(priv, head, 2);
1098
1099         /* check whether a vpll change is required */
1100         head = ffs((super & 0x00000600) >> 9) - 1;
1101         if (head >= 0) {
1102                 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1103                 if (pclk) {
1104                         struct nouveau_clock *clk = nouveau_clock(priv);
1105                         clk->pll_set(clk, PLL_VPLL0 + head, pclk);
1106                 }
1107
1108                 nv_mask(priv, 0x614200 + head * 0x800, 0x0000000f, 0x00000000);
1109         }
1110
1111         /* (re)attach the relevant OR to the head */
1112         head = ffs((super & 0x00000180) >> 7) - 1;
1113         if (head >= 0) {
1114                 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1115                 u32 conf = exec_clkcmp(priv, head, 0, pclk, &outp);
1116                 if (conf) {
1117                         if (outp.type == DCB_OUTPUT_ANALOG) {
1118                                 addr = 0x614280 + (ffs(outp.or) - 1) * 0x800;
1119                                 mask = 0xffffffff;
1120                                 data = 0x00000000;
1121                         } else {
1122                                 if (outp.type == DCB_OUTPUT_DP)
1123                                         nv50_disp_intr_unk20_dp(priv, &outp, pclk);
1124                                 addr = 0x614300 + (ffs(outp.or) - 1) * 0x800;
1125                                 mask = 0x00000707;
1126                                 data = (conf & 0x0100) ? 0x0101 : 0x0000;
1127                         }
1128
1129                         nv_mask(priv, addr, mask, data);
1130                 }
1131         }
1132
1133         nv_wr32(priv, 0x610024, 0x00000020);
1134         nv_wr32(priv, 0x610030, 0x80000000);
1135 }
1136
1137 /* If programming a TMDS output on a SOR that can also be configured for
1138  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
1139  *
1140  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
1141  * the VBIOS scripts on at least one board I have only switch it off on
1142  * link 0, causing a blank display if the output has previously been
1143  * programmed for DisplayPort.
1144  */
1145 static void
1146 nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
1147 {
1148         struct nouveau_bios *bios = nouveau_bios(priv);
1149         const int link = !(outp->sorconf.link & 1);
1150         const int   or = ffs(outp->or) - 1;
1151         const u32 loff = (or * 0x800) + (link * 0x80);
1152         const u16 mask = (outp->sorconf.link << 6) | outp->or;
1153         u8  ver, hdr;
1154
1155         if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp))
1156                 nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000);
1157 }
1158
1159 static void
1160 nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super)
1161 {
1162         int head = ffs((super & 0x00000180) >> 7) - 1;
1163         if (head >= 0) {
1164                 struct dcb_output outp;
1165                 u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
1166                 if (pclk && exec_clkcmp(priv, head, 1, pclk, &outp)) {
1167                         if (outp.type == DCB_OUTPUT_TMDS)
1168                                 nv50_disp_intr_unk40_tmds(priv, &outp);
1169                 }
1170         }
1171
1172         nv_wr32(priv, 0x610024, 0x00000040);
1173         nv_wr32(priv, 0x610030, 0x80000000);
1174 }
1175
1176 static void
1177 nv50_disp_intr_super(struct nv50_disp_priv *priv, u32 intr1)
1178 {
1179         u32 super = nv_rd32(priv, 0x610030);
1180
1181         nv_debug(priv, "supervisor 0x%08x 0x%08x\n", intr1, super);
1182
1183         if (intr1 & 0x00000010)
1184                 nv50_disp_intr_unk10(priv, super);
1185         if (intr1 & 0x00000020)
1186                 nv50_disp_intr_unk20(priv, super);
1187         if (intr1 & 0x00000040)
1188                 nv50_disp_intr_unk40(priv, super);
1189 }
1190
1191 void
1192 nv50_disp_intr(struct nouveau_subdev *subdev)
1193 {
1194         struct nv50_disp_priv *priv = (void *)subdev;
1195         u32 intr0 = nv_rd32(priv, 0x610020);
1196         u32 intr1 = nv_rd32(priv, 0x610024);
1197
1198         if (intr0 & 0x001f0000) {
1199                 nv50_disp_intr_error(priv);
1200                 intr0 &= ~0x001f0000;
1201         }
1202
1203         if (intr1 & 0x00000004) {
1204                 nv50_disp_intr_vblank(priv, 0);
1205                 nv_wr32(priv, 0x610024, 0x00000004);
1206                 intr1 &= ~0x00000004;
1207         }
1208
1209         if (intr1 & 0x00000008) {
1210                 nv50_disp_intr_vblank(priv, 1);
1211                 nv_wr32(priv, 0x610024, 0x00000008);
1212                 intr1 &= ~0x00000008;
1213         }
1214
1215         if (intr1 & 0x00000070) {
1216                 nv50_disp_intr_super(priv, intr1);
1217                 intr1 &= ~0x00000070;
1218         }
1219 }
1220
1221 static int
1222 nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
1223                struct nouveau_oclass *oclass, void *data, u32 size,
1224                struct nouveau_object **pobject)
1225 {
1226         struct nv50_disp_priv *priv;
1227         int ret;
1228
1229         ret = nouveau_disp_create(parent, engine, oclass, "PDISP",
1230                                   "display", &priv);
1231         *pobject = nv_object(priv);
1232         if (ret)
1233                 return ret;
1234
1235         nv_engine(priv)->sclass = nv50_disp_base_oclass;
1236         nv_engine(priv)->cclass = &nv50_disp_cclass;
1237         nv_subdev(priv)->intr = nv50_disp_intr;
1238         priv->sclass = nv50_disp_sclass;
1239         priv->head.nr = 2;
1240         priv->dac.nr = 3;
1241         priv->sor.nr = 2;
1242         priv->dac.power = nv50_dac_power;
1243         priv->dac.sense = nv50_dac_sense;
1244         priv->sor.power = nv50_sor_power;
1245
1246         INIT_LIST_HEAD(&priv->base.vblank.list);
1247         spin_lock_init(&priv->base.vblank.lock);
1248         return 0;
1249 }
1250
1251 struct nouveau_oclass
1252 nv50_disp_oclass = {
1253         .handle = NV_ENGINE(DISP, 0x50),
1254         .ofuncs = &(struct nouveau_ofuncs) {
1255                 .ctor = nv50_disp_ctor,
1256                 .dtor = _nouveau_disp_dtor,
1257                 .init = _nouveau_disp_init,
1258                 .fini = _nouveau_disp_fini,
1259         },
1260 };