2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 2
32 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
35 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
38 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
41 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
42 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
44 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
46 static const char * const forcewake_domain_names[] = {
53 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
55 BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
58 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
59 return forcewake_domain_names[id];
67 assert_device_not_suspended(struct drm_i915_private *dev_priv)
69 WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
70 "Device suspended\n");
74 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
76 WARN_ON(d->reg_set == 0);
77 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
81 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
83 mod_timer_pinned(&d->timer, jiffies + 1);
87 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
90 FORCEWAKE_KERNEL) == 0,
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
97 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
99 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
103 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
105 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
107 FORCEWAKE_ACK_TIMEOUT_MS))
108 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
109 intel_uncore_forcewake_domain_to_str(d->id));
113 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
115 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
119 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
121 /* something from same cacheline, but not from the set register */
123 __raw_posting_read(d->i915, d->reg_post);
127 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
129 struct intel_uncore_forcewake_domain *d;
130 enum forcewake_domain_id id;
132 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
133 fw_domain_wait_ack_clear(d);
135 fw_domain_wait_ack(d);
140 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
142 struct intel_uncore_forcewake_domain *d;
143 enum forcewake_domain_id id;
145 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
147 fw_domain_posting_read(d);
152 fw_domains_posting_read(struct drm_i915_private *dev_priv)
154 struct intel_uncore_forcewake_domain *d;
155 enum forcewake_domain_id id;
157 /* No need to do for all, just do for first found */
158 for_each_fw_domain(d, dev_priv, id) {
159 fw_domain_posting_read(d);
165 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
167 struct intel_uncore_forcewake_domain *d;
168 enum forcewake_domain_id id;
170 if (dev_priv->uncore.fw_domains == 0)
173 for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
176 fw_domains_posting_read(dev_priv);
179 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
181 /* w/a for a sporadic read returning 0 by waiting for the GT
184 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
185 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
186 DRM_ERROR("GT thread status wait timed out\n");
189 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
190 enum forcewake_domains fw_domains)
192 fw_domains_get(dev_priv, fw_domains);
194 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
195 __gen6_gt_wait_for_thread_c0(dev_priv);
198 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
202 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
203 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
204 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
207 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
208 enum forcewake_domains fw_domains)
210 fw_domains_put(dev_priv, fw_domains);
211 gen6_gt_check_fifodbg(dev_priv);
214 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
216 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
218 return count & GT_FIFO_FREE_ENTRIES_MASK;
221 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
225 /* On VLV, FIFO will be shared by both SW and HW.
226 * So, we need to read the FREE_ENTRIES everytime */
227 if (IS_VALLEYVIEW(dev_priv->dev))
228 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
230 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
232 u32 fifo = fifo_free_entries(dev_priv);
234 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
236 fifo = fifo_free_entries(dev_priv);
238 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
240 dev_priv->uncore.fifo_count = fifo;
242 dev_priv->uncore.fifo_count--;
247 static void intel_uncore_fw_release_timer(unsigned long arg)
249 struct intel_uncore_forcewake_domain *domain = (void *)arg;
250 unsigned long irqflags;
252 assert_device_not_suspended(domain->i915);
254 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
255 if (WARN_ON(domain->wake_count == 0))
256 domain->wake_count++;
258 if (--domain->wake_count == 0)
259 domain->i915->uncore.funcs.force_wake_put(domain->i915,
262 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
265 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 unsigned long irqflags;
269 struct intel_uncore_forcewake_domain *domain;
270 int retry_count = 100;
271 enum forcewake_domain_id id;
272 enum forcewake_domains fw = 0, active_domains;
274 /* Hold uncore.lock across reset to prevent any register access
275 * with forcewake not set correctly. Wait until all pending
276 * timers are run before holding.
281 for_each_fw_domain(domain, dev_priv, id) {
282 if (del_timer_sync(&domain->timer) == 0)
285 intel_uncore_fw_release_timer((unsigned long)domain);
288 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
290 for_each_fw_domain(domain, dev_priv, id) {
291 if (timer_pending(&domain->timer))
292 active_domains |= (1 << id);
295 if (active_domains == 0)
298 if (--retry_count == 0) {
299 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
303 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
307 WARN_ON(active_domains);
309 for_each_fw_domain(domain, dev_priv, id)
310 if (domain->wake_count)
314 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
316 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
318 if (restore) { /* If reset with a user forcewake, try to restore */
320 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
322 if (IS_GEN6(dev) || IS_GEN7(dev))
323 dev_priv->uncore.fifo_count =
324 fifo_free_entries(dev_priv);
328 assert_forcewakes_inactive(dev_priv);
330 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
333 static void intel_uncore_ellc_detect(struct drm_device *dev)
335 struct drm_i915_private *dev_priv = dev->dev_private;
337 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
338 INTEL_INFO(dev)->gen >= 9) &&
339 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
340 /* The docs do not explain exactly how the calculation can be
341 * made. It is somewhat guessable, but for now, it's always
343 * NB: We can't write IDICR yet because we do not have gt funcs
345 dev_priv->ellc_size = 128;
346 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
350 static void __intel_uncore_early_sanitize(struct drm_device *dev,
351 bool restore_forcewake)
353 struct drm_i915_private *dev_priv = dev->dev_private;
355 if (HAS_FPGA_DBG_UNCLAIMED(dev))
356 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
358 /* clear out old GT FIFO errors */
359 if (IS_GEN6(dev) || IS_GEN7(dev))
360 __raw_i915_write32(dev_priv, GTFIFODBG,
361 __raw_i915_read32(dev_priv, GTFIFODBG));
363 /* WaDisableShadowRegForCpd:chv */
364 if (IS_CHERRYVIEW(dev)) {
365 __raw_i915_write32(dev_priv, GTFIFOCTL,
366 __raw_i915_read32(dev_priv, GTFIFOCTL) |
367 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
368 GT_FIFO_CTL_RC6_POLICY_STALL);
371 intel_uncore_forcewake_reset(dev, restore_forcewake);
374 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
376 __intel_uncore_early_sanitize(dev, restore_forcewake);
377 i915_check_and_clear_faults(dev);
380 void intel_uncore_sanitize(struct drm_device *dev)
382 /* BIOS often leaves RC6 enabled, but disable it for hw init */
383 intel_disable_gt_powersave(dev);
386 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
387 enum forcewake_domains fw_domains)
389 struct intel_uncore_forcewake_domain *domain;
390 enum forcewake_domain_id id;
392 if (!dev_priv->uncore.funcs.force_wake_get)
395 fw_domains &= dev_priv->uncore.fw_domains;
397 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
398 if (domain->wake_count++)
399 fw_domains &= ~(1 << id);
403 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
407 * intel_uncore_forcewake_get - grab forcewake domain references
408 * @dev_priv: i915 device instance
409 * @fw_domains: forcewake domains to get reference on
411 * This function can be used get GT's forcewake domain references.
412 * Normal register access will handle the forcewake domains automatically.
413 * However if some sequence requires the GT to not power down a particular
414 * forcewake domains this function should be called at the beginning of the
415 * sequence. And subsequently the reference should be dropped by symmetric
416 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
417 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
419 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
420 enum forcewake_domains fw_domains)
422 unsigned long irqflags;
424 if (!dev_priv->uncore.funcs.force_wake_get)
427 WARN_ON(dev_priv->pm.suspended);
429 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
430 __intel_uncore_forcewake_get(dev_priv, fw_domains);
431 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
435 * intel_uncore_forcewake_get__locked - grab forcewake domain references
436 * @dev_priv: i915 device instance
437 * @fw_domains: forcewake domains to get reference on
439 * See intel_uncore_forcewake_get(). This variant places the onus
440 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
442 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
443 enum forcewake_domains fw_domains)
445 assert_spin_locked(&dev_priv->uncore.lock);
447 if (!dev_priv->uncore.funcs.force_wake_get)
450 __intel_uncore_forcewake_get(dev_priv, fw_domains);
453 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
454 enum forcewake_domains fw_domains)
456 struct intel_uncore_forcewake_domain *domain;
457 enum forcewake_domain_id id;
459 if (!dev_priv->uncore.funcs.force_wake_put)
462 fw_domains &= dev_priv->uncore.fw_domains;
464 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
465 if (WARN_ON(domain->wake_count == 0))
468 if (--domain->wake_count)
471 domain->wake_count++;
472 fw_domain_arm_timer(domain);
477 * intel_uncore_forcewake_put - release a forcewake domain reference
478 * @dev_priv: i915 device instance
479 * @fw_domains: forcewake domains to put references
481 * This function drops the device-level forcewakes for specified
482 * domains obtained by intel_uncore_forcewake_get().
484 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
485 enum forcewake_domains fw_domains)
487 unsigned long irqflags;
489 if (!dev_priv->uncore.funcs.force_wake_put)
492 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
493 __intel_uncore_forcewake_put(dev_priv, fw_domains);
494 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
498 * intel_uncore_forcewake_put__locked - grab forcewake domain references
499 * @dev_priv: i915 device instance
500 * @fw_domains: forcewake domains to get reference on
502 * See intel_uncore_forcewake_put(). This variant places the onus
503 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
505 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
506 enum forcewake_domains fw_domains)
508 assert_spin_locked(&dev_priv->uncore.lock);
510 if (!dev_priv->uncore.funcs.force_wake_put)
513 __intel_uncore_forcewake_put(dev_priv, fw_domains);
516 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
518 struct intel_uncore_forcewake_domain *domain;
519 enum forcewake_domain_id id;
521 if (!dev_priv->uncore.funcs.force_wake_get)
524 for_each_fw_domain(domain, dev_priv, id)
525 WARN_ON(domain->wake_count);
528 /* We give fast paths for the really cool registers */
529 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
530 ((reg) < 0x40000 && (reg) != FORCEWAKE)
532 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
534 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
535 (REG_RANGE((reg), 0x2000, 0x4000) || \
536 REG_RANGE((reg), 0x5000, 0x8000) || \
537 REG_RANGE((reg), 0xB000, 0x12000) || \
538 REG_RANGE((reg), 0x2E000, 0x30000))
540 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
541 (REG_RANGE((reg), 0x12000, 0x14000) || \
542 REG_RANGE((reg), 0x22000, 0x24000) || \
543 REG_RANGE((reg), 0x30000, 0x40000))
545 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
546 (REG_RANGE((reg), 0x2000, 0x4000) || \
547 REG_RANGE((reg), 0x5200, 0x8000) || \
548 REG_RANGE((reg), 0x8300, 0x8500) || \
549 REG_RANGE((reg), 0xB000, 0xB480) || \
550 REG_RANGE((reg), 0xE000, 0xE800))
552 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
553 (REG_RANGE((reg), 0x8800, 0x8900) || \
554 REG_RANGE((reg), 0xD000, 0xD800) || \
555 REG_RANGE((reg), 0x12000, 0x14000) || \
556 REG_RANGE((reg), 0x1A000, 0x1C000) || \
557 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
558 REG_RANGE((reg), 0x30000, 0x38000))
560 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
561 (REG_RANGE((reg), 0x4000, 0x5000) || \
562 REG_RANGE((reg), 0x8000, 0x8300) || \
563 REG_RANGE((reg), 0x8500, 0x8600) || \
564 REG_RANGE((reg), 0x9000, 0xB000) || \
565 REG_RANGE((reg), 0xF000, 0x10000))
567 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
568 REG_RANGE((reg), 0xB00, 0x2000)
570 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
571 (REG_RANGE((reg), 0x2000, 0x2700) || \
572 REG_RANGE((reg), 0x3000, 0x4000) || \
573 REG_RANGE((reg), 0x5200, 0x8000) || \
574 REG_RANGE((reg), 0x8140, 0x8160) || \
575 REG_RANGE((reg), 0x8300, 0x8500) || \
576 REG_RANGE((reg), 0x8C00, 0x8D00) || \
577 REG_RANGE((reg), 0xB000, 0xB480) || \
578 REG_RANGE((reg), 0xE000, 0xE900) || \
579 REG_RANGE((reg), 0x24400, 0x24800))
581 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
582 (REG_RANGE((reg), 0x8130, 0x8140) || \
583 REG_RANGE((reg), 0x8800, 0x8A00) || \
584 REG_RANGE((reg), 0xD000, 0xD800) || \
585 REG_RANGE((reg), 0x12000, 0x14000) || \
586 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
587 REG_RANGE((reg), 0x30000, 0x40000))
589 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
590 REG_RANGE((reg), 0x9400, 0x9800)
592 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
594 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
595 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
596 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
597 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
600 ilk_dummy_write(struct drm_i915_private *dev_priv)
602 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
603 * the chip from rc6 before touching it for real. MI_MODE is masked,
604 * hence harmless to write 0 into. */
605 __raw_i915_write32(dev_priv, MI_MODE, 0);
609 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
612 const char *op = read ? "reading" : "writing to";
613 const char *when = before ? "before" : "after";
615 if (!i915.mmio_debug)
618 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
619 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
621 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
622 i915.mmio_debug--; /* Only report the first N failures */
627 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
629 static bool mmio_debug_once = true;
631 if (i915.mmio_debug || !mmio_debug_once)
634 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
635 DRM_DEBUG("Unclaimed register detected, "
636 "enabling oneshot unclaimed register reporting. "
637 "Please use i915.mmio_debug=N for more information.\n");
638 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
639 i915.mmio_debug = mmio_debug_once--;
643 #define GEN2_READ_HEADER(x) \
645 assert_device_not_suspended(dev_priv);
647 #define GEN2_READ_FOOTER \
648 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
651 #define __gen2_read(x) \
653 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
654 GEN2_READ_HEADER(x); \
655 val = __raw_i915_read##x(dev_priv, reg); \
659 #define __gen5_read(x) \
661 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
662 GEN2_READ_HEADER(x); \
663 ilk_dummy_write(dev_priv); \
664 val = __raw_i915_read##x(dev_priv, reg); \
680 #undef GEN2_READ_FOOTER
681 #undef GEN2_READ_HEADER
683 #define GEN6_READ_HEADER(x) \
684 unsigned long irqflags; \
686 assert_device_not_suspended(dev_priv); \
687 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
689 #define GEN6_READ_FOOTER \
690 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
691 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
694 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
695 enum forcewake_domains fw_domains)
697 struct intel_uncore_forcewake_domain *domain;
698 enum forcewake_domain_id id;
700 if (WARN_ON(!fw_domains))
703 /* Ideally GCC would be constant-fold and eliminate this loop */
704 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
705 if (domain->wake_count) {
706 fw_domains &= ~(1 << id);
710 domain->wake_count++;
711 fw_domain_arm_timer(domain);
715 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
718 #define __vgpu_read(x) \
720 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
721 GEN6_READ_HEADER(x); \
722 val = __raw_i915_read##x(dev_priv, reg); \
726 #define __gen6_read(x) \
728 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
729 GEN6_READ_HEADER(x); \
730 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
731 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
732 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
733 val = __raw_i915_read##x(dev_priv, reg); \
734 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
738 #define __vlv_read(x) \
740 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
741 GEN6_READ_HEADER(x); \
742 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
743 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
744 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
745 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
746 val = __raw_i915_read##x(dev_priv, reg); \
750 #define __chv_read(x) \
752 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
753 GEN6_READ_HEADER(x); \
754 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
755 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
756 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
757 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
758 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
759 __force_wake_get(dev_priv, \
760 FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
761 val = __raw_i915_read##x(dev_priv, reg); \
765 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \
766 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
768 #define __gen9_read(x) \
770 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
771 enum forcewake_domains fw_engine; \
772 GEN6_READ_HEADER(x); \
773 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) \
775 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
776 fw_engine = FORCEWAKE_RENDER; \
777 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
778 fw_engine = FORCEWAKE_MEDIA; \
779 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
780 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
782 fw_engine = FORCEWAKE_BLITTER; \
784 __force_wake_get(dev_priv, fw_engine); \
785 val = __raw_i915_read##x(dev_priv, reg); \
815 #undef GEN6_READ_FOOTER
816 #undef GEN6_READ_HEADER
818 #define GEN2_WRITE_HEADER \
819 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
820 assert_device_not_suspended(dev_priv); \
822 #define GEN2_WRITE_FOOTER
824 #define __gen2_write(x) \
826 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
828 __raw_i915_write##x(dev_priv, reg, val); \
832 #define __gen5_write(x) \
834 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
836 ilk_dummy_write(dev_priv); \
837 __raw_i915_write##x(dev_priv, reg, val); \
853 #undef GEN2_WRITE_FOOTER
854 #undef GEN2_WRITE_HEADER
856 #define GEN6_WRITE_HEADER \
857 unsigned long irqflags; \
858 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
859 assert_device_not_suspended(dev_priv); \
860 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
862 #define GEN6_WRITE_FOOTER \
863 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
865 #define __gen6_write(x) \
867 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
868 u32 __fifo_ret = 0; \
870 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
871 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
873 __raw_i915_write##x(dev_priv, reg, val); \
874 if (unlikely(__fifo_ret)) { \
875 gen6_gt_check_fifodbg(dev_priv); \
880 #define __hsw_write(x) \
882 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
883 u32 __fifo_ret = 0; \
885 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
886 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
888 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
889 __raw_i915_write##x(dev_priv, reg, val); \
890 if (unlikely(__fifo_ret)) { \
891 gen6_gt_check_fifodbg(dev_priv); \
893 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
894 hsw_unclaimed_reg_detect(dev_priv); \
898 #define __vgpu_write(x) \
899 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
900 off_t reg, u##x val, bool trace) { \
902 __raw_i915_write##x(dev_priv, reg, val); \
906 static const u32 gen8_shadowed_regs[] = {
910 RING_TAIL(RENDER_RING_BASE),
911 RING_TAIL(GEN6_BSD_RING_BASE),
912 RING_TAIL(VEBOX_RING_BASE),
913 RING_TAIL(BLT_RING_BASE),
914 /* TODO: Other registers are not yet used */
917 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
920 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
921 if (reg == gen8_shadowed_regs[i])
927 #define __gen8_write(x) \
929 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
931 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
932 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
933 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
934 __raw_i915_write##x(dev_priv, reg, val); \
935 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
936 hsw_unclaimed_reg_detect(dev_priv); \
940 #define __chv_write(x) \
942 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
943 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
946 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
947 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
948 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
949 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
950 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
951 __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
953 __raw_i915_write##x(dev_priv, reg, val); \
957 static const u32 gen9_shadowed_regs[] = {
958 RING_TAIL(RENDER_RING_BASE),
959 RING_TAIL(GEN6_BSD_RING_BASE),
960 RING_TAIL(VEBOX_RING_BASE),
961 RING_TAIL(BLT_RING_BASE),
962 FORCEWAKE_BLITTER_GEN9,
963 FORCEWAKE_RENDER_GEN9,
964 FORCEWAKE_MEDIA_GEN9,
967 /* TODO: Other registers are not yet used */
970 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
973 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
974 if (reg == gen9_shadowed_regs[i])
980 #define __gen9_write(x) \
982 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
984 enum forcewake_domains fw_engine; \
986 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
987 is_gen9_shadowed(dev_priv, reg)) \
989 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
990 fw_engine = FORCEWAKE_RENDER; \
991 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
992 fw_engine = FORCEWAKE_MEDIA; \
993 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
994 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
996 fw_engine = FORCEWAKE_BLITTER; \
998 __force_wake_get(dev_priv, fw_engine); \
999 __raw_i915_write##x(dev_priv, reg, val); \
1000 GEN6_WRITE_FOOTER; \
1034 #undef GEN6_WRITE_FOOTER
1035 #undef GEN6_WRITE_HEADER
1037 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1039 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1040 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1041 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1042 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1045 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1047 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1048 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1049 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1050 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1054 static void fw_domain_init(struct drm_i915_private *dev_priv,
1055 enum forcewake_domain_id domain_id,
1056 u32 reg_set, u32 reg_ack)
1058 struct intel_uncore_forcewake_domain *d;
1060 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1063 d = &dev_priv->uncore.fw_domain[domain_id];
1065 WARN_ON(d->wake_count);
1068 d->reg_set = reg_set;
1069 d->reg_ack = reg_ack;
1071 if (IS_GEN6(dev_priv)) {
1073 d->val_set = FORCEWAKE_KERNEL;
1076 /* WaRsClearFWBitsAtReset:bdw,skl */
1077 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1078 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1079 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1082 if (IS_VALLEYVIEW(dev_priv))
1083 d->reg_post = FORCEWAKE_ACK_VLV;
1084 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1085 d->reg_post = ECOBUS;
1092 setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1094 dev_priv->uncore.fw_domains |= (1 << domain_id);
1099 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1103 if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1107 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1108 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1109 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1110 FORCEWAKE_RENDER_GEN9,
1111 FORCEWAKE_ACK_RENDER_GEN9);
1112 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1113 FORCEWAKE_BLITTER_GEN9,
1114 FORCEWAKE_ACK_BLITTER_GEN9);
1115 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1116 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1117 } else if (IS_VALLEYVIEW(dev)) {
1118 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1119 if (!IS_CHERRYVIEW(dev))
1120 dev_priv->uncore.funcs.force_wake_put =
1121 fw_domains_put_with_fifo;
1123 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1124 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1125 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1126 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1127 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1128 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1129 dev_priv->uncore.funcs.force_wake_get =
1130 fw_domains_get_with_thread_status;
1131 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1132 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1133 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1134 } else if (IS_IVYBRIDGE(dev)) {
1137 /* IVB configs may use multi-threaded forcewake */
1139 /* A small trick here - if the bios hasn't configured
1140 * MT forcewake, and if the device is in RC6, then
1141 * force_wake_mt_get will not wake the device and the
1142 * ECOBUS read will return zero. Which will be
1143 * (correctly) interpreted by the test below as MT
1144 * forcewake being disabled.
1146 dev_priv->uncore.funcs.force_wake_get =
1147 fw_domains_get_with_thread_status;
1148 dev_priv->uncore.funcs.force_wake_put =
1149 fw_domains_put_with_fifo;
1151 /* We need to init first for ECOBUS access and then
1152 * determine later if we want to reinit, in case of MT access is
1153 * not working. In this stage we don't know which flavour this
1154 * ivb is, so it is better to reset also the gen6 fw registers
1155 * before the ecobus check.
1158 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1159 __raw_posting_read(dev_priv, ECOBUS);
1161 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1162 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1164 mutex_lock(&dev->struct_mutex);
1165 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1166 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1167 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1168 mutex_unlock(&dev->struct_mutex);
1170 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1171 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1172 DRM_INFO("when using vblank-synced partial screen updates.\n");
1173 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1174 FORCEWAKE, FORCEWAKE_ACK);
1176 } else if (IS_GEN6(dev)) {
1177 dev_priv->uncore.funcs.force_wake_get =
1178 fw_domains_get_with_thread_status;
1179 dev_priv->uncore.funcs.force_wake_put =
1180 fw_domains_put_with_fifo;
1181 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1182 FORCEWAKE, FORCEWAKE_ACK);
1185 /* All future platforms are expected to require complex power gating */
1186 WARN_ON(dev_priv->uncore.fw_domains == 0);
1189 void intel_uncore_init(struct drm_device *dev)
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1193 i915_check_vgpu(dev);
1195 intel_uncore_ellc_detect(dev);
1196 intel_uncore_fw_domains_init(dev);
1197 __intel_uncore_early_sanitize(dev, false);
1199 switch (INTEL_INFO(dev)->gen) {
1201 MISSING_CASE(INTEL_INFO(dev)->gen);
1204 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1205 ASSIGN_READ_MMIO_VFUNCS(gen9);
1208 if (IS_CHERRYVIEW(dev)) {
1209 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1210 ASSIGN_READ_MMIO_VFUNCS(chv);
1213 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1214 ASSIGN_READ_MMIO_VFUNCS(gen6);
1219 if (IS_HASWELL(dev)) {
1220 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1222 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1225 if (IS_VALLEYVIEW(dev)) {
1226 ASSIGN_READ_MMIO_VFUNCS(vlv);
1228 ASSIGN_READ_MMIO_VFUNCS(gen6);
1232 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1233 ASSIGN_READ_MMIO_VFUNCS(gen5);
1238 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1239 ASSIGN_READ_MMIO_VFUNCS(gen2);
1243 if (intel_vgpu_active(dev)) {
1244 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1245 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1248 i915_check_and_clear_faults(dev);
1250 #undef ASSIGN_WRITE_MMIO_VFUNCS
1251 #undef ASSIGN_READ_MMIO_VFUNCS
1253 void intel_uncore_fini(struct drm_device *dev)
1255 /* Paranoia: make sure we have disabled everything before we exit. */
1256 intel_uncore_sanitize(dev);
1257 intel_uncore_forcewake_reset(dev, false);
1260 #define GEN_RANGE(l, h) GENMASK(h, l)
1262 static const struct register_whitelist {
1265 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1266 uint32_t gen_bitmask;
1268 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1271 int i915_reg_read_ioctl(struct drm_device *dev,
1272 void *data, struct drm_file *file)
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 struct drm_i915_reg_read *reg = data;
1276 struct register_whitelist const *entry = whitelist;
1279 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1280 if (entry->offset == reg->offset &&
1281 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1285 if (i == ARRAY_SIZE(whitelist))
1288 intel_runtime_pm_get(dev_priv);
1290 switch (entry->size) {
1292 reg->val = I915_READ64(reg->offset);
1295 reg->val = I915_READ(reg->offset);
1298 reg->val = I915_READ16(reg->offset);
1301 reg->val = I915_READ8(reg->offset);
1304 MISSING_CASE(entry->size);
1310 intel_runtime_pm_put(dev_priv);
1314 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1315 void *data, struct drm_file *file)
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct drm_i915_reset_stats *args = data;
1319 struct i915_ctx_hang_stats *hs;
1320 struct intel_context *ctx;
1323 if (args->flags || args->pad)
1326 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1329 ret = mutex_lock_interruptible(&dev->struct_mutex);
1333 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1335 mutex_unlock(&dev->struct_mutex);
1336 return PTR_ERR(ctx);
1338 hs = &ctx->hang_stats;
1340 if (capable(CAP_SYS_ADMIN))
1341 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1343 args->reset_count = 0;
1345 args->batch_active = hs->batch_active;
1346 args->batch_pending = hs->batch_pending;
1348 mutex_unlock(&dev->struct_mutex);
1353 static int i915_reset_complete(struct drm_device *dev)
1356 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1357 return (gdrst & GRDOM_RESET_STATUS) == 0;
1360 static int i915_do_reset(struct drm_device *dev)
1362 /* assert reset for at least 20 usec */
1363 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1365 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1367 return wait_for(i915_reset_complete(dev), 500);
1370 static int g4x_reset_complete(struct drm_device *dev)
1373 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1374 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1377 static int g33_do_reset(struct drm_device *dev)
1379 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1380 return wait_for(g4x_reset_complete(dev), 500);
1383 static int g4x_do_reset(struct drm_device *dev)
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1388 pci_write_config_byte(dev->pdev, I915_GDRST,
1389 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1390 ret = wait_for(g4x_reset_complete(dev), 500);
1394 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1395 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1396 POSTING_READ(VDECCLK_GATE_D);
1398 pci_write_config_byte(dev->pdev, I915_GDRST,
1399 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1400 ret = wait_for(g4x_reset_complete(dev), 500);
1404 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1405 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1406 POSTING_READ(VDECCLK_GATE_D);
1408 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1413 static int ironlake_do_reset(struct drm_device *dev)
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1418 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1419 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1420 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1421 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1425 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1426 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1427 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1428 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1432 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1437 static int gen6_do_reset(struct drm_device *dev)
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1442 /* Reset the chip */
1444 /* GEN6_GDRST is not in the gt power well, no need to check
1445 * for fifo space for the write or forcewake the chip for
1448 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1450 /* Spin waiting for the device to ack the reset request */
1451 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1453 intel_uncore_forcewake_reset(dev, true);
1458 int intel_gpu_reset(struct drm_device *dev)
1460 if (INTEL_INFO(dev)->gen >= 6)
1461 return gen6_do_reset(dev);
1462 else if (IS_GEN5(dev))
1463 return ironlake_do_reset(dev);
1464 else if (IS_G4X(dev))
1465 return g4x_do_reset(dev);
1466 else if (IS_G33(dev))
1467 return g33_do_reset(dev);
1468 else if (INTEL_INFO(dev)->gen >= 3)
1469 return i915_do_reset(dev);
1474 void intel_uncore_check_errors(struct drm_device *dev)
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1478 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1479 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1480 DRM_ERROR("Unclaimed register before interrupt\n");
1481 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);