2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
47 static inline int ring_space(struct intel_ring_buffer *ring)
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
56 render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
60 struct drm_device *dev = ring->dev;
67 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
69 * also flushed at 2d versus 3d pipeline switches.
73 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74 * MI_READ_FLUSH is set, and is always flushed on 965.
76 * I915_GEM_DOMAIN_COMMAND may not exist?
78 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79 * invalidated when MI_EXE_FLUSH is set.
81 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82 * invalidated with every MI_FLUSH.
86 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89 * are flushed at any MI_FLUSH.
92 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
93 if ((invalidate_domains|flush_domains) &
94 I915_GEM_DOMAIN_RENDER)
95 cmd &= ~MI_NO_WRITE_FLUSH;
96 if (INTEL_INFO(dev)->gen < 4) {
98 * On the 965, the sampler cache always gets flushed
99 * and this bit is reserved.
101 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
102 cmd |= MI_READ_FLUSH;
104 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
107 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
108 (IS_G4X(dev) || IS_GEN5(dev)))
109 cmd |= MI_INVALIDATE_ISP;
111 ret = intel_ring_begin(ring, 2);
115 intel_ring_emit(ring, cmd);
116 intel_ring_emit(ring, MI_NOOP);
117 intel_ring_advance(ring);
123 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124 * implementing two workarounds on gen6. From section 1.4.7.1
125 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
127 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128 * produced by non-pipelined state commands), software needs to first
129 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
132 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
135 * And the workaround for these two requires this workaround first:
137 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138 * BEFORE the pipe-control with a post-sync op and no write-cache
141 * And this last workaround is tricky because of the requirements on
142 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
145 * "1 of the following must also be set:
146 * - Render Target Cache Flush Enable ([12] of DW1)
147 * - Depth Cache Flush Enable ([0] of DW1)
148 * - Stall at Pixel Scoreboard ([1] of DW1)
149 * - Depth Stall ([13] of DW1)
150 * - Post-Sync Operation ([13] of DW1)
151 * - Notify Enable ([8] of DW1)"
153 * The cache flushes require the workaround flush that triggered this
154 * one, so we can't use it. Depth stall would trigger the same.
155 * Post-sync nonzero is what triggered this second workaround, so we
156 * can't use that one either. Notify enable is IRQs, which aren't
157 * really our business. That leaves only stall at scoreboard.
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
162 struct pipe_control *pc = ring->private;
163 u32 scratch_addr = pc->gtt_offset + 128;
167 ret = intel_ring_begin(ring, 6);
171 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
172 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
173 PIPE_CONTROL_STALL_AT_SCOREBOARD);
174 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
175 intel_ring_emit(ring, 0); /* low dword */
176 intel_ring_emit(ring, 0); /* high dword */
177 intel_ring_emit(ring, MI_NOOP);
178 intel_ring_advance(ring);
180 ret = intel_ring_begin(ring, 6);
184 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
185 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
186 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
187 intel_ring_emit(ring, 0);
188 intel_ring_emit(ring, 0);
189 intel_ring_emit(ring, MI_NOOP);
190 intel_ring_advance(ring);
196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
197 u32 invalidate_domains, u32 flush_domains)
200 struct pipe_control *pc = ring->private;
201 u32 scratch_addr = pc->gtt_offset + 128;
204 /* Force SNB workarounds for PIPE_CONTROL flushes */
205 intel_emit_post_sync_nonzero_flush(ring);
207 /* Just flush everything. Experiments have shown that reducing the
208 * number of bits based on the write domains has little performance
211 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
212 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
213 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
214 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
215 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
216 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
217 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
219 ret = intel_ring_begin(ring, 6);
223 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
224 intel_ring_emit(ring, flags);
225 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
226 intel_ring_emit(ring, 0); /* lower dword */
227 intel_ring_emit(ring, 0); /* uppwer dword */
228 intel_ring_emit(ring, MI_NOOP);
229 intel_ring_advance(ring);
234 static void ring_write_tail(struct intel_ring_buffer *ring,
237 drm_i915_private_t *dev_priv = ring->dev->dev_private;
238 I915_WRITE_TAIL(ring, value);
241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
243 drm_i915_private_t *dev_priv = ring->dev->dev_private;
244 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
245 RING_ACTHD(ring->mmio_base) : ACTHD;
247 return I915_READ(acthd_reg);
250 static int init_ring_common(struct intel_ring_buffer *ring)
252 struct drm_device *dev = ring->dev;
253 drm_i915_private_t *dev_priv = dev->dev_private;
254 struct drm_i915_gem_object *obj = ring->obj;
258 if (HAS_FORCE_WAKE(dev))
259 gen6_gt_force_wake_get(dev_priv);
261 /* Stop the ring if it's running. */
262 I915_WRITE_CTL(ring, 0);
263 I915_WRITE_HEAD(ring, 0);
264 ring->write_tail(ring, 0);
266 head = I915_READ_HEAD(ring) & HEAD_ADDR;
268 /* G45 ring initialization fails to reset head to zero */
270 DRM_DEBUG_KMS("%s head not reset to zero "
271 "ctl %08x head %08x tail %08x start %08x\n",
274 I915_READ_HEAD(ring),
275 I915_READ_TAIL(ring),
276 I915_READ_START(ring));
278 I915_WRITE_HEAD(ring, 0);
280 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
281 DRM_ERROR("failed to set %s head to zero "
282 "ctl %08x head %08x tail %08x start %08x\n",
285 I915_READ_HEAD(ring),
286 I915_READ_TAIL(ring),
287 I915_READ_START(ring));
291 /* Initialize the ring. This must happen _after_ we've cleared the ring
292 * registers with the above sequence (the readback of the HEAD registers
293 * also enforces ordering), otherwise the hw might lose the new ring
294 * register values. */
295 I915_WRITE_START(ring, obj->gtt_offset);
297 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
300 /* If the head is still not zero, the ring is dead */
301 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
302 I915_READ_START(ring) == obj->gtt_offset &&
303 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
304 DRM_ERROR("%s initialization failed "
305 "ctl %08x head %08x tail %08x start %08x\n",
308 I915_READ_HEAD(ring),
309 I915_READ_TAIL(ring),
310 I915_READ_START(ring));
315 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
316 i915_kernel_lost_context(ring->dev);
318 ring->head = I915_READ_HEAD(ring);
319 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
320 ring->space = ring_space(ring);
324 if (HAS_FORCE_WAKE(dev))
325 gen6_gt_force_wake_put(dev_priv);
331 init_pipe_control(struct intel_ring_buffer *ring)
333 struct pipe_control *pc;
334 struct drm_i915_gem_object *obj;
340 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
344 obj = i915_gem_alloc_object(ring->dev, 4096);
346 DRM_ERROR("Failed to allocate seqno page\n");
351 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
353 ret = i915_gem_object_pin(obj, 4096, true);
357 pc->gtt_offset = obj->gtt_offset;
358 pc->cpu_page = kmap(obj->pages[0]);
359 if (pc->cpu_page == NULL)
367 i915_gem_object_unpin(obj);
369 drm_gem_object_unreference(&obj->base);
376 cleanup_pipe_control(struct intel_ring_buffer *ring)
378 struct pipe_control *pc = ring->private;
379 struct drm_i915_gem_object *obj;
385 kunmap(obj->pages[0]);
386 i915_gem_object_unpin(obj);
387 drm_gem_object_unreference(&obj->base);
390 ring->private = NULL;
393 static int init_render_ring(struct intel_ring_buffer *ring)
395 struct drm_device *dev = ring->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int ret = init_ring_common(ring);
399 if (INTEL_INFO(dev)->gen > 3) {
400 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
401 I915_WRITE(MI_MODE, mode);
404 /* We need to disable the AsyncFlip performance optimisations in order
405 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
406 * programmed to '1' on all products.
408 if (INTEL_INFO(dev)->gen >= 6)
409 I915_WRITE(MI_MODE, GFX_MODE_ENABLE(ASYNC_FLIP_PERF_DISABLE));
411 /* Required for the hardware to program scanline values for waiting */
412 if (INTEL_INFO(dev)->gen == 6)
414 GFX_MODE_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
417 I915_WRITE(GFX_MODE_GEN7,
418 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
419 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
421 if (INTEL_INFO(dev)->gen >= 5) {
422 ret = init_pipe_control(ring);
429 /* From the Sandybridge PRM, volume 1 part 3, page 24:
430 * "If this bit is set, STCunit will have LRA as replacement
431 * policy. [...] This bit must be reset. LRA replacement
432 * policy is not supported."
434 I915_WRITE(CACHE_MODE_0,
435 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
438 if (INTEL_INFO(dev)->gen >= 6) {
440 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
446 static void render_ring_cleanup(struct intel_ring_buffer *ring)
451 cleanup_pipe_control(ring);
455 update_mboxes(struct intel_ring_buffer *ring,
459 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
460 MI_SEMAPHORE_GLOBAL_GTT |
461 MI_SEMAPHORE_REGISTER |
462 MI_SEMAPHORE_UPDATE);
463 intel_ring_emit(ring, seqno);
464 intel_ring_emit(ring, mmio_offset);
468 * gen6_add_request - Update the semaphore mailbox registers
470 * @ring - ring that is adding a request
471 * @seqno - return seqno stuck into the ring
473 * Update the mailbox registers in the *other* rings with the current seqno.
474 * This acts like a signal in the canonical semaphore.
477 gen6_add_request(struct intel_ring_buffer *ring,
484 ret = intel_ring_begin(ring, 10);
488 mbox1_reg = ring->signal_mbox[0];
489 mbox2_reg = ring->signal_mbox[1];
491 *seqno = i915_gem_next_request_seqno(ring);
493 update_mboxes(ring, *seqno, mbox1_reg);
494 update_mboxes(ring, *seqno, mbox2_reg);
495 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
496 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
497 intel_ring_emit(ring, *seqno);
498 intel_ring_emit(ring, MI_USER_INTERRUPT);
499 intel_ring_advance(ring);
505 * intel_ring_sync - sync the waiter to the signaller on seqno
507 * @waiter - ring that is waiting
508 * @signaller - ring which has, or will signal
509 * @seqno - seqno which the waiter will block on
512 intel_ring_sync(struct intel_ring_buffer *waiter,
513 struct intel_ring_buffer *signaller,
518 u32 dw1 = MI_SEMAPHORE_MBOX |
519 MI_SEMAPHORE_COMPARE |
520 MI_SEMAPHORE_REGISTER;
522 ret = intel_ring_begin(waiter, 4);
526 intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
527 intel_ring_emit(waiter, seqno);
528 intel_ring_emit(waiter, 0);
529 intel_ring_emit(waiter, MI_NOOP);
530 intel_ring_advance(waiter);
535 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
537 render_ring_sync_to(struct intel_ring_buffer *waiter,
538 struct intel_ring_buffer *signaller,
541 WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
542 return intel_ring_sync(waiter,
548 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
550 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
551 struct intel_ring_buffer *signaller,
554 WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
555 return intel_ring_sync(waiter,
561 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
563 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
564 struct intel_ring_buffer *signaller,
567 WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
568 return intel_ring_sync(waiter,
576 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
578 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
579 PIPE_CONTROL_DEPTH_STALL); \
580 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
581 intel_ring_emit(ring__, 0); \
582 intel_ring_emit(ring__, 0); \
586 pc_render_add_request(struct intel_ring_buffer *ring,
589 u32 seqno = i915_gem_next_request_seqno(ring);
590 struct pipe_control *pc = ring->private;
591 u32 scratch_addr = pc->gtt_offset + 128;
594 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
595 * incoherent with writes to memory, i.e. completely fubar,
596 * so we need to use PIPE_NOTIFY instead.
598 * However, we also need to workaround the qword write
599 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
600 * memory before requesting an interrupt.
602 ret = intel_ring_begin(ring, 32);
606 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
607 PIPE_CONTROL_WRITE_FLUSH |
608 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
609 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
610 intel_ring_emit(ring, seqno);
611 intel_ring_emit(ring, 0);
612 PIPE_CONTROL_FLUSH(ring, scratch_addr);
613 scratch_addr += 128; /* write to separate cachelines */
614 PIPE_CONTROL_FLUSH(ring, scratch_addr);
616 PIPE_CONTROL_FLUSH(ring, scratch_addr);
618 PIPE_CONTROL_FLUSH(ring, scratch_addr);
620 PIPE_CONTROL_FLUSH(ring, scratch_addr);
622 PIPE_CONTROL_FLUSH(ring, scratch_addr);
623 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
624 PIPE_CONTROL_WRITE_FLUSH |
625 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
626 PIPE_CONTROL_NOTIFY);
627 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
628 intel_ring_emit(ring, seqno);
629 intel_ring_emit(ring, 0);
630 intel_ring_advance(ring);
637 render_ring_add_request(struct intel_ring_buffer *ring,
640 u32 seqno = i915_gem_next_request_seqno(ring);
643 ret = intel_ring_begin(ring, 4);
647 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
648 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
649 intel_ring_emit(ring, seqno);
650 intel_ring_emit(ring, MI_USER_INTERRUPT);
651 intel_ring_advance(ring);
658 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
660 struct drm_device *dev = ring->dev;
662 /* Workaround to force correct ordering between irq and seqno writes on
663 * ivb (and maybe also on snb) by reading from a CS register (like
664 * ACTHD) before reading the status page. */
666 intel_ring_get_active_head(ring);
667 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
671 ring_get_seqno(struct intel_ring_buffer *ring)
673 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
677 pc_render_get_seqno(struct intel_ring_buffer *ring)
679 struct pipe_control *pc = ring->private;
680 return pc->cpu_page[0];
684 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
686 dev_priv->gt_irq_mask &= ~mask;
687 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
692 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
694 dev_priv->gt_irq_mask |= mask;
695 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
700 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
702 dev_priv->irq_mask &= ~mask;
703 I915_WRITE(IMR, dev_priv->irq_mask);
708 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
710 dev_priv->irq_mask |= mask;
711 I915_WRITE(IMR, dev_priv->irq_mask);
716 render_ring_get_irq(struct intel_ring_buffer *ring)
718 struct drm_device *dev = ring->dev;
719 drm_i915_private_t *dev_priv = dev->dev_private;
721 if (!dev->irq_enabled)
724 spin_lock(&ring->irq_lock);
725 if (ring->irq_refcount++ == 0) {
726 if (HAS_PCH_SPLIT(dev))
727 ironlake_enable_irq(dev_priv,
728 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
730 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
732 spin_unlock(&ring->irq_lock);
738 render_ring_put_irq(struct intel_ring_buffer *ring)
740 struct drm_device *dev = ring->dev;
741 drm_i915_private_t *dev_priv = dev->dev_private;
743 spin_lock(&ring->irq_lock);
744 if (--ring->irq_refcount == 0) {
745 if (HAS_PCH_SPLIT(dev))
746 ironlake_disable_irq(dev_priv,
750 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
752 spin_unlock(&ring->irq_lock);
755 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
757 struct drm_device *dev = ring->dev;
758 drm_i915_private_t *dev_priv = ring->dev->dev_private;
761 /* The ring status page addresses are no longer next to the rest of
762 * the ring registers as of gen7.
767 mmio = RENDER_HWS_PGA_GEN7;
770 mmio = BLT_HWS_PGA_GEN7;
773 mmio = BSD_HWS_PGA_GEN7;
776 } else if (IS_GEN6(ring->dev)) {
777 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
779 mmio = RING_HWS_PGA(ring->mmio_base);
782 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
787 bsd_ring_flush(struct intel_ring_buffer *ring,
788 u32 invalidate_domains,
793 ret = intel_ring_begin(ring, 2);
797 intel_ring_emit(ring, MI_FLUSH);
798 intel_ring_emit(ring, MI_NOOP);
799 intel_ring_advance(ring);
804 ring_add_request(struct intel_ring_buffer *ring,
810 ret = intel_ring_begin(ring, 4);
814 seqno = i915_gem_next_request_seqno(ring);
816 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
817 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
818 intel_ring_emit(ring, seqno);
819 intel_ring_emit(ring, MI_USER_INTERRUPT);
820 intel_ring_advance(ring);
827 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
829 struct drm_device *dev = ring->dev;
830 drm_i915_private_t *dev_priv = dev->dev_private;
832 if (!dev->irq_enabled)
835 /* It looks like we need to prevent the gt from suspending while waiting
836 * for an notifiy irq, otherwise irqs seem to get lost on at least the
837 * blt/bsd rings on ivb. */
839 gen6_gt_force_wake_get(dev_priv);
841 spin_lock(&ring->irq_lock);
842 if (ring->irq_refcount++ == 0) {
843 ring->irq_mask &= ~rflag;
844 I915_WRITE_IMR(ring, ring->irq_mask);
845 ironlake_enable_irq(dev_priv, gflag);
847 spin_unlock(&ring->irq_lock);
853 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
855 struct drm_device *dev = ring->dev;
856 drm_i915_private_t *dev_priv = dev->dev_private;
858 spin_lock(&ring->irq_lock);
859 if (--ring->irq_refcount == 0) {
860 ring->irq_mask |= rflag;
861 I915_WRITE_IMR(ring, ring->irq_mask);
862 ironlake_disable_irq(dev_priv, gflag);
864 spin_unlock(&ring->irq_lock);
867 gen6_gt_force_wake_put(dev_priv);
871 bsd_ring_get_irq(struct intel_ring_buffer *ring)
873 struct drm_device *dev = ring->dev;
874 drm_i915_private_t *dev_priv = dev->dev_private;
876 if (!dev->irq_enabled)
879 spin_lock(&ring->irq_lock);
880 if (ring->irq_refcount++ == 0) {
882 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
884 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
886 spin_unlock(&ring->irq_lock);
891 bsd_ring_put_irq(struct intel_ring_buffer *ring)
893 struct drm_device *dev = ring->dev;
894 drm_i915_private_t *dev_priv = dev->dev_private;
896 spin_lock(&ring->irq_lock);
897 if (--ring->irq_refcount == 0) {
899 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
901 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
903 spin_unlock(&ring->irq_lock);
907 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
911 ret = intel_ring_begin(ring, 2);
915 intel_ring_emit(ring,
916 MI_BATCH_BUFFER_START | (2 << 6) |
917 MI_BATCH_NON_SECURE_I965);
918 intel_ring_emit(ring, offset);
919 intel_ring_advance(ring);
925 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
928 struct drm_device *dev = ring->dev;
931 if (IS_I830(dev) || IS_845G(dev)) {
932 ret = intel_ring_begin(ring, 4);
936 intel_ring_emit(ring, MI_BATCH_BUFFER);
937 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
938 intel_ring_emit(ring, offset + len - 8);
939 intel_ring_emit(ring, 0);
941 ret = intel_ring_begin(ring, 2);
945 if (INTEL_INFO(dev)->gen >= 4) {
946 intel_ring_emit(ring,
947 MI_BATCH_BUFFER_START | (2 << 6) |
948 MI_BATCH_NON_SECURE_I965);
949 intel_ring_emit(ring, offset);
951 intel_ring_emit(ring,
952 MI_BATCH_BUFFER_START | (2 << 6));
953 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
956 intel_ring_advance(ring);
961 static void cleanup_status_page(struct intel_ring_buffer *ring)
963 drm_i915_private_t *dev_priv = ring->dev->dev_private;
964 struct drm_i915_gem_object *obj;
966 obj = ring->status_page.obj;
970 kunmap(obj->pages[0]);
971 i915_gem_object_unpin(obj);
972 drm_gem_object_unreference(&obj->base);
973 ring->status_page.obj = NULL;
975 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
978 static int init_status_page(struct intel_ring_buffer *ring)
980 struct drm_device *dev = ring->dev;
981 drm_i915_private_t *dev_priv = dev->dev_private;
982 struct drm_i915_gem_object *obj;
985 obj = i915_gem_alloc_object(dev, 4096);
987 DRM_ERROR("Failed to allocate status page\n");
992 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
994 ret = i915_gem_object_pin(obj, 4096, true);
999 ring->status_page.gfx_addr = obj->gtt_offset;
1000 ring->status_page.page_addr = kmap(obj->pages[0]);
1001 if (ring->status_page.page_addr == NULL) {
1002 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
1005 ring->status_page.obj = obj;
1006 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1008 intel_ring_setup_status_page(ring);
1009 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1010 ring->name, ring->status_page.gfx_addr);
1015 i915_gem_object_unpin(obj);
1017 drm_gem_object_unreference(&obj->base);
1022 int intel_init_ring_buffer(struct drm_device *dev,
1023 struct intel_ring_buffer *ring)
1025 struct drm_i915_gem_object *obj;
1029 INIT_LIST_HEAD(&ring->active_list);
1030 INIT_LIST_HEAD(&ring->request_list);
1031 INIT_LIST_HEAD(&ring->gpu_write_list);
1033 init_waitqueue_head(&ring->irq_queue);
1034 spin_lock_init(&ring->irq_lock);
1035 ring->irq_mask = ~0;
1037 if (I915_NEED_GFX_HWS(dev)) {
1038 ret = init_status_page(ring);
1043 obj = i915_gem_alloc_object(dev, ring->size);
1045 DRM_ERROR("Failed to allocate ringbuffer\n");
1052 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1056 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1060 ring->map.size = ring->size;
1061 ring->map.offset = dev->agp->base + obj->gtt_offset;
1063 ring->map.flags = 0;
1066 drm_core_ioremap_wc(&ring->map, dev);
1067 if (ring->map.handle == NULL) {
1068 DRM_ERROR("Failed to map ringbuffer.\n");
1073 ring->virtual_start = ring->map.handle;
1074 ret = ring->init(ring);
1078 /* Workaround an erratum on the i830 which causes a hang if
1079 * the TAIL pointer points to within the last 2 cachelines
1082 ring->effective_size = ring->size;
1083 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1084 ring->effective_size -= 128;
1089 drm_core_ioremapfree(&ring->map, dev);
1091 i915_gem_object_unpin(obj);
1093 drm_gem_object_unreference(&obj->base);
1096 cleanup_status_page(ring);
1100 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1102 struct drm_i915_private *dev_priv;
1105 if (ring->obj == NULL)
1108 /* Disable the ring buffer. The ring must be idle at this point */
1109 dev_priv = ring->dev->dev_private;
1110 ret = intel_wait_ring_idle(ring);
1112 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1115 I915_WRITE_CTL(ring, 0);
1117 drm_core_ioremapfree(&ring->map, ring->dev);
1119 i915_gem_object_unpin(ring->obj);
1120 drm_gem_object_unreference(&ring->obj->base);
1124 ring->cleanup(ring);
1126 cleanup_status_page(ring);
1129 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1132 int rem = ring->size - ring->tail;
1134 if (ring->space < rem) {
1135 int ret = intel_wait_ring_buffer(ring, rem);
1140 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1148 ring->space = ring_space(ring);
1153 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1155 struct drm_device *dev = ring->dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private;
1159 trace_i915_ring_wait_begin(ring);
1160 end = jiffies + 3 * HZ;
1162 ring->head = I915_READ_HEAD(ring);
1163 ring->space = ring_space(ring);
1164 if (ring->space >= n) {
1165 trace_i915_ring_wait_end(ring);
1169 if (dev->primary->master) {
1170 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1171 if (master_priv->sarea_priv)
1172 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1176 if (atomic_read(&dev_priv->mm.wedged))
1178 } while (!time_after(jiffies, end));
1179 trace_i915_ring_wait_end(ring);
1183 int intel_ring_begin(struct intel_ring_buffer *ring,
1186 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1187 int n = 4*num_dwords;
1190 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1193 if (unlikely(ring->tail + n > ring->effective_size)) {
1194 ret = intel_wrap_ring_buffer(ring);
1199 if (unlikely(ring->space < n)) {
1200 ret = intel_wait_ring_buffer(ring, n);
1209 void intel_ring_advance(struct intel_ring_buffer *ring)
1211 ring->tail &= ring->size - 1;
1212 ring->write_tail(ring, ring->tail);
1215 static const struct intel_ring_buffer render_ring = {
1216 .name = "render ring",
1218 .mmio_base = RENDER_RING_BASE,
1219 .size = 32 * PAGE_SIZE,
1220 .init = init_render_ring,
1221 .write_tail = ring_write_tail,
1222 .flush = render_ring_flush,
1223 .add_request = render_ring_add_request,
1224 .get_seqno = ring_get_seqno,
1225 .irq_get = render_ring_get_irq,
1226 .irq_put = render_ring_put_irq,
1227 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1228 .cleanup = render_ring_cleanup,
1229 .sync_to = render_ring_sync_to,
1230 .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID,
1231 MI_SEMAPHORE_SYNC_RV,
1232 MI_SEMAPHORE_SYNC_RB},
1233 .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC},
1236 /* ring buffer for bit-stream decoder */
1238 static const struct intel_ring_buffer bsd_ring = {
1241 .mmio_base = BSD_RING_BASE,
1242 .size = 32 * PAGE_SIZE,
1243 .init = init_ring_common,
1244 .write_tail = ring_write_tail,
1245 .flush = bsd_ring_flush,
1246 .add_request = ring_add_request,
1247 .get_seqno = ring_get_seqno,
1248 .irq_get = bsd_ring_get_irq,
1249 .irq_put = bsd_ring_put_irq,
1250 .dispatch_execbuffer = ring_dispatch_execbuffer,
1254 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1257 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1259 /* Every tail move must follow the sequence below */
1260 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1261 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1262 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1263 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1265 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1266 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1268 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1270 I915_WRITE_TAIL(ring, value);
1271 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1272 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1273 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1276 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1277 u32 invalidate, u32 flush)
1282 ret = intel_ring_begin(ring, 4);
1287 if (invalidate & I915_GEM_GPU_DOMAINS)
1288 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1289 intel_ring_emit(ring, cmd);
1290 intel_ring_emit(ring, 0);
1291 intel_ring_emit(ring, 0);
1292 intel_ring_emit(ring, MI_NOOP);
1293 intel_ring_advance(ring);
1298 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1299 u32 offset, u32 len)
1303 ret = intel_ring_begin(ring, 2);
1307 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1308 /* bit0-7 is the length on GEN6+ */
1309 intel_ring_emit(ring, offset);
1310 intel_ring_advance(ring);
1316 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1318 return gen6_ring_get_irq(ring,
1320 GEN6_RENDER_USER_INTERRUPT);
1324 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1326 return gen6_ring_put_irq(ring,
1328 GEN6_RENDER_USER_INTERRUPT);
1332 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1334 return gen6_ring_get_irq(ring,
1335 GT_GEN6_BSD_USER_INTERRUPT,
1336 GEN6_BSD_USER_INTERRUPT);
1340 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1342 return gen6_ring_put_irq(ring,
1343 GT_GEN6_BSD_USER_INTERRUPT,
1344 GEN6_BSD_USER_INTERRUPT);
1347 /* ring buffer for Video Codec for Gen6+ */
1348 static const struct intel_ring_buffer gen6_bsd_ring = {
1349 .name = "gen6 bsd ring",
1351 .mmio_base = GEN6_BSD_RING_BASE,
1352 .size = 32 * PAGE_SIZE,
1353 .init = init_ring_common,
1354 .write_tail = gen6_bsd_ring_write_tail,
1355 .flush = gen6_ring_flush,
1356 .add_request = gen6_add_request,
1357 .get_seqno = gen6_ring_get_seqno,
1358 .irq_get = gen6_bsd_ring_get_irq,
1359 .irq_put = gen6_bsd_ring_put_irq,
1360 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1361 .sync_to = gen6_bsd_ring_sync_to,
1362 .semaphore_register = {MI_SEMAPHORE_SYNC_VR,
1363 MI_SEMAPHORE_SYNC_INVALID,
1364 MI_SEMAPHORE_SYNC_VB},
1365 .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
1368 /* Blitter support (SandyBridge+) */
1371 blt_ring_get_irq(struct intel_ring_buffer *ring)
1373 return gen6_ring_get_irq(ring,
1374 GT_BLT_USER_INTERRUPT,
1375 GEN6_BLITTER_USER_INTERRUPT);
1379 blt_ring_put_irq(struct intel_ring_buffer *ring)
1381 gen6_ring_put_irq(ring,
1382 GT_BLT_USER_INTERRUPT,
1383 GEN6_BLITTER_USER_INTERRUPT);
1387 /* Workaround for some stepping of SNB,
1388 * each time when BLT engine ring tail moved,
1389 * the first command in the ring to be parsed
1390 * should be MI_BATCH_BUFFER_START
1392 #define NEED_BLT_WORKAROUND(dev) \
1393 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1395 static inline struct drm_i915_gem_object *
1396 to_blt_workaround(struct intel_ring_buffer *ring)
1398 return ring->private;
1401 static int blt_ring_init(struct intel_ring_buffer *ring)
1403 if (NEED_BLT_WORKAROUND(ring->dev)) {
1404 struct drm_i915_gem_object *obj;
1408 obj = i915_gem_alloc_object(ring->dev, 4096);
1412 ret = i915_gem_object_pin(obj, 4096, true);
1414 drm_gem_object_unreference(&obj->base);
1418 ptr = kmap(obj->pages[0]);
1419 *ptr++ = MI_BATCH_BUFFER_END;
1421 kunmap(obj->pages[0]);
1423 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1425 i915_gem_object_unpin(obj);
1426 drm_gem_object_unreference(&obj->base);
1430 ring->private = obj;
1433 return init_ring_common(ring);
1436 static int blt_ring_begin(struct intel_ring_buffer *ring,
1439 if (ring->private) {
1440 int ret = intel_ring_begin(ring, num_dwords+2);
1444 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1445 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1449 return intel_ring_begin(ring, 4);
1452 static int blt_ring_flush(struct intel_ring_buffer *ring,
1453 u32 invalidate, u32 flush)
1458 ret = blt_ring_begin(ring, 4);
1463 if (invalidate & I915_GEM_DOMAIN_RENDER)
1464 cmd |= MI_INVALIDATE_TLB;
1465 intel_ring_emit(ring, cmd);
1466 intel_ring_emit(ring, 0);
1467 intel_ring_emit(ring, 0);
1468 intel_ring_emit(ring, MI_NOOP);
1469 intel_ring_advance(ring);
1473 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1478 i915_gem_object_unpin(ring->private);
1479 drm_gem_object_unreference(ring->private);
1480 ring->private = NULL;
1483 static const struct intel_ring_buffer gen6_blt_ring = {
1486 .mmio_base = BLT_RING_BASE,
1487 .size = 32 * PAGE_SIZE,
1488 .init = blt_ring_init,
1489 .write_tail = ring_write_tail,
1490 .flush = blt_ring_flush,
1491 .add_request = gen6_add_request,
1492 .get_seqno = gen6_ring_get_seqno,
1493 .irq_get = blt_ring_get_irq,
1494 .irq_put = blt_ring_put_irq,
1495 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1496 .cleanup = blt_ring_cleanup,
1497 .sync_to = gen6_blt_ring_sync_to,
1498 .semaphore_register = {MI_SEMAPHORE_SYNC_BR,
1499 MI_SEMAPHORE_SYNC_BV,
1500 MI_SEMAPHORE_SYNC_INVALID},
1501 .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
1504 int intel_init_render_ring_buffer(struct drm_device *dev)
1506 drm_i915_private_t *dev_priv = dev->dev_private;
1507 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1509 *ring = render_ring;
1510 if (INTEL_INFO(dev)->gen >= 6) {
1511 ring->add_request = gen6_add_request;
1512 ring->flush = gen6_render_ring_flush;
1513 ring->irq_get = gen6_render_ring_get_irq;
1514 ring->irq_put = gen6_render_ring_put_irq;
1515 ring->get_seqno = gen6_ring_get_seqno;
1516 } else if (IS_GEN5(dev)) {
1517 ring->add_request = pc_render_add_request;
1518 ring->get_seqno = pc_render_get_seqno;
1521 if (!I915_NEED_GFX_HWS(dev)) {
1522 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1523 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1526 return intel_init_ring_buffer(dev, ring);
1529 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1531 drm_i915_private_t *dev_priv = dev->dev_private;
1532 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1534 *ring = render_ring;
1535 if (INTEL_INFO(dev)->gen >= 6) {
1536 ring->add_request = gen6_add_request;
1537 ring->irq_get = gen6_render_ring_get_irq;
1538 ring->irq_put = gen6_render_ring_put_irq;
1539 } else if (IS_GEN5(dev)) {
1540 ring->add_request = pc_render_add_request;
1541 ring->get_seqno = pc_render_get_seqno;
1544 if (!I915_NEED_GFX_HWS(dev))
1545 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1548 INIT_LIST_HEAD(&ring->active_list);
1549 INIT_LIST_HEAD(&ring->request_list);
1550 INIT_LIST_HEAD(&ring->gpu_write_list);
1553 ring->effective_size = ring->size;
1554 if (IS_I830(ring->dev))
1555 ring->effective_size -= 128;
1557 ring->map.offset = start;
1558 ring->map.size = size;
1560 ring->map.flags = 0;
1563 drm_core_ioremap_wc(&ring->map, dev);
1564 if (ring->map.handle == NULL) {
1565 DRM_ERROR("can not ioremap virtual address for"
1570 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1574 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1576 drm_i915_private_t *dev_priv = dev->dev_private;
1577 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1579 if (IS_GEN6(dev) || IS_GEN7(dev))
1580 *ring = gen6_bsd_ring;
1584 return intel_init_ring_buffer(dev, ring);
1587 int intel_init_blt_ring_buffer(struct drm_device *dev)
1589 drm_i915_private_t *dev_priv = dev->dev_private;
1590 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1592 *ring = gen6_blt_ring;
1594 return intel_init_ring_buffer(dev, ring);