drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static inline int ring_space(struct intel_ring_buffer *ring)
  38 {
  39         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  40         if (space < 0)
  41                 space += ring->size;
  42         return space;
  43 }
  44
  45 static u32 i915_gem_get_seqno(struct drm_device *dev)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         u32 seqno;
  49
  50         seqno = dev_priv->next_seqno;
  51
  52         /* reserve 0 for non-seqno */
  53         if (++dev_priv->next_seqno == 0)
  54                 dev_priv->next_seqno = 1;
  55
  56         return seqno;
  57 }
  58
  59 static int
  60 render_ring_flush(struct intel_ring_buffer *ring,
  61                   u32   invalidate_domains,
  62                   u32   flush_domains)
  63 {
  64         struct drm_device *dev = ring->dev;
  65         u32 cmd;
  66         int ret;
  67
  68         /*
  69          * read/write caches:
  70          *
  71          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  72          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  73          * also flushed at 2d versus 3d pipeline switches.
  74          *
  75          * read-only caches:
  76          *
  77          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  78          * MI_READ_FLUSH is set, and is always flushed on 965.
  79          *
  80          * I915_GEM_DOMAIN_COMMAND may not exist?
  81          *
  82          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  83          * invalidated when MI_EXE_FLUSH is set.
  84          *
  85          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  86          * invalidated with every MI_FLUSH.
  87          *
  88          * TLBs:
  89          *
  90          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  91          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  92          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  93          * are flushed at any MI_FLUSH.
  94          */
  95
  96         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  97         if ((invalidate_domains|flush_domains) &
  98             I915_GEM_DOMAIN_RENDER)
  99                 cmd &= ~MI_NO_WRITE_FLUSH;
 100         if (INTEL_INFO(dev)->gen < 4) {
 101                 /*
 102                  * On the 965, the sampler cache always gets flushed
 103                  * and this bit is reserved.
 104                  */
 105                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                         cmd |= MI_READ_FLUSH;
 107         }
 108         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 109                 cmd |= MI_EXE_FLUSH;
 110
 111         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 112             (IS_G4X(dev) || IS_GEN5(dev)))
 113                 cmd |= MI_INVALIDATE_ISP;
 114
 115         ret = intel_ring_begin(ring, 2);
 116         if (ret)
 117                 return ret;
 118
 119         intel_ring_emit(ring, cmd);
 120         intel_ring_emit(ring, MI_NOOP);
 121         intel_ring_advance(ring);
 122
 123         return 0;
 124 }
 125
 126 static void ring_write_tail(struct intel_ring_buffer *ring,
 127                             u32 value)
 128 {
 129         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 130         I915_WRITE_TAIL(ring, value);
 131 }
 132
 133 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 134 {
 135         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 136         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 137                         RING_ACTHD(ring->mmio_base) : ACTHD;
 138
 139         return I915_READ(acthd_reg);
 140 }
 141
 142 static int init_ring_common(struct intel_ring_buffer *ring)
 143 {
 144         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 145         struct drm_i915_gem_object *obj = ring->obj;
 146         u32 head;
 147
 148         /* Stop the ring if it's running. */
 149         I915_WRITE_CTL(ring, 0);
 150         I915_WRITE_HEAD(ring, 0);
 151         ring->write_tail(ring, 0);
 152
 153         /* Initialize the ring. */
 154         I915_WRITE_START(ring, obj->gtt_offset);
 155         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 156
 157         /* G45 ring initialization fails to reset head to zero */
 158         if (head != 0) {
 159                 DRM_DEBUG_KMS("%s head not reset to zero "
 160                               "ctl %08x head %08x tail %08x start %08x\n",
 161                               ring->name,
 162                               I915_READ_CTL(ring),
 163                               I915_READ_HEAD(ring),
 164                               I915_READ_TAIL(ring),
 165                               I915_READ_START(ring));
 166
 167                 I915_WRITE_HEAD(ring, 0);
 168
 169                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 170                         DRM_ERROR("failed to set %s head to zero "
 171                                   "ctl %08x head %08x tail %08x start %08x\n",
 172                                   ring->name,
 173                                   I915_READ_CTL(ring),
 174                                   I915_READ_HEAD(ring),
 175                                   I915_READ_TAIL(ring),
 176                                   I915_READ_START(ring));
 177                 }
 178         }
 179
 180         I915_WRITE_CTL(ring,
 181                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 182                         | RING_REPORT_64K | RING_VALID);
 183
 184         /* If the head is still not zero, the ring is dead */
 185         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 186             I915_READ_START(ring) != obj->gtt_offset ||
 187             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 188                 DRM_ERROR("%s initialization failed "
 189                                 "ctl %08x head %08x tail %08x start %08x\n",
 190                                 ring->name,
 191                                 I915_READ_CTL(ring),
 192                                 I915_READ_HEAD(ring),
 193                                 I915_READ_TAIL(ring),
 194                                 I915_READ_START(ring));
 195                 return -EIO;
 196         }
 197
 198         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 199                 i915_kernel_lost_context(ring->dev);
 200         else {
 201                 ring->head = I915_READ_HEAD(ring);
 202                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 203                 ring->space = ring_space(ring);
 204         }
 205
 206         return 0;
 207 }
 208
 209 /*
 210  * 965+ support PIPE_CONTROL commands, which provide finer grained control
 211  * over cache flushing.
 212  */
 213 struct pipe_control {
 214         struct drm_i915_gem_object *obj;
 215         volatile u32 *cpu_page;
 216         u32 gtt_offset;
 217 };
 218
 219 static int
 220 init_pipe_control(struct intel_ring_buffer *ring)
 221 {
 222         struct pipe_control *pc;
 223         struct drm_i915_gem_object *obj;
 224         int ret;
 225
 226         if (ring->private)
 227                 return 0;
 228
 229         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 230         if (!pc)
 231                 return -ENOMEM;
 232
 233         obj = i915_gem_alloc_object(ring->dev, 4096);
 234         if (obj == NULL) {
 235                 DRM_ERROR("Failed to allocate seqno page\n");
 236                 ret = -ENOMEM;
 237                 goto err;
 238         }
 239
 240         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 241
 242         ret = i915_gem_object_pin(obj, 4096, true);
 243         if (ret)
 244                 goto err_unref;
 245
 246         pc->gtt_offset = obj->gtt_offset;
 247         pc->cpu_page =  kmap(obj->pages[0]);
 248         if (pc->cpu_page == NULL)
 249                 goto err_unpin;
 250
 251         pc->obj = obj;
 252         ring->private = pc;
 253         return 0;
 254
 255 err_unpin:
 256         i915_gem_object_unpin(obj);
 257 err_unref:
 258         drm_gem_object_unreference(&obj->base);
 259 err:
 260         kfree(pc);
 261         return ret;
 262 }
 263
 264 static void
 265 cleanup_pipe_control(struct intel_ring_buffer *ring)
 266 {
 267         struct pipe_control *pc = ring->private;
 268         struct drm_i915_gem_object *obj;
 269
 270         if (!ring->private)
 271                 return;
 272
 273         obj = pc->obj;
 274         kunmap(obj->pages[0]);
 275         i915_gem_object_unpin(obj);
 276         drm_gem_object_unreference(&obj->base);
 277
 278         kfree(pc);
 279         ring->private = NULL;
 280 }
 281
 282 static int init_render_ring(struct intel_ring_buffer *ring)
 283 {
 284         struct drm_device *dev = ring->dev;
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         int ret = init_ring_common(ring);
 287
 288         if (INTEL_INFO(dev)->gen > 3) {
 289                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 290                 if (IS_GEN6(dev) || IS_GEN7(dev))
 291                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 292                 I915_WRITE(MI_MODE, mode);
 293                 if (IS_GEN7(dev))
 294                         I915_WRITE(GFX_MODE_GEN7,
 295                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 296                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
 297         }
 298
 299         if (INTEL_INFO(dev)->gen >= 6) {
 300         } else if (IS_GEN5(dev)) {
 301                 ret = init_pipe_control(ring);
 302                 if (ret)
 303                         return ret;
 304         }
 305
 306         return ret;
 307 }
 308
 309 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 310 {
 311         if (!ring->private)
 312                 return;
 313
 314         cleanup_pipe_control(ring);
 315 }
 316
 317 static void
 318 update_mboxes(struct intel_ring_buffer *ring,
 319             u32 seqno,
 320             u32 mmio_offset)
 321 {
 322         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 323                               MI_SEMAPHORE_GLOBAL_GTT |
 324                               MI_SEMAPHORE_REGISTER |
 325                               MI_SEMAPHORE_UPDATE);
 326         intel_ring_emit(ring, seqno);
 327         intel_ring_emit(ring, mmio_offset);
 328 }
 329
 330 /**
 331  * gen6_add_request - Update the semaphore mailbox registers
 332  *
 333  * @ring - ring that is adding a request
 334  * @seqno - return seqno stuck into the ring
 335  *
 336  * Update the mailbox registers in the *other* rings with the current seqno.
 337  * This acts like a signal in the canonical semaphore.
 338  */
 339 static int
 340 gen6_add_request(struct intel_ring_buffer *ring,
 341                  u32 *seqno)
 342 {
 343         u32 mbox1_reg;
 344         u32 mbox2_reg;
 345         int ret;
 346
 347         ret = intel_ring_begin(ring, 10);
 348         if (ret)
 349                 return ret;
 350
 351         mbox1_reg = ring->signal_mbox[0];
 352         mbox2_reg = ring->signal_mbox[1];
 353
 354         *seqno = i915_gem_get_seqno(ring->dev);
 355
 356         update_mboxes(ring, *seqno, mbox1_reg);
 357         update_mboxes(ring, *seqno, mbox2_reg);
 358         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 359         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 360         intel_ring_emit(ring, *seqno);
 361         intel_ring_emit(ring, MI_USER_INTERRUPT);
 362         intel_ring_advance(ring);
 363
 364         return 0;
 365 }
 366
 367 /**
 368  * intel_ring_sync - sync the waiter to the signaller on seqno
 369  *
 370  * @waiter - ring that is waiting
 371  * @signaller - ring which has, or will signal
 372  * @seqno - seqno which the waiter will block on
 373  */
 374 static int
 375 intel_ring_sync(struct intel_ring_buffer *waiter,
 376                 struct intel_ring_buffer *signaller,
 377                 int ring,
 378                 u32 seqno)
 379 {
 380         int ret;
 381         u32 dw1 = MI_SEMAPHORE_MBOX |
 382                   MI_SEMAPHORE_COMPARE |
 383                   MI_SEMAPHORE_REGISTER;
 384
 385         ret = intel_ring_begin(waiter, 4);
 386         if (ret)
 387                 return ret;
 388
 389         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
 390         intel_ring_emit(waiter, seqno);
 391         intel_ring_emit(waiter, 0);
 392         intel_ring_emit(waiter, MI_NOOP);
 393         intel_ring_advance(waiter);
 394
 395         return 0;
 396 }
 397
 398 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
 399 int
 400 render_ring_sync_to(struct intel_ring_buffer *waiter,
 401                     struct intel_ring_buffer *signaller,
 402                     u32 seqno)
 403 {
 404         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
 405         return intel_ring_sync(waiter,
 406                                signaller,
 407                                RCS,
 408                                seqno);
 409 }
 410
 411 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
 412 int
 413 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
 414                       struct intel_ring_buffer *signaller,
 415                       u32 seqno)
 416 {
 417         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
 418         return intel_ring_sync(waiter,
 419                                signaller,
 420                                VCS,
 421                                seqno);
 422 }
 423
 424 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
 425 int
 426 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
 427                       struct intel_ring_buffer *signaller,
 428                       u32 seqno)
 429 {
 430         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
 431         return intel_ring_sync(waiter,
 432                                signaller,
 433                                BCS,
 434                                seqno);
 435 }
 436
 437
 438
 439 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 440 do {                                                                    \
 441         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
 442                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 443         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 444         intel_ring_emit(ring__, 0);                                                     \
 445         intel_ring_emit(ring__, 0);                                                     \
 446 } while (0)
 447
 448 static int
 449 pc_render_add_request(struct intel_ring_buffer *ring,
 450                       u32 *result)
 451 {
 452         struct drm_device *dev = ring->dev;
 453         u32 seqno = i915_gem_get_seqno(dev);
 454         struct pipe_control *pc = ring->private;
 455         u32 scratch_addr = pc->gtt_offset + 128;
 456         int ret;
 457
 458         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 459          * incoherent with writes to memory, i.e. completely fubar,
 460          * so we need to use PIPE_NOTIFY instead.
 461          *
 462          * However, we also need to workaround the qword write
 463          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 464          * memory before requesting an interrupt.
 465          */
 466         ret = intel_ring_begin(ring, 32);
 467         if (ret)
 468                 return ret;
 469
 470         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 471                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 472         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 473         intel_ring_emit(ring, seqno);
 474         intel_ring_emit(ring, 0);
 475         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 476         scratch_addr += 128; /* write to separate cachelines */
 477         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 478         scratch_addr += 128;
 479         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 480         scratch_addr += 128;
 481         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 482         scratch_addr += 128;
 483         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 484         scratch_addr += 128;
 485         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 486         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 487                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 488                         PIPE_CONTROL_NOTIFY);
 489         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 490         intel_ring_emit(ring, seqno);
 491         intel_ring_emit(ring, 0);
 492         intel_ring_advance(ring);
 493
 494         *result = seqno;
 495         return 0;
 496 }
 497
 498 static int
 499 render_ring_add_request(struct intel_ring_buffer *ring,
 500                         u32 *result)
 501 {
 502         struct drm_device *dev = ring->dev;
 503         u32 seqno = i915_gem_get_seqno(dev);
 504         int ret;
 505
 506         ret = intel_ring_begin(ring, 4);
 507         if (ret)
 508                 return ret;
 509
 510         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 511         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 512         intel_ring_emit(ring, seqno);
 513         intel_ring_emit(ring, MI_USER_INTERRUPT);
 514         intel_ring_advance(ring);
 515
 516         *result = seqno;
 517         return 0;
 518 }
 519
 520 static u32
 521 ring_get_seqno(struct intel_ring_buffer *ring)
 522 {
 523         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 524 }
 525
 526 static u32
 527 pc_render_get_seqno(struct intel_ring_buffer *ring)
 528 {
 529         struct pipe_control *pc = ring->private;
 530         return pc->cpu_page[0];
 531 }
 532
 533 static void
 534 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 535 {
 536         dev_priv->gt_irq_mask &= ~mask;
 537         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 538         POSTING_READ(GTIMR);
 539 }
 540
 541 static void
 542 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 543 {
 544         dev_priv->gt_irq_mask |= mask;
 545         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 546         POSTING_READ(GTIMR);
 547 }
 548
 549 static void
 550 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 551 {
 552         dev_priv->irq_mask &= ~mask;
 553         I915_WRITE(IMR, dev_priv->irq_mask);
 554         POSTING_READ(IMR);
 555 }
 556
 557 static void
 558 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 559 {
 560         dev_priv->irq_mask |= mask;
 561         I915_WRITE(IMR, dev_priv->irq_mask);
 562         POSTING_READ(IMR);
 563 }
 564
 565 static bool
 566 render_ring_get_irq(struct intel_ring_buffer *ring)
 567 {
 568         struct drm_device *dev = ring->dev;
 569         drm_i915_private_t *dev_priv = dev->dev_private;
 570
 571         if (!dev->irq_enabled)
 572                 return false;
 573
 574         spin_lock(&ring->irq_lock);
 575         if (ring->irq_refcount++ == 0) {
 576                 if (HAS_PCH_SPLIT(dev))
 577                         ironlake_enable_irq(dev_priv,
 578                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 579                 else
 580                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 581         }
 582         spin_unlock(&ring->irq_lock);
 583
 584         return true;
 585 }
 586
 587 static void
 588 render_ring_put_irq(struct intel_ring_buffer *ring)
 589 {
 590         struct drm_device *dev = ring->dev;
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592
 593         spin_lock(&ring->irq_lock);
 594         if (--ring->irq_refcount == 0) {
 595                 if (HAS_PCH_SPLIT(dev))
 596                         ironlake_disable_irq(dev_priv,
 597                                              GT_USER_INTERRUPT |
 598                                              GT_PIPE_NOTIFY);
 599                 else
 600                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 601         }
 602         spin_unlock(&ring->irq_lock);
 603 }
 604
 605 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 606 {
 607         struct drm_device *dev = ring->dev;
 608         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 609         u32 mmio = 0;
 610
 611         /* The ring status page addresses are no longer next to the rest of
 612          * the ring registers as of gen7.
 613          */
 614         if (IS_GEN7(dev)) {
 615                 switch (ring->id) {
 616                 case RING_RENDER:
 617                         mmio = RENDER_HWS_PGA_GEN7;
 618                         break;
 619                 case RING_BLT:
 620                         mmio = BLT_HWS_PGA_GEN7;
 621                         break;
 622                 case RING_BSD:
 623                         mmio = BSD_HWS_PGA_GEN7;
 624                         break;
 625                 }
 626         } else if (IS_GEN6(ring->dev)) {
 627                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 628         } else {
 629                 mmio = RING_HWS_PGA(ring->mmio_base);
 630         }
 631
 632         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 633         POSTING_READ(mmio);
 634 }
 635
 636 static int
 637 bsd_ring_flush(struct intel_ring_buffer *ring,
 638                u32     invalidate_domains,
 639                u32     flush_domains)
 640 {
 641         int ret;
 642
 643         ret = intel_ring_begin(ring, 2);
 644         if (ret)
 645                 return ret;
 646
 647         intel_ring_emit(ring, MI_FLUSH);
 648         intel_ring_emit(ring, MI_NOOP);
 649         intel_ring_advance(ring);
 650         return 0;
 651 }
 652
 653 static int
 654 ring_add_request(struct intel_ring_buffer *ring,
 655                  u32 *result)
 656 {
 657         u32 seqno;
 658         int ret;
 659
 660         ret = intel_ring_begin(ring, 4);
 661         if (ret)
 662                 return ret;
 663
 664         seqno = i915_gem_get_seqno(ring->dev);
 665
 666         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 667         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 668         intel_ring_emit(ring, seqno);
 669         intel_ring_emit(ring, MI_USER_INTERRUPT);
 670         intel_ring_advance(ring);
 671
 672         *result = seqno;
 673         return 0;
 674 }
 675
 676 static bool
 677 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 678 {
 679         struct drm_device *dev = ring->dev;
 680         drm_i915_private_t *dev_priv = dev->dev_private;
 681
 682         if (!dev->irq_enabled)
 683                return false;
 684
 685         spin_lock(&ring->irq_lock);
 686         if (ring->irq_refcount++ == 0) {
 687                 ring->irq_mask &= ~rflag;
 688                 I915_WRITE_IMR(ring, ring->irq_mask);
 689                 ironlake_enable_irq(dev_priv, gflag);
 690         }
 691         spin_unlock(&ring->irq_lock);
 692
 693         return true;
 694 }
 695
 696 static void
 697 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 698 {
 699         struct drm_device *dev = ring->dev;
 700         drm_i915_private_t *dev_priv = dev->dev_private;
 701
 702         spin_lock(&ring->irq_lock);
 703         if (--ring->irq_refcount == 0) {
 704                 ring->irq_mask |= rflag;
 705                 I915_WRITE_IMR(ring, ring->irq_mask);
 706                 ironlake_disable_irq(dev_priv, gflag);
 707         }
 708         spin_unlock(&ring->irq_lock);
 709 }
 710
 711 static bool
 712 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 713 {
 714         struct drm_device *dev = ring->dev;
 715         drm_i915_private_t *dev_priv = dev->dev_private;
 716
 717         if (!dev->irq_enabled)
 718                 return false;
 719
 720         spin_lock(&ring->irq_lock);
 721         if (ring->irq_refcount++ == 0) {
 722                 if (IS_G4X(dev))
 723                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 724                 else
 725                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 726         }
 727         spin_unlock(&ring->irq_lock);
 728
 729         return true;
 730 }
 731 static void
 732 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 733 {
 734         struct drm_device *dev = ring->dev;
 735         drm_i915_private_t *dev_priv = dev->dev_private;
 736
 737         spin_lock(&ring->irq_lock);
 738         if (--ring->irq_refcount == 0) {
 739                 if (IS_G4X(dev))
 740                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 741                 else
 742                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 743         }
 744         spin_unlock(&ring->irq_lock);
 745 }
 746
 747 static int
 748 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 749 {
 750         int ret;
 751
 752         ret = intel_ring_begin(ring, 2);
 753         if (ret)
 754                 return ret;
 755
 756         intel_ring_emit(ring,
 757                         MI_BATCH_BUFFER_START | (2 << 6) |
 758                         MI_BATCH_NON_SECURE_I965);
 759         intel_ring_emit(ring, offset);
 760         intel_ring_advance(ring);
 761
 762         return 0;
 763 }
 764
 765 static int
 766 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 767                                 u32 offset, u32 len)
 768 {
 769         struct drm_device *dev = ring->dev;
 770         int ret;
 771
 772         if (IS_I830(dev) || IS_845G(dev)) {
 773                 ret = intel_ring_begin(ring, 4);
 774                 if (ret)
 775                         return ret;
 776
 777                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 778                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 779                 intel_ring_emit(ring, offset + len - 8);
 780                 intel_ring_emit(ring, 0);
 781         } else {
 782                 ret = intel_ring_begin(ring, 2);
 783                 if (ret)
 784                         return ret;
 785
 786                 if (INTEL_INFO(dev)->gen >= 4) {
 787                         intel_ring_emit(ring,
 788                                         MI_BATCH_BUFFER_START | (2 << 6) |
 789                                         MI_BATCH_NON_SECURE_I965);
 790                         intel_ring_emit(ring, offset);
 791                 } else {
 792                         intel_ring_emit(ring,
 793                                         MI_BATCH_BUFFER_START | (2 << 6));
 794                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 795                 }
 796         }
 797         intel_ring_advance(ring);
 798
 799         return 0;
 800 }
 801
 802 static void cleanup_status_page(struct intel_ring_buffer *ring)
 803 {
 804         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 805         struct drm_i915_gem_object *obj;
 806
 807         obj = ring->status_page.obj;
 808         if (obj == NULL)
 809                 return;
 810
 811         kunmap(obj->pages[0]);
 812         i915_gem_object_unpin(obj);
 813         drm_gem_object_unreference(&obj->base);
 814         ring->status_page.obj = NULL;
 815
 816         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 817 }
 818
 819 static int init_status_page(struct intel_ring_buffer *ring)
 820 {
 821         struct drm_device *dev = ring->dev;
 822         drm_i915_private_t *dev_priv = dev->dev_private;
 823         struct drm_i915_gem_object *obj;
 824         int ret;
 825
 826         obj = i915_gem_alloc_object(dev, 4096);
 827         if (obj == NULL) {
 828                 DRM_ERROR("Failed to allocate status page\n");
 829                 ret = -ENOMEM;
 830                 goto err;
 831         }
 832
 833         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 834
 835         ret = i915_gem_object_pin(obj, 4096, true);
 836         if (ret != 0) {
 837                 goto err_unref;
 838         }
 839
 840         ring->status_page.gfx_addr = obj->gtt_offset;
 841         ring->status_page.page_addr = kmap(obj->pages[0]);
 842         if (ring->status_page.page_addr == NULL) {
 843                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 844                 goto err_unpin;
 845         }
 846         ring->status_page.obj = obj;
 847         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 848
 849         intel_ring_setup_status_page(ring);
 850         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 851                         ring->name, ring->status_page.gfx_addr);
 852
 853         return 0;
 854
 855 err_unpin:
 856         i915_gem_object_unpin(obj);
 857 err_unref:
 858         drm_gem_object_unreference(&obj->base);
 859 err:
 860         return ret;
 861 }
 862
 863 int intel_init_ring_buffer(struct drm_device *dev,
 864                            struct intel_ring_buffer *ring)
 865 {
 866         struct drm_i915_gem_object *obj;
 867         int ret;
 868
 869         ring->dev = dev;
 870         INIT_LIST_HEAD(&ring->active_list);
 871         INIT_LIST_HEAD(&ring->request_list);
 872         INIT_LIST_HEAD(&ring->gpu_write_list);
 873
 874         init_waitqueue_head(&ring->irq_queue);
 875         spin_lock_init(&ring->irq_lock);
 876         ring->irq_mask = ~0;
 877
 878         if (I915_NEED_GFX_HWS(dev)) {
 879                 ret = init_status_page(ring);
 880                 if (ret)
 881                         return ret;
 882         }
 883
 884         obj = i915_gem_alloc_object(dev, ring->size);
 885         if (obj == NULL) {
 886                 DRM_ERROR("Failed to allocate ringbuffer\n");
 887                 ret = -ENOMEM;
 888                 goto err_hws;
 889         }
 890
 891         ring->obj = obj;
 892
 893         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 894         if (ret)
 895                 goto err_unref;
 896
 897         ring->map.size = ring->size;
 898         ring->map.offset = dev->agp->base + obj->gtt_offset;
 899         ring->map.type = 0;
 900         ring->map.flags = 0;
 901         ring->map.mtrr = 0;
 902
 903         drm_core_ioremap_wc(&ring->map, dev);
 904         if (ring->map.handle == NULL) {
 905                 DRM_ERROR("Failed to map ringbuffer.\n");
 906                 ret = -EINVAL;
 907                 goto err_unpin;
 908         }
 909
 910         ring->virtual_start = ring->map.handle;
 911         ret = ring->init(ring);
 912         if (ret)
 913                 goto err_unmap;
 914
 915         /* Workaround an erratum on the i830 which causes a hang if
 916          * the TAIL pointer points to within the last 2 cachelines
 917          * of the buffer.
 918          */
 919         ring->effective_size = ring->size;
 920         if (IS_I830(ring->dev))
 921                 ring->effective_size -= 128;
 922
 923         return 0;
 924
 925 err_unmap:
 926         drm_core_ioremapfree(&ring->map, dev);
 927 err_unpin:
 928         i915_gem_object_unpin(obj);
 929 err_unref:
 930         drm_gem_object_unreference(&obj->base);
 931         ring->obj = NULL;
 932 err_hws:
 933         cleanup_status_page(ring);
 934         return ret;
 935 }
 936
 937 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
 938 {
 939         struct drm_i915_private *dev_priv;
 940         int ret;
 941
 942         if (ring->obj == NULL)
 943                 return;
 944
 945         /* Disable the ring buffer. The ring must be idle at this point */
 946         dev_priv = ring->dev->dev_private;
 947         ret = intel_wait_ring_idle(ring);
 948         if (ret)
 949                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 950                           ring->name, ret);
 951
 952         I915_WRITE_CTL(ring, 0);
 953
 954         drm_core_ioremapfree(&ring->map, ring->dev);
 955
 956         i915_gem_object_unpin(ring->obj);
 957         drm_gem_object_unreference(&ring->obj->base);
 958         ring->obj = NULL;
 959
 960         if (ring->cleanup)
 961                 ring->cleanup(ring);
 962
 963         cleanup_status_page(ring);
 964 }
 965
 966 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
 967 {
 968         unsigned int *virt;
 969         int rem = ring->size - ring->tail;
 970
 971         if (ring->space < rem) {
 972                 int ret = intel_wait_ring_buffer(ring, rem);
 973                 if (ret)
 974                         return ret;
 975         }
 976
 977         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 978         rem /= 8;
 979         while (rem--) {
 980                 *virt++ = MI_NOOP;
 981                 *virt++ = MI_NOOP;
 982         }
 983
 984         ring->tail = 0;
 985         ring->space = ring_space(ring);
 986
 987         return 0;
 988 }
 989
 990 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
 991 {
 992         struct drm_device *dev = ring->dev;
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         unsigned long end;
 995         u32 head;
 996
 997         /* If the reported head position has wrapped or hasn't advanced,
 998          * fallback to the slow and accurate path.
 999          */
1000         head = intel_read_status_page(ring, 4);
1001         if (head > ring->head) {
1002                 ring->head = head;
1003                 ring->space = ring_space(ring);
1004                 if (ring->space >= n)
1005                         return 0;
1006         }
1007
1008         trace_i915_ring_wait_begin(ring);
1009         end = jiffies + 3 * HZ;
1010         do {
1011                 ring->head = I915_READ_HEAD(ring);
1012                 ring->space = ring_space(ring);
1013                 if (ring->space >= n) {
1014                         trace_i915_ring_wait_end(ring);
1015                         return 0;
1016                 }
1017
1018                 if (dev->primary->master) {
1019                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1020                         if (master_priv->sarea_priv)
1021                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1022                 }
1023
1024                 msleep(1);
1025                 if (atomic_read(&dev_priv->mm.wedged))
1026                         return -EAGAIN;
1027         } while (!time_after(jiffies, end));
1028         trace_i915_ring_wait_end(ring);
1029         return -EBUSY;
1030 }
1031
1032 int intel_ring_begin(struct intel_ring_buffer *ring,
1033                      int num_dwords)
1034 {
1035         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1036         int n = 4*num_dwords;
1037         int ret;
1038
1039         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1040                 return -EIO;
1041
1042         if (unlikely(ring->tail + n > ring->effective_size)) {
1043                 ret = intel_wrap_ring_buffer(ring);
1044                 if (unlikely(ret))
1045                         return ret;
1046         }
1047
1048         if (unlikely(ring->space < n)) {
1049                 ret = intel_wait_ring_buffer(ring, n);
1050                 if (unlikely(ret))
1051                         return ret;
1052         }
1053
1054         ring->space -= n;
1055         return 0;
1056 }
1057
1058 void intel_ring_advance(struct intel_ring_buffer *ring)
1059 {
1060         ring->tail &= ring->size - 1;
1061         ring->write_tail(ring, ring->tail);
1062 }
1063
1064 static const struct intel_ring_buffer render_ring = {
1065         .name                   = "render ring",
1066         .id                     = RING_RENDER,
1067         .mmio_base              = RENDER_RING_BASE,
1068         .size                   = 32 * PAGE_SIZE,
1069         .init                   = init_render_ring,
1070         .write_tail             = ring_write_tail,
1071         .flush                  = render_ring_flush,
1072         .add_request            = render_ring_add_request,
1073         .get_seqno              = ring_get_seqno,
1074         .irq_get                = render_ring_get_irq,
1075         .irq_put                = render_ring_put_irq,
1076         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1077         .cleanup                = render_ring_cleanup,
1078         .sync_to                = render_ring_sync_to,
1079         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1080                                    MI_SEMAPHORE_SYNC_RV,
1081                                    MI_SEMAPHORE_SYNC_RB},
1082         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1083 };
1084
1085 /* ring buffer for bit-stream decoder */
1086
1087 static const struct intel_ring_buffer bsd_ring = {
1088         .name                   = "bsd ring",
1089         .id                     = RING_BSD,
1090         .mmio_base              = BSD_RING_BASE,
1091         .size                   = 32 * PAGE_SIZE,
1092         .init                   = init_ring_common,
1093         .write_tail             = ring_write_tail,
1094         .flush                  = bsd_ring_flush,
1095         .add_request            = ring_add_request,
1096         .get_seqno              = ring_get_seqno,
1097         .irq_get                = bsd_ring_get_irq,
1098         .irq_put                = bsd_ring_put_irq,
1099         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1100 };
1101
1102
1103 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1104                                      u32 value)
1105 {
1106         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1107
1108        /* Every tail move must follow the sequence below */
1109         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1110                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1111                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1112         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1113
1114         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1115                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1116                 50))
1117         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1118
1119         I915_WRITE_TAIL(ring, value);
1120         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1121                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1122                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1123 }
1124
1125 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1126                            u32 invalidate, u32 flush)
1127 {
1128         uint32_t cmd;
1129         int ret;
1130
1131         ret = intel_ring_begin(ring, 4);
1132         if (ret)
1133                 return ret;
1134
1135         cmd = MI_FLUSH_DW;
1136         if (invalidate & I915_GEM_GPU_DOMAINS)
1137                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1138         intel_ring_emit(ring, cmd);
1139         intel_ring_emit(ring, 0);
1140         intel_ring_emit(ring, 0);
1141         intel_ring_emit(ring, MI_NOOP);
1142         intel_ring_advance(ring);
1143         return 0;
1144 }
1145
1146 static int
1147 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1148                               u32 offset, u32 len)
1149 {
1150         int ret;
1151
1152         ret = intel_ring_begin(ring, 2);
1153         if (ret)
1154                 return ret;
1155
1156         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1157         /* bit0-7 is the length on GEN6+ */
1158         intel_ring_emit(ring, offset);
1159         intel_ring_advance(ring);
1160
1161         return 0;
1162 }
1163
1164 static bool
1165 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1166 {
1167         return gen6_ring_get_irq(ring,
1168                                  GT_USER_INTERRUPT,
1169                                  GEN6_RENDER_USER_INTERRUPT);
1170 }
1171
1172 static void
1173 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1174 {
1175         return gen6_ring_put_irq(ring,
1176                                  GT_USER_INTERRUPT,
1177                                  GEN6_RENDER_USER_INTERRUPT);
1178 }
1179
1180 static bool
1181 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1182 {
1183         return gen6_ring_get_irq(ring,
1184                                  GT_GEN6_BSD_USER_INTERRUPT,
1185                                  GEN6_BSD_USER_INTERRUPT);
1186 }
1187
1188 static void
1189 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1190 {
1191         return gen6_ring_put_irq(ring,
1192                                  GT_GEN6_BSD_USER_INTERRUPT,
1193                                  GEN6_BSD_USER_INTERRUPT);
1194 }
1195
1196 /* ring buffer for Video Codec for Gen6+ */
1197 static const struct intel_ring_buffer gen6_bsd_ring = {
1198         .name                   = "gen6 bsd ring",
1199         .id                     = RING_BSD,
1200         .mmio_base              = GEN6_BSD_RING_BASE,
1201         .size                   = 32 * PAGE_SIZE,
1202         .init                   = init_ring_common,
1203         .write_tail             = gen6_bsd_ring_write_tail,
1204         .flush                  = gen6_ring_flush,
1205         .add_request            = gen6_add_request,
1206         .get_seqno              = ring_get_seqno,
1207         .irq_get                = gen6_bsd_ring_get_irq,
1208         .irq_put                = gen6_bsd_ring_put_irq,
1209         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1210         .sync_to                = gen6_bsd_ring_sync_to,
1211         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1212                                    MI_SEMAPHORE_SYNC_INVALID,
1213                                    MI_SEMAPHORE_SYNC_VB},
1214         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1215 };
1216
1217 /* Blitter support (SandyBridge+) */
1218
1219 static bool
1220 blt_ring_get_irq(struct intel_ring_buffer *ring)
1221 {
1222         return gen6_ring_get_irq(ring,
1223                                  GT_BLT_USER_INTERRUPT,
1224                                  GEN6_BLITTER_USER_INTERRUPT);
1225 }
1226
1227 static void
1228 blt_ring_put_irq(struct intel_ring_buffer *ring)
1229 {
1230         gen6_ring_put_irq(ring,
1231                           GT_BLT_USER_INTERRUPT,
1232                           GEN6_BLITTER_USER_INTERRUPT);
1233 }
1234
1235
1236 /* Workaround for some stepping of SNB,
1237  * each time when BLT engine ring tail moved,
1238  * the first command in the ring to be parsed
1239  * should be MI_BATCH_BUFFER_START
1240  */
1241 #define NEED_BLT_WORKAROUND(dev) \
1242         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1243
1244 static inline struct drm_i915_gem_object *
1245 to_blt_workaround(struct intel_ring_buffer *ring)
1246 {
1247         return ring->private;
1248 }
1249
1250 static int blt_ring_init(struct intel_ring_buffer *ring)
1251 {
1252         if (NEED_BLT_WORKAROUND(ring->dev)) {
1253                 struct drm_i915_gem_object *obj;
1254                 u32 *ptr;
1255                 int ret;
1256
1257                 obj = i915_gem_alloc_object(ring->dev, 4096);
1258                 if (obj == NULL)
1259                         return -ENOMEM;
1260
1261                 ret = i915_gem_object_pin(obj, 4096, true);
1262                 if (ret) {
1263                         drm_gem_object_unreference(&obj->base);
1264                         return ret;
1265                 }
1266
1267                 ptr = kmap(obj->pages[0]);
1268                 *ptr++ = MI_BATCH_BUFFER_END;
1269                 *ptr++ = MI_NOOP;
1270                 kunmap(obj->pages[0]);
1271
1272                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1273                 if (ret) {
1274                         i915_gem_object_unpin(obj);
1275                         drm_gem_object_unreference(&obj->base);
1276                         return ret;
1277                 }
1278
1279                 ring->private = obj;
1280         }
1281
1282         return init_ring_common(ring);
1283 }
1284
1285 static int blt_ring_begin(struct intel_ring_buffer *ring,
1286                           int num_dwords)
1287 {
1288         if (ring->private) {
1289                 int ret = intel_ring_begin(ring, num_dwords+2);
1290                 if (ret)
1291                         return ret;
1292
1293                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1294                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1295
1296                 return 0;
1297         } else
1298                 return intel_ring_begin(ring, 4);
1299 }
1300
1301 static int blt_ring_flush(struct intel_ring_buffer *ring,
1302                           u32 invalidate, u32 flush)
1303 {
1304         uint32_t cmd;
1305         int ret;
1306
1307         ret = blt_ring_begin(ring, 4);
1308         if (ret)
1309                 return ret;
1310
1311         cmd = MI_FLUSH_DW;
1312         if (invalidate & I915_GEM_DOMAIN_RENDER)
1313                 cmd |= MI_INVALIDATE_TLB;
1314         intel_ring_emit(ring, cmd);
1315         intel_ring_emit(ring, 0);
1316         intel_ring_emit(ring, 0);
1317         intel_ring_emit(ring, MI_NOOP);
1318         intel_ring_advance(ring);
1319         return 0;
1320 }
1321
1322 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1323 {
1324         if (!ring->private)
1325                 return;
1326
1327         i915_gem_object_unpin(ring->private);
1328         drm_gem_object_unreference(ring->private);
1329         ring->private = NULL;
1330 }
1331
1332 static const struct intel_ring_buffer gen6_blt_ring = {
1333         .name                   = "blt ring",
1334         .id                     = RING_BLT,
1335         .mmio_base              = BLT_RING_BASE,
1336         .size                   = 32 * PAGE_SIZE,
1337         .init                   = blt_ring_init,
1338         .write_tail             = ring_write_tail,
1339         .flush                  = blt_ring_flush,
1340         .add_request            = gen6_add_request,
1341         .get_seqno              = ring_get_seqno,
1342         .irq_get                = blt_ring_get_irq,
1343         .irq_put                = blt_ring_put_irq,
1344         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1345         .cleanup                = blt_ring_cleanup,
1346         .sync_to                = gen6_blt_ring_sync_to,
1347         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1348                                    MI_SEMAPHORE_SYNC_BV,
1349                                    MI_SEMAPHORE_SYNC_INVALID},
1350         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1351 };
1352
1353 int intel_init_render_ring_buffer(struct drm_device *dev)
1354 {
1355         drm_i915_private_t *dev_priv = dev->dev_private;
1356         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1357
1358         *ring = render_ring;
1359         if (INTEL_INFO(dev)->gen >= 6) {
1360                 ring->add_request = gen6_add_request;
1361                 ring->irq_get = gen6_render_ring_get_irq;
1362                 ring->irq_put = gen6_render_ring_put_irq;
1363         } else if (IS_GEN5(dev)) {
1364                 ring->add_request = pc_render_add_request;
1365                 ring->get_seqno = pc_render_get_seqno;
1366         }
1367
1368         if (!I915_NEED_GFX_HWS(dev)) {
1369                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1370                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1371         }
1372
1373         return intel_init_ring_buffer(dev, ring);
1374 }
1375
1376 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1377 {
1378         drm_i915_private_t *dev_priv = dev->dev_private;
1379         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1380
1381         *ring = render_ring;
1382         if (INTEL_INFO(dev)->gen >= 6) {
1383                 ring->add_request = gen6_add_request;
1384                 ring->irq_get = gen6_render_ring_get_irq;
1385                 ring->irq_put = gen6_render_ring_put_irq;
1386         } else if (IS_GEN5(dev)) {
1387                 ring->add_request = pc_render_add_request;
1388                 ring->get_seqno = pc_render_get_seqno;
1389         }
1390
1391         if (!I915_NEED_GFX_HWS(dev))
1392                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1393
1394         ring->dev = dev;
1395         INIT_LIST_HEAD(&ring->active_list);
1396         INIT_LIST_HEAD(&ring->request_list);
1397         INIT_LIST_HEAD(&ring->gpu_write_list);
1398
1399         ring->size = size;
1400         ring->effective_size = ring->size;
1401         if (IS_I830(ring->dev))
1402                 ring->effective_size -= 128;
1403
1404         ring->map.offset = start;
1405         ring->map.size = size;
1406         ring->map.type = 0;
1407         ring->map.flags = 0;
1408         ring->map.mtrr = 0;
1409
1410         drm_core_ioremap_wc(&ring->map, dev);
1411         if (ring->map.handle == NULL) {
1412                 DRM_ERROR("can not ioremap virtual address for"
1413                           " ring buffer\n");
1414                 return -ENOMEM;
1415         }
1416
1417         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1418         return 0;
1419 }
1420
1421 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1422 {
1423         drm_i915_private_t *dev_priv = dev->dev_private;
1424         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1425
1426         if (IS_GEN6(dev) || IS_GEN7(dev))
1427                 *ring = gen6_bsd_ring;
1428         else
1429                 *ring = bsd_ring;
1430
1431         return intel_init_ring_buffer(dev, ring);
1432 }
1433
1434 int intel_init_blt_ring_buffer(struct drm_device *dev)
1435 {
1436         drm_i915_private_t *dev_priv = dev->dev_private;
1437         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1438
1439         *ring = gen6_blt_ring;
1440
1441         return intel_init_ring_buffer(dev, ring);
1442 }