drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static void i8xx_disable_fbc(struct drm_device *dev)
  48 {
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         u32 fbc_ctl;
  51
  52         /* Disable compression */
  53         fbc_ctl = I915_READ(FBC_CONTROL);
  54         if ((fbc_ctl & FBC_CTL_EN) == 0)
  55                 return;
  56
  57         fbc_ctl &= ~FBC_CTL_EN;
  58         I915_WRITE(FBC_CONTROL, fbc_ctl);
  59
  60         /* Wait for compressing bit to clear */
  61         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  62                 DRM_DEBUG_KMS("FBC idle timed out\n");
  63                 return;
  64         }
  65
  66         DRM_DEBUG_KMS("disabled FBC\n");
  67 }
  68
  69 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  70 {
  71         struct drm_device *dev = crtc->dev;
  72         struct drm_i915_private *dev_priv = dev->dev_private;
  73         struct drm_framebuffer *fb = crtc->fb;
  74         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  75         struct drm_i915_gem_object *obj = intel_fb->obj;
  76         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  77         int cfb_pitch;
  78         int plane, i;
  79         u32 fbc_ctl, fbc_ctl2;
  80
  81         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  82         if (fb->pitches[0] < cfb_pitch)
  83                 cfb_pitch = fb->pitches[0];
  84
  85         /* FBC_CTL wants 64B units */
  86         cfb_pitch = (cfb_pitch / 64) - 1;
  87         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  88
  89         /* Clear old tags */
  90         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  91                 I915_WRITE(FBC_TAG + (i * 4), 0);
  92
  93         /* Set it up... */
  94         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  95         fbc_ctl2 |= plane;
  96         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  97         I915_WRITE(FBC_FENCE_OFF, crtc->y);
  98
  99         /* enable it... */
 100         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 101         if (IS_I945GM(dev))
 102                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 103         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 104         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 105         fbc_ctl |= obj->fence_reg;
 106         I915_WRITE(FBC_CONTROL, fbc_ctl);
 107
 108         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 109                       cfb_pitch, crtc->y, intel_crtc->plane);
 110 }
 111
 112 static bool i8xx_fbc_enabled(struct drm_device *dev)
 113 {
 114         struct drm_i915_private *dev_priv = dev->dev_private;
 115
 116         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 117 }
 118
 119 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 120 {
 121         struct drm_device *dev = crtc->dev;
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         struct drm_framebuffer *fb = crtc->fb;
 124         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 125         struct drm_i915_gem_object *obj = intel_fb->obj;
 126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 127         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 128         unsigned long stall_watermark = 200;
 129         u32 dpfc_ctl;
 130
 131         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 132         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 133         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 134
 135         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 136                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 137                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 138         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 139
 140         /* enable it... */
 141         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 142
 143         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 144 }
 145
 146 static void g4x_disable_fbc(struct drm_device *dev)
 147 {
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         u32 dpfc_ctl;
 150
 151         /* Disable compression */
 152         dpfc_ctl = I915_READ(DPFC_CONTROL);
 153         if (dpfc_ctl & DPFC_CTL_EN) {
 154                 dpfc_ctl &= ~DPFC_CTL_EN;
 155                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 156
 157                 DRM_DEBUG_KMS("disabled FBC\n");
 158         }
 159 }
 160
 161 static bool g4x_fbc_enabled(struct drm_device *dev)
 162 {
 163         struct drm_i915_private *dev_priv = dev->dev_private;
 164
 165         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 166 }
 167
 168 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 169 {
 170         struct drm_i915_private *dev_priv = dev->dev_private;
 171         u32 blt_ecoskpd;
 172
 173         /* Make sure blitter notifies FBC of writes */
 174         gen6_gt_force_wake_get(dev_priv);
 175         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 176         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 177                 GEN6_BLITTER_LOCK_SHIFT;
 178         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 179         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 180         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 181         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 182                          GEN6_BLITTER_LOCK_SHIFT);
 183         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 184         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 185         gen6_gt_force_wake_put(dev_priv);
 186 }
 187
 188 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 189 {
 190         struct drm_device *dev = crtc->dev;
 191         struct drm_i915_private *dev_priv = dev->dev_private;
 192         struct drm_framebuffer *fb = crtc->fb;
 193         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 194         struct drm_i915_gem_object *obj = intel_fb->obj;
 195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 196         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 197         unsigned long stall_watermark = 200;
 198         u32 dpfc_ctl;
 199
 200         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 201         dpfc_ctl &= DPFC_RESERVED;
 202         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 203         /* Set persistent mode for front-buffer rendering, ala X. */
 204         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 205         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 206         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 207
 208         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 209                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 210                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 211         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 212         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 213         /* enable it... */
 214         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 215
 216         if (IS_GEN6(dev)) {
 217                 I915_WRITE(SNB_DPFC_CTL_SA,
 218                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 219                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 220                 sandybridge_blit_fbc_update(dev);
 221         }
 222
 223         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 224 }
 225
 226 static void ironlake_disable_fbc(struct drm_device *dev)
 227 {
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         u32 dpfc_ctl;
 230
 231         /* Disable compression */
 232         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 233         if (dpfc_ctl & DPFC_CTL_EN) {
 234                 dpfc_ctl &= ~DPFC_CTL_EN;
 235                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 236
 237                 DRM_DEBUG_KMS("disabled FBC\n");
 238         }
 239 }
 240
 241 static bool ironlake_fbc_enabled(struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244
 245         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 246 }
 247
 248 bool intel_fbc_enabled(struct drm_device *dev)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251
 252         if (!dev_priv->display.fbc_enabled)
 253                 return false;
 254
 255         return dev_priv->display.fbc_enabled(dev);
 256 }
 257
 258 static void intel_fbc_work_fn(struct work_struct *__work)
 259 {
 260         struct intel_fbc_work *work =
 261                 container_of(to_delayed_work(__work),
 262                              struct intel_fbc_work, work);
 263         struct drm_device *dev = work->crtc->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265
 266         mutex_lock(&dev->struct_mutex);
 267         if (work == dev_priv->fbc_work) {
 268                 /* Double check that we haven't switched fb without cancelling
 269                  * the prior work.
 270                  */
 271                 if (work->crtc->fb == work->fb) {
 272                         dev_priv->display.enable_fbc(work->crtc,
 273                                                      work->interval);
 274
 275                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 276                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 277                         dev_priv->cfb_y = work->crtc->y;
 278                 }
 279
 280                 dev_priv->fbc_work = NULL;
 281         }
 282         mutex_unlock(&dev->struct_mutex);
 283
 284         kfree(work);
 285 }
 286
 287 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 288 {
 289         if (dev_priv->fbc_work == NULL)
 290                 return;
 291
 292         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 293
 294         /* Synchronisation is provided by struct_mutex and checking of
 295          * dev_priv->fbc_work, so we can perform the cancellation
 296          * entirely asynchronously.
 297          */
 298         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 299                 /* tasklet was killed before being run, clean up */
 300                 kfree(dev_priv->fbc_work);
 301
 302         /* Mark the work as no longer wanted so that if it does
 303          * wake-up (because the work was already running and waiting
 304          * for our mutex), it will discover that is no longer
 305          * necessary to run.
 306          */
 307         dev_priv->fbc_work = NULL;
 308 }
 309
 310 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 311 {
 312         struct intel_fbc_work *work;
 313         struct drm_device *dev = crtc->dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315
 316         if (!dev_priv->display.enable_fbc)
 317                 return;
 318
 319         intel_cancel_fbc_work(dev_priv);
 320
 321         work = kzalloc(sizeof *work, GFP_KERNEL);
 322         if (work == NULL) {
 323                 dev_priv->display.enable_fbc(crtc, interval);
 324                 return;
 325         }
 326
 327         work->crtc = crtc;
 328         work->fb = crtc->fb;
 329         work->interval = interval;
 330         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 331
 332         dev_priv->fbc_work = work;
 333
 334         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 335
 336         /* Delay the actual enabling to let pageflipping cease and the
 337          * display to settle before starting the compression. Note that
 338          * this delay also serves a second purpose: it allows for a
 339          * vblank to pass after disabling the FBC before we attempt
 340          * to modify the control registers.
 341          *
 342          * A more complicated solution would involve tracking vblanks
 343          * following the termination of the page-flipping sequence
 344          * and indeed performing the enable as a co-routine and not
 345          * waiting synchronously upon the vblank.
 346          */
 347         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 348 }
 349
 350 void intel_disable_fbc(struct drm_device *dev)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353
 354         intel_cancel_fbc_work(dev_priv);
 355
 356         if (!dev_priv->display.disable_fbc)
 357                 return;
 358
 359         dev_priv->display.disable_fbc(dev);
 360         dev_priv->cfb_plane = -1;
 361 }
 362
 363 /**
 364  * intel_update_fbc - enable/disable FBC as needed
 365  * @dev: the drm_device
 366  *
 367  * Set up the framebuffer compression hardware at mode set time.  We
 368  * enable it if possible:
 369  *   - plane A only (on pre-965)
 370  *   - no pixel mulitply/line duplication
 371  *   - no alpha buffer discard
 372  *   - no dual wide
 373  *   - framebuffer <= 2048 in width, 1536 in height
 374  *
 375  * We can't assume that any compression will take place (worst case),
 376  * so the compressed buffer has to be the same size as the uncompressed
 377  * one.  It also must reside (along with the line length buffer) in
 378  * stolen memory.
 379  *
 380  * We need to enable/disable FBC on a global basis.
 381  */
 382 void intel_update_fbc(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         struct drm_crtc *crtc = NULL, *tmp_crtc;
 386         struct intel_crtc *intel_crtc;
 387         struct drm_framebuffer *fb;
 388         struct intel_framebuffer *intel_fb;
 389         struct drm_i915_gem_object *obj;
 390         int enable_fbc;
 391
 392         if (!i915_powersave)
 393                 return;
 394
 395         if (!I915_HAS_FBC(dev))
 396                 return;
 397
 398         /*
 399          * If FBC is already on, we just have to verify that we can
 400          * keep it that way...
 401          * Need to disable if:
 402          *   - more than one pipe is active
 403          *   - changing FBC params (stride, fence, mode)
 404          *   - new fb is too large to fit in compressed buffer
 405          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 406          */
 407         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 408                 if (to_intel_crtc(tmp_crtc)->active &&
 409                     !to_intel_crtc(tmp_crtc)->primary_disabled &&
 410                     tmp_crtc->fb) {
 411                         if (crtc) {
 412                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 413                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 414                                 goto out_disable;
 415                         }
 416                         crtc = tmp_crtc;
 417                 }
 418         }
 419
 420         if (!crtc || crtc->fb == NULL) {
 421                 DRM_DEBUG_KMS("no output, disabling\n");
 422                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 423                 goto out_disable;
 424         }
 425
 426         intel_crtc = to_intel_crtc(crtc);
 427         fb = crtc->fb;
 428         intel_fb = to_intel_framebuffer(fb);
 429         obj = intel_fb->obj;
 430
 431         enable_fbc = i915_enable_fbc;
 432         if (enable_fbc < 0) {
 433                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 434                 enable_fbc = 1;
 435                 if (INTEL_INFO(dev)->gen <= 6)
 436                         enable_fbc = 0;
 437         }
 438         if (!enable_fbc) {
 439                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 440                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 441                 goto out_disable;
 442         }
 443         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
 444                 DRM_DEBUG_KMS("framebuffer too large, disabling "
 445                               "compression\n");
 446                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 447                 goto out_disable;
 448         }
 449         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 450             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 451                 DRM_DEBUG_KMS("mode incompatible with compression, "
 452                               "disabling\n");
 453                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 454                 goto out_disable;
 455         }
 456         if ((crtc->mode.hdisplay > 2048) ||
 457             (crtc->mode.vdisplay > 1536)) {
 458                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 459                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 460                 goto out_disable;
 461         }
 462         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 463                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 464                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 465                 goto out_disable;
 466         }
 467
 468         /* The use of a CPU fence is mandatory in order to detect writes
 469          * by the CPU to the scanout and trigger updates to the FBC.
 470          */
 471         if (obj->tiling_mode != I915_TILING_X ||
 472             obj->fence_reg == I915_FENCE_REG_NONE) {
 473                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 474                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 475                 goto out_disable;
 476         }
 477
 478         /* If the kernel debugger is active, always disable compression */
 479         if (in_dbg_master())
 480                 goto out_disable;
 481
 482         /* If the scanout has not changed, don't modify the FBC settings.
 483          * Note that we make the fundamental assumption that the fb->obj
 484          * cannot be unpinned (and have its GTT offset and fence revoked)
 485          * without first being decoupled from the scanout and FBC disabled.
 486          */
 487         if (dev_priv->cfb_plane == intel_crtc->plane &&
 488             dev_priv->cfb_fb == fb->base.id &&
 489             dev_priv->cfb_y == crtc->y)
 490                 return;
 491
 492         if (intel_fbc_enabled(dev)) {
 493                 /* We update FBC along two paths, after changing fb/crtc
 494                  * configuration (modeswitching) and after page-flipping
 495                  * finishes. For the latter, we know that not only did
 496                  * we disable the FBC at the start of the page-flip
 497                  * sequence, but also more than one vblank has passed.
 498                  *
 499                  * For the former case of modeswitching, it is possible
 500                  * to switch between two FBC valid configurations
 501                  * instantaneously so we do need to disable the FBC
 502                  * before we can modify its control registers. We also
 503                  * have to wait for the next vblank for that to take
 504                  * effect. However, since we delay enabling FBC we can
 505                  * assume that a vblank has passed since disabling and
 506                  * that we can safely alter the registers in the deferred
 507                  * callback.
 508                  *
 509                  * In the scenario that we go from a valid to invalid
 510                  * and then back to valid FBC configuration we have
 511                  * no strict enforcement that a vblank occurred since
 512                  * disabling the FBC. However, along all current pipe
 513                  * disabling paths we do need to wait for a vblank at
 514                  * some point. And we wait before enabling FBC anyway.
 515                  */
 516                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 517                 intel_disable_fbc(dev);
 518         }
 519
 520         intel_enable_fbc(crtc, 500);
 521         return;
 522
 523 out_disable:
 524         /* Multiple disables should be harmless */
 525         if (intel_fbc_enabled(dev)) {
 526                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 527                 intel_disable_fbc(dev);
 528         }
 529 }
 530
 531 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 532 {
 533         drm_i915_private_t *dev_priv = dev->dev_private;
 534         u32 tmp;
 535
 536         tmp = I915_READ(CLKCFG);
 537
 538         switch (tmp & CLKCFG_FSB_MASK) {
 539         case CLKCFG_FSB_533:
 540                 dev_priv->fsb_freq = 533; /* 133*4 */
 541                 break;
 542         case CLKCFG_FSB_800:
 543                 dev_priv->fsb_freq = 800; /* 200*4 */
 544                 break;
 545         case CLKCFG_FSB_667:
 546                 dev_priv->fsb_freq =  667; /* 167*4 */
 547                 break;
 548         case CLKCFG_FSB_400:
 549                 dev_priv->fsb_freq = 400; /* 100*4 */
 550                 break;
 551         }
 552
 553         switch (tmp & CLKCFG_MEM_MASK) {
 554         case CLKCFG_MEM_533:
 555                 dev_priv->mem_freq = 533;
 556                 break;
 557         case CLKCFG_MEM_667:
 558                 dev_priv->mem_freq = 667;
 559                 break;
 560         case CLKCFG_MEM_800:
 561                 dev_priv->mem_freq = 800;
 562                 break;
 563         }
 564
 565         /* detect pineview DDR3 setting */
 566         tmp = I915_READ(CSHRDDR3CTL);
 567         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 568 }
 569
 570 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 571 {
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         u16 ddrpll, csipll;
 574
 575         ddrpll = I915_READ16(DDRMPLL1);
 576         csipll = I915_READ16(CSIPLL0);
 577
 578         switch (ddrpll & 0xff) {
 579         case 0xc:
 580                 dev_priv->mem_freq = 800;
 581                 break;
 582         case 0x10:
 583                 dev_priv->mem_freq = 1066;
 584                 break;
 585         case 0x14:
 586                 dev_priv->mem_freq = 1333;
 587                 break;
 588         case 0x18:
 589                 dev_priv->mem_freq = 1600;
 590                 break;
 591         default:
 592                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 593                                  ddrpll & 0xff);
 594                 dev_priv->mem_freq = 0;
 595                 break;
 596         }
 597
 598         dev_priv->ips.r_t = dev_priv->mem_freq;
 599
 600         switch (csipll & 0x3ff) {
 601         case 0x00c:
 602                 dev_priv->fsb_freq = 3200;
 603                 break;
 604         case 0x00e:
 605                 dev_priv->fsb_freq = 3733;
 606                 break;
 607         case 0x010:
 608                 dev_priv->fsb_freq = 4266;
 609                 break;
 610         case 0x012:
 611                 dev_priv->fsb_freq = 4800;
 612                 break;
 613         case 0x014:
 614                 dev_priv->fsb_freq = 5333;
 615                 break;
 616         case 0x016:
 617                 dev_priv->fsb_freq = 5866;
 618                 break;
 619         case 0x018:
 620                 dev_priv->fsb_freq = 6400;
 621                 break;
 622         default:
 623                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 624                                  csipll & 0x3ff);
 625                 dev_priv->fsb_freq = 0;
 626                 break;
 627         }
 628
 629         if (dev_priv->fsb_freq == 3200) {
 630                 dev_priv->ips.c_m = 0;
 631         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 632                 dev_priv->ips.c_m = 1;
 633         } else {
 634                 dev_priv->ips.c_m = 2;
 635         }
 636 }
 637
 638 static const struct cxsr_latency cxsr_latency_table[] = {
 639         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 640         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 641         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 642         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 643         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 644
 645         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 646         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 647         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 648         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 649         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 650
 651         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 652         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 653         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 654         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 655         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 656
 657         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 658         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 659         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 660         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 661         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 662
 663         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 664         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 665         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 666         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 667         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 668
 669         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 670         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 671         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 672         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 673         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 674 };
 675
 676 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 677                                                          int is_ddr3,
 678                                                          int fsb,
 679                                                          int mem)
 680 {
 681         const struct cxsr_latency *latency;
 682         int i;
 683
 684         if (fsb == 0 || mem == 0)
 685                 return NULL;
 686
 687         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 688                 latency = &cxsr_latency_table[i];
 689                 if (is_desktop == latency->is_desktop &&
 690                     is_ddr3 == latency->is_ddr3 &&
 691                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 692                         return latency;
 693         }
 694
 695         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 696
 697         return NULL;
 698 }
 699
 700 static void pineview_disable_cxsr(struct drm_device *dev)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703
 704         /* deactivate cxsr */
 705         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 706 }
 707
 708 /*
 709  * Latency for FIFO fetches is dependent on several factors:
 710  *   - memory configuration (speed, channels)
 711  *   - chipset
 712  *   - current MCH state
 713  * It can be fairly high in some situations, so here we assume a fairly
 714  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 715  * set this value too high, the FIFO will fetch frequently to stay full)
 716  * and power consumption (set it too low to save power and we might see
 717  * FIFO underruns and display "flicker").
 718  *
 719  * A value of 5us seems to be a good balance; safe for very low end
 720  * platforms but not overly aggressive on lower latency configs.
 721  */
 722 static const int latency_ns = 5000;
 723
 724 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         uint32_t dsparb = I915_READ(DSPARB);
 728         int size;
 729
 730         size = dsparb & 0x7f;
 731         if (plane)
 732                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 733
 734         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 735                       plane ? "B" : "A", size);
 736
 737         return size;
 738 }
 739
 740 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         uint32_t dsparb = I915_READ(DSPARB);
 744         int size;
 745
 746         size = dsparb & 0x1ff;
 747         if (plane)
 748                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 749         size >>= 1; /* Convert to cachelines */
 750
 751         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 752                       plane ? "B" : "A", size);
 753
 754         return size;
 755 }
 756
 757 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         uint32_t dsparb = I915_READ(DSPARB);
 761         int size;
 762
 763         size = dsparb & 0x7f;
 764         size >>= 2; /* Convert to cachelines */
 765
 766         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 767                       plane ? "B" : "A",
 768                       size);
 769
 770         return size;
 771 }
 772
 773 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 774 {
 775         struct drm_i915_private *dev_priv = dev->dev_private;
 776         uint32_t dsparb = I915_READ(DSPARB);
 777         int size;
 778
 779         size = dsparb & 0x7f;
 780         size >>= 1; /* Convert to cachelines */
 781
 782         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 783                       plane ? "B" : "A", size);
 784
 785         return size;
 786 }
 787
 788 /* Pineview has different values for various configs */
 789 static const struct intel_watermark_params pineview_display_wm = {
 790         PINEVIEW_DISPLAY_FIFO,
 791         PINEVIEW_MAX_WM,
 792         PINEVIEW_DFT_WM,
 793         PINEVIEW_GUARD_WM,
 794         PINEVIEW_FIFO_LINE_SIZE
 795 };
 796 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 797         PINEVIEW_DISPLAY_FIFO,
 798         PINEVIEW_MAX_WM,
 799         PINEVIEW_DFT_HPLLOFF_WM,
 800         PINEVIEW_GUARD_WM,
 801         PINEVIEW_FIFO_LINE_SIZE
 802 };
 803 static const struct intel_watermark_params pineview_cursor_wm = {
 804         PINEVIEW_CURSOR_FIFO,
 805         PINEVIEW_CURSOR_MAX_WM,
 806         PINEVIEW_CURSOR_DFT_WM,
 807         PINEVIEW_CURSOR_GUARD_WM,
 808         PINEVIEW_FIFO_LINE_SIZE,
 809 };
 810 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 811         PINEVIEW_CURSOR_FIFO,
 812         PINEVIEW_CURSOR_MAX_WM,
 813         PINEVIEW_CURSOR_DFT_WM,
 814         PINEVIEW_CURSOR_GUARD_WM,
 815         PINEVIEW_FIFO_LINE_SIZE
 816 };
 817 static const struct intel_watermark_params g4x_wm_info = {
 818         G4X_FIFO_SIZE,
 819         G4X_MAX_WM,
 820         G4X_MAX_WM,
 821         2,
 822         G4X_FIFO_LINE_SIZE,
 823 };
 824 static const struct intel_watermark_params g4x_cursor_wm_info = {
 825         I965_CURSOR_FIFO,
 826         I965_CURSOR_MAX_WM,
 827         I965_CURSOR_DFT_WM,
 828         2,
 829         G4X_FIFO_LINE_SIZE,
 830 };
 831 static const struct intel_watermark_params valleyview_wm_info = {
 832         VALLEYVIEW_FIFO_SIZE,
 833         VALLEYVIEW_MAX_WM,
 834         VALLEYVIEW_MAX_WM,
 835         2,
 836         G4X_FIFO_LINE_SIZE,
 837 };
 838 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 839         I965_CURSOR_FIFO,
 840         VALLEYVIEW_CURSOR_MAX_WM,
 841         I965_CURSOR_DFT_WM,
 842         2,
 843         G4X_FIFO_LINE_SIZE,
 844 };
 845 static const struct intel_watermark_params i965_cursor_wm_info = {
 846         I965_CURSOR_FIFO,
 847         I965_CURSOR_MAX_WM,
 848         I965_CURSOR_DFT_WM,
 849         2,
 850         I915_FIFO_LINE_SIZE,
 851 };
 852 static const struct intel_watermark_params i945_wm_info = {
 853         I945_FIFO_SIZE,
 854         I915_MAX_WM,
 855         1,
 856         2,
 857         I915_FIFO_LINE_SIZE
 858 };
 859 static const struct intel_watermark_params i915_wm_info = {
 860         I915_FIFO_SIZE,
 861         I915_MAX_WM,
 862         1,
 863         2,
 864         I915_FIFO_LINE_SIZE
 865 };
 866 static const struct intel_watermark_params i855_wm_info = {
 867         I855GM_FIFO_SIZE,
 868         I915_MAX_WM,
 869         1,
 870         2,
 871         I830_FIFO_LINE_SIZE
 872 };
 873 static const struct intel_watermark_params i830_wm_info = {
 874         I830_FIFO_SIZE,
 875         I915_MAX_WM,
 876         1,
 877         2,
 878         I830_FIFO_LINE_SIZE
 879 };
 880
 881 static const struct intel_watermark_params ironlake_display_wm_info = {
 882         ILK_DISPLAY_FIFO,
 883         ILK_DISPLAY_MAXWM,
 884         ILK_DISPLAY_DFTWM,
 885         2,
 886         ILK_FIFO_LINE_SIZE
 887 };
 888 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 889         ILK_CURSOR_FIFO,
 890         ILK_CURSOR_MAXWM,
 891         ILK_CURSOR_DFTWM,
 892         2,
 893         ILK_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params ironlake_display_srwm_info = {
 896         ILK_DISPLAY_SR_FIFO,
 897         ILK_DISPLAY_MAX_SRWM,
 898         ILK_DISPLAY_DFT_SRWM,
 899         2,
 900         ILK_FIFO_LINE_SIZE
 901 };
 902 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 903         ILK_CURSOR_SR_FIFO,
 904         ILK_CURSOR_MAX_SRWM,
 905         ILK_CURSOR_DFT_SRWM,
 906         2,
 907         ILK_FIFO_LINE_SIZE
 908 };
 909
 910 static const struct intel_watermark_params sandybridge_display_wm_info = {
 911         SNB_DISPLAY_FIFO,
 912         SNB_DISPLAY_MAXWM,
 913         SNB_DISPLAY_DFTWM,
 914         2,
 915         SNB_FIFO_LINE_SIZE
 916 };
 917 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 918         SNB_CURSOR_FIFO,
 919         SNB_CURSOR_MAXWM,
 920         SNB_CURSOR_DFTWM,
 921         2,
 922         SNB_FIFO_LINE_SIZE
 923 };
 924 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 925         SNB_DISPLAY_SR_FIFO,
 926         SNB_DISPLAY_MAX_SRWM,
 927         SNB_DISPLAY_DFT_SRWM,
 928         2,
 929         SNB_FIFO_LINE_SIZE
 930 };
 931 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 932         SNB_CURSOR_SR_FIFO,
 933         SNB_CURSOR_MAX_SRWM,
 934         SNB_CURSOR_DFT_SRWM,
 935         2,
 936         SNB_FIFO_LINE_SIZE
 937 };
 938
 939
 940 /**
 941  * intel_calculate_wm - calculate watermark level
 942  * @clock_in_khz: pixel clock
 943  * @wm: chip FIFO params
 944  * @pixel_size: display pixel size
 945  * @latency_ns: memory latency for the platform
 946  *
 947  * Calculate the watermark level (the level at which the display plane will
 948  * start fetching from memory again).  Each chip has a different display
 949  * FIFO size and allocation, so the caller needs to figure that out and pass
 950  * in the correct intel_watermark_params structure.
 951  *
 952  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 953  * on the pixel size.  When it reaches the watermark level, it'll start
 954  * fetching FIFO line sized based chunks from memory until the FIFO fills
 955  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 956  * will occur, and a display engine hang could result.
 957  */
 958 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 959                                         const struct intel_watermark_params *wm,
 960                                         int fifo_size,
 961                                         int pixel_size,
 962                                         unsigned long latency_ns)
 963 {
 964         long entries_required, wm_size;
 965
 966         /*
 967          * Note: we need to make sure we don't overflow for various clock &
 968          * latency values.
 969          * clocks go from a few thousand to several hundred thousand.
 970          * latency is usually a few thousand
 971          */
 972         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 973                 1000;
 974         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 975
 976         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 977
 978         wm_size = fifo_size - (entries_required + wm->guard_size);
 979
 980         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 981
 982         /* Don't promote wm_size to unsigned... */
 983         if (wm_size > (long)wm->max_wm)
 984                 wm_size = wm->max_wm;
 985         if (wm_size <= 0)
 986                 wm_size = wm->default_wm;
 987         return wm_size;
 988 }
 989
 990 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 991 {
 992         struct drm_crtc *crtc, *enabled = NULL;
 993
 994         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 995                 if (to_intel_crtc(crtc)->active && crtc->fb) {
 996                         if (enabled)
 997                                 return NULL;
 998                         enabled = crtc;
 999                 }
1000         }
1001
1002         return enabled;
1003 }
1004
1005 static void pineview_update_wm(struct drm_device *dev)
1006 {
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         struct drm_crtc *crtc;
1009         const struct cxsr_latency *latency;
1010         u32 reg;
1011         unsigned long wm;
1012
1013         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1015         if (!latency) {
1016                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017                 pineview_disable_cxsr(dev);
1018                 return;
1019         }
1020
1021         crtc = single_enabled_crtc(dev);
1022         if (crtc) {
1023                 int clock = crtc->mode.clock;
1024                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026                 /* Display SR */
1027                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028                                         pineview_display_wm.fifo_size,
1029                                         pixel_size, latency->display_sr);
1030                 reg = I915_READ(DSPFW1);
1031                 reg &= ~DSPFW_SR_MASK;
1032                 reg |= wm << DSPFW_SR_SHIFT;
1033                 I915_WRITE(DSPFW1, reg);
1034                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036                 /* cursor SR */
1037                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038                                         pineview_display_wm.fifo_size,
1039                                         pixel_size, latency->cursor_sr);
1040                 reg = I915_READ(DSPFW3);
1041                 reg &= ~DSPFW_CURSOR_SR_MASK;
1042                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043                 I915_WRITE(DSPFW3, reg);
1044
1045                 /* Display HPLL off SR */
1046                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047                                         pineview_display_hplloff_wm.fifo_size,
1048                                         pixel_size, latency->display_hpll_disable);
1049                 reg = I915_READ(DSPFW3);
1050                 reg &= ~DSPFW_HPLL_SR_MASK;
1051                 reg |= wm & DSPFW_HPLL_SR_MASK;
1052                 I915_WRITE(DSPFW3, reg);
1053
1054                 /* cursor HPLL off SR */
1055                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056                                         pineview_display_hplloff_wm.fifo_size,
1057                                         pixel_size, latency->cursor_hpll_disable);
1058                 reg = I915_READ(DSPFW3);
1059                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061                 I915_WRITE(DSPFW3, reg);
1062                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064                 /* activate cxsr */
1065                 I915_WRITE(DSPFW3,
1066                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068         } else {
1069                 pineview_disable_cxsr(dev);
1070                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071         }
1072 }
1073
1074 static bool g4x_compute_wm0(struct drm_device *dev,
1075                             int plane,
1076                             const struct intel_watermark_params *display,
1077                             int display_latency_ns,
1078                             const struct intel_watermark_params *cursor,
1079                             int cursor_latency_ns,
1080                             int *plane_wm,
1081                             int *cursor_wm)
1082 {
1083         struct drm_crtc *crtc;
1084         int htotal, hdisplay, clock, pixel_size;
1085         int line_time_us, line_count;
1086         int entries, tlb_miss;
1087
1088         crtc = intel_get_crtc_for_plane(dev, plane);
1089         if (crtc->fb == NULL || !to_intel_crtc(crtc)->active) {
1090                 *cursor_wm = cursor->guard_size;
1091                 *plane_wm = display->guard_size;
1092                 return false;
1093         }
1094
1095         htotal = crtc->mode.htotal;
1096         hdisplay = crtc->mode.hdisplay;
1097         clock = crtc->mode.clock;
1098         pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100         /* Use the small buffer method to calculate plane watermark */
1101         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103         if (tlb_miss > 0)
1104                 entries += tlb_miss;
1105         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106         *plane_wm = entries + display->guard_size;
1107         if (*plane_wm > (int)display->max_wm)
1108                 *plane_wm = display->max_wm;
1109
1110         /* Use the large buffer method to calculate cursor watermark */
1111         line_time_us = ((htotal * 1000) / clock);
1112         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113         entries = line_count * 64 * pixel_size;
1114         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115         if (tlb_miss > 0)
1116                 entries += tlb_miss;
1117         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118         *cursor_wm = entries + cursor->guard_size;
1119         if (*cursor_wm > (int)cursor->max_wm)
1120                 *cursor_wm = (int)cursor->max_wm;
1121
1122         return true;
1123 }
1124
1125 /*
1126  * Check the wm result.
1127  *
1128  * If any calculated watermark values is larger than the maximum value that
1129  * can be programmed into the associated watermark register, that watermark
1130  * must be disabled.
1131  */
1132 static bool g4x_check_srwm(struct drm_device *dev,
1133                            int display_wm, int cursor_wm,
1134                            const struct intel_watermark_params *display,
1135                            const struct intel_watermark_params *cursor)
1136 {
1137         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138                       display_wm, cursor_wm);
1139
1140         if (display_wm > display->max_wm) {
1141                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142                               display_wm, display->max_wm);
1143                 return false;
1144         }
1145
1146         if (cursor_wm > cursor->max_wm) {
1147                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148                               cursor_wm, cursor->max_wm);
1149                 return false;
1150         }
1151
1152         if (!(display_wm || cursor_wm)) {
1153                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154                 return false;
1155         }
1156
1157         return true;
1158 }
1159
1160 static bool g4x_compute_srwm(struct drm_device *dev,
1161                              int plane,
1162                              int latency_ns,
1163                              const struct intel_watermark_params *display,
1164                              const struct intel_watermark_params *cursor,
1165                              int *display_wm, int *cursor_wm)
1166 {
1167         struct drm_crtc *crtc;
1168         int hdisplay, htotal, pixel_size, clock;
1169         unsigned long line_time_us;
1170         int line_count, line_size;
1171         int small, large;
1172         int entries;
1173
1174         if (!latency_ns) {
1175                 *display_wm = *cursor_wm = 0;
1176                 return false;
1177         }
1178
1179         crtc = intel_get_crtc_for_plane(dev, plane);
1180         hdisplay = crtc->mode.hdisplay;
1181         htotal = crtc->mode.htotal;
1182         clock = crtc->mode.clock;
1183         pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185         line_time_us = (htotal * 1000) / clock;
1186         line_count = (latency_ns / line_time_us + 1000) / 1000;
1187         line_size = hdisplay * pixel_size;
1188
1189         /* Use the minimum of the small and large buffer method for primary */
1190         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191         large = line_count * line_size;
1192
1193         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194         *display_wm = entries + display->guard_size;
1195
1196         /* calculate the self-refresh watermark for display cursor */
1197         entries = line_count * pixel_size * 64;
1198         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199         *cursor_wm = entries + cursor->guard_size;
1200
1201         return g4x_check_srwm(dev,
1202                               *display_wm, *cursor_wm,
1203                               display, cursor);
1204 }
1205
1206 static bool vlv_compute_drain_latency(struct drm_device *dev,
1207                                      int plane,
1208                                      int *plane_prec_mult,
1209                                      int *plane_dl,
1210                                      int *cursor_prec_mult,
1211                                      int *cursor_dl)
1212 {
1213         struct drm_crtc *crtc;
1214         int clock, pixel_size;
1215         int entries;
1216
1217         crtc = intel_get_crtc_for_plane(dev, plane);
1218         if (crtc->fb == NULL || !to_intel_crtc(crtc)->active)
1219                 return false;
1220
1221         clock = crtc->mode.clock;       /* VESA DOT Clock */
1222         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1223
1224         entries = (clock / 1000) * pixel_size;
1225         *plane_prec_mult = (entries > 256) ?
1226                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228                                                      pixel_size);
1229
1230         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1231         *cursor_prec_mult = (entries > 256) ?
1232                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235         return true;
1236 }
1237
1238 /*
1239  * Update drain latency registers of memory arbiter
1240  *
1241  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242  * to be programmed. Each plane has a drain latency multiplier and a drain
1243  * latency value.
1244  */
1245
1246 static void vlv_update_drain_latency(struct drm_device *dev)
1247 {
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252                                                         either 16 or 32 */
1253
1254         /* For plane A, Cursor A */
1255         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256                                       &cursor_prec_mult, &cursora_dl)) {
1257                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262                 I915_WRITE(VLV_DDL1, cursora_prec |
1263                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1264                                 planea_prec | planea_dl);
1265         }
1266
1267         /* For plane B, Cursor B */
1268         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269                                       &cursor_prec_mult, &cursorb_dl)) {
1270                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275                 I915_WRITE(VLV_DDL2, cursorb_prec |
1276                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277                                 planeb_prec | planeb_dl);
1278         }
1279 }
1280
1281 #define single_plane_enabled(mask) is_power_of_2(mask)
1282
1283 static void valleyview_update_wm(struct drm_device *dev)
1284 {
1285         static const int sr_latency_ns = 12000;
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288         int plane_sr, cursor_sr;
1289         int ignore_plane_sr, ignore_cursor_sr;
1290         unsigned int enabled = 0;
1291
1292         vlv_update_drain_latency(dev);
1293
1294         if (g4x_compute_wm0(dev, 0,
1295                             &valleyview_wm_info, latency_ns,
1296                             &valleyview_cursor_wm_info, latency_ns,
1297                             &planea_wm, &cursora_wm))
1298                 enabled |= 1;
1299
1300         if (g4x_compute_wm0(dev, 1,
1301                             &valleyview_wm_info, latency_ns,
1302                             &valleyview_cursor_wm_info, latency_ns,
1303                             &planeb_wm, &cursorb_wm))
1304                 enabled |= 2;
1305
1306         if (single_plane_enabled(enabled) &&
1307             g4x_compute_srwm(dev, ffs(enabled) - 1,
1308                              sr_latency_ns,
1309                              &valleyview_wm_info,
1310                              &valleyview_cursor_wm_info,
1311                              &plane_sr, &ignore_cursor_sr) &&
1312             g4x_compute_srwm(dev, ffs(enabled) - 1,
1313                              2*sr_latency_ns,
1314                              &valleyview_wm_info,
1315                              &valleyview_cursor_wm_info,
1316                              &ignore_plane_sr, &cursor_sr)) {
1317                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1318         } else {
1319                 I915_WRITE(FW_BLC_SELF_VLV,
1320                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1321                 plane_sr = cursor_sr = 0;
1322         }
1323
1324         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1325                       planea_wm, cursora_wm,
1326                       planeb_wm, cursorb_wm,
1327                       plane_sr, cursor_sr);
1328
1329         I915_WRITE(DSPFW1,
1330                    (plane_sr << DSPFW_SR_SHIFT) |
1331                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1332                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1333                    planea_wm);
1334         I915_WRITE(DSPFW2,
1335                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1336                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1337         I915_WRITE(DSPFW3,
1338                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1339                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1340 }
1341
1342 static void g4x_update_wm(struct drm_device *dev)
1343 {
1344         static const int sr_latency_ns = 12000;
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1347         int plane_sr, cursor_sr;
1348         unsigned int enabled = 0;
1349
1350         if (g4x_compute_wm0(dev, 0,
1351                             &g4x_wm_info, latency_ns,
1352                             &g4x_cursor_wm_info, latency_ns,
1353                             &planea_wm, &cursora_wm))
1354                 enabled |= 1;
1355
1356         if (g4x_compute_wm0(dev, 1,
1357                             &g4x_wm_info, latency_ns,
1358                             &g4x_cursor_wm_info, latency_ns,
1359                             &planeb_wm, &cursorb_wm))
1360                 enabled |= 2;
1361
1362         if (single_plane_enabled(enabled) &&
1363             g4x_compute_srwm(dev, ffs(enabled) - 1,
1364                              sr_latency_ns,
1365                              &g4x_wm_info,
1366                              &g4x_cursor_wm_info,
1367                              &plane_sr, &cursor_sr)) {
1368                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1369         } else {
1370                 I915_WRITE(FW_BLC_SELF,
1371                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1372                 plane_sr = cursor_sr = 0;
1373         }
1374
1375         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1376                       planea_wm, cursora_wm,
1377                       planeb_wm, cursorb_wm,
1378                       plane_sr, cursor_sr);
1379
1380         I915_WRITE(DSPFW1,
1381                    (plane_sr << DSPFW_SR_SHIFT) |
1382                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1383                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1384                    planea_wm);
1385         I915_WRITE(DSPFW2,
1386                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1387                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1388         /* HPLL off in SR has some issues on G4x... disable it */
1389         I915_WRITE(DSPFW3,
1390                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1391                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1392 }
1393
1394 static void i965_update_wm(struct drm_device *dev)
1395 {
1396         struct drm_i915_private *dev_priv = dev->dev_private;
1397         struct drm_crtc *crtc;
1398         int srwm = 1;
1399         int cursor_sr = 16;
1400
1401         /* Calc sr entries for one plane configs */
1402         crtc = single_enabled_crtc(dev);
1403         if (crtc) {
1404                 /* self-refresh has much higher latency */
1405                 static const int sr_latency_ns = 12000;
1406                 int clock = crtc->mode.clock;
1407                 int htotal = crtc->mode.htotal;
1408                 int hdisplay = crtc->mode.hdisplay;
1409                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1410                 unsigned long line_time_us;
1411                 int entries;
1412
1413                 line_time_us = ((htotal * 1000) / clock);
1414
1415                 /* Use ns/us then divide to preserve precision */
1416                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1417                         pixel_size * hdisplay;
1418                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1419                 srwm = I965_FIFO_SIZE - entries;
1420                 if (srwm < 0)
1421                         srwm = 1;
1422                 srwm &= 0x1ff;
1423                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1424                               entries, srwm);
1425
1426                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1427                         pixel_size * 64;
1428                 entries = DIV_ROUND_UP(entries,
1429                                           i965_cursor_wm_info.cacheline_size);
1430                 cursor_sr = i965_cursor_wm_info.fifo_size -
1431                         (entries + i965_cursor_wm_info.guard_size);
1432
1433                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1434                         cursor_sr = i965_cursor_wm_info.max_wm;
1435
1436                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1437                               "cursor %d\n", srwm, cursor_sr);
1438
1439                 if (IS_CRESTLINE(dev))
1440                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1441         } else {
1442                 /* Turn off self refresh if both pipes are enabled */
1443                 if (IS_CRESTLINE(dev))
1444                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1445                                    & ~FW_BLC_SELF_EN);
1446         }
1447
1448         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1449                       srwm);
1450
1451         /* 965 has limitations... */
1452         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1453                    (8 << 16) | (8 << 8) | (8 << 0));
1454         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1455         /* update cursor SR watermark */
1456         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1457 }
1458
1459 static void i9xx_update_wm(struct drm_device *dev)
1460 {
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         const struct intel_watermark_params *wm_info;
1463         uint32_t fwater_lo;
1464         uint32_t fwater_hi;
1465         int cwm, srwm = 1;
1466         int fifo_size;
1467         int planea_wm, planeb_wm;
1468         struct drm_crtc *crtc, *enabled = NULL;
1469
1470         if (IS_I945GM(dev))
1471                 wm_info = &i945_wm_info;
1472         else if (!IS_GEN2(dev))
1473                 wm_info = &i915_wm_info;
1474         else
1475                 wm_info = &i855_wm_info;
1476
1477         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1478         crtc = intel_get_crtc_for_plane(dev, 0);
1479         if (to_intel_crtc(crtc)->active && crtc->fb) {
1480                 int cpp = crtc->fb->bits_per_pixel / 8;
1481                 if (IS_GEN2(dev))
1482                         cpp = 4;
1483
1484                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1485                                                wm_info, fifo_size, cpp,
1486                                                latency_ns);
1487                 enabled = crtc;
1488         } else
1489                 planea_wm = fifo_size - wm_info->guard_size;
1490
1491         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1492         crtc = intel_get_crtc_for_plane(dev, 1);
1493         if (to_intel_crtc(crtc)->active && crtc->fb) {
1494                 int cpp = crtc->fb->bits_per_pixel / 8;
1495                 if (IS_GEN2(dev))
1496                         cpp = 4;
1497
1498                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1499                                                wm_info, fifo_size, cpp,
1500                                                latency_ns);
1501                 if (enabled == NULL)
1502                         enabled = crtc;
1503                 else
1504                         enabled = NULL;
1505         } else
1506                 planeb_wm = fifo_size - wm_info->guard_size;
1507
1508         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1509
1510         /*
1511          * Overlay gets an aggressive default since video jitter is bad.
1512          */
1513         cwm = 2;
1514
1515         /* Play safe and disable self-refresh before adjusting watermarks. */
1516         if (IS_I945G(dev) || IS_I945GM(dev))
1517                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1518         else if (IS_I915GM(dev))
1519                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1520
1521         /* Calc sr entries for one plane configs */
1522         if (HAS_FW_BLC(dev) && enabled) {
1523                 /* self-refresh has much higher latency */
1524                 static const int sr_latency_ns = 6000;
1525                 int clock = enabled->mode.clock;
1526                 int htotal = enabled->mode.htotal;
1527                 int hdisplay = enabled->mode.hdisplay;
1528                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1529                 unsigned long line_time_us;
1530                 int entries;
1531
1532                 line_time_us = (htotal * 1000) / clock;
1533
1534                 /* Use ns/us then divide to preserve precision */
1535                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1536                         pixel_size * hdisplay;
1537                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1538                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1539                 srwm = wm_info->fifo_size - entries;
1540                 if (srwm < 0)
1541                         srwm = 1;
1542
1543                 if (IS_I945G(dev) || IS_I945GM(dev))
1544                         I915_WRITE(FW_BLC_SELF,
1545                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1546                 else if (IS_I915GM(dev))
1547                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1548         }
1549
1550         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1551                       planea_wm, planeb_wm, cwm, srwm);
1552
1553         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1554         fwater_hi = (cwm & 0x1f);
1555
1556         /* Set request length to 8 cachelines per fetch */
1557         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1558         fwater_hi = fwater_hi | (1 << 8);
1559
1560         I915_WRITE(FW_BLC, fwater_lo);
1561         I915_WRITE(FW_BLC2, fwater_hi);
1562
1563         if (HAS_FW_BLC(dev)) {
1564                 if (enabled) {
1565                         if (IS_I945G(dev) || IS_I945GM(dev))
1566                                 I915_WRITE(FW_BLC_SELF,
1567                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1568                         else if (IS_I915GM(dev))
1569                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1570                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1571                 } else
1572                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1573         }
1574 }
1575
1576 static void i830_update_wm(struct drm_device *dev)
1577 {
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         struct drm_crtc *crtc;
1580         uint32_t fwater_lo;
1581         int planea_wm;
1582
1583         crtc = single_enabled_crtc(dev);
1584         if (crtc == NULL)
1585                 return;
1586
1587         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1588                                        dev_priv->display.get_fifo_size(dev, 0),
1589                                        4, latency_ns);
1590         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1591         fwater_lo |= (3<<8) | planea_wm;
1592
1593         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1594
1595         I915_WRITE(FW_BLC, fwater_lo);
1596 }
1597
1598 #define ILK_LP0_PLANE_LATENCY           700
1599 #define ILK_LP0_CURSOR_LATENCY          1300
1600
1601 /*
1602  * Check the wm result.
1603  *
1604  * If any calculated watermark values is larger than the maximum value that
1605  * can be programmed into the associated watermark register, that watermark
1606  * must be disabled.
1607  */
1608 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1609                                 int fbc_wm, int display_wm, int cursor_wm,
1610                                 const struct intel_watermark_params *display,
1611                                 const struct intel_watermark_params *cursor)
1612 {
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1616                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1617
1618         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1619                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1620                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1621
1622                 /* fbc has it's own way to disable FBC WM */
1623                 I915_WRITE(DISP_ARB_CTL,
1624                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1625                 return false;
1626         }
1627
1628         if (display_wm > display->max_wm) {
1629                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1630                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1631                 return false;
1632         }
1633
1634         if (cursor_wm > cursor->max_wm) {
1635                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1636                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1637                 return false;
1638         }
1639
1640         if (!(fbc_wm || display_wm || cursor_wm)) {
1641                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1642                 return false;
1643         }
1644
1645         return true;
1646 }
1647
1648 /*
1649  * Compute watermark values of WM[1-3],
1650  */
1651 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1652                                   int latency_ns,
1653                                   const struct intel_watermark_params *display,
1654                                   const struct intel_watermark_params *cursor,
1655                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1656 {
1657         struct drm_crtc *crtc;
1658         unsigned long line_time_us;
1659         int hdisplay, htotal, pixel_size, clock;
1660         int line_count, line_size;
1661         int small, large;
1662         int entries;
1663
1664         if (!latency_ns) {
1665                 *fbc_wm = *display_wm = *cursor_wm = 0;
1666                 return false;
1667         }
1668
1669         crtc = intel_get_crtc_for_plane(dev, plane);
1670         hdisplay = crtc->mode.hdisplay;
1671         htotal = crtc->mode.htotal;
1672         clock = crtc->mode.clock;
1673         pixel_size = crtc->fb->bits_per_pixel / 8;
1674
1675         line_time_us = (htotal * 1000) / clock;
1676         line_count = (latency_ns / line_time_us + 1000) / 1000;
1677         line_size = hdisplay * pixel_size;
1678
1679         /* Use the minimum of the small and large buffer method for primary */
1680         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1681         large = line_count * line_size;
1682
1683         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1684         *display_wm = entries + display->guard_size;
1685
1686         /*
1687          * Spec says:
1688          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1689          */
1690         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1691
1692         /* calculate the self-refresh watermark for display cursor */
1693         entries = line_count * pixel_size * 64;
1694         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1695         *cursor_wm = entries + cursor->guard_size;
1696
1697         return ironlake_check_srwm(dev, level,
1698                                    *fbc_wm, *display_wm, *cursor_wm,
1699                                    display, cursor);
1700 }
1701
1702 static void ironlake_update_wm(struct drm_device *dev)
1703 {
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705         int fbc_wm, plane_wm, cursor_wm;
1706         unsigned int enabled;
1707
1708         enabled = 0;
1709         if (g4x_compute_wm0(dev, 0,
1710                             &ironlake_display_wm_info,
1711                             ILK_LP0_PLANE_LATENCY,
1712                             &ironlake_cursor_wm_info,
1713                             ILK_LP0_CURSOR_LATENCY,
1714                             &plane_wm, &cursor_wm)) {
1715                 I915_WRITE(WM0_PIPEA_ILK,
1716                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1717                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1718                               " plane %d, " "cursor: %d\n",
1719                               plane_wm, cursor_wm);
1720                 enabled |= 1;
1721         }
1722
1723         if (g4x_compute_wm0(dev, 1,
1724                             &ironlake_display_wm_info,
1725                             ILK_LP0_PLANE_LATENCY,
1726                             &ironlake_cursor_wm_info,
1727                             ILK_LP0_CURSOR_LATENCY,
1728                             &plane_wm, &cursor_wm)) {
1729                 I915_WRITE(WM0_PIPEB_ILK,
1730                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1731                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1732                               " plane %d, cursor: %d\n",
1733                               plane_wm, cursor_wm);
1734                 enabled |= 2;
1735         }
1736
1737         /*
1738          * Calculate and update the self-refresh watermark only when one
1739          * display plane is used.
1740          */
1741         I915_WRITE(WM3_LP_ILK, 0);
1742         I915_WRITE(WM2_LP_ILK, 0);
1743         I915_WRITE(WM1_LP_ILK, 0);
1744
1745         if (!single_plane_enabled(enabled))
1746                 return;
1747         enabled = ffs(enabled) - 1;
1748
1749         /* WM1 */
1750         if (!ironlake_compute_srwm(dev, 1, enabled,
1751                                    ILK_READ_WM1_LATENCY() * 500,
1752                                    &ironlake_display_srwm_info,
1753                                    &ironlake_cursor_srwm_info,
1754                                    &fbc_wm, &plane_wm, &cursor_wm))
1755                 return;
1756
1757         I915_WRITE(WM1_LP_ILK,
1758                    WM1_LP_SR_EN |
1759                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1760                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1761                    (plane_wm << WM1_LP_SR_SHIFT) |
1762                    cursor_wm);
1763
1764         /* WM2 */
1765         if (!ironlake_compute_srwm(dev, 2, enabled,
1766                                    ILK_READ_WM2_LATENCY() * 500,
1767                                    &ironlake_display_srwm_info,
1768                                    &ironlake_cursor_srwm_info,
1769                                    &fbc_wm, &plane_wm, &cursor_wm))
1770                 return;
1771
1772         I915_WRITE(WM2_LP_ILK,
1773                    WM2_LP_EN |
1774                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1775                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1776                    (plane_wm << WM1_LP_SR_SHIFT) |
1777                    cursor_wm);
1778
1779         /*
1780          * WM3 is unsupported on ILK, probably because we don't have latency
1781          * data for that power state
1782          */
1783 }
1784
1785 static void sandybridge_update_wm(struct drm_device *dev)
1786 {
1787         struct drm_i915_private *dev_priv = dev->dev_private;
1788         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1789         u32 val;
1790         int fbc_wm, plane_wm, cursor_wm;
1791         unsigned int enabled;
1792
1793         enabled = 0;
1794         if (g4x_compute_wm0(dev, 0,
1795                             &sandybridge_display_wm_info, latency,
1796                             &sandybridge_cursor_wm_info, latency,
1797                             &plane_wm, &cursor_wm)) {
1798                 val = I915_READ(WM0_PIPEA_ILK);
1799                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1800                 I915_WRITE(WM0_PIPEA_ILK, val |
1801                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1802                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1803                               " plane %d, " "cursor: %d\n",
1804                               plane_wm, cursor_wm);
1805                 enabled |= 1;
1806         }
1807
1808         if (g4x_compute_wm0(dev, 1,
1809                             &sandybridge_display_wm_info, latency,
1810                             &sandybridge_cursor_wm_info, latency,
1811                             &plane_wm, &cursor_wm)) {
1812                 val = I915_READ(WM0_PIPEB_ILK);
1813                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1814                 I915_WRITE(WM0_PIPEB_ILK, val |
1815                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1816                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1817                               " plane %d, cursor: %d\n",
1818                               plane_wm, cursor_wm);
1819                 enabled |= 2;
1820         }
1821
1822         /*
1823          * Calculate and update the self-refresh watermark only when one
1824          * display plane is used.
1825          *
1826          * SNB support 3 levels of watermark.
1827          *
1828          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1829          * and disabled in the descending order
1830          *
1831          */
1832         I915_WRITE(WM3_LP_ILK, 0);
1833         I915_WRITE(WM2_LP_ILK, 0);
1834         I915_WRITE(WM1_LP_ILK, 0);
1835
1836         if (!single_plane_enabled(enabled) ||
1837             dev_priv->sprite_scaling_enabled)
1838                 return;
1839         enabled = ffs(enabled) - 1;
1840
1841         /* WM1 */
1842         if (!ironlake_compute_srwm(dev, 1, enabled,
1843                                    SNB_READ_WM1_LATENCY() * 500,
1844                                    &sandybridge_display_srwm_info,
1845                                    &sandybridge_cursor_srwm_info,
1846                                    &fbc_wm, &plane_wm, &cursor_wm))
1847                 return;
1848
1849         I915_WRITE(WM1_LP_ILK,
1850                    WM1_LP_SR_EN |
1851                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1852                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1853                    (plane_wm << WM1_LP_SR_SHIFT) |
1854                    cursor_wm);
1855
1856         /* WM2 */
1857         if (!ironlake_compute_srwm(dev, 2, enabled,
1858                                    SNB_READ_WM2_LATENCY() * 500,
1859                                    &sandybridge_display_srwm_info,
1860                                    &sandybridge_cursor_srwm_info,
1861                                    &fbc_wm, &plane_wm, &cursor_wm))
1862                 return;
1863
1864         I915_WRITE(WM2_LP_ILK,
1865                    WM2_LP_EN |
1866                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1867                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1868                    (plane_wm << WM1_LP_SR_SHIFT) |
1869                    cursor_wm);
1870
1871         /* WM3 */
1872         if (!ironlake_compute_srwm(dev, 3, enabled,
1873                                    SNB_READ_WM3_LATENCY() * 500,
1874                                    &sandybridge_display_srwm_info,
1875                                    &sandybridge_cursor_srwm_info,
1876                                    &fbc_wm, &plane_wm, &cursor_wm))
1877                 return;
1878
1879         I915_WRITE(WM3_LP_ILK,
1880                    WM3_LP_EN |
1881                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1882                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1883                    (plane_wm << WM1_LP_SR_SHIFT) |
1884                    cursor_wm);
1885 }
1886
1887 static void ivybridge_update_wm(struct drm_device *dev)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1891         u32 val;
1892         int fbc_wm, plane_wm, cursor_wm;
1893         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1894         unsigned int enabled;
1895
1896         enabled = 0;
1897         if (g4x_compute_wm0(dev, 0,
1898                             &sandybridge_display_wm_info, latency,
1899                             &sandybridge_cursor_wm_info, latency,
1900                             &plane_wm, &cursor_wm)) {
1901                 val = I915_READ(WM0_PIPEA_ILK);
1902                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1903                 I915_WRITE(WM0_PIPEA_ILK, val |
1904                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1905                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1906                               " plane %d, " "cursor: %d\n",
1907                               plane_wm, cursor_wm);
1908                 enabled |= 1;
1909         }
1910
1911         if (g4x_compute_wm0(dev, 1,
1912                             &sandybridge_display_wm_info, latency,
1913                             &sandybridge_cursor_wm_info, latency,
1914                             &plane_wm, &cursor_wm)) {
1915                 val = I915_READ(WM0_PIPEB_ILK);
1916                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1917                 I915_WRITE(WM0_PIPEB_ILK, val |
1918                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1919                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1920                               " plane %d, cursor: %d\n",
1921                               plane_wm, cursor_wm);
1922                 enabled |= 2;
1923         }
1924
1925         if (g4x_compute_wm0(dev, 2,
1926                             &sandybridge_display_wm_info, latency,
1927                             &sandybridge_cursor_wm_info, latency,
1928                             &plane_wm, &cursor_wm)) {
1929                 val = I915_READ(WM0_PIPEC_IVB);
1930                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1931                 I915_WRITE(WM0_PIPEC_IVB, val |
1932                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1933                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1934                               " plane %d, cursor: %d\n",
1935                               plane_wm, cursor_wm);
1936                 enabled |= 3;
1937         }
1938
1939         /*
1940          * Calculate and update the self-refresh watermark only when one
1941          * display plane is used.
1942          *
1943          * SNB support 3 levels of watermark.
1944          *
1945          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1946          * and disabled in the descending order
1947          *
1948          */
1949         I915_WRITE(WM3_LP_ILK, 0);
1950         I915_WRITE(WM2_LP_ILK, 0);
1951         I915_WRITE(WM1_LP_ILK, 0);
1952
1953         if (!single_plane_enabled(enabled) ||
1954             dev_priv->sprite_scaling_enabled)
1955                 return;
1956         enabled = ffs(enabled) - 1;
1957
1958         /* WM1 */
1959         if (!ironlake_compute_srwm(dev, 1, enabled,
1960                                    SNB_READ_WM1_LATENCY() * 500,
1961                                    &sandybridge_display_srwm_info,
1962                                    &sandybridge_cursor_srwm_info,
1963                                    &fbc_wm, &plane_wm, &cursor_wm))
1964                 return;
1965
1966         I915_WRITE(WM1_LP_ILK,
1967                    WM1_LP_SR_EN |
1968                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1969                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1970                    (plane_wm << WM1_LP_SR_SHIFT) |
1971                    cursor_wm);
1972
1973         /* WM2 */
1974         if (!ironlake_compute_srwm(dev, 2, enabled,
1975                                    SNB_READ_WM2_LATENCY() * 500,
1976                                    &sandybridge_display_srwm_info,
1977                                    &sandybridge_cursor_srwm_info,
1978                                    &fbc_wm, &plane_wm, &cursor_wm))
1979                 return;
1980
1981         I915_WRITE(WM2_LP_ILK,
1982                    WM2_LP_EN |
1983                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1984                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1985                    (plane_wm << WM1_LP_SR_SHIFT) |
1986                    cursor_wm);
1987
1988         /* WM3, note we have to correct the cursor latency */
1989         if (!ironlake_compute_srwm(dev, 3, enabled,
1990                                    SNB_READ_WM3_LATENCY() * 500,
1991                                    &sandybridge_display_srwm_info,
1992                                    &sandybridge_cursor_srwm_info,
1993                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
1994             !ironlake_compute_srwm(dev, 3, enabled,
1995                                    2 * SNB_READ_WM3_LATENCY() * 500,
1996                                    &sandybridge_display_srwm_info,
1997                                    &sandybridge_cursor_srwm_info,
1998                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
1999                 return;
2000
2001         I915_WRITE(WM3_LP_ILK,
2002                    WM3_LP_EN |
2003                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2004                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2005                    (plane_wm << WM1_LP_SR_SHIFT) |
2006                    cursor_wm);
2007 }
2008
2009 static void
2010 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2011                                  struct drm_display_mode *mode)
2012 {
2013         struct drm_i915_private *dev_priv = dev->dev_private;
2014         u32 temp;
2015
2016         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2017         temp &= ~PIPE_WM_LINETIME_MASK;
2018
2019         /* The WM are computed with base on how long it takes to fill a single
2020          * row at the given clock rate, multiplied by 8.
2021          * */
2022         temp |= PIPE_WM_LINETIME_TIME(
2023                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2024
2025         /* IPS watermarks are only used by pipe A, and are ignored by
2026          * pipes B and C.  They are calculated similarly to the common
2027          * linetime values, except that we are using CD clock frequency
2028          * in MHz instead of pixel rate for the division.
2029          *
2030          * This is a placeholder for the IPS watermark calculation code.
2031          */
2032
2033         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2034 }
2035
2036 static bool
2037 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2038                               uint32_t sprite_width, int pixel_size,
2039                               const struct intel_watermark_params *display,
2040                               int display_latency_ns, int *sprite_wm)
2041 {
2042         struct drm_crtc *crtc;
2043         int clock;
2044         int entries, tlb_miss;
2045
2046         crtc = intel_get_crtc_for_plane(dev, plane);
2047         if (crtc->fb == NULL || !to_intel_crtc(crtc)->active) {
2048                 *sprite_wm = display->guard_size;
2049                 return false;
2050         }
2051
2052         clock = crtc->mode.clock;
2053
2054         /* Use the small buffer method to calculate the sprite watermark */
2055         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2056         tlb_miss = display->fifo_size*display->cacheline_size -
2057                 sprite_width * 8;
2058         if (tlb_miss > 0)
2059                 entries += tlb_miss;
2060         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2061         *sprite_wm = entries + display->guard_size;
2062         if (*sprite_wm > (int)display->max_wm)
2063                 *sprite_wm = display->max_wm;
2064
2065         return true;
2066 }
2067
2068 static bool
2069 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2070                                 uint32_t sprite_width, int pixel_size,
2071                                 const struct intel_watermark_params *display,
2072                                 int latency_ns, int *sprite_wm)
2073 {
2074         struct drm_crtc *crtc;
2075         unsigned long line_time_us;
2076         int clock;
2077         int line_count, line_size;
2078         int small, large;
2079         int entries;
2080
2081         if (!latency_ns) {
2082                 *sprite_wm = 0;
2083                 return false;
2084         }
2085
2086         crtc = intel_get_crtc_for_plane(dev, plane);
2087         clock = crtc->mode.clock;
2088         if (!clock) {
2089                 *sprite_wm = 0;
2090                 return false;
2091         }
2092
2093         line_time_us = (sprite_width * 1000) / clock;
2094         if (!line_time_us) {
2095                 *sprite_wm = 0;
2096                 return false;
2097         }
2098
2099         line_count = (latency_ns / line_time_us + 1000) / 1000;
2100         line_size = sprite_width * pixel_size;
2101
2102         /* Use the minimum of the small and large buffer method for primary */
2103         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2104         large = line_count * line_size;
2105
2106         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2107         *sprite_wm = entries + display->guard_size;
2108
2109         return *sprite_wm > 0x3ff ? false : true;
2110 }
2111
2112 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2113                                          uint32_t sprite_width, int pixel_size)
2114 {
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2117         u32 val;
2118         int sprite_wm, reg;
2119         int ret;
2120
2121         switch (pipe) {
2122         case 0:
2123                 reg = WM0_PIPEA_ILK;
2124                 break;
2125         case 1:
2126                 reg = WM0_PIPEB_ILK;
2127                 break;
2128         case 2:
2129                 reg = WM0_PIPEC_IVB;
2130                 break;
2131         default:
2132                 return; /* bad pipe */
2133         }
2134
2135         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2136                                             &sandybridge_display_wm_info,
2137                                             latency, &sprite_wm);
2138         if (!ret) {
2139                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2140                               pipe);
2141                 return;
2142         }
2143
2144         val = I915_READ(reg);
2145         val &= ~WM0_PIPE_SPRITE_MASK;
2146         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2147         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2148
2149
2150         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2151                                               pixel_size,
2152                                               &sandybridge_display_srwm_info,
2153                                               SNB_READ_WM1_LATENCY() * 500,
2154                                               &sprite_wm);
2155         if (!ret) {
2156                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2157                               pipe);
2158                 return;
2159         }
2160         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2161
2162         /* Only IVB has two more LP watermarks for sprite */
2163         if (!IS_IVYBRIDGE(dev))
2164                 return;
2165
2166         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2167                                               pixel_size,
2168                                               &sandybridge_display_srwm_info,
2169                                               SNB_READ_WM2_LATENCY() * 500,
2170                                               &sprite_wm);
2171         if (!ret) {
2172                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2173                               pipe);
2174                 return;
2175         }
2176         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2177
2178         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2179                                               pixel_size,
2180                                               &sandybridge_display_srwm_info,
2181                                               SNB_READ_WM3_LATENCY() * 500,
2182                                               &sprite_wm);
2183         if (!ret) {
2184                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2185                               pipe);
2186                 return;
2187         }
2188         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2189 }
2190
2191 /**
2192  * intel_update_watermarks - update FIFO watermark values based on current modes
2193  *
2194  * Calculate watermark values for the various WM regs based on current mode
2195  * and plane configuration.
2196  *
2197  * There are several cases to deal with here:
2198  *   - normal (i.e. non-self-refresh)
2199  *   - self-refresh (SR) mode
2200  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2201  *   - lines are small relative to FIFO size (buffer can hold more than 2
2202  *     lines), so need to account for TLB latency
2203  *
2204  *   The normal calculation is:
2205  *     watermark = dotclock * bytes per pixel * latency
2206  *   where latency is platform & configuration dependent (we assume pessimal
2207  *   values here).
2208  *
2209  *   The SR calculation is:
2210  *     watermark = (trunc(latency/line time)+1) * surface width *
2211  *       bytes per pixel
2212  *   where
2213  *     line time = htotal / dotclock
2214  *     surface width = hdisplay for normal plane and 64 for cursor
2215  *   and latency is assumed to be high, as above.
2216  *
2217  * The final value programmed to the register should always be rounded up,
2218  * and include an extra 2 entries to account for clock crossings.
2219  *
2220  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2221  * to set the non-SR watermarks to 8.
2222  */
2223 void intel_update_watermarks(struct drm_device *dev)
2224 {
2225         struct drm_i915_private *dev_priv = dev->dev_private;
2226
2227         if (dev_priv->display.update_wm)
2228                 dev_priv->display.update_wm(dev);
2229 }
2230
2231 void intel_update_linetime_watermarks(struct drm_device *dev,
2232                 int pipe, struct drm_display_mode *mode)
2233 {
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235
2236         if (dev_priv->display.update_linetime_wm)
2237                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2238 }
2239
2240 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2241                                     uint32_t sprite_width, int pixel_size)
2242 {
2243         struct drm_i915_private *dev_priv = dev->dev_private;
2244
2245         if (dev_priv->display.update_sprite_wm)
2246                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2247                                                    pixel_size);
2248 }
2249
2250 static struct drm_i915_gem_object *
2251 intel_alloc_context_page(struct drm_device *dev)
2252 {
2253         struct drm_i915_gem_object *ctx;
2254         int ret;
2255
2256         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2257
2258         ctx = i915_gem_alloc_object(dev, 4096);
2259         if (!ctx) {
2260                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2261                 return NULL;
2262         }
2263
2264         ret = i915_gem_object_pin(ctx, 4096, true, false);
2265         if (ret) {
2266                 DRM_ERROR("failed to pin power context: %d\n", ret);
2267                 goto err_unref;
2268         }
2269
2270         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2271         if (ret) {
2272                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2273                 goto err_unpin;
2274         }
2275
2276         return ctx;
2277
2278 err_unpin:
2279         i915_gem_object_unpin(ctx);
2280 err_unref:
2281         drm_gem_object_unreference(&ctx->base);
2282         mutex_unlock(&dev->struct_mutex);
2283         return NULL;
2284 }
2285
2286 /**
2287  * Lock protecting IPS related data structures
2288  */
2289 DEFINE_SPINLOCK(mchdev_lock);
2290
2291 /* Global for IPS driver to get at the current i915 device. Protected by
2292  * mchdev_lock. */
2293 static struct drm_i915_private *i915_mch_dev;
2294
2295 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2296 {
2297         struct drm_i915_private *dev_priv = dev->dev_private;
2298         u16 rgvswctl;
2299
2300         assert_spin_locked(&mchdev_lock);
2301
2302         rgvswctl = I915_READ16(MEMSWCTL);
2303         if (rgvswctl & MEMCTL_CMD_STS) {
2304                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2305                 return false; /* still busy with another command */
2306         }
2307
2308         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2309                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2310         I915_WRITE16(MEMSWCTL, rgvswctl);
2311         POSTING_READ16(MEMSWCTL);
2312
2313         rgvswctl |= MEMCTL_CMD_STS;
2314         I915_WRITE16(MEMSWCTL, rgvswctl);
2315
2316         return true;
2317 }
2318
2319 static void ironlake_enable_drps(struct drm_device *dev)
2320 {
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         u32 rgvmodectl = I915_READ(MEMMODECTL);
2323         u8 fmax, fmin, fstart, vstart;
2324
2325         spin_lock_irq(&mchdev_lock);
2326
2327         /* Enable temp reporting */
2328         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2329         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2330
2331         /* 100ms RC evaluation intervals */
2332         I915_WRITE(RCUPEI, 100000);
2333         I915_WRITE(RCDNEI, 100000);
2334
2335         /* Set max/min thresholds to 90ms and 80ms respectively */
2336         I915_WRITE(RCBMAXAVG, 90000);
2337         I915_WRITE(RCBMINAVG, 80000);
2338
2339         I915_WRITE(MEMIHYST, 1);
2340
2341         /* Set up min, max, and cur for interrupt handling */
2342         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2343         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2344         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2345                 MEMMODE_FSTART_SHIFT;
2346
2347         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2348                 PXVFREQ_PX_SHIFT;
2349
2350         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2351         dev_priv->ips.fstart = fstart;
2352
2353         dev_priv->ips.max_delay = fstart;
2354         dev_priv->ips.min_delay = fmin;
2355         dev_priv->ips.cur_delay = fstart;
2356
2357         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2358                          fmax, fmin, fstart);
2359
2360         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2361
2362         /*
2363          * Interrupts will be enabled in ironlake_irq_postinstall
2364          */
2365
2366         I915_WRITE(VIDSTART, vstart);
2367         POSTING_READ(VIDSTART);
2368
2369         rgvmodectl |= MEMMODE_SWMODE_EN;
2370         I915_WRITE(MEMMODECTL, rgvmodectl);
2371
2372         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2373                 DRM_ERROR("stuck trying to change perf mode\n");
2374         mdelay(1);
2375
2376         ironlake_set_drps(dev, fstart);
2377
2378         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2379                 I915_READ(0x112e0);
2380         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2381         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2382         getrawmonotonic(&dev_priv->ips.last_time2);
2383
2384         spin_unlock_irq(&mchdev_lock);
2385 }
2386
2387 static void ironlake_disable_drps(struct drm_device *dev)
2388 {
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         u16 rgvswctl;
2391
2392         spin_lock_irq(&mchdev_lock);
2393
2394         rgvswctl = I915_READ16(MEMSWCTL);
2395
2396         /* Ack interrupts, disable EFC interrupt */
2397         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2398         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2399         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2400         I915_WRITE(DEIIR, DE_PCU_EVENT);
2401         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2402
2403         /* Go back to the starting frequency */
2404         ironlake_set_drps(dev, dev_priv->ips.fstart);
2405         mdelay(1);
2406         rgvswctl |= MEMCTL_CMD_STS;
2407         I915_WRITE(MEMSWCTL, rgvswctl);
2408         mdelay(1);
2409
2410         spin_unlock_irq(&mchdev_lock);
2411 }
2412
2413 /* There's a funny hw issue where the hw returns all 0 when reading from
2414  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2415  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2416  * all limits and the gpu stuck at whatever frequency it is at atm).
2417  */
2418 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2419 {
2420         u32 limits;
2421
2422         limits = 0;
2423
2424         if (*val >= dev_priv->rps.max_delay)
2425                 *val = dev_priv->rps.max_delay;
2426         limits |= dev_priv->rps.max_delay << 24;
2427
2428         /* Only set the down limit when we've reached the lowest level to avoid
2429          * getting more interrupts, otherwise leave this clear. This prevents a
2430          * race in the hw when coming out of rc6: There's a tiny window where
2431          * the hw runs at the minimal clock before selecting the desired
2432          * frequency, if the down threshold expires in that window we will not
2433          * receive a down interrupt. */
2434         if (*val <= dev_priv->rps.min_delay) {
2435                 *val = dev_priv->rps.min_delay;
2436                 limits |= dev_priv->rps.min_delay << 16;
2437         }
2438
2439         return limits;
2440 }
2441
2442 void gen6_set_rps(struct drm_device *dev, u8 val)
2443 {
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         u32 limits = gen6_rps_limits(dev_priv, &val);
2446
2447         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2448         WARN_ON(val > dev_priv->rps.max_delay);
2449         WARN_ON(val < dev_priv->rps.min_delay);
2450
2451         if (val == dev_priv->rps.cur_delay)
2452                 return;
2453
2454         I915_WRITE(GEN6_RPNSWREQ,
2455                    GEN6_FREQUENCY(val) |
2456                    GEN6_OFFSET(0) |
2457                    GEN6_AGGRESSIVE_TURBO);
2458
2459         /* Make sure we continue to get interrupts
2460          * until we hit the minimum or maximum frequencies.
2461          */
2462         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2463
2464         POSTING_READ(GEN6_RPNSWREQ);
2465
2466         dev_priv->rps.cur_delay = val;
2467
2468         trace_intel_gpu_freq_change(val * 50);
2469 }
2470
2471 static void gen6_disable_rps(struct drm_device *dev)
2472 {
2473         struct drm_i915_private *dev_priv = dev->dev_private;
2474
2475         I915_WRITE(GEN6_RC_CONTROL, 0);
2476         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2477         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2478         I915_WRITE(GEN6_PMIER, 0);
2479         /* Complete PM interrupt masking here doesn't race with the rps work
2480          * item again unmasking PM interrupts because that is using a different
2481          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2482          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2483
2484         spin_lock_irq(&dev_priv->rps.lock);
2485         dev_priv->rps.pm_iir = 0;
2486         spin_unlock_irq(&dev_priv->rps.lock);
2487
2488         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2489 }
2490
2491 int intel_enable_rc6(const struct drm_device *dev)
2492 {
2493         /* Respect the kernel parameter if it is set */
2494         if (i915_enable_rc6 >= 0)
2495                 return i915_enable_rc6;
2496
2497         /* Disable RC6 on Ironlake */
2498         if (INTEL_INFO(dev)->gen == 5)
2499                 return 0;
2500
2501         if (IS_HASWELL(dev)) {
2502                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2503                 return INTEL_RC6_ENABLE;
2504         }
2505
2506         /* snb/ivb have more than one rc6 state. */
2507         if (INTEL_INFO(dev)->gen == 6) {
2508                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2509                 return INTEL_RC6_ENABLE;
2510         }
2511
2512         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2513         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2514 }
2515
2516 static void gen6_enable_rps(struct drm_device *dev)
2517 {
2518         struct drm_i915_private *dev_priv = dev->dev_private;
2519         struct intel_ring_buffer *ring;
2520         u32 rp_state_cap;
2521         u32 gt_perf_status;
2522         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2523         u32 gtfifodbg;
2524         int rc6_mode;
2525         int i, ret;
2526
2527         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2528
2529         /* Here begins a magic sequence of register writes to enable
2530          * auto-downclocking.
2531          *
2532          * Perhaps there might be some value in exposing these to
2533          * userspace...
2534          */
2535         I915_WRITE(GEN6_RC_STATE, 0);
2536
2537         /* Clear the DBG now so we don't confuse earlier errors */
2538         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2539                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2540                 I915_WRITE(GTFIFODBG, gtfifodbg);
2541         }
2542
2543         gen6_gt_force_wake_get(dev_priv);
2544
2545         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2546         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2547
2548         /* In units of 100MHz */
2549         dev_priv->rps.max_delay = rp_state_cap & 0xff;
2550         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2551         dev_priv->rps.cur_delay = 0;
2552
2553         /* disable the counters and set deterministic thresholds */
2554         I915_WRITE(GEN6_RC_CONTROL, 0);
2555
2556         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2557         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2558         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2559         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2560         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2561
2562         for_each_ring(ring, dev_priv, i)
2563                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2564
2565         I915_WRITE(GEN6_RC_SLEEP, 0);
2566         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2567         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2568         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2569         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2570
2571         /* Check if we are enabling RC6 */
2572         rc6_mode = intel_enable_rc6(dev_priv->dev);
2573         if (rc6_mode & INTEL_RC6_ENABLE)
2574                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2575
2576         /* We don't use those on Haswell */
2577         if (!IS_HASWELL(dev)) {
2578                 if (rc6_mode & INTEL_RC6p_ENABLE)
2579                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2580
2581                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2582                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2583         }
2584
2585         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2586                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2587                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2588                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2589
2590         I915_WRITE(GEN6_RC_CONTROL,
2591                    rc6_mask |
2592                    GEN6_RC_CTL_EI_MODE(1) |
2593                    GEN6_RC_CTL_HW_ENABLE);
2594
2595         I915_WRITE(GEN6_RPNSWREQ,
2596                    GEN6_FREQUENCY(10) |
2597                    GEN6_OFFSET(0) |
2598                    GEN6_AGGRESSIVE_TURBO);
2599         I915_WRITE(GEN6_RC_VIDEO_FREQ,
2600                    GEN6_FREQUENCY(12));
2601
2602         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2603         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2604                    dev_priv->rps.max_delay << 24 |
2605                    dev_priv->rps.min_delay << 16);
2606
2607         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2608         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2609         I915_WRITE(GEN6_RP_UP_EI, 66000);
2610         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2611
2612         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2613         I915_WRITE(GEN6_RP_CONTROL,
2614                    GEN6_RP_MEDIA_TURBO |
2615                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2616                    GEN6_RP_MEDIA_IS_GFX |
2617                    GEN6_RP_ENABLE |
2618                    GEN6_RP_UP_BUSY_AVG |
2619                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2620
2621         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2622         if (!ret) {
2623                 pcu_mbox = 0;
2624                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2625                 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2626                         dev_priv->rps.max_delay = pcu_mbox & 0xff;
2627                         DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2628                 }
2629         } else {
2630                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2631         }
2632
2633         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2634
2635         /* requires MSI enabled */
2636         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2637         spin_lock_irq(&dev_priv->rps.lock);
2638         WARN_ON(dev_priv->rps.pm_iir != 0);
2639         I915_WRITE(GEN6_PMIMR, 0);
2640         spin_unlock_irq(&dev_priv->rps.lock);
2641         /* enable all PM interrupts */
2642         I915_WRITE(GEN6_PMINTRMSK, 0);
2643
2644         rc6vids = 0;
2645         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2646         if (IS_GEN6(dev) && ret) {
2647                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2648         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2649                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2650                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2651                 rc6vids &= 0xffff00;
2652                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2653                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2654                 if (ret)
2655                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2656         }
2657
2658         gen6_gt_force_wake_put(dev_priv);
2659 }
2660
2661 static void gen6_update_ring_freq(struct drm_device *dev)
2662 {
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         int min_freq = 15;
2665         int gpu_freq;
2666         unsigned int ia_freq, max_ia_freq;
2667         int scaling_factor = 180;
2668
2669         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2670
2671         max_ia_freq = cpufreq_quick_get_max(0);
2672         /*
2673          * Default to measured freq if none found, PCU will ensure we don't go
2674          * over
2675          */
2676         if (!max_ia_freq)
2677                 max_ia_freq = tsc_khz;
2678
2679         /* Convert from kHz to MHz */
2680         max_ia_freq /= 1000;
2681
2682         /*
2683          * For each potential GPU frequency, load a ring frequency we'd like
2684          * to use for memory access.  We do this by specifying the IA frequency
2685          * the PCU should use as a reference to determine the ring frequency.
2686          */
2687         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2688              gpu_freq--) {
2689                 int diff = dev_priv->rps.max_delay - gpu_freq;
2690
2691                 /*
2692                  * For GPU frequencies less than 750MHz, just use the lowest
2693                  * ring freq.
2694                  */
2695                 if (gpu_freq < min_freq)
2696                         ia_freq = 800;
2697                 else
2698                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2699                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2700                 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2701
2702                 sandybridge_pcode_write(dev_priv,
2703                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2704                                         ia_freq | gpu_freq);
2705         }
2706 }
2707
2708 void ironlake_teardown_rc6(struct drm_device *dev)
2709 {
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711
2712         if (dev_priv->ips.renderctx) {
2713                 i915_gem_object_unpin(dev_priv->ips.renderctx);
2714                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2715                 dev_priv->ips.renderctx = NULL;
2716         }
2717
2718         if (dev_priv->ips.pwrctx) {
2719                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2720                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2721                 dev_priv->ips.pwrctx = NULL;
2722         }
2723 }
2724
2725 static void ironlake_disable_rc6(struct drm_device *dev)
2726 {
2727         struct drm_i915_private *dev_priv = dev->dev_private;
2728
2729         if (I915_READ(PWRCTXA)) {
2730                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2731                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2732                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2733                          50);
2734
2735                 I915_WRITE(PWRCTXA, 0);
2736                 POSTING_READ(PWRCTXA);
2737
2738                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2739                 POSTING_READ(RSTDBYCTL);
2740         }
2741 }
2742
2743 static int ironlake_setup_rc6(struct drm_device *dev)
2744 {
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746
2747         if (dev_priv->ips.renderctx == NULL)
2748                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2749         if (!dev_priv->ips.renderctx)
2750                 return -ENOMEM;
2751
2752         if (dev_priv->ips.pwrctx == NULL)
2753                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2754         if (!dev_priv->ips.pwrctx) {
2755                 ironlake_teardown_rc6(dev);
2756                 return -ENOMEM;
2757         }
2758
2759         return 0;
2760 }
2761
2762 static void ironlake_enable_rc6(struct drm_device *dev)
2763 {
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2766         bool was_interruptible;
2767         int ret;
2768
2769         /* rc6 disabled by default due to repeated reports of hanging during
2770          * boot and resume.
2771          */
2772         if (!intel_enable_rc6(dev))
2773                 return;
2774
2775         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2776
2777         ret = ironlake_setup_rc6(dev);
2778         if (ret)
2779                 return;
2780
2781         was_interruptible = dev_priv->mm.interruptible;
2782         dev_priv->mm.interruptible = false;
2783
2784         /*
2785          * GPU can automatically power down the render unit if given a page
2786          * to save state.
2787          */
2788         ret = intel_ring_begin(ring, 6);
2789         if (ret) {
2790                 ironlake_teardown_rc6(dev);
2791                 dev_priv->mm.interruptible = was_interruptible;
2792                 return;
2793         }
2794
2795         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2796         intel_ring_emit(ring, MI_SET_CONTEXT);
2797         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2798                         MI_MM_SPACE_GTT |
2799                         MI_SAVE_EXT_STATE_EN |
2800                         MI_RESTORE_EXT_STATE_EN |
2801                         MI_RESTORE_INHIBIT);
2802         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2803         intel_ring_emit(ring, MI_NOOP);
2804         intel_ring_emit(ring, MI_FLUSH);
2805         intel_ring_advance(ring);
2806
2807         /*
2808          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2809          * does an implicit flush, combined with MI_FLUSH above, it should be
2810          * safe to assume that renderctx is valid
2811          */
2812         ret = intel_ring_idle(ring);
2813         dev_priv->mm.interruptible = was_interruptible;
2814         if (ret) {
2815                 DRM_ERROR("failed to enable ironlake power power savings\n");
2816                 ironlake_teardown_rc6(dev);
2817                 return;
2818         }
2819
2820         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2821         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2822 }
2823
2824 static unsigned long intel_pxfreq(u32 vidfreq)
2825 {
2826         unsigned long freq;
2827         int div = (vidfreq & 0x3f0000) >> 16;
2828         int post = (vidfreq & 0x3000) >> 12;
2829         int pre = (vidfreq & 0x7);
2830
2831         if (!pre)
2832                 return 0;
2833
2834         freq = ((div * 133333) / ((1<<post) * pre));
2835
2836         return freq;
2837 }
2838
2839 static const struct cparams {
2840         u16 i;
2841         u16 t;
2842         u16 m;
2843         u16 c;
2844 } cparams[] = {
2845         { 1, 1333, 301, 28664 },
2846         { 1, 1066, 294, 24460 },
2847         { 1, 800, 294, 25192 },
2848         { 0, 1333, 276, 27605 },
2849         { 0, 1066, 276, 27605 },
2850         { 0, 800, 231, 23784 },
2851 };
2852
2853 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2854 {
2855         u64 total_count, diff, ret;
2856         u32 count1, count2, count3, m = 0, c = 0;
2857         unsigned long now = jiffies_to_msecs(jiffies), diff1;
2858         int i;
2859
2860         assert_spin_locked(&mchdev_lock);
2861
2862         diff1 = now - dev_priv->ips.last_time1;
2863
2864         /* Prevent division-by-zero if we are asking too fast.
2865          * Also, we don't get interesting results if we are polling
2866          * faster than once in 10ms, so just return the saved value
2867          * in such cases.
2868          */
2869         if (diff1 <= 10)
2870                 return dev_priv->ips.chipset_power;
2871
2872         count1 = I915_READ(DMIEC);
2873         count2 = I915_READ(DDREC);
2874         count3 = I915_READ(CSIEC);
2875
2876         total_count = count1 + count2 + count3;
2877
2878         /* FIXME: handle per-counter overflow */
2879         if (total_count < dev_priv->ips.last_count1) {
2880                 diff = ~0UL - dev_priv->ips.last_count1;
2881                 diff += total_count;
2882         } else {
2883                 diff = total_count - dev_priv->ips.last_count1;
2884         }
2885
2886         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2887                 if (cparams[i].i == dev_priv->ips.c_m &&
2888                     cparams[i].t == dev_priv->ips.r_t) {
2889                         m = cparams[i].m;
2890                         c = cparams[i].c;
2891                         break;
2892                 }
2893         }
2894
2895         diff = div_u64(diff, diff1);
2896         ret = ((m * diff) + c);
2897         ret = div_u64(ret, 10);
2898
2899         dev_priv->ips.last_count1 = total_count;
2900         dev_priv->ips.last_time1 = now;
2901
2902         dev_priv->ips.chipset_power = ret;
2903
2904         return ret;
2905 }
2906
2907 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2908 {
2909         unsigned long val;
2910
2911         if (dev_priv->info->gen != 5)
2912                 return 0;
2913
2914         spin_lock_irq(&mchdev_lock);
2915
2916         val = __i915_chipset_val(dev_priv);
2917
2918         spin_unlock_irq(&mchdev_lock);
2919
2920         return val;
2921 }
2922
2923 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2924 {
2925         unsigned long m, x, b;
2926         u32 tsfs;
2927
2928         tsfs = I915_READ(TSFS);
2929
2930         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2931         x = I915_READ8(TR1);
2932
2933         b = tsfs & TSFS_INTR_MASK;
2934
2935         return ((m * x) / 127) - b;
2936 }
2937
2938 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2939 {
2940         static const struct v_table {
2941                 u16 vd; /* in .1 mil */
2942                 u16 vm; /* in .1 mil */
2943         } v_table[] = {
2944                 { 0, 0, },
2945                 { 375, 0, },
2946                 { 500, 0, },
2947                 { 625, 0, },
2948                 { 750, 0, },
2949                 { 875, 0, },
2950                 { 1000, 0, },
2951                 { 1125, 0, },
2952                 { 4125, 3000, },
2953                 { 4125, 3000, },
2954                 { 4125, 3000, },
2955                 { 4125, 3000, },
2956                 { 4125, 3000, },
2957                 { 4125, 3000, },
2958                 { 4125, 3000, },
2959                 { 4125, 3000, },
2960                 { 4125, 3000, },
2961                 { 4125, 3000, },
2962                 { 4125, 3000, },
2963                 { 4125, 3000, },
2964                 { 4125, 3000, },
2965                 { 4125, 3000, },
2966                 { 4125, 3000, },
2967                 { 4125, 3000, },
2968                 { 4125, 3000, },
2969                 { 4125, 3000, },
2970                 { 4125, 3000, },
2971                 { 4125, 3000, },
2972                 { 4125, 3000, },
2973                 { 4125, 3000, },
2974                 { 4125, 3000, },
2975                 { 4125, 3000, },
2976                 { 4250, 3125, },
2977                 { 4375, 3250, },
2978                 { 4500, 3375, },
2979                 { 4625, 3500, },
2980                 { 4750, 3625, },
2981                 { 4875, 3750, },
2982                 { 5000, 3875, },
2983                 { 5125, 4000, },
2984                 { 5250, 4125, },
2985                 { 5375, 4250, },
2986                 { 5500, 4375, },
2987                 { 5625, 4500, },
2988                 { 5750, 4625, },
2989                 { 5875, 4750, },
2990                 { 6000, 4875, },
2991                 { 6125, 5000, },
2992                 { 6250, 5125, },
2993                 { 6375, 5250, },
2994                 { 6500, 5375, },
2995                 { 6625, 5500, },
2996                 { 6750, 5625, },
2997                 { 6875, 5750, },
2998                 { 7000, 5875, },
2999                 { 7125, 6000, },
3000                 { 7250, 6125, },
3001                 { 7375, 6250, },
3002                 { 7500, 6375, },
3003                 { 7625, 6500, },
3004                 { 7750, 6625, },
3005                 { 7875, 6750, },
3006                 { 8000, 6875, },
3007                 { 8125, 7000, },
3008                 { 8250, 7125, },
3009                 { 8375, 7250, },
3010                 { 8500, 7375, },
3011                 { 8625, 7500, },
3012                 { 8750, 7625, },
3013                 { 8875, 7750, },
3014                 { 9000, 7875, },
3015                 { 9125, 8000, },
3016                 { 9250, 8125, },
3017                 { 9375, 8250, },
3018                 { 9500, 8375, },
3019                 { 9625, 8500, },
3020                 { 9750, 8625, },
3021                 { 9875, 8750, },
3022                 { 10000, 8875, },
3023                 { 10125, 9000, },
3024                 { 10250, 9125, },
3025                 { 10375, 9250, },
3026                 { 10500, 9375, },
3027                 { 10625, 9500, },
3028                 { 10750, 9625, },
3029                 { 10875, 9750, },
3030                 { 11000, 9875, },
3031                 { 11125, 10000, },
3032                 { 11250, 10125, },
3033                 { 11375, 10250, },
3034                 { 11500, 10375, },
3035                 { 11625, 10500, },
3036                 { 11750, 10625, },
3037                 { 11875, 10750, },
3038                 { 12000, 10875, },
3039                 { 12125, 11000, },
3040                 { 12250, 11125, },
3041                 { 12375, 11250, },
3042                 { 12500, 11375, },
3043                 { 12625, 11500, },
3044                 { 12750, 11625, },
3045                 { 12875, 11750, },
3046                 { 13000, 11875, },
3047                 { 13125, 12000, },
3048                 { 13250, 12125, },
3049                 { 13375, 12250, },
3050                 { 13500, 12375, },
3051                 { 13625, 12500, },
3052                 { 13750, 12625, },
3053                 { 13875, 12750, },
3054                 { 14000, 12875, },
3055                 { 14125, 13000, },
3056                 { 14250, 13125, },
3057                 { 14375, 13250, },
3058                 { 14500, 13375, },
3059                 { 14625, 13500, },
3060                 { 14750, 13625, },
3061                 { 14875, 13750, },
3062                 { 15000, 13875, },
3063                 { 15125, 14000, },
3064                 { 15250, 14125, },
3065                 { 15375, 14250, },
3066                 { 15500, 14375, },
3067                 { 15625, 14500, },
3068                 { 15750, 14625, },
3069                 { 15875, 14750, },
3070                 { 16000, 14875, },
3071                 { 16125, 15000, },
3072         };
3073         if (dev_priv->info->is_mobile)
3074                 return v_table[pxvid].vm;
3075         else
3076                 return v_table[pxvid].vd;
3077 }
3078
3079 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3080 {
3081         struct timespec now, diff1;
3082         u64 diff;
3083         unsigned long diffms;
3084         u32 count;
3085
3086         assert_spin_locked(&mchdev_lock);
3087
3088         getrawmonotonic(&now);
3089         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3090
3091         /* Don't divide by 0 */
3092         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3093         if (!diffms)
3094                 return;
3095
3096         count = I915_READ(GFXEC);
3097
3098         if (count < dev_priv->ips.last_count2) {
3099                 diff = ~0UL - dev_priv->ips.last_count2;
3100                 diff += count;
3101         } else {
3102                 diff = count - dev_priv->ips.last_count2;
3103         }
3104
3105         dev_priv->ips.last_count2 = count;
3106         dev_priv->ips.last_time2 = now;
3107
3108         /* More magic constants... */
3109         diff = diff * 1181;
3110         diff = div_u64(diff, diffms * 10);
3111         dev_priv->ips.gfx_power = diff;
3112 }
3113
3114 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3115 {
3116         if (dev_priv->info->gen != 5)
3117                 return;
3118
3119         spin_lock_irq(&mchdev_lock);
3120
3121         __i915_update_gfx_val(dev_priv);
3122
3123         spin_unlock_irq(&mchdev_lock);
3124 }
3125
3126 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3127 {
3128         unsigned long t, corr, state1, corr2, state2;
3129         u32 pxvid, ext_v;
3130
3131         assert_spin_locked(&mchdev_lock);
3132
3133         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3134         pxvid = (pxvid >> 24) & 0x7f;
3135         ext_v = pvid_to_extvid(dev_priv, pxvid);
3136
3137         state1 = ext_v;
3138
3139         t = i915_mch_val(dev_priv);
3140
3141         /* Revel in the empirically derived constants */
3142
3143         /* Correction factor in 1/100000 units */
3144         if (t > 80)
3145                 corr = ((t * 2349) + 135940);
3146         else if (t >= 50)
3147                 corr = ((t * 964) + 29317);
3148         else /* < 50 */
3149                 corr = ((t * 301) + 1004);
3150
3151         corr = corr * ((150142 * state1) / 10000 - 78642);
3152         corr /= 100000;
3153         corr2 = (corr * dev_priv->ips.corr);
3154
3155         state2 = (corr2 * state1) / 10000;
3156         state2 /= 100; /* convert to mW */
3157
3158         __i915_update_gfx_val(dev_priv);
3159
3160         return dev_priv->ips.gfx_power + state2;
3161 }
3162
3163 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3164 {
3165         unsigned long val;
3166
3167         if (dev_priv->info->gen != 5)
3168                 return 0;
3169
3170         spin_lock_irq(&mchdev_lock);
3171
3172         val = __i915_gfx_val(dev_priv);
3173
3174         spin_unlock_irq(&mchdev_lock);
3175
3176         return val;
3177 }
3178
3179 /**
3180  * i915_read_mch_val - return value for IPS use
3181  *
3182  * Calculate and return a value for the IPS driver to use when deciding whether
3183  * we have thermal and power headroom to increase CPU or GPU power budget.
3184  */
3185 unsigned long i915_read_mch_val(void)
3186 {
3187         struct drm_i915_private *dev_priv;
3188         unsigned long chipset_val, graphics_val, ret = 0;
3189
3190         spin_lock_irq(&mchdev_lock);
3191         if (!i915_mch_dev)
3192                 goto out_unlock;
3193         dev_priv = i915_mch_dev;
3194
3195         chipset_val = __i915_chipset_val(dev_priv);
3196         graphics_val = __i915_gfx_val(dev_priv);
3197
3198         ret = chipset_val + graphics_val;
3199
3200 out_unlock:
3201         spin_unlock_irq(&mchdev_lock);
3202
3203         return ret;
3204 }
3205 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3206
3207 /**
3208  * i915_gpu_raise - raise GPU frequency limit
3209  *
3210  * Raise the limit; IPS indicates we have thermal headroom.
3211  */
3212 bool i915_gpu_raise(void)
3213 {
3214         struct drm_i915_private *dev_priv;
3215         bool ret = true;
3216
3217         spin_lock_irq(&mchdev_lock);
3218         if (!i915_mch_dev) {
3219                 ret = false;
3220                 goto out_unlock;
3221         }
3222         dev_priv = i915_mch_dev;
3223
3224         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3225                 dev_priv->ips.max_delay--;
3226
3227 out_unlock:
3228         spin_unlock_irq(&mchdev_lock);
3229
3230         return ret;
3231 }
3232 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3233
3234 /**
3235  * i915_gpu_lower - lower GPU frequency limit
3236  *
3237  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3238  * frequency maximum.
3239  */
3240 bool i915_gpu_lower(void)
3241 {
3242         struct drm_i915_private *dev_priv;
3243         bool ret = true;
3244
3245         spin_lock_irq(&mchdev_lock);
3246         if (!i915_mch_dev) {
3247                 ret = false;
3248                 goto out_unlock;
3249         }
3250         dev_priv = i915_mch_dev;
3251
3252         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3253                 dev_priv->ips.max_delay++;
3254
3255 out_unlock:
3256         spin_unlock_irq(&mchdev_lock);
3257
3258         return ret;
3259 }
3260 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3261
3262 /**
3263  * i915_gpu_busy - indicate GPU business to IPS
3264  *
3265  * Tell the IPS driver whether or not the GPU is busy.
3266  */
3267 bool i915_gpu_busy(void)
3268 {
3269         struct drm_i915_private *dev_priv;
3270         struct intel_ring_buffer *ring;
3271         bool ret = false;
3272         int i;
3273
3274         spin_lock_irq(&mchdev_lock);
3275         if (!i915_mch_dev)
3276                 goto out_unlock;
3277         dev_priv = i915_mch_dev;
3278
3279         for_each_ring(ring, dev_priv, i)
3280                 ret |= !list_empty(&ring->request_list);
3281
3282 out_unlock:
3283         spin_unlock_irq(&mchdev_lock);
3284
3285         return ret;
3286 }
3287 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3288
3289 /**
3290  * i915_gpu_turbo_disable - disable graphics turbo
3291  *
3292  * Disable graphics turbo by resetting the max frequency and setting the
3293  * current frequency to the default.
3294  */
3295 bool i915_gpu_turbo_disable(void)
3296 {
3297         struct drm_i915_private *dev_priv;
3298         bool ret = true;
3299
3300         spin_lock_irq(&mchdev_lock);
3301         if (!i915_mch_dev) {
3302                 ret = false;
3303                 goto out_unlock;
3304         }
3305         dev_priv = i915_mch_dev;
3306
3307         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3308
3309         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3310                 ret = false;
3311
3312 out_unlock:
3313         spin_unlock_irq(&mchdev_lock);
3314
3315         return ret;
3316 }
3317 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3318
3319 /**
3320  * Tells the intel_ips driver that the i915 driver is now loaded, if
3321  * IPS got loaded first.
3322  *
3323  * This awkward dance is so that neither module has to depend on the
3324  * other in order for IPS to do the appropriate communication of
3325  * GPU turbo limits to i915.
3326  */
3327 static void
3328 ips_ping_for_i915_load(void)
3329 {
3330         void (*link)(void);
3331
3332         link = symbol_get(ips_link_to_i915_driver);
3333         if (link) {
3334                 link();
3335                 symbol_put(ips_link_to_i915_driver);
3336         }
3337 }
3338
3339 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3340 {
3341         /* We only register the i915 ips part with intel-ips once everything is
3342          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3343         spin_lock_irq(&mchdev_lock);
3344         i915_mch_dev = dev_priv;
3345         spin_unlock_irq(&mchdev_lock);
3346
3347         ips_ping_for_i915_load();
3348 }
3349
3350 void intel_gpu_ips_teardown(void)
3351 {
3352         spin_lock_irq(&mchdev_lock);
3353         i915_mch_dev = NULL;
3354         spin_unlock_irq(&mchdev_lock);
3355 }
3356 static void intel_init_emon(struct drm_device *dev)
3357 {
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         u32 lcfuse;
3360         u8 pxw[16];
3361         int i;
3362
3363         /* Disable to program */
3364         I915_WRITE(ECR, 0);
3365         POSTING_READ(ECR);
3366
3367         /* Program energy weights for various events */
3368         I915_WRITE(SDEW, 0x15040d00);
3369         I915_WRITE(CSIEW0, 0x007f0000);
3370         I915_WRITE(CSIEW1, 0x1e220004);
3371         I915_WRITE(CSIEW2, 0x04000004);
3372
3373         for (i = 0; i < 5; i++)
3374                 I915_WRITE(PEW + (i * 4), 0);
3375         for (i = 0; i < 3; i++)
3376                 I915_WRITE(DEW + (i * 4), 0);
3377
3378         /* Program P-state weights to account for frequency power adjustment */
3379         for (i = 0; i < 16; i++) {
3380                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3381                 unsigned long freq = intel_pxfreq(pxvidfreq);
3382                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3383                         PXVFREQ_PX_SHIFT;
3384                 unsigned long val;
3385
3386                 val = vid * vid;
3387                 val *= (freq / 1000);
3388                 val *= 255;
3389                 val /= (127*127*900);
3390                 if (val > 0xff)
3391                         DRM_ERROR("bad pxval: %ld\n", val);
3392                 pxw[i] = val;
3393         }
3394         /* Render standby states get 0 weight */
3395         pxw[14] = 0;
3396         pxw[15] = 0;
3397
3398         for (i = 0; i < 4; i++) {
3399                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3400                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3401                 I915_WRITE(PXW + (i * 4), val);
3402         }
3403
3404         /* Adjust magic regs to magic values (more experimental results) */
3405         I915_WRITE(OGW0, 0);
3406         I915_WRITE(OGW1, 0);
3407         I915_WRITE(EG0, 0x00007f00);
3408         I915_WRITE(EG1, 0x0000000e);
3409         I915_WRITE(EG2, 0x000e0000);
3410         I915_WRITE(EG3, 0x68000300);
3411         I915_WRITE(EG4, 0x42000000);
3412         I915_WRITE(EG5, 0x00140031);
3413         I915_WRITE(EG6, 0);
3414         I915_WRITE(EG7, 0);
3415
3416         for (i = 0; i < 8; i++)
3417                 I915_WRITE(PXWL + (i * 4), 0);
3418
3419         /* Enable PMON + select events */
3420         I915_WRITE(ECR, 0x80000019);
3421
3422         lcfuse = I915_READ(LCFUSE02);
3423
3424         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3425 }
3426
3427 void intel_disable_gt_powersave(struct drm_device *dev)
3428 {
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431         if (IS_IRONLAKE_M(dev)) {
3432                 ironlake_disable_drps(dev);
3433                 ironlake_disable_rc6(dev);
3434         } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3435                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3436                 mutex_lock(&dev_priv->rps.hw_lock);
3437                 gen6_disable_rps(dev);
3438                 mutex_unlock(&dev_priv->rps.hw_lock);
3439         }
3440 }
3441
3442 static void intel_gen6_powersave_work(struct work_struct *work)
3443 {
3444         struct drm_i915_private *dev_priv =
3445                 container_of(work, struct drm_i915_private,
3446                              rps.delayed_resume_work.work);
3447         struct drm_device *dev = dev_priv->dev;
3448
3449         mutex_lock(&dev_priv->rps.hw_lock);
3450         gen6_enable_rps(dev);
3451         gen6_update_ring_freq(dev);
3452         mutex_unlock(&dev_priv->rps.hw_lock);
3453 }
3454
3455 void intel_enable_gt_powersave(struct drm_device *dev)
3456 {
3457         struct drm_i915_private *dev_priv = dev->dev_private;
3458
3459         if (IS_IRONLAKE_M(dev)) {
3460                 ironlake_enable_drps(dev);
3461                 ironlake_enable_rc6(dev);
3462                 intel_init_emon(dev);
3463         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3464                 /*
3465                  * PCU communication is slow and this doesn't need to be
3466                  * done at any specific time, so do this out of our fast path
3467                  * to make resume and init faster.
3468                  */
3469                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3470                                       round_jiffies_up_relative(HZ));
3471         }
3472 }
3473
3474 static void ibx_init_clock_gating(struct drm_device *dev)
3475 {
3476         struct drm_i915_private *dev_priv = dev->dev_private;
3477
3478         /*
3479          * On Ibex Peak and Cougar Point, we need to disable clock
3480          * gating for the panel power sequencer or it will fail to
3481          * start up when no ports are active.
3482          */
3483         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3484 }
3485
3486 static void ironlake_init_clock_gating(struct drm_device *dev)
3487 {
3488         struct drm_i915_private *dev_priv = dev->dev_private;
3489         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3490
3491         /* Required for FBC */
3492         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3493                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3494                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3495
3496         I915_WRITE(PCH_3DCGDIS0,
3497                    MARIUNIT_CLOCK_GATE_DISABLE |
3498                    SVSMUNIT_CLOCK_GATE_DISABLE);
3499         I915_WRITE(PCH_3DCGDIS1,
3500                    VFMUNIT_CLOCK_GATE_DISABLE);
3501
3502         /*
3503          * According to the spec the following bits should be set in
3504          * order to enable memory self-refresh
3505          * The bit 22/21 of 0x42004
3506          * The bit 5 of 0x42020
3507          * The bit 15 of 0x45000
3508          */
3509         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3510                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3511                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3512         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3513         I915_WRITE(DISP_ARB_CTL,
3514                    (I915_READ(DISP_ARB_CTL) |
3515                     DISP_FBC_WM_DIS));
3516         I915_WRITE(WM3_LP_ILK, 0);
3517         I915_WRITE(WM2_LP_ILK, 0);
3518         I915_WRITE(WM1_LP_ILK, 0);
3519
3520         /*
3521          * Based on the document from hardware guys the following bits
3522          * should be set unconditionally in order to enable FBC.
3523          * The bit 22 of 0x42000
3524          * The bit 22 of 0x42004
3525          * The bit 7,8,9 of 0x42020.
3526          */
3527         if (IS_IRONLAKE_M(dev)) {
3528                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3529                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3530                            ILK_FBCQ_DIS);
3531                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3532                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3533                            ILK_DPARB_GATE);
3534         }
3535
3536         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3537
3538         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3539                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3540                    ILK_ELPIN_409_SELECT);
3541         I915_WRITE(_3D_CHICKEN2,
3542                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3543                    _3D_CHICKEN2_WM_READ_PIPELINED);
3544
3545         /* WaDisableRenderCachePipelinedFlush */
3546         I915_WRITE(CACHE_MODE_0,
3547                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3548
3549         ibx_init_clock_gating(dev);
3550 }
3551
3552 static void cpt_init_clock_gating(struct drm_device *dev)
3553 {
3554         struct drm_i915_private *dev_priv = dev->dev_private;
3555         int pipe;
3556
3557         /*
3558          * On Ibex Peak and Cougar Point, we need to disable clock
3559          * gating for the panel power sequencer or it will fail to
3560          * start up when no ports are active.
3561          */
3562         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3563         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3564                    DPLS_EDP_PPS_FIX_DIS);
3565         /* The below fixes the weird display corruption, a few pixels shifted
3566          * downward, on (only) LVDS of some HP laptops with IVY.
3567          */
3568         for_each_pipe(pipe)
3569                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3570         /* WADP0ClockGatingDisable */
3571         for_each_pipe(pipe) {
3572                 I915_WRITE(TRANS_CHICKEN1(pipe),
3573                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3574         }
3575 }
3576
3577 static void gen6_init_clock_gating(struct drm_device *dev)
3578 {
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         int pipe;
3581         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3582
3583         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3584
3585         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3586                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3587                    ILK_ELPIN_409_SELECT);
3588
3589         /* WaDisableHiZPlanesWhenMSAAEnabled */
3590         I915_WRITE(_3D_CHICKEN,
3591                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3592
3593         /* WaSetupGtModeTdRowDispatch */
3594         if (IS_SNB_GT1(dev))
3595                 I915_WRITE(GEN6_GT_MODE,
3596                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3597
3598         I915_WRITE(WM3_LP_ILK, 0);
3599         I915_WRITE(WM2_LP_ILK, 0);
3600         I915_WRITE(WM1_LP_ILK, 0);
3601
3602         I915_WRITE(CACHE_MODE_0,
3603                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3604
3605         I915_WRITE(GEN6_UCGCTL1,
3606                    I915_READ(GEN6_UCGCTL1) |
3607                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3608                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3609
3610         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3611          * gating disable must be set.  Failure to set it results in
3612          * flickering pixels due to Z write ordering failures after
3613          * some amount of runtime in the Mesa "fire" demo, and Unigine
3614          * Sanctuary and Tropics, and apparently anything else with
3615          * alpha test or pixel discard.
3616          *
3617          * According to the spec, bit 11 (RCCUNIT) must also be set,
3618          * but we didn't debug actual testcases to find it out.
3619          *
3620          * Also apply WaDisableVDSUnitClockGating and
3621          * WaDisableRCPBUnitClockGating.
3622          */
3623         I915_WRITE(GEN6_UCGCTL2,
3624                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3625                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3626                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3627
3628         /* Bspec says we need to always set all mask bits. */
3629         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3630                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3631
3632         /*
3633          * According to the spec the following bits should be
3634          * set in order to enable memory self-refresh and fbc:
3635          * The bit21 and bit22 of 0x42000
3636          * The bit21 and bit22 of 0x42004
3637          * The bit5 and bit7 of 0x42020
3638          * The bit14 of 0x70180
3639          * The bit14 of 0x71180
3640          */
3641         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3642                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3643                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3644         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3645                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3646                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3647         I915_WRITE(ILK_DSPCLK_GATE_D,
3648                    I915_READ(ILK_DSPCLK_GATE_D) |
3649                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3650                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3651
3652         /* WaMbcDriverBootEnable */
3653         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3654                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3655
3656         for_each_pipe(pipe) {
3657                 I915_WRITE(DSPCNTR(pipe),
3658                            I915_READ(DSPCNTR(pipe)) |
3659                            DISPPLANE_TRICKLE_FEED_DISABLE);
3660                 intel_flush_display_plane(dev_priv, pipe);
3661         }
3662
3663         /* The default value should be 0x200 according to docs, but the two
3664          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3665         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3666         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3667
3668         cpt_init_clock_gating(dev);
3669 }
3670
3671 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3672 {
3673         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3674
3675         reg &= ~GEN7_FF_SCHED_MASK;
3676         reg |= GEN7_FF_TS_SCHED_HW;
3677         reg |= GEN7_FF_VS_SCHED_HW;
3678         reg |= GEN7_FF_DS_SCHED_HW;
3679
3680         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3681 }
3682
3683 static void lpt_init_clock_gating(struct drm_device *dev)
3684 {
3685         struct drm_i915_private *dev_priv = dev->dev_private;
3686
3687         /*
3688          * TODO: this bit should only be enabled when really needed, then
3689          * disabled when not needed anymore in order to save power.
3690          */
3691         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3692                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3693                            I915_READ(SOUTH_DSPCLK_GATE_D) |
3694                            PCH_LP_PARTITION_LEVEL_DISABLE);
3695 }
3696
3697 static void haswell_init_clock_gating(struct drm_device *dev)
3698 {
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700         int pipe;
3701
3702         I915_WRITE(WM3_LP_ILK, 0);
3703         I915_WRITE(WM2_LP_ILK, 0);
3704         I915_WRITE(WM1_LP_ILK, 0);
3705
3706         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3707          * This implements the WaDisableRCZUnitClockGating workaround.
3708          */
3709         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3710
3711         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3712         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3713                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3714
3715         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3716         I915_WRITE(GEN7_L3CNTLREG1,
3717                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3718         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3719                         GEN7_WA_L3_CHICKEN_MODE);
3720
3721         /* This is required by WaCatErrorRejectionIssue */
3722         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3723                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3724                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3725
3726         for_each_pipe(pipe) {
3727                 I915_WRITE(DSPCNTR(pipe),
3728                            I915_READ(DSPCNTR(pipe)) |
3729                            DISPPLANE_TRICKLE_FEED_DISABLE);
3730                 intel_flush_display_plane(dev_priv, pipe);
3731         }
3732
3733         gen7_setup_fixed_func_scheduler(dev_priv);
3734
3735         /* WaDisable4x2SubspanOptimization */
3736         I915_WRITE(CACHE_MODE_1,
3737                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3738
3739         /* WaMbcDriverBootEnable */
3740         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3741                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3742
3743         /* XXX: This is a workaround for early silicon revisions and should be
3744          * removed later.
3745          */
3746         I915_WRITE(WM_DBG,
3747                         I915_READ(WM_DBG) |
3748                         WM_DBG_DISALLOW_MULTIPLE_LP |
3749                         WM_DBG_DISALLOW_SPRITE |
3750                         WM_DBG_DISALLOW_MAXFIFO);
3751
3752         lpt_init_clock_gating(dev);
3753 }
3754
3755 static void ivybridge_init_clock_gating(struct drm_device *dev)
3756 {
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758         int pipe;
3759         uint32_t snpcr;
3760
3761         I915_WRITE(WM3_LP_ILK, 0);
3762         I915_WRITE(WM2_LP_ILK, 0);
3763         I915_WRITE(WM1_LP_ILK, 0);
3764
3765         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3766
3767         /* WaDisableEarlyCull */
3768         I915_WRITE(_3D_CHICKEN3,
3769                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3770
3771         /* WaDisableBackToBackFlipFix */
3772         I915_WRITE(IVB_CHICKEN3,
3773                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3774                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3775
3776         /* WaDisablePSDDualDispatchEnable */
3777         if (IS_IVB_GT1(dev))
3778                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3779                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3780         else
3781                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3782                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3783
3784         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3785         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3786                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3787
3788         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3789         I915_WRITE(GEN7_L3CNTLREG1,
3790                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3791         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3792                    GEN7_WA_L3_CHICKEN_MODE);
3793         if (IS_IVB_GT1(dev))
3794                 I915_WRITE(GEN7_ROW_CHICKEN2,
3795                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3796         else
3797                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3798                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3799
3800
3801         /* WaForceL3Serialization */
3802         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3803                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3804
3805         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3806          * gating disable must be set.  Failure to set it results in
3807          * flickering pixels due to Z write ordering failures after
3808          * some amount of runtime in the Mesa "fire" demo, and Unigine
3809          * Sanctuary and Tropics, and apparently anything else with
3810          * alpha test or pixel discard.
3811          *
3812          * According to the spec, bit 11 (RCCUNIT) must also be set,
3813          * but we didn't debug actual testcases to find it out.
3814          *
3815          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3816          * This implements the WaDisableRCZUnitClockGating workaround.
3817          */
3818         I915_WRITE(GEN6_UCGCTL2,
3819                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3820                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3821
3822         /* This is required by WaCatErrorRejectionIssue */
3823         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3824                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3825                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3826
3827         for_each_pipe(pipe) {
3828                 I915_WRITE(DSPCNTR(pipe),
3829                            I915_READ(DSPCNTR(pipe)) |
3830                            DISPPLANE_TRICKLE_FEED_DISABLE);
3831                 intel_flush_display_plane(dev_priv, pipe);
3832         }
3833
3834         /* WaMbcDriverBootEnable */
3835         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3836                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3837
3838         gen7_setup_fixed_func_scheduler(dev_priv);
3839
3840         /* WaDisable4x2SubspanOptimization */
3841         I915_WRITE(CACHE_MODE_1,
3842                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3843
3844         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3845         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3846         snpcr |= GEN6_MBC_SNPCR_MED;
3847         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3848
3849         cpt_init_clock_gating(dev);
3850 }
3851
3852 static void valleyview_init_clock_gating(struct drm_device *dev)
3853 {
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         int pipe;
3856
3857         I915_WRITE(WM3_LP_ILK, 0);
3858         I915_WRITE(WM2_LP_ILK, 0);
3859         I915_WRITE(WM1_LP_ILK, 0);
3860
3861         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3862
3863         /* WaDisableEarlyCull */
3864         I915_WRITE(_3D_CHICKEN3,
3865                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3866
3867         /* WaDisableBackToBackFlipFix */
3868         I915_WRITE(IVB_CHICKEN3,
3869                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3870                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
3871
3872         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3873                    _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3874
3875         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3876         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3877                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3878
3879         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3880         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3881         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3882
3883         /* WaForceL3Serialization */
3884         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3885                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3886
3887         /* WaDisableDopClockGating */
3888         I915_WRITE(GEN7_ROW_CHICKEN2,
3889                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3890
3891         /* WaForceL3Serialization */
3892         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3893                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3894
3895         /* This is required by WaCatErrorRejectionIssue */
3896         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3897                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3898                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3899
3900         /* WaMbcDriverBootEnable */
3901         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3902                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3903
3904
3905         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3906          * gating disable must be set.  Failure to set it results in
3907          * flickering pixels due to Z write ordering failures after
3908          * some amount of runtime in the Mesa "fire" demo, and Unigine
3909          * Sanctuary and Tropics, and apparently anything else with
3910          * alpha test or pixel discard.
3911          *
3912          * According to the spec, bit 11 (RCCUNIT) must also be set,
3913          * but we didn't debug actual testcases to find it out.
3914          *
3915          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3916          * This implements the WaDisableRCZUnitClockGating workaround.
3917          *
3918          * Also apply WaDisableVDSUnitClockGating and
3919          * WaDisableRCPBUnitClockGating.
3920          */
3921         I915_WRITE(GEN6_UCGCTL2,
3922                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3923                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3924                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3925                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3926                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3927
3928         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3929
3930         for_each_pipe(pipe) {
3931                 I915_WRITE(DSPCNTR(pipe),
3932                            I915_READ(DSPCNTR(pipe)) |
3933                            DISPPLANE_TRICKLE_FEED_DISABLE);
3934                 intel_flush_display_plane(dev_priv, pipe);
3935         }
3936
3937         I915_WRITE(CACHE_MODE_1,
3938                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3939
3940         /*
3941          * On ValleyView, the GUnit needs to signal the GT
3942          * when flip and other events complete.  So enable
3943          * all the GUnit->GT interrupts here
3944          */
3945         I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3946                    PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3947                    SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3948                    PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3949                    PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3950                    SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3951                    PLANEA_FLIPDONE_INT_EN);
3952
3953         /*
3954          * WaDisableVLVClockGating_VBIIssue
3955          * Disable clock gating on th GCFG unit to prevent a delay
3956          * in the reporting of vblank events.
3957          */
3958         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3959 }
3960
3961 static void g4x_init_clock_gating(struct drm_device *dev)
3962 {
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         uint32_t dspclk_gate;
3965
3966         I915_WRITE(RENCLK_GATE_D1, 0);
3967         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3968                    GS_UNIT_CLOCK_GATE_DISABLE |
3969                    CL_UNIT_CLOCK_GATE_DISABLE);
3970         I915_WRITE(RAMCLK_GATE_D, 0);
3971         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3972                 OVRUNIT_CLOCK_GATE_DISABLE |
3973                 OVCUNIT_CLOCK_GATE_DISABLE;
3974         if (IS_GM45(dev))
3975                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3976         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3977
3978         /* WaDisableRenderCachePipelinedFlush */
3979         I915_WRITE(CACHE_MODE_0,
3980                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3981 }
3982
3983 static void crestline_init_clock_gating(struct drm_device *dev)
3984 {
3985         struct drm_i915_private *dev_priv = dev->dev_private;
3986
3987         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3988         I915_WRITE(RENCLK_GATE_D2, 0);
3989         I915_WRITE(DSPCLK_GATE_D, 0);
3990         I915_WRITE(RAMCLK_GATE_D, 0);
3991         I915_WRITE16(DEUC, 0);
3992 }
3993
3994 static void broadwater_init_clock_gating(struct drm_device *dev)
3995 {
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997
3998         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3999                    I965_RCC_CLOCK_GATE_DISABLE |
4000                    I965_RCPB_CLOCK_GATE_DISABLE |
4001                    I965_ISC_CLOCK_GATE_DISABLE |
4002                    I965_FBC_CLOCK_GATE_DISABLE);
4003         I915_WRITE(RENCLK_GATE_D2, 0);
4004 }
4005
4006 static void gen3_init_clock_gating(struct drm_device *dev)
4007 {
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         u32 dstate = I915_READ(D_STATE);
4010
4011         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4012                 DSTATE_DOT_CLOCK_GATING;
4013         I915_WRITE(D_STATE, dstate);
4014
4015         if (IS_PINEVIEW(dev))
4016                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4017
4018         /* IIR "flip pending" means done if this bit is set */
4019         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4020 }
4021
4022 static void i85x_init_clock_gating(struct drm_device *dev)
4023 {
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025
4026         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4027 }
4028
4029 static void i830_init_clock_gating(struct drm_device *dev)
4030 {
4031         struct drm_i915_private *dev_priv = dev->dev_private;
4032
4033         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4034 }
4035
4036 void intel_init_clock_gating(struct drm_device *dev)
4037 {
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039
4040         dev_priv->display.init_clock_gating(dev);
4041 }
4042
4043 /* Starting with Haswell, we have different power wells for
4044  * different parts of the GPU. This attempts to enable them all.
4045  */
4046 void intel_init_power_wells(struct drm_device *dev)
4047 {
4048         struct drm_i915_private *dev_priv = dev->dev_private;
4049         unsigned long power_wells[] = {
4050                 HSW_PWR_WELL_CTL1,
4051                 HSW_PWR_WELL_CTL2,
4052                 HSW_PWR_WELL_CTL4
4053         };
4054         int i;
4055
4056         if (!IS_HASWELL(dev))
4057                 return;
4058
4059         mutex_lock(&dev->struct_mutex);
4060
4061         for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4062                 int well = I915_READ(power_wells[i]);
4063
4064                 if ((well & HSW_PWR_WELL_STATE) == 0) {
4065                         I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
4066                         if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
4067                                 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4068                 }
4069         }
4070
4071         mutex_unlock(&dev->struct_mutex);
4072 }
4073
4074 /* Set up chip specific power management-related functions */
4075 void intel_init_pm(struct drm_device *dev)
4076 {
4077         struct drm_i915_private *dev_priv = dev->dev_private;
4078
4079         if (I915_HAS_FBC(dev)) {
4080                 if (HAS_PCH_SPLIT(dev)) {
4081                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4082                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
4083                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4084                 } else if (IS_GM45(dev)) {
4085                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4086                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4087                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4088                 } else if (IS_CRESTLINE(dev)) {
4089                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4090                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4091                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4092                 }
4093                 /* 855GM needs testing */
4094         }
4095
4096         /* For cxsr */
4097         if (IS_PINEVIEW(dev))
4098                 i915_pineview_get_mem_freq(dev);
4099         else if (IS_GEN5(dev))
4100                 i915_ironlake_get_mem_freq(dev);
4101
4102         /* For FIFO watermark updates */
4103         if (HAS_PCH_SPLIT(dev)) {
4104                 if (IS_GEN5(dev)) {
4105                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4106                                 dev_priv->display.update_wm = ironlake_update_wm;
4107                         else {
4108                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4109                                               "Disable CxSR\n");
4110                                 dev_priv->display.update_wm = NULL;
4111                         }
4112                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4113                 } else if (IS_GEN6(dev)) {
4114                         if (SNB_READ_WM0_LATENCY()) {
4115                                 dev_priv->display.update_wm = sandybridge_update_wm;
4116                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4117                         } else {
4118                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4119                                               "Disable CxSR\n");
4120                                 dev_priv->display.update_wm = NULL;
4121                         }
4122                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4123                 } else if (IS_IVYBRIDGE(dev)) {
4124                         /* FIXME: detect B0+ stepping and use auto training */
4125                         if (SNB_READ_WM0_LATENCY()) {
4126                                 dev_priv->display.update_wm = ivybridge_update_wm;
4127                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4128                         } else {
4129                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4130                                               "Disable CxSR\n");
4131                                 dev_priv->display.update_wm = NULL;
4132                         }
4133                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4134                 } else if (IS_HASWELL(dev)) {
4135                         if (SNB_READ_WM0_LATENCY()) {
4136                                 dev_priv->display.update_wm = sandybridge_update_wm;
4137                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4138                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4139                         } else {
4140                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4141                                               "Disable CxSR\n");
4142                                 dev_priv->display.update_wm = NULL;
4143                         }
4144                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4145                 } else
4146                         dev_priv->display.update_wm = NULL;
4147         } else if (IS_VALLEYVIEW(dev)) {
4148                 dev_priv->display.update_wm = valleyview_update_wm;
4149                 dev_priv->display.init_clock_gating =
4150                         valleyview_init_clock_gating;
4151         } else if (IS_PINEVIEW(dev)) {
4152                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4153                                             dev_priv->is_ddr3,
4154                                             dev_priv->fsb_freq,
4155                                             dev_priv->mem_freq)) {
4156                         DRM_INFO("failed to find known CxSR latency "
4157                                  "(found ddr%s fsb freq %d, mem freq %d), "
4158                                  "disabling CxSR\n",
4159                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4160                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4161                         /* Disable CxSR and never update its watermark again */
4162                         pineview_disable_cxsr(dev);
4163                         dev_priv->display.update_wm = NULL;
4164                 } else
4165                         dev_priv->display.update_wm = pineview_update_wm;
4166                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4167         } else if (IS_G4X(dev)) {
4168                 dev_priv->display.update_wm = g4x_update_wm;
4169                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4170         } else if (IS_GEN4(dev)) {
4171                 dev_priv->display.update_wm = i965_update_wm;
4172                 if (IS_CRESTLINE(dev))
4173                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4174                 else if (IS_BROADWATER(dev))
4175                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4176         } else if (IS_GEN3(dev)) {
4177                 dev_priv->display.update_wm = i9xx_update_wm;
4178                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4179                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4180         } else if (IS_I865G(dev)) {
4181                 dev_priv->display.update_wm = i830_update_wm;
4182                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4183                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4184         } else if (IS_I85X(dev)) {
4185                 dev_priv->display.update_wm = i9xx_update_wm;
4186                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4187                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4188         } else {
4189                 dev_priv->display.update_wm = i830_update_wm;
4190                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4191                 if (IS_845G(dev))
4192                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4193                 else
4194                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4195         }
4196 }
4197
4198 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4199 {
4200         u32 gt_thread_status_mask;
4201
4202         if (IS_HASWELL(dev_priv->dev))
4203                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4204         else
4205                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4206
4207         /* w/a for a sporadic read returning 0 by waiting for the GT
4208          * thread to wake up.
4209          */
4210         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4211                 DRM_ERROR("GT thread status wait timed out\n");
4212 }
4213
4214 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4215 {
4216         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4217         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4218 }
4219
4220 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4221 {
4222         u32 forcewake_ack;
4223
4224         if (IS_HASWELL(dev_priv->dev))
4225                 forcewake_ack = FORCEWAKE_ACK_HSW;
4226         else
4227                 forcewake_ack = FORCEWAKE_ACK;
4228
4229         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4230                             FORCEWAKE_ACK_TIMEOUT_MS))
4231                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4232
4233         I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4234         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4235
4236         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4237                             FORCEWAKE_ACK_TIMEOUT_MS))
4238                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4239
4240         __gen6_gt_wait_for_thread_c0(dev_priv);
4241 }
4242
4243 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4244 {
4245         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4246         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4247 }
4248
4249 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4250 {
4251         u32 forcewake_ack;
4252
4253         if (IS_HASWELL(dev_priv->dev))
4254                 forcewake_ack = FORCEWAKE_ACK_HSW;
4255         else
4256                 forcewake_ack = FORCEWAKE_MT_ACK;
4257
4258         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4259                             FORCEWAKE_ACK_TIMEOUT_MS))
4260                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4261
4262         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4263         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4264
4265         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4266                             FORCEWAKE_ACK_TIMEOUT_MS))
4267                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4268
4269         __gen6_gt_wait_for_thread_c0(dev_priv);
4270 }
4271
4272 /*
4273  * Generally this is called implicitly by the register read function. However,
4274  * if some sequence requires the GT to not power down then this function should
4275  * be called at the beginning of the sequence followed by a call to
4276  * gen6_gt_force_wake_put() at the end of the sequence.
4277  */
4278 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4279 {
4280         unsigned long irqflags;
4281
4282         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4283         if (dev_priv->forcewake_count++ == 0)
4284                 dev_priv->gt.force_wake_get(dev_priv);
4285         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4286 }
4287
4288 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4289 {
4290         u32 gtfifodbg;
4291         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4292         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4293              "MMIO read or write has been dropped %x\n", gtfifodbg))
4294                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4295 }
4296
4297 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4298 {
4299         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4300         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4301         gen6_gt_check_fifodbg(dev_priv);
4302 }
4303
4304 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4305 {
4306         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4307         /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
4308         gen6_gt_check_fifodbg(dev_priv);
4309 }
4310
4311 /*
4312  * see gen6_gt_force_wake_get()
4313  */
4314 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4315 {
4316         unsigned long irqflags;
4317
4318         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4319         if (--dev_priv->forcewake_count == 0)
4320                 dev_priv->gt.force_wake_put(dev_priv);
4321         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4322 }
4323
4324 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4325 {
4326         int ret = 0;
4327
4328         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4329                 int loop = 500;
4330                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4331                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4332                         udelay(10);
4333                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4334                 }
4335                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4336                         ++ret;
4337                 dev_priv->gt_fifo_count = fifo;
4338         }
4339         dev_priv->gt_fifo_count--;
4340
4341         return ret;
4342 }
4343
4344 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4345 {
4346         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4347 }
4348
4349 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4350 {
4351         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4352                             FORCEWAKE_ACK_TIMEOUT_MS))
4353                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4354
4355         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4356
4357         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4358                             FORCEWAKE_ACK_TIMEOUT_MS))
4359                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4360
4361         __gen6_gt_wait_for_thread_c0(dev_priv);
4362 }
4363
4364 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4365 {
4366         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4367         /* The below doubles as a POSTING_READ */
4368         gen6_gt_check_fifodbg(dev_priv);
4369 }
4370
4371 void intel_gt_reset(struct drm_device *dev)
4372 {
4373         struct drm_i915_private *dev_priv = dev->dev_private;
4374
4375         if (IS_VALLEYVIEW(dev)) {
4376                 vlv_force_wake_reset(dev_priv);
4377         } else if (INTEL_INFO(dev)->gen >= 6) {
4378                 __gen6_gt_force_wake_reset(dev_priv);
4379                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4380                         __gen6_gt_force_wake_mt_reset(dev_priv);
4381         }
4382 }
4383
4384 void intel_gt_init(struct drm_device *dev)
4385 {
4386         struct drm_i915_private *dev_priv = dev->dev_private;
4387
4388         spin_lock_init(&dev_priv->gt_lock);
4389
4390         intel_gt_reset(dev);
4391
4392         if (IS_VALLEYVIEW(dev)) {
4393                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4394                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4395         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4396                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4397                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4398         } else if (IS_GEN6(dev)) {
4399                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4400                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4401         }
4402         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4403                           intel_gen6_powersave_work);
4404 }
4405
4406 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4407 {
4408         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4409
4410         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4411                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4412                 return -EAGAIN;
4413         }
4414
4415         I915_WRITE(GEN6_PCODE_DATA, *val);
4416         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4417
4418         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4419                      500)) {
4420                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4421                 return -ETIMEDOUT;
4422         }
4423
4424         *val = I915_READ(GEN6_PCODE_DATA);
4425         I915_WRITE(GEN6_PCODE_DATA, 0);
4426
4427         return 0;
4428 }
4429
4430 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4431 {
4432         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4433
4434         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4435                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4436                 return -EAGAIN;
4437         }
4438
4439         I915_WRITE(GEN6_PCODE_DATA, val);
4440         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4441
4442         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4443                      500)) {
4444                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4445                 return -ETIMEDOUT;
4446         }
4447
4448         I915_WRITE(GEN6_PCODE_DATA, 0);
4449
4450         return 0;
4451 }