drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/i915_powerwell.h>
  35 #include <linux/pm_runtime.h>
  36
  37 /**
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  59  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  60  * during in-memory transfers and, therefore, reduce the power packet.
  61  *
  62  * The benefits of FBC are mostly visible with solid backgrounds and
  63  * variation-less patterns.
  64  *
  65  * FBC-related functionality can be enabled by the means of the
  66  * i915.i915_enable_fbc parameter
  67  */
  68
  69 static void i8xx_disable_fbc(struct drm_device *dev)
  70 {
  71         struct drm_i915_private *dev_priv = dev->dev_private;
  72         u32 fbc_ctl;
  73
  74         /* Disable compression */
  75         fbc_ctl = I915_READ(FBC_CONTROL);
  76         if ((fbc_ctl & FBC_CTL_EN) == 0)
  77                 return;
  78
  79         fbc_ctl &= ~FBC_CTL_EN;
  80         I915_WRITE(FBC_CONTROL, fbc_ctl);
  81
  82         /* Wait for compressing bit to clear */
  83         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  84                 DRM_DEBUG_KMS("FBC idle timed out\n");
  85                 return;
  86         }
  87
  88         DRM_DEBUG_KMS("disabled FBC\n");
  89 }
  90
  91 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct drm_i915_private *dev_priv = dev->dev_private;
  95         struct drm_framebuffer *fb = crtc->primary->fb;
  96         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  97         struct drm_i915_gem_object *obj = intel_fb->obj;
  98         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  99         int cfb_pitch;
 100         int i;
 101         u32 fbc_ctl;
 102
 103         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 104         if (fb->pitches[0] < cfb_pitch)
 105                 cfb_pitch = fb->pitches[0];
 106
 107         /* FBC_CTL wants 32B or 64B units */
 108         if (IS_GEN2(dev))
 109                 cfb_pitch = (cfb_pitch / 32) - 1;
 110         else
 111                 cfb_pitch = (cfb_pitch / 64) - 1;
 112
 113         /* Clear old tags */
 114         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 115                 I915_WRITE(FBC_TAG + (i * 4), 0);
 116
 117         if (IS_GEN4(dev)) {
 118                 u32 fbc_ctl2;
 119
 120                 /* Set it up... */
 121                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 122                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 123                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 124                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 125         }
 126
 127         /* enable it... */
 128         fbc_ctl = I915_READ(FBC_CONTROL);
 129         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 130         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 131         if (IS_I945GM(dev))
 132                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 133         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 134         fbc_ctl |= obj->fence_reg;
 135         I915_WRITE(FBC_CONTROL, fbc_ctl);
 136
 137         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 138                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 139 }
 140
 141 static bool i8xx_fbc_enabled(struct drm_device *dev)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144
 145         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 146 }
 147
 148 static void g4x_enable_fbc(struct drm_crtc *crtc)
 149 {
 150         struct drm_device *dev = crtc->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         struct drm_framebuffer *fb = crtc->primary->fb;
 153         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 154         struct drm_i915_gem_object *obj = intel_fb->obj;
 155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 156         u32 dpfc_ctl;
 157
 158         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 159         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 160                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 161         else
 162                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 163         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 164
 165         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 166
 167         /* enable it... */
 168         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 169
 170         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 171 }
 172
 173 static void g4x_disable_fbc(struct drm_device *dev)
 174 {
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         u32 dpfc_ctl;
 177
 178         /* Disable compression */
 179         dpfc_ctl = I915_READ(DPFC_CONTROL);
 180         if (dpfc_ctl & DPFC_CTL_EN) {
 181                 dpfc_ctl &= ~DPFC_CTL_EN;
 182                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 183
 184                 DRM_DEBUG_KMS("disabled FBC\n");
 185         }
 186 }
 187
 188 static bool g4x_fbc_enabled(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 193 }
 194
 195 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         u32 blt_ecoskpd;
 199
 200         /* Make sure blitter notifies FBC of writes */
 201
 202         /* Blitter is part of Media powerwell on VLV. No impact of
 203          * his param in other platforms for now */
 204         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 205
 206         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 208                 GEN6_BLITTER_LOCK_SHIFT;
 209         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 210         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 213                          GEN6_BLITTER_LOCK_SHIFT);
 214         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 215         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 216
 217         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 218 }
 219
 220 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 221 {
 222         struct drm_device *dev = crtc->dev;
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         struct drm_framebuffer *fb = crtc->primary->fb;
 225         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 226         struct drm_i915_gem_object *obj = intel_fb->obj;
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 228         u32 dpfc_ctl;
 229
 230         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 231         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 233         else
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 236         if (IS_GEN5(dev))
 237                 dpfc_ctl |= obj->fence_reg;
 238
 239         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 240         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 241         /* enable it... */
 242         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 243
 244         if (IS_GEN6(dev)) {
 245                 I915_WRITE(SNB_DPFC_CTL_SA,
 246                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 247                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 248                 sandybridge_blit_fbc_update(dev);
 249         }
 250
 251         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 252 }
 253
 254 static void ironlake_disable_fbc(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         u32 dpfc_ctl;
 258
 259         /* Disable compression */
 260         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 261         if (dpfc_ctl & DPFC_CTL_EN) {
 262                 dpfc_ctl &= ~DPFC_CTL_EN;
 263                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 264
 265                 DRM_DEBUG_KMS("disabled FBC\n");
 266         }
 267 }
 268
 269 static bool ironlake_fbc_enabled(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 274 }
 275
 276 static void gen7_enable_fbc(struct drm_crtc *crtc)
 277 {
 278         struct drm_device *dev = crtc->dev;
 279         struct drm_i915_private *dev_priv = dev->dev_private;
 280         struct drm_framebuffer *fb = crtc->primary->fb;
 281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 282         struct drm_i915_gem_object *obj = intel_fb->obj;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 dpfc_ctl;
 285
 286         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 287         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 288                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 289         else
 290                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 291         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 292
 293         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 294
 295         if (IS_IVYBRIDGE(dev)) {
 296                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 297                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 298                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 299                            ILK_FBCQ_DIS);
 300         } else {
 301                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 302                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 303                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 304                            HSW_FBCQ_DIS);
 305         }
 306
 307         I915_WRITE(SNB_DPFC_CTL_SA,
 308                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 309         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 310
 311         sandybridge_blit_fbc_update(dev);
 312
 313         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 314 }
 315
 316 bool intel_fbc_enabled(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         if (!dev_priv->display.fbc_enabled)
 321                 return false;
 322
 323         return dev_priv->display.fbc_enabled(dev);
 324 }
 325
 326 static void intel_fbc_work_fn(struct work_struct *__work)
 327 {
 328         struct intel_fbc_work *work =
 329                 container_of(to_delayed_work(__work),
 330                              struct intel_fbc_work, work);
 331         struct drm_device *dev = work->crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333
 334         mutex_lock(&dev->struct_mutex);
 335         if (work == dev_priv->fbc.fbc_work) {
 336                 /* Double check that we haven't switched fb without cancelling
 337                  * the prior work.
 338                  */
 339                 if (work->crtc->primary->fb == work->fb) {
 340                         dev_priv->display.enable_fbc(work->crtc);
 341
 342                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 343                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 344                         dev_priv->fbc.y = work->crtc->y;
 345                 }
 346
 347                 dev_priv->fbc.fbc_work = NULL;
 348         }
 349         mutex_unlock(&dev->struct_mutex);
 350
 351         kfree(work);
 352 }
 353
 354 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 355 {
 356         if (dev_priv->fbc.fbc_work == NULL)
 357                 return;
 358
 359         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 360
 361         /* Synchronisation is provided by struct_mutex and checking of
 362          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 363          * entirely asynchronously.
 364          */
 365         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 366                 /* tasklet was killed before being run, clean up */
 367                 kfree(dev_priv->fbc.fbc_work);
 368
 369         /* Mark the work as no longer wanted so that if it does
 370          * wake-up (because the work was already running and waiting
 371          * for our mutex), it will discover that is no longer
 372          * necessary to run.
 373          */
 374         dev_priv->fbc.fbc_work = NULL;
 375 }
 376
 377 static void intel_enable_fbc(struct drm_crtc *crtc)
 378 {
 379         struct intel_fbc_work *work;
 380         struct drm_device *dev = crtc->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382
 383         if (!dev_priv->display.enable_fbc)
 384                 return;
 385
 386         intel_cancel_fbc_work(dev_priv);
 387
 388         work = kzalloc(sizeof(*work), GFP_KERNEL);
 389         if (work == NULL) {
 390                 DRM_ERROR("Failed to allocate FBC work structure\n");
 391                 dev_priv->display.enable_fbc(crtc);
 392                 return;
 393         }
 394
 395         work->crtc = crtc;
 396         work->fb = crtc->primary->fb;
 397         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 398
 399         dev_priv->fbc.fbc_work = work;
 400
 401         /* Delay the actual enabling to let pageflipping cease and the
 402          * display to settle before starting the compression. Note that
 403          * this delay also serves a second purpose: it allows for a
 404          * vblank to pass after disabling the FBC before we attempt
 405          * to modify the control registers.
 406          *
 407          * A more complicated solution would involve tracking vblanks
 408          * following the termination of the page-flipping sequence
 409          * and indeed performing the enable as a co-routine and not
 410          * waiting synchronously upon the vblank.
 411          *
 412          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 413          */
 414         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 415 }
 416
 417 void intel_disable_fbc(struct drm_device *dev)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420
 421         intel_cancel_fbc_work(dev_priv);
 422
 423         if (!dev_priv->display.disable_fbc)
 424                 return;
 425
 426         dev_priv->display.disable_fbc(dev);
 427         dev_priv->fbc.plane = -1;
 428 }
 429
 430 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 431                               enum no_fbc_reason reason)
 432 {
 433         if (dev_priv->fbc.no_fbc_reason == reason)
 434                 return false;
 435
 436         dev_priv->fbc.no_fbc_reason = reason;
 437         return true;
 438 }
 439
 440 /**
 441  * intel_update_fbc - enable/disable FBC as needed
 442  * @dev: the drm_device
 443  *
 444  * Set up the framebuffer compression hardware at mode set time.  We
 445  * enable it if possible:
 446  *   - plane A only (on pre-965)
 447  *   - no pixel mulitply/line duplication
 448  *   - no alpha buffer discard
 449  *   - no dual wide
 450  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 451  *
 452  * We can't assume that any compression will take place (worst case),
 453  * so the compressed buffer has to be the same size as the uncompressed
 454  * one.  It also must reside (along with the line length buffer) in
 455  * stolen memory.
 456  *
 457  * We need to enable/disable FBC on a global basis.
 458  */
 459 void intel_update_fbc(struct drm_device *dev)
 460 {
 461         struct drm_i915_private *dev_priv = dev->dev_private;
 462         struct drm_crtc *crtc = NULL, *tmp_crtc;
 463         struct intel_crtc *intel_crtc;
 464         struct drm_framebuffer *fb;
 465         struct intel_framebuffer *intel_fb;
 466         struct drm_i915_gem_object *obj;
 467         const struct drm_display_mode *adjusted_mode;
 468         unsigned int max_width, max_height;
 469
 470         if (!HAS_FBC(dev)) {
 471                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 472                 return;
 473         }
 474
 475         if (!i915.powersave) {
 476                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 477                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 478                 return;
 479         }
 480
 481         /*
 482          * If FBC is already on, we just have to verify that we can
 483          * keep it that way...
 484          * Need to disable if:
 485          *   - more than one pipe is active
 486          *   - changing FBC params (stride, fence, mode)
 487          *   - new fb is too large to fit in compressed buffer
 488          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 489          */
 490         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 491                 if (intel_crtc_active(tmp_crtc) &&
 492                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 493                         if (crtc) {
 494                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 495                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 496                                 goto out_disable;
 497                         }
 498                         crtc = tmp_crtc;
 499                 }
 500         }
 501
 502         if (!crtc || crtc->primary->fb == NULL) {
 503                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 504                         DRM_DEBUG_KMS("no output, disabling\n");
 505                 goto out_disable;
 506         }
 507
 508         intel_crtc = to_intel_crtc(crtc);
 509         fb = crtc->primary->fb;
 510         intel_fb = to_intel_framebuffer(fb);
 511         obj = intel_fb->obj;
 512         adjusted_mode = &intel_crtc->config.adjusted_mode;
 513
 514         if (i915.enable_fbc < 0 &&
 515             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 516                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 517                         DRM_DEBUG_KMS("disabled per chip default\n");
 518                 goto out_disable;
 519         }
 520         if (!i915.enable_fbc) {
 521                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 522                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 523                 goto out_disable;
 524         }
 525         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 526             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 527                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 528                         DRM_DEBUG_KMS("mode incompatible with compression, "
 529                                       "disabling\n");
 530                 goto out_disable;
 531         }
 532
 533         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 534                 max_width = 4096;
 535                 max_height = 2048;
 536         } else {
 537                 max_width = 2048;
 538                 max_height = 1536;
 539         }
 540         if (intel_crtc->config.pipe_src_w > max_width ||
 541             intel_crtc->config.pipe_src_h > max_height) {
 542                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 543                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 544                 goto out_disable;
 545         }
 546         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 547             intel_crtc->plane != PLANE_A) {
 548                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 549                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 550                 goto out_disable;
 551         }
 552
 553         /* The use of a CPU fence is mandatory in order to detect writes
 554          * by the CPU to the scanout and trigger updates to the FBC.
 555          */
 556         if (obj->tiling_mode != I915_TILING_X ||
 557             obj->fence_reg == I915_FENCE_REG_NONE) {
 558                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 559                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 560                 goto out_disable;
 561         }
 562
 563         /* If the kernel debugger is active, always disable compression */
 564         if (in_dbg_master())
 565                 goto out_disable;
 566
 567         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 568                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 569                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 570                 goto out_disable;
 571         }
 572
 573         /* If the scanout has not changed, don't modify the FBC settings.
 574          * Note that we make the fundamental assumption that the fb->obj
 575          * cannot be unpinned (and have its GTT offset and fence revoked)
 576          * without first being decoupled from the scanout and FBC disabled.
 577          */
 578         if (dev_priv->fbc.plane == intel_crtc->plane &&
 579             dev_priv->fbc.fb_id == fb->base.id &&
 580             dev_priv->fbc.y == crtc->y)
 581                 return;
 582
 583         if (intel_fbc_enabled(dev)) {
 584                 /* We update FBC along two paths, after changing fb/crtc
 585                  * configuration (modeswitching) and after page-flipping
 586                  * finishes. For the latter, we know that not only did
 587                  * we disable the FBC at the start of the page-flip
 588                  * sequence, but also more than one vblank has passed.
 589                  *
 590                  * For the former case of modeswitching, it is possible
 591                  * to switch between two FBC valid configurations
 592                  * instantaneously so we do need to disable the FBC
 593                  * before we can modify its control registers. We also
 594                  * have to wait for the next vblank for that to take
 595                  * effect. However, since we delay enabling FBC we can
 596                  * assume that a vblank has passed since disabling and
 597                  * that we can safely alter the registers in the deferred
 598                  * callback.
 599                  *
 600                  * In the scenario that we go from a valid to invalid
 601                  * and then back to valid FBC configuration we have
 602                  * no strict enforcement that a vblank occurred since
 603                  * disabling the FBC. However, along all current pipe
 604                  * disabling paths we do need to wait for a vblank at
 605                  * some point. And we wait before enabling FBC anyway.
 606                  */
 607                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 608                 intel_disable_fbc(dev);
 609         }
 610
 611         intel_enable_fbc(crtc);
 612         dev_priv->fbc.no_fbc_reason = FBC_OK;
 613         return;
 614
 615 out_disable:
 616         /* Multiple disables should be harmless */
 617         if (intel_fbc_enabled(dev)) {
 618                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 619                 intel_disable_fbc(dev);
 620         }
 621         i915_gem_stolen_cleanup_compression(dev);
 622 }
 623
 624 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         u32 tmp;
 628
 629         tmp = I915_READ(CLKCFG);
 630
 631         switch (tmp & CLKCFG_FSB_MASK) {
 632         case CLKCFG_FSB_533:
 633                 dev_priv->fsb_freq = 533; /* 133*4 */
 634                 break;
 635         case CLKCFG_FSB_800:
 636                 dev_priv->fsb_freq = 800; /* 200*4 */
 637                 break;
 638         case CLKCFG_FSB_667:
 639                 dev_priv->fsb_freq =  667; /* 167*4 */
 640                 break;
 641         case CLKCFG_FSB_400:
 642                 dev_priv->fsb_freq = 400; /* 100*4 */
 643                 break;
 644         }
 645
 646         switch (tmp & CLKCFG_MEM_MASK) {
 647         case CLKCFG_MEM_533:
 648                 dev_priv->mem_freq = 533;
 649                 break;
 650         case CLKCFG_MEM_667:
 651                 dev_priv->mem_freq = 667;
 652                 break;
 653         case CLKCFG_MEM_800:
 654                 dev_priv->mem_freq = 800;
 655                 break;
 656         }
 657
 658         /* detect pineview DDR3 setting */
 659         tmp = I915_READ(CSHRDDR3CTL);
 660         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 661 }
 662
 663 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 664 {
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         u16 ddrpll, csipll;
 667
 668         ddrpll = I915_READ16(DDRMPLL1);
 669         csipll = I915_READ16(CSIPLL0);
 670
 671         switch (ddrpll & 0xff) {
 672         case 0xc:
 673                 dev_priv->mem_freq = 800;
 674                 break;
 675         case 0x10:
 676                 dev_priv->mem_freq = 1066;
 677                 break;
 678         case 0x14:
 679                 dev_priv->mem_freq = 1333;
 680                 break;
 681         case 0x18:
 682                 dev_priv->mem_freq = 1600;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 686                                  ddrpll & 0xff);
 687                 dev_priv->mem_freq = 0;
 688                 break;
 689         }
 690
 691         dev_priv->ips.r_t = dev_priv->mem_freq;
 692
 693         switch (csipll & 0x3ff) {
 694         case 0x00c:
 695                 dev_priv->fsb_freq = 3200;
 696                 break;
 697         case 0x00e:
 698                 dev_priv->fsb_freq = 3733;
 699                 break;
 700         case 0x010:
 701                 dev_priv->fsb_freq = 4266;
 702                 break;
 703         case 0x012:
 704                 dev_priv->fsb_freq = 4800;
 705                 break;
 706         case 0x014:
 707                 dev_priv->fsb_freq = 5333;
 708                 break;
 709         case 0x016:
 710                 dev_priv->fsb_freq = 5866;
 711                 break;
 712         case 0x018:
 713                 dev_priv->fsb_freq = 6400;
 714                 break;
 715         default:
 716                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 717                                  csipll & 0x3ff);
 718                 dev_priv->fsb_freq = 0;
 719                 break;
 720         }
 721
 722         if (dev_priv->fsb_freq == 3200) {
 723                 dev_priv->ips.c_m = 0;
 724         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 725                 dev_priv->ips.c_m = 1;
 726         } else {
 727                 dev_priv->ips.c_m = 2;
 728         }
 729 }
 730
 731 static const struct cxsr_latency cxsr_latency_table[] = {
 732         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 733         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 734         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 735         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 736         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 737
 738         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 739         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 740         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 741         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 742         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 743
 744         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 745         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 746         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 747         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 748         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 749
 750         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 751         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 752         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 753         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 754         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 755
 756         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 757         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 758         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 759         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 760         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 761
 762         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 763         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 764         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 765         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 766         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 767 };
 768
 769 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 770                                                          int is_ddr3,
 771                                                          int fsb,
 772                                                          int mem)
 773 {
 774         const struct cxsr_latency *latency;
 775         int i;
 776
 777         if (fsb == 0 || mem == 0)
 778                 return NULL;
 779
 780         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 781                 latency = &cxsr_latency_table[i];
 782                 if (is_desktop == latency->is_desktop &&
 783                     is_ddr3 == latency->is_ddr3 &&
 784                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 785                         return latency;
 786         }
 787
 788         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 789
 790         return NULL;
 791 }
 792
 793 static void pineview_disable_cxsr(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796
 797         /* deactivate cxsr */
 798         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 799 }
 800
 801 /*
 802  * Latency for FIFO fetches is dependent on several factors:
 803  *   - memory configuration (speed, channels)
 804  *   - chipset
 805  *   - current MCH state
 806  * It can be fairly high in some situations, so here we assume a fairly
 807  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 808  * set this value too high, the FIFO will fetch frequently to stay full)
 809  * and power consumption (set it too low to save power and we might see
 810  * FIFO underruns and display "flicker").
 811  *
 812  * A value of 5us seems to be a good balance; safe for very low end
 813  * platforms but not overly aggressive on lower latency configs.
 814  */
 815 static const int latency_ns = 5000;
 816
 817 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 818 {
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         uint32_t dsparb = I915_READ(DSPARB);
 821         int size;
 822
 823         size = dsparb & 0x7f;
 824         if (plane)
 825                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 826
 827         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 828                       plane ? "B" : "A", size);
 829
 830         return size;
 831 }
 832
 833 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 834 {
 835         struct drm_i915_private *dev_priv = dev->dev_private;
 836         uint32_t dsparb = I915_READ(DSPARB);
 837         int size;
 838
 839         size = dsparb & 0x1ff;
 840         if (plane)
 841                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         uint32_t dsparb = I915_READ(DSPARB);
 854         int size;
 855
 856         size = dsparb & 0x7f;
 857         size >>= 2; /* Convert to cachelines */
 858
 859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 860                       plane ? "B" : "A",
 861                       size);
 862
 863         return size;
 864 }
 865
 866 /* Pineview has different values for various configs */
 867 static const struct intel_watermark_params pineview_display_wm = {
 868         PINEVIEW_DISPLAY_FIFO,
 869         PINEVIEW_MAX_WM,
 870         PINEVIEW_DFT_WM,
 871         PINEVIEW_GUARD_WM,
 872         PINEVIEW_FIFO_LINE_SIZE
 873 };
 874 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 875         PINEVIEW_DISPLAY_FIFO,
 876         PINEVIEW_MAX_WM,
 877         PINEVIEW_DFT_HPLLOFF_WM,
 878         PINEVIEW_GUARD_WM,
 879         PINEVIEW_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params pineview_cursor_wm = {
 882         PINEVIEW_CURSOR_FIFO,
 883         PINEVIEW_CURSOR_MAX_WM,
 884         PINEVIEW_CURSOR_DFT_WM,
 885         PINEVIEW_CURSOR_GUARD_WM,
 886         PINEVIEW_FIFO_LINE_SIZE,
 887 };
 888 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 889         PINEVIEW_CURSOR_FIFO,
 890         PINEVIEW_CURSOR_MAX_WM,
 891         PINEVIEW_CURSOR_DFT_WM,
 892         PINEVIEW_CURSOR_GUARD_WM,
 893         PINEVIEW_FIFO_LINE_SIZE
 894 };
 895 static const struct intel_watermark_params g4x_wm_info = {
 896         G4X_FIFO_SIZE,
 897         G4X_MAX_WM,
 898         G4X_MAX_WM,
 899         2,
 900         G4X_FIFO_LINE_SIZE,
 901 };
 902 static const struct intel_watermark_params g4x_cursor_wm_info = {
 903         I965_CURSOR_FIFO,
 904         I965_CURSOR_MAX_WM,
 905         I965_CURSOR_DFT_WM,
 906         2,
 907         G4X_FIFO_LINE_SIZE,
 908 };
 909 static const struct intel_watermark_params valleyview_wm_info = {
 910         VALLEYVIEW_FIFO_SIZE,
 911         VALLEYVIEW_MAX_WM,
 912         VALLEYVIEW_MAX_WM,
 913         2,
 914         G4X_FIFO_LINE_SIZE,
 915 };
 916 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 917         I965_CURSOR_FIFO,
 918         VALLEYVIEW_CURSOR_MAX_WM,
 919         I965_CURSOR_DFT_WM,
 920         2,
 921         G4X_FIFO_LINE_SIZE,
 922 };
 923 static const struct intel_watermark_params i965_cursor_wm_info = {
 924         I965_CURSOR_FIFO,
 925         I965_CURSOR_MAX_WM,
 926         I965_CURSOR_DFT_WM,
 927         2,
 928         I915_FIFO_LINE_SIZE,
 929 };
 930 static const struct intel_watermark_params i945_wm_info = {
 931         I945_FIFO_SIZE,
 932         I915_MAX_WM,
 933         1,
 934         2,
 935         I915_FIFO_LINE_SIZE
 936 };
 937 static const struct intel_watermark_params i915_wm_info = {
 938         I915_FIFO_SIZE,
 939         I915_MAX_WM,
 940         1,
 941         2,
 942         I915_FIFO_LINE_SIZE
 943 };
 944 static const struct intel_watermark_params i830_wm_info = {
 945         I855GM_FIFO_SIZE,
 946         I915_MAX_WM,
 947         1,
 948         2,
 949         I830_FIFO_LINE_SIZE
 950 };
 951 static const struct intel_watermark_params i845_wm_info = {
 952         I830_FIFO_SIZE,
 953         I915_MAX_WM,
 954         1,
 955         2,
 956         I830_FIFO_LINE_SIZE
 957 };
 958
 959 /**
 960  * intel_calculate_wm - calculate watermark level
 961  * @clock_in_khz: pixel clock
 962  * @wm: chip FIFO params
 963  * @pixel_size: display pixel size
 964  * @latency_ns: memory latency for the platform
 965  *
 966  * Calculate the watermark level (the level at which the display plane will
 967  * start fetching from memory again).  Each chip has a different display
 968  * FIFO size and allocation, so the caller needs to figure that out and pass
 969  * in the correct intel_watermark_params structure.
 970  *
 971  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 972  * on the pixel size.  When it reaches the watermark level, it'll start
 973  * fetching FIFO line sized based chunks from memory until the FIFO fills
 974  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 975  * will occur, and a display engine hang could result.
 976  */
 977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 978                                         const struct intel_watermark_params *wm,
 979                                         int fifo_size,
 980                                         int pixel_size,
 981                                         unsigned long latency_ns)
 982 {
 983         long entries_required, wm_size;
 984
 985         /*
 986          * Note: we need to make sure we don't overflow for various clock &
 987          * latency values.
 988          * clocks go from a few thousand to several hundred thousand.
 989          * latency is usually a few thousand
 990          */
 991         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 992                 1000;
 993         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 994
 995         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 996
 997         wm_size = fifo_size - (entries_required + wm->guard_size);
 998
 999         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001         /* Don't promote wm_size to unsigned... */
1002         if (wm_size > (long)wm->max_wm)
1003                 wm_size = wm->max_wm;
1004         if (wm_size <= 0)
1005                 wm_size = wm->default_wm;
1006         return wm_size;
1007 }
1008
1009 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010 {
1011         struct drm_crtc *crtc, *enabled = NULL;
1012
1013         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1014                 if (intel_crtc_active(crtc)) {
1015                         if (enabled)
1016                                 return NULL;
1017                         enabled = crtc;
1018                 }
1019         }
1020
1021         return enabled;
1022 }
1023
1024 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1025 {
1026         struct drm_device *dev = unused_crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_crtc *crtc;
1029         const struct cxsr_latency *latency;
1030         u32 reg;
1031         unsigned long wm;
1032
1033         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1035         if (!latency) {
1036                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037                 pineview_disable_cxsr(dev);
1038                 return;
1039         }
1040
1041         crtc = single_enabled_crtc(dev);
1042         if (crtc) {
1043                 const struct drm_display_mode *adjusted_mode;
1044                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1045                 int clock;
1046
1047                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048                 clock = adjusted_mode->crtc_clock;
1049
1050                 /* Display SR */
1051                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052                                         pineview_display_wm.fifo_size,
1053                                         pixel_size, latency->display_sr);
1054                 reg = I915_READ(DSPFW1);
1055                 reg &= ~DSPFW_SR_MASK;
1056                 reg |= wm << DSPFW_SR_SHIFT;
1057                 I915_WRITE(DSPFW1, reg);
1058                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060                 /* cursor SR */
1061                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062                                         pineview_display_wm.fifo_size,
1063                                         pixel_size, latency->cursor_sr);
1064                 reg = I915_READ(DSPFW3);
1065                 reg &= ~DSPFW_CURSOR_SR_MASK;
1066                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067                 I915_WRITE(DSPFW3, reg);
1068
1069                 /* Display HPLL off SR */
1070                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071                                         pineview_display_hplloff_wm.fifo_size,
1072                                         pixel_size, latency->display_hpll_disable);
1073                 reg = I915_READ(DSPFW3);
1074                 reg &= ~DSPFW_HPLL_SR_MASK;
1075                 reg |= wm & DSPFW_HPLL_SR_MASK;
1076                 I915_WRITE(DSPFW3, reg);
1077
1078                 /* cursor HPLL off SR */
1079                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080                                         pineview_display_hplloff_wm.fifo_size,
1081                                         pixel_size, latency->cursor_hpll_disable);
1082                 reg = I915_READ(DSPFW3);
1083                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085                 I915_WRITE(DSPFW3, reg);
1086                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088                 /* activate cxsr */
1089                 I915_WRITE(DSPFW3,
1090                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092         } else {
1093                 pineview_disable_cxsr(dev);
1094                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095         }
1096 }
1097
1098 static bool g4x_compute_wm0(struct drm_device *dev,
1099                             int plane,
1100                             const struct intel_watermark_params *display,
1101                             int display_latency_ns,
1102                             const struct intel_watermark_params *cursor,
1103                             int cursor_latency_ns,
1104                             int *plane_wm,
1105                             int *cursor_wm)
1106 {
1107         struct drm_crtc *crtc;
1108         const struct drm_display_mode *adjusted_mode;
1109         int htotal, hdisplay, clock, pixel_size;
1110         int line_time_us, line_count;
1111         int entries, tlb_miss;
1112
1113         crtc = intel_get_crtc_for_plane(dev, plane);
1114         if (!intel_crtc_active(crtc)) {
1115                 *cursor_wm = cursor->guard_size;
1116                 *plane_wm = display->guard_size;
1117                 return false;
1118         }
1119
1120         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1121         clock = adjusted_mode->crtc_clock;
1122         htotal = adjusted_mode->crtc_htotal;
1123         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1124         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1125
1126         /* Use the small buffer method to calculate plane watermark */
1127         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129         if (tlb_miss > 0)
1130                 entries += tlb_miss;
1131         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132         *plane_wm = entries + display->guard_size;
1133         if (*plane_wm > (int)display->max_wm)
1134                 *plane_wm = display->max_wm;
1135
1136         /* Use the large buffer method to calculate cursor watermark */
1137         line_time_us = max(htotal * 1000 / clock, 1);
1138         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1140         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141         if (tlb_miss > 0)
1142                 entries += tlb_miss;
1143         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144         *cursor_wm = entries + cursor->guard_size;
1145         if (*cursor_wm > (int)cursor->max_wm)
1146                 *cursor_wm = (int)cursor->max_wm;
1147
1148         return true;
1149 }
1150
1151 /*
1152  * Check the wm result.
1153  *
1154  * If any calculated watermark values is larger than the maximum value that
1155  * can be programmed into the associated watermark register, that watermark
1156  * must be disabled.
1157  */
1158 static bool g4x_check_srwm(struct drm_device *dev,
1159                            int display_wm, int cursor_wm,
1160                            const struct intel_watermark_params *display,
1161                            const struct intel_watermark_params *cursor)
1162 {
1163         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164                       display_wm, cursor_wm);
1165
1166         if (display_wm > display->max_wm) {
1167                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168                               display_wm, display->max_wm);
1169                 return false;
1170         }
1171
1172         if (cursor_wm > cursor->max_wm) {
1173                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174                               cursor_wm, cursor->max_wm);
1175                 return false;
1176         }
1177
1178         if (!(display_wm || cursor_wm)) {
1179                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180                 return false;
1181         }
1182
1183         return true;
1184 }
1185
1186 static bool g4x_compute_srwm(struct drm_device *dev,
1187                              int plane,
1188                              int latency_ns,
1189                              const struct intel_watermark_params *display,
1190                              const struct intel_watermark_params *cursor,
1191                              int *display_wm, int *cursor_wm)
1192 {
1193         struct drm_crtc *crtc;
1194         const struct drm_display_mode *adjusted_mode;
1195         int hdisplay, htotal, pixel_size, clock;
1196         unsigned long line_time_us;
1197         int line_count, line_size;
1198         int small, large;
1199         int entries;
1200
1201         if (!latency_ns) {
1202                 *display_wm = *cursor_wm = 0;
1203                 return false;
1204         }
1205
1206         crtc = intel_get_crtc_for_plane(dev, plane);
1207         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1208         clock = adjusted_mode->crtc_clock;
1209         htotal = adjusted_mode->crtc_htotal;
1210         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1212
1213         line_time_us = max(htotal * 1000 / clock, 1);
1214         line_count = (latency_ns / line_time_us + 1000) / 1000;
1215         line_size = hdisplay * pixel_size;
1216
1217         /* Use the minimum of the small and large buffer method for primary */
1218         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219         large = line_count * line_size;
1220
1221         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222         *display_wm = entries + display->guard_size;
1223
1224         /* calculate the self-refresh watermark for display cursor */
1225         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1226         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227         *cursor_wm = entries + cursor->guard_size;
1228
1229         return g4x_check_srwm(dev,
1230                               *display_wm, *cursor_wm,
1231                               display, cursor);
1232 }
1233
1234 static bool vlv_compute_drain_latency(struct drm_device *dev,
1235                                      int plane,
1236                                      int *plane_prec_mult,
1237                                      int *plane_dl,
1238                                      int *cursor_prec_mult,
1239                                      int *cursor_dl)
1240 {
1241         struct drm_crtc *crtc;
1242         int clock, pixel_size;
1243         int entries;
1244
1245         crtc = intel_get_crtc_for_plane(dev, plane);
1246         if (!intel_crtc_active(crtc))
1247                 return false;
1248
1249         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1250         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1251
1252         entries = (clock / 1000) * pixel_size;
1253         *plane_prec_mult = (entries > 256) ?
1254                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256                                                      pixel_size);
1257
1258         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1259         *cursor_prec_mult = (entries > 256) ?
1260                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263         return true;
1264 }
1265
1266 /*
1267  * Update drain latency registers of memory arbiter
1268  *
1269  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270  * to be programmed. Each plane has a drain latency multiplier and a drain
1271  * latency value.
1272  */
1273
1274 static void vlv_update_drain_latency(struct drm_device *dev)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280                                                         either 16 or 32 */
1281
1282         /* For plane A, Cursor A */
1283         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284                                       &cursor_prec_mult, &cursora_dl)) {
1285                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290                 I915_WRITE(VLV_DDL1, cursora_prec |
1291                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1292                                 planea_prec | planea_dl);
1293         }
1294
1295         /* For plane B, Cursor B */
1296         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297                                       &cursor_prec_mult, &cursorb_dl)) {
1298                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303                 I915_WRITE(VLV_DDL2, cursorb_prec |
1304                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305                                 planeb_prec | planeb_dl);
1306         }
1307 }
1308
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1310
1311 static void valleyview_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         static const int sr_latency_ns = 12000;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317         int plane_sr, cursor_sr;
1318         int ignore_plane_sr, ignore_cursor_sr;
1319         unsigned int enabled = 0;
1320
1321         vlv_update_drain_latency(dev);
1322
1323         if (g4x_compute_wm0(dev, PIPE_A,
1324                             &valleyview_wm_info, latency_ns,
1325                             &valleyview_cursor_wm_info, latency_ns,
1326                             &planea_wm, &cursora_wm))
1327                 enabled |= 1 << PIPE_A;
1328
1329         if (g4x_compute_wm0(dev, PIPE_B,
1330                             &valleyview_wm_info, latency_ns,
1331                             &valleyview_cursor_wm_info, latency_ns,
1332                             &planeb_wm, &cursorb_wm))
1333                 enabled |= 1 << PIPE_B;
1334
1335         if (single_plane_enabled(enabled) &&
1336             g4x_compute_srwm(dev, ffs(enabled) - 1,
1337                              sr_latency_ns,
1338                              &valleyview_wm_info,
1339                              &valleyview_cursor_wm_info,
1340                              &plane_sr, &ignore_cursor_sr) &&
1341             g4x_compute_srwm(dev, ffs(enabled) - 1,
1342                              2*sr_latency_ns,
1343                              &valleyview_wm_info,
1344                              &valleyview_cursor_wm_info,
1345                              &ignore_plane_sr, &cursor_sr)) {
1346                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1347         } else {
1348                 I915_WRITE(FW_BLC_SELF_VLV,
1349                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1350                 plane_sr = cursor_sr = 0;
1351         }
1352
1353         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354                       planea_wm, cursora_wm,
1355                       planeb_wm, cursorb_wm,
1356                       plane_sr, cursor_sr);
1357
1358         I915_WRITE(DSPFW1,
1359                    (plane_sr << DSPFW_SR_SHIFT) |
1360                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362                    planea_wm);
1363         I915_WRITE(DSPFW2,
1364                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1365                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1366         I915_WRITE(DSPFW3,
1367                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1369 }
1370
1371 static void g4x_update_wm(struct drm_crtc *crtc)
1372 {
1373         struct drm_device *dev = crtc->dev;
1374         static const int sr_latency_ns = 12000;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377         int plane_sr, cursor_sr;
1378         unsigned int enabled = 0;
1379
1380         if (g4x_compute_wm0(dev, PIPE_A,
1381                             &g4x_wm_info, latency_ns,
1382                             &g4x_cursor_wm_info, latency_ns,
1383                             &planea_wm, &cursora_wm))
1384                 enabled |= 1 << PIPE_A;
1385
1386         if (g4x_compute_wm0(dev, PIPE_B,
1387                             &g4x_wm_info, latency_ns,
1388                             &g4x_cursor_wm_info, latency_ns,
1389                             &planeb_wm, &cursorb_wm))
1390                 enabled |= 1 << PIPE_B;
1391
1392         if (single_plane_enabled(enabled) &&
1393             g4x_compute_srwm(dev, ffs(enabled) - 1,
1394                              sr_latency_ns,
1395                              &g4x_wm_info,
1396                              &g4x_cursor_wm_info,
1397                              &plane_sr, &cursor_sr)) {
1398                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1399         } else {
1400                 I915_WRITE(FW_BLC_SELF,
1401                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1402                 plane_sr = cursor_sr = 0;
1403         }
1404
1405         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406                       planea_wm, cursora_wm,
1407                       planeb_wm, cursorb_wm,
1408                       plane_sr, cursor_sr);
1409
1410         I915_WRITE(DSPFW1,
1411                    (plane_sr << DSPFW_SR_SHIFT) |
1412                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414                    planea_wm);
1415         I915_WRITE(DSPFW2,
1416                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1417                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1418         /* HPLL off in SR has some issues on G4x... disable it */
1419         I915_WRITE(DSPFW3,
1420                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1421                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431
1432         /* Calc sr entries for one plane configs */
1433         crtc = single_enabled_crtc(dev);
1434         if (crtc) {
1435                 /* self-refresh has much higher latency */
1436                 static const int sr_latency_ns = 12000;
1437                 const struct drm_display_mode *adjusted_mode =
1438                         &to_intel_crtc(crtc)->config.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1442                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 if (IS_CRESTLINE(dev))
1473                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474         } else {
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 if (IS_CRESTLINE(dev))
1477                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478                                    & ~FW_BLC_SELF_EN);
1479         }
1480
1481         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482                       srwm);
1483
1484         /* 965 has limitations... */
1485         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486                    (8 << 16) | (8 << 8) | (8 << 0));
1487         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488         /* update cursor SR watermark */
1489         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490 }
1491
1492 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1493 {
1494         struct drm_device *dev = unused_crtc->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         const struct intel_watermark_params *wm_info;
1497         uint32_t fwater_lo;
1498         uint32_t fwater_hi;
1499         int cwm, srwm = 1;
1500         int fifo_size;
1501         int planea_wm, planeb_wm;
1502         struct drm_crtc *crtc, *enabled = NULL;
1503
1504         if (IS_I945GM(dev))
1505                 wm_info = &i945_wm_info;
1506         else if (!IS_GEN2(dev))
1507                 wm_info = &i915_wm_info;
1508         else
1509                 wm_info = &i830_wm_info;
1510
1511         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512         crtc = intel_get_crtc_for_plane(dev, 0);
1513         if (intel_crtc_active(crtc)) {
1514                 const struct drm_display_mode *adjusted_mode;
1515                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1516                 if (IS_GEN2(dev))
1517                         cpp = 4;
1518
1519                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1521                                                wm_info, fifo_size, cpp,
1522                                                latency_ns);
1523                 enabled = crtc;
1524         } else
1525                 planea_wm = fifo_size - wm_info->guard_size;
1526
1527         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528         crtc = intel_get_crtc_for_plane(dev, 1);
1529         if (intel_crtc_active(crtc)) {
1530                 const struct drm_display_mode *adjusted_mode;
1531                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1532                 if (IS_GEN2(dev))
1533                         cpp = 4;
1534
1535                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1537                                                wm_info, fifo_size, cpp,
1538                                                latency_ns);
1539                 if (enabled == NULL)
1540                         enabled = crtc;
1541                 else
1542                         enabled = NULL;
1543         } else
1544                 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         /*
1549          * Overlay gets an aggressive default since video jitter is bad.
1550          */
1551         cwm = 2;
1552
1553         /* Play safe and disable self-refresh before adjusting watermarks. */
1554         if (IS_I945G(dev) || IS_I945GM(dev))
1555                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1556         else if (IS_I915GM(dev))
1557                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1558
1559         /* Calc sr entries for one plane configs */
1560         if (HAS_FW_BLC(dev) && enabled) {
1561                 /* self-refresh has much higher latency */
1562                 static const int sr_latency_ns = 6000;
1563                 const struct drm_display_mode *adjusted_mode =
1564                         &to_intel_crtc(enabled)->config.adjusted_mode;
1565                 int clock = adjusted_mode->crtc_clock;
1566                 int htotal = adjusted_mode->crtc_htotal;
1567                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1568                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1569                 unsigned long line_time_us;
1570                 int entries;
1571
1572                 line_time_us = max(htotal * 1000 / clock, 1);
1573
1574                 /* Use ns/us then divide to preserve precision */
1575                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1576                         pixel_size * hdisplay;
1577                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1578                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1579                 srwm = wm_info->fifo_size - entries;
1580                 if (srwm < 0)
1581                         srwm = 1;
1582
1583                 if (IS_I945G(dev) || IS_I945GM(dev))
1584                         I915_WRITE(FW_BLC_SELF,
1585                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1586                 else if (IS_I915GM(dev))
1587                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1588         }
1589
1590         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1591                       planea_wm, planeb_wm, cwm, srwm);
1592
1593         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1594         fwater_hi = (cwm & 0x1f);
1595
1596         /* Set request length to 8 cachelines per fetch */
1597         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1598         fwater_hi = fwater_hi | (1 << 8);
1599
1600         I915_WRITE(FW_BLC, fwater_lo);
1601         I915_WRITE(FW_BLC2, fwater_hi);
1602
1603         if (HAS_FW_BLC(dev)) {
1604                 if (enabled) {
1605                         if (IS_I945G(dev) || IS_I945GM(dev))
1606                                 I915_WRITE(FW_BLC_SELF,
1607                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1608                         else if (IS_I915GM(dev))
1609                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1610                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1611                 } else
1612                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1613         }
1614 }
1615
1616 static void i845_update_wm(struct drm_crtc *unused_crtc)
1617 {
1618         struct drm_device *dev = unused_crtc->dev;
1619         struct drm_i915_private *dev_priv = dev->dev_private;
1620         struct drm_crtc *crtc;
1621         const struct drm_display_mode *adjusted_mode;
1622         uint32_t fwater_lo;
1623         int planea_wm;
1624
1625         crtc = single_enabled_crtc(dev);
1626         if (crtc == NULL)
1627                 return;
1628
1629         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1630         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1631                                        &i845_wm_info,
1632                                        dev_priv->display.get_fifo_size(dev, 0),
1633                                        4, latency_ns);
1634         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1635         fwater_lo |= (3<<8) | planea_wm;
1636
1637         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1638
1639         I915_WRITE(FW_BLC, fwater_lo);
1640 }
1641
1642 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1643                                     struct drm_crtc *crtc)
1644 {
1645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1646         uint32_t pixel_rate;
1647
1648         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1649
1650         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651          * adjust the pixel_rate here. */
1652
1653         if (intel_crtc->config.pch_pfit.enabled) {
1654                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1656
1657                 pipe_w = intel_crtc->config.pipe_src_w;
1658                 pipe_h = intel_crtc->config.pipe_src_h;
1659                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1660                 pfit_h = pfit_size & 0xFFFF;
1661                 if (pipe_w < pfit_w)
1662                         pipe_w = pfit_w;
1663                 if (pipe_h < pfit_h)
1664                         pipe_h = pfit_h;
1665
1666                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1667                                      pfit_w * pfit_h);
1668         }
1669
1670         return pixel_rate;
1671 }
1672
1673 /* latency must be in 0.1us units. */
1674 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1675                                uint32_t latency)
1676 {
1677         uint64_t ret;
1678
1679         if (WARN(latency == 0, "Latency value missing\n"))
1680                 return UINT_MAX;
1681
1682         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1683         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1684
1685         return ret;
1686 }
1687
1688 /* latency must be in 0.1us units. */
1689 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1690                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1691                                uint32_t latency)
1692 {
1693         uint32_t ret;
1694
1695         if (WARN(latency == 0, "Latency value missing\n"))
1696                 return UINT_MAX;
1697
1698         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1700         ret = DIV_ROUND_UP(ret, 64) + 2;
1701         return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705                            uint8_t bytes_per_pixel)
1706 {
1707         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1708 }
1709
1710 struct ilk_pipe_wm_parameters {
1711         bool active;
1712         uint32_t pipe_htotal;
1713         uint32_t pixel_rate;
1714         struct intel_plane_wm_parameters pri;
1715         struct intel_plane_wm_parameters spr;
1716         struct intel_plane_wm_parameters cur;
1717 };
1718
1719 struct ilk_wm_maximums {
1720         uint16_t pri;
1721         uint16_t spr;
1722         uint16_t cur;
1723         uint16_t fbc;
1724 };
1725
1726 /* used in computing the new watermarks state */
1727 struct intel_wm_config {
1728         unsigned int num_pipes_active;
1729         bool sprites_enabled;
1730         bool sprites_scaled;
1731 };
1732
1733 /*
1734  * For both WM_PIPE and WM_LP.
1735  * mem_value must be in 0.1us units.
1736  */
1737 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1738                                    uint32_t mem_value,
1739                                    bool is_lp)
1740 {
1741         uint32_t method1, method2;
1742
1743         if (!params->active || !params->pri.enabled)
1744                 return 0;
1745
1746         method1 = ilk_wm_method1(params->pixel_rate,
1747                                  params->pri.bytes_per_pixel,
1748                                  mem_value);
1749
1750         if (!is_lp)
1751                 return method1;
1752
1753         method2 = ilk_wm_method2(params->pixel_rate,
1754                                  params->pipe_htotal,
1755                                  params->pri.horiz_pixels,
1756                                  params->pri.bytes_per_pixel,
1757                                  mem_value);
1758
1759         return min(method1, method2);
1760 }
1761
1762 /*
1763  * For both WM_PIPE and WM_LP.
1764  * mem_value must be in 0.1us units.
1765  */
1766 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1767                                    uint32_t mem_value)
1768 {
1769         uint32_t method1, method2;
1770
1771         if (!params->active || !params->spr.enabled)
1772                 return 0;
1773
1774         method1 = ilk_wm_method1(params->pixel_rate,
1775                                  params->spr.bytes_per_pixel,
1776                                  mem_value);
1777         method2 = ilk_wm_method2(params->pixel_rate,
1778                                  params->pipe_htotal,
1779                                  params->spr.horiz_pixels,
1780                                  params->spr.bytes_per_pixel,
1781                                  mem_value);
1782         return min(method1, method2);
1783 }
1784
1785 /*
1786  * For both WM_PIPE and WM_LP.
1787  * mem_value must be in 0.1us units.
1788  */
1789 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1790                                    uint32_t mem_value)
1791 {
1792         if (!params->active || !params->cur.enabled)
1793                 return 0;
1794
1795         return ilk_wm_method2(params->pixel_rate,
1796                               params->pipe_htotal,
1797                               params->cur.horiz_pixels,
1798                               params->cur.bytes_per_pixel,
1799                               mem_value);
1800 }
1801
1802 /* Only for WM_LP. */
1803 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1804                                    uint32_t pri_val)
1805 {
1806         if (!params->active || !params->pri.enabled)
1807                 return 0;
1808
1809         return ilk_wm_fbc(pri_val,
1810                           params->pri.horiz_pixels,
1811                           params->pri.bytes_per_pixel);
1812 }
1813
1814 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1815 {
1816         if (INTEL_INFO(dev)->gen >= 8)
1817                 return 3072;
1818         else if (INTEL_INFO(dev)->gen >= 7)
1819                 return 768;
1820         else
1821                 return 512;
1822 }
1823
1824 /* Calculate the maximum primary/sprite plane watermark */
1825 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1826                                      int level,
1827                                      const struct intel_wm_config *config,
1828                                      enum intel_ddb_partitioning ddb_partitioning,
1829                                      bool is_sprite)
1830 {
1831         unsigned int fifo_size = ilk_display_fifo_size(dev);
1832         unsigned int max;
1833
1834         /* if sprites aren't enabled, sprites get nothing */
1835         if (is_sprite && !config->sprites_enabled)
1836                 return 0;
1837
1838         /* HSW allows LP1+ watermarks even with multiple pipes */
1839         if (level == 0 || config->num_pipes_active > 1) {
1840                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1841
1842                 /*
1843                  * For some reason the non self refresh
1844                  * FIFO size is only half of the self
1845                  * refresh FIFO size on ILK/SNB.
1846                  */
1847                 if (INTEL_INFO(dev)->gen <= 6)
1848                         fifo_size /= 2;
1849         }
1850
1851         if (config->sprites_enabled) {
1852                 /* level 0 is always calculated with 1:1 split */
1853                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1854                         if (is_sprite)
1855                                 fifo_size *= 5;
1856                         fifo_size /= 6;
1857                 } else {
1858                         fifo_size /= 2;
1859                 }
1860         }
1861
1862         /* clamp to max that the registers can hold */
1863         if (INTEL_INFO(dev)->gen >= 8)
1864                 max = level == 0 ? 255 : 2047;
1865         else if (INTEL_INFO(dev)->gen >= 7)
1866                 /* IVB/HSW primary/sprite plane watermarks */
1867                 max = level == 0 ? 127 : 1023;
1868         else if (!is_sprite)
1869                 /* ILK/SNB primary plane watermarks */
1870                 max = level == 0 ? 127 : 511;
1871         else
1872                 /* ILK/SNB sprite plane watermarks */
1873                 max = level == 0 ? 63 : 255;
1874
1875         return min(fifo_size, max);
1876 }
1877
1878 /* Calculate the maximum cursor plane watermark */
1879 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1880                                       int level,
1881                                       const struct intel_wm_config *config)
1882 {
1883         /* HSW LP1+ watermarks w/ multiple pipes */
1884         if (level > 0 && config->num_pipes_active > 1)
1885                 return 64;
1886
1887         /* otherwise just report max that registers can hold */
1888         if (INTEL_INFO(dev)->gen >= 7)
1889                 return level == 0 ? 63 : 255;
1890         else
1891                 return level == 0 ? 31 : 63;
1892 }
1893
1894 /* Calculate the maximum FBC watermark */
1895 static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
1896 {
1897         /* max that registers can hold */
1898         if (INTEL_INFO(dev)->gen >= 8)
1899                 return 31;
1900         else
1901                 return 15;
1902 }
1903
1904 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1905                                     int level,
1906                                     const struct intel_wm_config *config,
1907                                     enum intel_ddb_partitioning ddb_partitioning,
1908                                     struct ilk_wm_maximums *max)
1909 {
1910         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1911         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1912         max->cur = ilk_cursor_wm_max(dev, level, config);
1913         max->fbc = ilk_fbc_wm_max(dev);
1914 }
1915
1916 static bool ilk_validate_wm_level(int level,
1917                                   const struct ilk_wm_maximums *max,
1918                                   struct intel_wm_level *result)
1919 {
1920         bool ret;
1921
1922         /* already determined to be invalid? */
1923         if (!result->enable)
1924                 return false;
1925
1926         result->enable = result->pri_val <= max->pri &&
1927                          result->spr_val <= max->spr &&
1928                          result->cur_val <= max->cur;
1929
1930         ret = result->enable;
1931
1932         /*
1933          * HACK until we can pre-compute everything,
1934          * and thus fail gracefully if LP0 watermarks
1935          * are exceeded...
1936          */
1937         if (level == 0 && !result->enable) {
1938                 if (result->pri_val > max->pri)
1939                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1940                                       level, result->pri_val, max->pri);
1941                 if (result->spr_val > max->spr)
1942                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1943                                       level, result->spr_val, max->spr);
1944                 if (result->cur_val > max->cur)
1945                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1946                                       level, result->cur_val, max->cur);
1947
1948                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1949                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1950                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1951                 result->enable = true;
1952         }
1953
1954         return ret;
1955 }
1956
1957 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1958                                  int level,
1959                                  const struct ilk_pipe_wm_parameters *p,
1960                                  struct intel_wm_level *result)
1961 {
1962         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1963         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1964         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1965
1966         /* WM1+ latency values stored in 0.5us units */
1967         if (level > 0) {
1968                 pri_latency *= 5;
1969                 spr_latency *= 5;
1970                 cur_latency *= 5;
1971         }
1972
1973         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1974         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1975         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1976         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1977         result->enable = true;
1978 }
1979
1980 static uint32_t
1981 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1982 {
1983         struct drm_i915_private *dev_priv = dev->dev_private;
1984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1985         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
1986         u32 linetime, ips_linetime;
1987
1988         if (!intel_crtc_active(crtc))
1989                 return 0;
1990
1991         /* The WM are computed with base on how long it takes to fill a single
1992          * row at the given clock rate, multiplied by 8.
1993          * */
1994         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1995                                      mode->crtc_clock);
1996         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1997                                          intel_ddi_get_cdclk_freq(dev_priv));
1998
1999         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2000                PIPE_WM_LINETIME_TIME(linetime);
2001 }
2002
2003 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2004 {
2005         struct drm_i915_private *dev_priv = dev->dev_private;
2006
2007         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2008                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2009
2010                 wm[0] = (sskpd >> 56) & 0xFF;
2011                 if (wm[0] == 0)
2012                         wm[0] = sskpd & 0xF;
2013                 wm[1] = (sskpd >> 4) & 0xFF;
2014                 wm[2] = (sskpd >> 12) & 0xFF;
2015                 wm[3] = (sskpd >> 20) & 0x1FF;
2016                 wm[4] = (sskpd >> 32) & 0x1FF;
2017         } else if (INTEL_INFO(dev)->gen >= 6) {
2018                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2019
2020                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2021                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2022                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2023                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2024         } else if (INTEL_INFO(dev)->gen >= 5) {
2025                 uint32_t mltr = I915_READ(MLTR_ILK);
2026
2027                 /* ILK primary LP0 latency is 700 ns */
2028                 wm[0] = 7;
2029                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2030                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2031         }
2032 }
2033
2034 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2035 {
2036         /* ILK sprite LP0 latency is 1300 ns */
2037         if (INTEL_INFO(dev)->gen == 5)
2038                 wm[0] = 13;
2039 }
2040
2041 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2042 {
2043         /* ILK cursor LP0 latency is 1300 ns */
2044         if (INTEL_INFO(dev)->gen == 5)
2045                 wm[0] = 13;
2046
2047         /* WaDoubleCursorLP3Latency:ivb */
2048         if (IS_IVYBRIDGE(dev))
2049                 wm[3] *= 2;
2050 }
2051
2052 static int ilk_wm_max_level(const struct drm_device *dev)
2053 {
2054         /* how many WM levels are we expecting */
2055         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2056                 return 4;
2057         else if (INTEL_INFO(dev)->gen >= 6)
2058                 return 3;
2059         else
2060                 return 2;
2061 }
2062
2063 static void intel_print_wm_latency(struct drm_device *dev,
2064                                    const char *name,
2065                                    const uint16_t wm[5])
2066 {
2067         int level, max_level = ilk_wm_max_level(dev);
2068
2069         for (level = 0; level <= max_level; level++) {
2070                 unsigned int latency = wm[level];
2071
2072                 if (latency == 0) {
2073                         DRM_ERROR("%s WM%d latency not provided\n",
2074                                   name, level);
2075                         continue;
2076                 }
2077
2078                 /* WM1+ latency values in 0.5us units */
2079                 if (level > 0)
2080                         latency *= 5;
2081
2082                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2083                               name, level, wm[level],
2084                               latency / 10, latency % 10);
2085         }
2086 }
2087
2088 static void ilk_setup_wm_latency(struct drm_device *dev)
2089 {
2090         struct drm_i915_private *dev_priv = dev->dev_private;
2091
2092         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2093
2094         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2095                sizeof(dev_priv->wm.pri_latency));
2096         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2097                sizeof(dev_priv->wm.pri_latency));
2098
2099         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2100         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2101
2102         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2103         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2104         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2105 }
2106
2107 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2108                                       struct ilk_pipe_wm_parameters *p,
2109                                       struct intel_wm_config *config)
2110 {
2111         struct drm_device *dev = crtc->dev;
2112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2113         enum pipe pipe = intel_crtc->pipe;
2114         struct drm_plane *plane;
2115
2116         p->active = intel_crtc_active(crtc);
2117         if (p->active) {
2118                 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2119                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2120                 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2121                 p->cur.bytes_per_pixel = 4;
2122                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2123                 p->cur.horiz_pixels = intel_crtc->cursor_width;
2124                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2125                 p->pri.enabled = true;
2126                 p->cur.enabled = true;
2127         }
2128
2129         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2130                 config->num_pipes_active += intel_crtc_active(crtc);
2131
2132         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2133                 struct intel_plane *intel_plane = to_intel_plane(plane);
2134
2135                 if (intel_plane->pipe == pipe)
2136                         p->spr = intel_plane->wm;
2137
2138                 config->sprites_enabled |= intel_plane->wm.enabled;
2139                 config->sprites_scaled |= intel_plane->wm.scaled;
2140         }
2141 }
2142
2143 /* Compute new watermarks for the pipe */
2144 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2145                                   const struct ilk_pipe_wm_parameters *params,
2146                                   struct intel_pipe_wm *pipe_wm)
2147 {
2148         struct drm_device *dev = crtc->dev;
2149         const struct drm_i915_private *dev_priv = dev->dev_private;
2150         int level, max_level = ilk_wm_max_level(dev);
2151         /* LP0 watermark maximums depend on this pipe alone */
2152         struct intel_wm_config config = {
2153                 .num_pipes_active = 1,
2154                 .sprites_enabled = params->spr.enabled,
2155                 .sprites_scaled = params->spr.scaled,
2156         };
2157         struct ilk_wm_maximums max;
2158
2159         /* LP0 watermarks always use 1/2 DDB partitioning */
2160         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2161
2162         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2163         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2164                 max_level = 1;
2165
2166         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2167         if (params->spr.scaled)
2168                 max_level = 0;
2169
2170         for (level = 0; level <= max_level; level++)
2171                 ilk_compute_wm_level(dev_priv, level, params,
2172                                      &pipe_wm->wm[level]);
2173
2174         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2175                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2176
2177         /* At least LP0 must be valid */
2178         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2179 }
2180
2181 /*
2182  * Merge the watermarks from all active pipes for a specific level.
2183  */
2184 static void ilk_merge_wm_level(struct drm_device *dev,
2185                                int level,
2186                                struct intel_wm_level *ret_wm)
2187 {
2188         const struct intel_crtc *intel_crtc;
2189
2190         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2191                 const struct intel_wm_level *wm =
2192                         &intel_crtc->wm.active.wm[level];
2193
2194                 if (!wm->enable)
2195                         return;
2196
2197                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2198                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2199                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2200                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2201         }
2202
2203         ret_wm->enable = true;
2204 }
2205
2206 /*
2207  * Merge all low power watermarks for all active pipes.
2208  */
2209 static void ilk_wm_merge(struct drm_device *dev,
2210                          const struct intel_wm_config *config,
2211                          const struct ilk_wm_maximums *max,
2212                          struct intel_pipe_wm *merged)
2213 {
2214         int level, max_level = ilk_wm_max_level(dev);
2215
2216         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2217         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2218             config->num_pipes_active > 1)
2219                 return;
2220
2221         /* ILK: FBC WM must be disabled always */
2222         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2223
2224         /* merge each WM1+ level */
2225         for (level = 1; level <= max_level; level++) {
2226                 struct intel_wm_level *wm = &merged->wm[level];
2227
2228                 ilk_merge_wm_level(dev, level, wm);
2229
2230                 if (!ilk_validate_wm_level(level, max, wm))
2231                         break;
2232
2233                 /*
2234                  * The spec says it is preferred to disable
2235                  * FBC WMs instead of disabling a WM level.
2236                  */
2237                 if (wm->fbc_val > max->fbc) {
2238                         merged->fbc_wm_enabled = false;
2239                         wm->fbc_val = 0;
2240                 }
2241         }
2242
2243         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2244         /*
2245          * FIXME this is racy. FBC might get enabled later.
2246          * What we should check here is whether FBC can be
2247          * enabled sometime later.
2248          */
2249         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2250                 for (level = 2; level <= max_level; level++) {
2251                         struct intel_wm_level *wm = &merged->wm[level];
2252
2253                         wm->enable = false;
2254                 }
2255         }
2256 }
2257
2258 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2259 {
2260         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2261         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2262 }
2263
2264 /* The value we need to program into the WM_LPx latency field */
2265 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2266 {
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268
2269         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2270                 return 2 * level;
2271         else
2272                 return dev_priv->wm.pri_latency[level];
2273 }
2274
2275 static void ilk_compute_wm_results(struct drm_device *dev,
2276                                    const struct intel_pipe_wm *merged,
2277                                    enum intel_ddb_partitioning partitioning,
2278                                    struct ilk_wm_values *results)
2279 {
2280         struct intel_crtc *intel_crtc;
2281         int level, wm_lp;
2282
2283         results->enable_fbc_wm = merged->fbc_wm_enabled;
2284         results->partitioning = partitioning;
2285
2286         /* LP1+ register values */
2287         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2288                 const struct intel_wm_level *r;
2289
2290                 level = ilk_wm_lp_to_level(wm_lp, merged);
2291
2292                 r = &merged->wm[level];
2293                 if (!r->enable)
2294                         break;
2295
2296                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2297                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2298                         (r->pri_val << WM1_LP_SR_SHIFT) |
2299                         r->cur_val;
2300
2301                 if (INTEL_INFO(dev)->gen >= 8)
2302                         results->wm_lp[wm_lp - 1] |=
2303                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2304                 else
2305                         results->wm_lp[wm_lp - 1] |=
2306                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2307
2308                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2309                         WARN_ON(wm_lp != 1);
2310                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2311                 } else
2312                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2313         }
2314
2315         /* LP0 register values */
2316         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2317                 enum pipe pipe = intel_crtc->pipe;
2318                 const struct intel_wm_level *r =
2319                         &intel_crtc->wm.active.wm[0];
2320
2321                 if (WARN_ON(!r->enable))
2322                         continue;
2323
2324                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2325
2326                 results->wm_pipe[pipe] =
2327                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2328                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2329                         r->cur_val;
2330         }
2331 }
2332
2333 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2334  * case both are at the same level. Prefer r1 in case they're the same. */
2335 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2336                                                   struct intel_pipe_wm *r1,
2337                                                   struct intel_pipe_wm *r2)
2338 {
2339         int level, max_level = ilk_wm_max_level(dev);
2340         int level1 = 0, level2 = 0;
2341
2342         for (level = 1; level <= max_level; level++) {
2343                 if (r1->wm[level].enable)
2344                         level1 = level;
2345                 if (r2->wm[level].enable)
2346                         level2 = level;
2347         }
2348
2349         if (level1 == level2) {
2350                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2351                         return r2;
2352                 else
2353                         return r1;
2354         } else if (level1 > level2) {
2355                 return r1;
2356         } else {
2357                 return r2;
2358         }
2359 }
2360
2361 /* dirty bits used to track which watermarks need changes */
2362 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2363 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2364 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2365 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2366 #define WM_DIRTY_FBC (1 << 24)
2367 #define WM_DIRTY_DDB (1 << 25)
2368
2369 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2370                                          const struct ilk_wm_values *old,
2371                                          const struct ilk_wm_values *new)
2372 {
2373         unsigned int dirty = 0;
2374         enum pipe pipe;
2375         int wm_lp;
2376
2377         for_each_pipe(pipe) {
2378                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2379                         dirty |= WM_DIRTY_LINETIME(pipe);
2380                         /* Must disable LP1+ watermarks too */
2381                         dirty |= WM_DIRTY_LP_ALL;
2382                 }
2383
2384                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2385                         dirty |= WM_DIRTY_PIPE(pipe);
2386                         /* Must disable LP1+ watermarks too */
2387                         dirty |= WM_DIRTY_LP_ALL;
2388                 }
2389         }
2390
2391         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2392                 dirty |= WM_DIRTY_FBC;
2393                 /* Must disable LP1+ watermarks too */
2394                 dirty |= WM_DIRTY_LP_ALL;
2395         }
2396
2397         if (old->partitioning != new->partitioning) {
2398                 dirty |= WM_DIRTY_DDB;
2399                 /* Must disable LP1+ watermarks too */
2400                 dirty |= WM_DIRTY_LP_ALL;
2401         }
2402
2403         /* LP1+ watermarks already deemed dirty, no need to continue */
2404         if (dirty & WM_DIRTY_LP_ALL)
2405                 return dirty;
2406
2407         /* Find the lowest numbered LP1+ watermark in need of an update... */
2408         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2409                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2410                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2411                         break;
2412         }
2413
2414         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2415         for (; wm_lp <= 3; wm_lp++)
2416                 dirty |= WM_DIRTY_LP(wm_lp);
2417
2418         return dirty;
2419 }
2420
2421 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2422                                unsigned int dirty)
2423 {
2424         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2425         bool changed = false;
2426
2427         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2428                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2429                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2430                 changed = true;
2431         }
2432         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2433                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2434                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2435                 changed = true;
2436         }
2437         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2438                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2439                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2440                 changed = true;
2441         }
2442
2443         /*
2444          * Don't touch WM1S_LP_EN here.
2445          * Doing so could cause underruns.
2446          */
2447
2448         return changed;
2449 }
2450
2451 /*
2452  * The spec says we shouldn't write when we don't need, because every write
2453  * causes WMs to be re-evaluated, expending some power.
2454  */
2455 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2456                                 struct ilk_wm_values *results)
2457 {
2458         struct drm_device *dev = dev_priv->dev;
2459         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2460         unsigned int dirty;
2461         uint32_t val;
2462
2463         dirty = ilk_compute_wm_dirty(dev, previous, results);
2464         if (!dirty)
2465                 return;
2466
2467         _ilk_disable_lp_wm(dev_priv, dirty);
2468
2469         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2470                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2471         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2472                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2473         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2474                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2475
2476         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2477                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2478         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2479                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2480         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2481                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2482
2483         if (dirty & WM_DIRTY_DDB) {
2484                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2485                         val = I915_READ(WM_MISC);
2486                         if (results->partitioning == INTEL_DDB_PART_1_2)
2487                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2488                         else
2489                                 val |= WM_MISC_DATA_PARTITION_5_6;
2490                         I915_WRITE(WM_MISC, val);
2491                 } else {
2492                         val = I915_READ(DISP_ARB_CTL2);
2493                         if (results->partitioning == INTEL_DDB_PART_1_2)
2494                                 val &= ~DISP_DATA_PARTITION_5_6;
2495                         else
2496                                 val |= DISP_DATA_PARTITION_5_6;
2497                         I915_WRITE(DISP_ARB_CTL2, val);
2498                 }
2499         }
2500
2501         if (dirty & WM_DIRTY_FBC) {
2502                 val = I915_READ(DISP_ARB_CTL);
2503                 if (results->enable_fbc_wm)
2504                         val &= ~DISP_FBC_WM_DIS;
2505                 else
2506                         val |= DISP_FBC_WM_DIS;
2507                 I915_WRITE(DISP_ARB_CTL, val);
2508         }
2509
2510         if (dirty & WM_DIRTY_LP(1) &&
2511             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2512                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2513
2514         if (INTEL_INFO(dev)->gen >= 7) {
2515                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2516                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2517                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2518                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2519         }
2520
2521         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2522                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2523         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2524                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2525         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2526                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2527
2528         dev_priv->wm.hw = *results;
2529 }
2530
2531 static bool ilk_disable_lp_wm(struct drm_device *dev)
2532 {
2533         struct drm_i915_private *dev_priv = dev->dev_private;
2534
2535         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2536 }
2537
2538 static void ilk_update_wm(struct drm_crtc *crtc)
2539 {
2540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2541         struct drm_device *dev = crtc->dev;
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         struct ilk_wm_maximums max;
2544         struct ilk_pipe_wm_parameters params = {};
2545         struct ilk_wm_values results = {};
2546         enum intel_ddb_partitioning partitioning;
2547         struct intel_pipe_wm pipe_wm = {};
2548         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2549         struct intel_wm_config config = {};
2550
2551         ilk_compute_wm_parameters(crtc, &params, &config);
2552
2553         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2554
2555         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2556                 return;
2557
2558         intel_crtc->wm.active = pipe_wm;
2559
2560         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2561         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2562
2563         /* 5/6 split only in single pipe config on IVB+ */
2564         if (INTEL_INFO(dev)->gen >= 7 &&
2565             config.num_pipes_active == 1 && config.sprites_enabled) {
2566                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2567                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2568
2569                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2570         } else {
2571                 best_lp_wm = &lp_wm_1_2;
2572         }
2573
2574         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2575                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2576
2577         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2578
2579         ilk_write_wm_values(dev_priv, &results);
2580 }
2581
2582 static void ilk_update_sprite_wm(struct drm_plane *plane,
2583                                      struct drm_crtc *crtc,
2584                                      uint32_t sprite_width, int pixel_size,
2585                                      bool enabled, bool scaled)
2586 {
2587         struct drm_device *dev = plane->dev;
2588         struct intel_plane *intel_plane = to_intel_plane(plane);
2589
2590         intel_plane->wm.enabled = enabled;
2591         intel_plane->wm.scaled = scaled;
2592         intel_plane->wm.horiz_pixels = sprite_width;
2593         intel_plane->wm.bytes_per_pixel = pixel_size;
2594
2595         /*
2596          * IVB workaround: must disable low power watermarks for at least
2597          * one frame before enabling scaling.  LP watermarks can be re-enabled
2598          * when scaling is disabled.
2599          *
2600          * WaCxSRDisabledForSpriteScaling:ivb
2601          */
2602         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2603                 intel_wait_for_vblank(dev, intel_plane->pipe);
2604
2605         ilk_update_wm(crtc);
2606 }
2607
2608 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2609 {
2610         struct drm_device *dev = crtc->dev;
2611         struct drm_i915_private *dev_priv = dev->dev_private;
2612         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2615         enum pipe pipe = intel_crtc->pipe;
2616         static const unsigned int wm0_pipe_reg[] = {
2617                 [PIPE_A] = WM0_PIPEA_ILK,
2618                 [PIPE_B] = WM0_PIPEB_ILK,
2619                 [PIPE_C] = WM0_PIPEC_IVB,
2620         };
2621
2622         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2623         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2624                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2625
2626         if (intel_crtc_active(crtc)) {
2627                 u32 tmp = hw->wm_pipe[pipe];
2628
2629                 /*
2630                  * For active pipes LP0 watermark is marked as
2631                  * enabled, and LP1+ watermaks as disabled since
2632                  * we can't really reverse compute them in case
2633                  * multiple pipes are active.
2634                  */
2635                 active->wm[0].enable = true;
2636                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2637                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2638                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2639                 active->linetime = hw->wm_linetime[pipe];
2640         } else {
2641                 int level, max_level = ilk_wm_max_level(dev);
2642
2643                 /*
2644                  * For inactive pipes, all watermark levels
2645                  * should be marked as enabled but zeroed,
2646                  * which is what we'd compute them to.
2647                  */
2648                 for (level = 0; level <= max_level; level++)
2649                         active->wm[level].enable = true;
2650         }
2651 }
2652
2653 void ilk_wm_get_hw_state(struct drm_device *dev)
2654 {
2655         struct drm_i915_private *dev_priv = dev->dev_private;
2656         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2657         struct drm_crtc *crtc;
2658
2659         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2660                 ilk_pipe_wm_get_hw_state(crtc);
2661
2662         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2663         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2664         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2665
2666         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2667         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2668         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2669
2670         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2671                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2672                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2673         else if (IS_IVYBRIDGE(dev))
2674                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2675                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2676
2677         hw->enable_fbc_wm =
2678                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2679 }
2680
2681 /**
2682  * intel_update_watermarks - update FIFO watermark values based on current modes
2683  *
2684  * Calculate watermark values for the various WM regs based on current mode
2685  * and plane configuration.
2686  *
2687  * There are several cases to deal with here:
2688  *   - normal (i.e. non-self-refresh)
2689  *   - self-refresh (SR) mode
2690  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2691  *   - lines are small relative to FIFO size (buffer can hold more than 2
2692  *     lines), so need to account for TLB latency
2693  *
2694  *   The normal calculation is:
2695  *     watermark = dotclock * bytes per pixel * latency
2696  *   where latency is platform & configuration dependent (we assume pessimal
2697  *   values here).
2698  *
2699  *   The SR calculation is:
2700  *     watermark = (trunc(latency/line time)+1) * surface width *
2701  *       bytes per pixel
2702  *   where
2703  *     line time = htotal / dotclock
2704  *     surface width = hdisplay for normal plane and 64 for cursor
2705  *   and latency is assumed to be high, as above.
2706  *
2707  * The final value programmed to the register should always be rounded up,
2708  * and include an extra 2 entries to account for clock crossings.
2709  *
2710  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2711  * to set the non-SR watermarks to 8.
2712  */
2713 void intel_update_watermarks(struct drm_crtc *crtc)
2714 {
2715         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2716
2717         if (dev_priv->display.update_wm)
2718                 dev_priv->display.update_wm(crtc);
2719 }
2720
2721 void intel_update_sprite_watermarks(struct drm_plane *plane,
2722                                     struct drm_crtc *crtc,
2723                                     uint32_t sprite_width, int pixel_size,
2724                                     bool enabled, bool scaled)
2725 {
2726         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2727
2728         if (dev_priv->display.update_sprite_wm)
2729                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2730                                                    pixel_size, enabled, scaled);
2731 }
2732
2733 static struct drm_i915_gem_object *
2734 intel_alloc_context_page(struct drm_device *dev)
2735 {
2736         struct drm_i915_gem_object *ctx;
2737         int ret;
2738
2739         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2740
2741         ctx = i915_gem_alloc_object(dev, 4096);
2742         if (!ctx) {
2743                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2744                 return NULL;
2745         }
2746
2747         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2748         if (ret) {
2749                 DRM_ERROR("failed to pin power context: %d\n", ret);
2750                 goto err_unref;
2751         }
2752
2753         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2754         if (ret) {
2755                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2756                 goto err_unpin;
2757         }
2758
2759         return ctx;
2760
2761 err_unpin:
2762         i915_gem_object_ggtt_unpin(ctx);
2763 err_unref:
2764         drm_gem_object_unreference(&ctx->base);
2765         return NULL;
2766 }
2767
2768 /**
2769  * Lock protecting IPS related data structures
2770  */
2771 DEFINE_SPINLOCK(mchdev_lock);
2772
2773 /* Global for IPS driver to get at the current i915 device. Protected by
2774  * mchdev_lock. */
2775 static struct drm_i915_private *i915_mch_dev;
2776
2777 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2778 {
2779         struct drm_i915_private *dev_priv = dev->dev_private;
2780         u16 rgvswctl;
2781
2782         assert_spin_locked(&mchdev_lock);
2783
2784         rgvswctl = I915_READ16(MEMSWCTL);
2785         if (rgvswctl & MEMCTL_CMD_STS) {
2786                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2787                 return false; /* still busy with another command */
2788         }
2789
2790         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2791                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2792         I915_WRITE16(MEMSWCTL, rgvswctl);
2793         POSTING_READ16(MEMSWCTL);
2794
2795         rgvswctl |= MEMCTL_CMD_STS;
2796         I915_WRITE16(MEMSWCTL, rgvswctl);
2797
2798         return true;
2799 }
2800
2801 static void ironlake_enable_drps(struct drm_device *dev)
2802 {
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         u32 rgvmodectl = I915_READ(MEMMODECTL);
2805         u8 fmax, fmin, fstart, vstart;
2806
2807         spin_lock_irq(&mchdev_lock);
2808
2809         /* Enable temp reporting */
2810         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2811         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2812
2813         /* 100ms RC evaluation intervals */
2814         I915_WRITE(RCUPEI, 100000);
2815         I915_WRITE(RCDNEI, 100000);
2816
2817         /* Set max/min thresholds to 90ms and 80ms respectively */
2818         I915_WRITE(RCBMAXAVG, 90000);
2819         I915_WRITE(RCBMINAVG, 80000);
2820
2821         I915_WRITE(MEMIHYST, 1);
2822
2823         /* Set up min, max, and cur for interrupt handling */
2824         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2825         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2826         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2827                 MEMMODE_FSTART_SHIFT;
2828
2829         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2830                 PXVFREQ_PX_SHIFT;
2831
2832         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2833         dev_priv->ips.fstart = fstart;
2834
2835         dev_priv->ips.max_delay = fstart;
2836         dev_priv->ips.min_delay = fmin;
2837         dev_priv->ips.cur_delay = fstart;
2838
2839         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2840                          fmax, fmin, fstart);
2841
2842         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2843
2844         /*
2845          * Interrupts will be enabled in ironlake_irq_postinstall
2846          */
2847
2848         I915_WRITE(VIDSTART, vstart);
2849         POSTING_READ(VIDSTART);
2850
2851         rgvmodectl |= MEMMODE_SWMODE_EN;
2852         I915_WRITE(MEMMODECTL, rgvmodectl);
2853
2854         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2855                 DRM_ERROR("stuck trying to change perf mode\n");
2856         mdelay(1);
2857
2858         ironlake_set_drps(dev, fstart);
2859
2860         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2861                 I915_READ(0x112e0);
2862         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2863         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2864         getrawmonotonic(&dev_priv->ips.last_time2);
2865
2866         spin_unlock_irq(&mchdev_lock);
2867 }
2868
2869 static void ironlake_disable_drps(struct drm_device *dev)
2870 {
2871         struct drm_i915_private *dev_priv = dev->dev_private;
2872         u16 rgvswctl;
2873
2874         spin_lock_irq(&mchdev_lock);
2875
2876         rgvswctl = I915_READ16(MEMSWCTL);
2877
2878         /* Ack interrupts, disable EFC interrupt */
2879         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2880         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2881         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2882         I915_WRITE(DEIIR, DE_PCU_EVENT);
2883         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2884
2885         /* Go back to the starting frequency */
2886         ironlake_set_drps(dev, dev_priv->ips.fstart);
2887         mdelay(1);
2888         rgvswctl |= MEMCTL_CMD_STS;
2889         I915_WRITE(MEMSWCTL, rgvswctl);
2890         mdelay(1);
2891
2892         spin_unlock_irq(&mchdev_lock);
2893 }
2894
2895 /* There's a funny hw issue where the hw returns all 0 when reading from
2896  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2897  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2898  * all limits and the gpu stuck at whatever frequency it is at atm).
2899  */
2900 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2901 {
2902         u32 limits;
2903
2904         /* Only set the down limit when we've reached the lowest level to avoid
2905          * getting more interrupts, otherwise leave this clear. This prevents a
2906          * race in the hw when coming out of rc6: There's a tiny window where
2907          * the hw runs at the minimal clock before selecting the desired
2908          * frequency, if the down threshold expires in that window we will not
2909          * receive a down interrupt. */
2910         limits = dev_priv->rps.max_freq_softlimit << 24;
2911         if (val <= dev_priv->rps.min_freq_softlimit)
2912                 limits |= dev_priv->rps.min_freq_softlimit << 16;
2913
2914         return limits;
2915 }
2916
2917 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2918 {
2919         int new_power;
2920
2921         new_power = dev_priv->rps.power;
2922         switch (dev_priv->rps.power) {
2923         case LOW_POWER:
2924                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
2925                         new_power = BETWEEN;
2926                 break;
2927
2928         case BETWEEN:
2929                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
2930                         new_power = LOW_POWER;
2931                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
2932                         new_power = HIGH_POWER;
2933                 break;
2934
2935         case HIGH_POWER:
2936                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
2937                         new_power = BETWEEN;
2938                 break;
2939         }
2940         /* Max/min bins are special */
2941         if (val == dev_priv->rps.min_freq_softlimit)
2942                 new_power = LOW_POWER;
2943         if (val == dev_priv->rps.max_freq_softlimit)
2944                 new_power = HIGH_POWER;
2945         if (new_power == dev_priv->rps.power)
2946                 return;
2947
2948         /* Note the units here are not exactly 1us, but 1280ns. */
2949         switch (new_power) {
2950         case LOW_POWER:
2951                 /* Upclock if more than 95% busy over 16ms */
2952                 I915_WRITE(GEN6_RP_UP_EI, 12500);
2953                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2954
2955                 /* Downclock if less than 85% busy over 32ms */
2956                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2957                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2958
2959                 I915_WRITE(GEN6_RP_CONTROL,
2960                            GEN6_RP_MEDIA_TURBO |
2961                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2962                            GEN6_RP_MEDIA_IS_GFX |
2963                            GEN6_RP_ENABLE |
2964                            GEN6_RP_UP_BUSY_AVG |
2965                            GEN6_RP_DOWN_IDLE_AVG);
2966                 break;
2967
2968         case BETWEEN:
2969                 /* Upclock if more than 90% busy over 13ms */
2970                 I915_WRITE(GEN6_RP_UP_EI, 10250);
2971                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2972
2973                 /* Downclock if less than 75% busy over 32ms */
2974                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2975                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2976
2977                 I915_WRITE(GEN6_RP_CONTROL,
2978                            GEN6_RP_MEDIA_TURBO |
2979                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2980                            GEN6_RP_MEDIA_IS_GFX |
2981                            GEN6_RP_ENABLE |
2982                            GEN6_RP_UP_BUSY_AVG |
2983                            GEN6_RP_DOWN_IDLE_AVG);
2984                 break;
2985
2986         case HIGH_POWER:
2987                 /* Upclock if more than 85% busy over 10ms */
2988                 I915_WRITE(GEN6_RP_UP_EI, 8000);
2989                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2990
2991                 /* Downclock if less than 60% busy over 32ms */
2992                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2993                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2994
2995                 I915_WRITE(GEN6_RP_CONTROL,
2996                            GEN6_RP_MEDIA_TURBO |
2997                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
2998                            GEN6_RP_MEDIA_IS_GFX |
2999                            GEN6_RP_ENABLE |
3000                            GEN6_RP_UP_BUSY_AVG |
3001                            GEN6_RP_DOWN_IDLE_AVG);
3002                 break;
3003         }
3004
3005         dev_priv->rps.power = new_power;
3006         dev_priv->rps.last_adj = 0;
3007 }
3008
3009 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3010 {
3011         u32 mask = 0;
3012
3013         if (val > dev_priv->rps.min_freq_softlimit)
3014                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3015         if (val < dev_priv->rps.max_freq_softlimit)
3016                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3017
3018         /* IVB and SNB hard hangs on looping batchbuffer
3019          * if GEN6_PM_UP_EI_EXPIRED is masked.
3020          */
3021         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3022                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3023
3024         return ~mask;
3025 }
3026
3027 /* gen6_set_rps is called to update the frequency request, but should also be
3028  * called when the range (min_delay and max_delay) is modified so that we can
3029  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3030 void gen6_set_rps(struct drm_device *dev, u8 val)
3031 {
3032         struct drm_i915_private *dev_priv = dev->dev_private;
3033
3034         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3035         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3036         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3037
3038         /* min/max delay may still have been modified so be sure to
3039          * write the limits value.
3040          */
3041         if (val != dev_priv->rps.cur_freq) {
3042                 gen6_set_rps_thresholds(dev_priv, val);
3043
3044                 if (IS_HASWELL(dev))
3045                         I915_WRITE(GEN6_RPNSWREQ,
3046                                    HSW_FREQUENCY(val));
3047                 else
3048                         I915_WRITE(GEN6_RPNSWREQ,
3049                                    GEN6_FREQUENCY(val) |
3050                                    GEN6_OFFSET(0) |
3051                                    GEN6_AGGRESSIVE_TURBO);
3052         }
3053
3054         /* Make sure we continue to get interrupts
3055          * until we hit the minimum or maximum frequencies.
3056          */
3057         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3058         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3059
3060         POSTING_READ(GEN6_RPNSWREQ);
3061
3062         dev_priv->rps.cur_freq = val;
3063         trace_intel_gpu_freq_change(val * 50);
3064 }
3065
3066 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3067  *
3068  * * If Gfx is Idle, then
3069  * 1. Mask Turbo interrupts
3070  * 2. Bring up Gfx clock
3071  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3072  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3073  * 5. Unmask Turbo interrupts
3074 */
3075 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3076 {
3077         /*
3078          * When we are idle.  Drop to min voltage state.
3079          */
3080
3081         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3082                 return;
3083
3084         /* Mask turbo interrupt so that they will not come in between */
3085         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3086
3087         /* Bring up the Gfx clock */
3088         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3089                 I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
3090                                 VLV_GFX_CLK_FORCE_ON_BIT);
3091
3092         if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
3093                 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
3094                         DRM_ERROR("GFX_CLK_ON request timed out\n");
3095                 return;
3096         }
3097
3098         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3099
3100         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3101                                         dev_priv->rps.min_freq_softlimit);
3102
3103         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3104                                 & GENFREQSTATUS) == 0, 5))
3105                 DRM_ERROR("timed out waiting for Punit\n");
3106
3107         /* Release the Gfx clock */
3108         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3109                 I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
3110                                 ~VLV_GFX_CLK_FORCE_ON_BIT);
3111
3112         I915_WRITE(GEN6_PMINTRMSK,
3113                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3114 }
3115
3116 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3117 {
3118         struct drm_device *dev = dev_priv->dev;
3119
3120         mutex_lock(&dev_priv->rps.hw_lock);
3121         if (dev_priv->rps.enabled) {
3122                 if (IS_VALLEYVIEW(dev))
3123                         vlv_set_rps_idle(dev_priv);
3124                 else
3125                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3126                 dev_priv->rps.last_adj = 0;
3127         }
3128         mutex_unlock(&dev_priv->rps.hw_lock);
3129 }
3130
3131 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3132 {
3133         struct drm_device *dev = dev_priv->dev;
3134
3135         mutex_lock(&dev_priv->rps.hw_lock);
3136         if (dev_priv->rps.enabled) {
3137                 if (IS_VALLEYVIEW(dev))
3138                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3139                 else
3140                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3141                 dev_priv->rps.last_adj = 0;
3142         }
3143         mutex_unlock(&dev_priv->rps.hw_lock);
3144 }
3145
3146 void valleyview_set_rps(struct drm_device *dev, u8 val)
3147 {
3148         struct drm_i915_private *dev_priv = dev->dev_private;
3149
3150         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3151         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3152         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3153
3154         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3155                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3156                          dev_priv->rps.cur_freq,
3157                          vlv_gpu_freq(dev_priv, val), val);
3158
3159         if (val != dev_priv->rps.cur_freq)
3160                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3161
3162         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3163
3164         dev_priv->rps.cur_freq = val;
3165         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3166 }
3167
3168 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3169 {
3170         struct drm_i915_private *dev_priv = dev->dev_private;
3171
3172         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3173         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3174                                 ~dev_priv->pm_rps_events);
3175         /* Complete PM interrupt masking here doesn't race with the rps work
3176          * item again unmasking PM interrupts because that is using a different
3177          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3178          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3179
3180         spin_lock_irq(&dev_priv->irq_lock);
3181         dev_priv->rps.pm_iir = 0;
3182         spin_unlock_irq(&dev_priv->irq_lock);
3183
3184         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3185 }
3186
3187 static void gen6_disable_rps(struct drm_device *dev)
3188 {
3189         struct drm_i915_private *dev_priv = dev->dev_private;
3190
3191         I915_WRITE(GEN6_RC_CONTROL, 0);
3192         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3193
3194         gen6_disable_rps_interrupts(dev);
3195 }
3196
3197 static void valleyview_disable_rps(struct drm_device *dev)
3198 {
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200
3201         I915_WRITE(GEN6_RC_CONTROL, 0);
3202
3203         gen6_disable_rps_interrupts(dev);
3204 }
3205
3206 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3207 {
3208         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3209                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3210                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3211                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3212 }
3213
3214 int intel_enable_rc6(const struct drm_device *dev)
3215 {
3216         /* No RC6 before Ironlake */
3217         if (INTEL_INFO(dev)->gen < 5)
3218                 return 0;
3219
3220         /* Respect the kernel parameter if it is set */
3221         if (i915.enable_rc6 >= 0)
3222                 return i915.enable_rc6;
3223
3224         /* Disable RC6 on Ironlake */
3225         if (INTEL_INFO(dev)->gen == 5)
3226                 return 0;
3227
3228         if (IS_IVYBRIDGE(dev))
3229                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3230
3231         return INTEL_RC6_ENABLE;
3232 }
3233
3234 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3235 {
3236         struct drm_i915_private *dev_priv = dev->dev_private;
3237
3238         spin_lock_irq(&dev_priv->irq_lock);
3239         WARN_ON(dev_priv->rps.pm_iir);
3240         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3241         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3242         spin_unlock_irq(&dev_priv->irq_lock);
3243 }
3244
3245 static void gen8_enable_rps(struct drm_device *dev)
3246 {
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         struct intel_ring_buffer *ring;
3249         uint32_t rc6_mask = 0, rp_state_cap;
3250         int unused;
3251
3252         /* 1a: Software RC state - RC0 */
3253         I915_WRITE(GEN6_RC_STATE, 0);
3254
3255         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3256          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3257         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3258
3259         /* 2a: Disable RC states. */
3260         I915_WRITE(GEN6_RC_CONTROL, 0);
3261
3262         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3263
3264         /* 2b: Program RC6 thresholds.*/
3265         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3266         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3267         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3268         for_each_ring(ring, dev_priv, unused)
3269                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3270         I915_WRITE(GEN6_RC_SLEEP, 0);
3271         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3272
3273         /* 3: Enable RC6 */
3274         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3275                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3276         intel_print_rc6_info(dev, rc6_mask);
3277         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3278                                     GEN6_RC_CTL_EI_MODE(1) |
3279                                     rc6_mask);
3280
3281         /* 4 Program defaults and thresholds for RPS*/
3282         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3283         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3284         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3285         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3286
3287         /* Docs recommend 900MHz, and 300 MHz respectively */
3288         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3289                    dev_priv->rps.max_freq_softlimit << 24 |
3290                    dev_priv->rps.min_freq_softlimit << 16);
3291
3292         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3293         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3294         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3295         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3296
3297         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3298
3299         /* 5: Enable RPS */
3300         I915_WRITE(GEN6_RP_CONTROL,
3301                    GEN6_RP_MEDIA_TURBO |
3302                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3303                    GEN6_RP_MEDIA_IS_GFX |
3304                    GEN6_RP_ENABLE |
3305                    GEN6_RP_UP_BUSY_AVG |
3306                    GEN6_RP_DOWN_IDLE_AVG);
3307
3308         /* 6: Ring frequency + overclocking (our driver does this later */
3309
3310         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3311
3312         gen6_enable_rps_interrupts(dev);
3313
3314         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3315 }
3316
3317 static void gen6_enable_rps(struct drm_device *dev)
3318 {
3319         struct drm_i915_private *dev_priv = dev->dev_private;
3320         struct intel_ring_buffer *ring;
3321         u32 rp_state_cap;
3322         u32 gt_perf_status;
3323         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3324         u32 gtfifodbg;
3325         int rc6_mode;
3326         int i, ret;
3327
3328         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3329
3330         /* Here begins a magic sequence of register writes to enable
3331          * auto-downclocking.
3332          *
3333          * Perhaps there might be some value in exposing these to
3334          * userspace...
3335          */
3336         I915_WRITE(GEN6_RC_STATE, 0);
3337
3338         /* Clear the DBG now so we don't confuse earlier errors */
3339         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3340                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3341                 I915_WRITE(GTFIFODBG, gtfifodbg);
3342         }
3343
3344         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3345
3346         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3347         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3348
3349         /* All of these values are in units of 50MHz */
3350         dev_priv->rps.cur_freq          = 0;
3351         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3352         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3353         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3354         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3355         /* XXX: only BYT has a special efficient freq */
3356         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3357         /* hw_max = RP0 until we check for overclocking */
3358         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3359
3360         /* Preserve min/max settings in case of re-init */
3361         if (dev_priv->rps.max_freq_softlimit == 0)
3362                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3363
3364         if (dev_priv->rps.min_freq_softlimit == 0)
3365                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3366
3367         /* disable the counters and set deterministic thresholds */
3368         I915_WRITE(GEN6_RC_CONTROL, 0);
3369
3370         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3371         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3372         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3373         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3374         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3375
3376         for_each_ring(ring, dev_priv, i)
3377                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3378
3379         I915_WRITE(GEN6_RC_SLEEP, 0);
3380         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3381         if (IS_IVYBRIDGE(dev))
3382                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3383         else
3384                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3385         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3386         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3387
3388         /* Check if we are enabling RC6 */
3389         rc6_mode = intel_enable_rc6(dev_priv->dev);
3390         if (rc6_mode & INTEL_RC6_ENABLE)
3391                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3392
3393         /* We don't use those on Haswell */
3394         if (!IS_HASWELL(dev)) {
3395                 if (rc6_mode & INTEL_RC6p_ENABLE)
3396                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3397
3398                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3399                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3400         }
3401
3402         intel_print_rc6_info(dev, rc6_mask);
3403
3404         I915_WRITE(GEN6_RC_CONTROL,
3405                    rc6_mask |
3406                    GEN6_RC_CTL_EI_MODE(1) |
3407                    GEN6_RC_CTL_HW_ENABLE);
3408
3409         /* Power down if completely idle for over 50ms */
3410         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3411         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3412
3413         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3414         if (ret)
3415                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3416
3417         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3418         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3419                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3420                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3421                                  (pcu_mbox & 0xff) * 50);
3422                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3423         }
3424
3425         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3426         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3427
3428         gen6_enable_rps_interrupts(dev);
3429
3430         rc6vids = 0;
3431         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3432         if (IS_GEN6(dev) && ret) {
3433                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3434         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3435                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3436                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3437                 rc6vids &= 0xffff00;
3438                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3439                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3440                 if (ret)
3441                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3442         }
3443
3444         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3445 }
3446
3447 void gen6_update_ring_freq(struct drm_device *dev)
3448 {
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450         int min_freq = 15;
3451         unsigned int gpu_freq;
3452         unsigned int max_ia_freq, min_ring_freq;
3453         int scaling_factor = 180;
3454         struct cpufreq_policy *policy;
3455
3456         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3457
3458         policy = cpufreq_cpu_get(0);
3459         if (policy) {
3460                 max_ia_freq = policy->cpuinfo.max_freq;
3461                 cpufreq_cpu_put(policy);
3462         } else {
3463                 /*
3464                  * Default to measured freq if none found, PCU will ensure we
3465                  * don't go over
3466                  */
3467                 max_ia_freq = tsc_khz;
3468         }
3469
3470         /* Convert from kHz to MHz */
3471         max_ia_freq /= 1000;
3472
3473         min_ring_freq = I915_READ(DCLK) & 0xf;
3474         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3475         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3476
3477         /*
3478          * For each potential GPU frequency, load a ring frequency we'd like
3479          * to use for memory access.  We do this by specifying the IA frequency
3480          * the PCU should use as a reference to determine the ring frequency.
3481          */
3482         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3483              gpu_freq--) {
3484                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3485                 unsigned int ia_freq = 0, ring_freq = 0;
3486
3487                 if (INTEL_INFO(dev)->gen >= 8) {
3488                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3489                         ring_freq = max(min_ring_freq, gpu_freq);
3490                 } else if (IS_HASWELL(dev)) {
3491                         ring_freq = mult_frac(gpu_freq, 5, 4);
3492                         ring_freq = max(min_ring_freq, ring_freq);
3493                         /* leave ia_freq as the default, chosen by cpufreq */
3494                 } else {
3495                         /* On older processors, there is no separate ring
3496                          * clock domain, so in order to boost the bandwidth
3497                          * of the ring, we need to upclock the CPU (ia_freq).
3498                          *
3499                          * For GPU frequencies less than 750MHz,
3500                          * just use the lowest ring freq.
3501                          */
3502                         if (gpu_freq < min_freq)
3503                                 ia_freq = 800;
3504                         else
3505                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3506                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3507                 }
3508
3509                 sandybridge_pcode_write(dev_priv,
3510                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3511                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3512                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3513                                         gpu_freq);
3514         }
3515 }
3516
3517 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3518 {
3519         u32 val, rp0;
3520
3521         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3522
3523         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3524         /* Clamp to max */
3525         rp0 = min_t(u32, rp0, 0xea);
3526
3527         return rp0;
3528 }
3529
3530 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3531 {
3532         u32 val, rpe;
3533
3534         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3535         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3536         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3537         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3538
3539         return rpe;
3540 }
3541
3542 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3543 {
3544         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3545 }
3546
3547 /* Check that the pctx buffer wasn't move under us. */
3548 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3549 {
3550         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3551
3552         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3553                              dev_priv->vlv_pctx->stolen->start);
3554 }
3555
3556 static void valleyview_setup_pctx(struct drm_device *dev)
3557 {
3558         struct drm_i915_private *dev_priv = dev->dev_private;
3559         struct drm_i915_gem_object *pctx;
3560         unsigned long pctx_paddr;
3561         u32 pcbr;
3562         int pctx_size = 24*1024;
3563
3564         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3565
3566         pcbr = I915_READ(VLV_PCBR);
3567         if (pcbr) {
3568                 /* BIOS set it up already, grab the pre-alloc'd space */
3569                 int pcbr_offset;
3570
3571                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3572                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3573                                                                       pcbr_offset,
3574                                                                       I915_GTT_OFFSET_NONE,
3575                                                                       pctx_size);
3576                 goto out;
3577         }
3578
3579         /*
3580          * From the Gunit register HAS:
3581          * The Gfx driver is expected to program this register and ensure
3582          * proper allocation within Gfx stolen memory.  For example, this
3583          * register should be programmed such than the PCBR range does not
3584          * overlap with other ranges, such as the frame buffer, protected
3585          * memory, or any other relevant ranges.
3586          */
3587         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3588         if (!pctx) {
3589                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3590                 return;
3591         }
3592
3593         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3594         I915_WRITE(VLV_PCBR, pctx_paddr);
3595
3596 out:
3597         dev_priv->vlv_pctx = pctx;
3598 }
3599
3600 static void valleyview_cleanup_pctx(struct drm_device *dev)
3601 {
3602         struct drm_i915_private *dev_priv = dev->dev_private;
3603
3604         if (WARN_ON(!dev_priv->vlv_pctx))
3605                 return;
3606
3607         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3608         dev_priv->vlv_pctx = NULL;
3609 }
3610
3611 static void valleyview_enable_rps(struct drm_device *dev)
3612 {
3613         struct drm_i915_private *dev_priv = dev->dev_private;
3614         struct intel_ring_buffer *ring;
3615         u32 gtfifodbg, val, rc6_mode = 0;
3616         int i;
3617
3618         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3619
3620         valleyview_check_pctx(dev_priv);
3621
3622         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3623                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3624                                  gtfifodbg);
3625                 I915_WRITE(GTFIFODBG, gtfifodbg);
3626         }
3627
3628         /* If VLV, Forcewake all wells, else re-direct to regular path */
3629         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3630
3631         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3632         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3633         I915_WRITE(GEN6_RP_UP_EI, 66000);
3634         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3635
3636         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3637
3638         I915_WRITE(GEN6_RP_CONTROL,
3639                    GEN6_RP_MEDIA_TURBO |
3640                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3641                    GEN6_RP_MEDIA_IS_GFX |
3642                    GEN6_RP_ENABLE |
3643                    GEN6_RP_UP_BUSY_AVG |
3644                    GEN6_RP_DOWN_IDLE_CONT);
3645
3646         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3647         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3648         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3649
3650         for_each_ring(ring, dev_priv, i)
3651                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3652
3653         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3654
3655         /* allows RC6 residency counter to work */
3656         I915_WRITE(VLV_COUNTER_CONTROL,
3657                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3658                                       VLV_MEDIA_RC6_COUNT_EN |
3659                                       VLV_RENDER_RC6_COUNT_EN));
3660         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3661                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3662
3663         intel_print_rc6_info(dev, rc6_mode);
3664
3665         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3666
3667         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3668
3669         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3670         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3671
3672         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3673         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3674                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3675                          dev_priv->rps.cur_freq);
3676
3677         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3678         dev_priv->rps.rp0_freq  = dev_priv->rps.max_freq;
3679         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3680                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3681                          dev_priv->rps.max_freq);
3682
3683         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3684         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3685                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3686                          dev_priv->rps.efficient_freq);
3687
3688         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3689         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3690                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3691                          dev_priv->rps.min_freq);
3692
3693         /* Preserve min/max settings in case of re-init */
3694         if (dev_priv->rps.max_freq_softlimit == 0)
3695                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3696
3697         if (dev_priv->rps.min_freq_softlimit == 0)
3698                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3699
3700         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3701                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3702                          dev_priv->rps.efficient_freq);
3703
3704         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3705
3706         gen6_enable_rps_interrupts(dev);
3707
3708         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3709 }
3710
3711 void ironlake_teardown_rc6(struct drm_device *dev)
3712 {
3713         struct drm_i915_private *dev_priv = dev->dev_private;
3714
3715         if (dev_priv->ips.renderctx) {
3716                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3717                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3718                 dev_priv->ips.renderctx = NULL;
3719         }
3720
3721         if (dev_priv->ips.pwrctx) {
3722                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3723                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3724                 dev_priv->ips.pwrctx = NULL;
3725         }
3726 }
3727
3728 static void ironlake_disable_rc6(struct drm_device *dev)
3729 {
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731
3732         if (I915_READ(PWRCTXA)) {
3733                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3734                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3735                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3736                          50);
3737
3738                 I915_WRITE(PWRCTXA, 0);
3739                 POSTING_READ(PWRCTXA);
3740
3741                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3742                 POSTING_READ(RSTDBYCTL);
3743         }
3744 }
3745
3746 static int ironlake_setup_rc6(struct drm_device *dev)
3747 {
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749
3750         if (dev_priv->ips.renderctx == NULL)
3751                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3752         if (!dev_priv->ips.renderctx)
3753                 return -ENOMEM;
3754
3755         if (dev_priv->ips.pwrctx == NULL)
3756                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3757         if (!dev_priv->ips.pwrctx) {
3758                 ironlake_teardown_rc6(dev);
3759                 return -ENOMEM;
3760         }
3761
3762         return 0;
3763 }
3764
3765 static void ironlake_enable_rc6(struct drm_device *dev)
3766 {
3767         struct drm_i915_private *dev_priv = dev->dev_private;
3768         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3769         bool was_interruptible;
3770         int ret;
3771
3772         /* rc6 disabled by default due to repeated reports of hanging during
3773          * boot and resume.
3774          */
3775         if (!intel_enable_rc6(dev))
3776                 return;
3777
3778         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3779
3780         ret = ironlake_setup_rc6(dev);
3781         if (ret)
3782                 return;
3783
3784         was_interruptible = dev_priv->mm.interruptible;
3785         dev_priv->mm.interruptible = false;
3786
3787         /*
3788          * GPU can automatically power down the render unit if given a page
3789          * to save state.
3790          */
3791         ret = intel_ring_begin(ring, 6);
3792         if (ret) {
3793                 ironlake_teardown_rc6(dev);
3794                 dev_priv->mm.interruptible = was_interruptible;
3795                 return;
3796         }
3797
3798         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3799         intel_ring_emit(ring, MI_SET_CONTEXT);
3800         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3801                         MI_MM_SPACE_GTT |
3802                         MI_SAVE_EXT_STATE_EN |
3803                         MI_RESTORE_EXT_STATE_EN |
3804                         MI_RESTORE_INHIBIT);
3805         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3806         intel_ring_emit(ring, MI_NOOP);
3807         intel_ring_emit(ring, MI_FLUSH);
3808         intel_ring_advance(ring);
3809
3810         /*
3811          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3812          * does an implicit flush, combined with MI_FLUSH above, it should be
3813          * safe to assume that renderctx is valid
3814          */
3815         ret = intel_ring_idle(ring);
3816         dev_priv->mm.interruptible = was_interruptible;
3817         if (ret) {
3818                 DRM_ERROR("failed to enable ironlake power savings\n");
3819                 ironlake_teardown_rc6(dev);
3820                 return;
3821         }
3822
3823         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3824         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3825
3826         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
3827 }
3828
3829 static unsigned long intel_pxfreq(u32 vidfreq)
3830 {
3831         unsigned long freq;
3832         int div = (vidfreq & 0x3f0000) >> 16;
3833         int post = (vidfreq & 0x3000) >> 12;
3834         int pre = (vidfreq & 0x7);
3835
3836         if (!pre)
3837                 return 0;
3838
3839         freq = ((div * 133333) / ((1<<post) * pre));
3840
3841         return freq;
3842 }
3843
3844 static const struct cparams {
3845         u16 i;
3846         u16 t;
3847         u16 m;
3848         u16 c;
3849 } cparams[] = {
3850         { 1, 1333, 301, 28664 },
3851         { 1, 1066, 294, 24460 },
3852         { 1, 800, 294, 25192 },
3853         { 0, 1333, 276, 27605 },
3854         { 0, 1066, 276, 27605 },
3855         { 0, 800, 231, 23784 },
3856 };
3857
3858 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3859 {
3860         u64 total_count, diff, ret;
3861         u32 count1, count2, count3, m = 0, c = 0;
3862         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3863         int i;
3864
3865         assert_spin_locked(&mchdev_lock);
3866
3867         diff1 = now - dev_priv->ips.last_time1;
3868
3869         /* Prevent division-by-zero if we are asking too fast.
3870          * Also, we don't get interesting results if we are polling
3871          * faster than once in 10ms, so just return the saved value
3872          * in such cases.
3873          */
3874         if (diff1 <= 10)
3875                 return dev_priv->ips.chipset_power;
3876
3877         count1 = I915_READ(DMIEC);
3878         count2 = I915_READ(DDREC);
3879         count3 = I915_READ(CSIEC);
3880
3881         total_count = count1 + count2 + count3;
3882
3883         /* FIXME: handle per-counter overflow */
3884         if (total_count < dev_priv->ips.last_count1) {
3885                 diff = ~0UL - dev_priv->ips.last_count1;
3886                 diff += total_count;
3887         } else {
3888                 diff = total_count - dev_priv->ips.last_count1;
3889         }
3890
3891         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3892                 if (cparams[i].i == dev_priv->ips.c_m &&
3893                     cparams[i].t == dev_priv->ips.r_t) {
3894                         m = cparams[i].m;
3895                         c = cparams[i].c;
3896                         break;
3897                 }
3898         }
3899
3900         diff = div_u64(diff, diff1);
3901         ret = ((m * diff) + c);
3902         ret = div_u64(ret, 10);
3903
3904         dev_priv->ips.last_count1 = total_count;
3905         dev_priv->ips.last_time1 = now;
3906
3907         dev_priv->ips.chipset_power = ret;
3908
3909         return ret;
3910 }
3911
3912 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3913 {
3914         struct drm_device *dev = dev_priv->dev;
3915         unsigned long val;
3916
3917         if (INTEL_INFO(dev)->gen != 5)
3918                 return 0;
3919
3920         spin_lock_irq(&mchdev_lock);
3921
3922         val = __i915_chipset_val(dev_priv);
3923
3924         spin_unlock_irq(&mchdev_lock);
3925
3926         return val;
3927 }
3928
3929 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3930 {
3931         unsigned long m, x, b;
3932         u32 tsfs;
3933
3934         tsfs = I915_READ(TSFS);
3935
3936         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3937         x = I915_READ8(TR1);
3938
3939         b = tsfs & TSFS_INTR_MASK;
3940
3941         return ((m * x) / 127) - b;
3942 }
3943
3944 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3945 {
3946         struct drm_device *dev = dev_priv->dev;
3947         static const struct v_table {
3948                 u16 vd; /* in .1 mil */
3949                 u16 vm; /* in .1 mil */
3950         } v_table[] = {
3951                 { 0, 0, },
3952                 { 375, 0, },
3953                 { 500, 0, },
3954                 { 625, 0, },
3955                 { 750, 0, },
3956                 { 875, 0, },
3957                 { 1000, 0, },
3958                 { 1125, 0, },
3959                 { 4125, 3000, },
3960                 { 4125, 3000, },
3961                 { 4125, 3000, },
3962                 { 4125, 3000, },
3963                 { 4125, 3000, },
3964                 { 4125, 3000, },
3965                 { 4125, 3000, },
3966                 { 4125, 3000, },
3967                 { 4125, 3000, },
3968                 { 4125, 3000, },
3969                 { 4125, 3000, },
3970                 { 4125, 3000, },
3971                 { 4125, 3000, },
3972                 { 4125, 3000, },
3973                 { 4125, 3000, },
3974                 { 4125, 3000, },
3975                 { 4125, 3000, },
3976                 { 4125, 3000, },
3977                 { 4125, 3000, },
3978                 { 4125, 3000, },
3979                 { 4125, 3000, },
3980                 { 4125, 3000, },
3981                 { 4125, 3000, },
3982                 { 4125, 3000, },
3983                 { 4250, 3125, },
3984                 { 4375, 3250, },
3985                 { 4500, 3375, },
3986                 { 4625, 3500, },
3987                 { 4750, 3625, },
3988                 { 4875, 3750, },
3989                 { 5000, 3875, },
3990                 { 5125, 4000, },
3991                 { 5250, 4125, },
3992                 { 5375, 4250, },
3993                 { 5500, 4375, },
3994                 { 5625, 4500, },
3995                 { 5750, 4625, },
3996                 { 5875, 4750, },
3997                 { 6000, 4875, },
3998                 { 6125, 5000, },
3999                 { 6250, 5125, },
4000                 { 6375, 5250, },
4001                 { 6500, 5375, },
4002                 { 6625, 5500, },
4003                 { 6750, 5625, },
4004                 { 6875, 5750, },
4005                 { 7000, 5875, },
4006                 { 7125, 6000, },
4007                 { 7250, 6125, },
4008                 { 7375, 6250, },
4009                 { 7500, 6375, },
4010                 { 7625, 6500, },
4011                 { 7750, 6625, },
4012                 { 7875, 6750, },
4013                 { 8000, 6875, },
4014                 { 8125, 7000, },
4015                 { 8250, 7125, },
4016                 { 8375, 7250, },
4017                 { 8500, 7375, },
4018                 { 8625, 7500, },
4019                 { 8750, 7625, },
4020                 { 8875, 7750, },
4021                 { 9000, 7875, },
4022                 { 9125, 8000, },
4023                 { 9250, 8125, },
4024                 { 9375, 8250, },
4025                 { 9500, 8375, },
4026                 { 9625, 8500, },
4027                 { 9750, 8625, },
4028                 { 9875, 8750, },
4029                 { 10000, 8875, },
4030                 { 10125, 9000, },
4031                 { 10250, 9125, },
4032                 { 10375, 9250, },
4033                 { 10500, 9375, },
4034                 { 10625, 9500, },
4035                 { 10750, 9625, },
4036                 { 10875, 9750, },
4037                 { 11000, 9875, },
4038                 { 11125, 10000, },
4039                 { 11250, 10125, },
4040                 { 11375, 10250, },
4041                 { 11500, 10375, },
4042                 { 11625, 10500, },
4043                 { 11750, 10625, },
4044                 { 11875, 10750, },
4045                 { 12000, 10875, },
4046                 { 12125, 11000, },
4047                 { 12250, 11125, },
4048                 { 12375, 11250, },
4049                 { 12500, 11375, },
4050                 { 12625, 11500, },
4051                 { 12750, 11625, },
4052                 { 12875, 11750, },
4053                 { 13000, 11875, },
4054                 { 13125, 12000, },
4055                 { 13250, 12125, },
4056                 { 13375, 12250, },
4057                 { 13500, 12375, },
4058                 { 13625, 12500, },
4059                 { 13750, 12625, },
4060                 { 13875, 12750, },
4061                 { 14000, 12875, },
4062                 { 14125, 13000, },
4063                 { 14250, 13125, },
4064                 { 14375, 13250, },
4065                 { 14500, 13375, },
4066                 { 14625, 13500, },
4067                 { 14750, 13625, },
4068                 { 14875, 13750, },
4069                 { 15000, 13875, },
4070                 { 15125, 14000, },
4071                 { 15250, 14125, },
4072                 { 15375, 14250, },
4073                 { 15500, 14375, },
4074                 { 15625, 14500, },
4075                 { 15750, 14625, },
4076                 { 15875, 14750, },
4077                 { 16000, 14875, },
4078                 { 16125, 15000, },
4079         };
4080         if (INTEL_INFO(dev)->is_mobile)
4081                 return v_table[pxvid].vm;
4082         else
4083                 return v_table[pxvid].vd;
4084 }
4085
4086 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4087 {
4088         struct timespec now, diff1;
4089         u64 diff;
4090         unsigned long diffms;
4091         u32 count;
4092
4093         assert_spin_locked(&mchdev_lock);
4094
4095         getrawmonotonic(&now);
4096         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4097
4098         /* Don't divide by 0 */
4099         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4100         if (!diffms)
4101                 return;
4102
4103         count = I915_READ(GFXEC);
4104
4105         if (count < dev_priv->ips.last_count2) {
4106                 diff = ~0UL - dev_priv->ips.last_count2;
4107                 diff += count;
4108         } else {
4109                 diff = count - dev_priv->ips.last_count2;
4110         }
4111
4112         dev_priv->ips.last_count2 = count;
4113         dev_priv->ips.last_time2 = now;
4114
4115         /* More magic constants... */
4116         diff = diff * 1181;
4117         diff = div_u64(diff, diffms * 10);
4118         dev_priv->ips.gfx_power = diff;
4119 }
4120
4121 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4122 {
4123         struct drm_device *dev = dev_priv->dev;
4124
4125         if (INTEL_INFO(dev)->gen != 5)
4126                 return;
4127
4128         spin_lock_irq(&mchdev_lock);
4129
4130         __i915_update_gfx_val(dev_priv);
4131
4132         spin_unlock_irq(&mchdev_lock);
4133 }
4134
4135 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4136 {
4137         unsigned long t, corr, state1, corr2, state2;
4138         u32 pxvid, ext_v;
4139
4140         assert_spin_locked(&mchdev_lock);
4141
4142         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4143         pxvid = (pxvid >> 24) & 0x7f;
4144         ext_v = pvid_to_extvid(dev_priv, pxvid);
4145
4146         state1 = ext_v;
4147
4148         t = i915_mch_val(dev_priv);
4149
4150         /* Revel in the empirically derived constants */
4151
4152         /* Correction factor in 1/100000 units */
4153         if (t > 80)
4154                 corr = ((t * 2349) + 135940);
4155         else if (t >= 50)
4156                 corr = ((t * 964) + 29317);
4157         else /* < 50 */
4158                 corr = ((t * 301) + 1004);
4159
4160         corr = corr * ((150142 * state1) / 10000 - 78642);
4161         corr /= 100000;
4162         corr2 = (corr * dev_priv->ips.corr);
4163
4164         state2 = (corr2 * state1) / 10000;
4165         state2 /= 100; /* convert to mW */
4166
4167         __i915_update_gfx_val(dev_priv);
4168
4169         return dev_priv->ips.gfx_power + state2;
4170 }
4171
4172 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4173 {
4174         struct drm_device *dev = dev_priv->dev;
4175         unsigned long val;
4176
4177         if (INTEL_INFO(dev)->gen != 5)
4178                 return 0;
4179
4180         spin_lock_irq(&mchdev_lock);
4181
4182         val = __i915_gfx_val(dev_priv);
4183
4184         spin_unlock_irq(&mchdev_lock);
4185
4186         return val;
4187 }
4188
4189 /**
4190  * i915_read_mch_val - return value for IPS use
4191  *
4192  * Calculate and return a value for the IPS driver to use when deciding whether
4193  * we have thermal and power headroom to increase CPU or GPU power budget.
4194  */
4195 unsigned long i915_read_mch_val(void)
4196 {
4197         struct drm_i915_private *dev_priv;
4198         unsigned long chipset_val, graphics_val, ret = 0;
4199
4200         spin_lock_irq(&mchdev_lock);
4201         if (!i915_mch_dev)
4202                 goto out_unlock;
4203         dev_priv = i915_mch_dev;
4204
4205         chipset_val = __i915_chipset_val(dev_priv);
4206         graphics_val = __i915_gfx_val(dev_priv);
4207
4208         ret = chipset_val + graphics_val;
4209
4210 out_unlock:
4211         spin_unlock_irq(&mchdev_lock);
4212
4213         return ret;
4214 }
4215 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4216
4217 /**
4218  * i915_gpu_raise - raise GPU frequency limit
4219  *
4220  * Raise the limit; IPS indicates we have thermal headroom.
4221  */
4222 bool i915_gpu_raise(void)
4223 {
4224         struct drm_i915_private *dev_priv;
4225         bool ret = true;
4226
4227         spin_lock_irq(&mchdev_lock);
4228         if (!i915_mch_dev) {
4229                 ret = false;
4230                 goto out_unlock;
4231         }
4232         dev_priv = i915_mch_dev;
4233
4234         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4235                 dev_priv->ips.max_delay--;
4236
4237 out_unlock:
4238         spin_unlock_irq(&mchdev_lock);
4239
4240         return ret;
4241 }
4242 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4243
4244 /**
4245  * i915_gpu_lower - lower GPU frequency limit
4246  *
4247  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4248  * frequency maximum.
4249  */
4250 bool i915_gpu_lower(void)
4251 {
4252         struct drm_i915_private *dev_priv;
4253         bool ret = true;
4254
4255         spin_lock_irq(&mchdev_lock);
4256         if (!i915_mch_dev) {
4257                 ret = false;
4258                 goto out_unlock;
4259         }
4260         dev_priv = i915_mch_dev;
4261
4262         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4263                 dev_priv->ips.max_delay++;
4264
4265 out_unlock:
4266         spin_unlock_irq(&mchdev_lock);
4267
4268         return ret;
4269 }
4270 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4271
4272 /**
4273  * i915_gpu_busy - indicate GPU business to IPS
4274  *
4275  * Tell the IPS driver whether or not the GPU is busy.
4276  */
4277 bool i915_gpu_busy(void)
4278 {
4279         struct drm_i915_private *dev_priv;
4280         struct intel_ring_buffer *ring;
4281         bool ret = false;
4282         int i;
4283
4284         spin_lock_irq(&mchdev_lock);
4285         if (!i915_mch_dev)
4286                 goto out_unlock;
4287         dev_priv = i915_mch_dev;
4288
4289         for_each_ring(ring, dev_priv, i)
4290                 ret |= !list_empty(&ring->request_list);
4291
4292 out_unlock:
4293         spin_unlock_irq(&mchdev_lock);
4294
4295         return ret;
4296 }
4297 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4298
4299 /**
4300  * i915_gpu_turbo_disable - disable graphics turbo
4301  *
4302  * Disable graphics turbo by resetting the max frequency and setting the
4303  * current frequency to the default.
4304  */
4305 bool i915_gpu_turbo_disable(void)
4306 {
4307         struct drm_i915_private *dev_priv;
4308         bool ret = true;
4309
4310         spin_lock_irq(&mchdev_lock);
4311         if (!i915_mch_dev) {
4312                 ret = false;
4313                 goto out_unlock;
4314         }
4315         dev_priv = i915_mch_dev;
4316
4317         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4318
4319         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4320                 ret = false;
4321
4322 out_unlock:
4323         spin_unlock_irq(&mchdev_lock);
4324
4325         return ret;
4326 }
4327 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4328
4329 /**
4330  * Tells the intel_ips driver that the i915 driver is now loaded, if
4331  * IPS got loaded first.
4332  *
4333  * This awkward dance is so that neither module has to depend on the
4334  * other in order for IPS to do the appropriate communication of
4335  * GPU turbo limits to i915.
4336  */
4337 static void
4338 ips_ping_for_i915_load(void)
4339 {
4340         void (*link)(void);
4341
4342         link = symbol_get(ips_link_to_i915_driver);
4343         if (link) {
4344                 link();
4345                 symbol_put(ips_link_to_i915_driver);
4346         }
4347 }
4348
4349 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4350 {
4351         /* We only register the i915 ips part with intel-ips once everything is
4352          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4353         spin_lock_irq(&mchdev_lock);
4354         i915_mch_dev = dev_priv;
4355         spin_unlock_irq(&mchdev_lock);
4356
4357         ips_ping_for_i915_load();
4358 }
4359
4360 void intel_gpu_ips_teardown(void)
4361 {
4362         spin_lock_irq(&mchdev_lock);
4363         i915_mch_dev = NULL;
4364         spin_unlock_irq(&mchdev_lock);
4365 }
4366
4367 static void intel_init_emon(struct drm_device *dev)
4368 {
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         u32 lcfuse;
4371         u8 pxw[16];
4372         int i;
4373
4374         /* Disable to program */
4375         I915_WRITE(ECR, 0);
4376         POSTING_READ(ECR);
4377
4378         /* Program energy weights for various events */
4379         I915_WRITE(SDEW, 0x15040d00);
4380         I915_WRITE(CSIEW0, 0x007f0000);
4381         I915_WRITE(CSIEW1, 0x1e220004);
4382         I915_WRITE(CSIEW2, 0x04000004);
4383
4384         for (i = 0; i < 5; i++)
4385                 I915_WRITE(PEW + (i * 4), 0);
4386         for (i = 0; i < 3; i++)
4387                 I915_WRITE(DEW + (i * 4), 0);
4388
4389         /* Program P-state weights to account for frequency power adjustment */
4390         for (i = 0; i < 16; i++) {
4391                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4392                 unsigned long freq = intel_pxfreq(pxvidfreq);
4393                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4394                         PXVFREQ_PX_SHIFT;
4395                 unsigned long val;
4396
4397                 val = vid * vid;
4398                 val *= (freq / 1000);
4399                 val *= 255;
4400                 val /= (127*127*900);
4401                 if (val > 0xff)
4402                         DRM_ERROR("bad pxval: %ld\n", val);
4403                 pxw[i] = val;
4404         }
4405         /* Render standby states get 0 weight */
4406         pxw[14] = 0;
4407         pxw[15] = 0;
4408
4409         for (i = 0; i < 4; i++) {
4410                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4411                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4412                 I915_WRITE(PXW + (i * 4), val);
4413         }
4414
4415         /* Adjust magic regs to magic values (more experimental results) */
4416         I915_WRITE(OGW0, 0);
4417         I915_WRITE(OGW1, 0);
4418         I915_WRITE(EG0, 0x00007f00);
4419         I915_WRITE(EG1, 0x0000000e);
4420         I915_WRITE(EG2, 0x000e0000);
4421         I915_WRITE(EG3, 0x68000300);
4422         I915_WRITE(EG4, 0x42000000);
4423         I915_WRITE(EG5, 0x00140031);
4424         I915_WRITE(EG6, 0);
4425         I915_WRITE(EG7, 0);
4426
4427         for (i = 0; i < 8; i++)
4428                 I915_WRITE(PXWL + (i * 4), 0);
4429
4430         /* Enable PMON + select events */
4431         I915_WRITE(ECR, 0x80000019);
4432
4433         lcfuse = I915_READ(LCFUSE02);
4434
4435         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4436 }
4437
4438 void intel_init_gt_powersave(struct drm_device *dev)
4439 {
4440         if (IS_VALLEYVIEW(dev))
4441                 valleyview_setup_pctx(dev);
4442 }
4443
4444 void intel_cleanup_gt_powersave(struct drm_device *dev)
4445 {
4446         if (IS_VALLEYVIEW(dev))
4447                 valleyview_cleanup_pctx(dev);
4448 }
4449
4450 void intel_disable_gt_powersave(struct drm_device *dev)
4451 {
4452         struct drm_i915_private *dev_priv = dev->dev_private;
4453
4454         /* Interrupts should be disabled already to avoid re-arming. */
4455         WARN_ON(dev->irq_enabled);
4456
4457         if (IS_IRONLAKE_M(dev)) {
4458                 ironlake_disable_drps(dev);
4459                 ironlake_disable_rc6(dev);
4460         } else if (INTEL_INFO(dev)->gen >= 6) {
4461                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4462                 cancel_work_sync(&dev_priv->rps.work);
4463                 mutex_lock(&dev_priv->rps.hw_lock);
4464                 if (IS_VALLEYVIEW(dev))
4465                         valleyview_disable_rps(dev);
4466                 else
4467                         gen6_disable_rps(dev);
4468                 dev_priv->rps.enabled = false;
4469                 mutex_unlock(&dev_priv->rps.hw_lock);
4470         }
4471 }
4472
4473 static void intel_gen6_powersave_work(struct work_struct *work)
4474 {
4475         struct drm_i915_private *dev_priv =
4476                 container_of(work, struct drm_i915_private,
4477                              rps.delayed_resume_work.work);
4478         struct drm_device *dev = dev_priv->dev;
4479
4480         mutex_lock(&dev_priv->rps.hw_lock);
4481
4482         if (IS_VALLEYVIEW(dev)) {
4483                 valleyview_enable_rps(dev);
4484         } else if (IS_BROADWELL(dev)) {
4485                 gen8_enable_rps(dev);
4486                 gen6_update_ring_freq(dev);
4487         } else {
4488                 gen6_enable_rps(dev);
4489                 gen6_update_ring_freq(dev);
4490         }
4491         dev_priv->rps.enabled = true;
4492         mutex_unlock(&dev_priv->rps.hw_lock);
4493 }
4494
4495 void intel_enable_gt_powersave(struct drm_device *dev)
4496 {
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498
4499         if (IS_IRONLAKE_M(dev)) {
4500                 ironlake_enable_drps(dev);
4501                 ironlake_enable_rc6(dev);
4502                 intel_init_emon(dev);
4503         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4504                 /*
4505                  * PCU communication is slow and this doesn't need to be
4506                  * done at any specific time, so do this out of our fast path
4507                  * to make resume and init faster.
4508                  */
4509                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4510                                       round_jiffies_up_relative(HZ));
4511         }
4512 }
4513
4514 static void ibx_init_clock_gating(struct drm_device *dev)
4515 {
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517
4518         /*
4519          * On Ibex Peak and Cougar Point, we need to disable clock
4520          * gating for the panel power sequencer or it will fail to
4521          * start up when no ports are active.
4522          */
4523         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4524 }
4525
4526 static void g4x_disable_trickle_feed(struct drm_device *dev)
4527 {
4528         struct drm_i915_private *dev_priv = dev->dev_private;
4529         int pipe;
4530
4531         for_each_pipe(pipe) {
4532                 I915_WRITE(DSPCNTR(pipe),
4533                            I915_READ(DSPCNTR(pipe)) |
4534                            DISPPLANE_TRICKLE_FEED_DISABLE);
4535                 intel_flush_primary_plane(dev_priv, pipe);
4536         }
4537 }
4538
4539 static void ilk_init_lp_watermarks(struct drm_device *dev)
4540 {
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542
4543         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4544         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4545         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4546
4547         /*
4548          * Don't touch WM1S_LP_EN here.
4549          * Doing so could cause underruns.
4550          */
4551 }
4552
4553 static void ironlake_init_clock_gating(struct drm_device *dev)
4554 {
4555         struct drm_i915_private *dev_priv = dev->dev_private;
4556         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4557
4558         /*
4559          * Required for FBC
4560          * WaFbcDisableDpfcClockGating:ilk
4561          */
4562         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4563                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4564                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4565
4566         I915_WRITE(PCH_3DCGDIS0,
4567                    MARIUNIT_CLOCK_GATE_DISABLE |
4568                    SVSMUNIT_CLOCK_GATE_DISABLE);
4569         I915_WRITE(PCH_3DCGDIS1,
4570                    VFMUNIT_CLOCK_GATE_DISABLE);
4571
4572         /*
4573          * According to the spec the following bits should be set in
4574          * order to enable memory self-refresh
4575          * The bit 22/21 of 0x42004
4576          * The bit 5 of 0x42020
4577          * The bit 15 of 0x45000
4578          */
4579         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4580                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4581                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4582         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4583         I915_WRITE(DISP_ARB_CTL,
4584                    (I915_READ(DISP_ARB_CTL) |
4585                     DISP_FBC_WM_DIS));
4586
4587         ilk_init_lp_watermarks(dev);
4588
4589         /*
4590          * Based on the document from hardware guys the following bits
4591          * should be set unconditionally in order to enable FBC.
4592          * The bit 22 of 0x42000
4593          * The bit 22 of 0x42004
4594          * The bit 7,8,9 of 0x42020.
4595          */
4596         if (IS_IRONLAKE_M(dev)) {
4597                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4598                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4599                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4600                            ILK_FBCQ_DIS);
4601                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4602                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4603                            ILK_DPARB_GATE);
4604         }
4605
4606         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4607
4608         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4609                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4610                    ILK_ELPIN_409_SELECT);
4611         I915_WRITE(_3D_CHICKEN2,
4612                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4613                    _3D_CHICKEN2_WM_READ_PIPELINED);
4614
4615         /* WaDisableRenderCachePipelinedFlush:ilk */
4616         I915_WRITE(CACHE_MODE_0,
4617                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4618
4619         g4x_disable_trickle_feed(dev);
4620
4621         ibx_init_clock_gating(dev);
4622 }
4623
4624 static void cpt_init_clock_gating(struct drm_device *dev)
4625 {
4626         struct drm_i915_private *dev_priv = dev->dev_private;
4627         int pipe;
4628         uint32_t val;
4629
4630         /*
4631          * On Ibex Peak and Cougar Point, we need to disable clock
4632          * gating for the panel power sequencer or it will fail to
4633          * start up when no ports are active.
4634          */
4635         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4636                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4637                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4638         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4639                    DPLS_EDP_PPS_FIX_DIS);
4640         /* The below fixes the weird display corruption, a few pixels shifted
4641          * downward, on (only) LVDS of some HP laptops with IVY.
4642          */
4643         for_each_pipe(pipe) {
4644                 val = I915_READ(TRANS_CHICKEN2(pipe));
4645                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4646                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4647                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4648                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4649                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4650                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4651                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4652                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4653         }
4654         /* WADP0ClockGatingDisable */
4655         for_each_pipe(pipe) {
4656                 I915_WRITE(TRANS_CHICKEN1(pipe),
4657                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4658         }
4659 }
4660
4661 static void gen6_check_mch_setup(struct drm_device *dev)
4662 {
4663         struct drm_i915_private *dev_priv = dev->dev_private;
4664         uint32_t tmp;
4665
4666         tmp = I915_READ(MCH_SSKPD);
4667         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4668                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4669                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4670                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4671         }
4672 }
4673
4674 static void gen6_init_clock_gating(struct drm_device *dev)
4675 {
4676         struct drm_i915_private *dev_priv = dev->dev_private;
4677         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4678
4679         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4680
4681         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4682                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4683                    ILK_ELPIN_409_SELECT);
4684
4685         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4686         I915_WRITE(_3D_CHICKEN,
4687                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4688
4689         /* WaSetupGtModeTdRowDispatch:snb */
4690         if (IS_SNB_GT1(dev))
4691                 I915_WRITE(GEN6_GT_MODE,
4692                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4693
4694         /*
4695          * BSpec recoomends 8x4 when MSAA is used,
4696          * however in practice 16x4 seems fastest.
4697          *
4698          * Note that PS/WM thread counts depend on the WIZ hashing
4699          * disable bit, which we don't touch here, but it's good
4700          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4701          */
4702         I915_WRITE(GEN6_GT_MODE,
4703                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4704
4705         ilk_init_lp_watermarks(dev);
4706
4707         I915_WRITE(CACHE_MODE_0,
4708                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4709
4710         I915_WRITE(GEN6_UCGCTL1,
4711                    I915_READ(GEN6_UCGCTL1) |
4712                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4713                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4714
4715         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4716          * gating disable must be set.  Failure to set it results in
4717          * flickering pixels due to Z write ordering failures after
4718          * some amount of runtime in the Mesa "fire" demo, and Unigine
4719          * Sanctuary and Tropics, and apparently anything else with
4720          * alpha test or pixel discard.
4721          *
4722          * According to the spec, bit 11 (RCCUNIT) must also be set,
4723          * but we didn't debug actual testcases to find it out.
4724          *
4725          * WaDisableRCCUnitClockGating:snb
4726          * WaDisableRCPBUnitClockGating:snb
4727          */
4728         I915_WRITE(GEN6_UCGCTL2,
4729                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4730                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4731
4732         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4733         I915_WRITE(_3D_CHICKEN3,
4734                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4735
4736         /*
4737          * Bspec says:
4738          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4739          * 3DSTATE_SF number of SF output attributes is more than 16."
4740          */
4741         I915_WRITE(_3D_CHICKEN3,
4742                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4743
4744         /*
4745          * According to the spec the following bits should be
4746          * set in order to enable memory self-refresh and fbc:
4747          * The bit21 and bit22 of 0x42000
4748          * The bit21 and bit22 of 0x42004
4749          * The bit5 and bit7 of 0x42020
4750          * The bit14 of 0x70180
4751          * The bit14 of 0x71180
4752          *
4753          * WaFbcAsynchFlipDisableFbcQueue:snb
4754          */
4755         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4756                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4757                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4758         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4759                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4760                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4761         I915_WRITE(ILK_DSPCLK_GATE_D,
4762                    I915_READ(ILK_DSPCLK_GATE_D) |
4763                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4764                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4765
4766         g4x_disable_trickle_feed(dev);
4767
4768         cpt_init_clock_gating(dev);
4769
4770         gen6_check_mch_setup(dev);
4771 }
4772
4773 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4774 {
4775         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4776
4777         /*
4778          * WaVSThreadDispatchOverride:ivb,vlv
4779          *
4780          * This actually overrides the dispatch
4781          * mode for all thread types.
4782          */
4783         reg &= ~GEN7_FF_SCHED_MASK;
4784         reg |= GEN7_FF_TS_SCHED_HW;
4785         reg |= GEN7_FF_VS_SCHED_HW;
4786         reg |= GEN7_FF_DS_SCHED_HW;
4787
4788         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4789 }
4790
4791 static void lpt_init_clock_gating(struct drm_device *dev)
4792 {
4793         struct drm_i915_private *dev_priv = dev->dev_private;
4794
4795         /*
4796          * TODO: this bit should only be enabled when really needed, then
4797          * disabled when not needed anymore in order to save power.
4798          */
4799         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4800                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4801                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4802                            PCH_LP_PARTITION_LEVEL_DISABLE);
4803
4804         /* WADPOClockGatingDisable:hsw */
4805         I915_WRITE(_TRANSA_CHICKEN1,
4806                    I915_READ(_TRANSA_CHICKEN1) |
4807                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4808 }
4809
4810 static void lpt_suspend_hw(struct drm_device *dev)
4811 {
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813
4814         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4815                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4816
4817                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4818                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4819         }
4820 }
4821
4822 static void gen8_init_clock_gating(struct drm_device *dev)
4823 {
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         enum pipe pipe;
4826
4827         I915_WRITE(WM3_LP_ILK, 0);
4828         I915_WRITE(WM2_LP_ILK, 0);
4829         I915_WRITE(WM1_LP_ILK, 0);
4830
4831         /* FIXME(BDW): Check all the w/a, some might only apply to
4832          * pre-production hw. */
4833
4834         /* WaDisablePartialInstShootdown:bdw */
4835         I915_WRITE(GEN8_ROW_CHICKEN,
4836                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4837
4838         /* WaDisableThreadStallDopClockGating:bdw */
4839         /* FIXME: Unclear whether we really need this on production bdw. */
4840         I915_WRITE(GEN8_ROW_CHICKEN,
4841                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4842
4843         /*
4844          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4845          * pre-production hardware
4846          */
4847         I915_WRITE(HALF_SLICE_CHICKEN3,
4848                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4849         I915_WRITE(HALF_SLICE_CHICKEN3,
4850                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4851         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4852
4853         I915_WRITE(_3D_CHICKEN3,
4854                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4855
4856         I915_WRITE(COMMON_SLICE_CHICKEN2,
4857                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4858
4859         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4860                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4861
4862         /* WaSwitchSolVfFArbitrationPriority:bdw */
4863         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4864
4865         /* WaPsrDPAMaskVBlankInSRD:bdw */
4866         I915_WRITE(CHICKEN_PAR1_1,
4867                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4868
4869         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4870         for_each_pipe(pipe) {
4871                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
4872                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
4873                            BDW_DPRS_MASK_VBLANK_SRD);
4874         }
4875
4876         /* Use Force Non-Coherent whenever executing a 3D context. This is a
4877          * workaround for for a possible hang in the unlikely event a TLB
4878          * invalidation occurs during a PSD flush.
4879          */
4880         I915_WRITE(HDC_CHICKEN0,
4881                    I915_READ(HDC_CHICKEN0) |
4882                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
4883
4884         /* WaVSRefCountFullforceMissDisable:bdw */
4885         /* WaDSRefCountFullforceMissDisable:bdw */
4886         I915_WRITE(GEN7_FF_THREAD_MODE,
4887                    I915_READ(GEN7_FF_THREAD_MODE) &
4888                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4889
4890         /*
4891          * BSpec recommends 8x4 when MSAA is used,
4892          * however in practice 16x4 seems fastest.
4893          *
4894          * Note that PS/WM thread counts depend on the WIZ hashing
4895          * disable bit, which we don't touch here, but it's good
4896          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4897          */
4898         I915_WRITE(GEN7_GT_MODE,
4899                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4900
4901         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
4902                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4903
4904         /* WaDisableSDEUnitClockGating:bdw */
4905         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
4906                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
4907
4908         /* Wa4x4STCOptimizationDisable:bdw */
4909         I915_WRITE(CACHE_MODE_1,
4910                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
4911 }
4912
4913 static void haswell_init_clock_gating(struct drm_device *dev)
4914 {
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916
4917         ilk_init_lp_watermarks(dev);
4918
4919         /* L3 caching of data atomics doesn't work -- disable it. */
4920         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4921         I915_WRITE(HSW_ROW_CHICKEN3,
4922                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4923
4924         /* This is required by WaCatErrorRejectionIssue:hsw */
4925         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4926                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4927                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4928
4929         /* WaVSRefCountFullforceMissDisable:hsw */
4930         I915_WRITE(GEN7_FF_THREAD_MODE,
4931                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
4932
4933         /* enable HiZ Raw Stall Optimization */
4934         I915_WRITE(CACHE_MODE_0_GEN7,
4935                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4936
4937         /* WaDisable4x2SubspanOptimization:hsw */
4938         I915_WRITE(CACHE_MODE_1,
4939                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4940
4941         /*
4942          * BSpec recommends 8x4 when MSAA is used,
4943          * however in practice 16x4 seems fastest.
4944          *
4945          * Note that PS/WM thread counts depend on the WIZ hashing
4946          * disable bit, which we don't touch here, but it's good
4947          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4948          */
4949         I915_WRITE(GEN7_GT_MODE,
4950                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4951
4952         /* WaSwitchSolVfFArbitrationPriority:hsw */
4953         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4954
4955         /* WaRsPkgCStateDisplayPMReq:hsw */
4956         I915_WRITE(CHICKEN_PAR1_1,
4957                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4958
4959         lpt_init_clock_gating(dev);
4960 }
4961
4962 static void ivybridge_init_clock_gating(struct drm_device *dev)
4963 {
4964         struct drm_i915_private *dev_priv = dev->dev_private;
4965         uint32_t snpcr;
4966
4967         ilk_init_lp_watermarks(dev);
4968
4969         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4970
4971         /* WaDisableEarlyCull:ivb */
4972         I915_WRITE(_3D_CHICKEN3,
4973                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4974
4975         /* WaDisableBackToBackFlipFix:ivb */
4976         I915_WRITE(IVB_CHICKEN3,
4977                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4978                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4979
4980         /* WaDisablePSDDualDispatchEnable:ivb */
4981         if (IS_IVB_GT1(dev))
4982                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4983                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4984
4985         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4986         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4987                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4988
4989         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4990         I915_WRITE(GEN7_L3CNTLREG1,
4991                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4992         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4993                    GEN7_WA_L3_CHICKEN_MODE);
4994         if (IS_IVB_GT1(dev))
4995                 I915_WRITE(GEN7_ROW_CHICKEN2,
4996                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4997         else {
4998                 /* must write both registers */
4999                 I915_WRITE(GEN7_ROW_CHICKEN2,
5000                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5001                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5002                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5003         }
5004
5005         /* WaForceL3Serialization:ivb */
5006         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5007                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5008
5009         /*
5010          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5011          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5012          */
5013         I915_WRITE(GEN6_UCGCTL2,
5014                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5015
5016         /* This is required by WaCatErrorRejectionIssue:ivb */
5017         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5018                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5019                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5020
5021         g4x_disable_trickle_feed(dev);
5022
5023         gen7_setup_fixed_func_scheduler(dev_priv);
5024
5025         if (0) { /* causes HiZ corruption on ivb:gt1 */
5026                 /* enable HiZ Raw Stall Optimization */
5027                 I915_WRITE(CACHE_MODE_0_GEN7,
5028                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5029         }
5030
5031         /* WaDisable4x2SubspanOptimization:ivb */
5032         I915_WRITE(CACHE_MODE_1,
5033                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5034
5035         /*
5036          * BSpec recommends 8x4 when MSAA is used,
5037          * however in practice 16x4 seems fastest.
5038          *
5039          * Note that PS/WM thread counts depend on the WIZ hashing
5040          * disable bit, which we don't touch here, but it's good
5041          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5042          */
5043         I915_WRITE(GEN7_GT_MODE,
5044                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5045
5046         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5047         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5048         snpcr |= GEN6_MBC_SNPCR_MED;
5049         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5050
5051         if (!HAS_PCH_NOP(dev))
5052                 cpt_init_clock_gating(dev);
5053
5054         gen6_check_mch_setup(dev);
5055 }
5056
5057 static void valleyview_init_clock_gating(struct drm_device *dev)
5058 {
5059         struct drm_i915_private *dev_priv = dev->dev_private;
5060         u32 val;
5061
5062         mutex_lock(&dev_priv->rps.hw_lock);
5063         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5064         mutex_unlock(&dev_priv->rps.hw_lock);
5065         switch ((val >> 6) & 3) {
5066         case 0:
5067         case 1:
5068                 dev_priv->mem_freq = 800;
5069                 break;
5070         case 2:
5071                 dev_priv->mem_freq = 1066;
5072                 break;
5073         case 3:
5074                 dev_priv->mem_freq = 1333;
5075                 break;
5076         }
5077         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5078
5079         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5080
5081         /* WaDisableEarlyCull:vlv */
5082         I915_WRITE(_3D_CHICKEN3,
5083                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5084
5085         /* WaDisableBackToBackFlipFix:vlv */
5086         I915_WRITE(IVB_CHICKEN3,
5087                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5088                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5089
5090         /* WaPsdDispatchEnable:vlv */
5091         /* WaDisablePSDDualDispatchEnable:vlv */
5092         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5093                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5094                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5095
5096         /* WaForceL3Serialization:vlv */
5097         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5098                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5099
5100         /* WaDisableDopClockGating:vlv */
5101         I915_WRITE(GEN7_ROW_CHICKEN2,
5102                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5103
5104         /* This is required by WaCatErrorRejectionIssue:vlv */
5105         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5106                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5107                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5108
5109         gen7_setup_fixed_func_scheduler(dev_priv);
5110
5111         /*
5112          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5113          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5114          */
5115         I915_WRITE(GEN6_UCGCTL2,
5116                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5117
5118         /* WaDisableL3Bank2xClockGate:vlv */
5119         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5120
5121         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5122
5123         /*
5124          * BSpec says this must be set, even though
5125          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5126          */
5127         I915_WRITE(CACHE_MODE_1,
5128                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5129
5130         /*
5131          * WaIncreaseL3CreditsForVLVB0:vlv
5132          * This is the hardware default actually.
5133          */
5134         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5135
5136         /*
5137          * WaDisableVLVClockGating_VBIIssue:vlv
5138          * Disable clock gating on th GCFG unit to prevent a delay
5139          * in the reporting of vblank events.
5140          */
5141         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5142 }
5143
5144 static void g4x_init_clock_gating(struct drm_device *dev)
5145 {
5146         struct drm_i915_private *dev_priv = dev->dev_private;
5147         uint32_t dspclk_gate;
5148
5149         I915_WRITE(RENCLK_GATE_D1, 0);
5150         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5151                    GS_UNIT_CLOCK_GATE_DISABLE |
5152                    CL_UNIT_CLOCK_GATE_DISABLE);
5153         I915_WRITE(RAMCLK_GATE_D, 0);
5154         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5155                 OVRUNIT_CLOCK_GATE_DISABLE |
5156                 OVCUNIT_CLOCK_GATE_DISABLE;
5157         if (IS_GM45(dev))
5158                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5159         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5160
5161         /* WaDisableRenderCachePipelinedFlush */
5162         I915_WRITE(CACHE_MODE_0,
5163                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5164
5165         g4x_disable_trickle_feed(dev);
5166 }
5167
5168 static void crestline_init_clock_gating(struct drm_device *dev)
5169 {
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171
5172         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5173         I915_WRITE(RENCLK_GATE_D2, 0);
5174         I915_WRITE(DSPCLK_GATE_D, 0);
5175         I915_WRITE(RAMCLK_GATE_D, 0);
5176         I915_WRITE16(DEUC, 0);
5177         I915_WRITE(MI_ARB_STATE,
5178                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5179 }
5180
5181 static void broadwater_init_clock_gating(struct drm_device *dev)
5182 {
5183         struct drm_i915_private *dev_priv = dev->dev_private;
5184
5185         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5186                    I965_RCC_CLOCK_GATE_DISABLE |
5187                    I965_RCPB_CLOCK_GATE_DISABLE |
5188                    I965_ISC_CLOCK_GATE_DISABLE |
5189                    I965_FBC_CLOCK_GATE_DISABLE);
5190         I915_WRITE(RENCLK_GATE_D2, 0);
5191         I915_WRITE(MI_ARB_STATE,
5192                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5193 }
5194
5195 static void gen3_init_clock_gating(struct drm_device *dev)
5196 {
5197         struct drm_i915_private *dev_priv = dev->dev_private;
5198         u32 dstate = I915_READ(D_STATE);
5199
5200         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5201                 DSTATE_DOT_CLOCK_GATING;
5202         I915_WRITE(D_STATE, dstate);
5203
5204         if (IS_PINEVIEW(dev))
5205                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5206
5207         /* IIR "flip pending" means done if this bit is set */
5208         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5209 }
5210
5211 static void i85x_init_clock_gating(struct drm_device *dev)
5212 {
5213         struct drm_i915_private *dev_priv = dev->dev_private;
5214
5215         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5216 }
5217
5218 static void i830_init_clock_gating(struct drm_device *dev)
5219 {
5220         struct drm_i915_private *dev_priv = dev->dev_private;
5221
5222         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5223 }
5224
5225 void intel_init_clock_gating(struct drm_device *dev)
5226 {
5227         struct drm_i915_private *dev_priv = dev->dev_private;
5228
5229         dev_priv->display.init_clock_gating(dev);
5230 }
5231
5232 void intel_suspend_hw(struct drm_device *dev)
5233 {
5234         if (HAS_PCH_LPT(dev))
5235                 lpt_suspend_hw(dev);
5236 }
5237
5238 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5239         for (i = 0;                                                     \
5240              i < (power_domains)->power_well_count &&                   \
5241                  ((power_well) = &(power_domains)->power_wells[i]);     \
5242              i++)                                                       \
5243                 if ((power_well)->domains & (domain_mask))
5244
5245 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5246         for (i = (power_domains)->power_well_count - 1;                  \
5247              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5248              i--)                                                        \
5249                 if ((power_well)->domains & (domain_mask))
5250
5251 /**
5252  * We should only use the power well if we explicitly asked the hardware to
5253  * enable it, so check if it's enabled and also check if we've requested it to
5254  * be enabled.
5255  */
5256 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5257                                    struct i915_power_well *power_well)
5258 {
5259         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5260                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5261 }
5262
5263 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5264                                     enum intel_display_power_domain domain)
5265 {
5266         struct i915_power_domains *power_domains;
5267
5268         power_domains = &dev_priv->power_domains;
5269
5270         return power_domains->domain_use_count[domain];
5271 }
5272
5273 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5274                                  enum intel_display_power_domain domain)
5275 {
5276         struct i915_power_domains *power_domains;
5277         struct i915_power_well *power_well;
5278         bool is_enabled;
5279         int i;
5280
5281         if (dev_priv->pm.suspended)
5282                 return false;
5283
5284         power_domains = &dev_priv->power_domains;
5285
5286         is_enabled = true;
5287
5288         mutex_lock(&power_domains->lock);
5289         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5290                 if (power_well->always_on)
5291                         continue;
5292
5293                 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5294                         is_enabled = false;
5295                         break;
5296                 }
5297         }
5298         mutex_unlock(&power_domains->lock);
5299
5300         return is_enabled;
5301 }
5302
5303 /*
5304  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5305  * when not needed anymore. We have 4 registers that can request the power well
5306  * to be enabled, and it will only be disabled if none of the registers is
5307  * requesting it to be enabled.
5308  */
5309 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5310 {
5311         struct drm_device *dev = dev_priv->dev;
5312         unsigned long irqflags;
5313
5314         /*
5315          * After we re-enable the power well, if we touch VGA register 0x3d5
5316          * we'll get unclaimed register interrupts. This stops after we write
5317          * anything to the VGA MSR register. The vgacon module uses this
5318          * register all the time, so if we unbind our driver and, as a
5319          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5320          * console_unlock(). So make here we touch the VGA MSR register, making
5321          * sure vgacon can keep working normally without triggering interrupts
5322          * and error messages.
5323          */
5324         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5325         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5326         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5327
5328         if (IS_BROADWELL(dev)) {
5329                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5330                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5331                            dev_priv->de_irq_mask[PIPE_B]);
5332                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5333                            ~dev_priv->de_irq_mask[PIPE_B] |
5334                            GEN8_PIPE_VBLANK);
5335                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5336                            dev_priv->de_irq_mask[PIPE_C]);
5337                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5338                            ~dev_priv->de_irq_mask[PIPE_C] |
5339                            GEN8_PIPE_VBLANK);
5340                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5341                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5342         }
5343 }
5344
5345 static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5346 {
5347         assert_spin_locked(&dev->vbl_lock);
5348
5349         dev->vblank[pipe].last = 0;
5350 }
5351
5352 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5353 {
5354         struct drm_device *dev = dev_priv->dev;
5355         enum pipe pipe;
5356         unsigned long irqflags;
5357
5358         /*
5359          * After this, the registers on the pipes that are part of the power
5360          * well will become zero, so we have to adjust our counters according to
5361          * that.
5362          *
5363          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5364          */
5365         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5366         for_each_pipe(pipe)
5367                 if (pipe != PIPE_A)
5368                         reset_vblank_counter(dev, pipe);
5369         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5370 }
5371
5372 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5373                                struct i915_power_well *power_well, bool enable)
5374 {
5375         bool is_enabled, enable_requested;
5376         uint32_t tmp;
5377
5378         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5379         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5380         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5381
5382         if (enable) {
5383                 if (!enable_requested)
5384                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5385                                    HSW_PWR_WELL_ENABLE_REQUEST);
5386
5387                 if (!is_enabled) {
5388                         DRM_DEBUG_KMS("Enabling power well\n");
5389                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5390                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5391                                 DRM_ERROR("Timeout enabling power well\n");
5392                 }
5393
5394                 hsw_power_well_post_enable(dev_priv);
5395         } else {
5396                 if (enable_requested) {
5397                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5398                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5399                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5400
5401                         hsw_power_well_post_disable(dev_priv);
5402                 }
5403         }
5404 }
5405
5406 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5407                                    struct i915_power_well *power_well)
5408 {
5409         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5410
5411         /*
5412          * We're taking over the BIOS, so clear any requests made by it since
5413          * the driver is in charge now.
5414          */
5415         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5416                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5417 }
5418
5419 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5420                                   struct i915_power_well *power_well)
5421 {
5422         hsw_set_power_well(dev_priv, power_well, true);
5423 }
5424
5425 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5426                                    struct i915_power_well *power_well)
5427 {
5428         hsw_set_power_well(dev_priv, power_well, false);
5429 }
5430
5431 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5432                                            struct i915_power_well *power_well)
5433 {
5434 }
5435
5436 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5437                                              struct i915_power_well *power_well)
5438 {
5439         return true;
5440 }
5441
5442 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5443                                struct i915_power_well *power_well, bool enable)
5444 {
5445         enum punit_power_well power_well_id = power_well->data;
5446         u32 mask;
5447         u32 state;
5448         u32 ctrl;
5449
5450         mask = PUNIT_PWRGT_MASK(power_well_id);
5451         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5452                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5453
5454         mutex_lock(&dev_priv->rps.hw_lock);
5455
5456 #define COND \
5457         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5458
5459         if (COND)
5460                 goto out;
5461
5462         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5463         ctrl &= ~mask;
5464         ctrl |= state;
5465         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5466
5467         if (wait_for(COND, 100))
5468                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5469                           state,
5470                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5471
5472 #undef COND
5473
5474 out:
5475         mutex_unlock(&dev_priv->rps.hw_lock);
5476 }
5477
5478 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5479                                    struct i915_power_well *power_well)
5480 {
5481         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5482 }
5483
5484 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5485                                   struct i915_power_well *power_well)
5486 {
5487         vlv_set_power_well(dev_priv, power_well, true);
5488 }
5489
5490 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5491                                    struct i915_power_well *power_well)
5492 {
5493         vlv_set_power_well(dev_priv, power_well, false);
5494 }
5495
5496 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5497                                    struct i915_power_well *power_well)
5498 {
5499         int power_well_id = power_well->data;
5500         bool enabled = false;
5501         u32 mask;
5502         u32 state;
5503         u32 ctrl;
5504
5505         mask = PUNIT_PWRGT_MASK(power_well_id);
5506         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5507
5508         mutex_lock(&dev_priv->rps.hw_lock);
5509
5510         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5511         /*
5512          * We only ever set the power-on and power-gate states, anything
5513          * else is unexpected.
5514          */
5515         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5516                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5517         if (state == ctrl)
5518                 enabled = true;
5519
5520         /*
5521          * A transient state at this point would mean some unexpected party
5522          * is poking at the power controls too.
5523          */
5524         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5525         WARN_ON(ctrl != state);
5526
5527         mutex_unlock(&dev_priv->rps.hw_lock);
5528
5529         return enabled;
5530 }
5531
5532 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5533                                           struct i915_power_well *power_well)
5534 {
5535         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5536
5537         vlv_set_power_well(dev_priv, power_well, true);
5538
5539         spin_lock_irq(&dev_priv->irq_lock);
5540         valleyview_enable_display_irqs(dev_priv);
5541         spin_unlock_irq(&dev_priv->irq_lock);
5542
5543         /*
5544          * During driver initialization we need to defer enabling hotplug
5545          * processing until fbdev is set up.
5546          */
5547         if (dev_priv->enable_hotplug_processing)
5548                 intel_hpd_init(dev_priv->dev);
5549
5550         i915_redisable_vga_power_on(dev_priv->dev);
5551 }
5552
5553 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5554                                            struct i915_power_well *power_well)
5555 {
5556         struct drm_device *dev = dev_priv->dev;
5557         enum pipe pipe;
5558
5559         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5560
5561         spin_lock_irq(&dev_priv->irq_lock);
5562         for_each_pipe(pipe)
5563                 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5564
5565         valleyview_disable_display_irqs(dev_priv);
5566         spin_unlock_irq(&dev_priv->irq_lock);
5567
5568         spin_lock_irq(&dev->vbl_lock);
5569         for_each_pipe(pipe)
5570                 reset_vblank_counter(dev, pipe);
5571         spin_unlock_irq(&dev->vbl_lock);
5572
5573         vlv_set_power_well(dev_priv, power_well, false);
5574 }
5575
5576 static void check_power_well_state(struct drm_i915_private *dev_priv,
5577                                    struct i915_power_well *power_well)
5578 {
5579         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5580
5581         if (power_well->always_on || !i915.disable_power_well) {
5582                 if (!enabled)
5583                         goto mismatch;
5584
5585                 return;
5586         }
5587
5588         if (enabled != (power_well->count > 0))
5589                 goto mismatch;
5590
5591         return;
5592
5593 mismatch:
5594         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5595                   power_well->name, power_well->always_on, enabled,
5596                   power_well->count, i915.disable_power_well);
5597 }
5598
5599 void intel_display_power_get(struct drm_i915_private *dev_priv,
5600                              enum intel_display_power_domain domain)
5601 {
5602         struct i915_power_domains *power_domains;
5603         struct i915_power_well *power_well;
5604         int i;
5605
5606         intel_runtime_pm_get(dev_priv);
5607
5608         power_domains = &dev_priv->power_domains;
5609
5610         mutex_lock(&power_domains->lock);
5611
5612         for_each_power_well(i, power_well, BIT(domain), power_domains) {
5613                 if (!power_well->count++) {
5614                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5615                         power_well->ops->enable(dev_priv, power_well);
5616                 }
5617
5618                 check_power_well_state(dev_priv, power_well);
5619         }
5620
5621         power_domains->domain_use_count[domain]++;
5622
5623         mutex_unlock(&power_domains->lock);
5624 }
5625
5626 void intel_display_power_put(struct drm_i915_private *dev_priv,
5627                              enum intel_display_power_domain domain)
5628 {
5629         struct i915_power_domains *power_domains;
5630         struct i915_power_well *power_well;
5631         int i;
5632
5633         power_domains = &dev_priv->power_domains;
5634
5635         mutex_lock(&power_domains->lock);
5636
5637         WARN_ON(!power_domains->domain_use_count[domain]);
5638         power_domains->domain_use_count[domain]--;
5639
5640         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5641                 WARN_ON(!power_well->count);
5642
5643                 if (!--power_well->count && i915.disable_power_well) {
5644                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5645                         power_well->ops->disable(dev_priv, power_well);
5646                 }
5647
5648                 check_power_well_state(dev_priv, power_well);
5649         }
5650
5651         mutex_unlock(&power_domains->lock);
5652
5653         intel_runtime_pm_put(dev_priv);
5654 }
5655
5656 static struct i915_power_domains *hsw_pwr;
5657
5658 /* Display audio driver power well request */
5659 void i915_request_power_well(void)
5660 {
5661         struct drm_i915_private *dev_priv;
5662
5663         if (WARN_ON(!hsw_pwr))
5664                 return;
5665
5666         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5667                                 power_domains);
5668         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5669 }
5670 EXPORT_SYMBOL_GPL(i915_request_power_well);
5671
5672 /* Display audio driver power well release */
5673 void i915_release_power_well(void)
5674 {
5675         struct drm_i915_private *dev_priv;
5676
5677         if (WARN_ON(!hsw_pwr))
5678                 return;
5679
5680         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5681                                 power_domains);
5682         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5683 }
5684 EXPORT_SYMBOL_GPL(i915_release_power_well);
5685
5686 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5687
5688 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
5689         BIT(POWER_DOMAIN_PIPE_A) |                      \
5690         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
5691         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
5692         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
5693         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
5694         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
5695         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
5696         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
5697         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
5698         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
5699         BIT(POWER_DOMAIN_PORT_CRT) |                    \
5700         BIT(POWER_DOMAIN_INIT))
5701 #define HSW_DISPLAY_POWER_DOMAINS (                             \
5702         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
5703         BIT(POWER_DOMAIN_INIT))
5704
5705 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
5706         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
5707         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5708 #define BDW_DISPLAY_POWER_DOMAINS (                             \
5709         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
5710         BIT(POWER_DOMAIN_INIT))
5711
5712 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
5713 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
5714
5715 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
5716         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5717         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5718         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5719         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5720         BIT(POWER_DOMAIN_PORT_CRT) |            \
5721         BIT(POWER_DOMAIN_INIT))
5722
5723 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
5724         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
5725         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5726         BIT(POWER_DOMAIN_INIT))
5727
5728 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
5729         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
5730         BIT(POWER_DOMAIN_INIT))
5731
5732 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
5733         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
5734         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5735         BIT(POWER_DOMAIN_INIT))
5736
5737 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
5738         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
5739         BIT(POWER_DOMAIN_INIT))
5740
5741 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5742         .sync_hw = i9xx_always_on_power_well_noop,
5743         .enable = i9xx_always_on_power_well_noop,
5744         .disable = i9xx_always_on_power_well_noop,
5745         .is_enabled = i9xx_always_on_power_well_enabled,
5746 };
5747
5748 static struct i915_power_well i9xx_always_on_power_well[] = {
5749         {
5750                 .name = "always-on",
5751                 .always_on = 1,
5752                 .domains = POWER_DOMAIN_MASK,
5753                 .ops = &i9xx_always_on_power_well_ops,
5754         },
5755 };
5756
5757 static const struct i915_power_well_ops hsw_power_well_ops = {
5758         .sync_hw = hsw_power_well_sync_hw,
5759         .enable = hsw_power_well_enable,
5760         .disable = hsw_power_well_disable,
5761         .is_enabled = hsw_power_well_enabled,
5762 };
5763
5764 static struct i915_power_well hsw_power_wells[] = {
5765         {
5766                 .name = "always-on",
5767                 .always_on = 1,
5768                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5769                 .ops = &i9xx_always_on_power_well_ops,
5770         },
5771         {
5772                 .name = "display",
5773                 .domains = HSW_DISPLAY_POWER_DOMAINS,
5774                 .ops = &hsw_power_well_ops,
5775         },
5776 };
5777
5778 static struct i915_power_well bdw_power_wells[] = {
5779         {
5780                 .name = "always-on",
5781                 .always_on = 1,
5782                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5783                 .ops = &i9xx_always_on_power_well_ops,
5784         },
5785         {
5786                 .name = "display",
5787                 .domains = BDW_DISPLAY_POWER_DOMAINS,
5788                 .ops = &hsw_power_well_ops,
5789         },
5790 };
5791
5792 static const struct i915_power_well_ops vlv_display_power_well_ops = {
5793         .sync_hw = vlv_power_well_sync_hw,
5794         .enable = vlv_display_power_well_enable,
5795         .disable = vlv_display_power_well_disable,
5796         .is_enabled = vlv_power_well_enabled,
5797 };
5798
5799 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5800         .sync_hw = vlv_power_well_sync_hw,
5801         .enable = vlv_power_well_enable,
5802         .disable = vlv_power_well_disable,
5803         .is_enabled = vlv_power_well_enabled,
5804 };
5805
5806 static struct i915_power_well vlv_power_wells[] = {
5807         {
5808                 .name = "always-on",
5809                 .always_on = 1,
5810                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5811                 .ops = &i9xx_always_on_power_well_ops,
5812         },
5813         {
5814                 .name = "display",
5815                 .domains = VLV_DISPLAY_POWER_DOMAINS,
5816                 .data = PUNIT_POWER_WELL_DISP2D,
5817                 .ops = &vlv_display_power_well_ops,
5818         },
5819         {
5820                 .name = "dpio-common",
5821                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
5822                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
5823                 .ops = &vlv_dpio_power_well_ops,
5824         },
5825         {
5826                 .name = "dpio-tx-b-01",
5827                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5828                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5829                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5830                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5831                 .ops = &vlv_dpio_power_well_ops,
5832                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
5833         },
5834         {
5835                 .name = "dpio-tx-b-23",
5836                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5837                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5838                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5839                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5840                 .ops = &vlv_dpio_power_well_ops,
5841                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
5842         },
5843         {
5844                 .name = "dpio-tx-c-01",
5845                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5846                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5847                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5848                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5849                 .ops = &vlv_dpio_power_well_ops,
5850                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
5851         },
5852         {
5853                 .name = "dpio-tx-c-23",
5854                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5855                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5856                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5857                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5858                 .ops = &vlv_dpio_power_well_ops,
5859                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
5860         },
5861 };
5862
5863 #define set_power_wells(power_domains, __power_wells) ({                \
5864         (power_domains)->power_wells = (__power_wells);                 \
5865         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5866 })
5867
5868 int intel_power_domains_init(struct drm_i915_private *dev_priv)
5869 {
5870         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5871
5872         mutex_init(&power_domains->lock);
5873
5874         /*
5875          * The enabling order will be from lower to higher indexed wells,
5876          * the disabling order is reversed.
5877          */
5878         if (IS_HASWELL(dev_priv->dev)) {
5879                 set_power_wells(power_domains, hsw_power_wells);
5880                 hsw_pwr = power_domains;
5881         } else if (IS_BROADWELL(dev_priv->dev)) {
5882                 set_power_wells(power_domains, bdw_power_wells);
5883                 hsw_pwr = power_domains;
5884         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
5885                 set_power_wells(power_domains, vlv_power_wells);
5886         } else {
5887                 set_power_wells(power_domains, i9xx_always_on_power_well);
5888         }
5889
5890         return 0;
5891 }
5892
5893 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
5894 {
5895         hsw_pwr = NULL;
5896 }
5897
5898 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
5899 {
5900         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5901         struct i915_power_well *power_well;
5902         int i;
5903
5904         mutex_lock(&power_domains->lock);
5905         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
5906                 power_well->ops->sync_hw(dev_priv, power_well);
5907         mutex_unlock(&power_domains->lock);
5908 }
5909
5910 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
5911 {
5912         /* For now, we need the power well to be always enabled. */
5913         intel_display_set_init_power(dev_priv, true);
5914         intel_power_domains_resume(dev_priv);
5915 }
5916
5917 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5918 {
5919         intel_runtime_pm_get(dev_priv);
5920 }
5921
5922 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5923 {
5924         intel_runtime_pm_put(dev_priv);
5925 }
5926
5927 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5928 {
5929         struct drm_device *dev = dev_priv->dev;
5930         struct device *device = &dev->pdev->dev;
5931
5932         if (!HAS_RUNTIME_PM(dev))
5933                 return;
5934
5935         pm_runtime_get_sync(device);
5936         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5937 }
5938
5939 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5940 {
5941         struct drm_device *dev = dev_priv->dev;
5942         struct device *device = &dev->pdev->dev;
5943
5944         if (!HAS_RUNTIME_PM(dev))
5945                 return;
5946
5947         pm_runtime_mark_last_busy(device);
5948         pm_runtime_put_autosuspend(device);
5949 }
5950
5951 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5952 {
5953         struct drm_device *dev = dev_priv->dev;
5954         struct device *device = &dev->pdev->dev;
5955
5956         if (!HAS_RUNTIME_PM(dev))
5957                 return;
5958
5959         pm_runtime_set_active(device);
5960
5961         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5962         pm_runtime_mark_last_busy(device);
5963         pm_runtime_use_autosuspend(device);
5964
5965         pm_runtime_put_autosuspend(device);
5966 }
5967
5968 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5969 {
5970         struct drm_device *dev = dev_priv->dev;
5971         struct device *device = &dev->pdev->dev;
5972
5973         if (!HAS_RUNTIME_PM(dev))
5974                 return;
5975
5976         /* Make sure we're not suspended first. */
5977         pm_runtime_get_sync(device);
5978         pm_runtime_disable(device);
5979 }
5980
5981 /* Set up chip specific power management-related functions */
5982 void intel_init_pm(struct drm_device *dev)
5983 {
5984         struct drm_i915_private *dev_priv = dev->dev_private;
5985
5986         if (HAS_FBC(dev)) {
5987                 if (INTEL_INFO(dev)->gen >= 7) {
5988                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5989                         dev_priv->display.enable_fbc = gen7_enable_fbc;
5990                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5991                 } else if (INTEL_INFO(dev)->gen >= 5) {
5992                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5993                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5994                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5995                 } else if (IS_GM45(dev)) {
5996                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5997                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5998                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5999                 } else {
6000                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6001                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6002                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6003
6004                         /* This value was pulled out of someone's hat */
6005                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6006                 }
6007         }
6008
6009         /* For cxsr */
6010         if (IS_PINEVIEW(dev))
6011                 i915_pineview_get_mem_freq(dev);
6012         else if (IS_GEN5(dev))
6013                 i915_ironlake_get_mem_freq(dev);
6014
6015         /* For FIFO watermark updates */
6016         if (HAS_PCH_SPLIT(dev)) {
6017                 ilk_setup_wm_latency(dev);
6018
6019                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6020                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6021                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6022                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6023                         dev_priv->display.update_wm = ilk_update_wm;
6024                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6025                 } else {
6026                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6027                                       "Disable CxSR\n");
6028                 }
6029
6030                 if (IS_GEN5(dev))
6031                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6032                 else if (IS_GEN6(dev))
6033                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6034                 else if (IS_IVYBRIDGE(dev))
6035                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6036                 else if (IS_HASWELL(dev))
6037                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6038                 else if (INTEL_INFO(dev)->gen == 8)
6039                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6040         } else if (IS_VALLEYVIEW(dev)) {
6041                 dev_priv->display.update_wm = valleyview_update_wm;
6042                 dev_priv->display.init_clock_gating =
6043                         valleyview_init_clock_gating;
6044         } else if (IS_PINEVIEW(dev)) {
6045                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6046                                             dev_priv->is_ddr3,
6047                                             dev_priv->fsb_freq,
6048                                             dev_priv->mem_freq)) {
6049                         DRM_INFO("failed to find known CxSR latency "
6050                                  "(found ddr%s fsb freq %d, mem freq %d), "
6051                                  "disabling CxSR\n",
6052                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6053                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6054                         /* Disable CxSR and never update its watermark again */
6055                         pineview_disable_cxsr(dev);
6056                         dev_priv->display.update_wm = NULL;
6057                 } else
6058                         dev_priv->display.update_wm = pineview_update_wm;
6059                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6060         } else if (IS_G4X(dev)) {
6061                 dev_priv->display.update_wm = g4x_update_wm;
6062                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6063         } else if (IS_GEN4(dev)) {
6064                 dev_priv->display.update_wm = i965_update_wm;
6065                 if (IS_CRESTLINE(dev))
6066                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6067                 else if (IS_BROADWATER(dev))
6068                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6069         } else if (IS_GEN3(dev)) {
6070                 dev_priv->display.update_wm = i9xx_update_wm;
6071                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6072                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6073         } else if (IS_GEN2(dev)) {
6074                 if (INTEL_INFO(dev)->num_pipes == 1) {
6075                         dev_priv->display.update_wm = i845_update_wm;
6076                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6077                 } else {
6078                         dev_priv->display.update_wm = i9xx_update_wm;
6079                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6080                 }
6081
6082                 if (IS_I85X(dev) || IS_I865G(dev))
6083                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6084                 else
6085                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6086         } else {
6087                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6088         }
6089 }
6090
6091 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6092 {
6093         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6094
6095         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6096                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6097                 return -EAGAIN;
6098         }
6099
6100         I915_WRITE(GEN6_PCODE_DATA, *val);
6101         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6102
6103         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6104                      500)) {
6105                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6106                 return -ETIMEDOUT;
6107         }
6108
6109         *val = I915_READ(GEN6_PCODE_DATA);
6110         I915_WRITE(GEN6_PCODE_DATA, 0);
6111
6112         return 0;
6113 }
6114
6115 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6116 {
6117         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6118
6119         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6120                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6121                 return -EAGAIN;
6122         }
6123
6124         I915_WRITE(GEN6_PCODE_DATA, val);
6125         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6126
6127         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6128                      500)) {
6129                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6130                 return -ETIMEDOUT;
6131         }
6132
6133         I915_WRITE(GEN6_PCODE_DATA, 0);
6134
6135         return 0;
6136 }
6137
6138 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6139 {
6140         int div;
6141
6142         /* 4 x czclk */
6143         switch (dev_priv->mem_freq) {
6144         case 800:
6145                 div = 10;
6146                 break;
6147         case 1066:
6148                 div = 12;
6149                 break;
6150         case 1333:
6151                 div = 16;
6152                 break;
6153         default:
6154                 return -1;
6155         }
6156
6157         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6158 }
6159
6160 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6161 {
6162         int mul;
6163
6164         /* 4 x czclk */
6165         switch (dev_priv->mem_freq) {
6166         case 800:
6167                 mul = 10;
6168                 break;
6169         case 1066:
6170                 mul = 12;
6171                 break;
6172         case 1333:
6173                 mul = 16;
6174                 break;
6175         default:
6176                 return -1;
6177         }
6178
6179         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6180 }
6181
6182 void intel_pm_setup(struct drm_device *dev)
6183 {
6184         struct drm_i915_private *dev_priv = dev->dev_private;
6185
6186         mutex_init(&dev_priv->rps.hw_lock);
6187
6188         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6189                           intel_gen6_powersave_work);
6190
6191         dev_priv->pm.suspended = false;
6192         dev_priv->pm.irqs_disabled = false;
6193 }