drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_reg.h"
  35 #include "intel_drv.h"
  36
  37 /* Limits for overlay size. According to intel doc, the real limits are:
  38  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  39  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  40  * the mininum of both.  */
  41 #define IMAGE_MAX_WIDTH         2048
  42 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  43 /* on 830 and 845 these large limits result in the card hanging */
  44 #define IMAGE_MAX_WIDTH_LEGACY  1024
  45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  46
  47 /* overlay register definitions */
  48 /* OCMD register */
  49 #define OCMD_TILED_SURFACE      (0x1<<19)
  50 #define OCMD_MIRROR_MASK        (0x3<<17)
  51 #define OCMD_MIRROR_MODE        (0x3<<17)
  52 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  53 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  54 #define OCMD_MIRROR_BOTH        (0x3<<17)
  55 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  56 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  57 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  58 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  60 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  61 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  62 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_422_PACKED     (0x8<<10)
  64 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  65 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  66 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  67 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  68 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  69 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  70 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  71 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  72 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  73 #define OCMD_TEST_MODE          (0x1<<4)
  74 #define OCMD_BUFFER_SELECT      (0x3<<2)
  75 #define OCMD_BUFFER0            (0x0<<2)
  76 #define OCMD_BUFFER1            (0x1<<2)
  77 #define OCMD_FIELD_SELECT       (0x1<<2)
  78 #define OCMD_FIELD0             (0x0<<1)
  79 #define OCMD_FIELD1             (0x1<<1)
  80 #define OCMD_ENABLE             (0x1<<0)
  81
  82 /* OCONFIG register */
  83 #define OCONF_PIPE_MASK         (0x1<<18)
  84 #define OCONF_PIPE_A            (0x0<<18)
  85 #define OCONF_PIPE_B            (0x1<<18)
  86 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  87 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  88 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  89 #define OCONF_CSC_BYPASS        (0x1<<4)
  90 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  91 #define OCONF_TEST_MODE         (0x1<<2)
  92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  93 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  94
  95 /* DCLRKM (dst-key) register */
  96 #define DST_KEY_ENABLE          (0x1<<31)
  97 #define CLK_RGB24_MASK          0x0
  98 #define CLK_RGB16_MASK          0x070307
  99 #define CLK_RGB15_MASK          0x070707
 100 #define CLK_RGB8I_MASK          0xffffff
 101
 102 #define RGB16_TO_COLORKEY(c) \
 103         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 104 #define RGB15_TO_COLORKEY(c) \
 105         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 106
 107 /* overlay flip addr flag */
 108 #define OFC_UPDATE              0x1
 109
 110 /* polyphase filter coefficients */
 111 #define N_HORIZ_Y_TAPS          5
 112 #define N_VERT_Y_TAPS           3
 113 #define N_HORIZ_UV_TAPS         3
 114 #define N_VERT_UV_TAPS          3
 115 #define N_PHASES                17
 116 #define MAX_TAPS                5
 117
 118 /* memory bufferd overlay registers */
 119 struct overlay_registers {
 120         u32 OBUF_0Y;
 121         u32 OBUF_1Y;
 122         u32 OBUF_0U;
 123         u32 OBUF_0V;
 124         u32 OBUF_1U;
 125         u32 OBUF_1V;
 126         u32 OSTRIDE;
 127         u32 YRGB_VPH;
 128         u32 UV_VPH;
 129         u32 HORZ_PH;
 130         u32 INIT_PHS;
 131         u32 DWINPOS;
 132         u32 DWINSZ;
 133         u32 SWIDTH;
 134         u32 SWIDTHSW;
 135         u32 SHEIGHT;
 136         u32 YRGBSCALE;
 137         u32 UVSCALE;
 138         u32 OCLRC0;
 139         u32 OCLRC1;
 140         u32 DCLRKV;
 141         u32 DCLRKM;
 142         u32 SCLRKVH;
 143         u32 SCLRKVL;
 144         u32 SCLRKEN;
 145         u32 OCONFIG;
 146         u32 OCMD;
 147         u32 RESERVED1; /* 0x6C */
 148         u32 OSTART_0Y;
 149         u32 OSTART_1Y;
 150         u32 OSTART_0U;
 151         u32 OSTART_0V;
 152         u32 OSTART_1U;
 153         u32 OSTART_1V;
 154         u32 OTILEOFF_0Y;
 155         u32 OTILEOFF_1Y;
 156         u32 OTILEOFF_0U;
 157         u32 OTILEOFF_0V;
 158         u32 OTILEOFF_1U;
 159         u32 OTILEOFF_1V;
 160         u32 FASTHSCALE; /* 0xA0 */
 161         u32 UVSCALEV; /* 0xA4 */
 162         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 163         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 164         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 165         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 166         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 167         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 168         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 169         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 170         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 171 };
 172
 173 struct intel_overlay {
 174         struct drm_device *dev;
 175         struct intel_crtc *crtc;
 176         struct drm_i915_gem_object *vid_bo;
 177         struct drm_i915_gem_object *old_vid_bo;
 178         int active;
 179         int pfit_active;
 180         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 181         u32 color_key;
 182         u32 brightness, contrast, saturation;
 183         u32 old_xscale, old_yscale;
 184         /* register access */
 185         u32 flip_addr;
 186         struct drm_i915_gem_object *reg_bo;
 187         /* flip handling */
 188         uint32_t last_flip_req;
 189         void (*flip_tail)(struct intel_overlay *);
 190 };
 191
 192 static struct overlay_registers *
 193 intel_overlay_map_regs(struct intel_overlay *overlay)
 194 {
 195         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
 196         struct overlay_registers *regs;
 197
 198         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 199                 regs = overlay->reg_bo->phys_obj->handle->vaddr;
 200         else
 201                 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
 202                                          overlay->reg_bo->gtt_offset);
 203
 204         return regs;
 205 }
 206
 207 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 208                                      struct overlay_registers *regs)
 209 {
 210         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 211                 io_mapping_unmap(regs);
 212 }
 213
 214 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 215                                          struct drm_i915_gem_request *request,
 216                                          void (*tail)(struct intel_overlay *))
 217 {
 218         struct drm_device *dev = overlay->dev;
 219         drm_i915_private_t *dev_priv = dev->dev_private;
 220         int ret;
 221
 222         BUG_ON(overlay->last_flip_req);
 223         ret = i915_add_request(LP_RING(dev_priv), NULL, request);
 224         if (ret) {
 225             kfree(request);
 226             return ret;
 227         }
 228         overlay->last_flip_req = request->seqno;
 229         overlay->flip_tail = tail;
 230         ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req);
 231         if (ret)
 232                 return ret;
 233
 234         overlay->last_flip_req = 0;
 235         return 0;
 236 }
 237
 238 /* Workaround for i830 bug where pipe a must be enable to change control regs */
 239 static int
 240 i830_activate_pipe_a(struct drm_device *dev)
 241 {
 242         drm_i915_private_t *dev_priv = dev->dev_private;
 243         struct intel_crtc *crtc;
 244         struct drm_crtc_helper_funcs *crtc_funcs;
 245         struct drm_display_mode vesa_640x480 = {
 246                 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 247                          752, 800, 0, 480, 489, 492, 525, 0,
 248                          DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
 249         }, *mode;
 250
 251         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
 252         if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
 253                 return 0;
 254
 255         /* most i8xx have pipe a forced on, so don't trust dpms mode */
 256         if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
 257                 return 0;
 258
 259         crtc_funcs = crtc->base.helper_private;
 260         if (crtc_funcs->dpms == NULL)
 261                 return 0;
 262
 263         DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
 264
 265         mode = drm_mode_duplicate(dev, &vesa_640x480);
 266         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
 267         if (!drm_crtc_helper_set_mode(&crtc->base, mode,
 268                                        crtc->base.x, crtc->base.y,
 269                                        crtc->base.fb))
 270                 return 0;
 271
 272         crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
 273         return 1;
 274 }
 275
 276 static void
 277 i830_deactivate_pipe_a(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
 281         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 282
 283         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 284 }
 285
 286 /* overlay needs to be disable in OCMD reg */
 287 static int intel_overlay_on(struct intel_overlay *overlay)
 288 {
 289         struct drm_device *dev = overlay->dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         struct drm_i915_gem_request *request;
 292         int pipe_a_quirk = 0;
 293         int ret;
 294
 295         BUG_ON(overlay->active);
 296         overlay->active = 1;
 297
 298         if (IS_I830(dev)) {
 299                 pipe_a_quirk = i830_activate_pipe_a(dev);
 300                 if (pipe_a_quirk < 0)
 301                         return pipe_a_quirk;
 302         }
 303
 304         request = kzalloc(sizeof(*request), GFP_KERNEL);
 305         if (request == NULL) {
 306                 ret = -ENOMEM;
 307                 goto out;
 308         }
 309
 310         ret = BEGIN_LP_RING(4);
 311         if (ret) {
 312                 kfree(request);
 313                 goto out;
 314         }
 315
 316         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 317         OUT_RING(overlay->flip_addr | OFC_UPDATE);
 318         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 319         OUT_RING(MI_NOOP);
 320         ADVANCE_LP_RING();
 321
 322         ret = intel_overlay_do_wait_request(overlay, request, NULL);
 323 out:
 324         if (pipe_a_quirk)
 325                 i830_deactivate_pipe_a(dev);
 326
 327         return ret;
 328 }
 329
 330 /* overlay needs to be enabled in OCMD reg */
 331 static int intel_overlay_continue(struct intel_overlay *overlay,
 332                                   bool load_polyphase_filter)
 333 {
 334         struct drm_device *dev = overlay->dev;
 335         drm_i915_private_t *dev_priv = dev->dev_private;
 336         struct drm_i915_gem_request *request;
 337         u32 flip_addr = overlay->flip_addr;
 338         u32 tmp;
 339         int ret;
 340
 341         BUG_ON(!overlay->active);
 342
 343         request = kzalloc(sizeof(*request), GFP_KERNEL);
 344         if (request == NULL)
 345                 return -ENOMEM;
 346
 347         if (load_polyphase_filter)
 348                 flip_addr |= OFC_UPDATE;
 349
 350         /* check for underruns */
 351         tmp = I915_READ(DOVSTA);
 352         if (tmp & (1 << 17))
 353                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 354
 355         ret = BEGIN_LP_RING(2);
 356         if (ret) {
 357                 kfree(request);
 358                 return ret;
 359         }
 360         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 361         OUT_RING(flip_addr);
 362         ADVANCE_LP_RING();
 363
 364         ret = i915_add_request(LP_RING(dev_priv), NULL, request);
 365         if (ret) {
 366                 kfree(request);
 367                 return ret;
 368         }
 369
 370         overlay->last_flip_req = request->seqno;
 371         return 0;
 372 }
 373
 374 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 375 {
 376         struct drm_i915_gem_object *obj = overlay->old_vid_bo;
 377
 378         i915_gem_object_unpin(obj);
 379         drm_gem_object_unreference(&obj->base);
 380
 381         overlay->old_vid_bo = NULL;
 382 }
 383
 384 static void intel_overlay_off_tail(struct intel_overlay *overlay)
 385 {
 386         struct drm_i915_gem_object *obj = overlay->vid_bo;
 387
 388         /* never have the overlay hw on without showing a frame */
 389         BUG_ON(!overlay->vid_bo);
 390
 391         i915_gem_object_unpin(obj);
 392         drm_gem_object_unreference(&obj->base);
 393         overlay->vid_bo = NULL;
 394
 395         overlay->crtc->overlay = NULL;
 396         overlay->crtc = NULL;
 397         overlay->active = 0;
 398 }
 399
 400 /* overlay needs to be disabled in OCMD reg */
 401 static int intel_overlay_off(struct intel_overlay *overlay)
 402 {
 403         struct drm_device *dev = overlay->dev;
 404         struct drm_i915_private *dev_priv = dev->dev_private;
 405         u32 flip_addr = overlay->flip_addr;
 406         struct drm_i915_gem_request *request;
 407         int ret;
 408
 409         BUG_ON(!overlay->active);
 410
 411         request = kzalloc(sizeof(*request), GFP_KERNEL);
 412         if (request == NULL)
 413                 return -ENOMEM;
 414
 415         /* According to intel docs the overlay hw may hang (when switching
 416          * off) without loading the filter coeffs. It is however unclear whether
 417          * this applies to the disabling of the overlay or to the switching off
 418          * of the hw. Do it in both cases */
 419         flip_addr |= OFC_UPDATE;
 420
 421         ret = BEGIN_LP_RING(6);
 422         if (ret) {
 423                 kfree(request);
 424                 return ret;
 425         }
 426         /* wait for overlay to go idle */
 427         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 428         OUT_RING(flip_addr);
 429         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 430         /* turn overlay off */
 431         if (IS_I830(dev)) {
 432                 /* Workaround: Don't disable the overlay fully, since otherwise
 433                  * it dies on the next OVERLAY_ON cmd. */
 434                 OUT_RING(MI_NOOP);
 435                 OUT_RING(MI_NOOP);
 436                 OUT_RING(MI_NOOP);
 437         } else {
 438                 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 439                 OUT_RING(flip_addr);
 440                 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 441         }
 442         ADVANCE_LP_RING();
 443
 444         return intel_overlay_do_wait_request(overlay, request,
 445                                              intel_overlay_off_tail);
 446 }
 447
 448 /* recover from an interruption due to a signal
 449  * We have to be careful not to repeat work forever an make forward progess. */
 450 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 451 {
 452         struct drm_device *dev = overlay->dev;
 453         drm_i915_private_t *dev_priv = dev->dev_private;
 454         int ret;
 455
 456         if (overlay->last_flip_req == 0)
 457                 return 0;
 458
 459         ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req);
 460         if (ret)
 461                 return ret;
 462
 463         if (overlay->flip_tail)
 464                 overlay->flip_tail(overlay);
 465
 466         overlay->last_flip_req = 0;
 467         return 0;
 468 }
 469
 470 /* Wait for pending overlay flip and release old frame.
 471  * Needs to be called before the overlay register are changed
 472  * via intel_overlay_(un)map_regs
 473  */
 474 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 475 {
 476         struct drm_device *dev = overlay->dev;
 477         drm_i915_private_t *dev_priv = dev->dev_private;
 478         int ret;
 479
 480         /* Only wait if there is actually an old frame to release to
 481          * guarantee forward progress.
 482          */
 483         if (!overlay->old_vid_bo)
 484                 return 0;
 485
 486         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 487                 struct drm_i915_gem_request *request;
 488
 489                 /* synchronous slowpath */
 490                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 491                 if (request == NULL)
 492                         return -ENOMEM;
 493
 494                 ret = BEGIN_LP_RING(2);
 495                 if (ret) {
 496                         kfree(request);
 497                         return ret;
 498                 }
 499
 500                 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 501                 OUT_RING(MI_NOOP);
 502                 ADVANCE_LP_RING();
 503
 504                 ret = intel_overlay_do_wait_request(overlay, request,
 505                                                     intel_overlay_release_old_vid_tail);
 506                 if (ret)
 507                         return ret;
 508         }
 509
 510         intel_overlay_release_old_vid_tail(overlay);
 511         return 0;
 512 }
 513
 514 struct put_image_params {
 515         int format;
 516         short dst_x;
 517         short dst_y;
 518         short dst_w;
 519         short dst_h;
 520         short src_w;
 521         short src_scan_h;
 522         short src_scan_w;
 523         short src_h;
 524         short stride_Y;
 525         short stride_UV;
 526         int offset_Y;
 527         int offset_U;
 528         int offset_V;
 529 };
 530
 531 static int packed_depth_bytes(u32 format)
 532 {
 533         switch (format & I915_OVERLAY_DEPTH_MASK) {
 534         case I915_OVERLAY_YUV422:
 535                 return 4;
 536         case I915_OVERLAY_YUV411:
 537                 /* return 6; not implemented */
 538         default:
 539                 return -EINVAL;
 540         }
 541 }
 542
 543 static int packed_width_bytes(u32 format, short width)
 544 {
 545         switch (format & I915_OVERLAY_DEPTH_MASK) {
 546         case I915_OVERLAY_YUV422:
 547                 return width << 1;
 548         default:
 549                 return -EINVAL;
 550         }
 551 }
 552
 553 static int uv_hsubsampling(u32 format)
 554 {
 555         switch (format & I915_OVERLAY_DEPTH_MASK) {
 556         case I915_OVERLAY_YUV422:
 557         case I915_OVERLAY_YUV420:
 558                 return 2;
 559         case I915_OVERLAY_YUV411:
 560         case I915_OVERLAY_YUV410:
 561                 return 4;
 562         default:
 563                 return -EINVAL;
 564         }
 565 }
 566
 567 static int uv_vsubsampling(u32 format)
 568 {
 569         switch (format & I915_OVERLAY_DEPTH_MASK) {
 570         case I915_OVERLAY_YUV420:
 571         case I915_OVERLAY_YUV410:
 572                 return 2;
 573         case I915_OVERLAY_YUV422:
 574         case I915_OVERLAY_YUV411:
 575                 return 1;
 576         default:
 577                 return -EINVAL;
 578         }
 579 }
 580
 581 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
 582 {
 583         u32 mask, shift, ret;
 584         if (IS_GEN2(dev)) {
 585                 mask = 0x1f;
 586                 shift = 5;
 587         } else {
 588                 mask = 0x3f;
 589                 shift = 6;
 590         }
 591         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 592         if (!IS_GEN2(dev))
 593                 ret <<= 1;
 594         ret -= 1;
 595         return ret << 2;
 596 }
 597
 598 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 599         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 600         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 601         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 602         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 603         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 604         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 605         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 606         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 607         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 608         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 609         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 610         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 611         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 612         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 613         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 614         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 615         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 616 };
 617
 618 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 619         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 620         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 621         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 622         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 623         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 624         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 625         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 626         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 627         0x3000, 0x0800, 0x3000
 628 };
 629
 630 static void update_polyphase_filter(struct overlay_registers *regs)
 631 {
 632         memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 633         memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
 634 }
 635
 636 static bool update_scaling_factors(struct intel_overlay *overlay,
 637                                    struct overlay_registers *regs,
 638                                    struct put_image_params *params)
 639 {
 640         /* fixed point with a 12 bit shift */
 641         u32 xscale, yscale, xscale_UV, yscale_UV;
 642 #define FP_SHIFT 12
 643 #define FRACT_MASK 0xfff
 644         bool scale_changed = false;
 645         int uv_hscale = uv_hsubsampling(params->format);
 646         int uv_vscale = uv_vsubsampling(params->format);
 647
 648         if (params->dst_w > 1)
 649                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 650                         /(params->dst_w);
 651         else
 652                 xscale = 1 << FP_SHIFT;
 653
 654         if (params->dst_h > 1)
 655                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 656                         /(params->dst_h);
 657         else
 658                 yscale = 1 << FP_SHIFT;
 659
 660         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 661         xscale_UV = xscale/uv_hscale;
 662         yscale_UV = yscale/uv_vscale;
 663         /* make the Y scale to UV scale ratio an exact multiply */
 664         xscale = xscale_UV * uv_hscale;
 665         yscale = yscale_UV * uv_vscale;
 666         /*} else {
 667           xscale_UV = 0;
 668           yscale_UV = 0;
 669           }*/
 670
 671         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 672                 scale_changed = true;
 673         overlay->old_xscale = xscale;
 674         overlay->old_yscale = yscale;
 675
 676         regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
 677                            ((xscale >> FP_SHIFT)  << 16) |
 678                            ((xscale & FRACT_MASK) << 3));
 679
 680         regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
 681                          ((xscale_UV >> FP_SHIFT)  << 16) |
 682                          ((xscale_UV & FRACT_MASK) << 3));
 683
 684         regs->UVSCALEV = ((((yscale    >> FP_SHIFT) << 16) |
 685                            ((yscale_UV >> FP_SHIFT) << 0)));
 686
 687         if (scale_changed)
 688                 update_polyphase_filter(regs);
 689
 690         return scale_changed;
 691 }
 692
 693 static void update_colorkey(struct intel_overlay *overlay,
 694                             struct overlay_registers *regs)
 695 {
 696         u32 key = overlay->color_key;
 697
 698         switch (overlay->crtc->base.fb->bits_per_pixel) {
 699         case 8:
 700                 regs->DCLRKV = 0;
 701                 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
 702                 break;
 703
 704         case 16:
 705                 if (overlay->crtc->base.fb->depth == 15) {
 706                         regs->DCLRKV = RGB15_TO_COLORKEY(key);
 707                         regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
 708                 } else {
 709                         regs->DCLRKV = RGB16_TO_COLORKEY(key);
 710                         regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
 711                 }
 712                 break;
 713
 714         case 24:
 715         case 32:
 716                 regs->DCLRKV = key;
 717                 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
 718                 break;
 719         }
 720 }
 721
 722 static u32 overlay_cmd_reg(struct put_image_params *params)
 723 {
 724         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 725
 726         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 727                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 728                 case I915_OVERLAY_YUV422:
 729                         cmd |= OCMD_YUV_422_PLANAR;
 730                         break;
 731                 case I915_OVERLAY_YUV420:
 732                         cmd |= OCMD_YUV_420_PLANAR;
 733                         break;
 734                 case I915_OVERLAY_YUV411:
 735                 case I915_OVERLAY_YUV410:
 736                         cmd |= OCMD_YUV_410_PLANAR;
 737                         break;
 738                 }
 739         } else { /* YUV packed */
 740                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 741                 case I915_OVERLAY_YUV422:
 742                         cmd |= OCMD_YUV_422_PACKED;
 743                         break;
 744                 case I915_OVERLAY_YUV411:
 745                         cmd |= OCMD_YUV_411_PACKED;
 746                         break;
 747                 }
 748
 749                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 750                 case I915_OVERLAY_NO_SWAP:
 751                         break;
 752                 case I915_OVERLAY_UV_SWAP:
 753                         cmd |= OCMD_UV_SWAP;
 754                         break;
 755                 case I915_OVERLAY_Y_SWAP:
 756                         cmd |= OCMD_Y_SWAP;
 757                         break;
 758                 case I915_OVERLAY_Y_AND_UV_SWAP:
 759                         cmd |= OCMD_Y_AND_UV_SWAP;
 760                         break;
 761                 }
 762         }
 763
 764         return cmd;
 765 }
 766
 767 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 768                                       struct drm_i915_gem_object *new_bo,
 769                                       struct put_image_params *params)
 770 {
 771         int ret, tmp_width;
 772         struct overlay_registers *regs;
 773         bool scale_changed = false;
 774         struct drm_device *dev = overlay->dev;
 775
 776         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 777         BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
 778         BUG_ON(!overlay);
 779
 780         ret = intel_overlay_release_old_vid(overlay);
 781         if (ret != 0)
 782                 return ret;
 783
 784         ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
 785         if (ret != 0)
 786                 return ret;
 787
 788         ret = i915_gem_object_put_fence(new_bo);
 789         if (ret)
 790                 goto out_unpin;
 791
 792         if (!overlay->active) {
 793                 regs = intel_overlay_map_regs(overlay);
 794                 if (!regs) {
 795                         ret = -ENOMEM;
 796                         goto out_unpin;
 797                 }
 798                 regs->OCONFIG = OCONF_CC_OUT_8BIT;
 799                 if (IS_GEN4(overlay->dev))
 800                         regs->OCONFIG |= OCONF_CSC_MODE_BT709;
 801                 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
 802                         OCONF_PIPE_A : OCONF_PIPE_B;
 803                 intel_overlay_unmap_regs(overlay, regs);
 804
 805                 ret = intel_overlay_on(overlay);
 806                 if (ret != 0)
 807                         goto out_unpin;
 808         }
 809
 810         regs = intel_overlay_map_regs(overlay);
 811         if (!regs) {
 812                 ret = -ENOMEM;
 813                 goto out_unpin;
 814         }
 815
 816         regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
 817         regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
 818
 819         if (params->format & I915_OVERLAY_YUV_PACKED)
 820                 tmp_width = packed_width_bytes(params->format, params->src_w);
 821         else
 822                 tmp_width = params->src_w;
 823
 824         regs->SWIDTH = params->src_w;
 825         regs->SWIDTHSW = calc_swidthsw(overlay->dev,
 826                                        params->offset_Y, tmp_width);
 827         regs->SHEIGHT = params->src_h;
 828         regs->OBUF_0Y = new_bo->gtt_offset + params->offset_Y;
 829         regs->OSTRIDE = params->stride_Y;
 830
 831         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 832                 int uv_hscale = uv_hsubsampling(params->format);
 833                 int uv_vscale = uv_vsubsampling(params->format);
 834                 u32 tmp_U, tmp_V;
 835                 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
 836                 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
 837                                       params->src_w/uv_hscale);
 838                 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
 839                                       params->src_w/uv_hscale);
 840                 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
 841                 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
 842                 regs->OBUF_0U = new_bo->gtt_offset + params->offset_U;
 843                 regs->OBUF_0V = new_bo->gtt_offset + params->offset_V;
 844                 regs->OSTRIDE |= params->stride_UV << 16;
 845         }
 846
 847         scale_changed = update_scaling_factors(overlay, regs, params);
 848
 849         update_colorkey(overlay, regs);
 850
 851         regs->OCMD = overlay_cmd_reg(params);
 852
 853         intel_overlay_unmap_regs(overlay, regs);
 854
 855         ret = intel_overlay_continue(overlay, scale_changed);
 856         if (ret)
 857                 goto out_unpin;
 858
 859         overlay->old_vid_bo = overlay->vid_bo;
 860         overlay->vid_bo = new_bo;
 861
 862         return 0;
 863
 864 out_unpin:
 865         i915_gem_object_unpin(new_bo);
 866         return ret;
 867 }
 868
 869 int intel_overlay_switch_off(struct intel_overlay *overlay)
 870 {
 871         struct overlay_registers *regs;
 872         struct drm_device *dev = overlay->dev;
 873         int ret;
 874
 875         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
 876         BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
 877
 878         ret = intel_overlay_recover_from_interrupt(overlay);
 879         if (ret != 0)
 880                 return ret;
 881
 882         if (!overlay->active)
 883                 return 0;
 884
 885         ret = intel_overlay_release_old_vid(overlay);
 886         if (ret != 0)
 887                 return ret;
 888
 889         regs = intel_overlay_map_regs(overlay);
 890         regs->OCMD = 0;
 891         intel_overlay_unmap_regs(overlay, regs);
 892
 893         ret = intel_overlay_off(overlay);
 894         if (ret != 0)
 895                 return ret;
 896
 897         intel_overlay_off_tail(overlay);
 898         return 0;
 899 }
 900
 901 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 902                                           struct intel_crtc *crtc)
 903 {
 904         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
 905
 906         if (!crtc->active)
 907                 return -EINVAL;
 908
 909         /* can't use the overlay with double wide pipe */
 910         if (INTEL_INFO(overlay->dev)->gen < 4 &&
 911             (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
 912                 return -EINVAL;
 913
 914         return 0;
 915 }
 916
 917 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 918 {
 919         struct drm_device *dev = overlay->dev;
 920         drm_i915_private_t *dev_priv = dev->dev_private;
 921         u32 pfit_control = I915_READ(PFIT_CONTROL);
 922         u32 ratio;
 923
 924         /* XXX: This is not the same logic as in the xorg driver, but more in
 925          * line with the intel documentation for the i965
 926          */
 927         if (INTEL_INFO(dev)->gen >= 4) {
 928                 /* on i965 use the PGM reg to read out the autoscaler values */
 929                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 930         } else {
 931                 if (pfit_control & VERT_AUTO_SCALE)
 932                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 933                 else
 934                         ratio = I915_READ(PFIT_PGM_RATIOS);
 935                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 936         }
 937
 938         overlay->pfit_vscale_ratio = ratio;
 939 }
 940
 941 static int check_overlay_dst(struct intel_overlay *overlay,
 942                              struct drm_intel_overlay_put_image *rec)
 943 {
 944         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 945
 946         if (rec->dst_x < mode->crtc_hdisplay &&
 947             rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
 948             rec->dst_y < mode->crtc_vdisplay &&
 949             rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
 950                 return 0;
 951         else
 952                 return -EINVAL;
 953 }
 954
 955 static int check_overlay_scaling(struct put_image_params *rec)
 956 {
 957         u32 tmp;
 958
 959         /* downscaling limit is 8.0 */
 960         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 961         if (tmp > 7)
 962                 return -EINVAL;
 963         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 964         if (tmp > 7)
 965                 return -EINVAL;
 966
 967         return 0;
 968 }
 969
 970 static int check_overlay_src(struct drm_device *dev,
 971                              struct drm_intel_overlay_put_image *rec,
 972                              struct drm_i915_gem_object *new_bo)
 973 {
 974         int uv_hscale = uv_hsubsampling(rec->flags);
 975         int uv_vscale = uv_vsubsampling(rec->flags);
 976         u32 stride_mask;
 977         int depth;
 978         u32 tmp;
 979
 980         /* check src dimensions */
 981         if (IS_845G(dev) || IS_I830(dev)) {
 982                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 983                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 984                         return -EINVAL;
 985         } else {
 986                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 987                     rec->src_width  > IMAGE_MAX_WIDTH)
 988                         return -EINVAL;
 989         }
 990
 991         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 992         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 993             rec->src_width  < N_HORIZ_Y_TAPS*4)
 994                 return -EINVAL;
 995
 996         /* check alignment constraints */
 997         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 998         case I915_OVERLAY_RGB:
 999                 /* not implemented */
1000                 return -EINVAL;
1001
1002         case I915_OVERLAY_YUV_PACKED:
1003                 if (uv_vscale != 1)
1004                         return -EINVAL;
1005
1006                 depth = packed_depth_bytes(rec->flags);
1007                 if (depth < 0)
1008                         return depth;
1009
1010                 /* ignore UV planes */
1011                 rec->stride_UV = 0;
1012                 rec->offset_U = 0;
1013                 rec->offset_V = 0;
1014                 /* check pixel alignment */
1015                 if (rec->offset_Y % depth)
1016                         return -EINVAL;
1017                 break;
1018
1019         case I915_OVERLAY_YUV_PLANAR:
1020                 if (uv_vscale < 0 || uv_hscale < 0)
1021                         return -EINVAL;
1022                 /* no offset restrictions for planar formats */
1023                 break;
1024
1025         default:
1026                 return -EINVAL;
1027         }
1028
1029         if (rec->src_width % uv_hscale)
1030                 return -EINVAL;
1031
1032         /* stride checking */
1033         if (IS_I830(dev) || IS_845G(dev))
1034                 stride_mask = 255;
1035         else
1036                 stride_mask = 63;
1037
1038         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1039                 return -EINVAL;
1040         if (IS_GEN4(dev) && rec->stride_Y < 512)
1041                 return -EINVAL;
1042
1043         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1044                 4096 : 8192;
1045         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1046                 return -EINVAL;
1047
1048         /* check buffer dimensions */
1049         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1050         case I915_OVERLAY_RGB:
1051         case I915_OVERLAY_YUV_PACKED:
1052                 /* always 4 Y values per depth pixels */
1053                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1054                         return -EINVAL;
1055
1056                 tmp = rec->stride_Y*rec->src_height;
1057                 if (rec->offset_Y + tmp > new_bo->base.size)
1058                         return -EINVAL;
1059                 break;
1060
1061         case I915_OVERLAY_YUV_PLANAR:
1062                 if (rec->src_width > rec->stride_Y)
1063                         return -EINVAL;
1064                 if (rec->src_width/uv_hscale > rec->stride_UV)
1065                         return -EINVAL;
1066
1067                 tmp = rec->stride_Y * rec->src_height;
1068                 if (rec->offset_Y + tmp > new_bo->base.size)
1069                         return -EINVAL;
1070
1071                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1072                 if (rec->offset_U + tmp > new_bo->base.size ||
1073                     rec->offset_V + tmp > new_bo->base.size)
1074                         return -EINVAL;
1075                 break;
1076         }
1077
1078         return 0;
1079 }
1080
1081 /**
1082  * Return the pipe currently connected to the panel fitter,
1083  * or -1 if the panel fitter is not present or not in use
1084  */
1085 static int intel_panel_fitter_pipe(struct drm_device *dev)
1086 {
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088         u32  pfit_control;
1089
1090         /* i830 doesn't have a panel fitter */
1091         if (IS_I830(dev))
1092                 return -1;
1093
1094         pfit_control = I915_READ(PFIT_CONTROL);
1095
1096         /* See if the panel fitter is in use */
1097         if ((pfit_control & PFIT_ENABLE) == 0)
1098                 return -1;
1099
1100         /* 965 can place panel fitter on either pipe */
1101         if (IS_GEN4(dev))
1102                 return (pfit_control >> 29) & 0x3;
1103
1104         /* older chips can only use pipe 1 */
1105         return 1;
1106 }
1107
1108 int intel_overlay_put_image(struct drm_device *dev, void *data,
1109                             struct drm_file *file_priv)
1110 {
1111         struct drm_intel_overlay_put_image *put_image_rec = data;
1112         drm_i915_private_t *dev_priv = dev->dev_private;
1113         struct intel_overlay *overlay;
1114         struct drm_mode_object *drmmode_obj;
1115         struct intel_crtc *crtc;
1116         struct drm_i915_gem_object *new_bo;
1117         struct put_image_params *params;
1118         int ret;
1119
1120         if (!dev_priv) {
1121                 DRM_ERROR("called with no initialization\n");
1122                 return -EINVAL;
1123         }
1124
1125         overlay = dev_priv->overlay;
1126         if (!overlay) {
1127                 DRM_DEBUG("userspace bug: no overlay\n");
1128                 return -ENODEV;
1129         }
1130
1131         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1132                 mutex_lock(&dev->mode_config.mutex);
1133                 mutex_lock(&dev->struct_mutex);
1134
1135                 ret = intel_overlay_switch_off(overlay);
1136
1137                 mutex_unlock(&dev->struct_mutex);
1138                 mutex_unlock(&dev->mode_config.mutex);
1139
1140                 return ret;
1141         }
1142
1143         params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1144         if (!params)
1145                 return -ENOMEM;
1146
1147         drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1148                                            DRM_MODE_OBJECT_CRTC);
1149         if (!drmmode_obj) {
1150                 ret = -ENOENT;
1151                 goto out_free;
1152         }
1153         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1154
1155         new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1156                                                    put_image_rec->bo_handle));
1157         if (&new_bo->base == NULL) {
1158                 ret = -ENOENT;
1159                 goto out_free;
1160         }
1161
1162         mutex_lock(&dev->mode_config.mutex);
1163         mutex_lock(&dev->struct_mutex);
1164
1165         if (new_bo->tiling_mode) {
1166                 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1167                 ret = -EINVAL;
1168                 goto out_unlock;
1169         }
1170
1171         ret = intel_overlay_recover_from_interrupt(overlay);
1172         if (ret != 0)
1173                 goto out_unlock;
1174
1175         if (overlay->crtc != crtc) {
1176                 struct drm_display_mode *mode = &crtc->base.mode;
1177                 ret = intel_overlay_switch_off(overlay);
1178                 if (ret != 0)
1179                         goto out_unlock;
1180
1181                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1182                 if (ret != 0)
1183                         goto out_unlock;
1184
1185                 overlay->crtc = crtc;
1186                 crtc->overlay = overlay;
1187
1188                 /* line too wide, i.e. one-line-mode */
1189                 if (mode->hdisplay > 1024 &&
1190                     intel_panel_fitter_pipe(dev) == crtc->pipe) {
1191                         overlay->pfit_active = 1;
1192                         update_pfit_vscale_ratio(overlay);
1193                 } else
1194                         overlay->pfit_active = 0;
1195         }
1196
1197         ret = check_overlay_dst(overlay, put_image_rec);
1198         if (ret != 0)
1199                 goto out_unlock;
1200
1201         if (overlay->pfit_active) {
1202                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1203                                  overlay->pfit_vscale_ratio);
1204                 /* shifting right rounds downwards, so add 1 */
1205                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1206                                  overlay->pfit_vscale_ratio) + 1;
1207         } else {
1208                 params->dst_y = put_image_rec->dst_y;
1209                 params->dst_h = put_image_rec->dst_height;
1210         }
1211         params->dst_x = put_image_rec->dst_x;
1212         params->dst_w = put_image_rec->dst_width;
1213
1214         params->src_w = put_image_rec->src_width;
1215         params->src_h = put_image_rec->src_height;
1216         params->src_scan_w = put_image_rec->src_scan_width;
1217         params->src_scan_h = put_image_rec->src_scan_height;
1218         if (params->src_scan_h > params->src_h ||
1219             params->src_scan_w > params->src_w) {
1220                 ret = -EINVAL;
1221                 goto out_unlock;
1222         }
1223
1224         ret = check_overlay_src(dev, put_image_rec, new_bo);
1225         if (ret != 0)
1226                 goto out_unlock;
1227         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1228         params->stride_Y = put_image_rec->stride_Y;
1229         params->stride_UV = put_image_rec->stride_UV;
1230         params->offset_Y = put_image_rec->offset_Y;
1231         params->offset_U = put_image_rec->offset_U;
1232         params->offset_V = put_image_rec->offset_V;
1233
1234         /* Check scaling after src size to prevent a divide-by-zero. */
1235         ret = check_overlay_scaling(params);
1236         if (ret != 0)
1237                 goto out_unlock;
1238
1239         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1240         if (ret != 0)
1241                 goto out_unlock;
1242
1243         mutex_unlock(&dev->struct_mutex);
1244         mutex_unlock(&dev->mode_config.mutex);
1245
1246         kfree(params);
1247
1248         return 0;
1249
1250 out_unlock:
1251         mutex_unlock(&dev->struct_mutex);
1252         mutex_unlock(&dev->mode_config.mutex);
1253         drm_gem_object_unreference_unlocked(&new_bo->base);
1254 out_free:
1255         kfree(params);
1256
1257         return ret;
1258 }
1259
1260 static void update_reg_attrs(struct intel_overlay *overlay,
1261                              struct overlay_registers *regs)
1262 {
1263         regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1264         regs->OCLRC1 = overlay->saturation;
1265 }
1266
1267 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1268 {
1269         int i;
1270
1271         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1272                 return false;
1273
1274         for (i = 0; i < 3; i++) {
1275                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1276                         return false;
1277         }
1278
1279         return true;
1280 }
1281
1282 static bool check_gamma5_errata(u32 gamma5)
1283 {
1284         int i;
1285
1286         for (i = 0; i < 3; i++) {
1287                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1288                         return false;
1289         }
1290
1291         return true;
1292 }
1293
1294 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1295 {
1296         if (!check_gamma_bounds(0, attrs->gamma0) ||
1297             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1298             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1299             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1300             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1301             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1302             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1303                 return -EINVAL;
1304
1305         if (!check_gamma5_errata(attrs->gamma5))
1306                 return -EINVAL;
1307
1308         return 0;
1309 }
1310
1311 int intel_overlay_attrs(struct drm_device *dev, void *data,
1312                         struct drm_file *file_priv)
1313 {
1314         struct drm_intel_overlay_attrs *attrs = data;
1315         drm_i915_private_t *dev_priv = dev->dev_private;
1316         struct intel_overlay *overlay;
1317         struct overlay_registers *regs;
1318         int ret;
1319
1320         if (!dev_priv) {
1321                 DRM_ERROR("called with no initialization\n");
1322                 return -EINVAL;
1323         }
1324
1325         overlay = dev_priv->overlay;
1326         if (!overlay) {
1327                 DRM_DEBUG("userspace bug: no overlay\n");
1328                 return -ENODEV;
1329         }
1330
1331         mutex_lock(&dev->mode_config.mutex);
1332         mutex_lock(&dev->struct_mutex);
1333
1334         ret = -EINVAL;
1335         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1336                 attrs->color_key  = overlay->color_key;
1337                 attrs->brightness = overlay->brightness;
1338                 attrs->contrast   = overlay->contrast;
1339                 attrs->saturation = overlay->saturation;
1340
1341                 if (!IS_GEN2(dev)) {
1342                         attrs->gamma0 = I915_READ(OGAMC0);
1343                         attrs->gamma1 = I915_READ(OGAMC1);
1344                         attrs->gamma2 = I915_READ(OGAMC2);
1345                         attrs->gamma3 = I915_READ(OGAMC3);
1346                         attrs->gamma4 = I915_READ(OGAMC4);
1347                         attrs->gamma5 = I915_READ(OGAMC5);
1348                 }
1349         } else {
1350                 if (attrs->brightness < -128 || attrs->brightness > 127)
1351                         goto out_unlock;
1352                 if (attrs->contrast > 255)
1353                         goto out_unlock;
1354                 if (attrs->saturation > 1023)
1355                         goto out_unlock;
1356
1357                 overlay->color_key  = attrs->color_key;
1358                 overlay->brightness = attrs->brightness;
1359                 overlay->contrast   = attrs->contrast;
1360                 overlay->saturation = attrs->saturation;
1361
1362                 regs = intel_overlay_map_regs(overlay);
1363                 if (!regs) {
1364                         ret = -ENOMEM;
1365                         goto out_unlock;
1366                 }
1367
1368                 update_reg_attrs(overlay, regs);
1369
1370                 intel_overlay_unmap_regs(overlay, regs);
1371
1372                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1373                         if (IS_GEN2(dev))
1374                                 goto out_unlock;
1375
1376                         if (overlay->active) {
1377                                 ret = -EBUSY;
1378                                 goto out_unlock;
1379                         }
1380
1381                         ret = check_gamma(attrs);
1382                         if (ret)
1383                                 goto out_unlock;
1384
1385                         I915_WRITE(OGAMC0, attrs->gamma0);
1386                         I915_WRITE(OGAMC1, attrs->gamma1);
1387                         I915_WRITE(OGAMC2, attrs->gamma2);
1388                         I915_WRITE(OGAMC3, attrs->gamma3);
1389                         I915_WRITE(OGAMC4, attrs->gamma4);
1390                         I915_WRITE(OGAMC5, attrs->gamma5);
1391                 }
1392         }
1393
1394         ret = 0;
1395 out_unlock:
1396         mutex_unlock(&dev->struct_mutex);
1397         mutex_unlock(&dev->mode_config.mutex);
1398
1399         return ret;
1400 }
1401
1402 void intel_setup_overlay(struct drm_device *dev)
1403 {
1404         drm_i915_private_t *dev_priv = dev->dev_private;
1405         struct intel_overlay *overlay;
1406         struct drm_i915_gem_object *reg_bo;
1407         struct overlay_registers *regs;
1408         int ret;
1409
1410         if (!HAS_OVERLAY(dev))
1411                 return;
1412
1413         overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1414         if (!overlay)
1415                 return;
1416
1417         mutex_lock(&dev->struct_mutex);
1418         if (WARN_ON(dev_priv->overlay))
1419                 goto out_free;
1420
1421         overlay->dev = dev;
1422
1423         reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1424         if (!reg_bo)
1425                 goto out_free;
1426         overlay->reg_bo = reg_bo;
1427
1428         if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1429                 ret = i915_gem_attach_phys_object(dev, reg_bo,
1430                                                   I915_GEM_PHYS_OVERLAY_REGS,
1431                                                   PAGE_SIZE);
1432                 if (ret) {
1433                         DRM_ERROR("failed to attach phys overlay regs\n");
1434                         goto out_free_bo;
1435                 }
1436                 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1437         } else {
1438                 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
1439                 if (ret) {
1440                         DRM_ERROR("failed to pin overlay register bo\n");
1441                         goto out_free_bo;
1442                 }
1443                 overlay->flip_addr = reg_bo->gtt_offset;
1444
1445                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1446                 if (ret) {
1447                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1448                         goto out_unpin_bo;
1449                 }
1450         }
1451
1452         /* init all values */
1453         overlay->color_key = 0x0101fe;
1454         overlay->brightness = -19;
1455         overlay->contrast = 75;
1456         overlay->saturation = 146;
1457
1458         regs = intel_overlay_map_regs(overlay);
1459         if (!regs)
1460                 goto out_unpin_bo;
1461
1462         memset(regs, 0, sizeof(struct overlay_registers));
1463         update_polyphase_filter(regs);
1464         update_reg_attrs(overlay, regs);
1465
1466         intel_overlay_unmap_regs(overlay, regs);
1467
1468         dev_priv->overlay = overlay;
1469         mutex_unlock(&dev->struct_mutex);
1470         DRM_INFO("initialized overlay support\n");
1471         return;
1472
1473 out_unpin_bo:
1474         if (!OVERLAY_NEEDS_PHYSICAL(dev))
1475                 i915_gem_object_unpin(reg_bo);
1476 out_free_bo:
1477         drm_gem_object_unreference(&reg_bo->base);
1478 out_free:
1479         mutex_unlock(&dev->struct_mutex);
1480         kfree(overlay);
1481         return;
1482 }
1483
1484 void intel_cleanup_overlay(struct drm_device *dev)
1485 {
1486         drm_i915_private_t *dev_priv = dev->dev_private;
1487
1488         if (!dev_priv->overlay)
1489                 return;
1490
1491         /* The bo's should be free'd by the generic code already.
1492          * Furthermore modesetting teardown happens beforehand so the
1493          * hardware should be off already */
1494         BUG_ON(dev_priv->overlay->active);
1495
1496         drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1497         kfree(dev_priv->overlay);
1498 }
1499
1500 #ifdef CONFIG_DEBUG_FS
1501 #include <linux/seq_file.h>
1502
1503 struct intel_overlay_error_state {
1504         struct overlay_registers regs;
1505         unsigned long base;
1506         u32 dovsta;
1507         u32 isr;
1508 };
1509
1510 static struct overlay_registers *
1511 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1512 {
1513         drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1514         struct overlay_registers *regs;
1515
1516         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1517                 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1518         else
1519                 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1520                                                 overlay->reg_bo->gtt_offset);
1521
1522         return regs;
1523 }
1524
1525 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1526                                             struct overlay_registers *regs)
1527 {
1528         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1529                 io_mapping_unmap_atomic(regs);
1530 }
1531
1532
1533 struct intel_overlay_error_state *
1534 intel_overlay_capture_error_state(struct drm_device *dev)
1535 {
1536         drm_i915_private_t *dev_priv = dev->dev_private;
1537         struct intel_overlay *overlay = dev_priv->overlay;
1538         struct intel_overlay_error_state *error;
1539         struct overlay_registers __iomem *regs;
1540
1541         if (!overlay || !overlay->active)
1542                 return NULL;
1543
1544         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1545         if (error == NULL)
1546                 return NULL;
1547
1548         error->dovsta = I915_READ(DOVSTA);
1549         error->isr = I915_READ(ISR);
1550         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1551                 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1552         else
1553                 error->base = (long) overlay->reg_bo->gtt_offset;
1554
1555         regs = intel_overlay_map_regs_atomic(overlay);
1556         if (!regs)
1557                 goto err;
1558
1559         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1560         intel_overlay_unmap_regs_atomic(overlay, regs);
1561
1562         return error;
1563
1564 err:
1565         kfree(error);
1566         return NULL;
1567 }
1568
1569 void
1570 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1571 {
1572         seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1573                    error->dovsta, error->isr);
1574         seq_printf(m, "  Register file at 0x%08lx:\n",
1575                    error->base);
1576
1577 #define P(x) seq_printf(m, "    " #x ": 0x%08x\n", error->regs.x)
1578         P(OBUF_0Y);
1579         P(OBUF_1Y);
1580         P(OBUF_0U);
1581         P(OBUF_0V);
1582         P(OBUF_1U);
1583         P(OBUF_1V);
1584         P(OSTRIDE);
1585         P(YRGB_VPH);
1586         P(UV_VPH);
1587         P(HORZ_PH);
1588         P(INIT_PHS);
1589         P(DWINPOS);
1590         P(DWINSZ);
1591         P(SWIDTH);
1592         P(SWIDTHSW);
1593         P(SHEIGHT);
1594         P(YRGBSCALE);
1595         P(UVSCALE);
1596         P(OCLRC0);
1597         P(OCLRC1);
1598         P(DCLRKV);
1599         P(DCLRKM);
1600         P(SCLRKVH);
1601         P(SCLRKVL);
1602         P(SCLRKEN);
1603         P(OCONFIG);
1604         P(OCMD);
1605         P(OSTART_0Y);
1606         P(OSTART_1Y);
1607         P(OSTART_0U);
1608         P(OSTART_0V);
1609         P(OSTART_1U);
1610         P(OSTART_1V);
1611         P(OTILEOFF_0Y);
1612         P(OTILEOFF_1Y);
1613         P(OTILEOFF_0U);
1614         P(OTILEOFF_0V);
1615         P(OTILEOFF_1U);
1616         P(OTILEOFF_1V);
1617         P(FASTHSCALE);
1618         P(UVSCALEV);
1619 #undef P
1620 }
1621 #endif