drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38 };
  39
  40 static void band_gap_reset(struct drm_i915_private *dev_priv)
  41 {
  42         mutex_lock(&dev_priv->dpio_lock);
  43
  44         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  45         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  46         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  47         udelay(150);
  48         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  50
  51         mutex_unlock(&dev_priv->dpio_lock);
  52 }
  53
  54 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  55 {
  56         return container_of(intel_attached_encoder(connector),
  57                             struct intel_dsi, base);
  58 }
  59
  60 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  61 {
  62         return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
  63 }
  64
  65 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
  68 }
  69
  70 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  71 {
  72         DRM_DEBUG_KMS("\n");
  73 }
  74
  75 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  76                                      struct intel_crtc_config *config)
  77 {
  78         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  79                                                    base);
  80         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  81         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  82         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  83         struct drm_display_mode *mode = &config->requested_mode;
  84
  85         DRM_DEBUG_KMS("\n");
  86
  87         if (fixed_mode)
  88                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  89
  90         if (intel_dsi->dev.dev_ops->mode_fixup)
  91                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  92                                                           mode, adjusted_mode);
  93
  94         return true;
  95 }
  96
  97 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  98 {
  99         DRM_DEBUG_KMS("\n");
 100
 101         vlv_enable_dsi_pll(encoder);
 102 }
 103
 104 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 105 {
 106         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 107         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 108         int pipe = intel_crtc->pipe;
 109         u32 val;
 110
 111         DRM_DEBUG_KMS("\n");
 112
 113         mutex_lock(&dev_priv->dpio_lock);
 114         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 115          * needed everytime after power gate */
 116         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 117         mutex_unlock(&dev_priv->dpio_lock);
 118
 119         /* bandgap reset is needed after everytime we do power gate */
 120         band_gap_reset(dev_priv);
 121
 122         val = I915_READ(MIPI_PORT_CTRL(pipe));
 123         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 124         usleep_range(1000, 1500);
 125         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
 126         usleep_range(2000, 2500);
 127         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 128         usleep_range(2000, 2500);
 129         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 130         usleep_range(2000, 2500);
 131         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 132         usleep_range(2000, 2500);
 133 }
 134
 135 static void intel_dsi_enable(struct intel_encoder *encoder)
 136 {
 137         struct drm_device *dev = encoder->base.dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 140         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 141         int pipe = intel_crtc->pipe;
 142         u32 temp;
 143
 144         DRM_DEBUG_KMS("\n");
 145
 146         if (is_cmd_mode(intel_dsi))
 147                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 148         else {
 149                 msleep(20); /* XXX */
 150                 dpi_send_cmd(intel_dsi, TURN_ON);
 151                 msleep(100);
 152
 153                 if (intel_dsi->dev.dev_ops->enable)
 154                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 155
 156                 /* assert ip_tg_enable signal */
 157                 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 158                 temp = temp | intel_dsi->port_bits;
 159                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 160                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 161         }
 162 }
 163
 164 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 165 {
 166         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 167
 168         DRM_DEBUG_KMS("\n");
 169
 170         if (intel_dsi->dev.dev_ops->panel_reset)
 171                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 172
 173         /* put device in ready state */
 174         intel_dsi_device_ready(encoder);
 175
 176         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 177                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 178
 179         /* Enable port in pre-enable phase itself because as per hw team
 180          * recommendation, port should be enabled befor plane & pipe */
 181         intel_dsi_enable(encoder);
 182 }
 183
 184 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 185 {
 186         DRM_DEBUG_KMS("\n");
 187
 188         /* for DSI port enable has to be done before pipe
 189          * and plane enable, so port enable is done in
 190          * pre_enable phase itself unlike other encoders
 191          */
 192 }
 193
 194 static void intel_dsi_disable(struct intel_encoder *encoder)
 195 {
 196         struct drm_device *dev = encoder->base.dev;
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 199         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 200         int pipe = intel_crtc->pipe;
 201         u32 temp;
 202
 203         DRM_DEBUG_KMS("\n");
 204
 205         if (is_vid_mode(intel_dsi)) {
 206                 dpi_send_cmd(intel_dsi, SHUTDOWN);
 207                 msleep(10);
 208
 209                 /* de-assert ip_tg_enable signal */
 210                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 211                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 212                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 213
 214                 msleep(2);
 215         }
 216
 217         /* if disable packets are sent before sending shutdown packet then in
 218          * some next enable sequence send turn on packet error is observed */
 219         if (intel_dsi->dev.dev_ops->disable)
 220                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 221 }
 222
 223 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 224 {
 225         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 226         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 227         int pipe = intel_crtc->pipe;
 228         u32 val;
 229
 230         DRM_DEBUG_KMS("\n");
 231
 232         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 233         usleep_range(2000, 2500);
 234
 235         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
 236         usleep_range(2000, 2500);
 237
 238         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 239         usleep_range(2000, 2500);
 240
 241         val = I915_READ(MIPI_PORT_CTRL(pipe));
 242         I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
 243         usleep_range(1000, 1500);
 244
 245         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
 246                                         == 0x00000), 30))
 247                 DRM_ERROR("DSI LP not going Low\n");
 248
 249         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 250         usleep_range(2000, 2500);
 251
 252         vlv_disable_dsi_pll(encoder);
 253 }
 254 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 255 {
 256         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 257
 258         DRM_DEBUG_KMS("\n");
 259
 260         intel_dsi_clear_device_ready(encoder);
 261
 262         if (intel_dsi->dev.dev_ops->disable_panel_power)
 263                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 264 }
 265
 266 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 267                                    enum pipe *pipe)
 268 {
 269         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 270         enum intel_display_power_domain power_domain;
 271         u32 port, func;
 272         enum pipe p;
 273
 274         DRM_DEBUG_KMS("\n");
 275
 276         power_domain = intel_display_port_power_domain(encoder);
 277         if (!intel_display_power_enabled(dev_priv, power_domain))
 278                 return false;
 279
 280         /* XXX: this only works for one DSI output */
 281         for (p = PIPE_A; p <= PIPE_B; p++) {
 282                 port = I915_READ(MIPI_PORT_CTRL(p));
 283                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 284
 285                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 286                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 287                                 *pipe = p;
 288                                 return true;
 289                         }
 290                 }
 291         }
 292
 293         return false;
 294 }
 295
 296 static void intel_dsi_get_config(struct intel_encoder *encoder,
 297                                  struct intel_crtc_config *pipe_config)
 298 {
 299         DRM_DEBUG_KMS("\n");
 300
 301         /* XXX: read flags, set to adjusted_mode */
 302 }
 303
 304 static enum drm_mode_status
 305 intel_dsi_mode_valid(struct drm_connector *connector,
 306                      struct drm_display_mode *mode)
 307 {
 308         struct intel_connector *intel_connector = to_intel_connector(connector);
 309         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 310         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 311
 312         DRM_DEBUG_KMS("\n");
 313
 314         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 315                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 316                 return MODE_NO_DBLESCAN;
 317         }
 318
 319         if (fixed_mode) {
 320                 if (mode->hdisplay > fixed_mode->hdisplay)
 321                         return MODE_PANEL;
 322                 if (mode->vdisplay > fixed_mode->vdisplay)
 323                         return MODE_PANEL;
 324         }
 325
 326         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 327 }
 328
 329 /* return txclkesc cycles in terms of divider and duration in us */
 330 static u16 txclkesc(u32 divider, unsigned int us)
 331 {
 332         switch (divider) {
 333         case ESCAPE_CLOCK_DIVIDER_1:
 334         default:
 335                 return 20 * us;
 336         case ESCAPE_CLOCK_DIVIDER_2:
 337                 return 10 * us;
 338         case ESCAPE_CLOCK_DIVIDER_4:
 339                 return 5 * us;
 340         }
 341 }
 342
 343 /* return pixels in terms of txbyteclkhs */
 344 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 345 {
 346         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 347 }
 348
 349 static void set_dsi_timings(struct drm_encoder *encoder,
 350                             const struct drm_display_mode *mode)
 351 {
 352         struct drm_device *dev = encoder->dev;
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 355         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 356         int pipe = intel_crtc->pipe;
 357         unsigned int bpp = intel_crtc->config.pipe_bpp;
 358         unsigned int lane_count = intel_dsi->lane_count;
 359
 360         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 361
 362         hactive = mode->hdisplay;
 363         hfp = mode->hsync_start - mode->hdisplay;
 364         hsync = mode->hsync_end - mode->hsync_start;
 365         hbp = mode->htotal - mode->hsync_end;
 366
 367         vfp = mode->vsync_start - mode->vdisplay;
 368         vsync = mode->vsync_end - mode->vsync_start;
 369         vbp = mode->vtotal - mode->vsync_end;
 370
 371         /* horizontal values are in terms of high speed byte clock */
 372         hactive = txbyteclkhs(hactive, bpp, lane_count);
 373         hfp = txbyteclkhs(hfp, bpp, lane_count);
 374         hsync = txbyteclkhs(hsync, bpp, lane_count);
 375         hbp = txbyteclkhs(hbp, bpp, lane_count);
 376
 377         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 378         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 379
 380         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 381          * for non-burst sync events and burst modes */
 382         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 383         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 384
 385         /* vertical values are in terms of lines */
 386         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 387         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 388         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 389 }
 390
 391 static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 392 {
 393         struct drm_encoder *encoder = &intel_encoder->base;
 394         struct drm_device *dev = encoder->dev;
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 397         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 398         struct drm_display_mode *adjusted_mode =
 399                 &intel_crtc->config.adjusted_mode;
 400         int pipe = intel_crtc->pipe;
 401         unsigned int bpp = intel_crtc->config.pipe_bpp;
 402         u32 val, tmp;
 403
 404         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 405
 406         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 407          * off when doing this! txclkesc? */
 408         tmp = I915_READ(MIPI_CTRL(0));
 409         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 410         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 411
 412         /* read request priority is per pipe */
 413         tmp = I915_READ(MIPI_CTRL(pipe));
 414         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 415         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 416
 417         /* XXX: why here, why like this? handling in irq handler?! */
 418         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 419         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 420
 421         I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
 422
 423         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 424                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 425                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 426
 427         set_dsi_timings(encoder, adjusted_mode);
 428
 429         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 430         if (is_cmd_mode(intel_dsi)) {
 431                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 432                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 433         } else {
 434                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 435
 436                 /* XXX: cross-check bpp vs. pixel format? */
 437                 val |= intel_dsi->pixel_format;
 438         }
 439         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 440
 441         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 442          * stop state. */
 443
 444         /*
 445          * In burst mode, value greater than one DPI line Time in byte clock
 446          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 447          * recommended.
 448          *
 449          * In non-burst mode, Value greater than one DPI frame time in byte
 450          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 451          * is recommended.
 452          *
 453          * In DBI only mode, value greater than one DBI frame time in byte
 454          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 455          * is recommended.
 456          */
 457
 458         if (is_vid_mode(intel_dsi) &&
 459             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 460                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 461                            txbyteclkhs(adjusted_mode->htotal, bpp,
 462                                        intel_dsi->lane_count) + 1);
 463         } else {
 464                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 465                            txbyteclkhs(adjusted_mode->vtotal *
 466                                        adjusted_mode->htotal,
 467                                        bpp, intel_dsi->lane_count) + 1);
 468         }
 469         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
 470         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
 471         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
 472
 473         /* dphy stuff */
 474
 475         /* in terms of low power clock */
 476         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
 477
 478         /* recovery disables */
 479         I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
 480
 481         /* in terms of txbyteclkhs. actual high to low switch +
 482          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 483          *
 484          * XXX: write MIPI_STOP_STATE_STALL?
 485          */
 486         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
 487                                                 intel_dsi->hs_to_lp_count);
 488
 489         /* XXX: low power clock equivalence in terms of byte clock. the number
 490          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 491          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 492          * MIPI_STOP_STATE_STALL) / 105.???
 493          */
 494         I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
 495
 496         /* the bw essential for transmitting 16 long packets containing 252
 497          * bytes meant for dcs write memory command is programmed in this
 498          * register in terms of byte clocks. based on dsi transfer rate and the
 499          * number of lanes configured the time taken to transmit 16 long packets
 500          * in a dsi stream varies. */
 501         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
 502
 503         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 504                    intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 505                    intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 506
 507         if (is_vid_mode(intel_dsi))
 508                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 509                                 intel_dsi->video_frmt_cfg_bits |
 510                                 intel_dsi->video_mode_format);
 511 }
 512
 513 static enum drm_connector_status
 514 intel_dsi_detect(struct drm_connector *connector, bool force)
 515 {
 516         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 517         struct intel_encoder *intel_encoder = &intel_dsi->base;
 518         enum intel_display_power_domain power_domain;
 519         enum drm_connector_status connector_status;
 520         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 521
 522         DRM_DEBUG_KMS("\n");
 523         power_domain = intel_display_port_power_domain(intel_encoder);
 524
 525         intel_display_power_get(dev_priv, power_domain);
 526         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 527         intel_display_power_put(dev_priv, power_domain);
 528
 529         return connector_status;
 530 }
 531
 532 static int intel_dsi_get_modes(struct drm_connector *connector)
 533 {
 534         struct intel_connector *intel_connector = to_intel_connector(connector);
 535         struct drm_display_mode *mode;
 536
 537         DRM_DEBUG_KMS("\n");
 538
 539         if (!intel_connector->panel.fixed_mode) {
 540                 DRM_DEBUG_KMS("no fixed mode\n");
 541                 return 0;
 542         }
 543
 544         mode = drm_mode_duplicate(connector->dev,
 545                                   intel_connector->panel.fixed_mode);
 546         if (!mode) {
 547                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 548                 return 0;
 549         }
 550
 551         drm_mode_probed_add(connector, mode);
 552         return 1;
 553 }
 554
 555 static void intel_dsi_destroy(struct drm_connector *connector)
 556 {
 557         struct intel_connector *intel_connector = to_intel_connector(connector);
 558
 559         DRM_DEBUG_KMS("\n");
 560         intel_panel_fini(&intel_connector->panel);
 561         drm_connector_cleanup(connector);
 562         kfree(connector);
 563 }
 564
 565 static const struct drm_encoder_funcs intel_dsi_funcs = {
 566         .destroy = intel_encoder_destroy,
 567 };
 568
 569 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 570         .get_modes = intel_dsi_get_modes,
 571         .mode_valid = intel_dsi_mode_valid,
 572         .best_encoder = intel_best_encoder,
 573 };
 574
 575 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 576         .dpms = intel_connector_dpms,
 577         .detect = intel_dsi_detect,
 578         .destroy = intel_dsi_destroy,
 579         .fill_modes = drm_helper_probe_single_connector_modes,
 580 };
 581
 582 bool intel_dsi_init(struct drm_device *dev)
 583 {
 584         struct intel_dsi *intel_dsi;
 585         struct intel_encoder *intel_encoder;
 586         struct drm_encoder *encoder;
 587         struct intel_connector *intel_connector;
 588         struct drm_connector *connector;
 589         struct drm_display_mode *fixed_mode = NULL;
 590         const struct intel_dsi_device *dsi;
 591         unsigned int i;
 592
 593         DRM_DEBUG_KMS("\n");
 594
 595         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 596         if (!intel_dsi)
 597                 return false;
 598
 599         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 600         if (!intel_connector) {
 601                 kfree(intel_dsi);
 602                 return false;
 603         }
 604
 605         intel_encoder = &intel_dsi->base;
 606         encoder = &intel_encoder->base;
 607         intel_dsi->attached_connector = intel_connector;
 608
 609         connector = &intel_connector->base;
 610
 611         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 612
 613         /* XXX: very likely not all of these are needed */
 614         intel_encoder->hot_plug = intel_dsi_hot_plug;
 615         intel_encoder->compute_config = intel_dsi_compute_config;
 616         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 617         intel_encoder->pre_enable = intel_dsi_pre_enable;
 618         intel_encoder->enable = intel_dsi_enable_nop;
 619         intel_encoder->mode_set = intel_dsi_mode_set;
 620         intel_encoder->disable = intel_dsi_disable;
 621         intel_encoder->post_disable = intel_dsi_post_disable;
 622         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 623         intel_encoder->get_config = intel_dsi_get_config;
 624
 625         intel_connector->get_hw_state = intel_connector_get_hw_state;
 626         intel_connector->unregister = intel_connector_unregister;
 627
 628         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 629                 dsi = &intel_dsi_devices[i];
 630                 intel_dsi->dev = *dsi;
 631
 632                 if (dsi->dev_ops->init(&intel_dsi->dev))
 633                         break;
 634         }
 635
 636         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 637                 DRM_DEBUG_KMS("no device found\n");
 638                 goto err;
 639         }
 640
 641         intel_encoder->type = INTEL_OUTPUT_DSI;
 642         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 643
 644         intel_encoder->cloneable = 0;
 645         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 646                            DRM_MODE_CONNECTOR_DSI);
 647
 648         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 649
 650         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 651         connector->interlace_allowed = false;
 652         connector->doublescan_allowed = false;
 653
 654         intel_connector_attach_encoder(intel_connector, intel_encoder);
 655
 656         drm_sysfs_connector_add(connector);
 657
 658         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 659         if (!fixed_mode) {
 660                 DRM_DEBUG_KMS("no fixed mode\n");
 661                 goto err;
 662         }
 663
 664         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 665         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 666
 667         return true;
 668
 669 err:
 670         drm_encoder_cleanup(&intel_encoder->base);
 671         kfree(intel_dsi);
 672         kfree(intel_connector);
 673
 674         return false;
 675 }