drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38 };
  39
  40 static void band_gap_reset(struct drm_i915_private *dev_priv)
  41 {
  42         mutex_lock(&dev_priv->dpio_lock);
  43
  44         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  45         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  46         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  47         udelay(150);
  48         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  49         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  50
  51         mutex_unlock(&dev_priv->dpio_lock);
  52 }
  53
  54 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  55 {
  56         return container_of(intel_attached_encoder(connector),
  57                             struct intel_dsi, base);
  58 }
  59
  60 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  61 {
  62         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
  63 }
  64
  65 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  66 {
  67         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
  68 }
  69
  70 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  71 {
  72         DRM_DEBUG_KMS("\n");
  73 }
  74
  75 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  76                                      struct intel_crtc_config *config)
  77 {
  78         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  79                                                    base);
  80         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  81         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  82         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  83         struct drm_display_mode *mode = &config->requested_mode;
  84
  85         DRM_DEBUG_KMS("\n");
  86
  87         if (fixed_mode)
  88                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  89
  90         if (intel_dsi->dev.dev_ops->mode_fixup)
  91                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  92                                                           mode, adjusted_mode);
  93
  94         return true;
  95 }
  96
  97 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  98 {
  99         DRM_DEBUG_KMS("\n");
 100
 101         vlv_enable_dsi_pll(encoder);
 102 }
 103
 104 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 105 {
 106         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 107         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 108         int pipe = intel_crtc->pipe;
 109         u32 val;
 110
 111         DRM_DEBUG_KMS("\n");
 112
 113         mutex_lock(&dev_priv->dpio_lock);
 114         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 115          * needed everytime after power gate */
 116         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 117         mutex_unlock(&dev_priv->dpio_lock);
 118
 119         /* bandgap reset is needed after everytime we do power gate */
 120         band_gap_reset(dev_priv);
 121
 122         val = I915_READ(MIPI_PORT_CTRL(pipe));
 123         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
 124         usleep_range(1000, 1500);
 125         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
 126         usleep_range(2000, 2500);
 127         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 128         usleep_range(2000, 2500);
 129         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 130         usleep_range(2000, 2500);
 131         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
 132         usleep_range(2000, 2500);
 133 }
 134
 135 static void intel_dsi_enable(struct intel_encoder *encoder)
 136 {
 137         struct drm_device *dev = encoder->base.dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 140         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 141         int pipe = intel_crtc->pipe;
 142         u32 temp;
 143
 144         DRM_DEBUG_KMS("\n");
 145
 146         if (is_cmd_mode(intel_dsi))
 147                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 148         else {
 149                 msleep(20); /* XXX */
 150                 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
 151                 msleep(100);
 152
 153                 if (intel_dsi->dev.dev_ops->enable)
 154                         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 155
 156                 /* assert ip_tg_enable signal */
 157                 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
 158                 temp = temp | intel_dsi->port_bits;
 159                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 160                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 161         }
 162 }
 163
 164 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 165 {
 166         struct drm_device *dev = encoder->base.dev;
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 169         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 170         enum pipe pipe = intel_crtc->pipe;
 171         u32 tmp;
 172
 173         DRM_DEBUG_KMS("\n");
 174
 175         /* Disable DPOunit clock gating, can stall pipe
 176          * and we need DPLL REFA always enabled */
 177         tmp = I915_READ(DPLL(pipe));
 178         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 179         I915_WRITE(DPLL(pipe), tmp);
 180
 181         tmp = I915_READ(DSPCLK_GATE_D);
 182         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 183         I915_WRITE(DSPCLK_GATE_D, tmp);
 184
 185         /* put device in ready state */
 186         intel_dsi_device_ready(encoder);
 187
 188         msleep(intel_dsi->panel_on_delay);
 189
 190         if (intel_dsi->dev.dev_ops->panel_reset)
 191                 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
 192
 193         if (intel_dsi->dev.dev_ops->send_otp_cmds)
 194                 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
 195
 196         /* Enable port in pre-enable phase itself because as per hw team
 197          * recommendation, port should be enabled befor plane & pipe */
 198         intel_dsi_enable(encoder);
 199 }
 200
 201 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 202 {
 203         DRM_DEBUG_KMS("\n");
 204
 205         /* for DSI port enable has to be done before pipe
 206          * and plane enable, so port enable is done in
 207          * pre_enable phase itself unlike other encoders
 208          */
 209 }
 210
 211 static void intel_dsi_disable(struct intel_encoder *encoder)
 212 {
 213         struct drm_device *dev = encoder->base.dev;
 214         struct drm_i915_private *dev_priv = dev->dev_private;
 215         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 216         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 217         int pipe = intel_crtc->pipe;
 218         u32 temp;
 219
 220         DRM_DEBUG_KMS("\n");
 221
 222         if (is_vid_mode(intel_dsi)) {
 223                 /* Send Shutdown command to the panel in LP mode */
 224                 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
 225                 msleep(10);
 226
 227                 /* de-assert ip_tg_enable signal */
 228                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 229                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 230                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 231
 232                 msleep(2);
 233         }
 234
 235         /* Panel commands can be sent when clock is in LP11 */
 236         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
 237
 238         temp = I915_READ(MIPI_CTRL(pipe));
 239         temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 240         I915_WRITE(MIPI_CTRL(pipe), temp |
 241                         intel_dsi->escape_clk_div <<
 242                         ESCAPE_CLOCK_DIVIDER_SHIFT);
 243
 244         I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
 245
 246         temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
 247         temp &= ~VID_MODE_FORMAT_MASK;
 248         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
 249
 250         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
 251
 252         /* if disable packets are sent before sending shutdown packet then in
 253          * some next enable sequence send turn on packet error is observed */
 254         if (intel_dsi->dev.dev_ops->disable)
 255                 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 256 }
 257
 258 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 259 {
 260         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 261         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 262         int pipe = intel_crtc->pipe;
 263         u32 val;
 264
 265         DRM_DEBUG_KMS("\n");
 266
 267         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 268         usleep_range(2000, 2500);
 269
 270         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
 271         usleep_range(2000, 2500);
 272
 273         I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
 274         usleep_range(2000, 2500);
 275
 276         val = I915_READ(MIPI_PORT_CTRL(pipe));
 277         I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
 278         usleep_range(1000, 1500);
 279
 280         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
 281                                         == 0x00000), 30))
 282                 DRM_ERROR("DSI LP not going Low\n");
 283
 284         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
 285         usleep_range(2000, 2500);
 286
 287         vlv_disable_dsi_pll(encoder);
 288 }
 289
 290 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 291 {
 292         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 293         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 294         u32 val;
 295
 296         DRM_DEBUG_KMS("\n");
 297
 298         intel_dsi_clear_device_ready(encoder);
 299
 300         val = I915_READ(DSPCLK_GATE_D);
 301         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 302         I915_WRITE(DSPCLK_GATE_D, val);
 303
 304         if (intel_dsi->dev.dev_ops->disable_panel_power)
 305                 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
 306
 307         msleep(intel_dsi->panel_off_delay);
 308         msleep(intel_dsi->panel_pwr_cycle_delay);
 309 }
 310
 311 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 312                                    enum pipe *pipe)
 313 {
 314         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 315         enum intel_display_power_domain power_domain;
 316         u32 port, func;
 317         enum pipe p;
 318
 319         DRM_DEBUG_KMS("\n");
 320
 321         power_domain = intel_display_port_power_domain(encoder);
 322         if (!intel_display_power_enabled(dev_priv, power_domain))
 323                 return false;
 324
 325         /* XXX: this only works for one DSI output */
 326         for (p = PIPE_A; p <= PIPE_B; p++) {
 327                 port = I915_READ(MIPI_PORT_CTRL(p));
 328                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 329
 330                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 331                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 332                                 *pipe = p;
 333                                 return true;
 334                         }
 335                 }
 336         }
 337
 338         return false;
 339 }
 340
 341 static void intel_dsi_get_config(struct intel_encoder *encoder,
 342                                  struct intel_crtc_config *pipe_config)
 343 {
 344         DRM_DEBUG_KMS("\n");
 345
 346         /* XXX: read flags, set to adjusted_mode */
 347 }
 348
 349 static enum drm_mode_status
 350 intel_dsi_mode_valid(struct drm_connector *connector,
 351                      struct drm_display_mode *mode)
 352 {
 353         struct intel_connector *intel_connector = to_intel_connector(connector);
 354         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 355         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 356
 357         DRM_DEBUG_KMS("\n");
 358
 359         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 360                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 361                 return MODE_NO_DBLESCAN;
 362         }
 363
 364         if (fixed_mode) {
 365                 if (mode->hdisplay > fixed_mode->hdisplay)
 366                         return MODE_PANEL;
 367                 if (mode->vdisplay > fixed_mode->vdisplay)
 368                         return MODE_PANEL;
 369         }
 370
 371         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 372 }
 373
 374 /* return txclkesc cycles in terms of divider and duration in us */
 375 static u16 txclkesc(u32 divider, unsigned int us)
 376 {
 377         switch (divider) {
 378         case ESCAPE_CLOCK_DIVIDER_1:
 379         default:
 380                 return 20 * us;
 381         case ESCAPE_CLOCK_DIVIDER_2:
 382                 return 10 * us;
 383         case ESCAPE_CLOCK_DIVIDER_4:
 384                 return 5 * us;
 385         }
 386 }
 387
 388 /* return pixels in terms of txbyteclkhs */
 389 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 390 {
 391         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 392 }
 393
 394 static void set_dsi_timings(struct drm_encoder *encoder,
 395                             const struct drm_display_mode *mode)
 396 {
 397         struct drm_device *dev = encoder->dev;
 398         struct drm_i915_private *dev_priv = dev->dev_private;
 399         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 400         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 401         int pipe = intel_crtc->pipe;
 402         unsigned int bpp = intel_crtc->config.pipe_bpp;
 403         unsigned int lane_count = intel_dsi->lane_count;
 404
 405         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 406
 407         hactive = mode->hdisplay;
 408         hfp = mode->hsync_start - mode->hdisplay;
 409         hsync = mode->hsync_end - mode->hsync_start;
 410         hbp = mode->htotal - mode->hsync_end;
 411
 412         vfp = mode->vsync_start - mode->vdisplay;
 413         vsync = mode->vsync_end - mode->vsync_start;
 414         vbp = mode->vtotal - mode->vsync_end;
 415
 416         /* horizontal values are in terms of high speed byte clock */
 417         hactive = txbyteclkhs(hactive, bpp, lane_count);
 418         hfp = txbyteclkhs(hfp, bpp, lane_count);
 419         hsync = txbyteclkhs(hsync, bpp, lane_count);
 420         hbp = txbyteclkhs(hbp, bpp, lane_count);
 421
 422         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 423         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 424
 425         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 426          * for non-burst sync events and burst modes */
 427         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 428         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 429
 430         /* vertical values are in terms of lines */
 431         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 432         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 433         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 434 }
 435
 436 static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 437 {
 438         struct drm_encoder *encoder = &intel_encoder->base;
 439         struct drm_device *dev = encoder->dev;
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 442         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 443         struct drm_display_mode *adjusted_mode =
 444                 &intel_crtc->config.adjusted_mode;
 445         int pipe = intel_crtc->pipe;
 446         unsigned int bpp = intel_crtc->config.pipe_bpp;
 447         u32 val, tmp;
 448
 449         DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
 450
 451         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 452          * off when doing this! txclkesc? */
 453         tmp = I915_READ(MIPI_CTRL(0));
 454         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 455         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 456
 457         /* read request priority is per pipe */
 458         tmp = I915_READ(MIPI_CTRL(pipe));
 459         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 460         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 461
 462         /* XXX: why here, why like this? handling in irq handler?! */
 463         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 464         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 465
 466         I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
 467
 468         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 469                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 470                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 471
 472         set_dsi_timings(encoder, adjusted_mode);
 473
 474         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 475         if (is_cmd_mode(intel_dsi)) {
 476                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 477                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 478         } else {
 479                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 480
 481                 /* XXX: cross-check bpp vs. pixel format? */
 482                 val |= intel_dsi->pixel_format;
 483         }
 484         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 485
 486         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 487          * stop state. */
 488
 489         /*
 490          * In burst mode, value greater than one DPI line Time in byte clock
 491          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 492          * recommended.
 493          *
 494          * In non-burst mode, Value greater than one DPI frame time in byte
 495          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 496          * is recommended.
 497          *
 498          * In DBI only mode, value greater than one DBI frame time in byte
 499          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 500          * is recommended.
 501          */
 502
 503         if (is_vid_mode(intel_dsi) &&
 504             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 505                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 506                            txbyteclkhs(adjusted_mode->htotal, bpp,
 507                                        intel_dsi->lane_count) + 1);
 508         } else {
 509                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 510                            txbyteclkhs(adjusted_mode->vtotal *
 511                                        adjusted_mode->htotal,
 512                                        bpp, intel_dsi->lane_count) + 1);
 513         }
 514         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
 515         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
 516         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
 517
 518         /* dphy stuff */
 519
 520         /* in terms of low power clock */
 521         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
 522
 523         val = 0;
 524         if (intel_dsi->eotp_pkt == 0)
 525                 val |= EOT_DISABLE;
 526
 527         if (intel_dsi->clock_stop)
 528                 val |= CLOCKSTOP;
 529
 530         /* recovery disables */
 531         I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 532
 533         /* in terms of low power clock */
 534         I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
 535
 536         /* in terms of txbyteclkhs. actual high to low switch +
 537          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 538          *
 539          * XXX: write MIPI_STOP_STATE_STALL?
 540          */
 541         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
 542                                                 intel_dsi->hs_to_lp_count);
 543
 544         /* XXX: low power clock equivalence in terms of byte clock. the number
 545          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 546          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 547          * MIPI_STOP_STATE_STALL) / 105.???
 548          */
 549         I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
 550
 551         /* the bw essential for transmitting 16 long packets containing 252
 552          * bytes meant for dcs write memory command is programmed in this
 553          * register in terms of byte clocks. based on dsi transfer rate and the
 554          * number of lanes configured the time taken to transmit 16 long packets
 555          * in a dsi stream varies. */
 556         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
 557
 558         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 559                    intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 560                    intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 561
 562         if (is_vid_mode(intel_dsi))
 563                 /* Some panels might have resolution which is not a multiple of
 564                  * 64 like 1366 x 768. Enable RANDOM resolution support for such
 565                  * panels by default */
 566                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 567                                 intel_dsi->video_frmt_cfg_bits |
 568                                 intel_dsi->video_mode_format |
 569                                 IP_TG_CONFIG |
 570                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 571 }
 572
 573 static enum drm_connector_status
 574 intel_dsi_detect(struct drm_connector *connector, bool force)
 575 {
 576         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 577         struct intel_encoder *intel_encoder = &intel_dsi->base;
 578         enum intel_display_power_domain power_domain;
 579         enum drm_connector_status connector_status;
 580         struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
 581
 582         DRM_DEBUG_KMS("\n");
 583         power_domain = intel_display_port_power_domain(intel_encoder);
 584
 585         intel_display_power_get(dev_priv, power_domain);
 586         connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 587         intel_display_power_put(dev_priv, power_domain);
 588
 589         return connector_status;
 590 }
 591
 592 static int intel_dsi_get_modes(struct drm_connector *connector)
 593 {
 594         struct intel_connector *intel_connector = to_intel_connector(connector);
 595         struct drm_display_mode *mode;
 596
 597         DRM_DEBUG_KMS("\n");
 598
 599         if (!intel_connector->panel.fixed_mode) {
 600                 DRM_DEBUG_KMS("no fixed mode\n");
 601                 return 0;
 602         }
 603
 604         mode = drm_mode_duplicate(connector->dev,
 605                                   intel_connector->panel.fixed_mode);
 606         if (!mode) {
 607                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 608                 return 0;
 609         }
 610
 611         drm_mode_probed_add(connector, mode);
 612         return 1;
 613 }
 614
 615 static void intel_dsi_destroy(struct drm_connector *connector)
 616 {
 617         struct intel_connector *intel_connector = to_intel_connector(connector);
 618
 619         DRM_DEBUG_KMS("\n");
 620         intel_panel_fini(&intel_connector->panel);
 621         drm_connector_cleanup(connector);
 622         kfree(connector);
 623 }
 624
 625 static const struct drm_encoder_funcs intel_dsi_funcs = {
 626         .destroy = intel_encoder_destroy,
 627 };
 628
 629 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 630         .get_modes = intel_dsi_get_modes,
 631         .mode_valid = intel_dsi_mode_valid,
 632         .best_encoder = intel_best_encoder,
 633 };
 634
 635 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 636         .dpms = intel_connector_dpms,
 637         .detect = intel_dsi_detect,
 638         .destroy = intel_dsi_destroy,
 639         .fill_modes = drm_helper_probe_single_connector_modes,
 640 };
 641
 642 bool intel_dsi_init(struct drm_device *dev)
 643 {
 644         struct intel_dsi *intel_dsi;
 645         struct intel_encoder *intel_encoder;
 646         struct drm_encoder *encoder;
 647         struct intel_connector *intel_connector;
 648         struct drm_connector *connector;
 649         struct drm_display_mode *fixed_mode = NULL;
 650         const struct intel_dsi_device *dsi;
 651         unsigned int i;
 652
 653         DRM_DEBUG_KMS("\n");
 654
 655         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 656         if (!intel_dsi)
 657                 return false;
 658
 659         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 660         if (!intel_connector) {
 661                 kfree(intel_dsi);
 662                 return false;
 663         }
 664
 665         intel_encoder = &intel_dsi->base;
 666         encoder = &intel_encoder->base;
 667         intel_dsi->attached_connector = intel_connector;
 668
 669         connector = &intel_connector->base;
 670
 671         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 672
 673         /* XXX: very likely not all of these are needed */
 674         intel_encoder->hot_plug = intel_dsi_hot_plug;
 675         intel_encoder->compute_config = intel_dsi_compute_config;
 676         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 677         intel_encoder->pre_enable = intel_dsi_pre_enable;
 678         intel_encoder->enable = intel_dsi_enable_nop;
 679         intel_encoder->mode_set = intel_dsi_mode_set;
 680         intel_encoder->disable = intel_dsi_disable;
 681         intel_encoder->post_disable = intel_dsi_post_disable;
 682         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 683         intel_encoder->get_config = intel_dsi_get_config;
 684
 685         intel_connector->get_hw_state = intel_connector_get_hw_state;
 686         intel_connector->unregister = intel_connector_unregister;
 687
 688         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 689                 dsi = &intel_dsi_devices[i];
 690                 intel_dsi->dev = *dsi;
 691
 692                 if (dsi->dev_ops->init(&intel_dsi->dev))
 693                         break;
 694         }
 695
 696         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 697                 DRM_DEBUG_KMS("no device found\n");
 698                 goto err;
 699         }
 700
 701         intel_encoder->type = INTEL_OUTPUT_DSI;
 702         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 703
 704         intel_encoder->cloneable = 0;
 705         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 706                            DRM_MODE_CONNECTOR_DSI);
 707
 708         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 709
 710         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 711         connector->interlace_allowed = false;
 712         connector->doublescan_allowed = false;
 713
 714         intel_connector_attach_encoder(intel_connector, intel_encoder);
 715
 716         drm_sysfs_connector_add(connector);
 717
 718         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 719         if (!fixed_mode) {
 720                 DRM_DEBUG_KMS("no fixed mode\n");
 721                 goto err;
 722         }
 723
 724         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 725         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 726
 727         return true;
 728
 729 err:
 730         drm_encoder_cleanup(&intel_encoder->base);
 731         kfree(intel_dsi);
 732         kfree(intel_connector);
 733
 734         return false;
 735 }