2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
39 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
40 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
43 * _wait_for - magic (register) wait macro
45 * Does the right thing for modeset paths when run under kdgb or similar atomic
46 * contexts. Note that it's important that we check the condition again after
47 * having timed out, since the timeout could be due to preemption or similar and
48 * we've never had a chance to check the condition before the timeout.
50 #define _wait_for(COND, MS, W) ({ \
51 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
54 if (time_after(jiffies, timeout__)) { \
59 if (W && drm_can_sleep()) { \
68 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
69 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
71 DIV_ROUND_UP((US), 1000), 0)
73 #define KHz(x) (1000 * (x))
74 #define MHz(x) KHz(1000 * (x))
77 * Display related stuff
80 /* store information about an Ixxx DVO */
81 /* The i830->i865 use multiple DVOs with multiple i2cs */
82 /* the i915, i945 have a single sDVO i2c bus - which is different */
84 /* maximum connectors per crtcs in the mode set */
86 /* Maximum cursor sizes */
87 #define GEN2_CURSOR_WIDTH 64
88 #define GEN2_CURSOR_HEIGHT 64
89 #define MAX_CURSOR_WIDTH 256
90 #define MAX_CURSOR_HEIGHT 256
92 #define INTEL_I2C_BUS_DVO 1
93 #define INTEL_I2C_BUS_SDVO 2
95 /* these are outputs from the chip - integrated only
96 external chips are via DVO or SDVO output */
97 enum intel_output_type {
98 INTEL_OUTPUT_UNUSED = 0,
99 INTEL_OUTPUT_ANALOG = 1,
100 INTEL_OUTPUT_DVO = 2,
101 INTEL_OUTPUT_SDVO = 3,
102 INTEL_OUTPUT_LVDS = 4,
103 INTEL_OUTPUT_TVOUT = 5,
104 INTEL_OUTPUT_HDMI = 6,
105 INTEL_OUTPUT_DISPLAYPORT = 7,
106 INTEL_OUTPUT_EDP = 8,
107 INTEL_OUTPUT_DSI = 9,
108 INTEL_OUTPUT_UNKNOWN = 10,
109 INTEL_OUTPUT_DP_MST = 11,
112 #define INTEL_DVO_CHIP_NONE 0
113 #define INTEL_DVO_CHIP_LVDS 1
114 #define INTEL_DVO_CHIP_TMDS 2
115 #define INTEL_DVO_CHIP_TVOUT 4
117 #define INTEL_DSI_VIDEO_MODE 0
118 #define INTEL_DSI_COMMAND_MODE 1
120 struct intel_framebuffer {
121 struct drm_framebuffer base;
122 struct drm_i915_gem_object *obj;
126 struct drm_fb_helper helper;
127 struct intel_framebuffer *fb;
128 struct list_head fbdev_list;
129 struct drm_display_mode *our_mode;
133 struct intel_encoder {
134 struct drm_encoder base;
136 * The new crtc this encoder will be driven from. Only differs from
137 * base->crtc while a modeset is in progress.
139 struct intel_crtc *new_crtc;
141 enum intel_output_type type;
142 unsigned int cloneable;
143 bool connectors_active;
144 void (*hot_plug)(struct intel_encoder *);
145 bool (*compute_config)(struct intel_encoder *,
146 struct intel_crtc_config *);
147 void (*pre_pll_enable)(struct intel_encoder *);
148 void (*pre_enable)(struct intel_encoder *);
149 void (*enable)(struct intel_encoder *);
150 void (*mode_set)(struct intel_encoder *intel_encoder);
151 void (*disable)(struct intel_encoder *);
152 void (*post_disable)(struct intel_encoder *);
153 /* Read out the current hw state of this connector, returning true if
154 * the encoder is active. If the encoder is enabled it also set the pipe
155 * it is connected to in the pipe parameter. */
156 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
157 /* Reconstructs the equivalent mode flags for the current hardware
158 * state. This must be called _after_ display->get_pipe_config has
159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
160 * be set correctly before calling this function. */
161 void (*get_config)(struct intel_encoder *,
162 struct intel_crtc_config *pipe_config);
164 * Called during system suspend after all pending requests for the
165 * encoder are flushed (for example for DP AUX transactions) and
166 * device interrupts are disabled.
168 void (*suspend)(struct intel_encoder *);
170 enum hpd_pin hpd_pin;
174 struct drm_display_mode *fixed_mode;
175 struct drm_display_mode *downclock_mode;
185 bool combination_mode; /* gen 2/4 only */
187 struct backlight_device *device;
190 void (*backlight_power)(struct intel_connector *, bool enable);
193 struct intel_connector {
194 struct drm_connector base;
196 * The fixed encoder this connector is connected to.
198 struct intel_encoder *encoder;
201 * The new encoder this connector will be driven. Only differs from
202 * encoder while a modeset is in progress.
204 struct intel_encoder *new_encoder;
206 /* Reads out the current hw, returning true if the connector is enabled
207 * and active (i.e. dpms ON state). */
208 bool (*get_hw_state)(struct intel_connector *);
211 * Removes all interfaces through which the connector is accessible
212 * - like sysfs, debugfs entries -, so that no new operations can be
213 * started on the connector. Also makes sure all currently pending
214 * operations finish before returing.
216 void (*unregister)(struct intel_connector *);
218 /* Panel info for eDP and LVDS */
219 struct intel_panel panel;
221 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
223 struct edid *detect_edid;
225 /* since POLL and HPD connectors may use the same HPD line keep the native
226 state of connector->polled in case hotplug storm detection changes it */
229 void *port; /* store this opaque as its illegal to dereference it */
231 struct intel_dp *mst_port;
234 typedef struct dpll {
246 struct intel_plane_state {
247 struct drm_crtc *crtc;
248 struct drm_framebuffer *fb;
251 struct drm_rect clip;
252 struct drm_rect orig_src;
253 struct drm_rect orig_dst;
257 struct intel_plane_config {
263 struct intel_crtc_config {
265 * quirks - bitfield with hw state readout quirks
267 * For various reasons the hw state readout code might not be able to
268 * completely faithfully read out the current state. These cases are
269 * tracked with quirk flags so that fastboot and state checker can act
272 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
273 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
274 unsigned long quirks;
276 /* User requested mode, only valid as a starting point to
277 * compute adjusted_mode, except in the case of (S)DVO where
278 * it's also for the output timings of the (S)DVO chip.
279 * adjusted_mode will then correspond to the S(DVO) chip's
280 * preferred input timings. */
281 struct drm_display_mode requested_mode;
282 /* Actual pipe timings ie. what we program into the pipe timing
283 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
284 struct drm_display_mode adjusted_mode;
286 /* Pipe source size (ie. panel fitter input size)
287 * All planes will be positioned inside this space,
288 * and get clipped at the edges. */
289 int pipe_src_w, pipe_src_h;
291 /* Whether to set up the PCH/FDI. Note that we never allow sharing
292 * between pch encoders and cpu encoders. */
293 bool has_pch_encoder;
295 /* Are we sending infoframes on the attached port */
298 /* CPU Transcoder for the pipe. Currently this can only differ from the
299 * pipe on Haswell (where we have a special eDP transcoder). */
300 enum transcoder cpu_transcoder;
303 * Use reduced/limited/broadcast rbg range, compressing from the full
304 * range fed into the crtcs.
306 bool limited_color_range;
308 /* DP has a bunch of special case unfortunately, so mark the pipe
312 /* Whether we should send NULL infoframes. Required for audio. */
315 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
316 * has_dp_encoder is set. */
320 * Enable dithering, used when the selected pipe bpp doesn't match the
325 /* Controls for the clock computation, to override various stages. */
328 /* SDVO TV has a bunch of special case. To make multifunction encoders
329 * work correctly, we need to track this at runtime.*/
333 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
334 * required. This is set in the 2nd loop of calling encoder's
335 * ->compute_config if the first pick doesn't work out.
339 /* Settings for the intel dpll used on pretty much everything but
343 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
344 enum intel_dpll_id shared_dpll;
347 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
348 * - enum skl_dpll on SKL
350 uint32_t ddi_pll_sel;
352 /* Actual register state of the dpll, for shared dpll cross-checking. */
353 struct intel_dpll_hw_state dpll_hw_state;
356 struct intel_link_m_n dp_m_n;
358 /* m2_n2 for eDP downclock */
359 struct intel_link_m_n dp_m2_n2;
363 * Frequence the dpll for the port should run at. Differs from the
364 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
365 * already multiplied by pixel_multiplier.
369 /* Used by SDVO (and if we ever fix it, HDMI). */
370 unsigned pixel_multiplier;
372 /* Panel fitter controls for gen2-gen4 + VLV */
376 u32 lvds_border_bits;
379 /* Panel fitter placement and size for Ironlake+ */
387 /* FDI configuration, only valid if has_pch_encoder is set. */
389 struct intel_link_m_n fdi_m_n;
395 bool dp_encoder_is_mst;
399 struct intel_pipe_wm {
400 struct intel_wm_level wm[5];
404 bool sprites_enabled;
408 struct intel_mmio_flip {
409 struct drm_i915_gem_request *req;
410 struct work_struct work;
414 struct skl_wm_level wm[8];
415 struct skl_wm_level trans_wm;
420 struct drm_crtc base;
423 u8 lut_r[256], lut_g[256], lut_b[256];
425 * Whether the crtc and the connected output pipeline is active. Implies
426 * that crtc->enabled is set, i.e. the current mode configuration has
427 * some outputs connected to this crtc.
430 unsigned long enabled_power_domains;
431 bool primary_enabled; /* is the primary plane (partially) visible? */
433 struct intel_overlay *overlay;
434 struct intel_unpin_work *unpin_work;
436 atomic_t unpin_work_count;
438 /* Display surface base address adjustement for pageflips. Note that on
439 * gen4+ this only adjusts up to a tile, offsets within a tile are
440 * handled in the hw itself (with the TILEOFF register). */
441 unsigned long dspaddr_offset;
443 struct drm_i915_gem_object *cursor_bo;
444 uint32_t cursor_addr;
445 int16_t cursor_width, cursor_height;
446 uint32_t cursor_cntl;
447 uint32_t cursor_size;
448 uint32_t cursor_base;
450 struct intel_plane_config plane_config;
451 struct intel_crtc_config config;
452 struct intel_crtc_config *new_config;
455 /* reset counter value when the last flip was submitted */
456 unsigned int reset_counter;
458 /* Access to these should be protected by dev_priv->irq_lock. */
459 bool cpu_fifo_underrun_disabled;
460 bool pch_fifo_underrun_disabled;
462 /* per-pipe watermark state */
464 /* watermarks currently being used */
465 struct intel_pipe_wm active;
466 /* SKL wm values currently in use */
467 struct skl_pipe_wm skl_active;
471 struct intel_mmio_flip mmio_flip;
474 struct intel_plane_wm_parameters {
475 uint32_t horiz_pixels;
476 uint32_t vert_pixels;
477 uint8_t bytes_per_pixel;
483 struct drm_plane base;
486 struct drm_i915_gem_object *obj;
490 unsigned int crtc_w, crtc_h;
491 uint32_t src_x, src_y;
492 uint32_t src_w, src_h;
493 unsigned int rotation;
495 /* Since we need to change the watermarks before/after
496 * enabling/disabling the planes, we need to store the parameters here
497 * as the other pieces of the struct may not reflect the values we want
498 * for the watermark calculations. Currently only Haswell uses this.
500 struct intel_plane_wm_parameters wm;
502 void (*update_plane)(struct drm_plane *plane,
503 struct drm_crtc *crtc,
504 struct drm_framebuffer *fb,
505 struct drm_i915_gem_object *obj,
506 int crtc_x, int crtc_y,
507 unsigned int crtc_w, unsigned int crtc_h,
508 uint32_t x, uint32_t y,
509 uint32_t src_w, uint32_t src_h);
510 void (*disable_plane)(struct drm_plane *plane,
511 struct drm_crtc *crtc);
512 int (*update_colorkey)(struct drm_plane *plane,
513 struct drm_intel_sprite_colorkey *key);
514 void (*get_colorkey)(struct drm_plane *plane,
515 struct drm_intel_sprite_colorkey *key);
518 struct intel_watermark_params {
519 unsigned long fifo_size;
520 unsigned long max_wm;
521 unsigned long default_wm;
522 unsigned long guard_size;
523 unsigned long cacheline_size;
526 struct cxsr_latency {
529 unsigned long fsb_freq;
530 unsigned long mem_freq;
531 unsigned long display_sr;
532 unsigned long display_hpll_disable;
533 unsigned long cursor_sr;
534 unsigned long cursor_hpll_disable;
537 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
538 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
539 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
540 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
541 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
542 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
547 uint32_t color_range;
548 bool color_range_auto;
551 enum hdmi_force_audio force_audio;
552 bool rgb_quant_range_selectable;
553 enum hdmi_picture_aspect aspect_ratio;
554 void (*write_infoframe)(struct drm_encoder *encoder,
555 enum hdmi_infoframe_type type,
556 const void *frame, ssize_t len);
557 void (*set_infoframes)(struct drm_encoder *encoder,
559 struct drm_display_mode *adjusted_mode);
560 bool (*infoframe_enabled)(struct drm_encoder *encoder);
563 struct intel_dp_mst_encoder;
564 #define DP_MAX_DOWNSTREAM_PORTS 0x10
567 * HIGH_RR is the highest eDP panel refresh rate read from EDID
568 * LOW_RR is the lowest eDP panel refresh rate found from EDID
569 * parsing for same resolution.
571 enum edp_drrs_refresh_rate_type {
574 DRRS_MAX_RR, /* RR count */
579 uint32_t aux_ch_ctl_reg;
582 enum hdmi_force_audio force_audio;
583 uint32_t color_range;
584 bool color_range_auto;
587 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
588 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
589 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
590 struct drm_dp_aux aux;
591 uint8_t train_set[4];
592 int panel_power_up_delay;
593 int panel_power_down_delay;
594 int panel_power_cycle_delay;
595 int backlight_on_delay;
596 int backlight_off_delay;
597 struct delayed_work panel_vdd_work;
599 unsigned long last_power_cycle;
600 unsigned long last_power_on;
601 unsigned long last_backlight_off;
603 struct notifier_block edp_notifier;
606 * Pipe whose power sequencer is currently locked into
607 * this port. Only relevant on VLV/CHV.
610 struct edp_power_seq pps_delays;
613 bool can_mst; /* this port supports mst */
615 int active_mst_links;
616 /* connector directly attached - won't be use for modeset in mst world */
617 struct intel_connector *attached_connector;
619 /* mst connector list */
620 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
621 struct drm_dp_mst_topology_mgr mst_mgr;
623 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
625 * This function returns the value we have to program the AUX_CTL
626 * register with to kick off an AUX transaction.
628 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
631 uint32_t aux_clock_divider);
633 enum drrs_support_type type;
634 enum edp_drrs_refresh_rate_type refresh_rate_type;
640 struct intel_digital_port {
641 struct intel_encoder base;
645 struct intel_hdmi hdmi;
646 bool (*hpd_pulse)(struct intel_digital_port *, bool);
649 struct intel_dp_mst_encoder {
650 struct intel_encoder base;
652 struct intel_digital_port *primary;
653 void *port; /* store this opaque as its illegal to dereference it */
657 vlv_dport_to_channel(struct intel_digital_port *dport)
659 switch (dport->port) {
671 vlv_pipe_to_channel(enum pipe pipe)
684 static inline struct drm_crtc *
685 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
687 struct drm_i915_private *dev_priv = dev->dev_private;
688 return dev_priv->pipe_to_crtc_mapping[pipe];
691 static inline struct drm_crtc *
692 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
694 struct drm_i915_private *dev_priv = dev->dev_private;
695 return dev_priv->plane_to_crtc_mapping[plane];
698 struct intel_unpin_work {
699 struct work_struct work;
700 struct drm_crtc *crtc;
701 struct drm_i915_gem_object *old_fb_obj;
702 struct drm_i915_gem_object *pending_flip_obj;
703 struct drm_pending_vblank_event *event;
705 #define INTEL_FLIP_INACTIVE 0
706 #define INTEL_FLIP_PENDING 1
707 #define INTEL_FLIP_COMPLETE 2
710 struct drm_i915_gem_request *flip_queued_req;
711 int flip_queued_vblank;
712 int flip_ready_vblank;
713 bool enable_stall_check;
716 struct intel_set_config {
717 struct drm_encoder **save_connector_encoders;
718 struct drm_crtc **save_encoder_crtcs;
719 bool *save_crtc_enabled;
725 struct intel_load_detect_pipe {
726 struct drm_framebuffer *release_fb;
727 bool load_detect_temp;
731 static inline struct intel_encoder *
732 intel_attached_encoder(struct drm_connector *connector)
734 return to_intel_connector(connector)->encoder;
737 static inline struct intel_digital_port *
738 enc_to_dig_port(struct drm_encoder *encoder)
740 return container_of(encoder, struct intel_digital_port, base.base);
743 static inline struct intel_dp_mst_encoder *
744 enc_to_mst(struct drm_encoder *encoder)
746 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
749 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
751 return &enc_to_dig_port(encoder)->dp;
754 static inline struct intel_digital_port *
755 dp_to_dig_port(struct intel_dp *intel_dp)
757 return container_of(intel_dp, struct intel_digital_port, dp);
760 static inline struct intel_digital_port *
761 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
763 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
767 * Returns the number of planes for this pipe, ie the number of sprites + 1
768 * (primary plane). This doesn't count the cursor plane then.
770 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
772 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
775 /* intel_fifo_underrun.c */
776 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
777 enum pipe pipe, bool enable);
778 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
779 enum transcoder pch_transcoder,
781 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
783 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
784 enum transcoder pch_transcoder);
785 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
788 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
789 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
790 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
791 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
792 void gen6_reset_rps_interrupts(struct drm_device *dev);
793 void gen6_enable_rps_interrupts(struct drm_device *dev);
794 void gen6_disable_rps_interrupts(struct drm_device *dev);
795 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
796 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
797 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
800 * We only use drm_irq_uninstall() at unload and VT switch, so
801 * this is the only thing we need to check.
803 return dev_priv->pm.irqs_enabled;
806 int intel_get_crtc_scanline(struct intel_crtc *crtc);
807 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
810 void intel_crt_init(struct drm_device *dev);
814 void intel_prepare_ddi(struct drm_device *dev);
815 void hsw_fdi_link_train(struct drm_crtc *crtc);
816 void intel_ddi_init(struct drm_device *dev, enum port port);
817 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
818 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
819 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
820 void intel_ddi_pll_init(struct drm_device *dev);
821 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
822 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
823 enum transcoder cpu_transcoder);
824 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
825 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
826 bool intel_ddi_pll_select(struct intel_crtc *crtc);
827 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
828 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
829 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
830 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
831 void intel_ddi_get_config(struct intel_encoder *encoder,
832 struct intel_crtc_config *pipe_config);
834 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
835 void intel_ddi_clock_get(struct intel_encoder *encoder,
836 struct intel_crtc_config *pipe_config);
837 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
839 /* intel_frontbuffer.c */
840 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
841 struct intel_engine_cs *ring);
842 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
843 unsigned frontbuffer_bits);
844 void intel_frontbuffer_flip_complete(struct drm_device *dev,
845 unsigned frontbuffer_bits);
846 void intel_frontbuffer_flush(struct drm_device *dev,
847 unsigned frontbuffer_bits);
849 * intel_frontbuffer_flip - synchronous frontbuffer flip
851 * @frontbuffer_bits: frontbuffer plane tracking bits
853 * This function gets called after scheduling a flip on @obj. This is for
854 * synchronous plane updates which will happen on the next vblank and which will
855 * not get delayed by pending gpu rendering.
857 * Can be called without any locks held.
860 void intel_frontbuffer_flip(struct drm_device *dev,
861 unsigned frontbuffer_bits)
863 intel_frontbuffer_flush(dev, frontbuffer_bits);
866 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
870 void intel_init_audio(struct drm_device *dev);
871 void intel_audio_codec_enable(struct intel_encoder *encoder);
872 void intel_audio_codec_disable(struct intel_encoder *encoder);
874 /* intel_display.c */
875 const char *intel_output_name(int output);
876 bool intel_has_pending_fb_unpin(struct drm_device *dev);
877 int intel_pch_rawclk(struct drm_device *dev);
878 void intel_mark_busy(struct drm_device *dev);
879 void intel_mark_idle(struct drm_device *dev);
880 void intel_crtc_restore_mode(struct drm_crtc *crtc);
881 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
882 void intel_crtc_update_dpms(struct drm_crtc *crtc);
883 void intel_encoder_destroy(struct drm_encoder *encoder);
884 void intel_connector_dpms(struct drm_connector *, int mode);
885 bool intel_connector_get_hw_state(struct intel_connector *connector);
886 void intel_modeset_check_state(struct drm_device *dev);
887 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
888 struct intel_digital_port *port);
889 void intel_connector_attach_encoder(struct intel_connector *connector,
890 struct intel_encoder *encoder);
891 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
892 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
893 struct drm_crtc *crtc);
894 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
895 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
899 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
901 intel_wait_for_vblank(struct drm_device *dev, int pipe)
903 drm_wait_one_vblank(dev, pipe);
905 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
906 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
907 struct intel_digital_port *dport);
908 bool intel_get_load_detect_pipe(struct drm_connector *connector,
909 struct drm_display_mode *mode,
910 struct intel_load_detect_pipe *old,
911 struct drm_modeset_acquire_ctx *ctx);
912 void intel_release_load_detect_pipe(struct drm_connector *connector,
913 struct intel_load_detect_pipe *old);
914 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
915 struct drm_framebuffer *fb,
916 struct intel_engine_cs *pipelined);
917 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
918 struct drm_framebuffer *
919 __intel_framebuffer_create(struct drm_device *dev,
920 struct drm_mode_fb_cmd2 *mode_cmd,
921 struct drm_i915_gem_object *obj);
922 void intel_prepare_page_flip(struct drm_device *dev, int plane);
923 void intel_finish_page_flip(struct drm_device *dev, int pipe);
924 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
925 void intel_check_page_flip(struct drm_device *dev, int pipe);
927 /* shared dpll functions */
928 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
929 void assert_shared_dpll(struct drm_i915_private *dev_priv,
930 struct intel_shared_dpll *pll,
932 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
933 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
934 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
935 void intel_put_shared_dpll(struct intel_crtc *crtc);
937 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
938 const struct dpll *dpll);
939 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
941 /* modesetting asserts */
942 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
944 void assert_pll(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state);
946 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
947 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
948 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state);
950 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
951 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
952 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
953 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
954 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
955 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
956 unsigned int tiling_mode,
959 void intel_prepare_reset(struct drm_device *dev);
960 void intel_finish_reset(struct drm_device *dev);
961 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
962 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
963 void intel_dp_get_m_n(struct intel_crtc *crtc,
964 struct intel_crtc_config *pipe_config);
965 void intel_dp_set_m_n(struct intel_crtc *crtc);
966 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
968 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
970 bool intel_crtc_active(struct drm_crtc *crtc);
971 void hsw_enable_ips(struct intel_crtc *crtc);
972 void hsw_disable_ips(struct intel_crtc *crtc);
973 enum intel_display_power_domain
974 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
975 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
976 struct intel_crtc_config *pipe_config);
977 int intel_format_to_fourcc(int format);
978 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
979 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
982 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
983 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
984 struct intel_connector *intel_connector);
985 void intel_dp_start_link_train(struct intel_dp *intel_dp);
986 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
987 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
988 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
989 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
990 void intel_dp_check_link_status(struct intel_dp *intel_dp);
991 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
992 bool intel_dp_compute_config(struct intel_encoder *encoder,
993 struct intel_crtc_config *pipe_config);
994 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
995 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
997 void intel_edp_backlight_on(struct intel_dp *intel_dp);
998 void intel_edp_backlight_off(struct intel_dp *intel_dp);
999 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1000 void intel_edp_panel_on(struct intel_dp *intel_dp);
1001 void intel_edp_panel_off(struct intel_dp *intel_dp);
1002 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
1003 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1004 void intel_dp_mst_suspend(struct drm_device *dev);
1005 void intel_dp_mst_resume(struct drm_device *dev);
1006 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1007 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1008 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1009 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1010 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
1012 /* intel_dp_mst.c */
1013 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1014 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1016 void intel_dsi_init(struct drm_device *dev);
1020 void intel_dvo_init(struct drm_device *dev);
1023 /* legacy fbdev emulation in intel_fbdev.c */
1024 #ifdef CONFIG_DRM_I915_FBDEV
1025 extern int intel_fbdev_init(struct drm_device *dev);
1026 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1027 extern void intel_fbdev_fini(struct drm_device *dev);
1028 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1029 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1030 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1032 static inline int intel_fbdev_init(struct drm_device *dev)
1037 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1041 static inline void intel_fbdev_fini(struct drm_device *dev)
1045 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1049 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1055 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1056 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1057 struct intel_connector *intel_connector);
1058 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1059 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1060 struct intel_crtc_config *pipe_config);
1064 void intel_lvds_init(struct drm_device *dev);
1065 bool intel_is_dual_link_lvds(struct drm_device *dev);
1069 int intel_connector_update_modes(struct drm_connector *connector,
1071 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1072 void intel_attach_force_audio_property(struct drm_connector *connector);
1073 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1076 /* intel_overlay.c */
1077 void intel_setup_overlay(struct drm_device *dev);
1078 void intel_cleanup_overlay(struct drm_device *dev);
1079 int intel_overlay_switch_off(struct intel_overlay *overlay);
1080 int intel_overlay_put_image(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082 int intel_overlay_attrs(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1087 int intel_panel_init(struct intel_panel *panel,
1088 struct drm_display_mode *fixed_mode,
1089 struct drm_display_mode *downclock_mode);
1090 void intel_panel_fini(struct intel_panel *panel);
1091 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1092 struct drm_display_mode *adjusted_mode);
1093 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1094 struct intel_crtc_config *pipe_config,
1096 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1097 struct intel_crtc_config *pipe_config,
1099 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1100 u32 level, u32 max);
1101 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1102 void intel_panel_enable_backlight(struct intel_connector *connector);
1103 void intel_panel_disable_backlight(struct intel_connector *connector);
1104 void intel_panel_destroy_backlight(struct drm_connector *connector);
1105 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1106 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1107 extern struct drm_display_mode *intel_find_panel_downclock(
1108 struct drm_device *dev,
1109 struct drm_display_mode *fixed_mode,
1110 struct drm_connector *connector);
1111 void intel_backlight_register(struct drm_device *dev);
1112 void intel_backlight_unregister(struct drm_device *dev);
1116 void intel_psr_enable(struct intel_dp *intel_dp);
1117 void intel_psr_disable(struct intel_dp *intel_dp);
1118 void intel_psr_invalidate(struct drm_device *dev,
1119 unsigned frontbuffer_bits);
1120 void intel_psr_flush(struct drm_device *dev,
1121 unsigned frontbuffer_bits);
1122 void intel_psr_init(struct drm_device *dev);
1124 /* intel_runtime_pm.c */
1125 int intel_power_domains_init(struct drm_i915_private *);
1126 void intel_power_domains_fini(struct drm_i915_private *);
1127 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1128 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1130 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1131 enum intel_display_power_domain domain);
1132 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1133 enum intel_display_power_domain domain);
1134 void intel_display_power_get(struct drm_i915_private *dev_priv,
1135 enum intel_display_power_domain domain);
1136 void intel_display_power_put(struct drm_i915_private *dev_priv,
1137 enum intel_display_power_domain domain);
1138 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1139 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1140 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1141 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1142 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1144 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1147 void intel_init_clock_gating(struct drm_device *dev);
1148 void intel_suspend_hw(struct drm_device *dev);
1149 int ilk_wm_max_level(const struct drm_device *dev);
1150 void intel_update_watermarks(struct drm_crtc *crtc);
1151 void intel_update_sprite_watermarks(struct drm_plane *plane,
1152 struct drm_crtc *crtc,
1153 uint32_t sprite_width,
1154 uint32_t sprite_height,
1156 bool enabled, bool scaled);
1157 void intel_init_pm(struct drm_device *dev);
1158 void intel_pm_setup(struct drm_device *dev);
1159 bool intel_fbc_enabled(struct drm_device *dev);
1160 void intel_update_fbc(struct drm_device *dev);
1161 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1162 void intel_gpu_ips_teardown(void);
1163 void intel_init_gt_powersave(struct drm_device *dev);
1164 void intel_cleanup_gt_powersave(struct drm_device *dev);
1165 void intel_enable_gt_powersave(struct drm_device *dev);
1166 void intel_disable_gt_powersave(struct drm_device *dev);
1167 void intel_suspend_gt_powersave(struct drm_device *dev);
1168 void intel_reset_gt_powersave(struct drm_device *dev);
1169 void ironlake_teardown_rc6(struct drm_device *dev);
1170 void gen6_update_ring_freq(struct drm_device *dev);
1171 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1172 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1173 void ilk_wm_get_hw_state(struct drm_device *dev);
1174 void skl_wm_get_hw_state(struct drm_device *dev);
1175 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1176 struct skl_ddb_allocation *ddb /* out */);
1180 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1183 /* intel_sprite.c */
1184 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1185 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1187 int intel_plane_set_property(struct drm_plane *plane,
1188 struct drm_property *prop,
1190 int intel_plane_restore(struct drm_plane *plane);
1191 void intel_plane_disable(struct drm_plane *plane);
1192 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1193 struct drm_file *file_priv);
1194 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1195 struct drm_file *file_priv);
1196 bool intel_pipe_update_start(struct intel_crtc *crtc,
1197 uint32_t *start_vbl_count);
1198 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1201 void intel_tv_init(struct drm_device *dev);
1203 #endif /* __INTEL_DRV_H__ */