drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "intel_dp.h"
  37
  38 #define DP_LINK_STATUS_SIZE     6
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 #define DP_LINK_CONFIGURATION_SIZE      9
  42
  43 struct intel_dp_priv {
  44         uint32_t output_reg;
  45         uint32_t DP;
  46         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  47         uint32_t save_DP;
  48         uint8_t  save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
  49         bool has_audio;
  50         int dpms_mode;
  51         uint8_t link_bw;
  52         uint8_t lane_count;
  53         uint8_t dpcd[4];
  54         struct intel_output *intel_output;
  55         struct i2c_adapter adapter;
  56         struct i2c_algo_dp_aux_data algo;
  57 };
  58
  59 static void
  60 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
  61                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  62
  63 static void
  64 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
  65
  66 static int
  67 intel_dp_max_lane_count(struct intel_output *intel_output)
  68 {
  69         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
  70         int max_lane_count = 4;
  71
  72         if (dp_priv->dpcd[0] >= 0x11) {
  73                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  74                 switch (max_lane_count) {
  75                 case 1: case 2: case 4:
  76                         break;
  77                 default:
  78                         max_lane_count = 4;
  79                 }
  80         }
  81         return max_lane_count;
  82 }
  83
  84 static int
  85 intel_dp_max_link_bw(struct intel_output *intel_output)
  86 {
  87         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
  88         int max_link_bw = dp_priv->dpcd[1];
  89
  90         switch (max_link_bw) {
  91         case DP_LINK_BW_1_62:
  92         case DP_LINK_BW_2_7:
  93                 break;
  94         default:
  95                 max_link_bw = DP_LINK_BW_1_62;
  96                 break;
  97         }
  98         return max_link_bw;
  99 }
 100
 101 static int
 102 intel_dp_link_clock(uint8_t link_bw)
 103 {
 104         if (link_bw == DP_LINK_BW_2_7)
 105                 return 270000;
 106         else
 107                 return 162000;
 108 }
 109
 110 /* I think this is a fiction */
 111 static int
 112 intel_dp_link_required(int pixel_clock)
 113 {
 114         return pixel_clock * 3;
 115 }
 116
 117 static int
 118 intel_dp_mode_valid(struct drm_connector *connector,
 119                     struct drm_display_mode *mode)
 120 {
 121         struct intel_output *intel_output = to_intel_output(connector);
 122         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
 123         int max_lanes = intel_dp_max_lane_count(intel_output);
 124
 125         if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
 126                 return MODE_CLOCK_HIGH;
 127
 128         if (mode->clock < 10000)
 129                 return MODE_CLOCK_LOW;
 130
 131         return MODE_OK;
 132 }
 133
 134 static uint32_t
 135 pack_aux(uint8_t *src, int src_bytes)
 136 {
 137         int     i;
 138         uint32_t v = 0;
 139
 140         if (src_bytes > 4)
 141                 src_bytes = 4;
 142         for (i = 0; i < src_bytes; i++)
 143                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 144         return v;
 145 }
 146
 147 static void
 148 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 149 {
 150         int i;
 151         if (dst_bytes > 4)
 152                 dst_bytes = 4;
 153         for (i = 0; i < dst_bytes; i++)
 154                 dst[i] = src >> ((3-i) * 8);
 155 }
 156
 157 static int
 158 intel_dp_aux_ch(struct intel_output *intel_output,
 159                 uint8_t *send, int send_bytes,
 160                 uint8_t *recv, int recv_size)
 161 {
 162         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 163         uint32_t output_reg = dp_priv->output_reg;
 164         struct drm_device *dev = intel_output->base.dev;
 165         struct drm_i915_private *dev_priv = dev->dev_private;
 166         uint32_t ch_ctl = output_reg + 0x10;
 167         uint32_t ch_data = ch_ctl + 4;
 168         int i;
 169         int recv_bytes;
 170         uint32_t ctl;
 171         uint32_t status;
 172
 173         /* Load the send data into the aux channel data registers */
 174         for (i = 0; i < send_bytes; i += 4) {
 175                 uint32_t    d = pack_aux(send + i, send_bytes - i);;
 176
 177                 I915_WRITE(ch_data + i, d);
 178         }
 179
 180         /* The clock divider is based off the hrawclk,
 181          * and would like to run at 2MHz. The 133 below assumes
 182          * a 266MHz hrawclk; need to figure out how we're supposed
 183          * to know what hrawclk is...
 184          */
 185         ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 186                DP_AUX_CH_CTL_TIME_OUT_1600us |
 187                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 188                (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 189                (133 << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 190                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 191                DP_AUX_CH_CTL_RECEIVE_ERROR);
 192
 193         /* Send the command and wait for it to complete */
 194         I915_WRITE(ch_ctl, ctl);
 195         (void) I915_READ(ch_ctl);
 196         for (;;) {
 197                 udelay(100);
 198                 status = I915_READ(ch_ctl);
 199                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 200                         break;
 201         }
 202
 203         /* Clear done status and any errors */
 204         I915_WRITE(ch_ctl, (ctl |
 205                         DP_AUX_CH_CTL_DONE |
 206                         DP_AUX_CH_CTL_TIME_OUT_ERROR |
 207                         DP_AUX_CH_CTL_RECEIVE_ERROR));
 208         (void) I915_READ(ch_ctl);
 209
 210         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 211                 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status);
 212                 return -1;
 213         }
 214
 215         /* Check for timeout or receive error.
 216          * Timeouts occur when the sink is not connected
 217          */
 218         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR)) {
 219                 printk(KERN_ERR "dp_aux_ch error status 0x%08x\n", status);
 220                 return -1;
 221         }
 222
 223         /* Unload any bytes sent back from the other side */
 224         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 225                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 226
 227         if (recv_bytes > recv_size)
 228                 recv_bytes = recv_size;
 229
 230         for (i = 0; i < recv_bytes; i += 4) {
 231                 uint32_t    d = I915_READ(ch_data + i);
 232
 233                 unpack_aux(d, recv + i, recv_bytes - i);
 234         }
 235
 236         return recv_bytes;
 237 }
 238
 239 /* Write data to the aux channel in native mode */
 240 static int
 241 intel_dp_aux_native_write(struct intel_output *intel_output,
 242                           uint16_t address, uint8_t *send, int send_bytes)
 243 {
 244         int ret;
 245         uint8_t msg[20];
 246         int msg_bytes;
 247         uint8_t ack;
 248
 249         if (send_bytes > 16)
 250                 return -1;
 251         msg[0] = AUX_NATIVE_WRITE << 4;
 252         msg[1] = address >> 8;
 253         msg[2] = address;
 254         msg[3] = send_bytes - 1;
 255         memcpy(&msg[4], send, send_bytes);
 256         msg_bytes = send_bytes + 4;
 257         for (;;) {
 258                 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
 259                 if (ret < 0)
 260                         return ret;
 261                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 262                         break;
 263                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 264                         udelay(100);
 265                 else
 266                         return -1;
 267         }
 268         return send_bytes;
 269 }
 270
 271 /* Write a single byte to the aux channel in native mode */
 272 static int
 273 intel_dp_aux_native_write_1(struct intel_output *intel_output,
 274                             uint16_t address, uint8_t byte)
 275 {
 276         return intel_dp_aux_native_write(intel_output, address, &byte, 1);
 277 }
 278
 279 /* read bytes from a native aux channel */
 280 static int
 281 intel_dp_aux_native_read(struct intel_output *intel_output,
 282                          uint16_t address, uint8_t *recv, int recv_bytes)
 283 {
 284         uint8_t msg[4];
 285         int msg_bytes;
 286         uint8_t reply[20];
 287         int reply_bytes;
 288         uint8_t ack;
 289         int ret;
 290
 291         msg[0] = AUX_NATIVE_READ << 4;
 292         msg[1] = address >> 8;
 293         msg[2] = address & 0xff;
 294         msg[3] = recv_bytes - 1;
 295
 296         msg_bytes = 4;
 297         reply_bytes = recv_bytes + 1;
 298
 299         for (;;) {
 300                 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
 301                                       reply, reply_bytes);
 302                 if (ret <= 0)
 303                         return ret;
 304                 ack = reply[0];
 305                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 306                         memcpy(recv, reply + 1, ret - 1);
 307                         return ret - 1;
 308                 }
 309                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 310                         udelay(100);
 311                 else
 312                         return -1;
 313         }
 314 }
 315
 316 static int
 317 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
 318                     uint8_t *send, int send_bytes,
 319                     uint8_t *recv, int recv_bytes)
 320 {
 321         struct intel_dp_priv *dp_priv = container_of(adapter,
 322                                                      struct intel_dp_priv,
 323                                                      adapter);
 324         struct intel_output *intel_output = dp_priv->intel_output;
 325
 326         return intel_dp_aux_ch(intel_output,
 327                                send, send_bytes, recv, recv_bytes);
 328 }
 329
 330 static int
 331 intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
 332 {
 333         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
 334
 335         DRM_ERROR("i2c_init %s\n", name);
 336         dp_priv->algo.running = false;
 337         dp_priv->algo.address = 0;
 338         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 339
 340         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 341         dp_priv->adapter.owner = THIS_MODULE;
 342         dp_priv->adapter.class = I2C_CLASS_DDC;
 343         strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
 344         dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
 345         dp_priv->adapter.algo_data = &dp_priv->algo;
 346         dp_priv->adapter.dev.parent = &intel_output->base.kdev;
 347
 348         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 349 }
 350
 351 static bool
 352 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 353                     struct drm_display_mode *adjusted_mode)
 354 {
 355         struct intel_output *intel_output = enc_to_intel_output(encoder);
 356         struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
 357         int lane_count, clock;
 358         int max_lane_count = intel_dp_max_lane_count(intel_output);
 359         int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
 360         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 361
 362         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 363                 for (clock = 0; clock <= max_clock; clock++) {
 364                         int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
 365
 366                         if (intel_dp_link_required(mode->clock) <= link_avail) {
 367                                 dp_priv->link_bw = bws[clock];
 368                                 dp_priv->lane_count = lane_count;
 369                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 370                                 printk(KERN_ERR "link bw %02x lane count %d clock %d\n",
 371                                        dp_priv->link_bw, dp_priv->lane_count,
 372                                        adjusted_mode->clock);
 373                                 return true;
 374                         }
 375                 }
 376         }
 377         return false;
 378 }
 379
 380 struct intel_dp_m_n {
 381         uint32_t        tu;
 382         uint32_t        gmch_m;
 383         uint32_t        gmch_n;
 384         uint32_t        link_m;
 385         uint32_t        link_n;
 386 };
 387
 388 static void
 389 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 390 {
 391         while (*num > 0xffffff || *den > 0xffffff) {
 392                 *num >>= 1;
 393                 *den >>= 1;
 394         }
 395 }
 396
 397 static void
 398 intel_dp_compute_m_n(int bytes_per_pixel,
 399                      int nlanes,
 400                      int pixel_clock,
 401                      int link_clock,
 402                      struct intel_dp_m_n *m_n)
 403 {
 404         m_n->tu = 64;
 405         m_n->gmch_m = pixel_clock * bytes_per_pixel;
 406         m_n->gmch_n = link_clock * nlanes;
 407         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 408         m_n->link_m = pixel_clock;
 409         m_n->link_n = link_clock;
 410         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 411 }
 412
 413 void
 414 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 415                  struct drm_display_mode *adjusted_mode)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         struct drm_mode_config *mode_config = &dev->mode_config;
 419         struct drm_connector *connector;
 420         struct drm_i915_private *dev_priv = dev->dev_private;
 421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 422         int lane_count = 4;
 423         struct intel_dp_m_n m_n;
 424
 425         /*
 426          * Find the lane count in the intel_output private
 427          */
 428         list_for_each_entry(connector, &mode_config->connector_list, head) {
 429                 struct intel_output *intel_output = to_intel_output(connector);
 430                 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 431
 432                 if (!connector->encoder || connector->encoder->crtc != crtc)
 433                         continue;
 434
 435                 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
 436                         lane_count = dp_priv->lane_count;
 437                         break;
 438                 }
 439         }
 440
 441         /*
 442          * Compute the GMCH and Link ratios. The '3' here is
 443          * the number of bytes_per_pixel post-LUT, which we always
 444          * set up for 8-bits of R/G/B, or 3 bytes total.
 445          */
 446         intel_dp_compute_m_n(3, lane_count,
 447                              mode->clock, adjusted_mode->clock, &m_n);
 448
 449         if (intel_crtc->pipe == 0) {
 450                 I915_WRITE(PIPEA_GMCH_DATA_M,
 451                        ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 452                        m_n.gmch_m);
 453                 I915_WRITE(PIPEA_GMCH_DATA_N,
 454                        m_n.gmch_n);
 455                 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 456                 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 457         } else {
 458                 I915_WRITE(PIPEB_GMCH_DATA_M,
 459                        ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 460                        m_n.gmch_m);
 461                 I915_WRITE(PIPEB_GMCH_DATA_N,
 462                        m_n.gmch_n);
 463                 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 464                 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 465         }
 466 }
 467
 468 static void
 469 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 470                   struct drm_display_mode *adjusted_mode)
 471 {
 472         struct intel_output *intel_output = enc_to_intel_output(encoder);
 473         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 474         struct drm_crtc *crtc = intel_output->enc.crtc;
 475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 476
 477         dp_priv->DP = (DP_LINK_TRAIN_OFF |
 478                         DP_VOLTAGE_0_4 |
 479                         DP_PRE_EMPHASIS_0 |
 480                         DP_SYNC_VS_HIGH |
 481                         DP_SYNC_HS_HIGH);
 482
 483         switch (dp_priv->lane_count) {
 484         case 1:
 485                 dp_priv->DP |= DP_PORT_WIDTH_1;
 486                 break;
 487         case 2:
 488                 dp_priv->DP |= DP_PORT_WIDTH_2;
 489                 break;
 490         case 4:
 491                 dp_priv->DP |= DP_PORT_WIDTH_4;
 492                 break;
 493         }
 494         if (dp_priv->has_audio)
 495                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 496
 497         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 498         dp_priv->link_configuration[0] = dp_priv->link_bw;
 499         dp_priv->link_configuration[1] = dp_priv->lane_count;
 500
 501         /*
 502          * Check for DPCD version > 1.1,
 503          * enable enahanced frame stuff in that case
 504          */
 505         if (dp_priv->dpcd[0] >= 0x11) {
 506                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 507                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 508         }
 509
 510         if (intel_crtc->pipe == 1)
 511                 dp_priv->DP |= DP_PIPEB_SELECT;
 512 }
 513
 514
 515 static void
 516 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 517 {
 518         struct intel_output *intel_output = enc_to_intel_output(encoder);
 519         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 520         struct drm_device *dev = intel_output->base.dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 523
 524         if (mode != DRM_MODE_DPMS_ON) {
 525                 if (dp_reg & DP_PORT_EN)
 526                         intel_dp_link_down(intel_output, dp_priv->DP);
 527         } else {
 528                 if (!(dp_reg & DP_PORT_EN))
 529                         intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
 530         }
 531         dp_priv->dpms_mode = mode;
 532 }
 533
 534 /*
 535  * Fetch AUX CH registers 0x202 - 0x207 which contain
 536  * link status information
 537  */
 538 static bool
 539 intel_dp_get_link_status(struct intel_output *intel_output,
 540                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 541 {
 542         int ret;
 543
 544         ret = intel_dp_aux_native_read(intel_output,
 545                                        DP_LANE0_1_STATUS,
 546                                        link_status, DP_LINK_STATUS_SIZE);
 547         if (ret != DP_LINK_STATUS_SIZE)
 548                 return false;
 549         return true;
 550 }
 551
 552 static uint8_t
 553 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 554                      int r)
 555 {
 556         return link_status[r - DP_LANE0_1_STATUS];
 557 }
 558
 559 static void
 560 intel_dp_save(struct drm_connector *connector)
 561 {
 562         struct intel_output *intel_output = to_intel_output(connector);
 563         struct drm_device *dev = intel_output->base.dev;
 564         struct drm_i915_private *dev_priv = dev->dev_private;
 565         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 566
 567         dp_priv->save_DP = I915_READ(dp_priv->output_reg);
 568         intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
 569                                  dp_priv->save_link_configuration,
 570                                  sizeof (dp_priv->save_link_configuration));
 571 }
 572
 573 static uint8_t
 574 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 575                                  int lane)
 576 {
 577         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 578         int         s = ((lane & 1) ?
 579                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 580                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 581         uint8_t l = intel_dp_link_status(link_status, i);
 582
 583         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 584 }
 585
 586 static uint8_t
 587 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 588                                       int lane)
 589 {
 590         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 591         int         s = ((lane & 1) ?
 592                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 593                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 594         uint8_t l = intel_dp_link_status(link_status, i);
 595
 596         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 597 }
 598
 599
 600 #if 0
 601 static char     *voltage_names[] = {
 602         "0.4V", "0.6V", "0.8V", "1.2V"
 603 };
 604 static char     *pre_emph_names[] = {
 605         "0dB", "3.5dB", "6dB", "9.5dB"
 606 };
 607 static char     *link_train_names[] = {
 608         "pattern 1", "pattern 2", "idle", "off"
 609 };
 610 #endif
 611
 612 /*
 613  * These are source-specific values; current Intel hardware supports
 614  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 615  */
 616 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 617
 618 static uint8_t
 619 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 620 {
 621         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 622         case DP_TRAIN_VOLTAGE_SWING_400:
 623                 return DP_TRAIN_PRE_EMPHASIS_6;
 624         case DP_TRAIN_VOLTAGE_SWING_600:
 625                 return DP_TRAIN_PRE_EMPHASIS_6;
 626         case DP_TRAIN_VOLTAGE_SWING_800:
 627                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 628         case DP_TRAIN_VOLTAGE_SWING_1200:
 629         default:
 630                 return DP_TRAIN_PRE_EMPHASIS_0;
 631         }
 632 }
 633
 634 static void
 635 intel_get_adjust_train(struct intel_output *intel_output,
 636                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 637                        int lane_count,
 638                        uint8_t train_set[4])
 639 {
 640         uint8_t v = 0;
 641         uint8_t p = 0;
 642         int lane;
 643
 644         for (lane = 0; lane < lane_count; lane++) {
 645                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 646                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 647
 648                 if (this_v > v)
 649                         v = this_v;
 650                 if (this_p > p)
 651                         p = this_p;
 652         }
 653
 654         if (v >= I830_DP_VOLTAGE_MAX)
 655                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 656
 657         if (p >= intel_dp_pre_emphasis_max(v))
 658                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 659
 660         for (lane = 0; lane < 4; lane++)
 661                 train_set[lane] = v | p;
 662 }
 663
 664 static uint32_t
 665 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 666 {
 667         uint32_t        signal_levels = 0;
 668
 669         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 670         case DP_TRAIN_VOLTAGE_SWING_400:
 671         default:
 672                 signal_levels |= DP_VOLTAGE_0_4;
 673                 break;
 674         case DP_TRAIN_VOLTAGE_SWING_600:
 675                 signal_levels |= DP_VOLTAGE_0_6;
 676                 break;
 677         case DP_TRAIN_VOLTAGE_SWING_800:
 678                 signal_levels |= DP_VOLTAGE_0_8;
 679                 break;
 680         case DP_TRAIN_VOLTAGE_SWING_1200:
 681                 signal_levels |= DP_VOLTAGE_1_2;
 682                 break;
 683         }
 684         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 685         case DP_TRAIN_PRE_EMPHASIS_0:
 686         default:
 687                 signal_levels |= DP_PRE_EMPHASIS_0;
 688                 break;
 689         case DP_TRAIN_PRE_EMPHASIS_3_5:
 690                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 691                 break;
 692         case DP_TRAIN_PRE_EMPHASIS_6:
 693                 signal_levels |= DP_PRE_EMPHASIS_6;
 694                 break;
 695         case DP_TRAIN_PRE_EMPHASIS_9_5:
 696                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 697                 break;
 698         }
 699         return signal_levels;
 700 }
 701
 702 static uint8_t
 703 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 704                       int lane)
 705 {
 706         int i = DP_LANE0_1_STATUS + (lane >> 1);
 707         int s = (lane & 1) * 4;
 708         uint8_t l = intel_dp_link_status(link_status, i);
 709
 710         return (l >> s) & 0xf;
 711 }
 712
 713 /* Check for clock recovery is done on all channels */
 714 static bool
 715 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 716 {
 717         int lane;
 718         uint8_t lane_status;
 719
 720         for (lane = 0; lane < lane_count; lane++) {
 721                 lane_status = intel_get_lane_status(link_status, lane);
 722                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 723                         return false;
 724         }
 725         return true;
 726 }
 727
 728 /* Check to see if channel eq is done on all channels */
 729 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 730                          DP_LANE_CHANNEL_EQ_DONE|\
 731                          DP_LANE_SYMBOL_LOCKED)
 732 static bool
 733 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 734 {
 735         uint8_t lane_align;
 736         uint8_t lane_status;
 737         int lane;
 738
 739         lane_align = intel_dp_link_status(link_status,
 740                                           DP_LANE_ALIGN_STATUS_UPDATED);
 741         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 742                 return false;
 743         for (lane = 0; lane < lane_count; lane++) {
 744                 lane_status = intel_get_lane_status(link_status, lane);
 745                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 746                         return false;
 747         }
 748         return true;
 749 }
 750
 751 static bool
 752 intel_dp_set_link_train(struct intel_output *intel_output,
 753                         uint32_t dp_reg_value,
 754                         uint8_t dp_train_pat,
 755                         uint8_t train_set[4],
 756                         bool first)
 757 {
 758         struct drm_device *dev = intel_output->base.dev;
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 761         int ret;
 762
 763         I915_WRITE(dp_priv->output_reg, dp_reg_value);
 764         POSTING_READ(dp_priv->output_reg);
 765         if (first)
 766                 intel_wait_for_vblank(dev);
 767
 768         intel_dp_aux_native_write_1(intel_output,
 769                                     DP_TRAINING_PATTERN_SET,
 770                                     dp_train_pat);
 771
 772         ret = intel_dp_aux_native_write(intel_output,
 773                                         DP_TRAINING_LANE0_SET, train_set, 4);
 774         if (ret != 4)
 775                 return false;
 776
 777         return true;
 778 }
 779
 780 static void
 781 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
 782                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
 783 {
 784         struct drm_device *dev = intel_output->base.dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 787         uint8_t train_set[4];
 788         uint8_t link_status[DP_LINK_STATUS_SIZE];
 789         int i;
 790         uint8_t voltage;
 791         bool clock_recovery = false;
 792         bool channel_eq = false;
 793         bool first = true;
 794         int tries;
 795
 796         /* Write the link configuration data */
 797         intel_dp_aux_native_write(intel_output, 0x100,
 798                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
 799
 800         DP |= DP_PORT_EN;
 801         DP &= ~DP_LINK_TRAIN_MASK;
 802         memset(train_set, 0, 4);
 803         voltage = 0xff;
 804         tries = 0;
 805         clock_recovery = false;
 806         for (;;) {
 807                 /* Use train_set[0] to set the voltage and pre emphasis values */
 808                 uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
 809                 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
 810
 811                 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
 812                                              DP_TRAINING_PATTERN_1, train_set, first))
 813                         break;
 814                 first = false;
 815                 /* Set training pattern 1 */
 816
 817                 udelay(100);
 818                 if (!intel_dp_get_link_status(intel_output, link_status))
 819                         break;
 820
 821                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
 822                         clock_recovery = true;
 823                         break;
 824                 }
 825
 826                 /* Check to see if we've tried the max voltage */
 827                 for (i = 0; i < dp_priv->lane_count; i++)
 828                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 829                                 break;
 830                 if (i == dp_priv->lane_count)
 831                         break;
 832
 833                 /* Check to see if we've tried the same voltage 5 times */
 834                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 835                         ++tries;
 836                         if (tries == 5)
 837                                 break;
 838                 } else
 839                         tries = 0;
 840                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 841
 842                 /* Compute new train_set as requested by target */
 843                 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
 844         }
 845
 846         /* channel equalization */
 847         tries = 0;
 848         channel_eq = false;
 849         for (;;) {
 850                 /* Use train_set[0] to set the voltage and pre emphasis values */
 851                 uint32_t    signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
 852                 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
 853
 854                 /* channel eq pattern */
 855                 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
 856                                              DP_TRAINING_PATTERN_2, train_set,
 857                                              false))
 858                         break;
 859
 860                 udelay(400);
 861                 if (!intel_dp_get_link_status(intel_output, link_status))
 862                         break;
 863
 864                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
 865                         channel_eq = true;
 866                         break;
 867                 }
 868
 869                 /* Try 5 times */
 870                 if (tries > 5)
 871                         break;
 872
 873                 /* Compute new train_set as requested by target */
 874                 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
 875                 ++tries;
 876         }
 877
 878         I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
 879         POSTING_READ(dp_priv->output_reg);
 880         intel_dp_aux_native_write_1(intel_output,
 881                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
 882 }
 883
 884 static void
 885 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
 886 {
 887         struct drm_device *dev = intel_output->base.dev;
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 890
 891         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
 892         POSTING_READ(dp_priv->output_reg);
 893 }
 894
 895 static void
 896 intel_dp_restore(struct drm_connector *connector)
 897 {
 898         struct intel_output *intel_output = to_intel_output(connector);
 899         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 900
 901         if (dp_priv->save_DP & DP_PORT_EN)
 902                 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
 903         else
 904                 intel_dp_link_down(intel_output,  dp_priv->save_DP);
 905 }
 906
 907 /*
 908  * According to DP spec
 909  * 5.1.2:
 910  *  1. Read DPCD
 911  *  2. Configure link according to Receiver Capabilities
 912  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 913  *  4. Check link status on receipt of hot-plug interrupt
 914  */
 915
 916 static void
 917 intel_dp_check_link_status(struct intel_output *intel_output)
 918 {
 919         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 920         uint8_t link_status[DP_LINK_STATUS_SIZE];
 921
 922         if (!intel_output->enc.crtc)
 923                 return;
 924
 925         if (!intel_dp_get_link_status(intel_output, link_status)) {
 926                 intel_dp_link_down(intel_output, dp_priv->DP);
 927                 return;
 928         }
 929
 930         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
 931                 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
 932 }
 933
 934 /**
 935  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
 936  *
 937  * \return true if DP port is connected.
 938  * \return false if DP port is disconnected.
 939  */
 940 static enum drm_connector_status
 941 intel_dp_detect(struct drm_connector *connector)
 942 {
 943         struct intel_output *intel_output = to_intel_output(connector);
 944         struct drm_device *dev = intel_output->base.dev;
 945         struct drm_i915_private *dev_priv = dev->dev_private;
 946         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
 947         uint32_t temp, bit;
 948         enum drm_connector_status status;
 949
 950         dp_priv->has_audio = false;
 951
 952         temp = I915_READ(PORT_HOTPLUG_EN);
 953
 954         I915_WRITE(PORT_HOTPLUG_EN,
 955                temp |
 956                DPB_HOTPLUG_INT_EN |
 957                DPC_HOTPLUG_INT_EN |
 958                DPD_HOTPLUG_INT_EN);
 959
 960         POSTING_READ(PORT_HOTPLUG_EN);
 961
 962         switch (dp_priv->output_reg) {
 963         case DP_B:
 964                 bit = DPB_HOTPLUG_INT_STATUS;
 965                 break;
 966         case DP_C:
 967                 bit = DPC_HOTPLUG_INT_STATUS;
 968                 break;
 969         case DP_D:
 970                 bit = DPD_HOTPLUG_INT_STATUS;
 971                 break;
 972         default:
 973                 return connector_status_unknown;
 974         }
 975
 976         temp = I915_READ(PORT_HOTPLUG_STAT);
 977
 978         if ((temp & bit) == 0)
 979                 return connector_status_disconnected;
 980
 981         status = connector_status_disconnected;
 982         if (intel_dp_aux_native_read(intel_output,
 983                                      0x000, dp_priv->dpcd,
 984                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
 985         {
 986                 if (dp_priv->dpcd[0] != 0)
 987                         status = connector_status_connected;
 988         }
 989         return status;
 990 }
 991
 992 static int intel_dp_get_modes(struct drm_connector *connector)
 993 {
 994         struct intel_output *intel_output = to_intel_output(connector);
 995
 996         /* We should parse the EDID data and find out if it has an audio sink
 997          */
 998
 999         return intel_ddc_get_modes(intel_output);
1000 }
1001
1002 static void
1003 intel_dp_destroy (struct drm_connector *connector)
1004 {
1005         struct intel_output *intel_output = to_intel_output(connector);
1006
1007         if (intel_output->i2c_bus)
1008                 intel_i2c_destroy(intel_output->i2c_bus);
1009         drm_sysfs_connector_remove(connector);
1010         drm_connector_cleanup(connector);
1011         kfree(intel_output);
1012 }
1013
1014 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1015         .dpms = intel_dp_dpms,
1016         .mode_fixup = intel_dp_mode_fixup,
1017         .prepare = intel_encoder_prepare,
1018         .mode_set = intel_dp_mode_set,
1019         .commit = intel_encoder_commit,
1020 };
1021
1022 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1023         .dpms = drm_helper_connector_dpms,
1024         .save = intel_dp_save,
1025         .restore = intel_dp_restore,
1026         .detect = intel_dp_detect,
1027         .fill_modes = drm_helper_probe_single_connector_modes,
1028         .destroy = intel_dp_destroy,
1029 };
1030
1031 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1032         .get_modes = intel_dp_get_modes,
1033         .mode_valid = intel_dp_mode_valid,
1034         .best_encoder = intel_best_encoder,
1035 };
1036
1037 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1038 {
1039         drm_encoder_cleanup(encoder);
1040 }
1041
1042 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1043         .destroy = intel_dp_enc_destroy,
1044 };
1045
1046 void
1047 intel_dp_hot_plug(struct intel_output *intel_output)
1048 {
1049         struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1050
1051         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1052                 intel_dp_check_link_status(intel_output);
1053 }
1054
1055 void
1056 intel_dp_init(struct drm_device *dev, int output_reg)
1057 {
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         struct drm_connector *connector;
1060         struct intel_output *intel_output;
1061         struct intel_dp_priv *dp_priv;
1062
1063         intel_output = kcalloc(sizeof(struct intel_output) +
1064                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1065         if (!intel_output)
1066                 return;
1067
1068         dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1069
1070         connector = &intel_output->base;
1071         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1072                            DRM_MODE_CONNECTOR_DisplayPort);
1073         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1074
1075         intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1076
1077         connector->interlace_allowed = true;
1078         connector->doublescan_allowed = 0;
1079
1080         dp_priv->intel_output = intel_output;
1081         dp_priv->output_reg = output_reg;
1082         dp_priv->has_audio = false;
1083         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1084         intel_output->dev_priv = dp_priv;
1085
1086         drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1087                          DRM_MODE_ENCODER_TMDS);
1088         drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1089
1090         drm_mode_connector_attach_encoder(&intel_output->base,
1091                                           &intel_output->enc);
1092         drm_sysfs_connector_add(connector);
1093
1094         /* Set up the DDC bus. */
1095         intel_dp_i2c_init(intel_output,
1096                           (output_reg == DP_B) ? "DPDDC-B" :
1097                           (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
1098         intel_output->ddc_bus = &dp_priv->adapter;
1099         intel_output->hot_plug = intel_dp_hot_plug;
1100
1101         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1102          * 0xd.  Failure to do so will result in spurious interrupts being
1103          * generated on the port when a cable is not attached.
1104          */
1105         if (IS_G4X(dev) && !IS_GM45(dev)) {
1106                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1107                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1108         }
1109 }