drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[8];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70         unsigned long panel_off_jiffies;
  71 };
  72
  73 /**
  74  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  75  * @intel_dp: DP struct
  76  *
  77  * If a CPU or PCH DP output is attached to an eDP panel, this function
  78  * will return true, and false otherwise.
  79  */
  80 static bool is_edp(struct intel_dp *intel_dp)
  81 {
  82         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  83 }
  84
  85 /**
  86  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  87  * @intel_dp: DP struct
  88  *
  89  * Returns true if the given DP struct corresponds to a PCH DP port attached
  90  * to an eDP panel, false otherwise.  Helpful for determining whether we
  91  * may need FDI resources for a given DP output or not.
  92  */
  93 static bool is_pch_edp(struct intel_dp *intel_dp)
  94 {
  95         return intel_dp->is_pch_edp;
  96 }
  97
  98 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  99 {
 100         return container_of(encoder, struct intel_dp, base.base);
 101 }
 102
 103 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 104 {
 105         return container_of(intel_attached_encoder(connector),
 106                             struct intel_dp, base);
 107 }
 108
 109 /**
 110  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 111  * @encoder: DRM encoder
 112  *
 113  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 114  * by intel_display.c.
 115  */
 116 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 117 {
 118         struct intel_dp *intel_dp;
 119
 120         if (!encoder)
 121                 return false;
 122
 123         intel_dp = enc_to_intel_dp(encoder);
 124
 125         return is_pch_edp(intel_dp);
 126 }
 127
 128 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 129 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 130 static void intel_dp_link_down(struct intel_dp *intel_dp);
 131
 132 void
 133 intel_edp_link_config(struct intel_encoder *intel_encoder,
 134                        int *lane_num, int *link_bw)
 135 {
 136         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 137
 138         *lane_num = intel_dp->lane_count;
 139         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 140                 *link_bw = 162000;
 141         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 142                 *link_bw = 270000;
 143 }
 144
 145 static int
 146 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 147 {
 148         int max_lane_count = 4;
 149
 150         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 151                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 152                 switch (max_lane_count) {
 153                 case 1: case 2: case 4:
 154                         break;
 155                 default:
 156                         max_lane_count = 4;
 157                 }
 158         }
 159         return max_lane_count;
 160 }
 161
 162 static int
 163 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 164 {
 165         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 166
 167         switch (max_link_bw) {
 168         case DP_LINK_BW_1_62:
 169         case DP_LINK_BW_2_7:
 170                 break;
 171         default:
 172                 max_link_bw = DP_LINK_BW_1_62;
 173                 break;
 174         }
 175         return max_link_bw;
 176 }
 177
 178 static int
 179 intel_dp_link_clock(uint8_t link_bw)
 180 {
 181         if (link_bw == DP_LINK_BW_2_7)
 182                 return 270000;
 183         else
 184                 return 162000;
 185 }
 186
 187 /* I think this is a fiction */
 188 static int
 189 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 190 {
 191         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 193         int bpp = 24;
 194
 195         if (intel_crtc)
 196                 bpp = intel_crtc->bpp;
 197
 198         return (pixel_clock * bpp + 7) / 8;
 199 }
 200
 201 static int
 202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 203 {
 204         return (max_link_clock * max_lanes * 8) / 10;
 205 }
 206
 207 static int
 208 intel_dp_mode_valid(struct drm_connector *connector,
 209                     struct drm_display_mode *mode)
 210 {
 211         struct intel_dp *intel_dp = intel_attached_dp(connector);
 212         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 213         int max_lanes = intel_dp_max_lane_count(intel_dp);
 214
 215         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 216                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 217                         return MODE_PANEL;
 218
 219                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 220                         return MODE_PANEL;
 221         }
 222
 223         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 224            which are outside spec tolerances but somehow work by magic */
 225         if (!is_edp(intel_dp) &&
 226             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 227              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 228                 return MODE_CLOCK_HIGH;
 229
 230         if (mode->clock < 10000)
 231                 return MODE_CLOCK_LOW;
 232
 233         return MODE_OK;
 234 }
 235
 236 static uint32_t
 237 pack_aux(uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void
 250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         clkcfg = I915_READ(CLKCFG);
 267         switch (clkcfg & CLKCFG_FSB_MASK) {
 268         case CLKCFG_FSB_400:
 269                 return 100;
 270         case CLKCFG_FSB_533:
 271                 return 133;
 272         case CLKCFG_FSB_667:
 273                 return 166;
 274         case CLKCFG_FSB_800:
 275                 return 200;
 276         case CLKCFG_FSB_1067:
 277                 return 266;
 278         case CLKCFG_FSB_1333:
 279                 return 333;
 280         /* these two are just a guess; one of them might be right */
 281         case CLKCFG_FSB_1600:
 282         case CLKCFG_FSB_1600_ALT:
 283                 return 400;
 284         default:
 285                 return 133;
 286         }
 287 }
 288
 289 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 290 {
 291         struct drm_device *dev = intel_dp->base.base.dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293
 294         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 295 }
 296
 297 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 298 {
 299         struct drm_device *dev = intel_dp->base.base.dev;
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301
 302         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 303 }
 304
 305 static void
 306 intel_dp_check_edp(struct intel_dp *intel_dp)
 307 {
 308         struct drm_device *dev = intel_dp->base.base.dev;
 309         struct drm_i915_private *dev_priv = dev->dev_private;
 310
 311         if (!is_edp(intel_dp))
 312                 return;
 313         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 314                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 315                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 316                               I915_READ(PCH_PP_STATUS),
 317                               I915_READ(PCH_PP_CONTROL));
 318         }
 319 }
 320
 321 static int
 322 intel_dp_aux_ch(struct intel_dp *intel_dp,
 323                 uint8_t *send, int send_bytes,
 324                 uint8_t *recv, int recv_size)
 325 {
 326         uint32_t output_reg = intel_dp->output_reg;
 327         struct drm_device *dev = intel_dp->base.base.dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         uint32_t ch_ctl = output_reg + 0x10;
 330         uint32_t ch_data = ch_ctl + 4;
 331         int i;
 332         int recv_bytes;
 333         uint32_t status;
 334         uint32_t aux_clock_divider;
 335         int try, precharge;
 336
 337         intel_dp_check_edp(intel_dp);
 338         /* The clock divider is based off the hrawclk,
 339          * and would like to run at 2MHz. So, take the
 340          * hrawclk value and divide by 2 and use that
 341          *
 342          * Note that PCH attached eDP panels should use a 125MHz input
 343          * clock divider.
 344          */
 345         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 346                 if (IS_GEN6(dev))
 347                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 348                 else
 349                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 350         } else if (HAS_PCH_SPLIT(dev))
 351                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 352         else
 353                 aux_clock_divider = intel_hrawclk(dev) / 2;
 354
 355         if (IS_GEN6(dev))
 356                 precharge = 3;
 357         else
 358                 precharge = 5;
 359
 360         /* Try to wait for any previous AUX channel activity */
 361         for (try = 0; try < 3; try++) {
 362                 status = I915_READ(ch_ctl);
 363                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 364                         break;
 365                 msleep(1);
 366         }
 367
 368         if (try == 3) {
 369                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 370                      I915_READ(ch_ctl));
 371                 return -EBUSY;
 372         }
 373
 374         /* Must try at least 3 times according to DP spec */
 375         for (try = 0; try < 5; try++) {
 376                 /* Load the send data into the aux channel data registers */
 377                 for (i = 0; i < send_bytes; i += 4)
 378                         I915_WRITE(ch_data + i,
 379                                    pack_aux(send + i, send_bytes - i));
 380
 381                 /* Send the command and wait for it to complete */
 382                 I915_WRITE(ch_ctl,
 383                            DP_AUX_CH_CTL_SEND_BUSY |
 384                            DP_AUX_CH_CTL_TIME_OUT_400us |
 385                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 386                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 387                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 388                            DP_AUX_CH_CTL_DONE |
 389                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 390                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 391                 for (;;) {
 392                         status = I915_READ(ch_ctl);
 393                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 394                                 break;
 395                         udelay(100);
 396                 }
 397
 398                 /* Clear done status and any errors */
 399                 I915_WRITE(ch_ctl,
 400                            status |
 401                            DP_AUX_CH_CTL_DONE |
 402                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 403                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 404                 if (status & DP_AUX_CH_CTL_DONE)
 405                         break;
 406         }
 407
 408         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 409                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 410                 return -EBUSY;
 411         }
 412
 413         /* Check for timeout or receive error.
 414          * Timeouts occur when the sink is not connected
 415          */
 416         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 417                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 418                 return -EIO;
 419         }
 420
 421         /* Timeouts occur when the device isn't connected, so they're
 422          * "normal" -- don't fill the kernel log with these */
 423         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 424                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 425                 return -ETIMEDOUT;
 426         }
 427
 428         /* Unload any bytes sent back from the other side */
 429         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 430                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 431         if (recv_bytes > recv_size)
 432                 recv_bytes = recv_size;
 433
 434         for (i = 0; i < recv_bytes; i += 4)
 435                 unpack_aux(I915_READ(ch_data + i),
 436                            recv + i, recv_bytes - i);
 437
 438         return recv_bytes;
 439 }
 440
 441 /* Write data to the aux channel in native mode */
 442 static int
 443 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 444                           uint16_t address, uint8_t *send, int send_bytes)
 445 {
 446         int ret;
 447         uint8_t msg[20];
 448         int msg_bytes;
 449         uint8_t ack;
 450
 451         intel_dp_check_edp(intel_dp);
 452         if (send_bytes > 16)
 453                 return -1;
 454         msg[0] = AUX_NATIVE_WRITE << 4;
 455         msg[1] = address >> 8;
 456         msg[2] = address & 0xff;
 457         msg[3] = send_bytes - 1;
 458         memcpy(&msg[4], send, send_bytes);
 459         msg_bytes = send_bytes + 4;
 460         for (;;) {
 461                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 462                 if (ret < 0)
 463                         return ret;
 464                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 465                         break;
 466                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 467                         udelay(100);
 468                 else
 469                         return -EIO;
 470         }
 471         return send_bytes;
 472 }
 473
 474 /* Write a single byte to the aux channel in native mode */
 475 static int
 476 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 477                             uint16_t address, uint8_t byte)
 478 {
 479         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 480 }
 481
 482 /* read bytes from a native aux channel */
 483 static int
 484 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 485                          uint16_t address, uint8_t *recv, int recv_bytes)
 486 {
 487         uint8_t msg[4];
 488         int msg_bytes;
 489         uint8_t reply[20];
 490         int reply_bytes;
 491         uint8_t ack;
 492         int ret;
 493
 494         intel_dp_check_edp(intel_dp);
 495         msg[0] = AUX_NATIVE_READ << 4;
 496         msg[1] = address >> 8;
 497         msg[2] = address & 0xff;
 498         msg[3] = recv_bytes - 1;
 499
 500         msg_bytes = 4;
 501         reply_bytes = recv_bytes + 1;
 502
 503         for (;;) {
 504                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 505                                       reply, reply_bytes);
 506                 if (ret == 0)
 507                         return -EPROTO;
 508                 if (ret < 0)
 509                         return ret;
 510                 ack = reply[0];
 511                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 512                         memcpy(recv, reply + 1, ret - 1);
 513                         return ret - 1;
 514                 }
 515                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 516                         udelay(100);
 517                 else
 518                         return -EIO;
 519         }
 520 }
 521
 522 static int
 523 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 524                     uint8_t write_byte, uint8_t *read_byte)
 525 {
 526         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 527         struct intel_dp *intel_dp = container_of(adapter,
 528                                                 struct intel_dp,
 529                                                 adapter);
 530         uint16_t address = algo_data->address;
 531         uint8_t msg[5];
 532         uint8_t reply[2];
 533         unsigned retry;
 534         int msg_bytes;
 535         int reply_bytes;
 536         int ret;
 537
 538         intel_dp_check_edp(intel_dp);
 539         /* Set up the command byte */
 540         if (mode & MODE_I2C_READ)
 541                 msg[0] = AUX_I2C_READ << 4;
 542         else
 543                 msg[0] = AUX_I2C_WRITE << 4;
 544
 545         if (!(mode & MODE_I2C_STOP))
 546                 msg[0] |= AUX_I2C_MOT << 4;
 547
 548         msg[1] = address >> 8;
 549         msg[2] = address;
 550
 551         switch (mode) {
 552         case MODE_I2C_WRITE:
 553                 msg[3] = 0;
 554                 msg[4] = write_byte;
 555                 msg_bytes = 5;
 556                 reply_bytes = 1;
 557                 break;
 558         case MODE_I2C_READ:
 559                 msg[3] = 0;
 560                 msg_bytes = 4;
 561                 reply_bytes = 2;
 562                 break;
 563         default:
 564                 msg_bytes = 3;
 565                 reply_bytes = 1;
 566                 break;
 567         }
 568
 569         for (retry = 0; retry < 5; retry++) {
 570                 ret = intel_dp_aux_ch(intel_dp,
 571                                       msg, msg_bytes,
 572                                       reply, reply_bytes);
 573                 if (ret < 0) {
 574                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 575                         return ret;
 576                 }
 577
 578                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 579                 case AUX_NATIVE_REPLY_ACK:
 580                         /* I2C-over-AUX Reply field is only valid
 581                          * when paired with AUX ACK.
 582                          */
 583                         break;
 584                 case AUX_NATIVE_REPLY_NACK:
 585                         DRM_DEBUG_KMS("aux_ch native nack\n");
 586                         return -EREMOTEIO;
 587                 case AUX_NATIVE_REPLY_DEFER:
 588                         udelay(100);
 589                         continue;
 590                 default:
 591                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 592                                   reply[0]);
 593                         return -EREMOTEIO;
 594                 }
 595
 596                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 597                 case AUX_I2C_REPLY_ACK:
 598                         if (mode == MODE_I2C_READ) {
 599                                 *read_byte = reply[1];
 600                         }
 601                         return reply_bytes - 1;
 602                 case AUX_I2C_REPLY_NACK:
 603                         DRM_DEBUG_KMS("aux_i2c nack\n");
 604                         return -EREMOTEIO;
 605                 case AUX_I2C_REPLY_DEFER:
 606                         DRM_DEBUG_KMS("aux_i2c defer\n");
 607                         udelay(100);
 608                         break;
 609                 default:
 610                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 611                         return -EREMOTEIO;
 612                 }
 613         }
 614
 615         DRM_ERROR("too many retries, giving up\n");
 616         return -EREMOTEIO;
 617 }
 618
 619 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 620 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 621
 622 static int
 623 intel_dp_i2c_init(struct intel_dp *intel_dp,
 624                   struct intel_connector *intel_connector, const char *name)
 625 {
 626         int     ret;
 627
 628         DRM_DEBUG_KMS("i2c_init %s\n", name);
 629         intel_dp->algo.running = false;
 630         intel_dp->algo.address = 0;
 631         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 632
 633         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 634         intel_dp->adapter.owner = THIS_MODULE;
 635         intel_dp->adapter.class = I2C_CLASS_DDC;
 636         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 637         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 638         intel_dp->adapter.algo_data = &intel_dp->algo;
 639         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 640
 641         ironlake_edp_panel_vdd_on(intel_dp);
 642         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 643         ironlake_edp_panel_vdd_off(intel_dp, false);
 644         return ret;
 645 }
 646
 647 static bool
 648 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 649                     struct drm_display_mode *adjusted_mode)
 650 {
 651         struct drm_device *dev = encoder->dev;
 652         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 653         int lane_count, clock;
 654         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 655         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 656         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 657
 658         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 659                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 660                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 661                                         mode, adjusted_mode);
 662                 /*
 663                  * the mode->clock is used to calculate the Data&Link M/N
 664                  * of the pipe. For the eDP the fixed clock should be used.
 665                  */
 666                 mode->clock = intel_dp->panel_fixed_mode->clock;
 667         }
 668
 669         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 670                 for (clock = 0; clock <= max_clock; clock++) {
 671                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 672
 673                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 674                                         <= link_avail) {
 675                                 intel_dp->link_bw = bws[clock];
 676                                 intel_dp->lane_count = lane_count;
 677                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 678                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 679                                                 "count %d clock %d\n",
 680                                        intel_dp->link_bw, intel_dp->lane_count,
 681                                        adjusted_mode->clock);
 682                                 return true;
 683                         }
 684                 }
 685         }
 686
 687         if (is_edp(intel_dp)) {
 688                 /* okay we failed just pick the highest */
 689                 intel_dp->lane_count = max_lane_count;
 690                 intel_dp->link_bw = bws[max_clock];
 691                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 692                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 693                               "count %d clock %d\n",
 694                               intel_dp->link_bw, intel_dp->lane_count,
 695                               adjusted_mode->clock);
 696
 697                 return true;
 698         }
 699
 700         return false;
 701 }
 702
 703 struct intel_dp_m_n {
 704         uint32_t        tu;
 705         uint32_t        gmch_m;
 706         uint32_t        gmch_n;
 707         uint32_t        link_m;
 708         uint32_t        link_n;
 709 };
 710
 711 static void
 712 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 713 {
 714         while (*num > 0xffffff || *den > 0xffffff) {
 715                 *num >>= 1;
 716                 *den >>= 1;
 717         }
 718 }
 719
 720 static void
 721 intel_dp_compute_m_n(int bpp,
 722                      int nlanes,
 723                      int pixel_clock,
 724                      int link_clock,
 725                      struct intel_dp_m_n *m_n)
 726 {
 727         m_n->tu = 64;
 728         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 729         m_n->gmch_n = link_clock * nlanes;
 730         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 731         m_n->link_m = pixel_clock;
 732         m_n->link_n = link_clock;
 733         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 734 }
 735
 736 void
 737 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 738                  struct drm_display_mode *adjusted_mode)
 739 {
 740         struct drm_device *dev = crtc->dev;
 741         struct drm_mode_config *mode_config = &dev->mode_config;
 742         struct drm_encoder *encoder;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 745         int lane_count = 4;
 746         struct intel_dp_m_n m_n;
 747         int pipe = intel_crtc->pipe;
 748
 749         /*
 750          * Find the lane count in the intel_encoder private
 751          */
 752         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 753                 struct intel_dp *intel_dp;
 754
 755                 if (encoder->crtc != crtc)
 756                         continue;
 757
 758                 intel_dp = enc_to_intel_dp(encoder);
 759                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 760                         lane_count = intel_dp->lane_count;
 761                         break;
 762                 } else if (is_edp(intel_dp)) {
 763                         lane_count = dev_priv->edp.lanes;
 764                         break;
 765                 }
 766         }
 767
 768         /*
 769          * Compute the GMCH and Link ratios. The '3' here is
 770          * the number of bytes_per_pixel post-LUT, which we always
 771          * set up for 8-bits of R/G/B, or 3 bytes total.
 772          */
 773         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 774                              mode->clock, adjusted_mode->clock, &m_n);
 775
 776         if (HAS_PCH_SPLIT(dev)) {
 777                 I915_WRITE(TRANSDATA_M1(pipe),
 778                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 779                            m_n.gmch_m);
 780                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 781                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 782                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 783         } else {
 784                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 785                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 786                            m_n.gmch_m);
 787                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 788                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 789                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 790         }
 791 }
 792
 793 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 794 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 795
 796 static void
 797 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 798                   struct drm_display_mode *adjusted_mode)
 799 {
 800         struct drm_device *dev = encoder->dev;
 801         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 802         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 804
 805         /* Turn on the eDP PLL if needed */
 806         if (is_edp(intel_dp)) {
 807                 if (!is_pch_edp(intel_dp))
 808                         ironlake_edp_pll_on(encoder);
 809                 else
 810                         ironlake_edp_pll_off(encoder);
 811         }
 812
 813         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 814         intel_dp->DP |= intel_dp->color_range;
 815
 816         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 817                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 818         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 819                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 820
 821         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 822                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 823         else
 824                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 825
 826         switch (intel_dp->lane_count) {
 827         case 1:
 828                 intel_dp->DP |= DP_PORT_WIDTH_1;
 829                 break;
 830         case 2:
 831                 intel_dp->DP |= DP_PORT_WIDTH_2;
 832                 break;
 833         case 4:
 834                 intel_dp->DP |= DP_PORT_WIDTH_4;
 835                 break;
 836         }
 837         if (intel_dp->has_audio) {
 838                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 839                                  pipe_name(intel_crtc->pipe));
 840                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 841                 intel_write_eld(encoder, adjusted_mode);
 842         }
 843
 844         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 845         intel_dp->link_configuration[0] = intel_dp->link_bw;
 846         intel_dp->link_configuration[1] = intel_dp->lane_count;
 847         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 848
 849         /*
 850          * Check for DPCD version > 1.1 and enhanced framing support
 851          */
 852         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 853             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 854                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 855                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 856         }
 857
 858         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 859         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 860                 intel_dp->DP |= DP_PIPEB_SELECT;
 861
 862         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 863                 /* don't miss out required setting for eDP */
 864                 intel_dp->DP |= DP_PLL_ENABLE;
 865                 if (adjusted_mode->clock < 200000)
 866                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 867                 else
 868                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 869         }
 870 }
 871
 872 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 873 {
 874         unsigned long   off_time;
 875         unsigned long   delay;
 876
 877         DRM_DEBUG_KMS("Wait for panel power off time\n");
 878
 879         if (ironlake_edp_have_panel_power(intel_dp) ||
 880             ironlake_edp_have_panel_vdd(intel_dp))
 881         {
 882                 DRM_DEBUG_KMS("Panel still on, no delay needed\n");
 883                 return;
 884         }
 885
 886         off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
 887         if (time_after(jiffies, off_time)) {
 888                 DRM_DEBUG_KMS("Time already passed");
 889                 return;
 890         }
 891         delay = jiffies_to_msecs(off_time - jiffies);
 892         if (delay > intel_dp->panel_power_down_delay)
 893                 delay = intel_dp->panel_power_down_delay;
 894         DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
 895         msleep(delay);
 896 }
 897
 898 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 899 {
 900         struct drm_device *dev = intel_dp->base.base.dev;
 901         struct drm_i915_private *dev_priv = dev->dev_private;
 902         u32 pp;
 903
 904         if (!is_edp(intel_dp))
 905                 return;
 906         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 907
 908         WARN(intel_dp->want_panel_vdd,
 909              "eDP VDD already requested on\n");
 910
 911         intel_dp->want_panel_vdd = true;
 912         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 913                 DRM_DEBUG_KMS("eDP VDD already on\n");
 914                 return;
 915         }
 916
 917         ironlake_wait_panel_off(intel_dp);
 918         pp = I915_READ(PCH_PP_CONTROL);
 919         pp &= ~PANEL_UNLOCK_MASK;
 920         pp |= PANEL_UNLOCK_REGS;
 921         pp |= EDP_FORCE_VDD;
 922         I915_WRITE(PCH_PP_CONTROL, pp);
 923         POSTING_READ(PCH_PP_CONTROL);
 924         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 925                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 926
 927         /*
 928          * If the panel wasn't on, delay before accessing aux channel
 929          */
 930         if (!ironlake_edp_have_panel_power(intel_dp)) {
 931                 DRM_DEBUG_KMS("eDP was not running\n");
 932                 msleep(intel_dp->panel_power_up_delay);
 933         }
 934 }
 935
 936 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 937 {
 938         struct drm_device *dev = intel_dp->base.base.dev;
 939         struct drm_i915_private *dev_priv = dev->dev_private;
 940         u32 pp;
 941
 942         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
 943                 pp = I915_READ(PCH_PP_CONTROL);
 944                 pp &= ~PANEL_UNLOCK_MASK;
 945                 pp |= PANEL_UNLOCK_REGS;
 946                 pp &= ~EDP_FORCE_VDD;
 947                 I915_WRITE(PCH_PP_CONTROL, pp);
 948                 POSTING_READ(PCH_PP_CONTROL);
 949
 950                 /* Make sure sequencer is idle before allowing subsequent activity */
 951                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 952                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 953                 intel_dp->panel_off_jiffies = jiffies;
 954         }
 955 }
 956
 957 static void ironlake_panel_vdd_work(struct work_struct *__work)
 958 {
 959         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
 960                                                  struct intel_dp, panel_vdd_work);
 961         struct drm_device *dev = intel_dp->base.base.dev;
 962
 963         mutex_lock(&dev->struct_mutex);
 964         ironlake_panel_vdd_off_sync(intel_dp);
 965         mutex_unlock(&dev->struct_mutex);
 966 }
 967
 968 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 969 {
 970         if (!is_edp(intel_dp))
 971                 return;
 972
 973         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
 974         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
 975
 976         intel_dp->want_panel_vdd = false;
 977
 978         if (sync) {
 979                 ironlake_panel_vdd_off_sync(intel_dp);
 980         } else {
 981                 /*
 982                  * Queue the timer to fire a long
 983                  * time from now (relative to the power down delay)
 984                  * to keep the panel power up across a sequence of operations
 985                  */
 986                 schedule_delayed_work(&intel_dp->panel_vdd_work,
 987                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 988         }
 989 }
 990
 991 /* Returns true if the panel was already on when called */
 992 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 993 {
 994         struct drm_device *dev = intel_dp->base.base.dev;
 995         struct drm_i915_private *dev_priv = dev->dev_private;
 996         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 997
 998         if (!is_edp(intel_dp))
 999                 return;
1000         if (ironlake_edp_have_panel_power(intel_dp))
1001                 return;
1002
1003         ironlake_wait_panel_off(intel_dp);
1004         pp = I915_READ(PCH_PP_CONTROL);
1005         pp &= ~PANEL_UNLOCK_MASK;
1006         pp |= PANEL_UNLOCK_REGS;
1007
1008         if (IS_GEN5(dev)) {
1009                 /* ILK workaround: disable reset around power sequence */
1010                 pp &= ~PANEL_POWER_RESET;
1011                 I915_WRITE(PCH_PP_CONTROL, pp);
1012                 POSTING_READ(PCH_PP_CONTROL);
1013         }
1014
1015         pp |= POWER_TARGET_ON;
1016         I915_WRITE(PCH_PP_CONTROL, pp);
1017         POSTING_READ(PCH_PP_CONTROL);
1018
1019         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
1020                      5000))
1021                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
1022                           I915_READ(PCH_PP_STATUS));
1023
1024         if (IS_GEN5(dev)) {
1025                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1026                 I915_WRITE(PCH_PP_CONTROL, pp);
1027                 POSTING_READ(PCH_PP_CONTROL);
1028         }
1029 }
1030
1031 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
1032 {
1033         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1034         struct drm_device *dev = encoder->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
1037                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
1038
1039         if (!is_edp(intel_dp))
1040                 return;
1041         pp = I915_READ(PCH_PP_CONTROL);
1042         pp &= ~PANEL_UNLOCK_MASK;
1043         pp |= PANEL_UNLOCK_REGS;
1044
1045         if (IS_GEN5(dev)) {
1046                 /* ILK workaround: disable reset around power sequence */
1047                 pp &= ~PANEL_POWER_RESET;
1048                 I915_WRITE(PCH_PP_CONTROL, pp);
1049                 POSTING_READ(PCH_PP_CONTROL);
1050         }
1051
1052         intel_dp->panel_off_jiffies = jiffies;
1053
1054         if (IS_GEN5(dev)) {
1055                 pp &= ~POWER_TARGET_ON;
1056                 I915_WRITE(PCH_PP_CONTROL, pp);
1057                 POSTING_READ(PCH_PP_CONTROL);
1058                 pp &= ~POWER_TARGET_ON;
1059                 I915_WRITE(PCH_PP_CONTROL, pp);
1060                 POSTING_READ(PCH_PP_CONTROL);
1061                 msleep(intel_dp->panel_power_cycle_delay);
1062
1063                 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
1064                         DRM_ERROR("panel off wait timed out: 0x%08x\n",
1065                                   I915_READ(PCH_PP_STATUS));
1066
1067                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1068                 I915_WRITE(PCH_PP_CONTROL, pp);
1069                 POSTING_READ(PCH_PP_CONTROL);
1070         }
1071 }
1072
1073 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1074 {
1075         struct drm_device *dev = intel_dp->base.base.dev;
1076         struct drm_i915_private *dev_priv = dev->dev_private;
1077         u32 pp;
1078
1079         if (!is_edp(intel_dp))
1080                 return;
1081
1082         DRM_DEBUG_KMS("\n");
1083         /*
1084          * If we enable the backlight right away following a panel power
1085          * on, we may see slight flicker as the panel syncs with the eDP
1086          * link.  So delay a bit to make sure the image is solid before
1087          * allowing it to appear.
1088          */
1089         msleep(intel_dp->backlight_on_delay);
1090         pp = I915_READ(PCH_PP_CONTROL);
1091         pp &= ~PANEL_UNLOCK_MASK;
1092         pp |= PANEL_UNLOCK_REGS;
1093         pp |= EDP_BLC_ENABLE;
1094         I915_WRITE(PCH_PP_CONTROL, pp);
1095         POSTING_READ(PCH_PP_CONTROL);
1096 }
1097
1098 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1099 {
1100         struct drm_device *dev = intel_dp->base.base.dev;
1101         struct drm_i915_private *dev_priv = dev->dev_private;
1102         u32 pp;
1103
1104         if (!is_edp(intel_dp))
1105                 return;
1106
1107         DRM_DEBUG_KMS("\n");
1108         pp = I915_READ(PCH_PP_CONTROL);
1109         pp &= ~PANEL_UNLOCK_MASK;
1110         pp |= PANEL_UNLOCK_REGS;
1111         pp &= ~EDP_BLC_ENABLE;
1112         I915_WRITE(PCH_PP_CONTROL, pp);
1113         POSTING_READ(PCH_PP_CONTROL);
1114         msleep(intel_dp->backlight_off_delay);
1115 }
1116
1117 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1118 {
1119         struct drm_device *dev = encoder->dev;
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 dpa_ctl;
1122
1123         DRM_DEBUG_KMS("\n");
1124         dpa_ctl = I915_READ(DP_A);
1125         dpa_ctl |= DP_PLL_ENABLE;
1126         I915_WRITE(DP_A, dpa_ctl);
1127         POSTING_READ(DP_A);
1128         udelay(200);
1129 }
1130
1131 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1132 {
1133         struct drm_device *dev = encoder->dev;
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         u32 dpa_ctl;
1136
1137         dpa_ctl = I915_READ(DP_A);
1138         dpa_ctl &= ~DP_PLL_ENABLE;
1139         I915_WRITE(DP_A, dpa_ctl);
1140         POSTING_READ(DP_A);
1141         udelay(200);
1142 }
1143
1144 /* If the sink supports it, try to set the power state appropriately */
1145 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1146 {
1147         int ret, i;
1148
1149         /* Should have a valid DPCD by this point */
1150         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1151                 return;
1152
1153         if (mode != DRM_MODE_DPMS_ON) {
1154                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1155                                                   DP_SET_POWER_D3);
1156                 if (ret != 1)
1157                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1158         } else {
1159                 /*
1160                  * When turning on, we need to retry for 1ms to give the sink
1161                  * time to wake up.
1162                  */
1163                 for (i = 0; i < 3; i++) {
1164                         ret = intel_dp_aux_native_write_1(intel_dp,
1165                                                           DP_SET_POWER,
1166                                                           DP_SET_POWER_D0);
1167                         if (ret == 1)
1168                                 break;
1169                         msleep(1);
1170                 }
1171         }
1172 }
1173
1174 static void intel_dp_prepare(struct drm_encoder *encoder)
1175 {
1176         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1177
1178         /* Wake up the sink first */
1179         ironlake_edp_panel_vdd_on(intel_dp);
1180         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1181         ironlake_edp_panel_vdd_off(intel_dp, false);
1182
1183         /* Make sure the panel is off before trying to
1184          * change the mode
1185          */
1186         ironlake_edp_backlight_off(intel_dp);
1187         intel_dp_link_down(intel_dp);
1188         ironlake_edp_panel_off(encoder);
1189 }
1190
1191 static void intel_dp_commit(struct drm_encoder *encoder)
1192 {
1193         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1194
1195         ironlake_edp_panel_vdd_on(intel_dp);
1196         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1197         intel_dp_start_link_train(intel_dp);
1198         ironlake_edp_panel_on(intel_dp);
1199         ironlake_edp_panel_vdd_off(intel_dp, true);
1200
1201         intel_dp_complete_link_train(intel_dp);
1202         ironlake_edp_backlight_on(intel_dp);
1203
1204         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1205 }
1206
1207 static void
1208 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1209 {
1210         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1211         struct drm_device *dev = encoder->dev;
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1214
1215         if (mode != DRM_MODE_DPMS_ON) {
1216                 ironlake_edp_panel_vdd_on(intel_dp);
1217                 if (is_edp(intel_dp))
1218                         ironlake_edp_backlight_off(intel_dp);
1219                 intel_dp_sink_dpms(intel_dp, mode);
1220                 intel_dp_link_down(intel_dp);
1221                 ironlake_edp_panel_off(encoder);
1222                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1223                         ironlake_edp_pll_off(encoder);
1224                 ironlake_edp_panel_vdd_off(intel_dp, false);
1225         } else {
1226                 ironlake_edp_panel_vdd_on(intel_dp);
1227                 intel_dp_sink_dpms(intel_dp, mode);
1228                 if (!(dp_reg & DP_PORT_EN)) {
1229                         intel_dp_start_link_train(intel_dp);
1230                         ironlake_edp_panel_on(intel_dp);
1231                         ironlake_edp_panel_vdd_off(intel_dp, true);
1232                         intel_dp_complete_link_train(intel_dp);
1233                         ironlake_edp_backlight_on(intel_dp);
1234                 } else
1235                         ironlake_edp_panel_vdd_off(intel_dp, false);
1236                 ironlake_edp_backlight_on(intel_dp);
1237         }
1238         intel_dp->dpms_mode = mode;
1239 }
1240
1241 /*
1242  * Native read with retry for link status and receiver capability reads for
1243  * cases where the sink may still be asleep.
1244  */
1245 static bool
1246 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1247                                uint8_t *recv, int recv_bytes)
1248 {
1249         int ret, i;
1250
1251         /*
1252          * Sinks are *supposed* to come up within 1ms from an off state,
1253          * but we're also supposed to retry 3 times per the spec.
1254          */
1255         for (i = 0; i < 3; i++) {
1256                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1257                                                recv_bytes);
1258                 if (ret == recv_bytes)
1259                         return true;
1260                 msleep(1);
1261         }
1262
1263         return false;
1264 }
1265
1266 /*
1267  * Fetch AUX CH registers 0x202 - 0x207 which contain
1268  * link status information
1269  */
1270 static bool
1271 intel_dp_get_link_status(struct intel_dp *intel_dp)
1272 {
1273         return intel_dp_aux_native_read_retry(intel_dp,
1274                                               DP_LANE0_1_STATUS,
1275                                               intel_dp->link_status,
1276                                               DP_LINK_STATUS_SIZE);
1277 }
1278
1279 static uint8_t
1280 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1281                      int r)
1282 {
1283         return link_status[r - DP_LANE0_1_STATUS];
1284 }
1285
1286 static uint8_t
1287 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1288                                  int lane)
1289 {
1290         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1291         int         s = ((lane & 1) ?
1292                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1293                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1294         uint8_t l = intel_dp_link_status(link_status, i);
1295
1296         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1297 }
1298
1299 static uint8_t
1300 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1301                                       int lane)
1302 {
1303         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1304         int         s = ((lane & 1) ?
1305                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1306                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1307         uint8_t l = intel_dp_link_status(link_status, i);
1308
1309         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1310 }
1311
1312
1313 #if 0
1314 static char     *voltage_names[] = {
1315         "0.4V", "0.6V", "0.8V", "1.2V"
1316 };
1317 static char     *pre_emph_names[] = {
1318         "0dB", "3.5dB", "6dB", "9.5dB"
1319 };
1320 static char     *link_train_names[] = {
1321         "pattern 1", "pattern 2", "idle", "off"
1322 };
1323 #endif
1324
1325 /*
1326  * These are source-specific values; current Intel hardware supports
1327  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1328  */
1329 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1330
1331 static uint8_t
1332 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1333 {
1334         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1335         case DP_TRAIN_VOLTAGE_SWING_400:
1336                 return DP_TRAIN_PRE_EMPHASIS_6;
1337         case DP_TRAIN_VOLTAGE_SWING_600:
1338                 return DP_TRAIN_PRE_EMPHASIS_6;
1339         case DP_TRAIN_VOLTAGE_SWING_800:
1340                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1341         case DP_TRAIN_VOLTAGE_SWING_1200:
1342         default:
1343                 return DP_TRAIN_PRE_EMPHASIS_0;
1344         }
1345 }
1346
1347 static void
1348 intel_get_adjust_train(struct intel_dp *intel_dp)
1349 {
1350         uint8_t v = 0;
1351         uint8_t p = 0;
1352         int lane;
1353
1354         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1355                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1356                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1357
1358                 if (this_v > v)
1359                         v = this_v;
1360                 if (this_p > p)
1361                         p = this_p;
1362         }
1363
1364         if (v >= I830_DP_VOLTAGE_MAX)
1365                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1366
1367         if (p >= intel_dp_pre_emphasis_max(v))
1368                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1369
1370         for (lane = 0; lane < 4; lane++)
1371                 intel_dp->train_set[lane] = v | p;
1372 }
1373
1374 static uint32_t
1375 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1376 {
1377         uint32_t        signal_levels = 0;
1378
1379         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1380         case DP_TRAIN_VOLTAGE_SWING_400:
1381         default:
1382                 signal_levels |= DP_VOLTAGE_0_4;
1383                 break;
1384         case DP_TRAIN_VOLTAGE_SWING_600:
1385                 signal_levels |= DP_VOLTAGE_0_6;
1386                 break;
1387         case DP_TRAIN_VOLTAGE_SWING_800:
1388                 signal_levels |= DP_VOLTAGE_0_8;
1389                 break;
1390         case DP_TRAIN_VOLTAGE_SWING_1200:
1391                 signal_levels |= DP_VOLTAGE_1_2;
1392                 break;
1393         }
1394         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1395         case DP_TRAIN_PRE_EMPHASIS_0:
1396         default:
1397                 signal_levels |= DP_PRE_EMPHASIS_0;
1398                 break;
1399         case DP_TRAIN_PRE_EMPHASIS_3_5:
1400                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1401                 break;
1402         case DP_TRAIN_PRE_EMPHASIS_6:
1403                 signal_levels |= DP_PRE_EMPHASIS_6;
1404                 break;
1405         case DP_TRAIN_PRE_EMPHASIS_9_5:
1406                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1407                 break;
1408         }
1409         return signal_levels;
1410 }
1411
1412 /* Gen6's DP voltage swing and pre-emphasis control */
1413 static uint32_t
1414 intel_gen6_edp_signal_levels(uint8_t train_set)
1415 {
1416         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1417                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1418         switch (signal_levels) {
1419         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1420         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1421                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1422         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1423                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1424         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1425         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1426                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1427         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1428         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1429                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1430         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1431         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1432                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1433         default:
1434                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1435                               "0x%x\n", signal_levels);
1436                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1437         }
1438 }
1439
1440 static uint8_t
1441 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1442                       int lane)
1443 {
1444         int i = DP_LANE0_1_STATUS + (lane >> 1);
1445         int s = (lane & 1) * 4;
1446         uint8_t l = intel_dp_link_status(link_status, i);
1447
1448         return (l >> s) & 0xf;
1449 }
1450
1451 /* Check for clock recovery is done on all channels */
1452 static bool
1453 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1454 {
1455         int lane;
1456         uint8_t lane_status;
1457
1458         for (lane = 0; lane < lane_count; lane++) {
1459                 lane_status = intel_get_lane_status(link_status, lane);
1460                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1461                         return false;
1462         }
1463         return true;
1464 }
1465
1466 /* Check to see if channel eq is done on all channels */
1467 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1468                          DP_LANE_CHANNEL_EQ_DONE|\
1469                          DP_LANE_SYMBOL_LOCKED)
1470 static bool
1471 intel_channel_eq_ok(struct intel_dp *intel_dp)
1472 {
1473         uint8_t lane_align;
1474         uint8_t lane_status;
1475         int lane;
1476
1477         lane_align = intel_dp_link_status(intel_dp->link_status,
1478                                           DP_LANE_ALIGN_STATUS_UPDATED);
1479         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1480                 return false;
1481         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1482                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1483                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1484                         return false;
1485         }
1486         return true;
1487 }
1488
1489 static bool
1490 intel_dp_set_link_train(struct intel_dp *intel_dp,
1491                         uint32_t dp_reg_value,
1492                         uint8_t dp_train_pat)
1493 {
1494         struct drm_device *dev = intel_dp->base.base.dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         int ret;
1497
1498         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1499         POSTING_READ(intel_dp->output_reg);
1500
1501         intel_dp_aux_native_write_1(intel_dp,
1502                                     DP_TRAINING_PATTERN_SET,
1503                                     dp_train_pat);
1504
1505         ret = intel_dp_aux_native_write(intel_dp,
1506                                         DP_TRAINING_LANE0_SET,
1507                                         intel_dp->train_set, 4);
1508         if (ret != 4)
1509                 return false;
1510
1511         return true;
1512 }
1513
1514 /* Enable corresponding port and start training pattern 1 */
1515 static void
1516 intel_dp_start_link_train(struct intel_dp *intel_dp)
1517 {
1518         struct drm_device *dev = intel_dp->base.base.dev;
1519         struct drm_i915_private *dev_priv = dev->dev_private;
1520         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1521         int i;
1522         uint8_t voltage;
1523         bool clock_recovery = false;
1524         int tries;
1525         u32 reg;
1526         uint32_t DP = intel_dp->DP;
1527
1528         /*
1529          * On CPT we have to enable the port in training pattern 1, which
1530          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1531          * the port and wait for it to become active.
1532          */
1533         if (!HAS_PCH_CPT(dev)) {
1534                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1535                 POSTING_READ(intel_dp->output_reg);
1536                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1537         }
1538
1539         /* Write the link configuration data */
1540         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1541                                   intel_dp->link_configuration,
1542                                   DP_LINK_CONFIGURATION_SIZE);
1543
1544         DP |= DP_PORT_EN;
1545         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1546                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1547         else
1548                 DP &= ~DP_LINK_TRAIN_MASK;
1549         memset(intel_dp->train_set, 0, 4);
1550         voltage = 0xff;
1551         tries = 0;
1552         clock_recovery = false;
1553         for (;;) {
1554                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1555                 uint32_t    signal_levels;
1556                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1557                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1558                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1559                 } else {
1560                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1561                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1562                 }
1563
1564                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1565                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1566                 else
1567                         reg = DP | DP_LINK_TRAIN_PAT_1;
1568
1569                 if (!intel_dp_set_link_train(intel_dp, reg,
1570                                              DP_TRAINING_PATTERN_1 |
1571                                              DP_LINK_SCRAMBLING_DISABLE))
1572                         break;
1573                 /* Set training pattern 1 */
1574
1575                 udelay(100);
1576                 if (!intel_dp_get_link_status(intel_dp))
1577                         break;
1578
1579                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1580                         clock_recovery = true;
1581                         break;
1582                 }
1583
1584                 /* Check to see if we've tried the max voltage */
1585                 for (i = 0; i < intel_dp->lane_count; i++)
1586                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1587                                 break;
1588                 if (i == intel_dp->lane_count)
1589                         break;
1590
1591                 /* Check to see if we've tried the same voltage 5 times */
1592                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1593                         ++tries;
1594                         if (tries == 5)
1595                                 break;
1596                 } else
1597                         tries = 0;
1598                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1599
1600                 /* Compute new intel_dp->train_set as requested by target */
1601                 intel_get_adjust_train(intel_dp);
1602         }
1603
1604         intel_dp->DP = DP;
1605 }
1606
1607 static void
1608 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1609 {
1610         struct drm_device *dev = intel_dp->base.base.dev;
1611         struct drm_i915_private *dev_priv = dev->dev_private;
1612         bool channel_eq = false;
1613         int tries, cr_tries;
1614         u32 reg;
1615         uint32_t DP = intel_dp->DP;
1616
1617         /* channel equalization */
1618         tries = 0;
1619         cr_tries = 0;
1620         channel_eq = false;
1621         for (;;) {
1622                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1623                 uint32_t    signal_levels;
1624
1625                 if (cr_tries > 5) {
1626                         DRM_ERROR("failed to train DP, aborting\n");
1627                         intel_dp_link_down(intel_dp);
1628                         break;
1629                 }
1630
1631                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1632                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1633                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1634                 } else {
1635                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1636                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1637                 }
1638
1639                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1640                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1641                 else
1642                         reg = DP | DP_LINK_TRAIN_PAT_2;
1643
1644                 /* channel eq pattern */
1645                 if (!intel_dp_set_link_train(intel_dp, reg,
1646                                              DP_TRAINING_PATTERN_2 |
1647                                              DP_LINK_SCRAMBLING_DISABLE))
1648                         break;
1649
1650                 udelay(400);
1651                 if (!intel_dp_get_link_status(intel_dp))
1652                         break;
1653
1654                 /* Make sure clock is still ok */
1655                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1656                         intel_dp_start_link_train(intel_dp);
1657                         cr_tries++;
1658                         continue;
1659                 }
1660
1661                 if (intel_channel_eq_ok(intel_dp)) {
1662                         channel_eq = true;
1663                         break;
1664                 }
1665
1666                 /* Try 5 times, then try clock recovery if that fails */
1667                 if (tries > 5) {
1668                         intel_dp_link_down(intel_dp);
1669                         intel_dp_start_link_train(intel_dp);
1670                         tries = 0;
1671                         cr_tries++;
1672                         continue;
1673                 }
1674
1675                 /* Compute new intel_dp->train_set as requested by target */
1676                 intel_get_adjust_train(intel_dp);
1677                 ++tries;
1678         }
1679
1680         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1681                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1682         else
1683                 reg = DP | DP_LINK_TRAIN_OFF;
1684
1685         I915_WRITE(intel_dp->output_reg, reg);
1686         POSTING_READ(intel_dp->output_reg);
1687         intel_dp_aux_native_write_1(intel_dp,
1688                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1689 }
1690
1691 static void
1692 intel_dp_link_down(struct intel_dp *intel_dp)
1693 {
1694         struct drm_device *dev = intel_dp->base.base.dev;
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696         uint32_t DP = intel_dp->DP;
1697
1698         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1699                 return;
1700
1701         DRM_DEBUG_KMS("\n");
1702
1703         if (is_edp(intel_dp)) {
1704                 DP &= ~DP_PLL_ENABLE;
1705                 I915_WRITE(intel_dp->output_reg, DP);
1706                 POSTING_READ(intel_dp->output_reg);
1707                 udelay(100);
1708         }
1709
1710         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1711                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1712                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1713         } else {
1714                 DP &= ~DP_LINK_TRAIN_MASK;
1715                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1716         }
1717         POSTING_READ(intel_dp->output_reg);
1718
1719         msleep(17);
1720
1721         if (is_edp(intel_dp))
1722                 DP |= DP_LINK_TRAIN_OFF;
1723
1724         if (!HAS_PCH_CPT(dev) &&
1725             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1726                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1727
1728                 /* Hardware workaround: leaving our transcoder select
1729                  * set to transcoder B while it's off will prevent the
1730                  * corresponding HDMI output on transcoder A.
1731                  *
1732                  * Combine this with another hardware workaround:
1733                  * transcoder select bit can only be cleared while the
1734                  * port is enabled.
1735                  */
1736                 DP &= ~DP_PIPEB_SELECT;
1737                 I915_WRITE(intel_dp->output_reg, DP);
1738
1739                 /* Changes to enable or select take place the vblank
1740                  * after being written.
1741                  */
1742                 if (crtc == NULL) {
1743                         /* We can arrive here never having been attached
1744                          * to a CRTC, for instance, due to inheriting
1745                          * random state from the BIOS.
1746                          *
1747                          * If the pipe is not running, play safe and
1748                          * wait for the clocks to stabilise before
1749                          * continuing.
1750                          */
1751                         POSTING_READ(intel_dp->output_reg);
1752                         msleep(50);
1753                 } else
1754                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1755         }
1756
1757         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1758         POSTING_READ(intel_dp->output_reg);
1759         msleep(intel_dp->panel_power_down_delay);
1760 }
1761
1762 static bool
1763 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1764 {
1765         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1766                                            sizeof(intel_dp->dpcd)) &&
1767             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1768                 return true;
1769         }
1770
1771         return false;
1772 }
1773
1774 /*
1775  * According to DP spec
1776  * 5.1.2:
1777  *  1. Read DPCD
1778  *  2. Configure link according to Receiver Capabilities
1779  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1780  *  4. Check link status on receipt of hot-plug interrupt
1781  */
1782
1783 static void
1784 intel_dp_check_link_status(struct intel_dp *intel_dp)
1785 {
1786         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1787                 return;
1788
1789         if (!intel_dp->base.base.crtc)
1790                 return;
1791
1792         /* Try to read receiver status if the link appears to be up */
1793         if (!intel_dp_get_link_status(intel_dp)) {
1794                 intel_dp_link_down(intel_dp);
1795                 return;
1796         }
1797
1798         /* Now read the DPCD to see if it's actually running */
1799         if (!intel_dp_get_dpcd(intel_dp)) {
1800                 intel_dp_link_down(intel_dp);
1801                 return;
1802         }
1803
1804         if (!intel_channel_eq_ok(intel_dp)) {
1805                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1806                               drm_get_encoder_name(&intel_dp->base.base));
1807                 intel_dp_start_link_train(intel_dp);
1808                 intel_dp_complete_link_train(intel_dp);
1809         }
1810 }
1811
1812 static enum drm_connector_status
1813 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1814 {
1815         if (intel_dp_get_dpcd(intel_dp))
1816                 return connector_status_connected;
1817         return connector_status_disconnected;
1818 }
1819
1820 static enum drm_connector_status
1821 ironlake_dp_detect(struct intel_dp *intel_dp)
1822 {
1823         enum drm_connector_status status;
1824
1825         /* Can't disconnect eDP, but you can close the lid... */
1826         if (is_edp(intel_dp)) {
1827                 status = intel_panel_detect(intel_dp->base.base.dev);
1828                 if (status == connector_status_unknown)
1829                         status = connector_status_connected;
1830                 return status;
1831         }
1832
1833         return intel_dp_detect_dpcd(intel_dp);
1834 }
1835
1836 static enum drm_connector_status
1837 g4x_dp_detect(struct intel_dp *intel_dp)
1838 {
1839         struct drm_device *dev = intel_dp->base.base.dev;
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         uint32_t temp, bit;
1842
1843         switch (intel_dp->output_reg) {
1844         case DP_B:
1845                 bit = DPB_HOTPLUG_INT_STATUS;
1846                 break;
1847         case DP_C:
1848                 bit = DPC_HOTPLUG_INT_STATUS;
1849                 break;
1850         case DP_D:
1851                 bit = DPD_HOTPLUG_INT_STATUS;
1852                 break;
1853         default:
1854                 return connector_status_unknown;
1855         }
1856
1857         temp = I915_READ(PORT_HOTPLUG_STAT);
1858
1859         if ((temp & bit) == 0)
1860                 return connector_status_disconnected;
1861
1862         return intel_dp_detect_dpcd(intel_dp);
1863 }
1864
1865 static struct edid *
1866 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1867 {
1868         struct intel_dp *intel_dp = intel_attached_dp(connector);
1869         struct edid     *edid;
1870
1871         ironlake_edp_panel_vdd_on(intel_dp);
1872         edid = drm_get_edid(connector, adapter);
1873         ironlake_edp_panel_vdd_off(intel_dp, false);
1874         return edid;
1875 }
1876
1877 static int
1878 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1879 {
1880         struct intel_dp *intel_dp = intel_attached_dp(connector);
1881         int     ret;
1882
1883         ironlake_edp_panel_vdd_on(intel_dp);
1884         ret = intel_ddc_get_modes(connector, adapter);
1885         ironlake_edp_panel_vdd_off(intel_dp, false);
1886         return ret;
1887 }
1888
1889
1890 /**
1891  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1892  *
1893  * \return true if DP port is connected.
1894  * \return false if DP port is disconnected.
1895  */
1896 static enum drm_connector_status
1897 intel_dp_detect(struct drm_connector *connector, bool force)
1898 {
1899         struct intel_dp *intel_dp = intel_attached_dp(connector);
1900         struct drm_device *dev = intel_dp->base.base.dev;
1901         enum drm_connector_status status;
1902         struct edid *edid = NULL;
1903
1904         intel_dp->has_audio = false;
1905
1906         if (HAS_PCH_SPLIT(dev))
1907                 status = ironlake_dp_detect(intel_dp);
1908         else
1909                 status = g4x_dp_detect(intel_dp);
1910
1911         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1912                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1913                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1914                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1915
1916         if (status != connector_status_connected)
1917                 return status;
1918
1919         if (intel_dp->force_audio) {
1920                 intel_dp->has_audio = intel_dp->force_audio > 0;
1921         } else {
1922                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1923                 if (edid) {
1924                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1925                         connector->display_info.raw_edid = NULL;
1926                         kfree(edid);
1927                 }
1928         }
1929
1930         return connector_status_connected;
1931 }
1932
1933 static int intel_dp_get_modes(struct drm_connector *connector)
1934 {
1935         struct intel_dp *intel_dp = intel_attached_dp(connector);
1936         struct drm_device *dev = intel_dp->base.base.dev;
1937         struct drm_i915_private *dev_priv = dev->dev_private;
1938         int ret;
1939
1940         /* We should parse the EDID data and find out if it has an audio sink
1941          */
1942
1943         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1944         if (ret) {
1945                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
1946                         struct drm_display_mode *newmode;
1947                         list_for_each_entry(newmode, &connector->probed_modes,
1948                                             head) {
1949                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
1950                                         intel_dp->panel_fixed_mode =
1951                                                 drm_mode_duplicate(dev, newmode);
1952                                         break;
1953                                 }
1954                         }
1955                 }
1956                 return ret;
1957         }
1958
1959         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1960         if (is_edp(intel_dp)) {
1961                 /* initialize panel mode from VBT if available for eDP */
1962                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1963                         intel_dp->panel_fixed_mode =
1964                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1965                         if (intel_dp->panel_fixed_mode) {
1966                                 intel_dp->panel_fixed_mode->type |=
1967                                         DRM_MODE_TYPE_PREFERRED;
1968                         }
1969                 }
1970                 if (intel_dp->panel_fixed_mode) {
1971                         struct drm_display_mode *mode;
1972                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1973                         drm_mode_probed_add(connector, mode);
1974                         return 1;
1975                 }
1976         }
1977         return 0;
1978 }
1979
1980 static bool
1981 intel_dp_detect_audio(struct drm_connector *connector)
1982 {
1983         struct intel_dp *intel_dp = intel_attached_dp(connector);
1984         struct edid *edid;
1985         bool has_audio = false;
1986
1987         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1988         if (edid) {
1989                 has_audio = drm_detect_monitor_audio(edid);
1990
1991                 connector->display_info.raw_edid = NULL;
1992                 kfree(edid);
1993         }
1994
1995         return has_audio;
1996 }
1997
1998 static int
1999 intel_dp_set_property(struct drm_connector *connector,
2000                       struct drm_property *property,
2001                       uint64_t val)
2002 {
2003         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2004         struct intel_dp *intel_dp = intel_attached_dp(connector);
2005         int ret;
2006
2007         ret = drm_connector_property_set_value(connector, property, val);
2008         if (ret)
2009                 return ret;
2010
2011         if (property == dev_priv->force_audio_property) {
2012                 int i = val;
2013                 bool has_audio;
2014
2015                 if (i == intel_dp->force_audio)
2016                         return 0;
2017
2018                 intel_dp->force_audio = i;
2019
2020                 if (i == 0)
2021                         has_audio = intel_dp_detect_audio(connector);
2022                 else
2023                         has_audio = i > 0;
2024
2025                 if (has_audio == intel_dp->has_audio)
2026                         return 0;
2027
2028                 intel_dp->has_audio = has_audio;
2029                 goto done;
2030         }
2031
2032         if (property == dev_priv->broadcast_rgb_property) {
2033                 if (val == !!intel_dp->color_range)
2034                         return 0;
2035
2036                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2037                 goto done;
2038         }
2039
2040         return -EINVAL;
2041
2042 done:
2043         if (intel_dp->base.base.crtc) {
2044                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2045                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2046                                          crtc->x, crtc->y,
2047                                          crtc->fb);
2048         }
2049
2050         return 0;
2051 }
2052
2053 static void
2054 intel_dp_destroy(struct drm_connector *connector)
2055 {
2056         struct drm_device *dev = connector->dev;
2057
2058         if (intel_dpd_is_edp(dev))
2059                 intel_panel_destroy_backlight(dev);
2060
2061         drm_sysfs_connector_remove(connector);
2062         drm_connector_cleanup(connector);
2063         kfree(connector);
2064 }
2065
2066 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2067 {
2068         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2069
2070         i2c_del_adapter(&intel_dp->adapter);
2071         drm_encoder_cleanup(encoder);
2072         if (is_edp(intel_dp)) {
2073                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2074                 ironlake_panel_vdd_off_sync(intel_dp);
2075         }
2076         kfree(intel_dp);
2077 }
2078
2079 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2080         .dpms = intel_dp_dpms,
2081         .mode_fixup = intel_dp_mode_fixup,
2082         .prepare = intel_dp_prepare,
2083         .mode_set = intel_dp_mode_set,
2084         .commit = intel_dp_commit,
2085 };
2086
2087 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2088         .dpms = drm_helper_connector_dpms,
2089         .detect = intel_dp_detect,
2090         .fill_modes = drm_helper_probe_single_connector_modes,
2091         .set_property = intel_dp_set_property,
2092         .destroy = intel_dp_destroy,
2093 };
2094
2095 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2096         .get_modes = intel_dp_get_modes,
2097         .mode_valid = intel_dp_mode_valid,
2098         .best_encoder = intel_best_encoder,
2099 };
2100
2101 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2102         .destroy = intel_dp_encoder_destroy,
2103 };
2104
2105 static void
2106 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2107 {
2108         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2109
2110         intel_dp_check_link_status(intel_dp);
2111 }
2112
2113 /* Return which DP Port should be selected for Transcoder DP control */
2114 int
2115 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2116 {
2117         struct drm_device *dev = crtc->dev;
2118         struct drm_mode_config *mode_config = &dev->mode_config;
2119         struct drm_encoder *encoder;
2120
2121         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2122                 struct intel_dp *intel_dp;
2123
2124                 if (encoder->crtc != crtc)
2125                         continue;
2126
2127                 intel_dp = enc_to_intel_dp(encoder);
2128                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2129                         return intel_dp->output_reg;
2130         }
2131
2132         return -1;
2133 }
2134
2135 /* check the VBT to see whether the eDP is on DP-D port */
2136 bool intel_dpd_is_edp(struct drm_device *dev)
2137 {
2138         struct drm_i915_private *dev_priv = dev->dev_private;
2139         struct child_device_config *p_child;
2140         int i;
2141
2142         if (!dev_priv->child_dev_num)
2143                 return false;
2144
2145         for (i = 0; i < dev_priv->child_dev_num; i++) {
2146                 p_child = dev_priv->child_dev + i;
2147
2148                 if (p_child->dvo_port == PORT_IDPD &&
2149                     p_child->device_type == DEVICE_TYPE_eDP)
2150                         return true;
2151         }
2152         return false;
2153 }
2154
2155 static void
2156 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2157 {
2158         intel_attach_force_audio_property(connector);
2159         intel_attach_broadcast_rgb_property(connector);
2160 }
2161
2162 void
2163 intel_dp_init(struct drm_device *dev, int output_reg)
2164 {
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct drm_connector *connector;
2167         struct intel_dp *intel_dp;
2168         struct intel_encoder *intel_encoder;
2169         struct intel_connector *intel_connector;
2170         const char *name = NULL;
2171         int type;
2172
2173         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2174         if (!intel_dp)
2175                 return;
2176
2177         intel_dp->output_reg = output_reg;
2178         intel_dp->dpms_mode = -1;
2179
2180         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2181         if (!intel_connector) {
2182                 kfree(intel_dp);
2183                 return;
2184         }
2185         intel_encoder = &intel_dp->base;
2186
2187         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2188                 if (intel_dpd_is_edp(dev))
2189                         intel_dp->is_pch_edp = true;
2190
2191         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2192                 type = DRM_MODE_CONNECTOR_eDP;
2193                 intel_encoder->type = INTEL_OUTPUT_EDP;
2194         } else {
2195                 type = DRM_MODE_CONNECTOR_DisplayPort;
2196                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2197         }
2198
2199         connector = &intel_connector->base;
2200         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2201         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2202
2203         connector->polled = DRM_CONNECTOR_POLL_HPD;
2204
2205         if (output_reg == DP_B || output_reg == PCH_DP_B)
2206                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2207         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2208                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2209         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2210                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2211
2212         if (is_edp(intel_dp)) {
2213                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2214                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2215                                   ironlake_panel_vdd_work);
2216         }
2217
2218         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2219         connector->interlace_allowed = true;
2220         connector->doublescan_allowed = 0;
2221
2222         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2223                          DRM_MODE_ENCODER_TMDS);
2224         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2225
2226         intel_connector_attach_encoder(intel_connector, intel_encoder);
2227         drm_sysfs_connector_add(connector);
2228
2229         /* Set up the DDC bus. */
2230         switch (output_reg) {
2231                 case DP_A:
2232                         name = "DPDDC-A";
2233                         break;
2234                 case DP_B:
2235                 case PCH_DP_B:
2236                         dev_priv->hotplug_supported_mask |=
2237                                 HDMIB_HOTPLUG_INT_STATUS;
2238                         name = "DPDDC-B";
2239                         break;
2240                 case DP_C:
2241                 case PCH_DP_C:
2242                         dev_priv->hotplug_supported_mask |=
2243                                 HDMIC_HOTPLUG_INT_STATUS;
2244                         name = "DPDDC-C";
2245                         break;
2246                 case DP_D:
2247                 case PCH_DP_D:
2248                         dev_priv->hotplug_supported_mask |=
2249                                 HDMID_HOTPLUG_INT_STATUS;
2250                         name = "DPDDC-D";
2251                         break;
2252         }
2253
2254         /* Cache some DPCD data in the eDP case */
2255         if (is_edp(intel_dp)) {
2256                 bool ret;
2257                 struct edp_power_seq    cur, vbt;
2258                 u32 pp_on, pp_off, pp_div;
2259
2260                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2261                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2262                 pp_div = I915_READ(PCH_PP_DIVISOR);
2263
2264                 /* Pull timing values out of registers */
2265                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2266                         PANEL_POWER_UP_DELAY_SHIFT;
2267
2268                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2269                         PANEL_LIGHT_ON_DELAY_SHIFT;
2270
2271                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2272                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2273
2274                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2275                         PANEL_POWER_DOWN_DELAY_SHIFT;
2276
2277                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2278                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2279
2280                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2281                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2282
2283                 vbt = dev_priv->edp.pps;
2284
2285                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2286                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2287
2288 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2289
2290                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2291                 intel_dp->backlight_on_delay = get_delay(t8);
2292                 intel_dp->backlight_off_delay = get_delay(t9);
2293                 intel_dp->panel_power_down_delay = get_delay(t10);
2294                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2295
2296                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2297                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2298                               intel_dp->panel_power_cycle_delay);
2299
2300                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2301                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2302
2303                 intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
2304
2305                 ironlake_edp_panel_vdd_on(intel_dp);
2306                 ret = intel_dp_get_dpcd(intel_dp);
2307                 ironlake_edp_panel_vdd_off(intel_dp, false);
2308                 if (ret) {
2309                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2310                                 dev_priv->no_aux_handshake =
2311                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2312                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2313                 } else {
2314                         /* if this fails, presume the device is a ghost */
2315                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2316                         intel_dp_encoder_destroy(&intel_dp->base.base);
2317                         intel_dp_destroy(&intel_connector->base);
2318                         return;
2319                 }
2320         }
2321
2322         intel_dp_i2c_init(intel_dp, intel_connector, name);
2323
2324         intel_encoder->hot_plug = intel_dp_hot_plug;
2325
2326         if (is_edp(intel_dp)) {
2327                 dev_priv->int_edp_connector = connector;
2328                 intel_panel_setup_backlight(dev);
2329         }
2330
2331         intel_dp_add_properties(intel_dp, connector);
2332
2333         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2334          * 0xd.  Failure to do so will result in spurious interrupts being
2335          * generated on the port when a cable is not attached.
2336          */
2337         if (IS_G4X(dev) && !IS_GM45(dev)) {
2338                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2339                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2340         }
2341 }