drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[8];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62 };
  63
  64 /**
  65  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  66  * @intel_dp: DP struct
  67  *
  68  * If a CPU or PCH DP output is attached to an eDP panel, this function
  69  * will return true, and false otherwise.
  70  */
  71 static bool is_edp(struct intel_dp *intel_dp)
  72 {
  73         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  74 }
  75
  76 /**
  77  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  78  * @intel_dp: DP struct
  79  *
  80  * Returns true if the given DP struct corresponds to a PCH DP port attached
  81  * to an eDP panel, false otherwise.  Helpful for determining whether we
  82  * may need FDI resources for a given DP output or not.
  83  */
  84 static bool is_pch_edp(struct intel_dp *intel_dp)
  85 {
  86         return intel_dp->is_pch_edp;
  87 }
  88
  89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  90 {
  91         return container_of(encoder, struct intel_dp, base.base);
  92 }
  93
  94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  95 {
  96         return container_of(intel_attached_encoder(connector),
  97                             struct intel_dp, base);
  98 }
  99
 100 /**
 101  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 102  * @encoder: DRM encoder
 103  *
 104  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 105  * by intel_display.c.
 106  */
 107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 108 {
 109         struct intel_dp *intel_dp;
 110
 111         if (!encoder)
 112                 return false;
 113
 114         intel_dp = enc_to_intel_dp(encoder);
 115
 116         return is_pch_edp(intel_dp);
 117 }
 118
 119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 121 static void intel_dp_link_down(struct intel_dp *intel_dp);
 122
 123 void
 124 intel_edp_link_config (struct intel_encoder *intel_encoder,
 125                        int *lane_num, int *link_bw)
 126 {
 127         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 128
 129         *lane_num = intel_dp->lane_count;
 130         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 131                 *link_bw = 162000;
 132         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 133                 *link_bw = 270000;
 134 }
 135
 136 static int
 137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 138 {
 139         int max_lane_count = 4;
 140
 141         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 142                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 143                 switch (max_lane_count) {
 144                 case 1: case 2: case 4:
 145                         break;
 146                 default:
 147                         max_lane_count = 4;
 148                 }
 149         }
 150         return max_lane_count;
 151 }
 152
 153 static int
 154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 155 {
 156         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 157
 158         switch (max_link_bw) {
 159         case DP_LINK_BW_1_62:
 160         case DP_LINK_BW_2_7:
 161                 break;
 162         default:
 163                 max_link_bw = DP_LINK_BW_1_62;
 164                 break;
 165         }
 166         return max_link_bw;
 167 }
 168
 169 static int
 170 intel_dp_link_clock(uint8_t link_bw)
 171 {
 172         if (link_bw == DP_LINK_BW_2_7)
 173                 return 270000;
 174         else
 175                 return 162000;
 176 }
 177
 178 /* I think this is a fiction */
 179 static int
 180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 181 {
 182         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 184         int bpp = 24;
 185
 186         if (intel_crtc)
 187                 bpp = intel_crtc->bpp;
 188
 189         return (pixel_clock * bpp + 7) / 8;
 190 }
 191
 192 static int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         return (max_link_clock * max_lanes * 8) / 10;
 196 }
 197
 198 static int
 199 intel_dp_mode_valid(struct drm_connector *connector,
 200                     struct drm_display_mode *mode)
 201 {
 202         struct intel_dp *intel_dp = intel_attached_dp(connector);
 203         struct drm_device *dev = connector->dev;
 204         struct drm_i915_private *dev_priv = dev->dev_private;
 205         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 206         int max_lanes = intel_dp_max_lane_count(intel_dp);
 207
 208         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 209                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 210                         return MODE_PANEL;
 211
 212                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 213                         return MODE_PANEL;
 214         }
 215
 216         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 217            which are outside spec tolerances but somehow work by magic */
 218         if (!is_edp(intel_dp) &&
 219             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 220              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 221                 return MODE_CLOCK_HIGH;
 222
 223         if (mode->clock < 10000)
 224                 return MODE_CLOCK_LOW;
 225
 226         return MODE_OK;
 227 }
 228
 229 static uint32_t
 230 pack_aux(uint8_t *src, int src_bytes)
 231 {
 232         int     i;
 233         uint32_t v = 0;
 234
 235         if (src_bytes > 4)
 236                 src_bytes = 4;
 237         for (i = 0; i < src_bytes; i++)
 238                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 239         return v;
 240 }
 241
 242 static void
 243 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 244 {
 245         int i;
 246         if (dst_bytes > 4)
 247                 dst_bytes = 4;
 248         for (i = 0; i < dst_bytes; i++)
 249                 dst[i] = src >> ((3-i) * 8);
 250 }
 251
 252 /* hrawclock is 1/4 the FSB frequency */
 253 static int
 254 intel_hrawclk(struct drm_device *dev)
 255 {
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         uint32_t clkcfg;
 258
 259         clkcfg = I915_READ(CLKCFG);
 260         switch (clkcfg & CLKCFG_FSB_MASK) {
 261         case CLKCFG_FSB_400:
 262                 return 100;
 263         case CLKCFG_FSB_533:
 264                 return 133;
 265         case CLKCFG_FSB_667:
 266                 return 166;
 267         case CLKCFG_FSB_800:
 268                 return 200;
 269         case CLKCFG_FSB_1067:
 270                 return 266;
 271         case CLKCFG_FSB_1333:
 272                 return 333;
 273         /* these two are just a guess; one of them might be right */
 274         case CLKCFG_FSB_1600:
 275         case CLKCFG_FSB_1600_ALT:
 276                 return 400;
 277         default:
 278                 return 133;
 279         }
 280 }
 281
 282 static void
 283 intel_dp_check_edp(struct intel_dp *intel_dp)
 284 {
 285         struct drm_device *dev = intel_dp->base.base.dev;
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         u32 pp_status, pp_control;
 288         if (!is_edp(intel_dp))
 289                 return;
 290         pp_status = I915_READ(PCH_PP_STATUS);
 291         pp_control = I915_READ(PCH_PP_CONTROL);
 292         if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) {
 293                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 294                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 295                               pp_status,
 296                               I915_READ(PCH_PP_CONTROL));
 297         }
 298 }
 299
 300 static int
 301 intel_dp_aux_ch(struct intel_dp *intel_dp,
 302                 uint8_t *send, int send_bytes,
 303                 uint8_t *recv, int recv_size)
 304 {
 305         uint32_t output_reg = intel_dp->output_reg;
 306         struct drm_device *dev = intel_dp->base.base.dev;
 307         struct drm_i915_private *dev_priv = dev->dev_private;
 308         uint32_t ch_ctl = output_reg + 0x10;
 309         uint32_t ch_data = ch_ctl + 4;
 310         int i;
 311         int recv_bytes;
 312         uint32_t status;
 313         uint32_t aux_clock_divider;
 314         int try, precharge;
 315
 316         intel_dp_check_edp(intel_dp);
 317         /* The clock divider is based off the hrawclk,
 318          * and would like to run at 2MHz. So, take the
 319          * hrawclk value and divide by 2 and use that
 320          *
 321          * Note that PCH attached eDP panels should use a 125MHz input
 322          * clock divider.
 323          */
 324         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 325                 if (IS_GEN6(dev))
 326                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 327                 else
 328                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 329         } else if (HAS_PCH_SPLIT(dev))
 330                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 331         else
 332                 aux_clock_divider = intel_hrawclk(dev) / 2;
 333
 334         if (IS_GEN6(dev))
 335                 precharge = 3;
 336         else
 337                 precharge = 5;
 338
 339         /* Try to wait for any previous AUX channel activity */
 340         for (try = 0; try < 3; try++) {
 341                 status = I915_READ(ch_ctl);
 342                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 343                         break;
 344                 msleep(1);
 345         }
 346
 347         if (try == 3) {
 348                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 349                      I915_READ(ch_ctl));
 350                 return -EBUSY;
 351         }
 352
 353         /* Must try at least 3 times according to DP spec */
 354         for (try = 0; try < 5; try++) {
 355                 /* Load the send data into the aux channel data registers */
 356                 for (i = 0; i < send_bytes; i += 4)
 357                         I915_WRITE(ch_data + i,
 358                                    pack_aux(send + i, send_bytes - i));
 359
 360                 /* Send the command and wait for it to complete */
 361                 I915_WRITE(ch_ctl,
 362                            DP_AUX_CH_CTL_SEND_BUSY |
 363                            DP_AUX_CH_CTL_TIME_OUT_400us |
 364                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 365                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 366                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 367                            DP_AUX_CH_CTL_DONE |
 368                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 369                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 370                 for (;;) {
 371                         status = I915_READ(ch_ctl);
 372                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 373                                 break;
 374                         udelay(100);
 375                 }
 376
 377                 /* Clear done status and any errors */
 378                 I915_WRITE(ch_ctl,
 379                            status |
 380                            DP_AUX_CH_CTL_DONE |
 381                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 382                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 383                 if (status & DP_AUX_CH_CTL_DONE)
 384                         break;
 385         }
 386
 387         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 388                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 389                 return -EBUSY;
 390         }
 391
 392         /* Check for timeout or receive error.
 393          * Timeouts occur when the sink is not connected
 394          */
 395         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 396                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 397                 return -EIO;
 398         }
 399
 400         /* Timeouts occur when the device isn't connected, so they're
 401          * "normal" -- don't fill the kernel log with these */
 402         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 403                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 404                 return -ETIMEDOUT;
 405         }
 406
 407         /* Unload any bytes sent back from the other side */
 408         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 409                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 410         if (recv_bytes > recv_size)
 411                 recv_bytes = recv_size;
 412
 413         for (i = 0; i < recv_bytes; i += 4)
 414                 unpack_aux(I915_READ(ch_data + i),
 415                            recv + i, recv_bytes - i);
 416
 417         return recv_bytes;
 418 }
 419
 420 /* Write data to the aux channel in native mode */
 421 static int
 422 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 423                           uint16_t address, uint8_t *send, int send_bytes)
 424 {
 425         int ret;
 426         uint8_t msg[20];
 427         int msg_bytes;
 428         uint8_t ack;
 429
 430         intel_dp_check_edp(intel_dp);
 431         if (send_bytes > 16)
 432                 return -1;
 433         msg[0] = AUX_NATIVE_WRITE << 4;
 434         msg[1] = address >> 8;
 435         msg[2] = address & 0xff;
 436         msg[3] = send_bytes - 1;
 437         memcpy(&msg[4], send, send_bytes);
 438         msg_bytes = send_bytes + 4;
 439         for (;;) {
 440                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 441                 if (ret < 0)
 442                         return ret;
 443                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 444                         break;
 445                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 446                         udelay(100);
 447                 else
 448                         return -EIO;
 449         }
 450         return send_bytes;
 451 }
 452
 453 /* Write a single byte to the aux channel in native mode */
 454 static int
 455 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 456                             uint16_t address, uint8_t byte)
 457 {
 458         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 459 }
 460
 461 /* read bytes from a native aux channel */
 462 static int
 463 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 464                          uint16_t address, uint8_t *recv, int recv_bytes)
 465 {
 466         uint8_t msg[4];
 467         int msg_bytes;
 468         uint8_t reply[20];
 469         int reply_bytes;
 470         uint8_t ack;
 471         int ret;
 472
 473         intel_dp_check_edp(intel_dp);
 474         msg[0] = AUX_NATIVE_READ << 4;
 475         msg[1] = address >> 8;
 476         msg[2] = address & 0xff;
 477         msg[3] = recv_bytes - 1;
 478
 479         msg_bytes = 4;
 480         reply_bytes = recv_bytes + 1;
 481
 482         for (;;) {
 483                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 484                                       reply, reply_bytes);
 485                 if (ret == 0)
 486                         return -EPROTO;
 487                 if (ret < 0)
 488                         return ret;
 489                 ack = reply[0];
 490                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 491                         memcpy(recv, reply + 1, ret - 1);
 492                         return ret - 1;
 493                 }
 494                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 495                         udelay(100);
 496                 else
 497                         return -EIO;
 498         }
 499 }
 500
 501 static int
 502 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 503                     uint8_t write_byte, uint8_t *read_byte)
 504 {
 505         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 506         struct intel_dp *intel_dp = container_of(adapter,
 507                                                 struct intel_dp,
 508                                                 adapter);
 509         uint16_t address = algo_data->address;
 510         uint8_t msg[5];
 511         uint8_t reply[2];
 512         unsigned retry;
 513         int msg_bytes;
 514         int reply_bytes;
 515         int ret;
 516
 517         intel_dp_check_edp(intel_dp);
 518         /* Set up the command byte */
 519         if (mode & MODE_I2C_READ)
 520                 msg[0] = AUX_I2C_READ << 4;
 521         else
 522                 msg[0] = AUX_I2C_WRITE << 4;
 523
 524         if (!(mode & MODE_I2C_STOP))
 525                 msg[0] |= AUX_I2C_MOT << 4;
 526
 527         msg[1] = address >> 8;
 528         msg[2] = address;
 529
 530         switch (mode) {
 531         case MODE_I2C_WRITE:
 532                 msg[3] = 0;
 533                 msg[4] = write_byte;
 534                 msg_bytes = 5;
 535                 reply_bytes = 1;
 536                 break;
 537         case MODE_I2C_READ:
 538                 msg[3] = 0;
 539                 msg_bytes = 4;
 540                 reply_bytes = 2;
 541                 break;
 542         default:
 543                 msg_bytes = 3;
 544                 reply_bytes = 1;
 545                 break;
 546         }
 547
 548         for (retry = 0; retry < 5; retry++) {
 549                 ret = intel_dp_aux_ch(intel_dp,
 550                                       msg, msg_bytes,
 551                                       reply, reply_bytes);
 552                 if (ret < 0) {
 553                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 554                         return ret;
 555                 }
 556
 557                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 558                 case AUX_NATIVE_REPLY_ACK:
 559                         /* I2C-over-AUX Reply field is only valid
 560                          * when paired with AUX ACK.
 561                          */
 562                         break;
 563                 case AUX_NATIVE_REPLY_NACK:
 564                         DRM_DEBUG_KMS("aux_ch native nack\n");
 565                         return -EREMOTEIO;
 566                 case AUX_NATIVE_REPLY_DEFER:
 567                         udelay(100);
 568                         continue;
 569                 default:
 570                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 571                                   reply[0]);
 572                         return -EREMOTEIO;
 573                 }
 574
 575                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 576                 case AUX_I2C_REPLY_ACK:
 577                         if (mode == MODE_I2C_READ) {
 578                                 *read_byte = reply[1];
 579                         }
 580                         return reply_bytes - 1;
 581                 case AUX_I2C_REPLY_NACK:
 582                         DRM_DEBUG_KMS("aux_i2c nack\n");
 583                         return -EREMOTEIO;
 584                 case AUX_I2C_REPLY_DEFER:
 585                         DRM_DEBUG_KMS("aux_i2c defer\n");
 586                         udelay(100);
 587                         break;
 588                 default:
 589                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 590                         return -EREMOTEIO;
 591                 }
 592         }
 593
 594         DRM_ERROR("too many retries, giving up\n");
 595         return -EREMOTEIO;
 596 }
 597
 598 static int
 599 intel_dp_i2c_init(struct intel_dp *intel_dp,
 600                   struct intel_connector *intel_connector, const char *name)
 601 {
 602         DRM_DEBUG_KMS("i2c_init %s\n", name);
 603         intel_dp->algo.running = false;
 604         intel_dp->algo.address = 0;
 605         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 606
 607         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 608         intel_dp->adapter.owner = THIS_MODULE;
 609         intel_dp->adapter.class = I2C_CLASS_DDC;
 610         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 611         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 612         intel_dp->adapter.algo_data = &intel_dp->algo;
 613         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 614
 615         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 616 }
 617
 618 static bool
 619 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 620                     struct drm_display_mode *adjusted_mode)
 621 {
 622         struct drm_device *dev = encoder->dev;
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 625         int lane_count, clock;
 626         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 627         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 628         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 629
 630         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 631                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 632                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 633                                         mode, adjusted_mode);
 634                 /*
 635                  * the mode->clock is used to calculate the Data&Link M/N
 636                  * of the pipe. For the eDP the fixed clock should be used.
 637                  */
 638                 mode->clock = dev_priv->panel_fixed_mode->clock;
 639         }
 640
 641         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 642                 for (clock = 0; clock <= max_clock; clock++) {
 643                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 644
 645                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 646                                         <= link_avail) {
 647                                 intel_dp->link_bw = bws[clock];
 648                                 intel_dp->lane_count = lane_count;
 649                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 650                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 651                                                 "count %d clock %d\n",
 652                                        intel_dp->link_bw, intel_dp->lane_count,
 653                                        adjusted_mode->clock);
 654                                 return true;
 655                         }
 656                 }
 657         }
 658
 659         if (is_edp(intel_dp)) {
 660                 /* okay we failed just pick the highest */
 661                 intel_dp->lane_count = max_lane_count;
 662                 intel_dp->link_bw = bws[max_clock];
 663                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 664                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 665                               "count %d clock %d\n",
 666                               intel_dp->link_bw, intel_dp->lane_count,
 667                               adjusted_mode->clock);
 668
 669                 return true;
 670         }
 671
 672         return false;
 673 }
 674
 675 struct intel_dp_m_n {
 676         uint32_t        tu;
 677         uint32_t        gmch_m;
 678         uint32_t        gmch_n;
 679         uint32_t        link_m;
 680         uint32_t        link_n;
 681 };
 682
 683 static void
 684 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 685 {
 686         while (*num > 0xffffff || *den > 0xffffff) {
 687                 *num >>= 1;
 688                 *den >>= 1;
 689         }
 690 }
 691
 692 static void
 693 intel_dp_compute_m_n(int bpp,
 694                      int nlanes,
 695                      int pixel_clock,
 696                      int link_clock,
 697                      struct intel_dp_m_n *m_n)
 698 {
 699         m_n->tu = 64;
 700         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 701         m_n->gmch_n = link_clock * nlanes;
 702         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 703         m_n->link_m = pixel_clock;
 704         m_n->link_n = link_clock;
 705         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 706 }
 707
 708 void
 709 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 710                  struct drm_display_mode *adjusted_mode)
 711 {
 712         struct drm_device *dev = crtc->dev;
 713         struct drm_mode_config *mode_config = &dev->mode_config;
 714         struct drm_encoder *encoder;
 715         struct drm_i915_private *dev_priv = dev->dev_private;
 716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 717         int lane_count = 4;
 718         struct intel_dp_m_n m_n;
 719         int pipe = intel_crtc->pipe;
 720
 721         /*
 722          * Find the lane count in the intel_encoder private
 723          */
 724         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 725                 struct intel_dp *intel_dp;
 726
 727                 if (encoder->crtc != crtc)
 728                         continue;
 729
 730                 intel_dp = enc_to_intel_dp(encoder);
 731                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 732                         lane_count = intel_dp->lane_count;
 733                         break;
 734                 } else if (is_edp(intel_dp)) {
 735                         lane_count = dev_priv->edp.lanes;
 736                         break;
 737                 }
 738         }
 739
 740         /*
 741          * Compute the GMCH and Link ratios. The '3' here is
 742          * the number of bytes_per_pixel post-LUT, which we always
 743          * set up for 8-bits of R/G/B, or 3 bytes total.
 744          */
 745         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 746                              mode->clock, adjusted_mode->clock, &m_n);
 747
 748         if (HAS_PCH_SPLIT(dev)) {
 749                 I915_WRITE(TRANSDATA_M1(pipe),
 750                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 751                            m_n.gmch_m);
 752                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 753                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 754                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 755         } else {
 756                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 757                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 758                            m_n.gmch_m);
 759                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 760                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 761                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 762         }
 763 }
 764
 765 static void
 766 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 767                   struct drm_display_mode *adjusted_mode)
 768 {
 769         struct drm_device *dev = encoder->dev;
 770         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 771         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 773
 774         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 775         intel_dp->DP |= intel_dp->color_range;
 776
 777         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 778                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 779         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 780                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 781
 782         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 783                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 784         else
 785                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 786
 787         switch (intel_dp->lane_count) {
 788         case 1:
 789                 intel_dp->DP |= DP_PORT_WIDTH_1;
 790                 break;
 791         case 2:
 792                 intel_dp->DP |= DP_PORT_WIDTH_2;
 793                 break;
 794         case 4:
 795                 intel_dp->DP |= DP_PORT_WIDTH_4;
 796                 break;
 797         }
 798         if (intel_dp->has_audio)
 799                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 800
 801         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 802         intel_dp->link_configuration[0] = intel_dp->link_bw;
 803         intel_dp->link_configuration[1] = intel_dp->lane_count;
 804         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 805
 806         /*
 807          * Check for DPCD version > 1.1 and enhanced framing support
 808          */
 809         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 810             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 811                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 812                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 813         }
 814
 815         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 816         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 817                 intel_dp->DP |= DP_PIPEB_SELECT;
 818
 819         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 820                 /* don't miss out required setting for eDP */
 821                 intel_dp->DP |= DP_PLL_ENABLE;
 822                 if (adjusted_mode->clock < 200000)
 823                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 824                 else
 825                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 826         }
 827 }
 828
 829 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 830 {
 831         struct drm_device *dev = intel_dp->base.base.dev;
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         u32 pp;
 834
 835         if (!is_edp(intel_dp))
 836                 return;
 837         /*
 838          * If the panel wasn't on, make sure there's not a currently
 839          * active PP sequence before enabling AUX VDD.
 840          */
 841         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
 842                 msleep(dev_priv->panel_t3);
 843
 844         pp = I915_READ(PCH_PP_CONTROL);
 845         pp &= ~PANEL_UNLOCK_MASK;
 846         pp |= PANEL_UNLOCK_REGS;
 847         pp |= EDP_FORCE_VDD;
 848         I915_WRITE(PCH_PP_CONTROL, pp);
 849         POSTING_READ(PCH_PP_CONTROL);
 850 }
 851
 852 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 853 {
 854         struct drm_device *dev = intel_dp->base.base.dev;
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         u32 pp;
 857
 858         if (!is_edp(intel_dp))
 859                 return;
 860         pp = I915_READ(PCH_PP_CONTROL);
 861         pp &= ~PANEL_UNLOCK_MASK;
 862         pp |= PANEL_UNLOCK_REGS;
 863         pp &= ~EDP_FORCE_VDD;
 864         I915_WRITE(PCH_PP_CONTROL, pp);
 865         POSTING_READ(PCH_PP_CONTROL);
 866
 867         /* Make sure sequencer is idle before allowing subsequent activity */
 868         msleep(dev_priv->panel_t12);
 869 }
 870
 871 /* Returns true if the panel was already on when called */
 872 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 873 {
 874         struct drm_device *dev = intel_dp->base.base.dev;
 875         struct drm_i915_private *dev_priv = dev->dev_private;
 876         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 877
 878         if (!is_edp(intel_dp))
 879                 return;
 880         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 881                 return true;
 882
 883         pp = I915_READ(PCH_PP_CONTROL);
 884         pp &= ~PANEL_UNLOCK_MASK;
 885         pp |= PANEL_UNLOCK_REGS;
 886
 887         /* ILK workaround: disable reset around power sequence */
 888         pp &= ~PANEL_POWER_RESET;
 889         I915_WRITE(PCH_PP_CONTROL, pp);
 890         POSTING_READ(PCH_PP_CONTROL);
 891
 892         pp |= POWER_TARGET_ON;
 893         I915_WRITE(PCH_PP_CONTROL, pp);
 894         POSTING_READ(PCH_PP_CONTROL);
 895
 896         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 897                      5000))
 898                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 899                           I915_READ(PCH_PP_STATUS));
 900
 901         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 902         I915_WRITE(PCH_PP_CONTROL, pp);
 903         POSTING_READ(PCH_PP_CONTROL);
 904
 905         return false;
 906 }
 907
 908 static void ironlake_edp_panel_off (struct drm_device *dev)
 909 {
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 912                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 913
 914         if (!is_edp(intel_dp))
 915                 return;
 916         pp = I915_READ(PCH_PP_CONTROL);
 917         pp &= ~PANEL_UNLOCK_MASK;
 918         pp |= PANEL_UNLOCK_REGS;
 919
 920         /* ILK workaround: disable reset around power sequence */
 921         pp &= ~PANEL_POWER_RESET;
 922         I915_WRITE(PCH_PP_CONTROL, pp);
 923         POSTING_READ(PCH_PP_CONTROL);
 924
 925         pp &= ~POWER_TARGET_ON;
 926         I915_WRITE(PCH_PP_CONTROL, pp);
 927         POSTING_READ(PCH_PP_CONTROL);
 928
 929         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 930                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 931                           I915_READ(PCH_PP_STATUS));
 932
 933         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 934         I915_WRITE(PCH_PP_CONTROL, pp);
 935         POSTING_READ(PCH_PP_CONTROL);
 936 }
 937
 938 static void ironlake_edp_backlight_on (struct drm_device *dev)
 939 {
 940         struct drm_i915_private *dev_priv = dev->dev_private;
 941         u32 pp;
 942
 943         DRM_DEBUG_KMS("\n");
 944         /*
 945          * If we enable the backlight right away following a panel power
 946          * on, we may see slight flicker as the panel syncs with the eDP
 947          * link.  So delay a bit to make sure the image is solid before
 948          * allowing it to appear.
 949          */
 950         msleep(300);
 951         pp = I915_READ(PCH_PP_CONTROL);
 952         pp &= ~PANEL_UNLOCK_MASK;
 953         pp |= PANEL_UNLOCK_REGS;
 954         pp |= EDP_BLC_ENABLE;
 955         I915_WRITE(PCH_PP_CONTROL, pp);
 956 }
 957
 958 static void ironlake_edp_backlight_off (struct drm_device *dev)
 959 {
 960         struct drm_i915_private *dev_priv = dev->dev_private;
 961         u32 pp;
 962
 963         DRM_DEBUG_KMS("\n");
 964         pp = I915_READ(PCH_PP_CONTROL);
 965         pp &= ~PANEL_UNLOCK_MASK;
 966         pp |= PANEL_UNLOCK_REGS;
 967         pp &= ~EDP_BLC_ENABLE;
 968         I915_WRITE(PCH_PP_CONTROL, pp);
 969 }
 970
 971 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 972 {
 973         struct drm_device *dev = encoder->dev;
 974         struct drm_i915_private *dev_priv = dev->dev_private;
 975         u32 dpa_ctl;
 976
 977         DRM_DEBUG_KMS("\n");
 978         dpa_ctl = I915_READ(DP_A);
 979         dpa_ctl |= DP_PLL_ENABLE;
 980         I915_WRITE(DP_A, dpa_ctl);
 981         POSTING_READ(DP_A);
 982         udelay(200);
 983 }
 984
 985 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 986 {
 987         struct drm_device *dev = encoder->dev;
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         u32 dpa_ctl;
 990
 991         dpa_ctl = I915_READ(DP_A);
 992         dpa_ctl &= ~DP_PLL_ENABLE;
 993         I915_WRITE(DP_A, dpa_ctl);
 994         POSTING_READ(DP_A);
 995         udelay(200);
 996 }
 997
 998 /* If the sink supports it, try to set the power state appropriately */
 999 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1000 {
1001         int ret, i;
1002
1003         /* Should have a valid DPCD by this point */
1004         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1005                 return;
1006
1007         if (mode != DRM_MODE_DPMS_ON) {
1008                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1009                                                   DP_SET_POWER_D3);
1010                 if (ret != 1)
1011                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1012         } else {
1013                 /*
1014                  * When turning on, we need to retry for 1ms to give the sink
1015                  * time to wake up.
1016                  */
1017                 for (i = 0; i < 3; i++) {
1018                         ret = intel_dp_aux_native_write_1(intel_dp,
1019                                                           DP_SET_POWER,
1020                                                           DP_SET_POWER_D0);
1021                         if (ret == 1)
1022                                 break;
1023                         msleep(1);
1024                 }
1025         }
1026 }
1027
1028 static void intel_dp_prepare(struct drm_encoder *encoder)
1029 {
1030         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1031         struct drm_device *dev = encoder->dev;
1032
1033         /* Wake up the sink first */
1034         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1035
1036         if (is_edp(intel_dp)) {
1037                 ironlake_edp_backlight_off(dev);
1038                 ironlake_edp_panel_off(dev);
1039                 if (!is_pch_edp(intel_dp))
1040                         ironlake_edp_pll_on(encoder);
1041                 else
1042                         ironlake_edp_pll_off(encoder);
1043         }
1044         intel_dp_link_down(intel_dp);
1045 }
1046
1047 static void intel_dp_commit(struct drm_encoder *encoder)
1048 {
1049         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1050         struct drm_device *dev = encoder->dev;
1051
1052         ironlake_edp_panel_vdd_on(intel_dp);
1053
1054         intel_dp_start_link_train(intel_dp);
1055
1056         ironlake_edp_panel_on(intel_dp);
1057         ironlake_edp_panel_vdd_off(intel_dp);
1058
1059         intel_dp_complete_link_train(intel_dp);
1060
1061         if (is_edp(intel_dp))
1062                 ironlake_edp_backlight_on(dev);
1063
1064         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1065 }
1066
1067 static void
1068 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1069 {
1070         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1071         struct drm_device *dev = encoder->dev;
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1074
1075         if (mode != DRM_MODE_DPMS_ON) {
1076                 if (is_edp(intel_dp))
1077                         ironlake_edp_backlight_off(dev);
1078                 intel_dp_sink_dpms(intel_dp, mode);
1079                 intel_dp_link_down(intel_dp);
1080                 ironlake_edp_panel_off(dev);
1081                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1082                         ironlake_edp_pll_off(encoder);
1083         } else {
1084                 ironlake_edp_panel_vdd_on(intel_dp);
1085                 intel_dp_sink_dpms(intel_dp, mode);
1086                 if (!(dp_reg & DP_PORT_EN)) {
1087                         intel_dp_start_link_train(intel_dp);
1088                         ironlake_edp_panel_on(intel_dp);
1089                         ironlake_edp_panel_vdd_off(intel_dp);
1090                         intel_dp_complete_link_train(intel_dp);
1091                 }
1092                 if (is_edp(intel_dp))
1093                         ironlake_edp_backlight_on(dev);
1094         }
1095         intel_dp->dpms_mode = mode;
1096 }
1097
1098 /*
1099  * Native read with retry for link status and receiver capability reads for
1100  * cases where the sink may still be asleep.
1101  */
1102 static bool
1103 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1104                                uint8_t *recv, int recv_bytes)
1105 {
1106         int ret, i;
1107
1108         /*
1109          * Sinks are *supposed* to come up within 1ms from an off state,
1110          * but we're also supposed to retry 3 times per the spec.
1111          */
1112         for (i = 0; i < 3; i++) {
1113                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1114                                                recv_bytes);
1115                 if (ret == recv_bytes)
1116                         return true;
1117                 msleep(1);
1118         }
1119
1120         return false;
1121 }
1122
1123 /*
1124  * Fetch AUX CH registers 0x202 - 0x207 which contain
1125  * link status information
1126  */
1127 static bool
1128 intel_dp_get_link_status(struct intel_dp *intel_dp)
1129 {
1130         return intel_dp_aux_native_read_retry(intel_dp,
1131                                               DP_LANE0_1_STATUS,
1132                                               intel_dp->link_status,
1133                                               DP_LINK_STATUS_SIZE);
1134 }
1135
1136 static uint8_t
1137 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1138                      int r)
1139 {
1140         return link_status[r - DP_LANE0_1_STATUS];
1141 }
1142
1143 static uint8_t
1144 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1145                                  int lane)
1146 {
1147         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1148         int         s = ((lane & 1) ?
1149                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1150                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1151         uint8_t l = intel_dp_link_status(link_status, i);
1152
1153         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1154 }
1155
1156 static uint8_t
1157 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1158                                       int lane)
1159 {
1160         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1161         int         s = ((lane & 1) ?
1162                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1163                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1164         uint8_t l = intel_dp_link_status(link_status, i);
1165
1166         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1167 }
1168
1169
1170 #if 0
1171 static char     *voltage_names[] = {
1172         "0.4V", "0.6V", "0.8V", "1.2V"
1173 };
1174 static char     *pre_emph_names[] = {
1175         "0dB", "3.5dB", "6dB", "9.5dB"
1176 };
1177 static char     *link_train_names[] = {
1178         "pattern 1", "pattern 2", "idle", "off"
1179 };
1180 #endif
1181
1182 /*
1183  * These are source-specific values; current Intel hardware supports
1184  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1185  */
1186 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1187
1188 static uint8_t
1189 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1190 {
1191         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1192         case DP_TRAIN_VOLTAGE_SWING_400:
1193                 return DP_TRAIN_PRE_EMPHASIS_6;
1194         case DP_TRAIN_VOLTAGE_SWING_600:
1195                 return DP_TRAIN_PRE_EMPHASIS_6;
1196         case DP_TRAIN_VOLTAGE_SWING_800:
1197                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1198         case DP_TRAIN_VOLTAGE_SWING_1200:
1199         default:
1200                 return DP_TRAIN_PRE_EMPHASIS_0;
1201         }
1202 }
1203
1204 static void
1205 intel_get_adjust_train(struct intel_dp *intel_dp)
1206 {
1207         uint8_t v = 0;
1208         uint8_t p = 0;
1209         int lane;
1210
1211         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1212                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1213                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1214
1215                 if (this_v > v)
1216                         v = this_v;
1217                 if (this_p > p)
1218                         p = this_p;
1219         }
1220
1221         if (v >= I830_DP_VOLTAGE_MAX)
1222                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1223
1224         if (p >= intel_dp_pre_emphasis_max(v))
1225                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1226
1227         for (lane = 0; lane < 4; lane++)
1228                 intel_dp->train_set[lane] = v | p;
1229 }
1230
1231 static uint32_t
1232 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1233 {
1234         uint32_t        signal_levels = 0;
1235
1236         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1237         case DP_TRAIN_VOLTAGE_SWING_400:
1238         default:
1239                 signal_levels |= DP_VOLTAGE_0_4;
1240                 break;
1241         case DP_TRAIN_VOLTAGE_SWING_600:
1242                 signal_levels |= DP_VOLTAGE_0_6;
1243                 break;
1244         case DP_TRAIN_VOLTAGE_SWING_800:
1245                 signal_levels |= DP_VOLTAGE_0_8;
1246                 break;
1247         case DP_TRAIN_VOLTAGE_SWING_1200:
1248                 signal_levels |= DP_VOLTAGE_1_2;
1249                 break;
1250         }
1251         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1252         case DP_TRAIN_PRE_EMPHASIS_0:
1253         default:
1254                 signal_levels |= DP_PRE_EMPHASIS_0;
1255                 break;
1256         case DP_TRAIN_PRE_EMPHASIS_3_5:
1257                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1258                 break;
1259         case DP_TRAIN_PRE_EMPHASIS_6:
1260                 signal_levels |= DP_PRE_EMPHASIS_6;
1261                 break;
1262         case DP_TRAIN_PRE_EMPHASIS_9_5:
1263                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1264                 break;
1265         }
1266         return signal_levels;
1267 }
1268
1269 /* Gen6's DP voltage swing and pre-emphasis control */
1270 static uint32_t
1271 intel_gen6_edp_signal_levels(uint8_t train_set)
1272 {
1273         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1274                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1275         switch (signal_levels) {
1276         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1277         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1278                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1279         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1280                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1281         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1282         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1283                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1284         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1285         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1286                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1287         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1288         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1289                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1290         default:
1291                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1292                               "0x%x\n", signal_levels);
1293                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1294         }
1295 }
1296
1297 static uint8_t
1298 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1299                       int lane)
1300 {
1301         int i = DP_LANE0_1_STATUS + (lane >> 1);
1302         int s = (lane & 1) * 4;
1303         uint8_t l = intel_dp_link_status(link_status, i);
1304
1305         return (l >> s) & 0xf;
1306 }
1307
1308 /* Check for clock recovery is done on all channels */
1309 static bool
1310 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1311 {
1312         int lane;
1313         uint8_t lane_status;
1314
1315         for (lane = 0; lane < lane_count; lane++) {
1316                 lane_status = intel_get_lane_status(link_status, lane);
1317                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1318                         return false;
1319         }
1320         return true;
1321 }
1322
1323 /* Check to see if channel eq is done on all channels */
1324 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1325                          DP_LANE_CHANNEL_EQ_DONE|\
1326                          DP_LANE_SYMBOL_LOCKED)
1327 static bool
1328 intel_channel_eq_ok(struct intel_dp *intel_dp)
1329 {
1330         uint8_t lane_align;
1331         uint8_t lane_status;
1332         int lane;
1333
1334         lane_align = intel_dp_link_status(intel_dp->link_status,
1335                                           DP_LANE_ALIGN_STATUS_UPDATED);
1336         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1337                 return false;
1338         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1339                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1340                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool
1347 intel_dp_set_link_train(struct intel_dp *intel_dp,
1348                         uint32_t dp_reg_value,
1349                         uint8_t dp_train_pat)
1350 {
1351         struct drm_device *dev = intel_dp->base.base.dev;
1352         struct drm_i915_private *dev_priv = dev->dev_private;
1353         int ret;
1354
1355         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1356         POSTING_READ(intel_dp->output_reg);
1357
1358         intel_dp_aux_native_write_1(intel_dp,
1359                                     DP_TRAINING_PATTERN_SET,
1360                                     dp_train_pat);
1361
1362         ret = intel_dp_aux_native_write(intel_dp,
1363                                         DP_TRAINING_LANE0_SET,
1364                                         intel_dp->train_set, 4);
1365         if (ret != 4)
1366                 return false;
1367
1368         return true;
1369 }
1370
1371 /* Enable corresponding port and start training pattern 1 */
1372 static void
1373 intel_dp_start_link_train(struct intel_dp *intel_dp)
1374 {
1375         struct drm_device *dev = intel_dp->base.base.dev;
1376         struct drm_i915_private *dev_priv = dev->dev_private;
1377         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1378         int i;
1379         uint8_t voltage;
1380         bool clock_recovery = false;
1381         int tries;
1382         u32 reg;
1383         uint32_t DP = intel_dp->DP;
1384
1385         /*
1386          * On CPT we have to enable the port in training pattern 1, which
1387          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1388          * the port and wait for it to become active.
1389          */
1390         if (!HAS_PCH_CPT(dev)) {
1391                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1392                 POSTING_READ(intel_dp->output_reg);
1393                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1394         }
1395
1396         /* Write the link configuration data */
1397         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1398                                   intel_dp->link_configuration,
1399                                   DP_LINK_CONFIGURATION_SIZE);
1400
1401         DP |= DP_PORT_EN;
1402         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1403                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1404         else
1405                 DP &= ~DP_LINK_TRAIN_MASK;
1406         memset(intel_dp->train_set, 0, 4);
1407         voltage = 0xff;
1408         tries = 0;
1409         clock_recovery = false;
1410         for (;;) {
1411                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1412                 uint32_t    signal_levels;
1413                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1414                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1415                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1416                 } else {
1417                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1418                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1419                 }
1420
1421                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1422                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1423                 else
1424                         reg = DP | DP_LINK_TRAIN_PAT_1;
1425
1426                 if (!intel_dp_set_link_train(intel_dp, reg,
1427                                              DP_TRAINING_PATTERN_1 |
1428                                              DP_LINK_SCRAMBLING_DISABLE))
1429                         break;
1430                 /* Set training pattern 1 */
1431
1432                 udelay(100);
1433                 if (!intel_dp_get_link_status(intel_dp))
1434                         break;
1435
1436                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1437                         clock_recovery = true;
1438                         break;
1439                 }
1440
1441                 /* Check to see if we've tried the max voltage */
1442                 for (i = 0; i < intel_dp->lane_count; i++)
1443                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1444                                 break;
1445                 if (i == intel_dp->lane_count)
1446                         break;
1447
1448                 /* Check to see if we've tried the same voltage 5 times */
1449                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1450                         ++tries;
1451                         if (tries == 5)
1452                                 break;
1453                 } else
1454                         tries = 0;
1455                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1456
1457                 /* Compute new intel_dp->train_set as requested by target */
1458                 intel_get_adjust_train(intel_dp);
1459         }
1460
1461         intel_dp->DP = DP;
1462 }
1463
1464 static void
1465 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1466 {
1467         struct drm_device *dev = intel_dp->base.base.dev;
1468         struct drm_i915_private *dev_priv = dev->dev_private;
1469         bool channel_eq = false;
1470         int tries, cr_tries;
1471         u32 reg;
1472         uint32_t DP = intel_dp->DP;
1473
1474         /* channel equalization */
1475         tries = 0;
1476         cr_tries = 0;
1477         channel_eq = false;
1478         for (;;) {
1479                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1480                 uint32_t    signal_levels;
1481
1482                 if (cr_tries > 5) {
1483                         DRM_ERROR("failed to train DP, aborting\n");
1484                         intel_dp_link_down(intel_dp);
1485                         break;
1486                 }
1487
1488                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1489                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1490                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1491                 } else {
1492                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1493                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1494                 }
1495
1496                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1497                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1498                 else
1499                         reg = DP | DP_LINK_TRAIN_PAT_2;
1500
1501                 /* channel eq pattern */
1502                 if (!intel_dp_set_link_train(intel_dp, reg,
1503                                              DP_TRAINING_PATTERN_2 |
1504                                              DP_LINK_SCRAMBLING_DISABLE))
1505                         break;
1506
1507                 udelay(400);
1508                 if (!intel_dp_get_link_status(intel_dp))
1509                         break;
1510
1511                 /* Make sure clock is still ok */
1512                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1513                         intel_dp_start_link_train(intel_dp);
1514                         cr_tries++;
1515                         continue;
1516                 }
1517
1518                 if (intel_channel_eq_ok(intel_dp)) {
1519                         channel_eq = true;
1520                         break;
1521                 }
1522
1523                 /* Try 5 times, then try clock recovery if that fails */
1524                 if (tries > 5) {
1525                         intel_dp_link_down(intel_dp);
1526                         intel_dp_start_link_train(intel_dp);
1527                         tries = 0;
1528                         cr_tries++;
1529                         continue;
1530                 }
1531
1532                 /* Compute new intel_dp->train_set as requested by target */
1533                 intel_get_adjust_train(intel_dp);
1534                 ++tries;
1535         }
1536
1537         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1538                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1539         else
1540                 reg = DP | DP_LINK_TRAIN_OFF;
1541
1542         I915_WRITE(intel_dp->output_reg, reg);
1543         POSTING_READ(intel_dp->output_reg);
1544         intel_dp_aux_native_write_1(intel_dp,
1545                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1546 }
1547
1548 static void
1549 intel_dp_link_down(struct intel_dp *intel_dp)
1550 {
1551         struct drm_device *dev = intel_dp->base.base.dev;
1552         struct drm_i915_private *dev_priv = dev->dev_private;
1553         uint32_t DP = intel_dp->DP;
1554
1555         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1556                 return;
1557
1558         DRM_DEBUG_KMS("\n");
1559
1560         if (is_edp(intel_dp)) {
1561                 DP &= ~DP_PLL_ENABLE;
1562                 I915_WRITE(intel_dp->output_reg, DP);
1563                 POSTING_READ(intel_dp->output_reg);
1564                 udelay(100);
1565         }
1566
1567         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1568                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1569                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1570         } else {
1571                 DP &= ~DP_LINK_TRAIN_MASK;
1572                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1573         }
1574         POSTING_READ(intel_dp->output_reg);
1575
1576         msleep(17);
1577
1578         if (is_edp(intel_dp))
1579                 DP |= DP_LINK_TRAIN_OFF;
1580
1581         if (!HAS_PCH_CPT(dev) &&
1582             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1583                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1584
1585                 /* Hardware workaround: leaving our transcoder select
1586                  * set to transcoder B while it's off will prevent the
1587                  * corresponding HDMI output on transcoder A.
1588                  *
1589                  * Combine this with another hardware workaround:
1590                  * transcoder select bit can only be cleared while the
1591                  * port is enabled.
1592                  */
1593                 DP &= ~DP_PIPEB_SELECT;
1594                 I915_WRITE(intel_dp->output_reg, DP);
1595
1596                 /* Changes to enable or select take place the vblank
1597                  * after being written.
1598                  */
1599                 if (crtc == NULL) {
1600                         /* We can arrive here never having been attached
1601                          * to a CRTC, for instance, due to inheriting
1602                          * random state from the BIOS.
1603                          *
1604                          * If the pipe is not running, play safe and
1605                          * wait for the clocks to stabilise before
1606                          * continuing.
1607                          */
1608                         POSTING_READ(intel_dp->output_reg);
1609                         msleep(50);
1610                 } else
1611                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1612         }
1613
1614         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1615         POSTING_READ(intel_dp->output_reg);
1616 }
1617
1618 static bool
1619 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1620 {
1621         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1622                                            sizeof (intel_dp->dpcd)) &&
1623             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1624                 return true;
1625         }
1626
1627         return false;
1628 }
1629
1630 /*
1631  * According to DP spec
1632  * 5.1.2:
1633  *  1. Read DPCD
1634  *  2. Configure link according to Receiver Capabilities
1635  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1636  *  4. Check link status on receipt of hot-plug interrupt
1637  */
1638
1639 static void
1640 intel_dp_check_link_status(struct intel_dp *intel_dp)
1641 {
1642         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1643                 return;
1644
1645         if (!intel_dp->base.base.crtc)
1646                 return;
1647
1648         /* Try to read receiver status if the link appears to be up */
1649         if (!intel_dp_get_link_status(intel_dp)) {
1650                 intel_dp_link_down(intel_dp);
1651                 return;
1652         }
1653
1654         /* Now read the DPCD to see if it's actually running */
1655         if (!intel_dp_get_dpcd(intel_dp)) {
1656                 intel_dp_link_down(intel_dp);
1657                 return;
1658         }
1659
1660         if (!intel_channel_eq_ok(intel_dp)) {
1661                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1662                               drm_get_encoder_name(&intel_dp->base.base));
1663                 intel_dp_start_link_train(intel_dp);
1664                 intel_dp_complete_link_train(intel_dp);
1665         }
1666 }
1667
1668 static enum drm_connector_status
1669 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1670 {
1671         if (intel_dp_get_dpcd(intel_dp))
1672                 return connector_status_connected;
1673         return connector_status_disconnected;
1674 }
1675
1676 static enum drm_connector_status
1677 ironlake_dp_detect(struct intel_dp *intel_dp)
1678 {
1679         enum drm_connector_status status;
1680
1681         /* Can't disconnect eDP, but you can close the lid... */
1682         if (is_edp(intel_dp)) {
1683                 status = intel_panel_detect(intel_dp->base.base.dev);
1684                 if (status == connector_status_unknown)
1685                         status = connector_status_connected;
1686                 return status;
1687         }
1688
1689         return intel_dp_detect_dpcd(intel_dp);
1690 }
1691
1692 static enum drm_connector_status
1693 g4x_dp_detect(struct intel_dp *intel_dp)
1694 {
1695         struct drm_device *dev = intel_dp->base.base.dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697         uint32_t temp, bit;
1698
1699         switch (intel_dp->output_reg) {
1700         case DP_B:
1701                 bit = DPB_HOTPLUG_INT_STATUS;
1702                 break;
1703         case DP_C:
1704                 bit = DPC_HOTPLUG_INT_STATUS;
1705                 break;
1706         case DP_D:
1707                 bit = DPD_HOTPLUG_INT_STATUS;
1708                 break;
1709         default:
1710                 return connector_status_unknown;
1711         }
1712
1713         temp = I915_READ(PORT_HOTPLUG_STAT);
1714
1715         if ((temp & bit) == 0)
1716                 return connector_status_disconnected;
1717
1718         return intel_dp_detect_dpcd(intel_dp);
1719 }
1720
1721 /**
1722  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1723  *
1724  * \return true if DP port is connected.
1725  * \return false if DP port is disconnected.
1726  */
1727 static enum drm_connector_status
1728 intel_dp_detect(struct drm_connector *connector, bool force)
1729 {
1730         struct intel_dp *intel_dp = intel_attached_dp(connector);
1731         struct drm_device *dev = intel_dp->base.base.dev;
1732         enum drm_connector_status status;
1733         struct edid *edid = NULL;
1734
1735         intel_dp->has_audio = false;
1736
1737         if (HAS_PCH_SPLIT(dev))
1738                 status = ironlake_dp_detect(intel_dp);
1739         else
1740                 status = g4x_dp_detect(intel_dp);
1741
1742         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1743                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1744                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1745                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1746
1747         if (status != connector_status_connected)
1748                 return status;
1749
1750         if (intel_dp->force_audio) {
1751                 intel_dp->has_audio = intel_dp->force_audio > 0;
1752         } else {
1753                 edid = drm_get_edid(connector, &intel_dp->adapter);
1754                 if (edid) {
1755                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1756                         connector->display_info.raw_edid = NULL;
1757                         kfree(edid);
1758                 }
1759         }
1760
1761         return connector_status_connected;
1762 }
1763
1764 static int intel_dp_get_modes(struct drm_connector *connector)
1765 {
1766         struct intel_dp *intel_dp = intel_attached_dp(connector);
1767         struct drm_device *dev = intel_dp->base.base.dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         int ret;
1770
1771         /* We should parse the EDID data and find out if it has an audio sink
1772          */
1773
1774         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1775         if (ret) {
1776                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1777                         struct drm_display_mode *newmode;
1778                         list_for_each_entry(newmode, &connector->probed_modes,
1779                                             head) {
1780                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1781                                         dev_priv->panel_fixed_mode =
1782                                                 drm_mode_duplicate(dev, newmode);
1783                                         break;
1784                                 }
1785                         }
1786                 }
1787
1788                 return ret;
1789         }
1790
1791         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1792         if (is_edp(intel_dp)) {
1793                 /* initialize panel mode from VBT if available for eDP */
1794                 if (dev_priv->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1795                         dev_priv->panel_fixed_mode =
1796                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1797                         if (dev_priv->panel_fixed_mode) {
1798                                 dev_priv->panel_fixed_mode->type |=
1799                                         DRM_MODE_TYPE_PREFERRED;
1800                         }
1801                 }
1802                 if (dev_priv->panel_fixed_mode) {
1803                         struct drm_display_mode *mode;
1804                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1805                         drm_mode_probed_add(connector, mode);
1806                         return 1;
1807                 }
1808         }
1809         return 0;
1810 }
1811
1812 static bool
1813 intel_dp_detect_audio(struct drm_connector *connector)
1814 {
1815         struct intel_dp *intel_dp = intel_attached_dp(connector);
1816         struct edid *edid;
1817         bool has_audio = false;
1818
1819         edid = drm_get_edid(connector, &intel_dp->adapter);
1820         if (edid) {
1821                 has_audio = drm_detect_monitor_audio(edid);
1822
1823                 connector->display_info.raw_edid = NULL;
1824                 kfree(edid);
1825         }
1826
1827         return has_audio;
1828 }
1829
1830 static int
1831 intel_dp_set_property(struct drm_connector *connector,
1832                       struct drm_property *property,
1833                       uint64_t val)
1834 {
1835         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1836         struct intel_dp *intel_dp = intel_attached_dp(connector);
1837         int ret;
1838
1839         ret = drm_connector_property_set_value(connector, property, val);
1840         if (ret)
1841                 return ret;
1842
1843         if (property == dev_priv->force_audio_property) {
1844                 int i = val;
1845                 bool has_audio;
1846
1847                 if (i == intel_dp->force_audio)
1848                         return 0;
1849
1850                 intel_dp->force_audio = i;
1851
1852                 if (i == 0)
1853                         has_audio = intel_dp_detect_audio(connector);
1854                 else
1855                         has_audio = i > 0;
1856
1857                 if (has_audio == intel_dp->has_audio)
1858                         return 0;
1859
1860                 intel_dp->has_audio = has_audio;
1861                 goto done;
1862         }
1863
1864         if (property == dev_priv->broadcast_rgb_property) {
1865                 if (val == !!intel_dp->color_range)
1866                         return 0;
1867
1868                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1869                 goto done;
1870         }
1871
1872         return -EINVAL;
1873
1874 done:
1875         if (intel_dp->base.base.crtc) {
1876                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1877                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1878                                          crtc->x, crtc->y,
1879                                          crtc->fb);
1880         }
1881
1882         return 0;
1883 }
1884
1885 static void
1886 intel_dp_destroy (struct drm_connector *connector)
1887 {
1888         struct drm_device *dev = connector->dev;
1889
1890         if (intel_dpd_is_edp(dev))
1891                 intel_panel_destroy_backlight(dev);
1892
1893         drm_sysfs_connector_remove(connector);
1894         drm_connector_cleanup(connector);
1895         kfree(connector);
1896 }
1897
1898 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1899 {
1900         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1901
1902         i2c_del_adapter(&intel_dp->adapter);
1903         drm_encoder_cleanup(encoder);
1904         kfree(intel_dp);
1905 }
1906
1907 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1908         .dpms = intel_dp_dpms,
1909         .mode_fixup = intel_dp_mode_fixup,
1910         .prepare = intel_dp_prepare,
1911         .mode_set = intel_dp_mode_set,
1912         .commit = intel_dp_commit,
1913 };
1914
1915 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1916         .dpms = drm_helper_connector_dpms,
1917         .detect = intel_dp_detect,
1918         .fill_modes = drm_helper_probe_single_connector_modes,
1919         .set_property = intel_dp_set_property,
1920         .destroy = intel_dp_destroy,
1921 };
1922
1923 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1924         .get_modes = intel_dp_get_modes,
1925         .mode_valid = intel_dp_mode_valid,
1926         .best_encoder = intel_best_encoder,
1927 };
1928
1929 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1930         .destroy = intel_dp_encoder_destroy,
1931 };
1932
1933 static void
1934 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1935 {
1936         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1937
1938         intel_dp_check_link_status(intel_dp);
1939 }
1940
1941 /* Return which DP Port should be selected for Transcoder DP control */
1942 int
1943 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1944 {
1945         struct drm_device *dev = crtc->dev;
1946         struct drm_mode_config *mode_config = &dev->mode_config;
1947         struct drm_encoder *encoder;
1948
1949         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1950                 struct intel_dp *intel_dp;
1951
1952                 if (encoder->crtc != crtc)
1953                         continue;
1954
1955                 intel_dp = enc_to_intel_dp(encoder);
1956                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1957                         return intel_dp->output_reg;
1958         }
1959
1960         return -1;
1961 }
1962
1963 /* check the VBT to see whether the eDP is on DP-D port */
1964 bool intel_dpd_is_edp(struct drm_device *dev)
1965 {
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         struct child_device_config *p_child;
1968         int i;
1969
1970         if (!dev_priv->child_dev_num)
1971                 return false;
1972
1973         for (i = 0; i < dev_priv->child_dev_num; i++) {
1974                 p_child = dev_priv->child_dev + i;
1975
1976                 if (p_child->dvo_port == PORT_IDPD &&
1977                     p_child->device_type == DEVICE_TYPE_eDP)
1978                         return true;
1979         }
1980         return false;
1981 }
1982
1983 static void
1984 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1985 {
1986         intel_attach_force_audio_property(connector);
1987         intel_attach_broadcast_rgb_property(connector);
1988 }
1989
1990 void
1991 intel_dp_init(struct drm_device *dev, int output_reg)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         struct drm_connector *connector;
1995         struct intel_dp *intel_dp;
1996         struct intel_encoder *intel_encoder;
1997         struct intel_connector *intel_connector;
1998         const char *name = NULL;
1999         int type;
2000
2001         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2002         if (!intel_dp)
2003                 return;
2004
2005         intel_dp->output_reg = output_reg;
2006         intel_dp->dpms_mode = -1;
2007
2008         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2009         if (!intel_connector) {
2010                 kfree(intel_dp);
2011                 return;
2012         }
2013         intel_encoder = &intel_dp->base;
2014
2015         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2016                 if (intel_dpd_is_edp(dev))
2017                         intel_dp->is_pch_edp = true;
2018
2019         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2020                 type = DRM_MODE_CONNECTOR_eDP;
2021                 intel_encoder->type = INTEL_OUTPUT_EDP;
2022         } else {
2023                 type = DRM_MODE_CONNECTOR_DisplayPort;
2024                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2025         }
2026
2027         connector = &intel_connector->base;
2028         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2029         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2030
2031         connector->polled = DRM_CONNECTOR_POLL_HPD;
2032
2033         if (output_reg == DP_B || output_reg == PCH_DP_B)
2034                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2035         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2036                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2037         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2038                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2039
2040         if (is_edp(intel_dp))
2041                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2042
2043         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2044         connector->interlace_allowed = true;
2045         connector->doublescan_allowed = 0;
2046
2047         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2048                          DRM_MODE_ENCODER_TMDS);
2049         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2050
2051         intel_connector_attach_encoder(intel_connector, intel_encoder);
2052         drm_sysfs_connector_add(connector);
2053
2054         /* Set up the DDC bus. */
2055         switch (output_reg) {
2056                 case DP_A:
2057                         name = "DPDDC-A";
2058                         break;
2059                 case DP_B:
2060                 case PCH_DP_B:
2061                         dev_priv->hotplug_supported_mask |=
2062                                 HDMIB_HOTPLUG_INT_STATUS;
2063                         name = "DPDDC-B";
2064                         break;
2065                 case DP_C:
2066                 case PCH_DP_C:
2067                         dev_priv->hotplug_supported_mask |=
2068                                 HDMIC_HOTPLUG_INT_STATUS;
2069                         name = "DPDDC-C";
2070                         break;
2071                 case DP_D:
2072                 case PCH_DP_D:
2073                         dev_priv->hotplug_supported_mask |=
2074                                 HDMID_HOTPLUG_INT_STATUS;
2075                         name = "DPDDC-D";
2076                         break;
2077         }
2078
2079         intel_dp_i2c_init(intel_dp, intel_connector, name);
2080
2081         /* Cache some DPCD data in the eDP case */
2082         if (is_edp(intel_dp)) {
2083                 bool ret;
2084                 u32 pp_on, pp_div;
2085
2086                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2087                 pp_div = I915_READ(PCH_PP_DIVISOR);
2088
2089                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2090                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2091                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2092                 dev_priv->panel_t12 = pp_div & 0xf;
2093                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2094
2095                 ironlake_edp_panel_vdd_on(intel_dp);
2096                 ret = intel_dp_get_dpcd(intel_dp);
2097                 ironlake_edp_panel_vdd_off(intel_dp);
2098                 if (ret) {
2099                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2100                                 dev_priv->no_aux_handshake =
2101                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2102                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2103                 } else {
2104                         /* if this fails, presume the device is a ghost */
2105                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2106                         intel_dp_encoder_destroy(&intel_dp->base.base);
2107                         intel_dp_destroy(&intel_connector->base);
2108                         return;
2109                 }
2110         }
2111
2112         intel_encoder->hot_plug = intel_dp_hot_plug;
2113
2114         if (is_edp(intel_dp)) {
2115                 dev_priv->int_edp_connector = connector;
2116                 intel_panel_setup_backlight(dev);
2117         }
2118
2119         intel_dp_add_properties(intel_dp, connector);
2120
2121         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2122          * 0xd.  Failure to do so will result in spurious interrupts being
2123          * generated on the port when a cable is not attached.
2124          */
2125         if (IS_G4X(dev) && !IS_GM45(dev)) {
2126                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2127                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2128         }
2129 }