drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[8];
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59         bool is_pch_edp;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68 };
  69
  70 /**
  71  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  72  * @intel_dp: DP struct
  73  *
  74  * If a CPU or PCH DP output is attached to an eDP panel, this function
  75  * will return true, and false otherwise.
  76  */
  77 static bool is_edp(struct intel_dp *intel_dp)
  78 {
  79         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  80 }
  81
  82 /**
  83  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  84  * @intel_dp: DP struct
  85  *
  86  * Returns true if the given DP struct corresponds to a PCH DP port attached
  87  * to an eDP panel, false otherwise.  Helpful for determining whether we
  88  * may need FDI resources for a given DP output or not.
  89  */
  90 static bool is_pch_edp(struct intel_dp *intel_dp)
  91 {
  92         return intel_dp->is_pch_edp;
  93 }
  94
  95 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  96 {
  97         return container_of(encoder, struct intel_dp, base.base);
  98 }
  99
 100 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 101 {
 102         return container_of(intel_attached_encoder(connector),
 103                             struct intel_dp, base);
 104 }
 105
 106 /**
 107  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 108  * @encoder: DRM encoder
 109  *
 110  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 111  * by intel_display.c.
 112  */
 113 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 114 {
 115         struct intel_dp *intel_dp;
 116
 117         if (!encoder)
 118                 return false;
 119
 120         intel_dp = enc_to_intel_dp(encoder);
 121
 122         return is_pch_edp(intel_dp);
 123 }
 124
 125 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 126 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 127 static void intel_dp_link_down(struct intel_dp *intel_dp);
 128
 129 void
 130 intel_edp_link_config (struct intel_encoder *intel_encoder,
 131                        int *lane_num, int *link_bw)
 132 {
 133         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 134
 135         *lane_num = intel_dp->lane_count;
 136         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 137                 *link_bw = 162000;
 138         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 139                 *link_bw = 270000;
 140 }
 141
 142 static int
 143 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 144 {
 145         int max_lane_count = 4;
 146
 147         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 148                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 149                 switch (max_lane_count) {
 150                 case 1: case 2: case 4:
 151                         break;
 152                 default:
 153                         max_lane_count = 4;
 154                 }
 155         }
 156         return max_lane_count;
 157 }
 158
 159 static int
 160 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 161 {
 162         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 163
 164         switch (max_link_bw) {
 165         case DP_LINK_BW_1_62:
 166         case DP_LINK_BW_2_7:
 167                 break;
 168         default:
 169                 max_link_bw = DP_LINK_BW_1_62;
 170                 break;
 171         }
 172         return max_link_bw;
 173 }
 174
 175 static int
 176 intel_dp_link_clock(uint8_t link_bw)
 177 {
 178         if (link_bw == DP_LINK_BW_2_7)
 179                 return 270000;
 180         else
 181                 return 162000;
 182 }
 183
 184 /* I think this is a fiction */
 185 static int
 186 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 187 {
 188         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 190         int bpp = 24;
 191
 192         if (intel_crtc)
 193                 bpp = intel_crtc->bpp;
 194
 195         return (pixel_clock * bpp + 7) / 8;
 196 }
 197
 198 static int
 199 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 200 {
 201         return (max_link_clock * max_lanes * 8) / 10;
 202 }
 203
 204 static int
 205 intel_dp_mode_valid(struct drm_connector *connector,
 206                     struct drm_display_mode *mode)
 207 {
 208         struct intel_dp *intel_dp = intel_attached_dp(connector);
 209         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 210         int max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 213                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 214                         return MODE_PANEL;
 215
 216                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 217                         return MODE_PANEL;
 218         }
 219
 220         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 221            which are outside spec tolerances but somehow work by magic */
 222         if (!is_edp(intel_dp) &&
 223             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 224              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         return MODE_OK;
 231 }
 232
 233 static uint32_t
 234 pack_aux(uint8_t *src, int src_bytes)
 235 {
 236         int     i;
 237         uint32_t v = 0;
 238
 239         if (src_bytes > 4)
 240                 src_bytes = 4;
 241         for (i = 0; i < src_bytes; i++)
 242                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 243         return v;
 244 }
 245
 246 static void
 247 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 248 {
 249         int i;
 250         if (dst_bytes > 4)
 251                 dst_bytes = 4;
 252         for (i = 0; i < dst_bytes; i++)
 253                 dst[i] = src >> ((3-i) * 8);
 254 }
 255
 256 /* hrawclock is 1/4 the FSB frequency */
 257 static int
 258 intel_hrawclk(struct drm_device *dev)
 259 {
 260         struct drm_i915_private *dev_priv = dev->dev_private;
 261         uint32_t clkcfg;
 262
 263         clkcfg = I915_READ(CLKCFG);
 264         switch (clkcfg & CLKCFG_FSB_MASK) {
 265         case CLKCFG_FSB_400:
 266                 return 100;
 267         case CLKCFG_FSB_533:
 268                 return 133;
 269         case CLKCFG_FSB_667:
 270                 return 166;
 271         case CLKCFG_FSB_800:
 272                 return 200;
 273         case CLKCFG_FSB_1067:
 274                 return 266;
 275         case CLKCFG_FSB_1333:
 276                 return 333;
 277         /* these two are just a guess; one of them might be right */
 278         case CLKCFG_FSB_1600:
 279         case CLKCFG_FSB_1600_ALT:
 280                 return 400;
 281         default:
 282                 return 133;
 283         }
 284 }
 285
 286 static void
 287 intel_dp_check_edp(struct intel_dp *intel_dp)
 288 {
 289         struct drm_device *dev = intel_dp->base.base.dev;
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         u32 pp_status, pp_control;
 292         if (!is_edp(intel_dp))
 293                 return;
 294         pp_status = I915_READ(PCH_PP_STATUS);
 295         pp_control = I915_READ(PCH_PP_CONTROL);
 296         if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) {
 297                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 298                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 299                               pp_status,
 300                               I915_READ(PCH_PP_CONTROL));
 301         }
 302 }
 303
 304 static int
 305 intel_dp_aux_ch(struct intel_dp *intel_dp,
 306                 uint8_t *send, int send_bytes,
 307                 uint8_t *recv, int recv_size)
 308 {
 309         uint32_t output_reg = intel_dp->output_reg;
 310         struct drm_device *dev = intel_dp->base.base.dev;
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         uint32_t ch_ctl = output_reg + 0x10;
 313         uint32_t ch_data = ch_ctl + 4;
 314         int i;
 315         int recv_bytes;
 316         uint32_t status;
 317         uint32_t aux_clock_divider;
 318         int try, precharge;
 319
 320         intel_dp_check_edp(intel_dp);
 321         /* The clock divider is based off the hrawclk,
 322          * and would like to run at 2MHz. So, take the
 323          * hrawclk value and divide by 2 and use that
 324          *
 325          * Note that PCH attached eDP panels should use a 125MHz input
 326          * clock divider.
 327          */
 328         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 329                 if (IS_GEN6(dev))
 330                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 331                 else
 332                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 333         } else if (HAS_PCH_SPLIT(dev))
 334                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 335         else
 336                 aux_clock_divider = intel_hrawclk(dev) / 2;
 337
 338         if (IS_GEN6(dev))
 339                 precharge = 3;
 340         else
 341                 precharge = 5;
 342
 343         /* Try to wait for any previous AUX channel activity */
 344         for (try = 0; try < 3; try++) {
 345                 status = I915_READ(ch_ctl);
 346                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 347                         break;
 348                 msleep(1);
 349         }
 350
 351         if (try == 3) {
 352                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 353                      I915_READ(ch_ctl));
 354                 return -EBUSY;
 355         }
 356
 357         /* Must try at least 3 times according to DP spec */
 358         for (try = 0; try < 5; try++) {
 359                 /* Load the send data into the aux channel data registers */
 360                 for (i = 0; i < send_bytes; i += 4)
 361                         I915_WRITE(ch_data + i,
 362                                    pack_aux(send + i, send_bytes - i));
 363
 364                 /* Send the command and wait for it to complete */
 365                 I915_WRITE(ch_ctl,
 366                            DP_AUX_CH_CTL_SEND_BUSY |
 367                            DP_AUX_CH_CTL_TIME_OUT_400us |
 368                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 369                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 370                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 371                            DP_AUX_CH_CTL_DONE |
 372                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 373                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 374                 for (;;) {
 375                         status = I915_READ(ch_ctl);
 376                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 377                                 break;
 378                         udelay(100);
 379                 }
 380
 381                 /* Clear done status and any errors */
 382                 I915_WRITE(ch_ctl,
 383                            status |
 384                            DP_AUX_CH_CTL_DONE |
 385                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 386                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 387                 if (status & DP_AUX_CH_CTL_DONE)
 388                         break;
 389         }
 390
 391         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 392                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 393                 return -EBUSY;
 394         }
 395
 396         /* Check for timeout or receive error.
 397          * Timeouts occur when the sink is not connected
 398          */
 399         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 400                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 401                 return -EIO;
 402         }
 403
 404         /* Timeouts occur when the device isn't connected, so they're
 405          * "normal" -- don't fill the kernel log with these */
 406         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 407                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 408                 return -ETIMEDOUT;
 409         }
 410
 411         /* Unload any bytes sent back from the other side */
 412         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 413                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 414         if (recv_bytes > recv_size)
 415                 recv_bytes = recv_size;
 416
 417         for (i = 0; i < recv_bytes; i += 4)
 418                 unpack_aux(I915_READ(ch_data + i),
 419                            recv + i, recv_bytes - i);
 420
 421         return recv_bytes;
 422 }
 423
 424 /* Write data to the aux channel in native mode */
 425 static int
 426 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 427                           uint16_t address, uint8_t *send, int send_bytes)
 428 {
 429         int ret;
 430         uint8_t msg[20];
 431         int msg_bytes;
 432         uint8_t ack;
 433
 434         intel_dp_check_edp(intel_dp);
 435         if (send_bytes > 16)
 436                 return -1;
 437         msg[0] = AUX_NATIVE_WRITE << 4;
 438         msg[1] = address >> 8;
 439         msg[2] = address & 0xff;
 440         msg[3] = send_bytes - 1;
 441         memcpy(&msg[4], send, send_bytes);
 442         msg_bytes = send_bytes + 4;
 443         for (;;) {
 444                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 445                 if (ret < 0)
 446                         return ret;
 447                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 448                         break;
 449                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 450                         udelay(100);
 451                 else
 452                         return -EIO;
 453         }
 454         return send_bytes;
 455 }
 456
 457 /* Write a single byte to the aux channel in native mode */
 458 static int
 459 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 460                             uint16_t address, uint8_t byte)
 461 {
 462         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 463 }
 464
 465 /* read bytes from a native aux channel */
 466 static int
 467 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 468                          uint16_t address, uint8_t *recv, int recv_bytes)
 469 {
 470         uint8_t msg[4];
 471         int msg_bytes;
 472         uint8_t reply[20];
 473         int reply_bytes;
 474         uint8_t ack;
 475         int ret;
 476
 477         intel_dp_check_edp(intel_dp);
 478         msg[0] = AUX_NATIVE_READ << 4;
 479         msg[1] = address >> 8;
 480         msg[2] = address & 0xff;
 481         msg[3] = recv_bytes - 1;
 482
 483         msg_bytes = 4;
 484         reply_bytes = recv_bytes + 1;
 485
 486         for (;;) {
 487                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 488                                       reply, reply_bytes);
 489                 if (ret == 0)
 490                         return -EPROTO;
 491                 if (ret < 0)
 492                         return ret;
 493                 ack = reply[0];
 494                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 495                         memcpy(recv, reply + 1, ret - 1);
 496                         return ret - 1;
 497                 }
 498                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 499                         udelay(100);
 500                 else
 501                         return -EIO;
 502         }
 503 }
 504
 505 static int
 506 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 507                     uint8_t write_byte, uint8_t *read_byte)
 508 {
 509         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 510         struct intel_dp *intel_dp = container_of(adapter,
 511                                                 struct intel_dp,
 512                                                 adapter);
 513         uint16_t address = algo_data->address;
 514         uint8_t msg[5];
 515         uint8_t reply[2];
 516         unsigned retry;
 517         int msg_bytes;
 518         int reply_bytes;
 519         int ret;
 520
 521         intel_dp_check_edp(intel_dp);
 522         /* Set up the command byte */
 523         if (mode & MODE_I2C_READ)
 524                 msg[0] = AUX_I2C_READ << 4;
 525         else
 526                 msg[0] = AUX_I2C_WRITE << 4;
 527
 528         if (!(mode & MODE_I2C_STOP))
 529                 msg[0] |= AUX_I2C_MOT << 4;
 530
 531         msg[1] = address >> 8;
 532         msg[2] = address;
 533
 534         switch (mode) {
 535         case MODE_I2C_WRITE:
 536                 msg[3] = 0;
 537                 msg[4] = write_byte;
 538                 msg_bytes = 5;
 539                 reply_bytes = 1;
 540                 break;
 541         case MODE_I2C_READ:
 542                 msg[3] = 0;
 543                 msg_bytes = 4;
 544                 reply_bytes = 2;
 545                 break;
 546         default:
 547                 msg_bytes = 3;
 548                 reply_bytes = 1;
 549                 break;
 550         }
 551
 552         for (retry = 0; retry < 5; retry++) {
 553                 ret = intel_dp_aux_ch(intel_dp,
 554                                       msg, msg_bytes,
 555                                       reply, reply_bytes);
 556                 if (ret < 0) {
 557                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 558                         return ret;
 559                 }
 560
 561                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 562                 case AUX_NATIVE_REPLY_ACK:
 563                         /* I2C-over-AUX Reply field is only valid
 564                          * when paired with AUX ACK.
 565                          */
 566                         break;
 567                 case AUX_NATIVE_REPLY_NACK:
 568                         DRM_DEBUG_KMS("aux_ch native nack\n");
 569                         return -EREMOTEIO;
 570                 case AUX_NATIVE_REPLY_DEFER:
 571                         udelay(100);
 572                         continue;
 573                 default:
 574                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 575                                   reply[0]);
 576                         return -EREMOTEIO;
 577                 }
 578
 579                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 580                 case AUX_I2C_REPLY_ACK:
 581                         if (mode == MODE_I2C_READ) {
 582                                 *read_byte = reply[1];
 583                         }
 584                         return reply_bytes - 1;
 585                 case AUX_I2C_REPLY_NACK:
 586                         DRM_DEBUG_KMS("aux_i2c nack\n");
 587                         return -EREMOTEIO;
 588                 case AUX_I2C_REPLY_DEFER:
 589                         DRM_DEBUG_KMS("aux_i2c defer\n");
 590                         udelay(100);
 591                         break;
 592                 default:
 593                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 594                         return -EREMOTEIO;
 595                 }
 596         }
 597
 598         DRM_ERROR("too many retries, giving up\n");
 599         return -EREMOTEIO;
 600 }
 601
 602 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 603 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp);
 604
 605 static int
 606 intel_dp_i2c_init(struct intel_dp *intel_dp,
 607                   struct intel_connector *intel_connector, const char *name)
 608 {
 609         int     ret;
 610
 611         DRM_DEBUG_KMS("i2c_init %s\n", name);
 612         intel_dp->algo.running = false;
 613         intel_dp->algo.address = 0;
 614         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 615
 616         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 617         intel_dp->adapter.owner = THIS_MODULE;
 618         intel_dp->adapter.class = I2C_CLASS_DDC;
 619         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 620         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 621         intel_dp->adapter.algo_data = &intel_dp->algo;
 622         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 623
 624         ironlake_edp_panel_vdd_on(intel_dp);
 625         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 626         ironlake_edp_panel_vdd_off(intel_dp);
 627         return ret;
 628 }
 629
 630 static bool
 631 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 632                     struct drm_display_mode *adjusted_mode)
 633 {
 634         struct drm_device *dev = encoder->dev;
 635         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 636         int lane_count, clock;
 637         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 638         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 639         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 640
 641         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 642                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 643                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 644                                         mode, adjusted_mode);
 645                 /*
 646                  * the mode->clock is used to calculate the Data&Link M/N
 647                  * of the pipe. For the eDP the fixed clock should be used.
 648                  */
 649                 mode->clock = intel_dp->panel_fixed_mode->clock;
 650         }
 651
 652         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 653                 for (clock = 0; clock <= max_clock; clock++) {
 654                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 655
 656                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 657                                         <= link_avail) {
 658                                 intel_dp->link_bw = bws[clock];
 659                                 intel_dp->lane_count = lane_count;
 660                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 661                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 662                                                 "count %d clock %d\n",
 663                                        intel_dp->link_bw, intel_dp->lane_count,
 664                                        adjusted_mode->clock);
 665                                 return true;
 666                         }
 667                 }
 668         }
 669
 670         if (is_edp(intel_dp)) {
 671                 /* okay we failed just pick the highest */
 672                 intel_dp->lane_count = max_lane_count;
 673                 intel_dp->link_bw = bws[max_clock];
 674                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 675                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 676                               "count %d clock %d\n",
 677                               intel_dp->link_bw, intel_dp->lane_count,
 678                               adjusted_mode->clock);
 679
 680                 return true;
 681         }
 682
 683         return false;
 684 }
 685
 686 struct intel_dp_m_n {
 687         uint32_t        tu;
 688         uint32_t        gmch_m;
 689         uint32_t        gmch_n;
 690         uint32_t        link_m;
 691         uint32_t        link_n;
 692 };
 693
 694 static void
 695 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 696 {
 697         while (*num > 0xffffff || *den > 0xffffff) {
 698                 *num >>= 1;
 699                 *den >>= 1;
 700         }
 701 }
 702
 703 static void
 704 intel_dp_compute_m_n(int bpp,
 705                      int nlanes,
 706                      int pixel_clock,
 707                      int link_clock,
 708                      struct intel_dp_m_n *m_n)
 709 {
 710         m_n->tu = 64;
 711         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 712         m_n->gmch_n = link_clock * nlanes;
 713         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 714         m_n->link_m = pixel_clock;
 715         m_n->link_n = link_clock;
 716         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 717 }
 718
 719 void
 720 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 721                  struct drm_display_mode *adjusted_mode)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         struct drm_mode_config *mode_config = &dev->mode_config;
 725         struct drm_encoder *encoder;
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728         int lane_count = 4;
 729         struct intel_dp_m_n m_n;
 730         int pipe = intel_crtc->pipe;
 731
 732         /*
 733          * Find the lane count in the intel_encoder private
 734          */
 735         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 736                 struct intel_dp *intel_dp;
 737
 738                 if (encoder->crtc != crtc)
 739                         continue;
 740
 741                 intel_dp = enc_to_intel_dp(encoder);
 742                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 743                         lane_count = intel_dp->lane_count;
 744                         break;
 745                 } else if (is_edp(intel_dp)) {
 746                         lane_count = dev_priv->edp.lanes;
 747                         break;
 748                 }
 749         }
 750
 751         /*
 752          * Compute the GMCH and Link ratios. The '3' here is
 753          * the number of bytes_per_pixel post-LUT, which we always
 754          * set up for 8-bits of R/G/B, or 3 bytes total.
 755          */
 756         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 757                              mode->clock, adjusted_mode->clock, &m_n);
 758
 759         if (HAS_PCH_SPLIT(dev)) {
 760                 I915_WRITE(TRANSDATA_M1(pipe),
 761                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 762                            m_n.gmch_m);
 763                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 764                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 765                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 766         } else {
 767                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 768                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 769                            m_n.gmch_m);
 770                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 771                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 772                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 773         }
 774 }
 775
 776 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 777 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 778
 779 static void
 780 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 781                   struct drm_display_mode *adjusted_mode)
 782 {
 783         struct drm_device *dev = encoder->dev;
 784         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 785         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 787
 788         /* Turn on the eDP PLL if needed */
 789         if (is_edp(intel_dp)) {
 790                 if (!is_pch_edp(intel_dp))
 791                         ironlake_edp_pll_on(encoder);
 792                 else
 793                         ironlake_edp_pll_off(encoder);
 794         }
 795
 796         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 797         intel_dp->DP |= intel_dp->color_range;
 798
 799         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 800                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 801         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 802                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 803
 804         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 805                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 806         else
 807                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 808
 809         switch (intel_dp->lane_count) {
 810         case 1:
 811                 intel_dp->DP |= DP_PORT_WIDTH_1;
 812                 break;
 813         case 2:
 814                 intel_dp->DP |= DP_PORT_WIDTH_2;
 815                 break;
 816         case 4:
 817                 intel_dp->DP |= DP_PORT_WIDTH_4;
 818                 break;
 819         }
 820         if (intel_dp->has_audio)
 821                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 822
 823         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 824         intel_dp->link_configuration[0] = intel_dp->link_bw;
 825         intel_dp->link_configuration[1] = intel_dp->lane_count;
 826         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 827
 828         /*
 829          * Check for DPCD version > 1.1 and enhanced framing support
 830          */
 831         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 832             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 833                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 834                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 835         }
 836
 837         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 838         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 839                 intel_dp->DP |= DP_PIPEB_SELECT;
 840
 841         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 842                 /* don't miss out required setting for eDP */
 843                 intel_dp->DP |= DP_PLL_ENABLE;
 844                 if (adjusted_mode->clock < 200000)
 845                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 846                 else
 847                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 848         }
 849 }
 850
 851 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 852 {
 853         struct drm_device *dev = intel_dp->base.base.dev;
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         u32 pp, pp_status;
 856
 857         if (!is_edp(intel_dp))
 858                 return;
 859         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 860         /*
 861          * If the panel wasn't on, make sure there's not a currently
 862          * active PP sequence before enabling AUX VDD.
 863          */
 864         pp_status = I915_READ(PCH_PP_STATUS);
 865
 866         pp = I915_READ(PCH_PP_CONTROL);
 867         pp &= ~PANEL_UNLOCK_MASK;
 868         pp |= PANEL_UNLOCK_REGS;
 869         pp |= EDP_FORCE_VDD;
 870         I915_WRITE(PCH_PP_CONTROL, pp);
 871         POSTING_READ(PCH_PP_CONTROL);
 872         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 873                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 874         if (!(pp_status & PP_ON)) {
 875                 msleep(intel_dp->panel_power_up_delay);
 876                 DRM_DEBUG_KMS("eDP VDD was not on\n");
 877         }
 878 }
 879
 880 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 881 {
 882         struct drm_device *dev = intel_dp->base.base.dev;
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         u32 pp;
 885
 886         if (!is_edp(intel_dp))
 887                 return;
 888         DRM_DEBUG_KMS("Turn eDP VDD off\n");
 889         pp = I915_READ(PCH_PP_CONTROL);
 890         pp &= ~PANEL_UNLOCK_MASK;
 891         pp |= PANEL_UNLOCK_REGS;
 892         pp &= ~EDP_FORCE_VDD;
 893         I915_WRITE(PCH_PP_CONTROL, pp);
 894         POSTING_READ(PCH_PP_CONTROL);
 895
 896         /* Make sure sequencer is idle before allowing subsequent activity */
 897         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 898                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 899         msleep(intel_dp->panel_power_cycle_delay);
 900 }
 901
 902 /* Returns true if the panel was already on when called */
 903 static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
 904 {
 905         struct drm_device *dev = intel_dp->base.base.dev;
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 908
 909         if (!is_edp(intel_dp))
 910                 return true;
 911         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 912                 return;
 913
 914         pp = I915_READ(PCH_PP_CONTROL);
 915         pp &= ~PANEL_UNLOCK_MASK;
 916         pp |= PANEL_UNLOCK_REGS;
 917
 918         /* ILK workaround: disable reset around power sequence */
 919         pp &= ~PANEL_POWER_RESET;
 920         I915_WRITE(PCH_PP_CONTROL, pp);
 921         POSTING_READ(PCH_PP_CONTROL);
 922
 923         pp |= POWER_TARGET_ON;
 924         I915_WRITE(PCH_PP_CONTROL, pp);
 925         POSTING_READ(PCH_PP_CONTROL);
 926
 927         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 928                      5000))
 929                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 930                           I915_READ(PCH_PP_STATUS));
 931
 932         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 933         I915_WRITE(PCH_PP_CONTROL, pp);
 934         POSTING_READ(PCH_PP_CONTROL);
 935 }
 936
 937 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
 938 {
 939         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 940         struct drm_device *dev = encoder->dev;
 941         struct drm_i915_private *dev_priv = dev->dev_private;
 942         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 943                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 944
 945         if (!is_edp(intel_dp))
 946                 return;
 947         pp = I915_READ(PCH_PP_CONTROL);
 948         pp &= ~PANEL_UNLOCK_MASK;
 949         pp |= PANEL_UNLOCK_REGS;
 950
 951         /* ILK workaround: disable reset around power sequence */
 952         pp &= ~PANEL_POWER_RESET;
 953         I915_WRITE(PCH_PP_CONTROL, pp);
 954         POSTING_READ(PCH_PP_CONTROL);
 955
 956         pp &= ~POWER_TARGET_ON;
 957         I915_WRITE(PCH_PP_CONTROL, pp);
 958         POSTING_READ(PCH_PP_CONTROL);
 959         msleep(intel_dp->panel_power_cycle_delay);
 960
 961         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 962                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 963                           I915_READ(PCH_PP_STATUS));
 964
 965         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 966         I915_WRITE(PCH_PP_CONTROL, pp);
 967         POSTING_READ(PCH_PP_CONTROL);
 968 }
 969
 970 static void ironlake_edp_backlight_on (struct intel_dp *intel_dp)
 971 {
 972         struct drm_device *dev = intel_dp->base.base.dev;
 973         struct drm_i915_private *dev_priv = dev->dev_private;
 974         u32 pp;
 975
 976         if (!is_edp(intel_dp))
 977                 return;
 978
 979         DRM_DEBUG_KMS("\n");
 980         /*
 981          * If we enable the backlight right away following a panel power
 982          * on, we may see slight flicker as the panel syncs with the eDP
 983          * link.  So delay a bit to make sure the image is solid before
 984          * allowing it to appear.
 985          */
 986         msleep(intel_dp->backlight_on_delay);
 987         pp = I915_READ(PCH_PP_CONTROL);
 988         pp &= ~PANEL_UNLOCK_MASK;
 989         pp |= PANEL_UNLOCK_REGS;
 990         pp |= EDP_BLC_ENABLE;
 991         I915_WRITE(PCH_PP_CONTROL, pp);
 992         POSTING_READ(PCH_PP_CONTROL);
 993 }
 994
 995 static void ironlake_edp_backlight_off (struct intel_dp *intel_dp)
 996 {
 997         struct drm_device *dev = intel_dp->base.base.dev;
 998         struct drm_i915_private *dev_priv = dev->dev_private;
 999         u32 pp;
1000
1001         if (!is_edp(intel_dp))
1002                 return;
1003
1004         DRM_DEBUG_KMS("\n");
1005         pp = I915_READ(PCH_PP_CONTROL);
1006         pp &= ~PANEL_UNLOCK_MASK;
1007         pp |= PANEL_UNLOCK_REGS;
1008         pp &= ~EDP_BLC_ENABLE;
1009         I915_WRITE(PCH_PP_CONTROL, pp);
1010         POSTING_READ(PCH_PP_CONTROL);
1011         msleep(intel_dp->backlight_off_delay);
1012 }
1013
1014 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1015 {
1016         struct drm_device *dev = encoder->dev;
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         u32 dpa_ctl;
1019
1020         DRM_DEBUG_KMS("\n");
1021         dpa_ctl = I915_READ(DP_A);
1022         dpa_ctl |= DP_PLL_ENABLE;
1023         I915_WRITE(DP_A, dpa_ctl);
1024         POSTING_READ(DP_A);
1025         udelay(200);
1026 }
1027
1028 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1029 {
1030         struct drm_device *dev = encoder->dev;
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         u32 dpa_ctl;
1033
1034         dpa_ctl = I915_READ(DP_A);
1035         dpa_ctl &= ~DP_PLL_ENABLE;
1036         I915_WRITE(DP_A, dpa_ctl);
1037         POSTING_READ(DP_A);
1038         udelay(200);
1039 }
1040
1041 /* If the sink supports it, try to set the power state appropriately */
1042 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1043 {
1044         int ret, i;
1045
1046         /* Should have a valid DPCD by this point */
1047         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1048                 return;
1049
1050         if (mode != DRM_MODE_DPMS_ON) {
1051                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1052                                                   DP_SET_POWER_D3);
1053                 if (ret != 1)
1054                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1055         } else {
1056                 /*
1057                  * When turning on, we need to retry for 1ms to give the sink
1058                  * time to wake up.
1059                  */
1060                 for (i = 0; i < 3; i++) {
1061                         ret = intel_dp_aux_native_write_1(intel_dp,
1062                                                           DP_SET_POWER,
1063                                                           DP_SET_POWER_D0);
1064                         if (ret == 1)
1065                                 break;
1066                         msleep(1);
1067                 }
1068         }
1069 }
1070
1071 static void intel_dp_prepare(struct drm_encoder *encoder)
1072 {
1073         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1074
1075         /* Wake up the sink first */
1076         ironlake_edp_panel_vdd_on(intel_dp);
1077         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1078         ironlake_edp_panel_vdd_off(intel_dp);
1079
1080         /* Make sure the panel is off before trying to
1081          * change the mode
1082          */
1083         ironlake_edp_backlight_off(intel_dp);
1084         intel_dp_link_down(intel_dp);
1085         ironlake_edp_panel_off(encoder);
1086 }
1087
1088 static void intel_dp_commit(struct drm_encoder *encoder)
1089 {
1090         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1091
1092         ironlake_edp_panel_vdd_on(intel_dp);
1093         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1094         intel_dp_start_link_train(intel_dp);
1095         ironlake_edp_panel_on(intel_dp);
1096         ironlake_edp_panel_vdd_off(intel_dp);
1097         intel_dp_complete_link_train(intel_dp);
1098         ironlake_edp_backlight_on(intel_dp);
1099
1100         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1101 }
1102
1103 static void
1104 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1105 {
1106         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1107         struct drm_device *dev = encoder->dev;
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1110
1111         if (mode != DRM_MODE_DPMS_ON) {
1112                 ironlake_edp_panel_vdd_on(intel_dp);
1113                 if (is_edp(intel_dp))
1114                         ironlake_edp_backlight_off(intel_dp);
1115                 intel_dp_sink_dpms(intel_dp, mode);
1116                 intel_dp_link_down(intel_dp);
1117                 ironlake_edp_panel_off(encoder);
1118                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1119                         ironlake_edp_pll_off(encoder);
1120                 ironlake_edp_panel_vdd_off(intel_dp);
1121         } else {
1122                 ironlake_edp_panel_vdd_on(intel_dp);
1123                 intel_dp_sink_dpms(intel_dp, mode);
1124                 if (!(dp_reg & DP_PORT_EN)) {
1125                         intel_dp_start_link_train(intel_dp);
1126                         ironlake_edp_panel_on(intel_dp);
1127                         ironlake_edp_panel_vdd_off(intel_dp);
1128                         intel_dp_complete_link_train(intel_dp);
1129                         ironlake_edp_backlight_on(intel_dp);
1130                 } else
1131                         ironlake_edp_panel_vdd_off(intel_dp);
1132         }
1133         intel_dp->dpms_mode = mode;
1134 }
1135
1136 /*
1137  * Native read with retry for link status and receiver capability reads for
1138  * cases where the sink may still be asleep.
1139  */
1140 static bool
1141 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1142                                uint8_t *recv, int recv_bytes)
1143 {
1144         int ret, i;
1145
1146         /*
1147          * Sinks are *supposed* to come up within 1ms from an off state,
1148          * but we're also supposed to retry 3 times per the spec.
1149          */
1150         for (i = 0; i < 3; i++) {
1151                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1152                                                recv_bytes);
1153                 if (ret == recv_bytes)
1154                         return true;
1155                 msleep(1);
1156         }
1157
1158         return false;
1159 }
1160
1161 /*
1162  * Fetch AUX CH registers 0x202 - 0x207 which contain
1163  * link status information
1164  */
1165 static bool
1166 intel_dp_get_link_status(struct intel_dp *intel_dp)
1167 {
1168         return intel_dp_aux_native_read_retry(intel_dp,
1169                                               DP_LANE0_1_STATUS,
1170                                               intel_dp->link_status,
1171                                               DP_LINK_STATUS_SIZE);
1172 }
1173
1174 static uint8_t
1175 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1176                      int r)
1177 {
1178         return link_status[r - DP_LANE0_1_STATUS];
1179 }
1180
1181 static uint8_t
1182 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1183                                  int lane)
1184 {
1185         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1186         int         s = ((lane & 1) ?
1187                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1188                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1189         uint8_t l = intel_dp_link_status(link_status, i);
1190
1191         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1192 }
1193
1194 static uint8_t
1195 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1196                                       int lane)
1197 {
1198         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1199         int         s = ((lane & 1) ?
1200                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1201                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1202         uint8_t l = intel_dp_link_status(link_status, i);
1203
1204         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1205 }
1206
1207
1208 #if 0
1209 static char     *voltage_names[] = {
1210         "0.4V", "0.6V", "0.8V", "1.2V"
1211 };
1212 static char     *pre_emph_names[] = {
1213         "0dB", "3.5dB", "6dB", "9.5dB"
1214 };
1215 static char     *link_train_names[] = {
1216         "pattern 1", "pattern 2", "idle", "off"
1217 };
1218 #endif
1219
1220 /*
1221  * These are source-specific values; current Intel hardware supports
1222  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1223  */
1224 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1225
1226 static uint8_t
1227 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1228 {
1229         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1230         case DP_TRAIN_VOLTAGE_SWING_400:
1231                 return DP_TRAIN_PRE_EMPHASIS_6;
1232         case DP_TRAIN_VOLTAGE_SWING_600:
1233                 return DP_TRAIN_PRE_EMPHASIS_6;
1234         case DP_TRAIN_VOLTAGE_SWING_800:
1235                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1236         case DP_TRAIN_VOLTAGE_SWING_1200:
1237         default:
1238                 return DP_TRAIN_PRE_EMPHASIS_0;
1239         }
1240 }
1241
1242 static void
1243 intel_get_adjust_train(struct intel_dp *intel_dp)
1244 {
1245         uint8_t v = 0;
1246         uint8_t p = 0;
1247         int lane;
1248
1249         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1250                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1251                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1252
1253                 if (this_v > v)
1254                         v = this_v;
1255                 if (this_p > p)
1256                         p = this_p;
1257         }
1258
1259         if (v >= I830_DP_VOLTAGE_MAX)
1260                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1261
1262         if (p >= intel_dp_pre_emphasis_max(v))
1263                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1264
1265         for (lane = 0; lane < 4; lane++)
1266                 intel_dp->train_set[lane] = v | p;
1267 }
1268
1269 static uint32_t
1270 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1271 {
1272         uint32_t        signal_levels = 0;
1273
1274         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1275         case DP_TRAIN_VOLTAGE_SWING_400:
1276         default:
1277                 signal_levels |= DP_VOLTAGE_0_4;
1278                 break;
1279         case DP_TRAIN_VOLTAGE_SWING_600:
1280                 signal_levels |= DP_VOLTAGE_0_6;
1281                 break;
1282         case DP_TRAIN_VOLTAGE_SWING_800:
1283                 signal_levels |= DP_VOLTAGE_0_8;
1284                 break;
1285         case DP_TRAIN_VOLTAGE_SWING_1200:
1286                 signal_levels |= DP_VOLTAGE_1_2;
1287                 break;
1288         }
1289         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1290         case DP_TRAIN_PRE_EMPHASIS_0:
1291         default:
1292                 signal_levels |= DP_PRE_EMPHASIS_0;
1293                 break;
1294         case DP_TRAIN_PRE_EMPHASIS_3_5:
1295                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1296                 break;
1297         case DP_TRAIN_PRE_EMPHASIS_6:
1298                 signal_levels |= DP_PRE_EMPHASIS_6;
1299                 break;
1300         case DP_TRAIN_PRE_EMPHASIS_9_5:
1301                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1302                 break;
1303         }
1304         return signal_levels;
1305 }
1306
1307 /* Gen6's DP voltage swing and pre-emphasis control */
1308 static uint32_t
1309 intel_gen6_edp_signal_levels(uint8_t train_set)
1310 {
1311         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1312                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1313         switch (signal_levels) {
1314         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1315         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1316                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1317         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1318                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1319         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1320         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1321                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1322         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1323         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1324                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1325         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1326         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1327                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1328         default:
1329                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1330                               "0x%x\n", signal_levels);
1331                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1332         }
1333 }
1334
1335 static uint8_t
1336 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1337                       int lane)
1338 {
1339         int i = DP_LANE0_1_STATUS + (lane >> 1);
1340         int s = (lane & 1) * 4;
1341         uint8_t l = intel_dp_link_status(link_status, i);
1342
1343         return (l >> s) & 0xf;
1344 }
1345
1346 /* Check for clock recovery is done on all channels */
1347 static bool
1348 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1349 {
1350         int lane;
1351         uint8_t lane_status;
1352
1353         for (lane = 0; lane < lane_count; lane++) {
1354                 lane_status = intel_get_lane_status(link_status, lane);
1355                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1356                         return false;
1357         }
1358         return true;
1359 }
1360
1361 /* Check to see if channel eq is done on all channels */
1362 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1363                          DP_LANE_CHANNEL_EQ_DONE|\
1364                          DP_LANE_SYMBOL_LOCKED)
1365 static bool
1366 intel_channel_eq_ok(struct intel_dp *intel_dp)
1367 {
1368         uint8_t lane_align;
1369         uint8_t lane_status;
1370         int lane;
1371
1372         lane_align = intel_dp_link_status(intel_dp->link_status,
1373                                           DP_LANE_ALIGN_STATUS_UPDATED);
1374         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1375                 return false;
1376         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1377                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1378                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool
1385 intel_dp_set_link_train(struct intel_dp *intel_dp,
1386                         uint32_t dp_reg_value,
1387                         uint8_t dp_train_pat)
1388 {
1389         struct drm_device *dev = intel_dp->base.base.dev;
1390         struct drm_i915_private *dev_priv = dev->dev_private;
1391         int ret;
1392
1393         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1394         POSTING_READ(intel_dp->output_reg);
1395
1396         intel_dp_aux_native_write_1(intel_dp,
1397                                     DP_TRAINING_PATTERN_SET,
1398                                     dp_train_pat);
1399
1400         ret = intel_dp_aux_native_write(intel_dp,
1401                                         DP_TRAINING_LANE0_SET,
1402                                         intel_dp->train_set, 4);
1403         if (ret != 4)
1404                 return false;
1405
1406         return true;
1407 }
1408
1409 /* Enable corresponding port and start training pattern 1 */
1410 static void
1411 intel_dp_start_link_train(struct intel_dp *intel_dp)
1412 {
1413         struct drm_device *dev = intel_dp->base.base.dev;
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1416         int i;
1417         uint8_t voltage;
1418         bool clock_recovery = false;
1419         int tries;
1420         u32 reg;
1421         uint32_t DP = intel_dp->DP;
1422
1423         /*
1424          * On CPT we have to enable the port in training pattern 1, which
1425          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1426          * the port and wait for it to become active.
1427          */
1428         if (!HAS_PCH_CPT(dev)) {
1429                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1430                 POSTING_READ(intel_dp->output_reg);
1431                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1432         }
1433
1434         /* Write the link configuration data */
1435         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1436                                   intel_dp->link_configuration,
1437                                   DP_LINK_CONFIGURATION_SIZE);
1438
1439         DP |= DP_PORT_EN;
1440         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1441                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1442         else
1443                 DP &= ~DP_LINK_TRAIN_MASK;
1444         memset(intel_dp->train_set, 0, 4);
1445         voltage = 0xff;
1446         tries = 0;
1447         clock_recovery = false;
1448         for (;;) {
1449                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1450                 uint32_t    signal_levels;
1451                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1452                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1453                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1454                 } else {
1455                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1456                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1457                 }
1458
1459                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1460                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1461                 else
1462                         reg = DP | DP_LINK_TRAIN_PAT_1;
1463
1464                 if (!intel_dp_set_link_train(intel_dp, reg,
1465                                              DP_TRAINING_PATTERN_1 |
1466                                              DP_LINK_SCRAMBLING_DISABLE))
1467                         break;
1468                 /* Set training pattern 1 */
1469
1470                 udelay(100);
1471                 if (!intel_dp_get_link_status(intel_dp))
1472                         break;
1473
1474                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1475                         clock_recovery = true;
1476                         break;
1477                 }
1478
1479                 /* Check to see if we've tried the max voltage */
1480                 for (i = 0; i < intel_dp->lane_count; i++)
1481                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1482                                 break;
1483                 if (i == intel_dp->lane_count)
1484                         break;
1485
1486                 /* Check to see if we've tried the same voltage 5 times */
1487                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1488                         ++tries;
1489                         if (tries == 5)
1490                                 break;
1491                 } else
1492                         tries = 0;
1493                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1494
1495                 /* Compute new intel_dp->train_set as requested by target */
1496                 intel_get_adjust_train(intel_dp);
1497         }
1498
1499         intel_dp->DP = DP;
1500 }
1501
1502 static void
1503 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1504 {
1505         struct drm_device *dev = intel_dp->base.base.dev;
1506         struct drm_i915_private *dev_priv = dev->dev_private;
1507         bool channel_eq = false;
1508         int tries, cr_tries;
1509         u32 reg;
1510         uint32_t DP = intel_dp->DP;
1511
1512         /* channel equalization */
1513         tries = 0;
1514         cr_tries = 0;
1515         channel_eq = false;
1516         for (;;) {
1517                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1518                 uint32_t    signal_levels;
1519
1520                 if (cr_tries > 5) {
1521                         DRM_ERROR("failed to train DP, aborting\n");
1522                         intel_dp_link_down(intel_dp);
1523                         break;
1524                 }
1525
1526                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1527                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1528                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1529                 } else {
1530                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1531                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1532                 }
1533
1534                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1535                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1536                 else
1537                         reg = DP | DP_LINK_TRAIN_PAT_2;
1538
1539                 /* channel eq pattern */
1540                 if (!intel_dp_set_link_train(intel_dp, reg,
1541                                              DP_TRAINING_PATTERN_2 |
1542                                              DP_LINK_SCRAMBLING_DISABLE))
1543                         break;
1544
1545                 udelay(400);
1546                 if (!intel_dp_get_link_status(intel_dp))
1547                         break;
1548
1549                 /* Make sure clock is still ok */
1550                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1551                         intel_dp_start_link_train(intel_dp);
1552                         cr_tries++;
1553                         continue;
1554                 }
1555
1556                 if (intel_channel_eq_ok(intel_dp)) {
1557                         channel_eq = true;
1558                         break;
1559                 }
1560
1561                 /* Try 5 times, then try clock recovery if that fails */
1562                 if (tries > 5) {
1563                         intel_dp_link_down(intel_dp);
1564                         intel_dp_start_link_train(intel_dp);
1565                         tries = 0;
1566                         cr_tries++;
1567                         continue;
1568                 }
1569
1570                 /* Compute new intel_dp->train_set as requested by target */
1571                 intel_get_adjust_train(intel_dp);
1572                 ++tries;
1573         }
1574
1575         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1576                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1577         else
1578                 reg = DP | DP_LINK_TRAIN_OFF;
1579
1580         I915_WRITE(intel_dp->output_reg, reg);
1581         POSTING_READ(intel_dp->output_reg);
1582         intel_dp_aux_native_write_1(intel_dp,
1583                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1584 }
1585
1586 static void
1587 intel_dp_link_down(struct intel_dp *intel_dp)
1588 {
1589         struct drm_device *dev = intel_dp->base.base.dev;
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591         uint32_t DP = intel_dp->DP;
1592
1593         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1594                 return;
1595
1596         DRM_DEBUG_KMS("\n");
1597
1598         if (is_edp(intel_dp)) {
1599                 DP &= ~DP_PLL_ENABLE;
1600                 I915_WRITE(intel_dp->output_reg, DP);
1601                 POSTING_READ(intel_dp->output_reg);
1602                 udelay(100);
1603         }
1604
1605         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1606                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1607                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1608         } else {
1609                 DP &= ~DP_LINK_TRAIN_MASK;
1610                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1611         }
1612         POSTING_READ(intel_dp->output_reg);
1613
1614         msleep(17);
1615
1616         if (is_edp(intel_dp))
1617                 DP |= DP_LINK_TRAIN_OFF;
1618
1619         if (!HAS_PCH_CPT(dev) &&
1620             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1621                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1622
1623                 /* Hardware workaround: leaving our transcoder select
1624                  * set to transcoder B while it's off will prevent the
1625                  * corresponding HDMI output on transcoder A.
1626                  *
1627                  * Combine this with another hardware workaround:
1628                  * transcoder select bit can only be cleared while the
1629                  * port is enabled.
1630                  */
1631                 DP &= ~DP_PIPEB_SELECT;
1632                 I915_WRITE(intel_dp->output_reg, DP);
1633
1634                 /* Changes to enable or select take place the vblank
1635                  * after being written.
1636                  */
1637                 if (crtc == NULL) {
1638                         /* We can arrive here never having been attached
1639                          * to a CRTC, for instance, due to inheriting
1640                          * random state from the BIOS.
1641                          *
1642                          * If the pipe is not running, play safe and
1643                          * wait for the clocks to stabilise before
1644                          * continuing.
1645                          */
1646                         POSTING_READ(intel_dp->output_reg);
1647                         msleep(50);
1648                 } else
1649                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1650         }
1651
1652         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1653         POSTING_READ(intel_dp->output_reg);
1654         msleep(intel_dp->panel_power_down_delay);
1655 }
1656
1657 static bool
1658 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1659 {
1660         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1661                                            sizeof (intel_dp->dpcd)) &&
1662             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1663                 return true;
1664         }
1665
1666         return false;
1667 }
1668
1669 /*
1670  * According to DP spec
1671  * 5.1.2:
1672  *  1. Read DPCD
1673  *  2. Configure link according to Receiver Capabilities
1674  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1675  *  4. Check link status on receipt of hot-plug interrupt
1676  */
1677
1678 static void
1679 intel_dp_check_link_status(struct intel_dp *intel_dp)
1680 {
1681         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1682                 return;
1683
1684         if (!intel_dp->base.base.crtc)
1685                 return;
1686
1687         /* Try to read receiver status if the link appears to be up */
1688         if (!intel_dp_get_link_status(intel_dp)) {
1689                 intel_dp_link_down(intel_dp);
1690                 return;
1691         }
1692
1693         /* Now read the DPCD to see if it's actually running */
1694         if (!intel_dp_get_dpcd(intel_dp)) {
1695                 intel_dp_link_down(intel_dp);
1696                 return;
1697         }
1698
1699         if (!intel_channel_eq_ok(intel_dp)) {
1700                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1701                               drm_get_encoder_name(&intel_dp->base.base));
1702                 intel_dp_start_link_train(intel_dp);
1703                 intel_dp_complete_link_train(intel_dp);
1704         }
1705 }
1706
1707 static enum drm_connector_status
1708 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1709 {
1710         if (intel_dp_get_dpcd(intel_dp))
1711                 return connector_status_connected;
1712         return connector_status_disconnected;
1713 }
1714
1715 static enum drm_connector_status
1716 ironlake_dp_detect(struct intel_dp *intel_dp)
1717 {
1718         enum drm_connector_status status;
1719
1720         /* Can't disconnect eDP, but you can close the lid... */
1721         if (is_edp(intel_dp)) {
1722                 status = intel_panel_detect(intel_dp->base.base.dev);
1723                 if (status == connector_status_unknown)
1724                         status = connector_status_connected;
1725                 return status;
1726         }
1727
1728         return intel_dp_detect_dpcd(intel_dp);
1729 }
1730
1731 static enum drm_connector_status
1732 g4x_dp_detect(struct intel_dp *intel_dp)
1733 {
1734         struct drm_device *dev = intel_dp->base.base.dev;
1735         struct drm_i915_private *dev_priv = dev->dev_private;
1736         uint32_t temp, bit;
1737
1738         switch (intel_dp->output_reg) {
1739         case DP_B:
1740                 bit = DPB_HOTPLUG_INT_STATUS;
1741                 break;
1742         case DP_C:
1743                 bit = DPC_HOTPLUG_INT_STATUS;
1744                 break;
1745         case DP_D:
1746                 bit = DPD_HOTPLUG_INT_STATUS;
1747                 break;
1748         default:
1749                 return connector_status_unknown;
1750         }
1751
1752         temp = I915_READ(PORT_HOTPLUG_STAT);
1753
1754         if ((temp & bit) == 0)
1755                 return connector_status_disconnected;
1756
1757         return intel_dp_detect_dpcd(intel_dp);
1758 }
1759
1760 static struct edid *
1761 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1762 {
1763         struct intel_dp *intel_dp = intel_attached_dp(connector);
1764         struct edid     *edid;
1765
1766         ironlake_edp_panel_vdd_on(intel_dp);
1767         edid = drm_get_edid(connector, adapter);
1768         ironlake_edp_panel_vdd_off(intel_dp);
1769         return edid;
1770 }
1771
1772 static int
1773 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1774 {
1775         struct intel_dp *intel_dp = intel_attached_dp(connector);
1776         int     ret;
1777
1778         ironlake_edp_panel_vdd_on(intel_dp);
1779         ret = intel_ddc_get_modes(connector, adapter);
1780         ironlake_edp_panel_vdd_off(intel_dp);
1781         return ret;
1782 }
1783
1784
1785 /**
1786  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1787  *
1788  * \return true if DP port is connected.
1789  * \return false if DP port is disconnected.
1790  */
1791 static enum drm_connector_status
1792 intel_dp_detect(struct drm_connector *connector, bool force)
1793 {
1794         struct intel_dp *intel_dp = intel_attached_dp(connector);
1795         struct drm_device *dev = intel_dp->base.base.dev;
1796         enum drm_connector_status status;
1797         struct edid *edid = NULL;
1798
1799         intel_dp->has_audio = false;
1800
1801         if (HAS_PCH_SPLIT(dev))
1802                 status = ironlake_dp_detect(intel_dp);
1803         else
1804                 status = g4x_dp_detect(intel_dp);
1805
1806         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1807                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1808                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1809                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1810
1811         if (status != connector_status_connected)
1812                 return status;
1813
1814         if (intel_dp->force_audio) {
1815                 intel_dp->has_audio = intel_dp->force_audio > 0;
1816         } else {
1817                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1818                 if (edid) {
1819                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1820                         connector->display_info.raw_edid = NULL;
1821                         kfree(edid);
1822                 }
1823         }
1824
1825         return connector_status_connected;
1826 }
1827
1828 static int intel_dp_get_modes(struct drm_connector *connector)
1829 {
1830         struct intel_dp *intel_dp = intel_attached_dp(connector);
1831         struct drm_device *dev = intel_dp->base.base.dev;
1832         struct drm_i915_private *dev_priv = dev->dev_private;
1833         int ret;
1834
1835         /* We should parse the EDID data and find out if it has an audio sink
1836          */
1837
1838         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1839         if (ret) {
1840                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
1841                         struct drm_display_mode *newmode;
1842                         list_for_each_entry(newmode, &connector->probed_modes,
1843                                             head) {
1844                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
1845                                         intel_dp->panel_fixed_mode =
1846                                                 drm_mode_duplicate(dev, newmode);
1847                                         break;
1848                                 }
1849                         }
1850                 }
1851                 return ret;
1852         }
1853
1854         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1855         if (is_edp(intel_dp)) {
1856                 /* initialize panel mode from VBT if available for eDP */
1857                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1858                         intel_dp->panel_fixed_mode =
1859                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1860                         if (intel_dp->panel_fixed_mode) {
1861                                 intel_dp->panel_fixed_mode->type |=
1862                                         DRM_MODE_TYPE_PREFERRED;
1863                         }
1864                 }
1865                 if (intel_dp->panel_fixed_mode) {
1866                         struct drm_display_mode *mode;
1867                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1868                         drm_mode_probed_add(connector, mode);
1869                         return 1;
1870                 }
1871         }
1872         return 0;
1873 }
1874
1875 static bool
1876 intel_dp_detect_audio(struct drm_connector *connector)
1877 {
1878         struct intel_dp *intel_dp = intel_attached_dp(connector);
1879         struct edid *edid;
1880         bool has_audio = false;
1881
1882         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1883         if (edid) {
1884                 has_audio = drm_detect_monitor_audio(edid);
1885
1886                 connector->display_info.raw_edid = NULL;
1887                 kfree(edid);
1888         }
1889
1890         return has_audio;
1891 }
1892
1893 static int
1894 intel_dp_set_property(struct drm_connector *connector,
1895                       struct drm_property *property,
1896                       uint64_t val)
1897 {
1898         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1899         struct intel_dp *intel_dp = intel_attached_dp(connector);
1900         int ret;
1901
1902         ret = drm_connector_property_set_value(connector, property, val);
1903         if (ret)
1904                 return ret;
1905
1906         if (property == dev_priv->force_audio_property) {
1907                 int i = val;
1908                 bool has_audio;
1909
1910                 if (i == intel_dp->force_audio)
1911                         return 0;
1912
1913                 intel_dp->force_audio = i;
1914
1915                 if (i == 0)
1916                         has_audio = intel_dp_detect_audio(connector);
1917                 else
1918                         has_audio = i > 0;
1919
1920                 if (has_audio == intel_dp->has_audio)
1921                         return 0;
1922
1923                 intel_dp->has_audio = has_audio;
1924                 goto done;
1925         }
1926
1927         if (property == dev_priv->broadcast_rgb_property) {
1928                 if (val == !!intel_dp->color_range)
1929                         return 0;
1930
1931                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1932                 goto done;
1933         }
1934
1935         return -EINVAL;
1936
1937 done:
1938         if (intel_dp->base.base.crtc) {
1939                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1940                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1941                                          crtc->x, crtc->y,
1942                                          crtc->fb);
1943         }
1944
1945         return 0;
1946 }
1947
1948 static void
1949 intel_dp_destroy (struct drm_connector *connector)
1950 {
1951         struct drm_device *dev = connector->dev;
1952
1953         if (intel_dpd_is_edp(dev))
1954                 intel_panel_destroy_backlight(dev);
1955
1956         drm_sysfs_connector_remove(connector);
1957         drm_connector_cleanup(connector);
1958         kfree(connector);
1959 }
1960
1961 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1962 {
1963         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1964
1965         i2c_del_adapter(&intel_dp->adapter);
1966         drm_encoder_cleanup(encoder);
1967         kfree(intel_dp);
1968 }
1969
1970 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1971         .dpms = intel_dp_dpms,
1972         .mode_fixup = intel_dp_mode_fixup,
1973         .prepare = intel_dp_prepare,
1974         .mode_set = intel_dp_mode_set,
1975         .commit = intel_dp_commit,
1976 };
1977
1978 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1979         .dpms = drm_helper_connector_dpms,
1980         .detect = intel_dp_detect,
1981         .fill_modes = drm_helper_probe_single_connector_modes,
1982         .set_property = intel_dp_set_property,
1983         .destroy = intel_dp_destroy,
1984 };
1985
1986 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1987         .get_modes = intel_dp_get_modes,
1988         .mode_valid = intel_dp_mode_valid,
1989         .best_encoder = intel_best_encoder,
1990 };
1991
1992 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1993         .destroy = intel_dp_encoder_destroy,
1994 };
1995
1996 static void
1997 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1998 {
1999         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2000
2001         intel_dp_check_link_status(intel_dp);
2002 }
2003
2004 /* Return which DP Port should be selected for Transcoder DP control */
2005 int
2006 intel_trans_dp_port_sel (struct drm_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->dev;
2009         struct drm_mode_config *mode_config = &dev->mode_config;
2010         struct drm_encoder *encoder;
2011
2012         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2013                 struct intel_dp *intel_dp;
2014
2015                 if (encoder->crtc != crtc)
2016                         continue;
2017
2018                 intel_dp = enc_to_intel_dp(encoder);
2019                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2020                         return intel_dp->output_reg;
2021         }
2022
2023         return -1;
2024 }
2025
2026 /* check the VBT to see whether the eDP is on DP-D port */
2027 bool intel_dpd_is_edp(struct drm_device *dev)
2028 {
2029         struct drm_i915_private *dev_priv = dev->dev_private;
2030         struct child_device_config *p_child;
2031         int i;
2032
2033         if (!dev_priv->child_dev_num)
2034                 return false;
2035
2036         for (i = 0; i < dev_priv->child_dev_num; i++) {
2037                 p_child = dev_priv->child_dev + i;
2038
2039                 if (p_child->dvo_port == PORT_IDPD &&
2040                     p_child->device_type == DEVICE_TYPE_eDP)
2041                         return true;
2042         }
2043         return false;
2044 }
2045
2046 static void
2047 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2048 {
2049         intel_attach_force_audio_property(connector);
2050         intel_attach_broadcast_rgb_property(connector);
2051 }
2052
2053 void
2054 intel_dp_init(struct drm_device *dev, int output_reg)
2055 {
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057         struct drm_connector *connector;
2058         struct intel_dp *intel_dp;
2059         struct intel_encoder *intel_encoder;
2060         struct intel_connector *intel_connector;
2061         const char *name = NULL;
2062         int type;
2063
2064         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2065         if (!intel_dp)
2066                 return;
2067
2068         intel_dp->output_reg = output_reg;
2069         intel_dp->dpms_mode = -1;
2070
2071         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2072         if (!intel_connector) {
2073                 kfree(intel_dp);
2074                 return;
2075         }
2076         intel_encoder = &intel_dp->base;
2077
2078         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2079                 if (intel_dpd_is_edp(dev))
2080                         intel_dp->is_pch_edp = true;
2081
2082         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2083                 type = DRM_MODE_CONNECTOR_eDP;
2084                 intel_encoder->type = INTEL_OUTPUT_EDP;
2085         } else {
2086                 type = DRM_MODE_CONNECTOR_DisplayPort;
2087                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2088         }
2089
2090         connector = &intel_connector->base;
2091         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2092         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2093
2094         connector->polled = DRM_CONNECTOR_POLL_HPD;
2095
2096         if (output_reg == DP_B || output_reg == PCH_DP_B)
2097                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2098         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2099                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2100         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2101                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2102
2103         if (is_edp(intel_dp))
2104                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2105
2106         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2107         connector->interlace_allowed = true;
2108         connector->doublescan_allowed = 0;
2109
2110         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2111                          DRM_MODE_ENCODER_TMDS);
2112         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2113
2114         intel_connector_attach_encoder(intel_connector, intel_encoder);
2115         drm_sysfs_connector_add(connector);
2116
2117         /* Set up the DDC bus. */
2118         switch (output_reg) {
2119                 case DP_A:
2120                         name = "DPDDC-A";
2121                         break;
2122                 case DP_B:
2123                 case PCH_DP_B:
2124                         dev_priv->hotplug_supported_mask |=
2125                                 HDMIB_HOTPLUG_INT_STATUS;
2126                         name = "DPDDC-B";
2127                         break;
2128                 case DP_C:
2129                 case PCH_DP_C:
2130                         dev_priv->hotplug_supported_mask |=
2131                                 HDMIC_HOTPLUG_INT_STATUS;
2132                         name = "DPDDC-C";
2133                         break;
2134                 case DP_D:
2135                 case PCH_DP_D:
2136                         dev_priv->hotplug_supported_mask |=
2137                                 HDMID_HOTPLUG_INT_STATUS;
2138                         name = "DPDDC-D";
2139                         break;
2140         }
2141
2142         /* Cache some DPCD data in the eDP case */
2143         if (is_edp(intel_dp)) {
2144                 bool ret;
2145                 struct edp_power_seq    cur, vbt;
2146                 u32 pp_on, pp_off, pp_div;
2147
2148                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2149                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2150                 pp_div = I915_READ(PCH_PP_DIVISOR);
2151
2152                 /* Pull timing values out of registers */
2153                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2154                         PANEL_POWER_UP_DELAY_SHIFT;
2155
2156                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2157                         PANEL_LIGHT_ON_DELAY_SHIFT;
2158
2159                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2160                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2161
2162                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2163                         PANEL_POWER_DOWN_DELAY_SHIFT;
2164
2165                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2166                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2167
2168                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2169                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2170
2171                 vbt = dev_priv->edp.pps;
2172
2173                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2174                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2175
2176 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2177
2178                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2179                 intel_dp->backlight_on_delay = get_delay(t8);
2180                 intel_dp->backlight_off_delay = get_delay(t9);
2181                 intel_dp->panel_power_down_delay = get_delay(t10);
2182                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2183
2184                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2185                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2186                               intel_dp->panel_power_cycle_delay);
2187
2188                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2189                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2190
2191                 ironlake_edp_panel_vdd_on(intel_dp);
2192                 ret = intel_dp_get_dpcd(intel_dp);
2193                 ironlake_edp_panel_vdd_off(intel_dp);
2194                 if (ret) {
2195                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2196                                 dev_priv->no_aux_handshake =
2197                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2198                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2199                 } else {
2200                         /* if this fails, presume the device is a ghost */
2201                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2202                         intel_dp_encoder_destroy(&intel_dp->base.base);
2203                         intel_dp_destroy(&intel_connector->base);
2204                         return;
2205                 }
2206         }
2207
2208         intel_dp_i2c_init(intel_dp, intel_connector, name);
2209
2210         intel_encoder->hot_plug = intel_dp_hot_plug;
2211
2212         if (is_edp(intel_dp)) {
2213                 dev_priv->int_edp_connector = connector;
2214                 intel_panel_setup_backlight(dev);
2215         }
2216
2217         intel_dp_add_properties(intel_dp, connector);
2218
2219         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2220          * 0xd.  Failure to do so will result in spurious interrupts being
2221          * generated on the port when a cable is not attached.
2222          */
2223         if (IS_G4X(dev) && !IS_GM45(dev)) {
2224                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2225                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2226         }
2227 }