2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66 * @intel_dp: DP struct
68 * If a CPU or PCH DP output is attached to an eDP panel, this function
69 * will return true, and false otherwise.
71 static bool is_edp(struct intel_dp *intel_dp)
73 return intel_dp->base.type == INTEL_OUTPUT_EDP;
77 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78 * @intel_dp: DP struct
80 * Returns true if the given DP struct corresponds to a PCH DP port attached
81 * to an eDP panel, false otherwise. Helpful for determining whether we
82 * may need FDI resources for a given DP output or not.
84 static bool is_pch_edp(struct intel_dp *intel_dp)
86 return intel_dp->is_pch_edp;
89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
91 return container_of(encoder, struct intel_dp, base.base);
94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
96 return container_of(intel_attached_encoder(connector),
97 struct intel_dp, base);
101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102 * @encoder: DRM encoder
104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
105 * by intel_display.c.
107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
109 struct intel_dp *intel_dp;
114 intel_dp = enc_to_intel_dp(encoder);
116 return is_pch_edp(intel_dp);
119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_link_down(struct intel_dp *intel_dp);
124 intel_edp_link_config (struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw)
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
129 *lane_num = intel_dp->lane_count;
130 if (intel_dp->link_bw == DP_LINK_BW_1_62)
132 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
139 int max_lane_count = 4;
141 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
150 return max_lane_count;
154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
156 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
158 switch (max_link_bw) {
159 case DP_LINK_BW_1_62:
163 max_link_bw = DP_LINK_BW_1_62;
170 intel_dp_link_clock(uint8_t link_bw)
172 if (link_bw == DP_LINK_BW_2_7)
178 /* I think this is a fiction */
180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
182 struct drm_crtc *crtc = intel_dp->base.base.crtc;
183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
187 bpp = intel_crtc->bpp;
189 return (pixel_clock * bpp + 7) / 8;
193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
195 return (max_link_clock * max_lanes * 8) / 10;
199 intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
202 struct intel_dp *intel_dp = intel_attached_dp(connector);
203 struct drm_device *dev = connector->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
206 int max_lanes = intel_dp_max_lane_count(intel_dp);
208 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
209 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
212 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
216 /* only refuse the mode on non eDP since we have seen some weird eDP panels
217 which are outside spec tolerances but somehow work by magic */
218 if (!is_edp(intel_dp) &&
219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
220 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
221 return MODE_CLOCK_HIGH;
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
230 pack_aux(uint8_t *src, int src_bytes)
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
243 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
248 for (i = 0; i < dst_bytes; i++)
249 dst[i] = src >> ((3-i) * 8);
252 /* hrawclock is 1/4 the FSB frequency */
254 intel_hrawclk(struct drm_device *dev)
256 struct drm_i915_private *dev_priv = dev->dev_private;
259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
269 case CLKCFG_FSB_1067:
271 case CLKCFG_FSB_1333:
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
283 intel_dp_aux_ch(struct intel_dp *intel_dp,
284 uint8_t *send, int send_bytes,
285 uint8_t *recv, int recv_size)
287 uint32_t output_reg = intel_dp->output_reg;
288 struct drm_device *dev = intel_dp->base.base.dev;
289 struct drm_i915_private *dev_priv = dev->dev_private;
290 uint32_t ch_ctl = output_reg + 0x10;
291 uint32_t ch_data = ch_ctl + 4;
295 uint32_t aux_clock_divider;
298 /* The clock divider is based off the hrawclk,
299 * and would like to run at 2MHz. So, take the
300 * hrawclk value and divide by 2 and use that
302 * Note that PCH attached eDP panels should use a 125MHz input
305 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
307 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
309 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
310 } else if (HAS_PCH_SPLIT(dev))
311 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
313 aux_clock_divider = intel_hrawclk(dev) / 2;
320 /* Try to wait for any previous AUX channel activity */
321 for (try = 0; try < 3; try++) {
322 status = I915_READ(ch_ctl);
323 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
329 WARN(1, "dp_aux_ch not started status 0x%08x\n",
334 /* Must try at least 3 times according to DP spec */
335 for (try = 0; try < 5; try++) {
336 /* Load the send data into the aux channel data registers */
337 for (i = 0; i < send_bytes; i += 4)
338 I915_WRITE(ch_data + i,
339 pack_aux(send + i, send_bytes - i));
341 /* Send the command and wait for it to complete */
343 DP_AUX_CH_CTL_SEND_BUSY |
344 DP_AUX_CH_CTL_TIME_OUT_400us |
345 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
346 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
347 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
349 DP_AUX_CH_CTL_TIME_OUT_ERROR |
350 DP_AUX_CH_CTL_RECEIVE_ERROR);
352 status = I915_READ(ch_ctl);
353 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
358 /* Clear done status and any errors */
362 DP_AUX_CH_CTL_TIME_OUT_ERROR |
363 DP_AUX_CH_CTL_RECEIVE_ERROR);
364 if (status & DP_AUX_CH_CTL_DONE)
368 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
369 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
373 /* Check for timeout or receive error.
374 * Timeouts occur when the sink is not connected
376 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
377 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
381 /* Timeouts occur when the device isn't connected, so they're
382 * "normal" -- don't fill the kernel log with these */
383 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
384 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
388 /* Unload any bytes sent back from the other side */
389 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
390 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
391 if (recv_bytes > recv_size)
392 recv_bytes = recv_size;
394 for (i = 0; i < recv_bytes; i += 4)
395 unpack_aux(I915_READ(ch_data + i),
396 recv + i, recv_bytes - i);
401 /* Write data to the aux channel in native mode */
403 intel_dp_aux_native_write(struct intel_dp *intel_dp,
404 uint16_t address, uint8_t *send, int send_bytes)
413 msg[0] = AUX_NATIVE_WRITE << 4;
414 msg[1] = address >> 8;
415 msg[2] = address & 0xff;
416 msg[3] = send_bytes - 1;
417 memcpy(&msg[4], send, send_bytes);
418 msg_bytes = send_bytes + 4;
420 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
423 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
425 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
433 /* Write a single byte to the aux channel in native mode */
435 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
436 uint16_t address, uint8_t byte)
438 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
441 /* read bytes from a native aux channel */
443 intel_dp_aux_native_read(struct intel_dp *intel_dp,
444 uint16_t address, uint8_t *recv, int recv_bytes)
453 msg[0] = AUX_NATIVE_READ << 4;
454 msg[1] = address >> 8;
455 msg[2] = address & 0xff;
456 msg[3] = recv_bytes - 1;
459 reply_bytes = recv_bytes + 1;
462 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
469 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
470 memcpy(recv, reply + 1, ret - 1);
473 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
481 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
482 uint8_t write_byte, uint8_t *read_byte)
484 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
485 struct intel_dp *intel_dp = container_of(adapter,
488 uint16_t address = algo_data->address;
496 /* Set up the command byte */
497 if (mode & MODE_I2C_READ)
498 msg[0] = AUX_I2C_READ << 4;
500 msg[0] = AUX_I2C_WRITE << 4;
502 if (!(mode & MODE_I2C_STOP))
503 msg[0] |= AUX_I2C_MOT << 4;
505 msg[1] = address >> 8;
526 for (retry = 0; retry < 5; retry++) {
527 ret = intel_dp_aux_ch(intel_dp,
531 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
535 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
536 case AUX_NATIVE_REPLY_ACK:
537 /* I2C-over-AUX Reply field is only valid
538 * when paired with AUX ACK.
541 case AUX_NATIVE_REPLY_NACK:
542 DRM_DEBUG_KMS("aux_ch native nack\n");
544 case AUX_NATIVE_REPLY_DEFER:
548 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
553 switch (reply[0] & AUX_I2C_REPLY_MASK) {
554 case AUX_I2C_REPLY_ACK:
555 if (mode == MODE_I2C_READ) {
556 *read_byte = reply[1];
558 return reply_bytes - 1;
559 case AUX_I2C_REPLY_NACK:
560 DRM_DEBUG_KMS("aux_i2c nack\n");
562 case AUX_I2C_REPLY_DEFER:
563 DRM_DEBUG_KMS("aux_i2c defer\n");
567 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
572 DRM_ERROR("too many retries, giving up\n");
577 intel_dp_i2c_init(struct intel_dp *intel_dp,
578 struct intel_connector *intel_connector, const char *name)
580 DRM_DEBUG_KMS("i2c_init %s\n", name);
581 intel_dp->algo.running = false;
582 intel_dp->algo.address = 0;
583 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
585 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
586 intel_dp->adapter.owner = THIS_MODULE;
587 intel_dp->adapter.class = I2C_CLASS_DDC;
588 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
589 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
590 intel_dp->adapter.algo_data = &intel_dp->algo;
591 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
593 return i2c_dp_aux_add_bus(&intel_dp->adapter);
597 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
598 struct drm_display_mode *adjusted_mode)
600 struct drm_device *dev = encoder->dev;
601 struct drm_i915_private *dev_priv = dev->dev_private;
602 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
603 int lane_count, clock;
604 int max_lane_count = intel_dp_max_lane_count(intel_dp);
605 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
606 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
608 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
609 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
610 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
611 mode, adjusted_mode);
613 * the mode->clock is used to calculate the Data&Link M/N
614 * of the pipe. For the eDP the fixed clock should be used.
616 mode->clock = dev_priv->panel_fixed_mode->clock;
619 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
620 for (clock = 0; clock <= max_clock; clock++) {
621 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
623 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
625 intel_dp->link_bw = bws[clock];
626 intel_dp->lane_count = lane_count;
627 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
628 DRM_DEBUG_KMS("Display port link bw %02x lane "
629 "count %d clock %d\n",
630 intel_dp->link_bw, intel_dp->lane_count,
631 adjusted_mode->clock);
637 if (is_edp(intel_dp)) {
638 /* okay we failed just pick the highest */
639 intel_dp->lane_count = max_lane_count;
640 intel_dp->link_bw = bws[max_clock];
641 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
642 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
643 "count %d clock %d\n",
644 intel_dp->link_bw, intel_dp->lane_count,
645 adjusted_mode->clock);
653 struct intel_dp_m_n {
662 intel_reduce_ratio(uint32_t *num, uint32_t *den)
664 while (*num > 0xffffff || *den > 0xffffff) {
671 intel_dp_compute_m_n(int bpp,
675 struct intel_dp_m_n *m_n)
678 m_n->gmch_m = (pixel_clock * bpp) >> 3;
679 m_n->gmch_n = link_clock * nlanes;
680 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
681 m_n->link_m = pixel_clock;
682 m_n->link_n = link_clock;
683 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
687 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
688 struct drm_display_mode *adjusted_mode)
690 struct drm_device *dev = crtc->dev;
691 struct drm_mode_config *mode_config = &dev->mode_config;
692 struct drm_encoder *encoder;
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
696 struct intel_dp_m_n m_n;
697 int pipe = intel_crtc->pipe;
700 * Find the lane count in the intel_encoder private
702 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
703 struct intel_dp *intel_dp;
705 if (encoder->crtc != crtc)
708 intel_dp = enc_to_intel_dp(encoder);
709 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
710 lane_count = intel_dp->lane_count;
712 } else if (is_edp(intel_dp)) {
713 lane_count = dev_priv->edp.lanes;
719 * Compute the GMCH and Link ratios. The '3' here is
720 * the number of bytes_per_pixel post-LUT, which we always
721 * set up for 8-bits of R/G/B, or 3 bytes total.
723 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
724 mode->clock, adjusted_mode->clock, &m_n);
726 if (HAS_PCH_SPLIT(dev)) {
727 I915_WRITE(TRANSDATA_M1(pipe),
728 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
730 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
731 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
732 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
734 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
735 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
737 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
738 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
739 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
744 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
745 struct drm_display_mode *adjusted_mode)
747 struct drm_device *dev = encoder->dev;
748 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
749 struct drm_crtc *crtc = intel_dp->base.base.crtc;
750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
752 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
753 intel_dp->DP |= intel_dp->color_range;
755 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
756 intel_dp->DP |= DP_SYNC_HS_HIGH;
757 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
758 intel_dp->DP |= DP_SYNC_VS_HIGH;
760 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
761 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
763 intel_dp->DP |= DP_LINK_TRAIN_OFF;
765 switch (intel_dp->lane_count) {
767 intel_dp->DP |= DP_PORT_WIDTH_1;
770 intel_dp->DP |= DP_PORT_WIDTH_2;
773 intel_dp->DP |= DP_PORT_WIDTH_4;
776 if (intel_dp->has_audio)
777 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
779 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
780 intel_dp->link_configuration[0] = intel_dp->link_bw;
781 intel_dp->link_configuration[1] = intel_dp->lane_count;
782 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
785 * Check for DPCD version > 1.1 and enhanced framing support
787 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
788 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
789 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
790 intel_dp->DP |= DP_ENHANCED_FRAMING;
793 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
794 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
795 intel_dp->DP |= DP_PIPEB_SELECT;
797 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
798 /* don't miss out required setting for eDP */
799 intel_dp->DP |= DP_PLL_ENABLE;
800 if (adjusted_mode->clock < 200000)
801 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
803 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
807 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
809 struct drm_device *dev = intel_dp->base.base.dev;
810 struct drm_i915_private *dev_priv = dev->dev_private;
814 * If the panel wasn't on, make sure there's not a currently
815 * active PP sequence before enabling AUX VDD.
817 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
818 msleep(dev_priv->panel_t3);
820 pp = I915_READ(PCH_PP_CONTROL);
822 I915_WRITE(PCH_PP_CONTROL, pp);
823 POSTING_READ(PCH_PP_CONTROL);
826 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
828 struct drm_device *dev = intel_dp->base.base.dev;
829 struct drm_i915_private *dev_priv = dev->dev_private;
832 pp = I915_READ(PCH_PP_CONTROL);
833 pp &= ~EDP_FORCE_VDD;
834 I915_WRITE(PCH_PP_CONTROL, pp);
835 POSTING_READ(PCH_PP_CONTROL);
837 /* Make sure sequencer is idle before allowing subsequent activity */
838 msleep(dev_priv->panel_t12);
841 /* Returns true if the panel was already on when called */
842 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
844 struct drm_device *dev = intel_dp->base.base.dev;
845 struct drm_i915_private *dev_priv = dev->dev_private;
846 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
848 if (I915_READ(PCH_PP_STATUS) & PP_ON)
851 pp = I915_READ(PCH_PP_CONTROL);
853 /* ILK workaround: disable reset around power sequence */
854 pp &= ~PANEL_POWER_RESET;
855 I915_WRITE(PCH_PP_CONTROL, pp);
856 POSTING_READ(PCH_PP_CONTROL);
858 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
859 I915_WRITE(PCH_PP_CONTROL, pp);
860 POSTING_READ(PCH_PP_CONTROL);
862 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
864 DRM_ERROR("panel on wait timed out: 0x%08x\n",
865 I915_READ(PCH_PP_STATUS));
867 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
868 I915_WRITE(PCH_PP_CONTROL, pp);
869 POSTING_READ(PCH_PP_CONTROL);
874 static void ironlake_edp_panel_off (struct drm_device *dev)
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
878 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
880 pp = I915_READ(PCH_PP_CONTROL);
882 /* ILK workaround: disable reset around power sequence */
883 pp &= ~PANEL_POWER_RESET;
884 I915_WRITE(PCH_PP_CONTROL, pp);
885 POSTING_READ(PCH_PP_CONTROL);
887 pp &= ~POWER_TARGET_ON;
888 I915_WRITE(PCH_PP_CONTROL, pp);
889 POSTING_READ(PCH_PP_CONTROL);
891 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
892 DRM_ERROR("panel off wait timed out: 0x%08x\n",
893 I915_READ(PCH_PP_STATUS));
895 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
896 I915_WRITE(PCH_PP_CONTROL, pp);
897 POSTING_READ(PCH_PP_CONTROL);
900 static void ironlake_edp_backlight_on (struct drm_device *dev)
902 struct drm_i915_private *dev_priv = dev->dev_private;
907 * If we enable the backlight right away following a panel power
908 * on, we may see slight flicker as the panel syncs with the eDP
909 * link. So delay a bit to make sure the image is solid before
910 * allowing it to appear.
913 pp = I915_READ(PCH_PP_CONTROL);
914 pp |= EDP_BLC_ENABLE;
915 I915_WRITE(PCH_PP_CONTROL, pp);
918 static void ironlake_edp_backlight_off (struct drm_device *dev)
920 struct drm_i915_private *dev_priv = dev->dev_private;
924 pp = I915_READ(PCH_PP_CONTROL);
925 pp &= ~EDP_BLC_ENABLE;
926 I915_WRITE(PCH_PP_CONTROL, pp);
929 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
931 struct drm_device *dev = encoder->dev;
932 struct drm_i915_private *dev_priv = dev->dev_private;
936 dpa_ctl = I915_READ(DP_A);
937 dpa_ctl |= DP_PLL_ENABLE;
938 I915_WRITE(DP_A, dpa_ctl);
943 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
945 struct drm_device *dev = encoder->dev;
946 struct drm_i915_private *dev_priv = dev->dev_private;
949 dpa_ctl = I915_READ(DP_A);
950 dpa_ctl &= ~DP_PLL_ENABLE;
951 I915_WRITE(DP_A, dpa_ctl);
956 /* If the sink supports it, try to set the power state appropriately */
957 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
961 /* Should have a valid DPCD by this point */
962 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
965 if (mode != DRM_MODE_DPMS_ON) {
966 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
969 DRM_DEBUG_DRIVER("failed to write sink power state\n");
972 * When turning on, we need to retry for 1ms to give the sink
975 for (i = 0; i < 3; i++) {
976 ret = intel_dp_aux_native_write_1(intel_dp,
986 static void intel_dp_prepare(struct drm_encoder *encoder)
988 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
989 struct drm_device *dev = encoder->dev;
991 /* Wake up the sink first */
992 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
994 if (is_edp(intel_dp)) {
995 ironlake_edp_backlight_off(dev);
996 ironlake_edp_panel_off(dev);
997 if (!is_pch_edp(intel_dp))
998 ironlake_edp_pll_on(encoder);
1000 ironlake_edp_pll_off(encoder);
1002 intel_dp_link_down(intel_dp);
1005 static void intel_dp_commit(struct drm_encoder *encoder)
1007 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1008 struct drm_device *dev = encoder->dev;
1010 if (is_edp(intel_dp))
1011 ironlake_edp_panel_vdd_on(intel_dp);
1013 intel_dp_start_link_train(intel_dp);
1015 if (is_edp(intel_dp)) {
1016 ironlake_edp_panel_on(intel_dp);
1017 ironlake_edp_panel_vdd_off(intel_dp);
1020 intel_dp_complete_link_train(intel_dp);
1022 if (is_edp(intel_dp))
1023 ironlake_edp_backlight_on(dev);
1025 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1029 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1031 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1032 struct drm_device *dev = encoder->dev;
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1036 if (mode != DRM_MODE_DPMS_ON) {
1037 if (is_edp(intel_dp))
1038 ironlake_edp_backlight_off(dev);
1039 intel_dp_sink_dpms(intel_dp, mode);
1040 intel_dp_link_down(intel_dp);
1041 if (is_edp(intel_dp))
1042 ironlake_edp_panel_off(dev);
1043 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1044 ironlake_edp_pll_off(encoder);
1046 if (is_edp(intel_dp))
1047 ironlake_edp_panel_vdd_on(intel_dp);
1048 intel_dp_sink_dpms(intel_dp, mode);
1049 if (!(dp_reg & DP_PORT_EN)) {
1050 intel_dp_start_link_train(intel_dp);
1051 if (is_edp(intel_dp)) {
1052 ironlake_edp_panel_on(intel_dp);
1053 ironlake_edp_panel_vdd_off(intel_dp);
1055 intel_dp_complete_link_train(intel_dp);
1057 if (is_edp(intel_dp))
1058 ironlake_edp_backlight_on(dev);
1060 intel_dp->dpms_mode = mode;
1064 * Native read with retry for link status and receiver capability reads for
1065 * cases where the sink may still be asleep.
1068 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1069 uint8_t *recv, int recv_bytes)
1074 * Sinks are *supposed* to come up within 1ms from an off state,
1075 * but we're also supposed to retry 3 times per the spec.
1077 for (i = 0; i < 3; i++) {
1078 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1080 if (ret == recv_bytes)
1089 * Fetch AUX CH registers 0x202 - 0x207 which contain
1090 * link status information
1093 intel_dp_get_link_status(struct intel_dp *intel_dp)
1095 return intel_dp_aux_native_read_retry(intel_dp,
1097 intel_dp->link_status,
1098 DP_LINK_STATUS_SIZE);
1102 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1105 return link_status[r - DP_LANE0_1_STATUS];
1109 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1112 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1113 int s = ((lane & 1) ?
1114 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1115 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1116 uint8_t l = intel_dp_link_status(link_status, i);
1118 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1122 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1125 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1126 int s = ((lane & 1) ?
1127 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1128 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1129 uint8_t l = intel_dp_link_status(link_status, i);
1131 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1136 static char *voltage_names[] = {
1137 "0.4V", "0.6V", "0.8V", "1.2V"
1139 static char *pre_emph_names[] = {
1140 "0dB", "3.5dB", "6dB", "9.5dB"
1142 static char *link_train_names[] = {
1143 "pattern 1", "pattern 2", "idle", "off"
1148 * These are source-specific values; current Intel hardware supports
1149 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1151 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1154 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1156 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1157 case DP_TRAIN_VOLTAGE_SWING_400:
1158 return DP_TRAIN_PRE_EMPHASIS_6;
1159 case DP_TRAIN_VOLTAGE_SWING_600:
1160 return DP_TRAIN_PRE_EMPHASIS_6;
1161 case DP_TRAIN_VOLTAGE_SWING_800:
1162 return DP_TRAIN_PRE_EMPHASIS_3_5;
1163 case DP_TRAIN_VOLTAGE_SWING_1200:
1165 return DP_TRAIN_PRE_EMPHASIS_0;
1170 intel_get_adjust_train(struct intel_dp *intel_dp)
1176 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1177 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1178 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1186 if (v >= I830_DP_VOLTAGE_MAX)
1187 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1189 if (p >= intel_dp_pre_emphasis_max(v))
1190 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1192 for (lane = 0; lane < 4; lane++)
1193 intel_dp->train_set[lane] = v | p;
1197 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1199 uint32_t signal_levels = 0;
1201 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1202 case DP_TRAIN_VOLTAGE_SWING_400:
1204 signal_levels |= DP_VOLTAGE_0_4;
1206 case DP_TRAIN_VOLTAGE_SWING_600:
1207 signal_levels |= DP_VOLTAGE_0_6;
1209 case DP_TRAIN_VOLTAGE_SWING_800:
1210 signal_levels |= DP_VOLTAGE_0_8;
1212 case DP_TRAIN_VOLTAGE_SWING_1200:
1213 signal_levels |= DP_VOLTAGE_1_2;
1216 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1217 case DP_TRAIN_PRE_EMPHASIS_0:
1219 signal_levels |= DP_PRE_EMPHASIS_0;
1221 case DP_TRAIN_PRE_EMPHASIS_3_5:
1222 signal_levels |= DP_PRE_EMPHASIS_3_5;
1224 case DP_TRAIN_PRE_EMPHASIS_6:
1225 signal_levels |= DP_PRE_EMPHASIS_6;
1227 case DP_TRAIN_PRE_EMPHASIS_9_5:
1228 signal_levels |= DP_PRE_EMPHASIS_9_5;
1231 return signal_levels;
1234 /* Gen6's DP voltage swing and pre-emphasis control */
1236 intel_gen6_edp_signal_levels(uint8_t train_set)
1238 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1239 DP_TRAIN_PRE_EMPHASIS_MASK);
1240 switch (signal_levels) {
1241 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1242 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1243 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1244 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1245 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1246 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1248 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1249 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1250 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1251 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1252 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1253 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1254 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1256 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1257 "0x%x\n", signal_levels);
1258 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1263 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1266 int i = DP_LANE0_1_STATUS + (lane >> 1);
1267 int s = (lane & 1) * 4;
1268 uint8_t l = intel_dp_link_status(link_status, i);
1270 return (l >> s) & 0xf;
1273 /* Check for clock recovery is done on all channels */
1275 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1278 uint8_t lane_status;
1280 for (lane = 0; lane < lane_count; lane++) {
1281 lane_status = intel_get_lane_status(link_status, lane);
1282 if ((lane_status & DP_LANE_CR_DONE) == 0)
1288 /* Check to see if channel eq is done on all channels */
1289 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1290 DP_LANE_CHANNEL_EQ_DONE|\
1291 DP_LANE_SYMBOL_LOCKED)
1293 intel_channel_eq_ok(struct intel_dp *intel_dp)
1296 uint8_t lane_status;
1299 lane_align = intel_dp_link_status(intel_dp->link_status,
1300 DP_LANE_ALIGN_STATUS_UPDATED);
1301 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1303 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1304 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1305 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1312 intel_dp_set_link_train(struct intel_dp *intel_dp,
1313 uint32_t dp_reg_value,
1314 uint8_t dp_train_pat)
1316 struct drm_device *dev = intel_dp->base.base.dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1320 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1321 POSTING_READ(intel_dp->output_reg);
1323 intel_dp_aux_native_write_1(intel_dp,
1324 DP_TRAINING_PATTERN_SET,
1327 ret = intel_dp_aux_native_write(intel_dp,
1328 DP_TRAINING_LANE0_SET,
1329 intel_dp->train_set, 4);
1336 /* Enable corresponding port and start training pattern 1 */
1338 intel_dp_start_link_train(struct intel_dp *intel_dp)
1340 struct drm_device *dev = intel_dp->base.base.dev;
1341 struct drm_i915_private *dev_priv = dev->dev_private;
1342 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1345 bool clock_recovery = false;
1348 uint32_t DP = intel_dp->DP;
1351 * On CPT we have to enable the port in training pattern 1, which
1352 * will happen below in intel_dp_set_link_train. Otherwise, enable
1353 * the port and wait for it to become active.
1355 if (!HAS_PCH_CPT(dev)) {
1356 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1357 POSTING_READ(intel_dp->output_reg);
1358 intel_wait_for_vblank(dev, intel_crtc->pipe);
1361 /* Write the link configuration data */
1362 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1363 intel_dp->link_configuration,
1364 DP_LINK_CONFIGURATION_SIZE);
1367 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1368 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1370 DP &= ~DP_LINK_TRAIN_MASK;
1371 memset(intel_dp->train_set, 0, 4);
1374 clock_recovery = false;
1376 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1377 uint32_t signal_levels;
1378 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1379 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1380 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1382 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1383 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1386 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1387 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1389 reg = DP | DP_LINK_TRAIN_PAT_1;
1391 if (!intel_dp_set_link_train(intel_dp, reg,
1392 DP_TRAINING_PATTERN_1 |
1393 DP_LINK_SCRAMBLING_DISABLE))
1395 /* Set training pattern 1 */
1398 if (!intel_dp_get_link_status(intel_dp))
1401 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1402 clock_recovery = true;
1406 /* Check to see if we've tried the max voltage */
1407 for (i = 0; i < intel_dp->lane_count; i++)
1408 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1410 if (i == intel_dp->lane_count)
1413 /* Check to see if we've tried the same voltage 5 times */
1414 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1420 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1422 /* Compute new intel_dp->train_set as requested by target */
1423 intel_get_adjust_train(intel_dp);
1430 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1432 struct drm_device *dev = intel_dp->base.base.dev;
1433 struct drm_i915_private *dev_priv = dev->dev_private;
1434 bool channel_eq = false;
1435 int tries, cr_tries;
1437 uint32_t DP = intel_dp->DP;
1439 /* channel equalization */
1444 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1445 uint32_t signal_levels;
1448 DRM_ERROR("failed to train DP, aborting\n");
1449 intel_dp_link_down(intel_dp);
1453 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1454 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1455 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1457 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1458 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1461 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1462 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1464 reg = DP | DP_LINK_TRAIN_PAT_2;
1466 /* channel eq pattern */
1467 if (!intel_dp_set_link_train(intel_dp, reg,
1468 DP_TRAINING_PATTERN_2 |
1469 DP_LINK_SCRAMBLING_DISABLE))
1473 if (!intel_dp_get_link_status(intel_dp))
1476 /* Make sure clock is still ok */
1477 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1478 intel_dp_start_link_train(intel_dp);
1483 if (intel_channel_eq_ok(intel_dp)) {
1488 /* Try 5 times, then try clock recovery if that fails */
1490 intel_dp_link_down(intel_dp);
1491 intel_dp_start_link_train(intel_dp);
1497 /* Compute new intel_dp->train_set as requested by target */
1498 intel_get_adjust_train(intel_dp);
1502 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1503 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1505 reg = DP | DP_LINK_TRAIN_OFF;
1507 I915_WRITE(intel_dp->output_reg, reg);
1508 POSTING_READ(intel_dp->output_reg);
1509 intel_dp_aux_native_write_1(intel_dp,
1510 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1514 intel_dp_link_down(struct intel_dp *intel_dp)
1516 struct drm_device *dev = intel_dp->base.base.dev;
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 uint32_t DP = intel_dp->DP;
1520 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1523 DRM_DEBUG_KMS("\n");
1525 if (is_edp(intel_dp)) {
1526 DP &= ~DP_PLL_ENABLE;
1527 I915_WRITE(intel_dp->output_reg, DP);
1528 POSTING_READ(intel_dp->output_reg);
1532 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1533 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1534 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1536 DP &= ~DP_LINK_TRAIN_MASK;
1537 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1539 POSTING_READ(intel_dp->output_reg);
1543 if (is_edp(intel_dp))
1544 DP |= DP_LINK_TRAIN_OFF;
1546 if (!HAS_PCH_CPT(dev) &&
1547 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1548 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1550 /* Hardware workaround: leaving our transcoder select
1551 * set to transcoder B while it's off will prevent the
1552 * corresponding HDMI output on transcoder A.
1554 * Combine this with another hardware workaround:
1555 * transcoder select bit can only be cleared while the
1558 DP &= ~DP_PIPEB_SELECT;
1559 I915_WRITE(intel_dp->output_reg, DP);
1561 /* Changes to enable or select take place the vblank
1562 * after being written.
1565 /* We can arrive here never having been attached
1566 * to a CRTC, for instance, due to inheriting
1567 * random state from the BIOS.
1569 * If the pipe is not running, play safe and
1570 * wait for the clocks to stabilise before
1573 POSTING_READ(intel_dp->output_reg);
1576 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1579 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1580 POSTING_READ(intel_dp->output_reg);
1584 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1586 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1587 sizeof (intel_dp->dpcd)) &&
1588 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1596 * According to DP spec
1599 * 2. Configure link according to Receiver Capabilities
1600 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1601 * 4. Check link status on receipt of hot-plug interrupt
1605 intel_dp_check_link_status(struct intel_dp *intel_dp)
1607 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1610 if (!intel_dp->base.base.crtc)
1613 /* Try to read receiver status if the link appears to be up */
1614 if (!intel_dp_get_link_status(intel_dp)) {
1615 intel_dp_link_down(intel_dp);
1619 /* Now read the DPCD to see if it's actually running */
1620 if (!intel_dp_get_dpcd(intel_dp)) {
1621 intel_dp_link_down(intel_dp);
1625 if (!intel_channel_eq_ok(intel_dp)) {
1626 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1627 drm_get_encoder_name(&intel_dp->base.base));
1628 intel_dp_start_link_train(intel_dp);
1629 intel_dp_complete_link_train(intel_dp);
1633 static enum drm_connector_status
1634 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1636 if (intel_dp_get_dpcd(intel_dp))
1637 return connector_status_connected;
1638 return connector_status_disconnected;
1641 static enum drm_connector_status
1642 ironlake_dp_detect(struct intel_dp *intel_dp)
1644 enum drm_connector_status status;
1646 /* Can't disconnect eDP, but you can close the lid... */
1647 if (is_edp(intel_dp)) {
1648 status = intel_panel_detect(intel_dp->base.base.dev);
1649 if (status == connector_status_unknown)
1650 status = connector_status_connected;
1654 return intel_dp_detect_dpcd(intel_dp);
1657 static enum drm_connector_status
1658 g4x_dp_detect(struct intel_dp *intel_dp)
1660 struct drm_device *dev = intel_dp->base.base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1664 switch (intel_dp->output_reg) {
1666 bit = DPB_HOTPLUG_INT_STATUS;
1669 bit = DPC_HOTPLUG_INT_STATUS;
1672 bit = DPD_HOTPLUG_INT_STATUS;
1675 return connector_status_unknown;
1678 temp = I915_READ(PORT_HOTPLUG_STAT);
1680 if ((temp & bit) == 0)
1681 return connector_status_disconnected;
1683 return intel_dp_detect_dpcd(intel_dp);
1687 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1689 * \return true if DP port is connected.
1690 * \return false if DP port is disconnected.
1692 static enum drm_connector_status
1693 intel_dp_detect(struct drm_connector *connector, bool force)
1695 struct intel_dp *intel_dp = intel_attached_dp(connector);
1696 struct drm_device *dev = intel_dp->base.base.dev;
1697 enum drm_connector_status status;
1698 struct edid *edid = NULL;
1700 intel_dp->has_audio = false;
1702 if (HAS_PCH_SPLIT(dev))
1703 status = ironlake_dp_detect(intel_dp);
1705 status = g4x_dp_detect(intel_dp);
1707 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1708 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1709 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1710 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1712 if (status != connector_status_connected)
1715 if (intel_dp->force_audio) {
1716 intel_dp->has_audio = intel_dp->force_audio > 0;
1718 edid = drm_get_edid(connector, &intel_dp->adapter);
1720 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1721 connector->display_info.raw_edid = NULL;
1726 return connector_status_connected;
1729 static int intel_dp_get_modes(struct drm_connector *connector)
1731 struct intel_dp *intel_dp = intel_attached_dp(connector);
1732 struct drm_device *dev = intel_dp->base.base.dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1736 /* We should parse the EDID data and find out if it has an audio sink
1739 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1741 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1742 struct drm_display_mode *newmode;
1743 list_for_each_entry(newmode, &connector->probed_modes,
1745 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1746 dev_priv->panel_fixed_mode =
1747 drm_mode_duplicate(dev, newmode);
1756 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1757 if (is_edp(intel_dp)) {
1758 if (dev_priv->panel_fixed_mode != NULL) {
1759 struct drm_display_mode *mode;
1760 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1761 drm_mode_probed_add(connector, mode);
1769 intel_dp_detect_audio(struct drm_connector *connector)
1771 struct intel_dp *intel_dp = intel_attached_dp(connector);
1773 bool has_audio = false;
1775 edid = drm_get_edid(connector, &intel_dp->adapter);
1777 has_audio = drm_detect_monitor_audio(edid);
1779 connector->display_info.raw_edid = NULL;
1787 intel_dp_set_property(struct drm_connector *connector,
1788 struct drm_property *property,
1791 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1792 struct intel_dp *intel_dp = intel_attached_dp(connector);
1795 ret = drm_connector_property_set_value(connector, property, val);
1799 if (property == dev_priv->force_audio_property) {
1803 if (i == intel_dp->force_audio)
1806 intel_dp->force_audio = i;
1809 has_audio = intel_dp_detect_audio(connector);
1813 if (has_audio == intel_dp->has_audio)
1816 intel_dp->has_audio = has_audio;
1820 if (property == dev_priv->broadcast_rgb_property) {
1821 if (val == !!intel_dp->color_range)
1824 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1831 if (intel_dp->base.base.crtc) {
1832 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1833 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1842 intel_dp_destroy (struct drm_connector *connector)
1844 struct drm_device *dev = connector->dev;
1846 if (intel_dpd_is_edp(dev))
1847 intel_panel_destroy_backlight(dev);
1849 drm_sysfs_connector_remove(connector);
1850 drm_connector_cleanup(connector);
1854 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1856 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1858 i2c_del_adapter(&intel_dp->adapter);
1859 drm_encoder_cleanup(encoder);
1863 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1864 .dpms = intel_dp_dpms,
1865 .mode_fixup = intel_dp_mode_fixup,
1866 .prepare = intel_dp_prepare,
1867 .mode_set = intel_dp_mode_set,
1868 .commit = intel_dp_commit,
1871 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1872 .dpms = drm_helper_connector_dpms,
1873 .detect = intel_dp_detect,
1874 .fill_modes = drm_helper_probe_single_connector_modes,
1875 .set_property = intel_dp_set_property,
1876 .destroy = intel_dp_destroy,
1879 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1880 .get_modes = intel_dp_get_modes,
1881 .mode_valid = intel_dp_mode_valid,
1882 .best_encoder = intel_best_encoder,
1885 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1886 .destroy = intel_dp_encoder_destroy,
1890 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1892 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1894 intel_dp_check_link_status(intel_dp);
1897 /* Return which DP Port should be selected for Transcoder DP control */
1899 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1901 struct drm_device *dev = crtc->dev;
1902 struct drm_mode_config *mode_config = &dev->mode_config;
1903 struct drm_encoder *encoder;
1905 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1906 struct intel_dp *intel_dp;
1908 if (encoder->crtc != crtc)
1911 intel_dp = enc_to_intel_dp(encoder);
1912 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1913 return intel_dp->output_reg;
1919 /* check the VBT to see whether the eDP is on DP-D port */
1920 bool intel_dpd_is_edp(struct drm_device *dev)
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct child_device_config *p_child;
1926 if (!dev_priv->child_dev_num)
1929 for (i = 0; i < dev_priv->child_dev_num; i++) {
1930 p_child = dev_priv->child_dev + i;
1932 if (p_child->dvo_port == PORT_IDPD &&
1933 p_child->device_type == DEVICE_TYPE_eDP)
1940 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1942 intel_attach_force_audio_property(connector);
1943 intel_attach_broadcast_rgb_property(connector);
1947 intel_dp_init(struct drm_device *dev, int output_reg)
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1950 struct drm_connector *connector;
1951 struct intel_dp *intel_dp;
1952 struct intel_encoder *intel_encoder;
1953 struct intel_connector *intel_connector;
1954 const char *name = NULL;
1957 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1961 intel_dp->output_reg = output_reg;
1962 intel_dp->dpms_mode = -1;
1964 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1965 if (!intel_connector) {
1969 intel_encoder = &intel_dp->base;
1971 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1972 if (intel_dpd_is_edp(dev))
1973 intel_dp->is_pch_edp = true;
1975 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1976 type = DRM_MODE_CONNECTOR_eDP;
1977 intel_encoder->type = INTEL_OUTPUT_EDP;
1979 type = DRM_MODE_CONNECTOR_DisplayPort;
1980 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1983 connector = &intel_connector->base;
1984 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1985 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1987 connector->polled = DRM_CONNECTOR_POLL_HPD;
1989 if (output_reg == DP_B || output_reg == PCH_DP_B)
1990 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1991 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1992 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1993 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1994 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1996 if (is_edp(intel_dp))
1997 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1999 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2000 connector->interlace_allowed = true;
2001 connector->doublescan_allowed = 0;
2003 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2004 DRM_MODE_ENCODER_TMDS);
2005 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2007 intel_connector_attach_encoder(intel_connector, intel_encoder);
2008 drm_sysfs_connector_add(connector);
2010 /* Set up the DDC bus. */
2011 switch (output_reg) {
2017 dev_priv->hotplug_supported_mask |=
2018 HDMIB_HOTPLUG_INT_STATUS;
2023 dev_priv->hotplug_supported_mask |=
2024 HDMIC_HOTPLUG_INT_STATUS;
2029 dev_priv->hotplug_supported_mask |=
2030 HDMID_HOTPLUG_INT_STATUS;
2035 intel_dp_i2c_init(intel_dp, intel_connector, name);
2037 /* Cache some DPCD data in the eDP case */
2038 if (is_edp(intel_dp)) {
2042 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2043 pp_div = I915_READ(PCH_PP_DIVISOR);
2045 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2046 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2047 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2048 dev_priv->panel_t12 = pp_div & 0xf;
2049 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2051 ironlake_edp_panel_vdd_on(intel_dp);
2052 ret = intel_dp_get_dpcd(intel_dp);
2053 ironlake_edp_panel_vdd_off(intel_dp);
2055 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2056 dev_priv->no_aux_handshake =
2057 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2058 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2060 /* if this fails, presume the device is a ghost */
2061 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2062 intel_dp_encoder_destroy(&intel_dp->base.base);
2063 intel_dp_destroy(&intel_connector->base);
2068 intel_encoder->hot_plug = intel_dp_hot_plug;
2070 if (is_edp(intel_dp)) {
2071 /* initialize panel mode from VBT if available for eDP */
2072 if (dev_priv->lfp_lvds_vbt_mode) {
2073 dev_priv->panel_fixed_mode =
2074 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2075 if (dev_priv->panel_fixed_mode) {
2076 dev_priv->panel_fixed_mode->type |=
2077 DRM_MODE_TYPE_PREFERRED;
2080 dev_priv->int_edp_connector = connector;
2081 intel_panel_setup_backlight(dev);
2084 intel_dp_add_properties(intel_dp, connector);
2086 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2087 * 0xd. Failure to do so will result in spurious interrupts being
2088 * generated on the port when a cable is not attached.
2090 if (IS_G4X(dev) && !IS_GM45(dev)) {
2091 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2092 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);