2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
56 struct i2c_adapter adapter;
57 struct i2c_algo_dp_aux_data algo;
60 uint8_t link_status[DP_LINK_STATUS_SIZE];
64 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
65 * @intel_dp: DP struct
67 * If a CPU or PCH DP output is attached to an eDP panel, this function
68 * will return true, and false otherwise.
70 static bool is_edp(struct intel_dp *intel_dp)
72 return intel_dp->base.type == INTEL_OUTPUT_EDP;
76 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
77 * @intel_dp: DP struct
79 * Returns true if the given DP struct corresponds to a PCH DP port attached
80 * to an eDP panel, false otherwise. Helpful for determining whether we
81 * may need FDI resources for a given DP output or not.
83 static bool is_pch_edp(struct intel_dp *intel_dp)
85 return intel_dp->is_pch_edp;
88 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
90 return container_of(encoder, struct intel_dp, base.base);
93 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
95 return container_of(intel_attached_encoder(connector),
96 struct intel_dp, base);
100 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
101 * @encoder: DRM encoder
103 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
104 * by intel_display.c.
106 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
108 struct intel_dp *intel_dp;
113 intel_dp = enc_to_intel_dp(encoder);
115 return is_pch_edp(intel_dp);
118 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
119 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_link_down(struct intel_dp *intel_dp);
123 intel_edp_link_config (struct intel_encoder *intel_encoder,
124 int *lane_num, int *link_bw)
126 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
128 *lane_num = intel_dp->lane_count;
129 if (intel_dp->link_bw == DP_LINK_BW_1_62)
131 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
136 intel_dp_max_lane_count(struct intel_dp *intel_dp)
138 int max_lane_count = 4;
140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
141 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
142 switch (max_lane_count) {
143 case 1: case 2: case 4:
149 return max_lane_count;
153 intel_dp_max_link_bw(struct intel_dp *intel_dp)
155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
157 switch (max_link_bw) {
158 case DP_LINK_BW_1_62:
162 max_link_bw = DP_LINK_BW_1_62;
169 intel_dp_link_clock(uint8_t link_bw)
171 if (link_bw == DP_LINK_BW_2_7)
177 /* I think this is a fiction */
179 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
181 struct drm_i915_private *dev_priv = dev->dev_private;
183 if (is_edp(intel_dp))
184 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
186 return pixel_clock * 3;
190 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
192 return (max_link_clock * max_lanes * 8) / 10;
196 intel_dp_mode_valid(struct drm_connector *connector,
197 struct drm_display_mode *mode)
199 struct intel_dp *intel_dp = intel_attached_dp(connector);
200 struct drm_device *dev = connector->dev;
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
203 int max_lanes = intel_dp_max_lane_count(intel_dp);
205 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
206 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
209 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
213 /* only refuse the mode on non eDP since we have seen some weird eDP panels
214 which are outside spec tolerances but somehow work by magic */
215 if (!is_edp(intel_dp) &&
216 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
217 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
218 return MODE_CLOCK_HIGH;
220 if (mode->clock < 10000)
221 return MODE_CLOCK_LOW;
227 pack_aux(uint8_t *src, int src_bytes)
234 for (i = 0; i < src_bytes; i++)
235 v |= ((uint32_t) src[i]) << ((3-i) * 8);
240 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
245 for (i = 0; i < dst_bytes; i++)
246 dst[i] = src >> ((3-i) * 8);
249 /* hrawclock is 1/4 the FSB frequency */
251 intel_hrawclk(struct drm_device *dev)
253 struct drm_i915_private *dev_priv = dev->dev_private;
256 clkcfg = I915_READ(CLKCFG);
257 switch (clkcfg & CLKCFG_FSB_MASK) {
266 case CLKCFG_FSB_1067:
268 case CLKCFG_FSB_1333:
270 /* these two are just a guess; one of them might be right */
271 case CLKCFG_FSB_1600:
272 case CLKCFG_FSB_1600_ALT:
280 intel_dp_aux_ch(struct intel_dp *intel_dp,
281 uint8_t *send, int send_bytes,
282 uint8_t *recv, int recv_size)
284 uint32_t output_reg = intel_dp->output_reg;
285 struct drm_device *dev = intel_dp->base.base.dev;
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 uint32_t ch_ctl = output_reg + 0x10;
288 uint32_t ch_data = ch_ctl + 4;
292 uint32_t aux_clock_divider;
295 /* The clock divider is based off the hrawclk,
296 * and would like to run at 2MHz. So, take the
297 * hrawclk value and divide by 2 and use that
299 * Note that PCH attached eDP panels should use a 125MHz input
302 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
304 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
306 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
307 } else if (HAS_PCH_SPLIT(dev))
308 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
310 aux_clock_divider = intel_hrawclk(dev) / 2;
317 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
318 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
323 /* Must try at least 3 times according to DP spec */
324 for (try = 0; try < 5; try++) {
325 /* Load the send data into the aux channel data registers */
326 for (i = 0; i < send_bytes; i += 4)
327 I915_WRITE(ch_data + i,
328 pack_aux(send + i, send_bytes - i));
330 /* Send the command and wait for it to complete */
332 DP_AUX_CH_CTL_SEND_BUSY |
333 DP_AUX_CH_CTL_TIME_OUT_400us |
334 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
335 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
336 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
338 DP_AUX_CH_CTL_TIME_OUT_ERROR |
339 DP_AUX_CH_CTL_RECEIVE_ERROR);
341 status = I915_READ(ch_ctl);
342 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
347 /* Clear done status and any errors */
351 DP_AUX_CH_CTL_TIME_OUT_ERROR |
352 DP_AUX_CH_CTL_RECEIVE_ERROR);
353 if (status & DP_AUX_CH_CTL_DONE)
357 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
358 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
362 /* Check for timeout or receive error.
363 * Timeouts occur when the sink is not connected
365 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
366 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
370 /* Timeouts occur when the device isn't connected, so they're
371 * "normal" -- don't fill the kernel log with these */
372 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
373 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
377 /* Unload any bytes sent back from the other side */
378 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
379 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
380 if (recv_bytes > recv_size)
381 recv_bytes = recv_size;
383 for (i = 0; i < recv_bytes; i += 4)
384 unpack_aux(I915_READ(ch_data + i),
385 recv + i, recv_bytes - i);
390 /* Write data to the aux channel in native mode */
392 intel_dp_aux_native_write(struct intel_dp *intel_dp,
393 uint16_t address, uint8_t *send, int send_bytes)
402 msg[0] = AUX_NATIVE_WRITE << 4;
403 msg[1] = address >> 8;
404 msg[2] = address & 0xff;
405 msg[3] = send_bytes - 1;
406 memcpy(&msg[4], send, send_bytes);
407 msg_bytes = send_bytes + 4;
409 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
412 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
414 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
422 /* Write a single byte to the aux channel in native mode */
424 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
425 uint16_t address, uint8_t byte)
427 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
430 /* read bytes from a native aux channel */
432 intel_dp_aux_native_read(struct intel_dp *intel_dp,
433 uint16_t address, uint8_t *recv, int recv_bytes)
442 msg[0] = AUX_NATIVE_READ << 4;
443 msg[1] = address >> 8;
444 msg[2] = address & 0xff;
445 msg[3] = recv_bytes - 1;
448 reply_bytes = recv_bytes + 1;
451 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
458 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
459 memcpy(recv, reply + 1, ret - 1);
462 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
470 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
471 uint8_t write_byte, uint8_t *read_byte)
473 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
474 struct intel_dp *intel_dp = container_of(adapter,
477 uint16_t address = algo_data->address;
485 /* Set up the command byte */
486 if (mode & MODE_I2C_READ)
487 msg[0] = AUX_I2C_READ << 4;
489 msg[0] = AUX_I2C_WRITE << 4;
491 if (!(mode & MODE_I2C_STOP))
492 msg[0] |= AUX_I2C_MOT << 4;
494 msg[1] = address >> 8;
515 for (retry = 0; retry < 5; retry++) {
516 ret = intel_dp_aux_ch(intel_dp,
520 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
524 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
525 case AUX_NATIVE_REPLY_ACK:
526 /* I2C-over-AUX Reply field is only valid
527 * when paired with AUX ACK.
530 case AUX_NATIVE_REPLY_NACK:
531 DRM_DEBUG_KMS("aux_ch native nack\n");
533 case AUX_NATIVE_REPLY_DEFER:
537 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
542 switch (reply[0] & AUX_I2C_REPLY_MASK) {
543 case AUX_I2C_REPLY_ACK:
544 if (mode == MODE_I2C_READ) {
545 *read_byte = reply[1];
547 return reply_bytes - 1;
548 case AUX_I2C_REPLY_NACK:
549 DRM_DEBUG_KMS("aux_i2c nack\n");
551 case AUX_I2C_REPLY_DEFER:
552 DRM_DEBUG_KMS("aux_i2c defer\n");
556 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
561 DRM_ERROR("too many retries, giving up\n");
566 intel_dp_i2c_init(struct intel_dp *intel_dp,
567 struct intel_connector *intel_connector, const char *name)
569 DRM_DEBUG_KMS("i2c_init %s\n", name);
570 intel_dp->algo.running = false;
571 intel_dp->algo.address = 0;
572 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
574 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
575 intel_dp->adapter.owner = THIS_MODULE;
576 intel_dp->adapter.class = I2C_CLASS_DDC;
577 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
578 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
579 intel_dp->adapter.algo_data = &intel_dp->algo;
580 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
582 return i2c_dp_aux_add_bus(&intel_dp->adapter);
586 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
587 struct drm_display_mode *adjusted_mode)
589 struct drm_device *dev = encoder->dev;
590 struct drm_i915_private *dev_priv = dev->dev_private;
591 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
592 int lane_count, clock;
593 int max_lane_count = intel_dp_max_lane_count(intel_dp);
594 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
595 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
597 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
598 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
599 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
600 mode, adjusted_mode);
602 * the mode->clock is used to calculate the Data&Link M/N
603 * of the pipe. For the eDP the fixed clock should be used.
605 mode->clock = dev_priv->panel_fixed_mode->clock;
608 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
609 for (clock = 0; clock <= max_clock; clock++) {
610 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
612 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
614 intel_dp->link_bw = bws[clock];
615 intel_dp->lane_count = lane_count;
616 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
617 DRM_DEBUG_KMS("Display port link bw %02x lane "
618 "count %d clock %d\n",
619 intel_dp->link_bw, intel_dp->lane_count,
620 adjusted_mode->clock);
626 if (is_edp(intel_dp)) {
627 /* okay we failed just pick the highest */
628 intel_dp->lane_count = max_lane_count;
629 intel_dp->link_bw = bws[max_clock];
630 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
631 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
632 "count %d clock %d\n",
633 intel_dp->link_bw, intel_dp->lane_count,
634 adjusted_mode->clock);
642 struct intel_dp_m_n {
651 intel_reduce_ratio(uint32_t *num, uint32_t *den)
653 while (*num > 0xffffff || *den > 0xffffff) {
660 intel_dp_compute_m_n(int bpp,
664 struct intel_dp_m_n *m_n)
667 m_n->gmch_m = (pixel_clock * bpp) >> 3;
668 m_n->gmch_n = link_clock * nlanes;
669 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
670 m_n->link_m = pixel_clock;
671 m_n->link_n = link_clock;
672 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
676 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
677 struct drm_display_mode *adjusted_mode)
679 struct drm_device *dev = crtc->dev;
680 struct drm_mode_config *mode_config = &dev->mode_config;
681 struct drm_encoder *encoder;
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
684 int lane_count = 4, bpp = 24;
685 struct intel_dp_m_n m_n;
686 int pipe = intel_crtc->pipe;
689 * Find the lane count in the intel_encoder private
691 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
692 struct intel_dp *intel_dp;
694 if (encoder->crtc != crtc)
697 intel_dp = enc_to_intel_dp(encoder);
698 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
699 lane_count = intel_dp->lane_count;
701 } else if (is_edp(intel_dp)) {
702 lane_count = dev_priv->edp.lanes;
703 bpp = dev_priv->edp.bpp;
709 * Compute the GMCH and Link ratios. The '3' here is
710 * the number of bytes_per_pixel post-LUT, which we always
711 * set up for 8-bits of R/G/B, or 3 bytes total.
713 intel_dp_compute_m_n(bpp, lane_count,
714 mode->clock, adjusted_mode->clock, &m_n);
716 if (HAS_PCH_SPLIT(dev)) {
717 I915_WRITE(TRANSDATA_M1(pipe),
718 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
720 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
721 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
722 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
724 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
725 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
727 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
728 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
729 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
734 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
735 struct drm_display_mode *adjusted_mode)
737 struct drm_device *dev = encoder->dev;
738 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
739 struct drm_crtc *crtc = intel_dp->base.base.crtc;
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
743 intel_dp->DP |= intel_dp->color_range;
745 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
746 intel_dp->DP |= DP_SYNC_HS_HIGH;
747 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
748 intel_dp->DP |= DP_SYNC_VS_HIGH;
750 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
751 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
753 intel_dp->DP |= DP_LINK_TRAIN_OFF;
755 switch (intel_dp->lane_count) {
757 intel_dp->DP |= DP_PORT_WIDTH_1;
760 intel_dp->DP |= DP_PORT_WIDTH_2;
763 intel_dp->DP |= DP_PORT_WIDTH_4;
766 if (intel_dp->has_audio)
767 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
769 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
770 intel_dp->link_configuration[0] = intel_dp->link_bw;
771 intel_dp->link_configuration[1] = intel_dp->lane_count;
774 * Check for DPCD version > 1.1 and enhanced framing support
776 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
777 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
779 intel_dp->DP |= DP_ENHANCED_FRAMING;
782 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
783 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
784 intel_dp->DP |= DP_PIPEB_SELECT;
786 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
787 /* don't miss out required setting for eDP */
788 intel_dp->DP |= DP_PLL_ENABLE;
789 if (adjusted_mode->clock < 200000)
790 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
792 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
796 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
798 struct drm_device *dev = intel_dp->base.base.dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
803 * If the panel wasn't on, make sure there's not a currently
804 * active PP sequence before enabling AUX VDD.
806 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
807 msleep(dev_priv->panel_t3);
809 pp = I915_READ(PCH_PP_CONTROL);
811 I915_WRITE(PCH_PP_CONTROL, pp);
812 POSTING_READ(PCH_PP_CONTROL);
815 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
817 struct drm_device *dev = intel_dp->base.base.dev;
818 struct drm_i915_private *dev_priv = dev->dev_private;
821 pp = I915_READ(PCH_PP_CONTROL);
822 pp &= ~EDP_FORCE_VDD;
823 I915_WRITE(PCH_PP_CONTROL, pp);
824 POSTING_READ(PCH_PP_CONTROL);
826 /* Make sure sequencer is idle before allowing subsequent activity */
827 msleep(dev_priv->panel_t12);
830 /* Returns true if the panel was already on when called */
831 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
833 struct drm_device *dev = intel_dp->base.base.dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
837 if (I915_READ(PCH_PP_STATUS) & PP_ON)
840 pp = I915_READ(PCH_PP_CONTROL);
842 /* ILK workaround: disable reset around power sequence */
843 pp &= ~PANEL_POWER_RESET;
844 I915_WRITE(PCH_PP_CONTROL, pp);
845 POSTING_READ(PCH_PP_CONTROL);
847 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
848 I915_WRITE(PCH_PP_CONTROL, pp);
849 POSTING_READ(PCH_PP_CONTROL);
851 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
853 DRM_ERROR("panel on wait timed out: 0x%08x\n",
854 I915_READ(PCH_PP_STATUS));
856 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
857 I915_WRITE(PCH_PP_CONTROL, pp);
858 POSTING_READ(PCH_PP_CONTROL);
863 static void ironlake_edp_panel_off (struct drm_device *dev)
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
867 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
869 pp = I915_READ(PCH_PP_CONTROL);
871 /* ILK workaround: disable reset around power sequence */
872 pp &= ~PANEL_POWER_RESET;
873 I915_WRITE(PCH_PP_CONTROL, pp);
874 POSTING_READ(PCH_PP_CONTROL);
876 pp &= ~POWER_TARGET_ON;
877 I915_WRITE(PCH_PP_CONTROL, pp);
878 POSTING_READ(PCH_PP_CONTROL);
880 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
881 DRM_ERROR("panel off wait timed out: 0x%08x\n",
882 I915_READ(PCH_PP_STATUS));
884 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
885 I915_WRITE(PCH_PP_CONTROL, pp);
886 POSTING_READ(PCH_PP_CONTROL);
889 static void ironlake_edp_backlight_on (struct drm_device *dev)
891 struct drm_i915_private *dev_priv = dev->dev_private;
896 * If we enable the backlight right away following a panel power
897 * on, we may see slight flicker as the panel syncs with the eDP
898 * link. So delay a bit to make sure the image is solid before
899 * allowing it to appear.
902 pp = I915_READ(PCH_PP_CONTROL);
903 pp |= EDP_BLC_ENABLE;
904 I915_WRITE(PCH_PP_CONTROL, pp);
907 static void ironlake_edp_backlight_off (struct drm_device *dev)
909 struct drm_i915_private *dev_priv = dev->dev_private;
913 pp = I915_READ(PCH_PP_CONTROL);
914 pp &= ~EDP_BLC_ENABLE;
915 I915_WRITE(PCH_PP_CONTROL, pp);
918 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
920 struct drm_device *dev = encoder->dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
925 dpa_ctl = I915_READ(DP_A);
926 dpa_ctl |= DP_PLL_ENABLE;
927 I915_WRITE(DP_A, dpa_ctl);
932 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
934 struct drm_device *dev = encoder->dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
938 dpa_ctl = I915_READ(DP_A);
939 dpa_ctl &= ~DP_PLL_ENABLE;
940 I915_WRITE(DP_A, dpa_ctl);
945 /* If the sink supports it, try to set the power state appropriately */
946 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
950 /* Should have a valid DPCD by this point */
951 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
954 if (mode != DRM_MODE_DPMS_ON) {
955 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
958 DRM_DEBUG_DRIVER("failed to write sink power state\n");
961 * When turning on, we need to retry for 1ms to give the sink
964 for (i = 0; i < 3; i++) {
965 ret = intel_dp_aux_native_write_1(intel_dp,
975 static void intel_dp_prepare(struct drm_encoder *encoder)
977 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
978 struct drm_device *dev = encoder->dev;
980 /* Wake up the sink first */
981 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
983 if (is_edp(intel_dp)) {
984 ironlake_edp_backlight_off(dev);
985 ironlake_edp_panel_off(dev);
986 if (!is_pch_edp(intel_dp))
987 ironlake_edp_pll_on(encoder);
989 ironlake_edp_pll_off(encoder);
991 intel_dp_link_down(intel_dp);
994 static void intel_dp_commit(struct drm_encoder *encoder)
996 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
997 struct drm_device *dev = encoder->dev;
999 if (is_edp(intel_dp))
1000 ironlake_edp_panel_vdd_on(intel_dp);
1002 intel_dp_start_link_train(intel_dp);
1004 if (is_edp(intel_dp)) {
1005 ironlake_edp_panel_on(intel_dp);
1006 ironlake_edp_panel_vdd_off(intel_dp);
1009 intel_dp_complete_link_train(intel_dp);
1011 if (is_edp(intel_dp))
1012 ironlake_edp_backlight_on(dev);
1016 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1018 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1019 struct drm_device *dev = encoder->dev;
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1023 if (mode != DRM_MODE_DPMS_ON) {
1024 if (is_edp(intel_dp))
1025 ironlake_edp_backlight_off(dev);
1026 intel_dp_sink_dpms(intel_dp, mode);
1027 intel_dp_link_down(intel_dp);
1028 if (is_edp(intel_dp))
1029 ironlake_edp_panel_off(dev);
1030 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1031 ironlake_edp_pll_off(encoder);
1033 if (is_edp(intel_dp))
1034 ironlake_edp_panel_vdd_on(intel_dp);
1035 intel_dp_sink_dpms(intel_dp, mode);
1036 if (!(dp_reg & DP_PORT_EN)) {
1037 intel_dp_start_link_train(intel_dp);
1038 if (is_edp(intel_dp)) {
1039 ironlake_edp_panel_on(intel_dp);
1040 ironlake_edp_panel_vdd_off(intel_dp);
1042 intel_dp_complete_link_train(intel_dp);
1044 if (is_edp(intel_dp))
1045 ironlake_edp_backlight_on(dev);
1050 * Native read with retry for link status and receiver capability reads for
1051 * cases where the sink may still be asleep.
1054 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1055 uint8_t *recv, int recv_bytes)
1060 * Sinks are *supposed* to come up within 1ms from an off state,
1061 * but we're also supposed to retry 3 times per the spec.
1063 for (i = 0; i < 3; i++) {
1064 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1066 if (ret == recv_bytes)
1075 * Fetch AUX CH registers 0x202 - 0x207 which contain
1076 * link status information
1079 intel_dp_get_link_status(struct intel_dp *intel_dp)
1081 return intel_dp_aux_native_read_retry(intel_dp,
1083 intel_dp->link_status,
1084 DP_LINK_STATUS_SIZE);
1088 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1091 return link_status[r - DP_LANE0_1_STATUS];
1095 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1098 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1099 int s = ((lane & 1) ?
1100 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1101 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1102 uint8_t l = intel_dp_link_status(link_status, i);
1104 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1108 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1112 int s = ((lane & 1) ?
1113 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1114 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1115 uint8_t l = intel_dp_link_status(link_status, i);
1117 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1122 static char *voltage_names[] = {
1123 "0.4V", "0.6V", "0.8V", "1.2V"
1125 static char *pre_emph_names[] = {
1126 "0dB", "3.5dB", "6dB", "9.5dB"
1128 static char *link_train_names[] = {
1129 "pattern 1", "pattern 2", "idle", "off"
1134 * These are source-specific values; current Intel hardware supports
1135 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1137 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1140 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1142 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1143 case DP_TRAIN_VOLTAGE_SWING_400:
1144 return DP_TRAIN_PRE_EMPHASIS_6;
1145 case DP_TRAIN_VOLTAGE_SWING_600:
1146 return DP_TRAIN_PRE_EMPHASIS_6;
1147 case DP_TRAIN_VOLTAGE_SWING_800:
1148 return DP_TRAIN_PRE_EMPHASIS_3_5;
1149 case DP_TRAIN_VOLTAGE_SWING_1200:
1151 return DP_TRAIN_PRE_EMPHASIS_0;
1156 intel_get_adjust_train(struct intel_dp *intel_dp)
1162 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1163 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1164 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1172 if (v >= I830_DP_VOLTAGE_MAX)
1173 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1175 if (p >= intel_dp_pre_emphasis_max(v))
1176 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1178 for (lane = 0; lane < 4; lane++)
1179 intel_dp->train_set[lane] = v | p;
1183 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1185 uint32_t signal_levels = 0;
1187 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1188 case DP_TRAIN_VOLTAGE_SWING_400:
1190 signal_levels |= DP_VOLTAGE_0_4;
1192 case DP_TRAIN_VOLTAGE_SWING_600:
1193 signal_levels |= DP_VOLTAGE_0_6;
1195 case DP_TRAIN_VOLTAGE_SWING_800:
1196 signal_levels |= DP_VOLTAGE_0_8;
1198 case DP_TRAIN_VOLTAGE_SWING_1200:
1199 signal_levels |= DP_VOLTAGE_1_2;
1202 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1203 case DP_TRAIN_PRE_EMPHASIS_0:
1205 signal_levels |= DP_PRE_EMPHASIS_0;
1207 case DP_TRAIN_PRE_EMPHASIS_3_5:
1208 signal_levels |= DP_PRE_EMPHASIS_3_5;
1210 case DP_TRAIN_PRE_EMPHASIS_6:
1211 signal_levels |= DP_PRE_EMPHASIS_6;
1213 case DP_TRAIN_PRE_EMPHASIS_9_5:
1214 signal_levels |= DP_PRE_EMPHASIS_9_5;
1217 return signal_levels;
1220 /* Gen6's DP voltage swing and pre-emphasis control */
1222 intel_gen6_edp_signal_levels(uint8_t train_set)
1224 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1225 DP_TRAIN_PRE_EMPHASIS_MASK);
1226 switch (signal_levels) {
1227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1230 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1231 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1232 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1233 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1234 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1235 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1236 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1237 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1238 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1239 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1240 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1242 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1243 "0x%x\n", signal_levels);
1244 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1249 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1252 int i = DP_LANE0_1_STATUS + (lane >> 1);
1253 int s = (lane & 1) * 4;
1254 uint8_t l = intel_dp_link_status(link_status, i);
1256 return (l >> s) & 0xf;
1259 /* Check for clock recovery is done on all channels */
1261 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1264 uint8_t lane_status;
1266 for (lane = 0; lane < lane_count; lane++) {
1267 lane_status = intel_get_lane_status(link_status, lane);
1268 if ((lane_status & DP_LANE_CR_DONE) == 0)
1274 /* Check to see if channel eq is done on all channels */
1275 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1276 DP_LANE_CHANNEL_EQ_DONE|\
1277 DP_LANE_SYMBOL_LOCKED)
1279 intel_channel_eq_ok(struct intel_dp *intel_dp)
1282 uint8_t lane_status;
1285 lane_align = intel_dp_link_status(intel_dp->link_status,
1286 DP_LANE_ALIGN_STATUS_UPDATED);
1287 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1289 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1290 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1291 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1298 intel_dp_set_link_train(struct intel_dp *intel_dp,
1299 uint32_t dp_reg_value,
1300 uint8_t dp_train_pat)
1302 struct drm_device *dev = intel_dp->base.base.dev;
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1306 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1307 POSTING_READ(intel_dp->output_reg);
1309 intel_dp_aux_native_write_1(intel_dp,
1310 DP_TRAINING_PATTERN_SET,
1313 ret = intel_dp_aux_native_write(intel_dp,
1314 DP_TRAINING_LANE0_SET,
1315 intel_dp->train_set, 4);
1322 /* Enable corresponding port and start training pattern 1 */
1324 intel_dp_start_link_train(struct intel_dp *intel_dp)
1326 struct drm_device *dev = intel_dp->base.base.dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1331 bool clock_recovery = false;
1334 uint32_t DP = intel_dp->DP;
1336 /* Enable output, wait for it to become active */
1337 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1338 POSTING_READ(intel_dp->output_reg);
1339 intel_wait_for_vblank(dev, intel_crtc->pipe);
1341 /* Write the link configuration data */
1342 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1343 intel_dp->link_configuration,
1344 DP_LINK_CONFIGURATION_SIZE);
1347 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1348 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1350 DP &= ~DP_LINK_TRAIN_MASK;
1351 memset(intel_dp->train_set, 0, 4);
1354 clock_recovery = false;
1356 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1357 uint32_t signal_levels;
1358 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1359 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1360 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1362 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1363 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1366 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1367 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1369 reg = DP | DP_LINK_TRAIN_PAT_1;
1371 if (!intel_dp_set_link_train(intel_dp, reg,
1372 DP_TRAINING_PATTERN_1))
1374 /* Set training pattern 1 */
1377 if (!intel_dp_get_link_status(intel_dp))
1380 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1381 clock_recovery = true;
1385 /* Check to see if we've tried the max voltage */
1386 for (i = 0; i < intel_dp->lane_count; i++)
1387 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1389 if (i == intel_dp->lane_count)
1392 /* Check to see if we've tried the same voltage 5 times */
1393 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1399 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1401 /* Compute new intel_dp->train_set as requested by target */
1402 intel_get_adjust_train(intel_dp);
1409 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1411 struct drm_device *dev = intel_dp->base.base.dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 bool channel_eq = false;
1414 int tries, cr_tries;
1416 uint32_t DP = intel_dp->DP;
1418 /* channel equalization */
1423 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1424 uint32_t signal_levels;
1427 DRM_ERROR("failed to train DP, aborting\n");
1428 intel_dp_link_down(intel_dp);
1432 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1433 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1434 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1436 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1437 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1440 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1441 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1443 reg = DP | DP_LINK_TRAIN_PAT_2;
1445 /* channel eq pattern */
1446 if (!intel_dp_set_link_train(intel_dp, reg,
1447 DP_TRAINING_PATTERN_2))
1451 if (!intel_dp_get_link_status(intel_dp))
1454 /* Make sure clock is still ok */
1455 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1456 intel_dp_start_link_train(intel_dp);
1461 if (intel_channel_eq_ok(intel_dp)) {
1466 /* Try 5 times, then try clock recovery if that fails */
1468 intel_dp_link_down(intel_dp);
1469 intel_dp_start_link_train(intel_dp);
1475 /* Compute new intel_dp->train_set as requested by target */
1476 intel_get_adjust_train(intel_dp);
1480 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1481 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1483 reg = DP | DP_LINK_TRAIN_OFF;
1485 I915_WRITE(intel_dp->output_reg, reg);
1486 POSTING_READ(intel_dp->output_reg);
1487 intel_dp_aux_native_write_1(intel_dp,
1488 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1492 intel_dp_link_down(struct intel_dp *intel_dp)
1494 struct drm_device *dev = intel_dp->base.base.dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 uint32_t DP = intel_dp->DP;
1498 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1501 DRM_DEBUG_KMS("\n");
1503 if (is_edp(intel_dp)) {
1504 DP &= ~DP_PLL_ENABLE;
1505 I915_WRITE(intel_dp->output_reg, DP);
1506 POSTING_READ(intel_dp->output_reg);
1510 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1511 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1512 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1514 DP &= ~DP_LINK_TRAIN_MASK;
1515 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1517 POSTING_READ(intel_dp->output_reg);
1521 if (is_edp(intel_dp))
1522 DP |= DP_LINK_TRAIN_OFF;
1524 if (!HAS_PCH_CPT(dev) &&
1525 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1526 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1528 /* Hardware workaround: leaving our transcoder select
1529 * set to transcoder B while it's off will prevent the
1530 * corresponding HDMI output on transcoder A.
1532 * Combine this with another hardware workaround:
1533 * transcoder select bit can only be cleared while the
1536 DP &= ~DP_PIPEB_SELECT;
1537 I915_WRITE(intel_dp->output_reg, DP);
1539 /* Changes to enable or select take place the vblank
1540 * after being written.
1543 /* We can arrive here never having been attached
1544 * to a CRTC, for instance, due to inheriting
1545 * random state from the BIOS.
1547 * If the pipe is not running, play safe and
1548 * wait for the clocks to stabilise before
1551 POSTING_READ(intel_dp->output_reg);
1554 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1557 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1558 POSTING_READ(intel_dp->output_reg);
1562 * According to DP spec
1565 * 2. Configure link according to Receiver Capabilities
1566 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1567 * 4. Check link status on receipt of hot-plug interrupt
1571 intel_dp_check_link_status(struct intel_dp *intel_dp)
1575 if (!intel_dp->base.base.crtc)
1578 if (!intel_dp_get_link_status(intel_dp)) {
1579 intel_dp_link_down(intel_dp);
1583 /* Try to read receiver status if the link appears to be up */
1584 ret = intel_dp_aux_native_read(intel_dp,
1585 0x000, intel_dp->dpcd,
1586 sizeof (intel_dp->dpcd));
1587 if (ret != sizeof(intel_dp->dpcd)) {
1588 intel_dp_link_down(intel_dp);
1592 if (!intel_channel_eq_ok(intel_dp)) {
1593 intel_dp_start_link_train(intel_dp);
1594 intel_dp_complete_link_train(intel_dp);
1598 static enum drm_connector_status
1599 ironlake_dp_detect(struct intel_dp *intel_dp)
1601 enum drm_connector_status status;
1604 /* Can't disconnect eDP, but you can close the lid... */
1605 if (is_edp(intel_dp)) {
1606 status = intel_panel_detect(intel_dp->base.base.dev);
1607 if (status == connector_status_unknown)
1608 status = connector_status_connected;
1612 status = connector_status_disconnected;
1613 ret = intel_dp_aux_native_read_retry(intel_dp,
1614 0x000, intel_dp->dpcd,
1615 sizeof (intel_dp->dpcd));
1616 if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
1617 status = connector_status_connected;
1618 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1619 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1623 static enum drm_connector_status
1624 g4x_dp_detect(struct intel_dp *intel_dp)
1626 struct drm_device *dev = intel_dp->base.base.dev;
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 enum drm_connector_status status;
1631 switch (intel_dp->output_reg) {
1633 bit = DPB_HOTPLUG_INT_STATUS;
1636 bit = DPC_HOTPLUG_INT_STATUS;
1639 bit = DPD_HOTPLUG_INT_STATUS;
1642 return connector_status_unknown;
1645 temp = I915_READ(PORT_HOTPLUG_STAT);
1647 if ((temp & bit) == 0)
1648 return connector_status_disconnected;
1650 status = connector_status_disconnected;
1651 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1652 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1654 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1655 status = connector_status_connected;
1662 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1664 * \return true if DP port is connected.
1665 * \return false if DP port is disconnected.
1667 static enum drm_connector_status
1668 intel_dp_detect(struct drm_connector *connector, bool force)
1670 struct intel_dp *intel_dp = intel_attached_dp(connector);
1671 struct drm_device *dev = intel_dp->base.base.dev;
1672 enum drm_connector_status status;
1673 struct edid *edid = NULL;
1675 intel_dp->has_audio = false;
1677 if (HAS_PCH_SPLIT(dev))
1678 status = ironlake_dp_detect(intel_dp);
1680 status = g4x_dp_detect(intel_dp);
1681 if (status != connector_status_connected)
1684 if (intel_dp->force_audio) {
1685 intel_dp->has_audio = intel_dp->force_audio > 0;
1687 edid = drm_get_edid(connector, &intel_dp->adapter);
1689 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1690 connector->display_info.raw_edid = NULL;
1695 return connector_status_connected;
1698 static int intel_dp_get_modes(struct drm_connector *connector)
1700 struct intel_dp *intel_dp = intel_attached_dp(connector);
1701 struct drm_device *dev = intel_dp->base.base.dev;
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1705 /* We should parse the EDID data and find out if it has an audio sink
1708 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1710 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1711 struct drm_display_mode *newmode;
1712 list_for_each_entry(newmode, &connector->probed_modes,
1714 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1715 dev_priv->panel_fixed_mode =
1716 drm_mode_duplicate(dev, newmode);
1725 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1726 if (is_edp(intel_dp)) {
1727 if (dev_priv->panel_fixed_mode != NULL) {
1728 struct drm_display_mode *mode;
1729 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1730 drm_mode_probed_add(connector, mode);
1738 intel_dp_detect_audio(struct drm_connector *connector)
1740 struct intel_dp *intel_dp = intel_attached_dp(connector);
1742 bool has_audio = false;
1744 edid = drm_get_edid(connector, &intel_dp->adapter);
1746 has_audio = drm_detect_monitor_audio(edid);
1748 connector->display_info.raw_edid = NULL;
1756 intel_dp_set_property(struct drm_connector *connector,
1757 struct drm_property *property,
1760 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1761 struct intel_dp *intel_dp = intel_attached_dp(connector);
1764 ret = drm_connector_property_set_value(connector, property, val);
1768 if (property == dev_priv->force_audio_property) {
1772 if (i == intel_dp->force_audio)
1775 intel_dp->force_audio = i;
1778 has_audio = intel_dp_detect_audio(connector);
1782 if (has_audio == intel_dp->has_audio)
1785 intel_dp->has_audio = has_audio;
1789 if (property == dev_priv->broadcast_rgb_property) {
1790 if (val == !!intel_dp->color_range)
1793 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1800 if (intel_dp->base.base.crtc) {
1801 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1802 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1811 intel_dp_destroy (struct drm_connector *connector)
1813 drm_sysfs_connector_remove(connector);
1814 drm_connector_cleanup(connector);
1818 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1822 i2c_del_adapter(&intel_dp->adapter);
1823 drm_encoder_cleanup(encoder);
1827 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1828 .dpms = intel_dp_dpms,
1829 .mode_fixup = intel_dp_mode_fixup,
1830 .prepare = intel_dp_prepare,
1831 .mode_set = intel_dp_mode_set,
1832 .commit = intel_dp_commit,
1835 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1836 .dpms = drm_helper_connector_dpms,
1837 .detect = intel_dp_detect,
1838 .fill_modes = drm_helper_probe_single_connector_modes,
1839 .set_property = intel_dp_set_property,
1840 .destroy = intel_dp_destroy,
1843 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1844 .get_modes = intel_dp_get_modes,
1845 .mode_valid = intel_dp_mode_valid,
1846 .best_encoder = intel_best_encoder,
1849 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1850 .destroy = intel_dp_encoder_destroy,
1854 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1856 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1858 intel_dp_check_link_status(intel_dp);
1861 /* Return which DP Port should be selected for Transcoder DP control */
1863 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1865 struct drm_device *dev = crtc->dev;
1866 struct drm_mode_config *mode_config = &dev->mode_config;
1867 struct drm_encoder *encoder;
1869 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1870 struct intel_dp *intel_dp;
1872 if (encoder->crtc != crtc)
1875 intel_dp = enc_to_intel_dp(encoder);
1876 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1877 return intel_dp->output_reg;
1883 /* check the VBT to see whether the eDP is on DP-D port */
1884 bool intel_dpd_is_edp(struct drm_device *dev)
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct child_device_config *p_child;
1890 if (!dev_priv->child_dev_num)
1893 for (i = 0; i < dev_priv->child_dev_num; i++) {
1894 p_child = dev_priv->child_dev + i;
1896 if (p_child->dvo_port == PORT_IDPD &&
1897 p_child->device_type == DEVICE_TYPE_eDP)
1904 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1906 intel_attach_force_audio_property(connector);
1907 intel_attach_broadcast_rgb_property(connector);
1911 intel_dp_init(struct drm_device *dev, int output_reg)
1913 struct drm_i915_private *dev_priv = dev->dev_private;
1914 struct drm_connector *connector;
1915 struct intel_dp *intel_dp;
1916 struct intel_encoder *intel_encoder;
1917 struct intel_connector *intel_connector;
1918 const char *name = NULL;
1921 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1925 intel_dp->output_reg = output_reg;
1927 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1928 if (!intel_connector) {
1932 intel_encoder = &intel_dp->base;
1934 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1935 if (intel_dpd_is_edp(dev))
1936 intel_dp->is_pch_edp = true;
1938 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1939 type = DRM_MODE_CONNECTOR_eDP;
1940 intel_encoder->type = INTEL_OUTPUT_EDP;
1942 type = DRM_MODE_CONNECTOR_DisplayPort;
1943 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1946 connector = &intel_connector->base;
1947 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1948 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1950 connector->polled = DRM_CONNECTOR_POLL_HPD;
1952 if (output_reg == DP_B || output_reg == PCH_DP_B)
1953 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1954 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1955 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1956 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1957 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1959 if (is_edp(intel_dp))
1960 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1962 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1963 connector->interlace_allowed = true;
1964 connector->doublescan_allowed = 0;
1966 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1967 DRM_MODE_ENCODER_TMDS);
1968 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1970 intel_connector_attach_encoder(intel_connector, intel_encoder);
1971 drm_sysfs_connector_add(connector);
1973 /* Set up the DDC bus. */
1974 switch (output_reg) {
1980 dev_priv->hotplug_supported_mask |=
1981 HDMIB_HOTPLUG_INT_STATUS;
1986 dev_priv->hotplug_supported_mask |=
1987 HDMIC_HOTPLUG_INT_STATUS;
1992 dev_priv->hotplug_supported_mask |=
1993 HDMID_HOTPLUG_INT_STATUS;
1998 intel_dp_i2c_init(intel_dp, intel_connector, name);
2000 /* Cache some DPCD data in the eDP case */
2001 if (is_edp(intel_dp)) {
2005 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2006 pp_div = I915_READ(PCH_PP_DIVISOR);
2008 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2009 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2010 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2011 dev_priv->panel_t12 = pp_div & 0xf;
2012 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2014 ironlake_edp_panel_vdd_on(intel_dp);
2015 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
2017 sizeof(intel_dp->dpcd));
2018 ironlake_edp_panel_vdd_off(intel_dp);
2019 if (ret == sizeof(intel_dp->dpcd)) {
2020 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2021 dev_priv->no_aux_handshake =
2022 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2023 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2025 /* if this fails, presume the device is a ghost */
2026 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2027 intel_dp_encoder_destroy(&intel_dp->base.base);
2028 intel_dp_destroy(&intel_connector->base);
2033 intel_encoder->hot_plug = intel_dp_hot_plug;
2035 if (is_edp(intel_dp)) {
2036 /* initialize panel mode from VBT if available for eDP */
2037 if (dev_priv->lfp_lvds_vbt_mode) {
2038 dev_priv->panel_fixed_mode =
2039 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2040 if (dev_priv->panel_fixed_mode) {
2041 dev_priv->panel_fixed_mode->type |=
2042 DRM_MODE_TYPE_PREFERRED;
2047 intel_dp_add_properties(intel_dp, connector);
2049 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2050 * 0xd. Failure to do so will result in spurious interrupts being
2051 * generated on the port when a cable is not attached.
2053 if (IS_G4X(dev) && !IS_GM45(dev)) {
2054 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2055 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);