drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         uint32_t color_range;
  53         uint8_t link_bw;
  54         uint8_t lane_count;
  55         uint8_t dpcd[8];
  56         struct i2c_adapter adapter;
  57         struct i2c_algo_dp_aux_data algo;
  58         bool is_pch_edp;
  59         uint8_t train_set[4];
  60         uint8_t link_status[DP_LINK_STATUS_SIZE];
  61 };
  62
  63 /**
  64  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  65  * @intel_dp: DP struct
  66  *
  67  * If a CPU or PCH DP output is attached to an eDP panel, this function
  68  * will return true, and false otherwise.
  69  */
  70 static bool is_edp(struct intel_dp *intel_dp)
  71 {
  72         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  73 }
  74
  75 /**
  76  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  77  * @intel_dp: DP struct
  78  *
  79  * Returns true if the given DP struct corresponds to a PCH DP port attached
  80  * to an eDP panel, false otherwise.  Helpful for determining whether we
  81  * may need FDI resources for a given DP output or not.
  82  */
  83 static bool is_pch_edp(struct intel_dp *intel_dp)
  84 {
  85         return intel_dp->is_pch_edp;
  86 }
  87
  88 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  89 {
  90         return container_of(encoder, struct intel_dp, base.base);
  91 }
  92
  93 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  94 {
  95         return container_of(intel_attached_encoder(connector),
  96                             struct intel_dp, base);
  97 }
  98
  99 /**
 100  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 101  * @encoder: DRM encoder
 102  *
 103  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 104  * by intel_display.c.
 105  */
 106 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 107 {
 108         struct intel_dp *intel_dp;
 109
 110         if (!encoder)
 111                 return false;
 112
 113         intel_dp = enc_to_intel_dp(encoder);
 114
 115         return is_pch_edp(intel_dp);
 116 }
 117
 118 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 119 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 120 static void intel_dp_link_down(struct intel_dp *intel_dp);
 121
 122 void
 123 intel_edp_link_config (struct intel_encoder *intel_encoder,
 124                        int *lane_num, int *link_bw)
 125 {
 126         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 127
 128         *lane_num = intel_dp->lane_count;
 129         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 130                 *link_bw = 162000;
 131         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 132                 *link_bw = 270000;
 133 }
 134
 135 static int
 136 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 137 {
 138         int max_lane_count = 4;
 139
 140         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 141                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 142                 switch (max_lane_count) {
 143                 case 1: case 2: case 4:
 144                         break;
 145                 default:
 146                         max_lane_count = 4;
 147                 }
 148         }
 149         return max_lane_count;
 150 }
 151
 152 static int
 153 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 154 {
 155         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 156
 157         switch (max_link_bw) {
 158         case DP_LINK_BW_1_62:
 159         case DP_LINK_BW_2_7:
 160                 break;
 161         default:
 162                 max_link_bw = DP_LINK_BW_1_62;
 163                 break;
 164         }
 165         return max_link_bw;
 166 }
 167
 168 static int
 169 intel_dp_link_clock(uint8_t link_bw)
 170 {
 171         if (link_bw == DP_LINK_BW_2_7)
 172                 return 270000;
 173         else
 174                 return 162000;
 175 }
 176
 177 /* I think this is a fiction */
 178 static int
 179 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 180 {
 181         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 183         int bpp = 24;
 184
 185         if (intel_crtc)
 186                 bpp = intel_crtc->bpp;
 187
 188         return (pixel_clock * bpp + 7) / 8;
 189 }
 190
 191 static int
 192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 193 {
 194         return (max_link_clock * max_lanes * 8) / 10;
 195 }
 196
 197 static int
 198 intel_dp_mode_valid(struct drm_connector *connector,
 199                     struct drm_display_mode *mode)
 200 {
 201         struct intel_dp *intel_dp = intel_attached_dp(connector);
 202         struct drm_device *dev = connector->dev;
 203         struct drm_i915_private *dev_priv = dev->dev_private;
 204         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 205         int max_lanes = intel_dp_max_lane_count(intel_dp);
 206
 207         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 208                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 209                         return MODE_PANEL;
 210
 211                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 212                         return MODE_PANEL;
 213         }
 214
 215         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 216            which are outside spec tolerances but somehow work by magic */
 217         if (!is_edp(intel_dp) &&
 218             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 219              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 220                 return MODE_CLOCK_HIGH;
 221
 222         if (mode->clock < 10000)
 223                 return MODE_CLOCK_LOW;
 224
 225         return MODE_OK;
 226 }
 227
 228 static uint32_t
 229 pack_aux(uint8_t *src, int src_bytes)
 230 {
 231         int     i;
 232         uint32_t v = 0;
 233
 234         if (src_bytes > 4)
 235                 src_bytes = 4;
 236         for (i = 0; i < src_bytes; i++)
 237                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 238         return v;
 239 }
 240
 241 static void
 242 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 243 {
 244         int i;
 245         if (dst_bytes > 4)
 246                 dst_bytes = 4;
 247         for (i = 0; i < dst_bytes; i++)
 248                 dst[i] = src >> ((3-i) * 8);
 249 }
 250
 251 /* hrawclock is 1/4 the FSB frequency */
 252 static int
 253 intel_hrawclk(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         uint32_t clkcfg;
 257
 258         clkcfg = I915_READ(CLKCFG);
 259         switch (clkcfg & CLKCFG_FSB_MASK) {
 260         case CLKCFG_FSB_400:
 261                 return 100;
 262         case CLKCFG_FSB_533:
 263                 return 133;
 264         case CLKCFG_FSB_667:
 265                 return 166;
 266         case CLKCFG_FSB_800:
 267                 return 200;
 268         case CLKCFG_FSB_1067:
 269                 return 266;
 270         case CLKCFG_FSB_1333:
 271                 return 333;
 272         /* these two are just a guess; one of them might be right */
 273         case CLKCFG_FSB_1600:
 274         case CLKCFG_FSB_1600_ALT:
 275                 return 400;
 276         default:
 277                 return 133;
 278         }
 279 }
 280
 281 static int
 282 intel_dp_aux_ch(struct intel_dp *intel_dp,
 283                 uint8_t *send, int send_bytes,
 284                 uint8_t *recv, int recv_size)
 285 {
 286         uint32_t output_reg = intel_dp->output_reg;
 287         struct drm_device *dev = intel_dp->base.base.dev;
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         uint32_t ch_ctl = output_reg + 0x10;
 290         uint32_t ch_data = ch_ctl + 4;
 291         int i;
 292         int recv_bytes;
 293         uint32_t status;
 294         uint32_t aux_clock_divider;
 295         int try, precharge;
 296
 297         /* The clock divider is based off the hrawclk,
 298          * and would like to run at 2MHz. So, take the
 299          * hrawclk value and divide by 2 and use that
 300          *
 301          * Note that PCH attached eDP panels should use a 125MHz input
 302          * clock divider.
 303          */
 304         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 305                 if (IS_GEN6(dev))
 306                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 307                 else
 308                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 309         } else if (HAS_PCH_SPLIT(dev))
 310                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 311         else
 312                 aux_clock_divider = intel_hrawclk(dev) / 2;
 313
 314         if (IS_GEN6(dev))
 315                 precharge = 3;
 316         else
 317                 precharge = 5;
 318
 319         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 320                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 321                           I915_READ(ch_ctl));
 322                 return -EBUSY;
 323         }
 324
 325         /* Must try at least 3 times according to DP spec */
 326         for (try = 0; try < 5; try++) {
 327                 /* Load the send data into the aux channel data registers */
 328                 for (i = 0; i < send_bytes; i += 4)
 329                         I915_WRITE(ch_data + i,
 330                                    pack_aux(send + i, send_bytes - i));
 331
 332                 /* Send the command and wait for it to complete */
 333                 I915_WRITE(ch_ctl,
 334                            DP_AUX_CH_CTL_SEND_BUSY |
 335                            DP_AUX_CH_CTL_TIME_OUT_400us |
 336                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 337                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 338                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 339                            DP_AUX_CH_CTL_DONE |
 340                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 341                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 342                 for (;;) {
 343                         status = I915_READ(ch_ctl);
 344                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 345                                 break;
 346                         udelay(100);
 347                 }
 348
 349                 /* Clear done status and any errors */
 350                 I915_WRITE(ch_ctl,
 351                            status |
 352                            DP_AUX_CH_CTL_DONE |
 353                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 354                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 355                 if (status & DP_AUX_CH_CTL_DONE)
 356                         break;
 357         }
 358
 359         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 360                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 361                 return -EBUSY;
 362         }
 363
 364         /* Check for timeout or receive error.
 365          * Timeouts occur when the sink is not connected
 366          */
 367         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 368                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 369                 return -EIO;
 370         }
 371
 372         /* Timeouts occur when the device isn't connected, so they're
 373          * "normal" -- don't fill the kernel log with these */
 374         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 375                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 376                 return -ETIMEDOUT;
 377         }
 378
 379         /* Unload any bytes sent back from the other side */
 380         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 381                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 382         if (recv_bytes > recv_size)
 383                 recv_bytes = recv_size;
 384
 385         for (i = 0; i < recv_bytes; i += 4)
 386                 unpack_aux(I915_READ(ch_data + i),
 387                            recv + i, recv_bytes - i);
 388
 389         return recv_bytes;
 390 }
 391
 392 /* Write data to the aux channel in native mode */
 393 static int
 394 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 395                           uint16_t address, uint8_t *send, int send_bytes)
 396 {
 397         int ret;
 398         uint8_t msg[20];
 399         int msg_bytes;
 400         uint8_t ack;
 401
 402         if (send_bytes > 16)
 403                 return -1;
 404         msg[0] = AUX_NATIVE_WRITE << 4;
 405         msg[1] = address >> 8;
 406         msg[2] = address & 0xff;
 407         msg[3] = send_bytes - 1;
 408         memcpy(&msg[4], send, send_bytes);
 409         msg_bytes = send_bytes + 4;
 410         for (;;) {
 411                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 412                 if (ret < 0)
 413                         return ret;
 414                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 415                         break;
 416                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 417                         udelay(100);
 418                 else
 419                         return -EIO;
 420         }
 421         return send_bytes;
 422 }
 423
 424 /* Write a single byte to the aux channel in native mode */
 425 static int
 426 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 427                             uint16_t address, uint8_t byte)
 428 {
 429         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 430 }
 431
 432 /* read bytes from a native aux channel */
 433 static int
 434 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 435                          uint16_t address, uint8_t *recv, int recv_bytes)
 436 {
 437         uint8_t msg[4];
 438         int msg_bytes;
 439         uint8_t reply[20];
 440         int reply_bytes;
 441         uint8_t ack;
 442         int ret;
 443
 444         msg[0] = AUX_NATIVE_READ << 4;
 445         msg[1] = address >> 8;
 446         msg[2] = address & 0xff;
 447         msg[3] = recv_bytes - 1;
 448
 449         msg_bytes = 4;
 450         reply_bytes = recv_bytes + 1;
 451
 452         for (;;) {
 453                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 454                                       reply, reply_bytes);
 455                 if (ret == 0)
 456                         return -EPROTO;
 457                 if (ret < 0)
 458                         return ret;
 459                 ack = reply[0];
 460                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 461                         memcpy(recv, reply + 1, ret - 1);
 462                         return ret - 1;
 463                 }
 464                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 465                         udelay(100);
 466                 else
 467                         return -EIO;
 468         }
 469 }
 470
 471 static int
 472 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 473                     uint8_t write_byte, uint8_t *read_byte)
 474 {
 475         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 476         struct intel_dp *intel_dp = container_of(adapter,
 477                                                 struct intel_dp,
 478                                                 adapter);
 479         uint16_t address = algo_data->address;
 480         uint8_t msg[5];
 481         uint8_t reply[2];
 482         unsigned retry;
 483         int msg_bytes;
 484         int reply_bytes;
 485         int ret;
 486
 487         /* Set up the command byte */
 488         if (mode & MODE_I2C_READ)
 489                 msg[0] = AUX_I2C_READ << 4;
 490         else
 491                 msg[0] = AUX_I2C_WRITE << 4;
 492
 493         if (!(mode & MODE_I2C_STOP))
 494                 msg[0] |= AUX_I2C_MOT << 4;
 495
 496         msg[1] = address >> 8;
 497         msg[2] = address;
 498
 499         switch (mode) {
 500         case MODE_I2C_WRITE:
 501                 msg[3] = 0;
 502                 msg[4] = write_byte;
 503                 msg_bytes = 5;
 504                 reply_bytes = 1;
 505                 break;
 506         case MODE_I2C_READ:
 507                 msg[3] = 0;
 508                 msg_bytes = 4;
 509                 reply_bytes = 2;
 510                 break;
 511         default:
 512                 msg_bytes = 3;
 513                 reply_bytes = 1;
 514                 break;
 515         }
 516
 517         for (retry = 0; retry < 5; retry++) {
 518                 ret = intel_dp_aux_ch(intel_dp,
 519                                       msg, msg_bytes,
 520                                       reply, reply_bytes);
 521                 if (ret < 0) {
 522                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 523                         return ret;
 524                 }
 525
 526                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 527                 case AUX_NATIVE_REPLY_ACK:
 528                         /* I2C-over-AUX Reply field is only valid
 529                          * when paired with AUX ACK.
 530                          */
 531                         break;
 532                 case AUX_NATIVE_REPLY_NACK:
 533                         DRM_DEBUG_KMS("aux_ch native nack\n");
 534                         return -EREMOTEIO;
 535                 case AUX_NATIVE_REPLY_DEFER:
 536                         udelay(100);
 537                         continue;
 538                 default:
 539                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 540                                   reply[0]);
 541                         return -EREMOTEIO;
 542                 }
 543
 544                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 545                 case AUX_I2C_REPLY_ACK:
 546                         if (mode == MODE_I2C_READ) {
 547                                 *read_byte = reply[1];
 548                         }
 549                         return reply_bytes - 1;
 550                 case AUX_I2C_REPLY_NACK:
 551                         DRM_DEBUG_KMS("aux_i2c nack\n");
 552                         return -EREMOTEIO;
 553                 case AUX_I2C_REPLY_DEFER:
 554                         DRM_DEBUG_KMS("aux_i2c defer\n");
 555                         udelay(100);
 556                         break;
 557                 default:
 558                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 559                         return -EREMOTEIO;
 560                 }
 561         }
 562
 563         DRM_ERROR("too many retries, giving up\n");
 564         return -EREMOTEIO;
 565 }
 566
 567 static int
 568 intel_dp_i2c_init(struct intel_dp *intel_dp,
 569                   struct intel_connector *intel_connector, const char *name)
 570 {
 571         DRM_DEBUG_KMS("i2c_init %s\n", name);
 572         intel_dp->algo.running = false;
 573         intel_dp->algo.address = 0;
 574         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 575
 576         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 577         intel_dp->adapter.owner = THIS_MODULE;
 578         intel_dp->adapter.class = I2C_CLASS_DDC;
 579         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 580         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 581         intel_dp->adapter.algo_data = &intel_dp->algo;
 582         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 583
 584         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 585 }
 586
 587 static bool
 588 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 589                     struct drm_display_mode *adjusted_mode)
 590 {
 591         struct drm_device *dev = encoder->dev;
 592         struct drm_i915_private *dev_priv = dev->dev_private;
 593         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 594         int lane_count, clock;
 595         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 596         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 597         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 598
 599         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 600                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 601                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 602                                         mode, adjusted_mode);
 603                 /*
 604                  * the mode->clock is used to calculate the Data&Link M/N
 605                  * of the pipe. For the eDP the fixed clock should be used.
 606                  */
 607                 mode->clock = dev_priv->panel_fixed_mode->clock;
 608         }
 609
 610         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 611                 for (clock = 0; clock <= max_clock; clock++) {
 612                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 613
 614                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 615                                         <= link_avail) {
 616                                 intel_dp->link_bw = bws[clock];
 617                                 intel_dp->lane_count = lane_count;
 618                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 619                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 620                                                 "count %d clock %d\n",
 621                                        intel_dp->link_bw, intel_dp->lane_count,
 622                                        adjusted_mode->clock);
 623                                 return true;
 624                         }
 625                 }
 626         }
 627
 628         if (is_edp(intel_dp)) {
 629                 /* okay we failed just pick the highest */
 630                 intel_dp->lane_count = max_lane_count;
 631                 intel_dp->link_bw = bws[max_clock];
 632                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 633                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 634                               "count %d clock %d\n",
 635                               intel_dp->link_bw, intel_dp->lane_count,
 636                               adjusted_mode->clock);
 637
 638                 return true;
 639         }
 640
 641         return false;
 642 }
 643
 644 struct intel_dp_m_n {
 645         uint32_t        tu;
 646         uint32_t        gmch_m;
 647         uint32_t        gmch_n;
 648         uint32_t        link_m;
 649         uint32_t        link_n;
 650 };
 651
 652 static void
 653 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 654 {
 655         while (*num > 0xffffff || *den > 0xffffff) {
 656                 *num >>= 1;
 657                 *den >>= 1;
 658         }
 659 }
 660
 661 static void
 662 intel_dp_compute_m_n(int bpp,
 663                      int nlanes,
 664                      int pixel_clock,
 665                      int link_clock,
 666                      struct intel_dp_m_n *m_n)
 667 {
 668         m_n->tu = 64;
 669         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 670         m_n->gmch_n = link_clock * nlanes;
 671         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 672         m_n->link_m = pixel_clock;
 673         m_n->link_n = link_clock;
 674         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 675 }
 676
 677 void
 678 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 679                  struct drm_display_mode *adjusted_mode)
 680 {
 681         struct drm_device *dev = crtc->dev;
 682         struct drm_mode_config *mode_config = &dev->mode_config;
 683         struct drm_encoder *encoder;
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 686         int lane_count = 4;
 687         struct intel_dp_m_n m_n;
 688         int pipe = intel_crtc->pipe;
 689
 690         /*
 691          * Find the lane count in the intel_encoder private
 692          */
 693         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 694                 struct intel_dp *intel_dp;
 695
 696                 if (encoder->crtc != crtc)
 697                         continue;
 698
 699                 intel_dp = enc_to_intel_dp(encoder);
 700                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 701                         lane_count = intel_dp->lane_count;
 702                         break;
 703                 } else if (is_edp(intel_dp)) {
 704                         lane_count = dev_priv->edp.lanes;
 705                         break;
 706                 }
 707         }
 708
 709         /*
 710          * Compute the GMCH and Link ratios. The '3' here is
 711          * the number of bytes_per_pixel post-LUT, which we always
 712          * set up for 8-bits of R/G/B, or 3 bytes total.
 713          */
 714         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 715                              mode->clock, adjusted_mode->clock, &m_n);
 716
 717         if (HAS_PCH_SPLIT(dev)) {
 718                 I915_WRITE(TRANSDATA_M1(pipe),
 719                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 720                            m_n.gmch_m);
 721                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 722                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 723                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 724         } else {
 725                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 726                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 727                            m_n.gmch_m);
 728                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 729                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 730                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 731         }
 732 }
 733
 734 static void
 735 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 736                   struct drm_display_mode *adjusted_mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 740         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 742
 743         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 744         intel_dp->DP |= intel_dp->color_range;
 745
 746         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 747                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 748         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 749                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 750
 751         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 752                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 753         else
 754                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 755
 756         switch (intel_dp->lane_count) {
 757         case 1:
 758                 intel_dp->DP |= DP_PORT_WIDTH_1;
 759                 break;
 760         case 2:
 761                 intel_dp->DP |= DP_PORT_WIDTH_2;
 762                 break;
 763         case 4:
 764                 intel_dp->DP |= DP_PORT_WIDTH_4;
 765                 break;
 766         }
 767         if (intel_dp->has_audio)
 768                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 769
 770         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 771         intel_dp->link_configuration[0] = intel_dp->link_bw;
 772         intel_dp->link_configuration[1] = intel_dp->lane_count;
 773         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 774
 775         /*
 776          * Check for DPCD version > 1.1 and enhanced framing support
 777          */
 778         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 779             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 780                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 781                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 782         }
 783
 784         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 785         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 786                 intel_dp->DP |= DP_PIPEB_SELECT;
 787
 788         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 789                 /* don't miss out required setting for eDP */
 790                 intel_dp->DP |= DP_PLL_ENABLE;
 791                 if (adjusted_mode->clock < 200000)
 792                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 793                 else
 794                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 795         }
 796 }
 797
 798 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 799 {
 800         struct drm_device *dev = intel_dp->base.base.dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         u32 pp;
 803
 804         /*
 805          * If the panel wasn't on, make sure there's not a currently
 806          * active PP sequence before enabling AUX VDD.
 807          */
 808         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
 809                 msleep(dev_priv->panel_t3);
 810
 811         pp = I915_READ(PCH_PP_CONTROL);
 812         pp |= EDP_FORCE_VDD;
 813         I915_WRITE(PCH_PP_CONTROL, pp);
 814         POSTING_READ(PCH_PP_CONTROL);
 815 }
 816
 817 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
 818 {
 819         struct drm_device *dev = intel_dp->base.base.dev;
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         u32 pp;
 822
 823         pp = I915_READ(PCH_PP_CONTROL);
 824         pp &= ~EDP_FORCE_VDD;
 825         I915_WRITE(PCH_PP_CONTROL, pp);
 826         POSTING_READ(PCH_PP_CONTROL);
 827
 828         /* Make sure sequencer is idle before allowing subsequent activity */
 829         msleep(dev_priv->panel_t12);
 830 }
 831
 832 /* Returns true if the panel was already on when called */
 833 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 834 {
 835         struct drm_device *dev = intel_dp->base.base.dev;
 836         struct drm_i915_private *dev_priv = dev->dev_private;
 837         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 838
 839         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 840                 return true;
 841
 842         pp = I915_READ(PCH_PP_CONTROL);
 843
 844         /* ILK workaround: disable reset around power sequence */
 845         pp &= ~PANEL_POWER_RESET;
 846         I915_WRITE(PCH_PP_CONTROL, pp);
 847         POSTING_READ(PCH_PP_CONTROL);
 848
 849         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 850         I915_WRITE(PCH_PP_CONTROL, pp);
 851         POSTING_READ(PCH_PP_CONTROL);
 852
 853         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 854                      5000))
 855                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 856                           I915_READ(PCH_PP_STATUS));
 857
 858         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 859         I915_WRITE(PCH_PP_CONTROL, pp);
 860         POSTING_READ(PCH_PP_CONTROL);
 861
 862         return false;
 863 }
 864
 865 static void ironlake_edp_panel_off (struct drm_device *dev)
 866 {
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 869                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 870
 871         pp = I915_READ(PCH_PP_CONTROL);
 872
 873         /* ILK workaround: disable reset around power sequence */
 874         pp &= ~PANEL_POWER_RESET;
 875         I915_WRITE(PCH_PP_CONTROL, pp);
 876         POSTING_READ(PCH_PP_CONTROL);
 877
 878         pp &= ~POWER_TARGET_ON;
 879         I915_WRITE(PCH_PP_CONTROL, pp);
 880         POSTING_READ(PCH_PP_CONTROL);
 881
 882         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 883                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 884                           I915_READ(PCH_PP_STATUS));
 885
 886         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 887         I915_WRITE(PCH_PP_CONTROL, pp);
 888         POSTING_READ(PCH_PP_CONTROL);
 889 }
 890
 891 static void ironlake_edp_backlight_on (struct drm_device *dev)
 892 {
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894         u32 pp;
 895
 896         DRM_DEBUG_KMS("\n");
 897         /*
 898          * If we enable the backlight right away following a panel power
 899          * on, we may see slight flicker as the panel syncs with the eDP
 900          * link.  So delay a bit to make sure the image is solid before
 901          * allowing it to appear.
 902          */
 903         msleep(300);
 904         pp = I915_READ(PCH_PP_CONTROL);
 905         pp |= EDP_BLC_ENABLE;
 906         I915_WRITE(PCH_PP_CONTROL, pp);
 907 }
 908
 909 static void ironlake_edp_backlight_off (struct drm_device *dev)
 910 {
 911         struct drm_i915_private *dev_priv = dev->dev_private;
 912         u32 pp;
 913
 914         DRM_DEBUG_KMS("\n");
 915         pp = I915_READ(PCH_PP_CONTROL);
 916         pp &= ~EDP_BLC_ENABLE;
 917         I915_WRITE(PCH_PP_CONTROL, pp);
 918 }
 919
 920 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 921 {
 922         struct drm_device *dev = encoder->dev;
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         u32 dpa_ctl;
 925
 926         DRM_DEBUG_KMS("\n");
 927         dpa_ctl = I915_READ(DP_A);
 928         dpa_ctl |= DP_PLL_ENABLE;
 929         I915_WRITE(DP_A, dpa_ctl);
 930         POSTING_READ(DP_A);
 931         udelay(200);
 932 }
 933
 934 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 935 {
 936         struct drm_device *dev = encoder->dev;
 937         struct drm_i915_private *dev_priv = dev->dev_private;
 938         u32 dpa_ctl;
 939
 940         dpa_ctl = I915_READ(DP_A);
 941         dpa_ctl &= ~DP_PLL_ENABLE;
 942         I915_WRITE(DP_A, dpa_ctl);
 943         POSTING_READ(DP_A);
 944         udelay(200);
 945 }
 946
 947 /* If the sink supports it, try to set the power state appropriately */
 948 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 949 {
 950         int ret, i;
 951
 952         /* Should have a valid DPCD by this point */
 953         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
 954                 return;
 955
 956         if (mode != DRM_MODE_DPMS_ON) {
 957                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
 958                                                   DP_SET_POWER_D3);
 959                 if (ret != 1)
 960                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
 961         } else {
 962                 /*
 963                  * When turning on, we need to retry for 1ms to give the sink
 964                  * time to wake up.
 965                  */
 966                 for (i = 0; i < 3; i++) {
 967                         ret = intel_dp_aux_native_write_1(intel_dp,
 968                                                           DP_SET_POWER,
 969                                                           DP_SET_POWER_D0);
 970                         if (ret == 1)
 971                                 break;
 972                         msleep(1);
 973                 }
 974         }
 975 }
 976
 977 static void intel_dp_prepare(struct drm_encoder *encoder)
 978 {
 979         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 980         struct drm_device *dev = encoder->dev;
 981
 982         /* Wake up the sink first */
 983         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 984
 985         if (is_edp(intel_dp)) {
 986                 ironlake_edp_backlight_off(dev);
 987                 ironlake_edp_panel_off(dev);
 988                 if (!is_pch_edp(intel_dp))
 989                         ironlake_edp_pll_on(encoder);
 990                 else
 991                         ironlake_edp_pll_off(encoder);
 992         }
 993         intel_dp_link_down(intel_dp);
 994 }
 995
 996 static void intel_dp_commit(struct drm_encoder *encoder)
 997 {
 998         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 999         struct drm_device *dev = encoder->dev;
1000
1001         if (is_edp(intel_dp))
1002                 ironlake_edp_panel_vdd_on(intel_dp);
1003
1004         intel_dp_start_link_train(intel_dp);
1005
1006         if (is_edp(intel_dp)) {
1007                 ironlake_edp_panel_on(intel_dp);
1008                 ironlake_edp_panel_vdd_off(intel_dp);
1009         }
1010
1011         intel_dp_complete_link_train(intel_dp);
1012
1013         if (is_edp(intel_dp))
1014                 ironlake_edp_backlight_on(dev);
1015 }
1016
1017 static void
1018 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1019 {
1020         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1021         struct drm_device *dev = encoder->dev;
1022         struct drm_i915_private *dev_priv = dev->dev_private;
1023         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1024
1025         if (mode != DRM_MODE_DPMS_ON) {
1026                 if (is_edp(intel_dp))
1027                         ironlake_edp_backlight_off(dev);
1028                 intel_dp_sink_dpms(intel_dp, mode);
1029                 intel_dp_link_down(intel_dp);
1030                 if (is_edp(intel_dp))
1031                         ironlake_edp_panel_off(dev);
1032                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1033                         ironlake_edp_pll_off(encoder);
1034         } else {
1035                 if (is_edp(intel_dp))
1036                         ironlake_edp_panel_vdd_on(intel_dp);
1037                 intel_dp_sink_dpms(intel_dp, mode);
1038                 if (!(dp_reg & DP_PORT_EN)) {
1039                         intel_dp_start_link_train(intel_dp);
1040                         if (is_edp(intel_dp)) {
1041                                 ironlake_edp_panel_on(intel_dp);
1042                                 ironlake_edp_panel_vdd_off(intel_dp);
1043                         }
1044                         intel_dp_complete_link_train(intel_dp);
1045                 }
1046                 if (is_edp(intel_dp))
1047                         ironlake_edp_backlight_on(dev);
1048         }
1049 }
1050
1051 /*
1052  * Native read with retry for link status and receiver capability reads for
1053  * cases where the sink may still be asleep.
1054  */
1055 static bool
1056 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1057                                uint8_t *recv, int recv_bytes)
1058 {
1059         int ret, i;
1060
1061         /*
1062          * Sinks are *supposed* to come up within 1ms from an off state,
1063          * but we're also supposed to retry 3 times per the spec.
1064          */
1065         for (i = 0; i < 3; i++) {
1066                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1067                                                recv_bytes);
1068                 if (ret == recv_bytes)
1069                         return true;
1070                 msleep(1);
1071         }
1072
1073         return false;
1074 }
1075
1076 /*
1077  * Fetch AUX CH registers 0x202 - 0x207 which contain
1078  * link status information
1079  */
1080 static bool
1081 intel_dp_get_link_status(struct intel_dp *intel_dp)
1082 {
1083         return intel_dp_aux_native_read_retry(intel_dp,
1084                                               DP_LANE0_1_STATUS,
1085                                               intel_dp->link_status,
1086                                               DP_LINK_STATUS_SIZE);
1087 }
1088
1089 static uint8_t
1090 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1091                      int r)
1092 {
1093         return link_status[r - DP_LANE0_1_STATUS];
1094 }
1095
1096 static uint8_t
1097 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1098                                  int lane)
1099 {
1100         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1101         int         s = ((lane & 1) ?
1102                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1103                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1104         uint8_t l = intel_dp_link_status(link_status, i);
1105
1106         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1107 }
1108
1109 static uint8_t
1110 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1111                                       int lane)
1112 {
1113         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1114         int         s = ((lane & 1) ?
1115                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1116                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1117         uint8_t l = intel_dp_link_status(link_status, i);
1118
1119         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1120 }
1121
1122
1123 #if 0
1124 static char     *voltage_names[] = {
1125         "0.4V", "0.6V", "0.8V", "1.2V"
1126 };
1127 static char     *pre_emph_names[] = {
1128         "0dB", "3.5dB", "6dB", "9.5dB"
1129 };
1130 static char     *link_train_names[] = {
1131         "pattern 1", "pattern 2", "idle", "off"
1132 };
1133 #endif
1134
1135 /*
1136  * These are source-specific values; current Intel hardware supports
1137  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1138  */
1139 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1140
1141 static uint8_t
1142 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1143 {
1144         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1145         case DP_TRAIN_VOLTAGE_SWING_400:
1146                 return DP_TRAIN_PRE_EMPHASIS_6;
1147         case DP_TRAIN_VOLTAGE_SWING_600:
1148                 return DP_TRAIN_PRE_EMPHASIS_6;
1149         case DP_TRAIN_VOLTAGE_SWING_800:
1150                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1151         case DP_TRAIN_VOLTAGE_SWING_1200:
1152         default:
1153                 return DP_TRAIN_PRE_EMPHASIS_0;
1154         }
1155 }
1156
1157 static void
1158 intel_get_adjust_train(struct intel_dp *intel_dp)
1159 {
1160         uint8_t v = 0;
1161         uint8_t p = 0;
1162         int lane;
1163
1164         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1165                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1166                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1167
1168                 if (this_v > v)
1169                         v = this_v;
1170                 if (this_p > p)
1171                         p = this_p;
1172         }
1173
1174         if (v >= I830_DP_VOLTAGE_MAX)
1175                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1176
1177         if (p >= intel_dp_pre_emphasis_max(v))
1178                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1179
1180         for (lane = 0; lane < 4; lane++)
1181                 intel_dp->train_set[lane] = v | p;
1182 }
1183
1184 static uint32_t
1185 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1186 {
1187         uint32_t        signal_levels = 0;
1188
1189         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1190         case DP_TRAIN_VOLTAGE_SWING_400:
1191         default:
1192                 signal_levels |= DP_VOLTAGE_0_4;
1193                 break;
1194         case DP_TRAIN_VOLTAGE_SWING_600:
1195                 signal_levels |= DP_VOLTAGE_0_6;
1196                 break;
1197         case DP_TRAIN_VOLTAGE_SWING_800:
1198                 signal_levels |= DP_VOLTAGE_0_8;
1199                 break;
1200         case DP_TRAIN_VOLTAGE_SWING_1200:
1201                 signal_levels |= DP_VOLTAGE_1_2;
1202                 break;
1203         }
1204         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1205         case DP_TRAIN_PRE_EMPHASIS_0:
1206         default:
1207                 signal_levels |= DP_PRE_EMPHASIS_0;
1208                 break;
1209         case DP_TRAIN_PRE_EMPHASIS_3_5:
1210                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1211                 break;
1212         case DP_TRAIN_PRE_EMPHASIS_6:
1213                 signal_levels |= DP_PRE_EMPHASIS_6;
1214                 break;
1215         case DP_TRAIN_PRE_EMPHASIS_9_5:
1216                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1217                 break;
1218         }
1219         return signal_levels;
1220 }
1221
1222 /* Gen6's DP voltage swing and pre-emphasis control */
1223 static uint32_t
1224 intel_gen6_edp_signal_levels(uint8_t train_set)
1225 {
1226         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1227                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1228         switch (signal_levels) {
1229         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1230         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1231                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1232         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1233                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1234         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1235         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1236                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1237         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1238         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1239                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1240         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1241         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1242                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1243         default:
1244                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1245                               "0x%x\n", signal_levels);
1246                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1247         }
1248 }
1249
1250 static uint8_t
1251 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1252                       int lane)
1253 {
1254         int i = DP_LANE0_1_STATUS + (lane >> 1);
1255         int s = (lane & 1) * 4;
1256         uint8_t l = intel_dp_link_status(link_status, i);
1257
1258         return (l >> s) & 0xf;
1259 }
1260
1261 /* Check for clock recovery is done on all channels */
1262 static bool
1263 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1264 {
1265         int lane;
1266         uint8_t lane_status;
1267
1268         for (lane = 0; lane < lane_count; lane++) {
1269                 lane_status = intel_get_lane_status(link_status, lane);
1270                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1271                         return false;
1272         }
1273         return true;
1274 }
1275
1276 /* Check to see if channel eq is done on all channels */
1277 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1278                          DP_LANE_CHANNEL_EQ_DONE|\
1279                          DP_LANE_SYMBOL_LOCKED)
1280 static bool
1281 intel_channel_eq_ok(struct intel_dp *intel_dp)
1282 {
1283         uint8_t lane_align;
1284         uint8_t lane_status;
1285         int lane;
1286
1287         lane_align = intel_dp_link_status(intel_dp->link_status,
1288                                           DP_LANE_ALIGN_STATUS_UPDATED);
1289         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1290                 return false;
1291         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1292                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1293                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1294                         return false;
1295         }
1296         return true;
1297 }
1298
1299 static bool
1300 intel_dp_set_link_train(struct intel_dp *intel_dp,
1301                         uint32_t dp_reg_value,
1302                         uint8_t dp_train_pat)
1303 {
1304         struct drm_device *dev = intel_dp->base.base.dev;
1305         struct drm_i915_private *dev_priv = dev->dev_private;
1306         int ret;
1307
1308         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1309         POSTING_READ(intel_dp->output_reg);
1310
1311         intel_dp_aux_native_write_1(intel_dp,
1312                                     DP_TRAINING_PATTERN_SET,
1313                                     dp_train_pat);
1314
1315         ret = intel_dp_aux_native_write(intel_dp,
1316                                         DP_TRAINING_LANE0_SET,
1317                                         intel_dp->train_set, 4);
1318         if (ret != 4)
1319                 return false;
1320
1321         return true;
1322 }
1323
1324 /* Enable corresponding port and start training pattern 1 */
1325 static void
1326 intel_dp_start_link_train(struct intel_dp *intel_dp)
1327 {
1328         struct drm_device *dev = intel_dp->base.base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1331         int i;
1332         uint8_t voltage;
1333         bool clock_recovery = false;
1334         int tries;
1335         u32 reg;
1336         uint32_t DP = intel_dp->DP;
1337
1338         /*
1339          * On CPT we have to enable the port in training pattern 1, which
1340          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1341          * the port and wait for it to become active.
1342          */
1343         if (!HAS_PCH_CPT(dev)) {
1344                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1345                 POSTING_READ(intel_dp->output_reg);
1346                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1347         }
1348
1349         /* Write the link configuration data */
1350         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1351                                   intel_dp->link_configuration,
1352                                   DP_LINK_CONFIGURATION_SIZE);
1353
1354         DP |= DP_PORT_EN;
1355         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1356                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1357         else
1358                 DP &= ~DP_LINK_TRAIN_MASK;
1359         memset(intel_dp->train_set, 0, 4);
1360         voltage = 0xff;
1361         tries = 0;
1362         clock_recovery = false;
1363         for (;;) {
1364                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1365                 uint32_t    signal_levels;
1366                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1367                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1368                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1369                 } else {
1370                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1371                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1372                 }
1373
1374                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1375                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1376                 else
1377                         reg = DP | DP_LINK_TRAIN_PAT_1;
1378
1379                 if (!intel_dp_set_link_train(intel_dp, reg,
1380                                              DP_TRAINING_PATTERN_1 |
1381                                              DP_LINK_SCRAMBLING_DISABLE))
1382                         break;
1383                 /* Set training pattern 1 */
1384
1385                 udelay(100);
1386                 if (!intel_dp_get_link_status(intel_dp))
1387                         break;
1388
1389                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1390                         clock_recovery = true;
1391                         break;
1392                 }
1393
1394                 /* Check to see if we've tried the max voltage */
1395                 for (i = 0; i < intel_dp->lane_count; i++)
1396                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1397                                 break;
1398                 if (i == intel_dp->lane_count)
1399                         break;
1400
1401                 /* Check to see if we've tried the same voltage 5 times */
1402                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1403                         ++tries;
1404                         if (tries == 5)
1405                                 break;
1406                 } else
1407                         tries = 0;
1408                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1409
1410                 /* Compute new intel_dp->train_set as requested by target */
1411                 intel_get_adjust_train(intel_dp);
1412         }
1413
1414         intel_dp->DP = DP;
1415 }
1416
1417 static void
1418 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1419 {
1420         struct drm_device *dev = intel_dp->base.base.dev;
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         bool channel_eq = false;
1423         int tries, cr_tries;
1424         u32 reg;
1425         uint32_t DP = intel_dp->DP;
1426
1427         /* channel equalization */
1428         tries = 0;
1429         cr_tries = 0;
1430         channel_eq = false;
1431         for (;;) {
1432                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1433                 uint32_t    signal_levels;
1434
1435                 if (cr_tries > 5) {
1436                         DRM_ERROR("failed to train DP, aborting\n");
1437                         intel_dp_link_down(intel_dp);
1438                         break;
1439                 }
1440
1441                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1442                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1443                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1444                 } else {
1445                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1446                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1447                 }
1448
1449                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1450                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1451                 else
1452                         reg = DP | DP_LINK_TRAIN_PAT_2;
1453
1454                 /* channel eq pattern */
1455                 if (!intel_dp_set_link_train(intel_dp, reg,
1456                                              DP_TRAINING_PATTERN_2 |
1457                                              DP_LINK_SCRAMBLING_DISABLE))
1458                         break;
1459
1460                 udelay(400);
1461                 if (!intel_dp_get_link_status(intel_dp))
1462                         break;
1463
1464                 /* Make sure clock is still ok */
1465                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1466                         intel_dp_start_link_train(intel_dp);
1467                         cr_tries++;
1468                         continue;
1469                 }
1470
1471                 if (intel_channel_eq_ok(intel_dp)) {
1472                         channel_eq = true;
1473                         break;
1474                 }
1475
1476                 /* Try 5 times, then try clock recovery if that fails */
1477                 if (tries > 5) {
1478                         intel_dp_link_down(intel_dp);
1479                         intel_dp_start_link_train(intel_dp);
1480                         tries = 0;
1481                         cr_tries++;
1482                         continue;
1483                 }
1484
1485                 /* Compute new intel_dp->train_set as requested by target */
1486                 intel_get_adjust_train(intel_dp);
1487                 ++tries;
1488         }
1489
1490         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1491                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1492         else
1493                 reg = DP | DP_LINK_TRAIN_OFF;
1494
1495         I915_WRITE(intel_dp->output_reg, reg);
1496         POSTING_READ(intel_dp->output_reg);
1497         intel_dp_aux_native_write_1(intel_dp,
1498                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1499 }
1500
1501 static void
1502 intel_dp_link_down(struct intel_dp *intel_dp)
1503 {
1504         struct drm_device *dev = intel_dp->base.base.dev;
1505         struct drm_i915_private *dev_priv = dev->dev_private;
1506         uint32_t DP = intel_dp->DP;
1507
1508         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1509                 return;
1510
1511         DRM_DEBUG_KMS("\n");
1512
1513         if (is_edp(intel_dp)) {
1514                 DP &= ~DP_PLL_ENABLE;
1515                 I915_WRITE(intel_dp->output_reg, DP);
1516                 POSTING_READ(intel_dp->output_reg);
1517                 udelay(100);
1518         }
1519
1520         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1521                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1522                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1523         } else {
1524                 DP &= ~DP_LINK_TRAIN_MASK;
1525                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1526         }
1527         POSTING_READ(intel_dp->output_reg);
1528
1529         msleep(17);
1530
1531         if (is_edp(intel_dp))
1532                 DP |= DP_LINK_TRAIN_OFF;
1533
1534         if (!HAS_PCH_CPT(dev) &&
1535             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1536                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1537
1538                 /* Hardware workaround: leaving our transcoder select
1539                  * set to transcoder B while it's off will prevent the
1540                  * corresponding HDMI output on transcoder A.
1541                  *
1542                  * Combine this with another hardware workaround:
1543                  * transcoder select bit can only be cleared while the
1544                  * port is enabled.
1545                  */
1546                 DP &= ~DP_PIPEB_SELECT;
1547                 I915_WRITE(intel_dp->output_reg, DP);
1548
1549                 /* Changes to enable or select take place the vblank
1550                  * after being written.
1551                  */
1552                 if (crtc == NULL) {
1553                         /* We can arrive here never having been attached
1554                          * to a CRTC, for instance, due to inheriting
1555                          * random state from the BIOS.
1556                          *
1557                          * If the pipe is not running, play safe and
1558                          * wait for the clocks to stabilise before
1559                          * continuing.
1560                          */
1561                         POSTING_READ(intel_dp->output_reg);
1562                         msleep(50);
1563                 } else
1564                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1565         }
1566
1567         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1568         POSTING_READ(intel_dp->output_reg);
1569 }
1570
1571 /*
1572  * According to DP spec
1573  * 5.1.2:
1574  *  1. Read DPCD
1575  *  2. Configure link according to Receiver Capabilities
1576  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1577  *  4. Check link status on receipt of hot-plug interrupt
1578  */
1579
1580 static void
1581 intel_dp_check_link_status(struct intel_dp *intel_dp)
1582 {
1583         int ret;
1584
1585         if (!intel_dp->base.base.crtc)
1586                 return;
1587
1588         if (!intel_dp_get_link_status(intel_dp)) {
1589                 intel_dp_link_down(intel_dp);
1590                 return;
1591         }
1592
1593         /* Try to read receiver status if the link appears to be up */
1594         ret = intel_dp_aux_native_read(intel_dp,
1595                                        0x000, intel_dp->dpcd,
1596                                        sizeof (intel_dp->dpcd));
1597         if (ret != sizeof(intel_dp->dpcd)) {
1598                 intel_dp_link_down(intel_dp);
1599                 return;
1600         }
1601
1602         if (!intel_channel_eq_ok(intel_dp)) {
1603                 intel_dp_start_link_train(intel_dp);
1604                 intel_dp_complete_link_train(intel_dp);
1605         }
1606 }
1607
1608 static enum drm_connector_status
1609 i915_dp_detect_common(struct intel_dp *intel_dp)
1610 {
1611         enum drm_connector_status status = connector_status_disconnected;
1612
1613         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1614                                            sizeof (intel_dp->dpcd)) &&
1615             (intel_dp->dpcd[DP_DPCD_REV] != 0))
1616                 status = connector_status_connected;
1617
1618         return status;
1619 }
1620
1621 static enum drm_connector_status
1622 ironlake_dp_detect(struct intel_dp *intel_dp)
1623 {
1624         enum drm_connector_status status;
1625
1626         /* Can't disconnect eDP, but you can close the lid... */
1627         if (is_edp(intel_dp)) {
1628                 status = intel_panel_detect(intel_dp->base.base.dev);
1629                 if (status == connector_status_unknown)
1630                         status = connector_status_connected;
1631                 return status;
1632         }
1633
1634         return i915_dp_detect_common(intel_dp);
1635 }
1636
1637 static enum drm_connector_status
1638 g4x_dp_detect(struct intel_dp *intel_dp)
1639 {
1640         struct drm_device *dev = intel_dp->base.base.dev;
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642         uint32_t temp, bit;
1643
1644         switch (intel_dp->output_reg) {
1645         case DP_B:
1646                 bit = DPB_HOTPLUG_INT_STATUS;
1647                 break;
1648         case DP_C:
1649                 bit = DPC_HOTPLUG_INT_STATUS;
1650                 break;
1651         case DP_D:
1652                 bit = DPD_HOTPLUG_INT_STATUS;
1653                 break;
1654         default:
1655                 return connector_status_unknown;
1656         }
1657
1658         temp = I915_READ(PORT_HOTPLUG_STAT);
1659
1660         if ((temp & bit) == 0)
1661                 return connector_status_disconnected;
1662
1663         return i915_dp_detect_common(intel_dp);
1664 }
1665
1666 /**
1667  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1668  *
1669  * \return true if DP port is connected.
1670  * \return false if DP port is disconnected.
1671  */
1672 static enum drm_connector_status
1673 intel_dp_detect(struct drm_connector *connector, bool force)
1674 {
1675         struct intel_dp *intel_dp = intel_attached_dp(connector);
1676         struct drm_device *dev = intel_dp->base.base.dev;
1677         enum drm_connector_status status;
1678         struct edid *edid = NULL;
1679
1680         intel_dp->has_audio = false;
1681         memset(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd));
1682
1683         if (HAS_PCH_SPLIT(dev))
1684                 status = ironlake_dp_detect(intel_dp);
1685         else
1686                 status = g4x_dp_detect(intel_dp);
1687
1688         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1689                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1690                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1691                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1692
1693         if (status != connector_status_connected)
1694                 return status;
1695
1696         if (intel_dp->force_audio) {
1697                 intel_dp->has_audio = intel_dp->force_audio > 0;
1698         } else {
1699                 edid = drm_get_edid(connector, &intel_dp->adapter);
1700                 if (edid) {
1701                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1702                         connector->display_info.raw_edid = NULL;
1703                         kfree(edid);
1704                 }
1705         }
1706
1707         return connector_status_connected;
1708 }
1709
1710 static int intel_dp_get_modes(struct drm_connector *connector)
1711 {
1712         struct intel_dp *intel_dp = intel_attached_dp(connector);
1713         struct drm_device *dev = intel_dp->base.base.dev;
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715         int ret;
1716
1717         /* We should parse the EDID data and find out if it has an audio sink
1718          */
1719
1720         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1721         if (ret) {
1722                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1723                         struct drm_display_mode *newmode;
1724                         list_for_each_entry(newmode, &connector->probed_modes,
1725                                             head) {
1726                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1727                                         dev_priv->panel_fixed_mode =
1728                                                 drm_mode_duplicate(dev, newmode);
1729                                         break;
1730                                 }
1731                         }
1732                 }
1733
1734                 return ret;
1735         }
1736
1737         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1738         if (is_edp(intel_dp)) {
1739                 if (dev_priv->panel_fixed_mode != NULL) {
1740                         struct drm_display_mode *mode;
1741                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1742                         drm_mode_probed_add(connector, mode);
1743                         return 1;
1744                 }
1745         }
1746         return 0;
1747 }
1748
1749 static bool
1750 intel_dp_detect_audio(struct drm_connector *connector)
1751 {
1752         struct intel_dp *intel_dp = intel_attached_dp(connector);
1753         struct edid *edid;
1754         bool has_audio = false;
1755
1756         edid = drm_get_edid(connector, &intel_dp->adapter);
1757         if (edid) {
1758                 has_audio = drm_detect_monitor_audio(edid);
1759
1760                 connector->display_info.raw_edid = NULL;
1761                 kfree(edid);
1762         }
1763
1764         return has_audio;
1765 }
1766
1767 static int
1768 intel_dp_set_property(struct drm_connector *connector,
1769                       struct drm_property *property,
1770                       uint64_t val)
1771 {
1772         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1773         struct intel_dp *intel_dp = intel_attached_dp(connector);
1774         int ret;
1775
1776         ret = drm_connector_property_set_value(connector, property, val);
1777         if (ret)
1778                 return ret;
1779
1780         if (property == dev_priv->force_audio_property) {
1781                 int i = val;
1782                 bool has_audio;
1783
1784                 if (i == intel_dp->force_audio)
1785                         return 0;
1786
1787                 intel_dp->force_audio = i;
1788
1789                 if (i == 0)
1790                         has_audio = intel_dp_detect_audio(connector);
1791                 else
1792                         has_audio = i > 0;
1793
1794                 if (has_audio == intel_dp->has_audio)
1795                         return 0;
1796
1797                 intel_dp->has_audio = has_audio;
1798                 goto done;
1799         }
1800
1801         if (property == dev_priv->broadcast_rgb_property) {
1802                 if (val == !!intel_dp->color_range)
1803                         return 0;
1804
1805                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1806                 goto done;
1807         }
1808
1809         return -EINVAL;
1810
1811 done:
1812         if (intel_dp->base.base.crtc) {
1813                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1814                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1815                                          crtc->x, crtc->y,
1816                                          crtc->fb);
1817         }
1818
1819         return 0;
1820 }
1821
1822 static void
1823 intel_dp_destroy (struct drm_connector *connector)
1824 {
1825         drm_sysfs_connector_remove(connector);
1826         drm_connector_cleanup(connector);
1827         kfree(connector);
1828 }
1829
1830 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1831 {
1832         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1833
1834         i2c_del_adapter(&intel_dp->adapter);
1835         drm_encoder_cleanup(encoder);
1836         kfree(intel_dp);
1837 }
1838
1839 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1840         .dpms = intel_dp_dpms,
1841         .mode_fixup = intel_dp_mode_fixup,
1842         .prepare = intel_dp_prepare,
1843         .mode_set = intel_dp_mode_set,
1844         .commit = intel_dp_commit,
1845 };
1846
1847 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1848         .dpms = drm_helper_connector_dpms,
1849         .detect = intel_dp_detect,
1850         .fill_modes = drm_helper_probe_single_connector_modes,
1851         .set_property = intel_dp_set_property,
1852         .destroy = intel_dp_destroy,
1853 };
1854
1855 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1856         .get_modes = intel_dp_get_modes,
1857         .mode_valid = intel_dp_mode_valid,
1858         .best_encoder = intel_best_encoder,
1859 };
1860
1861 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1862         .destroy = intel_dp_encoder_destroy,
1863 };
1864
1865 static void
1866 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1867 {
1868         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1869
1870         intel_dp_check_link_status(intel_dp);
1871 }
1872
1873 /* Return which DP Port should be selected for Transcoder DP control */
1874 int
1875 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1876 {
1877         struct drm_device *dev = crtc->dev;
1878         struct drm_mode_config *mode_config = &dev->mode_config;
1879         struct drm_encoder *encoder;
1880
1881         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1882                 struct intel_dp *intel_dp;
1883
1884                 if (encoder->crtc != crtc)
1885                         continue;
1886
1887                 intel_dp = enc_to_intel_dp(encoder);
1888                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1889                         return intel_dp->output_reg;
1890         }
1891
1892         return -1;
1893 }
1894
1895 /* check the VBT to see whether the eDP is on DP-D port */
1896 bool intel_dpd_is_edp(struct drm_device *dev)
1897 {
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         struct child_device_config *p_child;
1900         int i;
1901
1902         if (!dev_priv->child_dev_num)
1903                 return false;
1904
1905         for (i = 0; i < dev_priv->child_dev_num; i++) {
1906                 p_child = dev_priv->child_dev + i;
1907
1908                 if (p_child->dvo_port == PORT_IDPD &&
1909                     p_child->device_type == DEVICE_TYPE_eDP)
1910                         return true;
1911         }
1912         return false;
1913 }
1914
1915 static void
1916 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1917 {
1918         intel_attach_force_audio_property(connector);
1919         intel_attach_broadcast_rgb_property(connector);
1920 }
1921
1922 void
1923 intel_dp_init(struct drm_device *dev, int output_reg)
1924 {
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct drm_connector *connector;
1927         struct intel_dp *intel_dp;
1928         struct intel_encoder *intel_encoder;
1929         struct intel_connector *intel_connector;
1930         const char *name = NULL;
1931         int type;
1932
1933         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1934         if (!intel_dp)
1935                 return;
1936
1937         intel_dp->output_reg = output_reg;
1938
1939         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1940         if (!intel_connector) {
1941                 kfree(intel_dp);
1942                 return;
1943         }
1944         intel_encoder = &intel_dp->base;
1945
1946         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1947                 if (intel_dpd_is_edp(dev))
1948                         intel_dp->is_pch_edp = true;
1949
1950         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1951                 type = DRM_MODE_CONNECTOR_eDP;
1952                 intel_encoder->type = INTEL_OUTPUT_EDP;
1953         } else {
1954                 type = DRM_MODE_CONNECTOR_DisplayPort;
1955                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1956         }
1957
1958         connector = &intel_connector->base;
1959         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1960         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1961
1962         connector->polled = DRM_CONNECTOR_POLL_HPD;
1963
1964         if (output_reg == DP_B || output_reg == PCH_DP_B)
1965                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1966         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1967                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1968         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1969                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1970
1971         if (is_edp(intel_dp))
1972                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1973
1974         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1975         connector->interlace_allowed = true;
1976         connector->doublescan_allowed = 0;
1977
1978         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1979                          DRM_MODE_ENCODER_TMDS);
1980         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1981
1982         intel_connector_attach_encoder(intel_connector, intel_encoder);
1983         drm_sysfs_connector_add(connector);
1984
1985         /* Set up the DDC bus. */
1986         switch (output_reg) {
1987                 case DP_A:
1988                         name = "DPDDC-A";
1989                         break;
1990                 case DP_B:
1991                 case PCH_DP_B:
1992                         dev_priv->hotplug_supported_mask |=
1993                                 HDMIB_HOTPLUG_INT_STATUS;
1994                         name = "DPDDC-B";
1995                         break;
1996                 case DP_C:
1997                 case PCH_DP_C:
1998                         dev_priv->hotplug_supported_mask |=
1999                                 HDMIC_HOTPLUG_INT_STATUS;
2000                         name = "DPDDC-C";
2001                         break;
2002                 case DP_D:
2003                 case PCH_DP_D:
2004                         dev_priv->hotplug_supported_mask |=
2005                                 HDMID_HOTPLUG_INT_STATUS;
2006                         name = "DPDDC-D";
2007                         break;
2008         }
2009
2010         intel_dp_i2c_init(intel_dp, intel_connector, name);
2011
2012         /* Cache some DPCD data in the eDP case */
2013         if (is_edp(intel_dp)) {
2014                 int ret;
2015                 u32 pp_on, pp_div;
2016
2017                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2018                 pp_div = I915_READ(PCH_PP_DIVISOR);
2019
2020                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2021                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2022                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2023                 dev_priv->panel_t12 = pp_div & 0xf;
2024                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2025
2026                 ironlake_edp_panel_vdd_on(intel_dp);
2027                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
2028                                                intel_dp->dpcd,
2029                                                sizeof(intel_dp->dpcd));
2030                 ironlake_edp_panel_vdd_off(intel_dp);
2031                 if (ret == sizeof(intel_dp->dpcd)) {
2032                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2033                                 dev_priv->no_aux_handshake =
2034                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2035                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2036                 } else {
2037                         /* if this fails, presume the device is a ghost */
2038                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2039                         intel_dp_encoder_destroy(&intel_dp->base.base);
2040                         intel_dp_destroy(&intel_connector->base);
2041                         return;
2042                 }
2043         }
2044
2045         intel_encoder->hot_plug = intel_dp_hot_plug;
2046
2047         if (is_edp(intel_dp)) {
2048                 /* initialize panel mode from VBT if available for eDP */
2049                 if (dev_priv->lfp_lvds_vbt_mode) {
2050                         dev_priv->panel_fixed_mode =
2051                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2052                         if (dev_priv->panel_fixed_mode) {
2053                                 dev_priv->panel_fixed_mode->type |=
2054                                         DRM_MODE_TYPE_PREFERRED;
2055                         }
2056                 }
2057         }
2058
2059         intel_dp_add_properties(intel_dp, connector);
2060
2061         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2062          * 0xd.  Failure to do so will result in spurious interrupts being
2063          * generated on the port when a cable is not attached.
2064          */
2065         if (IS_G4X(dev) && !IS_GM45(dev)) {
2066                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2067                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2068         }
2069 }