2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
46 struct intel_encoder base;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66 * @intel_dp: DP struct
68 * If a CPU or PCH DP output is attached to an eDP panel, this function
69 * will return true, and false otherwise.
71 static bool is_edp(struct intel_dp *intel_dp)
73 return intel_dp->base.type == INTEL_OUTPUT_EDP;
77 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78 * @intel_dp: DP struct
80 * Returns true if the given DP struct corresponds to a PCH DP port attached
81 * to an eDP panel, false otherwise. Helpful for determining whether we
82 * may need FDI resources for a given DP output or not.
84 static bool is_pch_edp(struct intel_dp *intel_dp)
86 return intel_dp->is_pch_edp;
89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
91 return container_of(encoder, struct intel_dp, base.base);
94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
96 return container_of(intel_attached_encoder(connector),
97 struct intel_dp, base);
101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102 * @encoder: DRM encoder
104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
105 * by intel_display.c.
107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
109 struct intel_dp *intel_dp;
114 intel_dp = enc_to_intel_dp(encoder);
116 return is_pch_edp(intel_dp);
119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_link_down(struct intel_dp *intel_dp);
124 intel_edp_link_config (struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw)
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
129 *lane_num = intel_dp->lane_count;
130 if (intel_dp->link_bw == DP_LINK_BW_1_62)
132 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
139 int max_lane_count = 4;
141 if (intel_dp->dpcd[0] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[2] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
150 return max_lane_count;
154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
156 int max_link_bw = intel_dp->dpcd[1];
158 switch (max_link_bw) {
159 case DP_LINK_BW_1_62:
163 max_link_bw = DP_LINK_BW_1_62;
170 intel_dp_link_clock(uint8_t link_bw)
172 if (link_bw == DP_LINK_BW_2_7)
178 /* I think this is a fiction */
180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
182 struct drm_i915_private *dev_priv = dev->dev_private;
184 if (is_edp(intel_dp))
185 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
187 return pixel_clock * 3;
191 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
193 return (max_link_clock * max_lanes * 8) / 10;
197 intel_dp_mode_valid(struct drm_connector *connector,
198 struct drm_display_mode *mode)
200 struct intel_dp *intel_dp = intel_attached_dp(connector);
201 struct drm_device *dev = connector->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
204 int max_lanes = intel_dp_max_lane_count(intel_dp);
206 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
207 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
210 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
214 /* only refuse the mode on non eDP since we have seen some weird eDP panels
215 which are outside spec tolerances but somehow work by magic */
216 if (!is_edp(intel_dp) &&
217 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
218 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
219 return MODE_CLOCK_HIGH;
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
228 pack_aux(uint8_t *src, int src_bytes)
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device *dev)
254 struct drm_i915_private *dev_priv = dev->dev_private;
257 clkcfg = I915_READ(CLKCFG);
258 switch (clkcfg & CLKCFG_FSB_MASK) {
267 case CLKCFG_FSB_1067:
269 case CLKCFG_FSB_1333:
271 /* these two are just a guess; one of them might be right */
272 case CLKCFG_FSB_1600:
273 case CLKCFG_FSB_1600_ALT:
281 intel_dp_aux_ch(struct intel_dp *intel_dp,
282 uint8_t *send, int send_bytes,
283 uint8_t *recv, int recv_size)
285 uint32_t output_reg = intel_dp->output_reg;
286 struct drm_device *dev = intel_dp->base.base.dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 uint32_t ch_ctl = output_reg + 0x10;
289 uint32_t ch_data = ch_ctl + 4;
293 uint32_t aux_clock_divider;
296 /* The clock divider is based off the hrawclk,
297 * and would like to run at 2MHz. So, take the
298 * hrawclk value and divide by 2 and use that
300 * Note that PCH attached eDP panels should use a 125MHz input
303 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
305 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
307 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
308 } else if (HAS_PCH_SPLIT(dev))
309 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
311 aux_clock_divider = intel_hrawclk(dev) / 2;
318 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
319 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
324 /* Must try at least 3 times according to DP spec */
325 for (try = 0; try < 5; try++) {
326 /* Load the send data into the aux channel data registers */
327 for (i = 0; i < send_bytes; i += 4)
328 I915_WRITE(ch_data + i,
329 pack_aux(send + i, send_bytes - i));
331 /* Send the command and wait for it to complete */
333 DP_AUX_CH_CTL_SEND_BUSY |
334 DP_AUX_CH_CTL_TIME_OUT_400us |
335 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
336 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
337 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
339 DP_AUX_CH_CTL_TIME_OUT_ERROR |
340 DP_AUX_CH_CTL_RECEIVE_ERROR);
342 status = I915_READ(ch_ctl);
343 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
348 /* Clear done status and any errors */
352 DP_AUX_CH_CTL_TIME_OUT_ERROR |
353 DP_AUX_CH_CTL_RECEIVE_ERROR);
354 if (status & DP_AUX_CH_CTL_DONE)
358 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
359 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
363 /* Check for timeout or receive error.
364 * Timeouts occur when the sink is not connected
366 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
367 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
371 /* Timeouts occur when the device isn't connected, so they're
372 * "normal" -- don't fill the kernel log with these */
373 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
374 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
378 /* Unload any bytes sent back from the other side */
379 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
380 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
381 if (recv_bytes > recv_size)
382 recv_bytes = recv_size;
384 for (i = 0; i < recv_bytes; i += 4)
385 unpack_aux(I915_READ(ch_data + i),
386 recv + i, recv_bytes - i);
391 /* Write data to the aux channel in native mode */
393 intel_dp_aux_native_write(struct intel_dp *intel_dp,
394 uint16_t address, uint8_t *send, int send_bytes)
403 msg[0] = AUX_NATIVE_WRITE << 4;
404 msg[1] = address >> 8;
405 msg[2] = address & 0xff;
406 msg[3] = send_bytes - 1;
407 memcpy(&msg[4], send, send_bytes);
408 msg_bytes = send_bytes + 4;
410 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
413 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
415 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
423 /* Write a single byte to the aux channel in native mode */
425 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
426 uint16_t address, uint8_t byte)
428 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
431 /* read bytes from a native aux channel */
433 intel_dp_aux_native_read(struct intel_dp *intel_dp,
434 uint16_t address, uint8_t *recv, int recv_bytes)
443 msg[0] = AUX_NATIVE_READ << 4;
444 msg[1] = address >> 8;
445 msg[2] = address & 0xff;
446 msg[3] = recv_bytes - 1;
449 reply_bytes = recv_bytes + 1;
452 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
459 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
460 memcpy(recv, reply + 1, ret - 1);
463 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
471 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
472 uint8_t write_byte, uint8_t *read_byte)
474 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
475 struct intel_dp *intel_dp = container_of(adapter,
478 uint16_t address = algo_data->address;
486 /* Set up the command byte */
487 if (mode & MODE_I2C_READ)
488 msg[0] = AUX_I2C_READ << 4;
490 msg[0] = AUX_I2C_WRITE << 4;
492 if (!(mode & MODE_I2C_STOP))
493 msg[0] |= AUX_I2C_MOT << 4;
495 msg[1] = address >> 8;
516 for (retry = 0; retry < 5; retry++) {
517 ret = intel_dp_aux_ch(intel_dp,
521 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
525 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
526 case AUX_NATIVE_REPLY_ACK:
527 /* I2C-over-AUX Reply field is only valid
528 * when paired with AUX ACK.
531 case AUX_NATIVE_REPLY_NACK:
532 DRM_DEBUG_KMS("aux_ch native nack\n");
534 case AUX_NATIVE_REPLY_DEFER:
538 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
543 switch (reply[0] & AUX_I2C_REPLY_MASK) {
544 case AUX_I2C_REPLY_ACK:
545 if (mode == MODE_I2C_READ) {
546 *read_byte = reply[1];
548 return reply_bytes - 1;
549 case AUX_I2C_REPLY_NACK:
550 DRM_DEBUG_KMS("aux_i2c nack\n");
552 case AUX_I2C_REPLY_DEFER:
553 DRM_DEBUG_KMS("aux_i2c defer\n");
557 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
562 DRM_ERROR("too many retries, giving up\n");
567 intel_dp_i2c_init(struct intel_dp *intel_dp,
568 struct intel_connector *intel_connector, const char *name)
570 DRM_DEBUG_KMS("i2c_init %s\n", name);
571 intel_dp->algo.running = false;
572 intel_dp->algo.address = 0;
573 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
575 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
576 intel_dp->adapter.owner = THIS_MODULE;
577 intel_dp->adapter.class = I2C_CLASS_DDC;
578 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
579 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
580 intel_dp->adapter.algo_data = &intel_dp->algo;
581 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
583 return i2c_dp_aux_add_bus(&intel_dp->adapter);
587 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
588 struct drm_display_mode *adjusted_mode)
590 struct drm_device *dev = encoder->dev;
591 struct drm_i915_private *dev_priv = dev->dev_private;
592 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
593 int lane_count, clock;
594 int max_lane_count = intel_dp_max_lane_count(intel_dp);
595 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
596 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
598 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
599 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
600 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
601 mode, adjusted_mode);
603 * the mode->clock is used to calculate the Data&Link M/N
604 * of the pipe. For the eDP the fixed clock should be used.
606 mode->clock = dev_priv->panel_fixed_mode->clock;
609 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
610 for (clock = 0; clock <= max_clock; clock++) {
611 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
613 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
615 intel_dp->link_bw = bws[clock];
616 intel_dp->lane_count = lane_count;
617 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
618 DRM_DEBUG_KMS("Display port link bw %02x lane "
619 "count %d clock %d\n",
620 intel_dp->link_bw, intel_dp->lane_count,
621 adjusted_mode->clock);
627 if (is_edp(intel_dp)) {
628 /* okay we failed just pick the highest */
629 intel_dp->lane_count = max_lane_count;
630 intel_dp->link_bw = bws[max_clock];
631 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
632 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
633 "count %d clock %d\n",
634 intel_dp->link_bw, intel_dp->lane_count,
635 adjusted_mode->clock);
643 struct intel_dp_m_n {
652 intel_reduce_ratio(uint32_t *num, uint32_t *den)
654 while (*num > 0xffffff || *den > 0xffffff) {
661 intel_dp_compute_m_n(int bpp,
665 struct intel_dp_m_n *m_n)
668 m_n->gmch_m = (pixel_clock * bpp) >> 3;
669 m_n->gmch_n = link_clock * nlanes;
670 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
671 m_n->link_m = pixel_clock;
672 m_n->link_n = link_clock;
673 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
677 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
678 struct drm_display_mode *adjusted_mode)
680 struct drm_device *dev = crtc->dev;
681 struct drm_mode_config *mode_config = &dev->mode_config;
682 struct drm_encoder *encoder;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
685 int lane_count = 4, bpp = 24;
686 struct intel_dp_m_n m_n;
687 int pipe = intel_crtc->pipe;
690 * Find the lane count in the intel_encoder private
692 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
693 struct intel_dp *intel_dp;
695 if (encoder->crtc != crtc)
698 intel_dp = enc_to_intel_dp(encoder);
699 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
700 lane_count = intel_dp->lane_count;
702 } else if (is_edp(intel_dp)) {
703 lane_count = dev_priv->edp.lanes;
704 bpp = dev_priv->edp.bpp;
710 * Compute the GMCH and Link ratios. The '3' here is
711 * the number of bytes_per_pixel post-LUT, which we always
712 * set up for 8-bits of R/G/B, or 3 bytes total.
714 intel_dp_compute_m_n(bpp, lane_count,
715 mode->clock, adjusted_mode->clock, &m_n);
717 if (HAS_PCH_SPLIT(dev)) {
718 I915_WRITE(TRANSDATA_M1(pipe),
719 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
721 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
722 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
723 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
725 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
726 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
728 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
729 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
730 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
735 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
736 struct drm_display_mode *adjusted_mode)
738 struct drm_device *dev = encoder->dev;
739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
740 struct drm_crtc *crtc = intel_dp->base.base.crtc;
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
744 intel_dp->DP |= intel_dp->color_range;
746 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
747 intel_dp->DP |= DP_SYNC_HS_HIGH;
748 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
749 intel_dp->DP |= DP_SYNC_VS_HIGH;
751 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
752 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
754 intel_dp->DP |= DP_LINK_TRAIN_OFF;
756 switch (intel_dp->lane_count) {
758 intel_dp->DP |= DP_PORT_WIDTH_1;
761 intel_dp->DP |= DP_PORT_WIDTH_2;
764 intel_dp->DP |= DP_PORT_WIDTH_4;
767 if (intel_dp->has_audio)
768 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
770 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
771 intel_dp->link_configuration[0] = intel_dp->link_bw;
772 intel_dp->link_configuration[1] = intel_dp->lane_count;
775 * Check for DPCD version > 1.1 and enhanced framing support
777 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
779 intel_dp->DP |= DP_ENHANCED_FRAMING;
782 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
783 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
784 intel_dp->DP |= DP_PIPEB_SELECT;
786 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
787 /* don't miss out required setting for eDP */
788 intel_dp->DP |= DP_PLL_ENABLE;
789 if (adjusted_mode->clock < 200000)
790 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
792 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
796 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
798 struct drm_device *dev = intel_dp->base.base.dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
803 * If the panel wasn't on, make sure there's not a currently
804 * active PP sequence before enabling AUX VDD.
806 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
807 msleep(dev_priv->panel_t3);
809 pp = I915_READ(PCH_PP_CONTROL);
811 I915_WRITE(PCH_PP_CONTROL, pp);
812 POSTING_READ(PCH_PP_CONTROL);
815 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
817 struct drm_device *dev = intel_dp->base.base.dev;
818 struct drm_i915_private *dev_priv = dev->dev_private;
821 pp = I915_READ(PCH_PP_CONTROL);
822 pp &= ~EDP_FORCE_VDD;
823 I915_WRITE(PCH_PP_CONTROL, pp);
824 POSTING_READ(PCH_PP_CONTROL);
826 /* Make sure sequencer is idle before allowing subsequent activity */
827 msleep(dev_priv->panel_t12);
830 /* Returns true if the panel was already on when called */
831 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
833 struct drm_device *dev = intel_dp->base.base.dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
837 if (I915_READ(PCH_PP_STATUS) & PP_ON)
840 pp = I915_READ(PCH_PP_CONTROL);
842 /* ILK workaround: disable reset around power sequence */
843 pp &= ~PANEL_POWER_RESET;
844 I915_WRITE(PCH_PP_CONTROL, pp);
845 POSTING_READ(PCH_PP_CONTROL);
847 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
848 I915_WRITE(PCH_PP_CONTROL, pp);
849 POSTING_READ(PCH_PP_CONTROL);
851 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
853 DRM_ERROR("panel on wait timed out: 0x%08x\n",
854 I915_READ(PCH_PP_STATUS));
856 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
857 I915_WRITE(PCH_PP_CONTROL, pp);
858 POSTING_READ(PCH_PP_CONTROL);
863 static void ironlake_edp_panel_off (struct drm_device *dev)
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
867 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
869 pp = I915_READ(PCH_PP_CONTROL);
871 /* ILK workaround: disable reset around power sequence */
872 pp &= ~PANEL_POWER_RESET;
873 I915_WRITE(PCH_PP_CONTROL, pp);
874 POSTING_READ(PCH_PP_CONTROL);
876 pp &= ~POWER_TARGET_ON;
877 I915_WRITE(PCH_PP_CONTROL, pp);
878 POSTING_READ(PCH_PP_CONTROL);
880 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
881 DRM_ERROR("panel off wait timed out: 0x%08x\n",
882 I915_READ(PCH_PP_STATUS));
884 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
885 I915_WRITE(PCH_PP_CONTROL, pp);
886 POSTING_READ(PCH_PP_CONTROL);
889 static void ironlake_edp_backlight_on (struct drm_device *dev)
891 struct drm_i915_private *dev_priv = dev->dev_private;
896 * If we enable the backlight right away following a panel power
897 * on, we may see slight flicker as the panel syncs with the eDP
898 * link. So delay a bit to make sure the image is solid before
899 * allowing it to appear.
902 pp = I915_READ(PCH_PP_CONTROL);
903 pp |= EDP_BLC_ENABLE;
904 I915_WRITE(PCH_PP_CONTROL, pp);
907 static void ironlake_edp_backlight_off (struct drm_device *dev)
909 struct drm_i915_private *dev_priv = dev->dev_private;
913 pp = I915_READ(PCH_PP_CONTROL);
914 pp &= ~EDP_BLC_ENABLE;
915 I915_WRITE(PCH_PP_CONTROL, pp);
918 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
920 struct drm_device *dev = encoder->dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
925 dpa_ctl = I915_READ(DP_A);
926 dpa_ctl |= DP_PLL_ENABLE;
927 I915_WRITE(DP_A, dpa_ctl);
932 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
934 struct drm_device *dev = encoder->dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
938 dpa_ctl = I915_READ(DP_A);
939 dpa_ctl &= ~DP_PLL_ENABLE;
940 I915_WRITE(DP_A, dpa_ctl);
945 static void intel_dp_prepare(struct drm_encoder *encoder)
947 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
948 struct drm_device *dev = encoder->dev;
950 if (is_edp(intel_dp)) {
951 ironlake_edp_backlight_off(dev);
952 ironlake_edp_panel_off(dev);
953 if (!is_pch_edp(intel_dp))
954 ironlake_edp_pll_on(encoder);
956 ironlake_edp_pll_off(encoder);
958 intel_dp_link_down(intel_dp);
961 static void intel_dp_commit(struct drm_encoder *encoder)
963 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
964 struct drm_device *dev = encoder->dev;
966 if (is_edp(intel_dp))
967 ironlake_edp_panel_vdd_on(intel_dp);
969 intel_dp_start_link_train(intel_dp);
971 if (is_edp(intel_dp)) {
972 ironlake_edp_panel_on(intel_dp);
973 ironlake_edp_panel_vdd_off(intel_dp);
976 intel_dp_complete_link_train(intel_dp);
978 if (is_edp(intel_dp))
979 ironlake_edp_backlight_on(dev);
983 intel_dp_dpms(struct drm_encoder *encoder, int mode)
985 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
986 struct drm_device *dev = encoder->dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
990 if (mode != DRM_MODE_DPMS_ON) {
991 if (is_edp(intel_dp))
992 ironlake_edp_backlight_off(dev);
993 intel_dp_link_down(intel_dp);
994 if (is_edp(intel_dp))
995 ironlake_edp_panel_off(dev);
996 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
997 ironlake_edp_pll_off(encoder);
999 if (is_edp(intel_dp))
1000 ironlake_edp_panel_vdd_on(intel_dp);
1001 if (!(dp_reg & DP_PORT_EN)) {
1002 intel_dp_start_link_train(intel_dp);
1003 if (is_edp(intel_dp)) {
1004 ironlake_edp_panel_on(intel_dp);
1005 ironlake_edp_panel_vdd_off(intel_dp);
1007 intel_dp_complete_link_train(intel_dp);
1009 if (is_edp(intel_dp))
1010 ironlake_edp_backlight_on(dev);
1012 intel_dp->dpms_mode = mode;
1016 * Fetch AUX CH registers 0x202 - 0x207 which contain
1017 * link status information
1020 intel_dp_get_link_status(struct intel_dp *intel_dp)
1024 ret = intel_dp_aux_native_read(intel_dp,
1026 intel_dp->link_status, DP_LINK_STATUS_SIZE);
1027 if (ret != DP_LINK_STATUS_SIZE)
1033 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1036 return link_status[r - DP_LANE0_1_STATUS];
1040 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1043 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1044 int s = ((lane & 1) ?
1045 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1046 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1047 uint8_t l = intel_dp_link_status(link_status, i);
1049 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1053 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1056 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1057 int s = ((lane & 1) ?
1058 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1059 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1060 uint8_t l = intel_dp_link_status(link_status, i);
1062 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1067 static char *voltage_names[] = {
1068 "0.4V", "0.6V", "0.8V", "1.2V"
1070 static char *pre_emph_names[] = {
1071 "0dB", "3.5dB", "6dB", "9.5dB"
1073 static char *link_train_names[] = {
1074 "pattern 1", "pattern 2", "idle", "off"
1079 * These are source-specific values; current Intel hardware supports
1080 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1082 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1085 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1087 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1088 case DP_TRAIN_VOLTAGE_SWING_400:
1089 return DP_TRAIN_PRE_EMPHASIS_6;
1090 case DP_TRAIN_VOLTAGE_SWING_600:
1091 return DP_TRAIN_PRE_EMPHASIS_6;
1092 case DP_TRAIN_VOLTAGE_SWING_800:
1093 return DP_TRAIN_PRE_EMPHASIS_3_5;
1094 case DP_TRAIN_VOLTAGE_SWING_1200:
1096 return DP_TRAIN_PRE_EMPHASIS_0;
1101 intel_get_adjust_train(struct intel_dp *intel_dp)
1107 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1108 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1109 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1117 if (v >= I830_DP_VOLTAGE_MAX)
1118 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1120 if (p >= intel_dp_pre_emphasis_max(v))
1121 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1123 for (lane = 0; lane < 4; lane++)
1124 intel_dp->train_set[lane] = v | p;
1128 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1130 uint32_t signal_levels = 0;
1132 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1133 case DP_TRAIN_VOLTAGE_SWING_400:
1135 signal_levels |= DP_VOLTAGE_0_4;
1137 case DP_TRAIN_VOLTAGE_SWING_600:
1138 signal_levels |= DP_VOLTAGE_0_6;
1140 case DP_TRAIN_VOLTAGE_SWING_800:
1141 signal_levels |= DP_VOLTAGE_0_8;
1143 case DP_TRAIN_VOLTAGE_SWING_1200:
1144 signal_levels |= DP_VOLTAGE_1_2;
1147 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1148 case DP_TRAIN_PRE_EMPHASIS_0:
1150 signal_levels |= DP_PRE_EMPHASIS_0;
1152 case DP_TRAIN_PRE_EMPHASIS_3_5:
1153 signal_levels |= DP_PRE_EMPHASIS_3_5;
1155 case DP_TRAIN_PRE_EMPHASIS_6:
1156 signal_levels |= DP_PRE_EMPHASIS_6;
1158 case DP_TRAIN_PRE_EMPHASIS_9_5:
1159 signal_levels |= DP_PRE_EMPHASIS_9_5;
1162 return signal_levels;
1165 /* Gen6's DP voltage swing and pre-emphasis control */
1167 intel_gen6_edp_signal_levels(uint8_t train_set)
1169 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1170 DP_TRAIN_PRE_EMPHASIS_MASK);
1171 switch (signal_levels) {
1172 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1173 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1174 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1175 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1176 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1177 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1178 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1179 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1180 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1181 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1182 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1183 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1184 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1185 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1187 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1188 "0x%x\n", signal_levels);
1189 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1194 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1197 int i = DP_LANE0_1_STATUS + (lane >> 1);
1198 int s = (lane & 1) * 4;
1199 uint8_t l = intel_dp_link_status(link_status, i);
1201 return (l >> s) & 0xf;
1204 /* Check for clock recovery is done on all channels */
1206 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1209 uint8_t lane_status;
1211 for (lane = 0; lane < lane_count; lane++) {
1212 lane_status = intel_get_lane_status(link_status, lane);
1213 if ((lane_status & DP_LANE_CR_DONE) == 0)
1219 /* Check to see if channel eq is done on all channels */
1220 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1221 DP_LANE_CHANNEL_EQ_DONE|\
1222 DP_LANE_SYMBOL_LOCKED)
1224 intel_channel_eq_ok(struct intel_dp *intel_dp)
1227 uint8_t lane_status;
1230 lane_align = intel_dp_link_status(intel_dp->link_status,
1231 DP_LANE_ALIGN_STATUS_UPDATED);
1232 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1234 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1235 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1236 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1243 intel_dp_set_link_train(struct intel_dp *intel_dp,
1244 uint32_t dp_reg_value,
1245 uint8_t dp_train_pat)
1247 struct drm_device *dev = intel_dp->base.base.dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1251 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1252 POSTING_READ(intel_dp->output_reg);
1254 intel_dp_aux_native_write_1(intel_dp,
1255 DP_TRAINING_PATTERN_SET,
1258 ret = intel_dp_aux_native_write(intel_dp,
1259 DP_TRAINING_LANE0_SET,
1260 intel_dp->train_set, 4);
1267 /* Enable corresponding port and start training pattern 1 */
1269 intel_dp_start_link_train(struct intel_dp *intel_dp)
1271 struct drm_device *dev = intel_dp->base.base.dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1276 bool clock_recovery = false;
1279 uint32_t DP = intel_dp->DP;
1281 /* Enable output, wait for it to become active */
1282 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1283 POSTING_READ(intel_dp->output_reg);
1284 intel_wait_for_vblank(dev, intel_crtc->pipe);
1286 /* Write the link configuration data */
1287 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1288 intel_dp->link_configuration,
1289 DP_LINK_CONFIGURATION_SIZE);
1292 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1293 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1295 DP &= ~DP_LINK_TRAIN_MASK;
1296 memset(intel_dp->train_set, 0, 4);
1299 clock_recovery = false;
1301 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1302 uint32_t signal_levels;
1303 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1304 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1305 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1307 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1308 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1311 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1312 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1314 reg = DP | DP_LINK_TRAIN_PAT_1;
1316 if (!intel_dp_set_link_train(intel_dp, reg,
1317 DP_TRAINING_PATTERN_1))
1319 /* Set training pattern 1 */
1322 if (!intel_dp_get_link_status(intel_dp))
1325 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1326 clock_recovery = true;
1330 /* Check to see if we've tried the max voltage */
1331 for (i = 0; i < intel_dp->lane_count; i++)
1332 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1334 if (i == intel_dp->lane_count)
1337 /* Check to see if we've tried the same voltage 5 times */
1338 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1344 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1346 /* Compute new intel_dp->train_set as requested by target */
1347 intel_get_adjust_train(intel_dp);
1354 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1356 struct drm_device *dev = intel_dp->base.base.dev;
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358 bool channel_eq = false;
1359 int tries, cr_tries;
1361 uint32_t DP = intel_dp->DP;
1363 /* channel equalization */
1368 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1369 uint32_t signal_levels;
1372 DRM_ERROR("failed to train DP, aborting\n");
1373 intel_dp_link_down(intel_dp);
1377 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1378 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1379 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1381 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1382 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1385 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1386 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1388 reg = DP | DP_LINK_TRAIN_PAT_2;
1390 /* channel eq pattern */
1391 if (!intel_dp_set_link_train(intel_dp, reg,
1392 DP_TRAINING_PATTERN_2))
1396 if (!intel_dp_get_link_status(intel_dp))
1399 /* Make sure clock is still ok */
1400 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1401 intel_dp_start_link_train(intel_dp);
1406 if (intel_channel_eq_ok(intel_dp)) {
1411 /* Try 5 times, then try clock recovery if that fails */
1413 intel_dp_link_down(intel_dp);
1414 intel_dp_start_link_train(intel_dp);
1420 /* Compute new intel_dp->train_set as requested by target */
1421 intel_get_adjust_train(intel_dp);
1425 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1426 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1428 reg = DP | DP_LINK_TRAIN_OFF;
1430 I915_WRITE(intel_dp->output_reg, reg);
1431 POSTING_READ(intel_dp->output_reg);
1432 intel_dp_aux_native_write_1(intel_dp,
1433 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1437 intel_dp_link_down(struct intel_dp *intel_dp)
1439 struct drm_device *dev = intel_dp->base.base.dev;
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 uint32_t DP = intel_dp->DP;
1443 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1446 DRM_DEBUG_KMS("\n");
1448 if (is_edp(intel_dp)) {
1449 DP &= ~DP_PLL_ENABLE;
1450 I915_WRITE(intel_dp->output_reg, DP);
1451 POSTING_READ(intel_dp->output_reg);
1455 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1456 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1457 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1459 DP &= ~DP_LINK_TRAIN_MASK;
1460 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1462 POSTING_READ(intel_dp->output_reg);
1466 if (is_edp(intel_dp))
1467 DP |= DP_LINK_TRAIN_OFF;
1469 if (!HAS_PCH_CPT(dev) &&
1470 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1471 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1473 /* Hardware workaround: leaving our transcoder select
1474 * set to transcoder B while it's off will prevent the
1475 * corresponding HDMI output on transcoder A.
1477 * Combine this with another hardware workaround:
1478 * transcoder select bit can only be cleared while the
1481 DP &= ~DP_PIPEB_SELECT;
1482 I915_WRITE(intel_dp->output_reg, DP);
1484 /* Changes to enable or select take place the vblank
1485 * after being written.
1488 /* We can arrive here never having been attached
1489 * to a CRTC, for instance, due to inheriting
1490 * random state from the BIOS.
1492 * If the pipe is not running, play safe and
1493 * wait for the clocks to stabilise before
1496 POSTING_READ(intel_dp->output_reg);
1499 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1502 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1503 POSTING_READ(intel_dp->output_reg);
1507 * According to DP spec
1510 * 2. Configure link according to Receiver Capabilities
1511 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1512 * 4. Check link status on receipt of hot-plug interrupt
1516 intel_dp_check_link_status(struct intel_dp *intel_dp)
1518 if (!intel_dp->base.base.crtc)
1521 if (!intel_dp_get_link_status(intel_dp)) {
1522 intel_dp_link_down(intel_dp);
1526 if (!intel_channel_eq_ok(intel_dp)) {
1527 intel_dp_start_link_train(intel_dp);
1528 intel_dp_complete_link_train(intel_dp);
1532 static enum drm_connector_status
1533 ironlake_dp_detect(struct intel_dp *intel_dp)
1535 enum drm_connector_status status;
1537 /* Can't disconnect eDP, but you can close the lid... */
1538 if (is_edp(intel_dp)) {
1539 status = intel_panel_detect(intel_dp->base.base.dev);
1540 if (status == connector_status_unknown)
1541 status = connector_status_connected;
1545 status = connector_status_disconnected;
1546 if (intel_dp_aux_native_read(intel_dp,
1547 0x000, intel_dp->dpcd,
1548 sizeof (intel_dp->dpcd))
1549 == sizeof(intel_dp->dpcd)) {
1550 if (intel_dp->dpcd[0] != 0)
1551 status = connector_status_connected;
1553 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1554 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1558 static enum drm_connector_status
1559 g4x_dp_detect(struct intel_dp *intel_dp)
1561 struct drm_device *dev = intel_dp->base.base.dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 enum drm_connector_status status;
1566 switch (intel_dp->output_reg) {
1568 bit = DPB_HOTPLUG_INT_STATUS;
1571 bit = DPC_HOTPLUG_INT_STATUS;
1574 bit = DPD_HOTPLUG_INT_STATUS;
1577 return connector_status_unknown;
1580 temp = I915_READ(PORT_HOTPLUG_STAT);
1582 if ((temp & bit) == 0)
1583 return connector_status_disconnected;
1585 status = connector_status_disconnected;
1586 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1587 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1589 if (intel_dp->dpcd[0] != 0)
1590 status = connector_status_connected;
1597 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1599 * \return true if DP port is connected.
1600 * \return false if DP port is disconnected.
1602 static enum drm_connector_status
1603 intel_dp_detect(struct drm_connector *connector, bool force)
1605 struct intel_dp *intel_dp = intel_attached_dp(connector);
1606 struct drm_device *dev = intel_dp->base.base.dev;
1607 enum drm_connector_status status;
1608 struct edid *edid = NULL;
1610 intel_dp->has_audio = false;
1612 if (HAS_PCH_SPLIT(dev))
1613 status = ironlake_dp_detect(intel_dp);
1615 status = g4x_dp_detect(intel_dp);
1616 if (status != connector_status_connected)
1619 if (intel_dp->force_audio) {
1620 intel_dp->has_audio = intel_dp->force_audio > 0;
1622 edid = drm_get_edid(connector, &intel_dp->adapter);
1624 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1625 connector->display_info.raw_edid = NULL;
1630 return connector_status_connected;
1633 static int intel_dp_get_modes(struct drm_connector *connector)
1635 struct intel_dp *intel_dp = intel_attached_dp(connector);
1636 struct drm_device *dev = intel_dp->base.base.dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1640 /* We should parse the EDID data and find out if it has an audio sink
1643 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1645 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1646 struct drm_display_mode *newmode;
1647 list_for_each_entry(newmode, &connector->probed_modes,
1649 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1650 dev_priv->panel_fixed_mode =
1651 drm_mode_duplicate(dev, newmode);
1660 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1661 if (is_edp(intel_dp)) {
1662 if (dev_priv->panel_fixed_mode != NULL) {
1663 struct drm_display_mode *mode;
1664 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1665 drm_mode_probed_add(connector, mode);
1673 intel_dp_detect_audio(struct drm_connector *connector)
1675 struct intel_dp *intel_dp = intel_attached_dp(connector);
1677 bool has_audio = false;
1679 edid = drm_get_edid(connector, &intel_dp->adapter);
1681 has_audio = drm_detect_monitor_audio(edid);
1683 connector->display_info.raw_edid = NULL;
1691 intel_dp_set_property(struct drm_connector *connector,
1692 struct drm_property *property,
1695 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1696 struct intel_dp *intel_dp = intel_attached_dp(connector);
1699 ret = drm_connector_property_set_value(connector, property, val);
1703 if (property == dev_priv->force_audio_property) {
1707 if (i == intel_dp->force_audio)
1710 intel_dp->force_audio = i;
1713 has_audio = intel_dp_detect_audio(connector);
1717 if (has_audio == intel_dp->has_audio)
1720 intel_dp->has_audio = has_audio;
1724 if (property == dev_priv->broadcast_rgb_property) {
1725 if (val == !!intel_dp->color_range)
1728 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1735 if (intel_dp->base.base.crtc) {
1736 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1737 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1746 intel_dp_destroy (struct drm_connector *connector)
1748 drm_sysfs_connector_remove(connector);
1749 drm_connector_cleanup(connector);
1753 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1755 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1757 i2c_del_adapter(&intel_dp->adapter);
1758 drm_encoder_cleanup(encoder);
1762 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1763 .dpms = intel_dp_dpms,
1764 .mode_fixup = intel_dp_mode_fixup,
1765 .prepare = intel_dp_prepare,
1766 .mode_set = intel_dp_mode_set,
1767 .commit = intel_dp_commit,
1770 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1771 .dpms = drm_helper_connector_dpms,
1772 .detect = intel_dp_detect,
1773 .fill_modes = drm_helper_probe_single_connector_modes,
1774 .set_property = intel_dp_set_property,
1775 .destroy = intel_dp_destroy,
1778 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1779 .get_modes = intel_dp_get_modes,
1780 .mode_valid = intel_dp_mode_valid,
1781 .best_encoder = intel_best_encoder,
1784 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1785 .destroy = intel_dp_encoder_destroy,
1789 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1791 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1793 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1794 intel_dp_check_link_status(intel_dp);
1797 /* Return which DP Port should be selected for Transcoder DP control */
1799 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1801 struct drm_device *dev = crtc->dev;
1802 struct drm_mode_config *mode_config = &dev->mode_config;
1803 struct drm_encoder *encoder;
1805 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1806 struct intel_dp *intel_dp;
1808 if (encoder->crtc != crtc)
1811 intel_dp = enc_to_intel_dp(encoder);
1812 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1813 return intel_dp->output_reg;
1819 /* check the VBT to see whether the eDP is on DP-D port */
1820 bool intel_dpd_is_edp(struct drm_device *dev)
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 struct child_device_config *p_child;
1826 if (!dev_priv->child_dev_num)
1829 for (i = 0; i < dev_priv->child_dev_num; i++) {
1830 p_child = dev_priv->child_dev + i;
1832 if (p_child->dvo_port == PORT_IDPD &&
1833 p_child->device_type == DEVICE_TYPE_eDP)
1840 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1842 intel_attach_force_audio_property(connector);
1843 intel_attach_broadcast_rgb_property(connector);
1847 intel_dp_init(struct drm_device *dev, int output_reg)
1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 struct drm_connector *connector;
1851 struct intel_dp *intel_dp;
1852 struct intel_encoder *intel_encoder;
1853 struct intel_connector *intel_connector;
1854 const char *name = NULL;
1857 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1861 intel_dp->output_reg = output_reg;
1862 intel_dp->dpms_mode = -1;
1864 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1865 if (!intel_connector) {
1869 intel_encoder = &intel_dp->base;
1871 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1872 if (intel_dpd_is_edp(dev))
1873 intel_dp->is_pch_edp = true;
1875 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1876 type = DRM_MODE_CONNECTOR_eDP;
1877 intel_encoder->type = INTEL_OUTPUT_EDP;
1879 type = DRM_MODE_CONNECTOR_DisplayPort;
1880 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1883 connector = &intel_connector->base;
1884 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1885 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1887 connector->polled = DRM_CONNECTOR_POLL_HPD;
1889 if (output_reg == DP_B || output_reg == PCH_DP_B)
1890 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1891 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1892 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1893 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1894 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1896 if (is_edp(intel_dp))
1897 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1899 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1900 connector->interlace_allowed = true;
1901 connector->doublescan_allowed = 0;
1903 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1904 DRM_MODE_ENCODER_TMDS);
1905 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1907 intel_connector_attach_encoder(intel_connector, intel_encoder);
1908 drm_sysfs_connector_add(connector);
1910 /* Set up the DDC bus. */
1911 switch (output_reg) {
1917 dev_priv->hotplug_supported_mask |=
1918 HDMIB_HOTPLUG_INT_STATUS;
1923 dev_priv->hotplug_supported_mask |=
1924 HDMIC_HOTPLUG_INT_STATUS;
1929 dev_priv->hotplug_supported_mask |=
1930 HDMID_HOTPLUG_INT_STATUS;
1935 intel_dp_i2c_init(intel_dp, intel_connector, name);
1937 /* Cache some DPCD data in the eDP case */
1938 if (is_edp(intel_dp)) {
1942 pp_on = I915_READ(PCH_PP_ON_DELAYS);
1943 pp_div = I915_READ(PCH_PP_DIVISOR);
1945 /* Get T3 & T12 values (note: VESA not bspec terminology) */
1946 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
1947 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
1948 dev_priv->panel_t12 = pp_div & 0xf;
1949 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
1951 ironlake_edp_panel_vdd_on(intel_dp);
1952 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1954 sizeof(intel_dp->dpcd));
1955 ironlake_edp_panel_vdd_off(intel_dp);
1956 if (ret == sizeof(intel_dp->dpcd)) {
1957 if (intel_dp->dpcd[0] >= 0x11)
1958 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1959 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1961 /* if this fails, presume the device is a ghost */
1962 DRM_INFO("failed to retrieve link info, disabling eDP\n");
1963 intel_dp_encoder_destroy(&intel_dp->base.base);
1964 intel_dp_destroy(&intel_connector->base);
1969 intel_encoder->hot_plug = intel_dp_hot_plug;
1971 if (is_edp(intel_dp)) {
1972 /* initialize panel mode from VBT if available for eDP */
1973 if (dev_priv->lfp_lvds_vbt_mode) {
1974 dev_priv->panel_fixed_mode =
1975 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1976 if (dev_priv->panel_fixed_mode) {
1977 dev_priv->panel_fixed_mode->type |=
1978 DRM_MODE_TYPE_PREFERRED;
1983 intel_dp_add_properties(intel_dp, connector);
1985 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1986 * 0xd. Failure to do so will result in spurious interrupts being
1987 * generated on the port when a cable is not attached.
1989 if (IS_G4X(dev) && !IS_GM45(dev)) {
1990 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1991 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);