2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include "intel_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
118 .find_pll = intel_find_best_PLL,
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
132 .find_pll = intel_find_best_PLL,
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
146 .find_pll = intel_find_best_PLL,
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
160 .find_pll = intel_find_best_PLL,
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
177 .find_pll = intel_g4x_find_best_PLL,
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
191 .find_pll = intel_g4x_find_best_PLL,
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
206 .find_pll = intel_g4x_find_best_PLL,
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
221 .find_pll = intel_g4x_find_best_PLL,
224 static const intel_limit_t intel_limits_g4x_display_port = {
225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
235 .find_pll = intel_find_pll_g4x_dp,
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
251 .find_pll = intel_find_best_PLL,
254 static const intel_limit_t intel_limits_pineview_lvds = {
255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
265 .find_pll = intel_find_best_PLL,
268 /* Ironlake / Sandybridge
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
273 static const intel_limit_t intel_limits_ironlake_dac = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_g4x_find_best_PLL,
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_g4x_find_best_PLL,
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
312 .find_pll = intel_g4x_find_best_PLL,
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 .find_pll = intel_g4x_find_best_PLL,
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 .find_pll = intel_g4x_find_best_PLL,
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
355 .find_pll = intel_find_pll_ironlake_dp,
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 const intel_limit_t *limit;
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_dual_lvds_100m;
372 limit = &intel_limits_ironlake_dual_lvds;
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_single_lvds_100m;
377 limit = &intel_limits_ironlake_single_lvds;
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381 limit = &intel_limits_ironlake_display_port;
383 limit = &intel_limits_ironlake_dac;
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 /* LVDS with dual channel */
398 limit = &intel_limits_g4x_dual_channel_lvds;
400 /* LVDS with dual channel */
401 limit = &intel_limits_g4x_single_channel_lvds;
402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404 limit = &intel_limits_g4x_hdmi;
405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406 limit = &intel_limits_g4x_sdvo;
407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408 limit = &intel_limits_g4x_display_port;
409 } else /* The option is for other outputs */
410 limit = &intel_limits_i9xx_sdvo;
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
420 if (HAS_PCH_SPLIT(dev))
421 limit = intel_ironlake_limit(crtc, refclk);
422 else if (IS_G4X(dev)) {
423 limit = intel_g4x_limit(crtc);
424 } else if (IS_PINEVIEW(dev)) {
425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426 limit = &intel_limits_pineview_lvds;
428 limit = &intel_limits_pineview_sdvo;
429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
433 limit = &intel_limits_i9xx_sdvo;
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i8xx_lvds;
438 limit = &intel_limits_i8xx_dvo;
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
465 * Returns whether any output on the specified pipe is of the specified type
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
480 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526 (I915_READ(LVDS)) != 0) {
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 clock.p2 = limit->p2.p2_fast;
537 clock.p2 = limit->p2.p2_slow;
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
542 clock.p2 = limit->p2.p2_fast;
545 memset (best_clock, 0, sizeof (*best_clock));
547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
560 intel_clock(dev, refclk, &clock);
561 if (!intel_PLL_is_valid(dev, limit,
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
575 return (err != target);
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
594 if (HAS_PCH_SPLIT(dev))
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600 clock.p2 = limit->p2.p2_fast;
602 clock.p2 = limit->p2.p2_slow;
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
607 clock.p2 = limit->p2.p2_fast;
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
612 /* based on hardware requirement, prefer smaller n to precision */
613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614 /* based on hardware requirement, prefere larger m1,m2 */
615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
623 intel_clock(dev, refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
628 this_err = abs(clock.dot - target);
629 if (this_err < err_most) {
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
646 struct drm_device *dev = crtc->dev;
649 if (target < 200000) {
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
673 if (target < 200000) {
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
695 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @pipe: pipe to wait for
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int pipestat_reg = PIPESTAT(pipe);
707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723 /* Wait for vblank interrupt bit to set */
724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
727 DRM_DEBUG_KMS("vblank wait timed out\n");
731 * intel_wait_for_pipe_off - wait for pipe to turn off
733 * @pipe: pipe to wait for
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
740 * wait for the pipe register state bit to turn off
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 struct drm_i915_private *dev_priv = dev->dev_private;
751 if (INTEL_INFO(dev)->gen >= 4) {
752 int reg = PIPECONF(pipe);
754 /* Wait for the Pipe State to go off */
755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
760 int reg = PIPEDSL(pipe);
761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763 /* Wait for the display line to settle */
765 last_line = I915_READ(reg) & DSL_LINEMASK;
767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
774 static const char *state_string(bool enabled)
776 return enabled ? "on" : "off";
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
878 int pp_reg, lvds_reg;
880 enum pipe panel_pipe = PIPE_A;
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
916 pipe_name(pipe), state_string(state), state_string(cur_state));
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
983 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, u32 port_sel, u32 val)
986 if ((val & DP_PORT_EN) == 0)
989 if (HAS_PCH_CPT(dev_priv->dev)) {
990 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
995 if ((val & DP_PIPE_MASK) != (pipe << 30))
1001 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, u32 val)
1004 if ((val & PORT_ENABLE) == 0)
1007 if (HAS_PCH_CPT(dev_priv->dev)) {
1008 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1011 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1017 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, u32 val)
1020 if ((val & LVDS_PORT_EN) == 0)
1023 if (HAS_PCH_CPT(dev_priv->dev)) {
1024 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1027 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1033 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, u32 val)
1036 if ((val & ADPA_DAC_ENABLE) == 0)
1038 if (HAS_PCH_CPT(dev_priv->dev)) {
1039 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1042 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1048 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, int reg, u32 port_sel)
1051 u32 val = I915_READ(reg);
1052 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1053 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1054 reg, pipe_name(pipe));
1057 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, int reg)
1060 u32 val = I915_READ(reg);
1061 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1062 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1063 reg, pipe_name(pipe));
1066 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1072 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1077 val = I915_READ(reg);
1078 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1079 "PCH VGA enabled on transcoder %c, should be disabled\n",
1083 val = I915_READ(reg);
1084 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1085 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1088 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1094 * intel_enable_pll - enable a PLL
1095 * @dev_priv: i915 private structure
1096 * @pipe: pipe PLL to enable
1098 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1099 * make sure the PLL reg is writable first though, since the panel write
1100 * protect mechanism may be enabled.
1102 * Note! This is for pre-ILK only.
1104 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1109 /* No really, not for ILK+ */
1110 BUG_ON(dev_priv->info->gen >= 5);
1112 /* PLL is protected by panel, make sure we can write it */
1113 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1114 assert_panel_unlocked(dev_priv, pipe);
1117 val = I915_READ(reg);
1118 val |= DPLL_VCO_ENABLE;
1120 /* We do this three times for luck */
1121 I915_WRITE(reg, val);
1123 udelay(150); /* wait for warmup */
1124 I915_WRITE(reg, val);
1126 udelay(150); /* wait for warmup */
1127 I915_WRITE(reg, val);
1129 udelay(150); /* wait for warmup */
1133 * intel_disable_pll - disable a PLL
1134 * @dev_priv: i915 private structure
1135 * @pipe: pipe PLL to disable
1137 * Disable the PLL for @pipe, making sure the pipe is off first.
1139 * Note! This is for pre-ILK only.
1141 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 /* Don't disable pipe A or pipe A PLLs if needed */
1147 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1150 /* Make sure the pipe isn't still relying on us */
1151 assert_pipe_disabled(dev_priv, pipe);
1154 val = I915_READ(reg);
1155 val &= ~DPLL_VCO_ENABLE;
1156 I915_WRITE(reg, val);
1161 * intel_enable_pch_pll - enable PCH PLL
1162 * @dev_priv: i915 private structure
1163 * @pipe: pipe PLL to enable
1165 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1166 * drives the transcoder clock.
1168 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1174 /* PCH only available on ILK+ */
1175 BUG_ON(dev_priv->info->gen < 5);
1177 /* PCH refclock must be enabled first */
1178 assert_pch_refclk_enabled(dev_priv);
1180 reg = PCH_DPLL(pipe);
1181 val = I915_READ(reg);
1182 val |= DPLL_VCO_ENABLE;
1183 I915_WRITE(reg, val);
1188 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1194 /* PCH only available on ILK+ */
1195 BUG_ON(dev_priv->info->gen < 5);
1197 /* Make sure transcoder isn't still depending on us */
1198 assert_transcoder_disabled(dev_priv, pipe);
1200 reg = PCH_DPLL(pipe);
1201 val = I915_READ(reg);
1202 val &= ~DPLL_VCO_ENABLE;
1203 I915_WRITE(reg, val);
1208 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1217 /* Make sure PCH DPLL is enabled */
1218 assert_pch_pll_enabled(dev_priv, pipe);
1220 /* FDI must be feeding us bits for PCH ports */
1221 assert_fdi_tx_enabled(dev_priv, pipe);
1222 assert_fdi_rx_enabled(dev_priv, pipe);
1224 reg = TRANSCONF(pipe);
1225 val = I915_READ(reg);
1227 if (HAS_PCH_IBX(dev_priv->dev)) {
1229 * make the BPC in transcoder be consistent with
1230 * that in pipeconf reg.
1232 val &= ~PIPE_BPC_MASK;
1233 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1235 I915_WRITE(reg, val | TRANS_ENABLE);
1236 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1237 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1240 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1246 /* FDI relies on the transcoder */
1247 assert_fdi_tx_disabled(dev_priv, pipe);
1248 assert_fdi_rx_disabled(dev_priv, pipe);
1250 /* Ports must be off as well */
1251 assert_pch_ports_disabled(dev_priv, pipe);
1253 reg = TRANSCONF(pipe);
1254 val = I915_READ(reg);
1255 val &= ~TRANS_ENABLE;
1256 I915_WRITE(reg, val);
1257 /* wait for PCH transcoder off, transcoder state */
1258 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1259 DRM_ERROR("failed to disable transcoder\n");
1263 * intel_enable_pipe - enable a pipe, asserting requirements
1264 * @dev_priv: i915 private structure
1265 * @pipe: pipe to enable
1266 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1268 * Enable @pipe, making sure that various hardware specific requirements
1269 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1271 * @pipe should be %PIPE_A or %PIPE_B.
1273 * Will wait until the pipe is actually running (i.e. first vblank) before
1276 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1283 * A pipe without a PLL won't actually be able to drive bits from
1284 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1287 if (!HAS_PCH_SPLIT(dev_priv->dev))
1288 assert_pll_enabled(dev_priv, pipe);
1291 /* if driving the PCH, we need FDI enabled */
1292 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1293 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1295 /* FIXME: assert CPU port conditions for SNB+ */
1298 reg = PIPECONF(pipe);
1299 val = I915_READ(reg);
1300 if (val & PIPECONF_ENABLE)
1303 I915_WRITE(reg, val | PIPECONF_ENABLE);
1304 intel_wait_for_vblank(dev_priv->dev, pipe);
1308 * intel_disable_pipe - disable a pipe, asserting requirements
1309 * @dev_priv: i915 private structure
1310 * @pipe: pipe to disable
1312 * Disable @pipe, making sure that various hardware specific requirements
1313 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1315 * @pipe should be %PIPE_A or %PIPE_B.
1317 * Will wait until the pipe has shut down before returning.
1319 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1326 * Make sure planes won't keep trying to pump pixels to us,
1327 * or we might hang the display.
1329 assert_planes_disabled(dev_priv, pipe);
1331 /* Don't disable pipe A or pipe A PLLs if needed */
1332 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1335 reg = PIPECONF(pipe);
1336 val = I915_READ(reg);
1337 if ((val & PIPECONF_ENABLE) == 0)
1340 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1341 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1345 * Plane regs are double buffered, going from enabled->disabled needs a
1346 * trigger in order to latch. The display address reg provides this.
1348 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1351 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1352 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1356 * intel_enable_plane - enable a display plane on a given pipe
1357 * @dev_priv: i915 private structure
1358 * @plane: plane to enable
1359 * @pipe: pipe being fed
1361 * Enable @plane on @pipe, making sure that @pipe is running first.
1363 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1364 enum plane plane, enum pipe pipe)
1369 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1370 assert_pipe_enabled(dev_priv, pipe);
1372 reg = DSPCNTR(plane);
1373 val = I915_READ(reg);
1374 if (val & DISPLAY_PLANE_ENABLE)
1377 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1378 intel_flush_display_plane(dev_priv, plane);
1379 intel_wait_for_vblank(dev_priv->dev, pipe);
1383 * intel_disable_plane - disable a display plane
1384 * @dev_priv: i915 private structure
1385 * @plane: plane to disable
1386 * @pipe: pipe consuming the data
1388 * Disable @plane; should be an independent operation.
1390 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1391 enum plane plane, enum pipe pipe)
1396 reg = DSPCNTR(plane);
1397 val = I915_READ(reg);
1398 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1401 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1402 intel_flush_display_plane(dev_priv, plane);
1403 intel_wait_for_vblank(dev_priv->dev, pipe);
1406 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, int reg, u32 port_sel)
1409 u32 val = I915_READ(reg);
1410 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1411 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1412 I915_WRITE(reg, val & ~DP_PORT_EN);
1416 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, int reg)
1419 u32 val = I915_READ(reg);
1420 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1421 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1423 I915_WRITE(reg, val & ~PORT_ENABLE);
1427 /* Disable any ports connected to this transcoder */
1428 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1433 val = I915_READ(PCH_PP_CONTROL);
1434 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1436 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1437 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1438 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441 val = I915_READ(reg);
1442 if (adpa_pipe_enabled(dev_priv, val, pipe))
1443 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1446 val = I915_READ(reg);
1447 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1448 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1449 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1454 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1455 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1456 disable_pch_hdmi(dev_priv, pipe, HDMID);
1459 static void i8xx_disable_fbc(struct drm_device *dev)
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1464 /* Disable compression */
1465 fbc_ctl = I915_READ(FBC_CONTROL);
1466 if ((fbc_ctl & FBC_CTL_EN) == 0)
1469 fbc_ctl &= ~FBC_CTL_EN;
1470 I915_WRITE(FBC_CONTROL, fbc_ctl);
1472 /* Wait for compressing bit to clear */
1473 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1474 DRM_DEBUG_KMS("FBC idle timed out\n");
1478 DRM_DEBUG_KMS("disabled FBC\n");
1481 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1483 struct drm_device *dev = crtc->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 struct drm_framebuffer *fb = crtc->fb;
1486 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1487 struct drm_i915_gem_object *obj = intel_fb->obj;
1488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1491 u32 fbc_ctl, fbc_ctl2;
1493 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1494 if (fb->pitch < cfb_pitch)
1495 cfb_pitch = fb->pitch;
1497 /* FBC_CTL wants 64B units */
1498 cfb_pitch = (cfb_pitch / 64) - 1;
1499 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1501 /* Clear old tags */
1502 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1503 I915_WRITE(FBC_TAG + (i * 4), 0);
1506 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1508 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1509 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1512 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1514 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1515 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1516 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1517 fbc_ctl |= obj->fence_reg;
1518 I915_WRITE(FBC_CONTROL, fbc_ctl);
1520 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1521 cfb_pitch, crtc->y, intel_crtc->plane);
1524 static bool i8xx_fbc_enabled(struct drm_device *dev)
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1528 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1531 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1533 struct drm_device *dev = crtc->dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_framebuffer *fb = crtc->fb;
1536 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1537 struct drm_i915_gem_object *obj = intel_fb->obj;
1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1539 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1540 unsigned long stall_watermark = 200;
1543 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1544 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1545 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1547 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1548 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1549 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1550 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1553 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1555 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1558 static void g4x_disable_fbc(struct drm_device *dev)
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1563 /* Disable compression */
1564 dpfc_ctl = I915_READ(DPFC_CONTROL);
1565 if (dpfc_ctl & DPFC_CTL_EN) {
1566 dpfc_ctl &= ~DPFC_CTL_EN;
1567 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1569 DRM_DEBUG_KMS("disabled FBC\n");
1573 static bool g4x_fbc_enabled(struct drm_device *dev)
1575 struct drm_i915_private *dev_priv = dev->dev_private;
1577 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1580 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1585 /* Make sure blitter notifies FBC of writes */
1586 gen6_gt_force_wake_get(dev_priv);
1587 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1588 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1589 GEN6_BLITTER_LOCK_SHIFT;
1590 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1591 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1592 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1593 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1594 GEN6_BLITTER_LOCK_SHIFT);
1595 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1596 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1597 gen6_gt_force_wake_put(dev_priv);
1600 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 struct drm_device *dev = crtc->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 struct drm_framebuffer *fb = crtc->fb;
1605 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1606 struct drm_i915_gem_object *obj = intel_fb->obj;
1607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1608 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1609 unsigned long stall_watermark = 200;
1612 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1613 dpfc_ctl &= DPFC_RESERVED;
1614 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1615 /* Set persistent mode for front-buffer rendering, ala X. */
1616 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1617 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1618 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1620 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1624 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1626 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1629 I915_WRITE(SNB_DPFC_CTL_SA,
1630 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1631 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1632 sandybridge_blit_fbc_update(dev);
1635 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1638 static void ironlake_disable_fbc(struct drm_device *dev)
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1643 /* Disable compression */
1644 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1645 if (dpfc_ctl & DPFC_CTL_EN) {
1646 dpfc_ctl &= ~DPFC_CTL_EN;
1647 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1649 DRM_DEBUG_KMS("disabled FBC\n");
1653 static bool ironlake_fbc_enabled(struct drm_device *dev)
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1657 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1660 bool intel_fbc_enabled(struct drm_device *dev)
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1664 if (!dev_priv->display.fbc_enabled)
1667 return dev_priv->display.fbc_enabled(dev);
1670 static void intel_fbc_work_fn(struct work_struct *__work)
1672 struct intel_fbc_work *work =
1673 container_of(to_delayed_work(__work),
1674 struct intel_fbc_work, work);
1675 struct drm_device *dev = work->crtc->dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1678 mutex_lock(&dev->struct_mutex);
1679 if (work == dev_priv->fbc_work) {
1680 /* Double check that we haven't switched fb without cancelling
1683 if (work->crtc->fb == work->fb) {
1684 dev_priv->display.enable_fbc(work->crtc,
1687 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1688 dev_priv->cfb_fb = work->crtc->fb->base.id;
1689 dev_priv->cfb_y = work->crtc->y;
1692 dev_priv->fbc_work = NULL;
1694 mutex_unlock(&dev->struct_mutex);
1699 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1701 if (dev_priv->fbc_work == NULL)
1704 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1706 /* Synchronisation is provided by struct_mutex and checking of
1707 * dev_priv->fbc_work, so we can perform the cancellation
1708 * entirely asynchronously.
1710 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1711 /* tasklet was killed before being run, clean up */
1712 kfree(dev_priv->fbc_work);
1714 /* Mark the work as no longer wanted so that if it does
1715 * wake-up (because the work was already running and waiting
1716 * for our mutex), it will discover that is no longer
1719 dev_priv->fbc_work = NULL;
1722 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1724 struct intel_fbc_work *work;
1725 struct drm_device *dev = crtc->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1728 if (!dev_priv->display.enable_fbc)
1731 intel_cancel_fbc_work(dev_priv);
1733 work = kzalloc(sizeof *work, GFP_KERNEL);
1735 dev_priv->display.enable_fbc(crtc, interval);
1740 work->fb = crtc->fb;
1741 work->interval = interval;
1742 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1744 dev_priv->fbc_work = work;
1746 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1748 /* Delay the actual enabling to let pageflipping cease and the
1749 * display to settle before starting the compression. Note that
1750 * this delay also serves a second purpose: it allows for a
1751 * vblank to pass after disabling the FBC before we attempt
1752 * to modify the control registers.
1754 * A more complicated solution would involve tracking vblanks
1755 * following the termination of the page-flipping sequence
1756 * and indeed performing the enable as a co-routine and not
1757 * waiting synchronously upon the vblank.
1759 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1762 void intel_disable_fbc(struct drm_device *dev)
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1766 intel_cancel_fbc_work(dev_priv);
1768 if (!dev_priv->display.disable_fbc)
1771 dev_priv->display.disable_fbc(dev);
1772 dev_priv->cfb_plane = -1;
1776 * intel_update_fbc - enable/disable FBC as needed
1777 * @dev: the drm_device
1779 * Set up the framebuffer compression hardware at mode set time. We
1780 * enable it if possible:
1781 * - plane A only (on pre-965)
1782 * - no pixel mulitply/line duplication
1783 * - no alpha buffer discard
1785 * - framebuffer <= 2048 in width, 1536 in height
1787 * We can't assume that any compression will take place (worst case),
1788 * so the compressed buffer has to be the same size as the uncompressed
1789 * one. It also must reside (along with the line length buffer) in
1792 * We need to enable/disable FBC on a global basis.
1794 static void intel_update_fbc(struct drm_device *dev)
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 struct drm_crtc *crtc = NULL, *tmp_crtc;
1798 struct intel_crtc *intel_crtc;
1799 struct drm_framebuffer *fb;
1800 struct intel_framebuffer *intel_fb;
1801 struct drm_i915_gem_object *obj;
1803 DRM_DEBUG_KMS("\n");
1805 if (!i915_powersave)
1808 if (!I915_HAS_FBC(dev))
1812 * If FBC is already on, we just have to verify that we can
1813 * keep it that way...
1814 * Need to disable if:
1815 * - more than one pipe is active
1816 * - changing FBC params (stride, fence, mode)
1817 * - new fb is too large to fit in compressed buffer
1818 * - going to an unsupported config (interlace, pixel multiply, etc.)
1820 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1821 if (tmp_crtc->enabled && tmp_crtc->fb) {
1823 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1824 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1831 if (!crtc || crtc->fb == NULL) {
1832 DRM_DEBUG_KMS("no output, disabling\n");
1833 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1837 intel_crtc = to_intel_crtc(crtc);
1839 intel_fb = to_intel_framebuffer(fb);
1840 obj = intel_fb->obj;
1842 if (!i915_enable_fbc) {
1843 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1844 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1847 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1848 DRM_DEBUG_KMS("framebuffer too large, disabling "
1850 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1853 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1854 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1855 DRM_DEBUG_KMS("mode incompatible with compression, "
1857 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1860 if ((crtc->mode.hdisplay > 2048) ||
1861 (crtc->mode.vdisplay > 1536)) {
1862 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1863 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1866 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1867 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1868 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1872 /* The use of a CPU fence is mandatory in order to detect writes
1873 * by the CPU to the scanout and trigger updates to the FBC.
1875 if (obj->tiling_mode != I915_TILING_X ||
1876 obj->fence_reg == I915_FENCE_REG_NONE) {
1877 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1878 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1882 /* If the kernel debugger is active, always disable compression */
1883 if (in_dbg_master())
1886 /* If the scanout has not changed, don't modify the FBC settings.
1887 * Note that we make the fundamental assumption that the fb->obj
1888 * cannot be unpinned (and have its GTT offset and fence revoked)
1889 * without first being decoupled from the scanout and FBC disabled.
1891 if (dev_priv->cfb_plane == intel_crtc->plane &&
1892 dev_priv->cfb_fb == fb->base.id &&
1893 dev_priv->cfb_y == crtc->y)
1896 if (intel_fbc_enabled(dev)) {
1897 /* We update FBC along two paths, after changing fb/crtc
1898 * configuration (modeswitching) and after page-flipping
1899 * finishes. For the latter, we know that not only did
1900 * we disable the FBC at the start of the page-flip
1901 * sequence, but also more than one vblank has passed.
1903 * For the former case of modeswitching, it is possible
1904 * to switch between two FBC valid configurations
1905 * instantaneously so we do need to disable the FBC
1906 * before we can modify its control registers. We also
1907 * have to wait for the next vblank for that to take
1908 * effect. However, since we delay enabling FBC we can
1909 * assume that a vblank has passed since disabling and
1910 * that we can safely alter the registers in the deferred
1913 * In the scenario that we go from a valid to invalid
1914 * and then back to valid FBC configuration we have
1915 * no strict enforcement that a vblank occurred since
1916 * disabling the FBC. However, along all current pipe
1917 * disabling paths we do need to wait for a vblank at
1918 * some point. And we wait before enabling FBC anyway.
1920 DRM_DEBUG_KMS("disabling active FBC for update\n");
1921 intel_disable_fbc(dev);
1924 intel_enable_fbc(crtc, 500);
1928 /* Multiple disables should be harmless */
1929 if (intel_fbc_enabled(dev)) {
1930 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1931 intel_disable_fbc(dev);
1936 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1937 struct drm_i915_gem_object *obj,
1938 struct intel_ring_buffer *pipelined)
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1944 switch (obj->tiling_mode) {
1945 case I915_TILING_NONE:
1946 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1947 alignment = 128 * 1024;
1948 else if (INTEL_INFO(dev)->gen >= 4)
1949 alignment = 4 * 1024;
1951 alignment = 64 * 1024;
1954 /* pin() will align the object as required by fence */
1958 /* FIXME: Is this true? */
1959 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 dev_priv->mm.interruptible = false;
1966 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1968 goto err_interruptible;
1970 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971 * fence, whereas 965+ only requires a fence if using
1972 * framebuffer compression. For simplicity, we always install
1973 * a fence as the cost is not that onerous.
1975 if (obj->tiling_mode != I915_TILING_NONE) {
1976 ret = i915_gem_object_get_fence(obj, pipelined);
1981 dev_priv->mm.interruptible = true;
1985 i915_gem_object_unpin(obj);
1987 dev_priv->mm.interruptible = true;
1991 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1994 struct drm_device *dev = crtc->dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1997 struct intel_framebuffer *intel_fb;
1998 struct drm_i915_gem_object *obj;
1999 int plane = intel_crtc->plane;
2000 unsigned long Start, Offset;
2009 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 intel_fb = to_intel_framebuffer(fb);
2014 obj = intel_fb->obj;
2016 reg = DSPCNTR(plane);
2017 dspcntr = I915_READ(reg);
2018 /* Mask out pixel format bits in case we change it */
2019 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2020 switch (fb->bits_per_pixel) {
2022 dspcntr |= DISPPLANE_8BPP;
2025 if (fb->depth == 15)
2026 dspcntr |= DISPPLANE_15_16BPP;
2028 dspcntr |= DISPPLANE_16BPP;
2032 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2035 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2038 if (INTEL_INFO(dev)->gen >= 4) {
2039 if (obj->tiling_mode != I915_TILING_NONE)
2040 dspcntr |= DISPPLANE_TILED;
2042 dspcntr &= ~DISPPLANE_TILED;
2045 I915_WRITE(reg, dspcntr);
2047 Start = obj->gtt_offset;
2048 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2050 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2051 Start, Offset, x, y, fb->pitch);
2052 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2053 if (INTEL_INFO(dev)->gen >= 4) {
2054 I915_WRITE(DSPSURF(plane), Start);
2055 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2056 I915_WRITE(DSPADDR(plane), Offset);
2058 I915_WRITE(DSPADDR(plane), Start + Offset);
2064 static int ironlake_update_plane(struct drm_crtc *crtc,
2065 struct drm_framebuffer *fb, int x, int y)
2067 struct drm_device *dev = crtc->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070 struct intel_framebuffer *intel_fb;
2071 struct drm_i915_gem_object *obj;
2072 int plane = intel_crtc->plane;
2073 unsigned long Start, Offset;
2082 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2086 intel_fb = to_intel_framebuffer(fb);
2087 obj = intel_fb->obj;
2089 reg = DSPCNTR(plane);
2090 dspcntr = I915_READ(reg);
2091 /* Mask out pixel format bits in case we change it */
2092 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093 switch (fb->bits_per_pixel) {
2095 dspcntr |= DISPPLANE_8BPP;
2098 if (fb->depth != 16)
2101 dspcntr |= DISPPLANE_16BPP;
2105 if (fb->depth == 24)
2106 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2107 else if (fb->depth == 30)
2108 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2113 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2120 dspcntr &= ~DISPPLANE_TILED;
2123 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2125 I915_WRITE(reg, dspcntr);
2127 Start = obj->gtt_offset;
2128 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2130 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2131 Start, Offset, x, y, fb->pitch);
2132 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2133 I915_WRITE(DSPSURF(plane), Start);
2134 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2135 I915_WRITE(DSPADDR(plane), Offset);
2141 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2143 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2144 int x, int y, enum mode_set_atomic state)
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2150 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2154 intel_update_fbc(dev);
2155 intel_increase_pllclock(crtc);
2161 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2162 struct drm_framebuffer *old_fb)
2164 struct drm_device *dev = crtc->dev;
2165 struct drm_i915_master_private *master_priv;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171 DRM_ERROR("No FB bound\n");
2175 switch (intel_crtc->plane) {
2180 DRM_ERROR("no plane for crtc\n");
2184 mutex_lock(&dev->struct_mutex);
2185 ret = intel_pin_and_fence_fb_obj(dev,
2186 to_intel_framebuffer(crtc->fb)->obj,
2189 mutex_unlock(&dev->struct_mutex);
2190 DRM_ERROR("pin & fence failed\n");
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2198 wait_event(dev_priv->pending_flip_queue,
2199 atomic_read(&dev_priv->mm.wedged) ||
2200 atomic_read(&obj->pending_flip) == 0);
2202 /* Big Hammer, we also need to ensure that any pending
2203 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2204 * current scanout is retired before unpinning the old
2207 * This should only fail upon a hung GPU, in which case we
2208 * can safely continue.
2210 ret = i915_gem_object_finish_gpu(obj);
2214 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2215 LEAVE_ATOMIC_MODE_SET);
2217 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2218 mutex_unlock(&dev->struct_mutex);
2219 DRM_ERROR("failed to update base address\n");
2224 intel_wait_for_vblank(dev, intel_crtc->pipe);
2225 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2228 mutex_unlock(&dev->struct_mutex);
2230 if (!dev->primary->master)
2233 master_priv = dev->primary->master->driver_priv;
2234 if (!master_priv->sarea_priv)
2237 if (intel_crtc->pipe) {
2238 master_priv->sarea_priv->pipeB_x = x;
2239 master_priv->sarea_priv->pipeB_y = y;
2241 master_priv->sarea_priv->pipeA_x = x;
2242 master_priv->sarea_priv->pipeA_y = y;
2248 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2254 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2255 dpa_ctl = I915_READ(DP_A);
2256 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2258 if (clock < 200000) {
2260 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2261 /* workaround for 160Mhz:
2262 1) program 0x4600c bits 15:0 = 0x8124
2263 2) program 0x46010 bit 0 = 1
2264 3) program 0x46034 bit 24 = 1
2265 4) program 0x64000 bit 14 = 1
2267 temp = I915_READ(0x4600c);
2269 I915_WRITE(0x4600c, temp | 0x8124);
2271 temp = I915_READ(0x46010);
2272 I915_WRITE(0x46010, temp | 1);
2274 temp = I915_READ(0x46034);
2275 I915_WRITE(0x46034, temp | (1 << 24));
2277 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2279 I915_WRITE(DP_A, dpa_ctl);
2285 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2287 struct drm_device *dev = crtc->dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 int pipe = intel_crtc->pipe;
2293 /* enable normal train */
2294 reg = FDI_TX_CTL(pipe);
2295 temp = I915_READ(reg);
2296 if (IS_IVYBRIDGE(dev)) {
2297 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2300 temp &= ~FDI_LINK_TRAIN_NONE;
2301 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2303 I915_WRITE(reg, temp);
2305 reg = FDI_RX_CTL(pipe);
2306 temp = I915_READ(reg);
2307 if (HAS_PCH_CPT(dev)) {
2308 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2311 temp &= ~FDI_LINK_TRAIN_NONE;
2312 temp |= FDI_LINK_TRAIN_NONE;
2314 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2316 /* wait one idle pattern time */
2320 /* IVB wants error correction enabled */
2321 if (IS_IVYBRIDGE(dev))
2322 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323 FDI_FE_ERRC_ENABLE);
2326 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 u32 flags = I915_READ(SOUTH_CHICKEN1);
2331 flags |= FDI_PHASE_SYNC_OVR(pipe);
2332 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2333 flags |= FDI_PHASE_SYNC_EN(pipe);
2334 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2335 POSTING_READ(SOUTH_CHICKEN1);
2338 /* The FDI link training functions for ILK/Ibexpeak. */
2339 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2341 struct drm_device *dev = crtc->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344 int pipe = intel_crtc->pipe;
2345 int plane = intel_crtc->plane;
2346 u32 reg, temp, tries;
2348 /* FDI needs bits from pipe & plane first */
2349 assert_pipe_enabled(dev_priv, pipe);
2350 assert_plane_enabled(dev_priv, plane);
2352 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2354 reg = FDI_RX_IMR(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~FDI_RX_SYMBOL_LOCK;
2357 temp &= ~FDI_RX_BIT_LOCK;
2358 I915_WRITE(reg, temp);
2362 /* enable CPU FDI TX and PCH FDI RX */
2363 reg = FDI_TX_CTL(pipe);
2364 temp = I915_READ(reg);
2366 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_1;
2369 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_1;
2375 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2380 /* Ironlake workaround, enable clock pointer after FDI enable*/
2381 if (HAS_PCH_IBX(dev)) {
2382 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2383 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2384 FDI_RX_PHASE_SYNC_POINTER_EN);
2387 reg = FDI_RX_IIR(pipe);
2388 for (tries = 0; tries < 5; tries++) {
2389 temp = I915_READ(reg);
2390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2392 if ((temp & FDI_RX_BIT_LOCK)) {
2393 DRM_DEBUG_KMS("FDI train 1 done.\n");
2394 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2399 DRM_ERROR("FDI train 1 fail!\n");
2402 reg = FDI_TX_CTL(pipe);
2403 temp = I915_READ(reg);
2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_PATTERN_2;
2406 I915_WRITE(reg, temp);
2408 reg = FDI_RX_CTL(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_LINK_TRAIN_NONE;
2411 temp |= FDI_LINK_TRAIN_PATTERN_2;
2412 I915_WRITE(reg, temp);
2417 reg = FDI_RX_IIR(pipe);
2418 for (tries = 0; tries < 5; tries++) {
2419 temp = I915_READ(reg);
2420 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422 if (temp & FDI_RX_SYMBOL_LOCK) {
2423 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2424 DRM_DEBUG_KMS("FDI train 2 done.\n");
2429 DRM_ERROR("FDI train 2 fail!\n");
2431 DRM_DEBUG_KMS("FDI train done\n");
2435 static const int snb_b_fdi_train_param [] = {
2436 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2437 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2438 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2439 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2442 /* The FDI link training functions for SNB/Cougarpoint. */
2443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2445 struct drm_device *dev = crtc->dev;
2446 struct drm_i915_private *dev_priv = dev->dev_private;
2447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2448 int pipe = intel_crtc->pipe;
2451 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2453 reg = FDI_RX_IMR(pipe);
2454 temp = I915_READ(reg);
2455 temp &= ~FDI_RX_SYMBOL_LOCK;
2456 temp &= ~FDI_RX_BIT_LOCK;
2457 I915_WRITE(reg, temp);
2462 /* enable CPU FDI TX and PCH FDI RX */
2463 reg = FDI_TX_CTL(pipe);
2464 temp = I915_READ(reg);
2466 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_1;
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
2476 if (HAS_PCH_CPT(dev)) {
2477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
2483 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2488 if (HAS_PCH_CPT(dev))
2489 cpt_phase_pointer_enable(dev, pipe);
2491 for (i = 0; i < 4; i++ ) {
2492 reg = FDI_TX_CTL(pipe);
2493 temp = I915_READ(reg);
2494 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2495 temp |= snb_b_fdi_train_param[i];
2496 I915_WRITE(reg, temp);
2501 reg = FDI_RX_IIR(pipe);
2502 temp = I915_READ(reg);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505 if (temp & FDI_RX_BIT_LOCK) {
2506 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507 DRM_DEBUG_KMS("FDI train 1 done.\n");
2512 DRM_ERROR("FDI train 1 fail!\n");
2515 reg = FDI_TX_CTL(pipe);
2516 temp = I915_READ(reg);
2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2522 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2524 I915_WRITE(reg, temp);
2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 if (HAS_PCH_CPT(dev)) {
2529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2532 temp &= ~FDI_LINK_TRAIN_NONE;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2;
2535 I915_WRITE(reg, temp);
2540 for (i = 0; i < 4; i++ ) {
2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2544 temp |= snb_b_fdi_train_param[i];
2545 I915_WRITE(reg, temp);
2550 reg = FDI_RX_IIR(pipe);
2551 temp = I915_READ(reg);
2552 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2554 if (temp & FDI_RX_SYMBOL_LOCK) {
2555 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2556 DRM_DEBUG_KMS("FDI train 2 done.\n");
2561 DRM_ERROR("FDI train 2 fail!\n");
2563 DRM_DEBUG_KMS("FDI train done.\n");
2566 /* Manual link training for Ivy Bridge A0 parts */
2567 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2569 struct drm_device *dev = crtc->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572 int pipe = intel_crtc->pipe;
2575 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2577 reg = FDI_RX_IMR(pipe);
2578 temp = I915_READ(reg);
2579 temp &= ~FDI_RX_SYMBOL_LOCK;
2580 temp &= ~FDI_RX_BIT_LOCK;
2581 I915_WRITE(reg, temp);
2586 /* enable CPU FDI TX and PCH FDI RX */
2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2590 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2591 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2592 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2597 reg = FDI_RX_CTL(pipe);
2598 temp = I915_READ(reg);
2599 temp &= ~FDI_LINK_TRAIN_AUTO;
2600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2607 if (HAS_PCH_CPT(dev))
2608 cpt_phase_pointer_enable(dev, pipe);
2610 for (i = 0; i < 4; i++ ) {
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2624 if (temp & FDI_RX_BIT_LOCK ||
2625 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2626 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2627 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632 DRM_ERROR("FDI train 1 fail!\n");
2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 I915_WRITE(reg, temp);
2643 reg = FDI_RX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647 I915_WRITE(reg, temp);
2652 for (i = 0; i < 4; i++ ) {
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 temp |= snb_b_fdi_train_param[i];
2657 I915_WRITE(reg, temp);
2662 reg = FDI_RX_IIR(pipe);
2663 temp = I915_READ(reg);
2664 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666 if (temp & FDI_RX_SYMBOL_LOCK) {
2667 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2668 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673 DRM_ERROR("FDI train 2 fail!\n");
2675 DRM_DEBUG_KMS("FDI train done.\n");
2678 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2680 struct drm_device *dev = crtc->dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2683 int pipe = intel_crtc->pipe;
2686 /* Write the TU size bits so error detection works */
2687 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2688 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2690 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2691 reg = FDI_RX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~((0x7 << 19) | (0x7 << 16));
2694 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2695 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2696 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2701 /* Switch from Rawclk to PCDclk */
2702 temp = I915_READ(reg);
2703 I915_WRITE(reg, temp | FDI_PCDCLK);
2708 /* Enable CPU FDI TX PLL, always on for Ironlake */
2709 reg = FDI_TX_CTL(pipe);
2710 temp = I915_READ(reg);
2711 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2712 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2719 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 u32 flags = I915_READ(SOUTH_CHICKEN1);
2724 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2725 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2726 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2727 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2728 POSTING_READ(SOUTH_CHICKEN1);
2730 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2732 struct drm_device *dev = crtc->dev;
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2735 int pipe = intel_crtc->pipe;
2738 /* disable CPU FDI tx and PCH FDI rx */
2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2744 reg = FDI_RX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 temp &= ~(0x7 << 16);
2747 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2748 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2753 /* Ironlake workaround, disable clock pointer after downing FDI */
2754 if (HAS_PCH_IBX(dev)) {
2755 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2756 I915_WRITE(FDI_RX_CHICKEN(pipe),
2757 I915_READ(FDI_RX_CHICKEN(pipe) &
2758 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2759 } else if (HAS_PCH_CPT(dev)) {
2760 cpt_phase_pointer_disable(dev, pipe);
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
2781 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2782 I915_WRITE(reg, temp);
2789 * When we disable a pipe, we need to clear any pending scanline wait events
2790 * to avoid hanging the ring, which we assume we are waiting on.
2792 static void intel_clear_scanline_wait(struct drm_device *dev)
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 struct intel_ring_buffer *ring;
2799 /* Can't break the hang on i8xx */
2802 ring = LP_RING(dev_priv);
2803 tmp = I915_READ_CTL(ring);
2804 if (tmp & RING_WAIT)
2805 I915_WRITE_CTL(ring, tmp);
2808 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810 struct drm_i915_gem_object *obj;
2811 struct drm_i915_private *dev_priv;
2813 if (crtc->fb == NULL)
2816 obj = to_intel_framebuffer(crtc->fb)->obj;
2817 dev_priv = crtc->dev->dev_private;
2818 wait_event(dev_priv->pending_flip_queue,
2819 atomic_read(&obj->pending_flip) == 0);
2822 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_mode_config *mode_config = &dev->mode_config;
2826 struct intel_encoder *encoder;
2829 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2830 * must be driven by its own crtc; no sharing is possible.
2832 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2833 if (encoder->base.crtc != crtc)
2836 switch (encoder->type) {
2837 case INTEL_OUTPUT_EDP:
2838 if (!intel_encoder_is_pch_edp(&encoder->base))
2848 * Enable PCH resources required for PCH ports:
2850 * - FDI training & RX/TX
2851 * - update transcoder timings
2852 * - DP transcoding bits
2855 static void ironlake_pch_enable(struct drm_crtc *crtc)
2857 struct drm_device *dev = crtc->dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2860 int pipe = intel_crtc->pipe;
2863 /* For PCH output, training FDI link */
2864 dev_priv->display.fdi_link_train(crtc);
2866 intel_enable_pch_pll(dev_priv, pipe);
2868 if (HAS_PCH_CPT(dev)) {
2869 /* Be sure PCH DPLL SEL is set */
2870 temp = I915_READ(PCH_DPLL_SEL);
2871 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2872 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2873 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2874 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2875 I915_WRITE(PCH_DPLL_SEL, temp);
2878 /* set transcoder timing, panel must allow it */
2879 assert_panel_unlocked(dev_priv, pipe);
2880 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2881 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2882 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2884 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2885 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2886 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2888 intel_fdi_normal_train(crtc);
2890 /* For PCH DP, enable TRANS_DP_CTL */
2891 if (HAS_PCH_CPT(dev) &&
2892 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2893 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2894 reg = TRANS_DP_CTL(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2897 TRANS_DP_SYNC_MASK |
2899 temp |= (TRANS_DP_OUTPUT_ENABLE |
2900 TRANS_DP_ENH_FRAMING);
2901 temp |= bpc << 9; /* same format but at 11:9 */
2903 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2904 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2905 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2906 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2908 switch (intel_trans_dp_port_sel(crtc)) {
2910 temp |= TRANS_DP_PORT_SEL_B;
2913 temp |= TRANS_DP_PORT_SEL_C;
2916 temp |= TRANS_DP_PORT_SEL_D;
2919 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2920 temp |= TRANS_DP_PORT_SEL_B;
2924 I915_WRITE(reg, temp);
2927 intel_enable_transcoder(dev_priv, pipe);
2930 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
2936 int plane = intel_crtc->plane;
2940 if (intel_crtc->active)
2943 intel_crtc->active = true;
2944 intel_update_watermarks(dev);
2946 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2947 temp = I915_READ(PCH_LVDS);
2948 if ((temp & LVDS_PORT_EN) == 0)
2949 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2952 is_pch_port = intel_crtc_driving_pch(crtc);
2955 ironlake_fdi_pll_enable(crtc);
2957 ironlake_fdi_disable(crtc);
2959 /* Enable panel fitting for LVDS */
2960 if (dev_priv->pch_pf_size &&
2961 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2962 /* Force use of hard-coded filter coefficients
2963 * as some pre-programmed values are broken,
2966 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2967 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2968 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2972 * On ILK+ LUT must be loaded before the pipe is running but with
2975 intel_crtc_load_lut(crtc);
2977 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2978 intel_enable_plane(dev_priv, plane, pipe);
2981 ironlake_pch_enable(crtc);
2983 mutex_lock(&dev->struct_mutex);
2984 intel_update_fbc(dev);
2985 mutex_unlock(&dev->struct_mutex);
2987 intel_crtc_update_cursor(crtc, true);
2990 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995 int pipe = intel_crtc->pipe;
2996 int plane = intel_crtc->plane;
2999 if (!intel_crtc->active)
3002 intel_crtc_wait_for_pending_flips(crtc);
3003 drm_vblank_off(dev, pipe);
3004 intel_crtc_update_cursor(crtc, false);
3006 intel_disable_plane(dev_priv, plane, pipe);
3008 if (dev_priv->cfb_plane == plane)
3009 intel_disable_fbc(dev);
3011 intel_disable_pipe(dev_priv, pipe);
3014 I915_WRITE(PF_CTL(pipe), 0);
3015 I915_WRITE(PF_WIN_SZ(pipe), 0);
3017 ironlake_fdi_disable(crtc);
3019 /* This is a horrible layering violation; we should be doing this in
3020 * the connector/encoder ->prepare instead, but we don't always have
3021 * enough information there about the config to know whether it will
3022 * actually be necessary or just cause undesired flicker.
3024 intel_disable_pch_ports(dev_priv, pipe);
3026 intel_disable_transcoder(dev_priv, pipe);
3028 if (HAS_PCH_CPT(dev)) {
3029 /* disable TRANS_DP_CTL */
3030 reg = TRANS_DP_CTL(pipe);
3031 temp = I915_READ(reg);
3032 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3033 temp |= TRANS_DP_PORT_SEL_NONE;
3034 I915_WRITE(reg, temp);
3036 /* disable DPLL_SEL */
3037 temp = I915_READ(PCH_DPLL_SEL);
3040 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3043 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3046 /* FIXME: manage transcoder PLLs? */
3047 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3052 I915_WRITE(PCH_DPLL_SEL, temp);
3055 /* disable PCH DPLL */
3056 intel_disable_pch_pll(dev_priv, pipe);
3058 /* Switch from PCDclk to Rawclk */
3059 reg = FDI_RX_CTL(pipe);
3060 temp = I915_READ(reg);
3061 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3063 /* Disable CPU FDI TX PLL */
3064 reg = FDI_TX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3071 reg = FDI_RX_CTL(pipe);
3072 temp = I915_READ(reg);
3073 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3075 /* Wait for the clocks to turn off. */
3079 intel_crtc->active = false;
3080 intel_update_watermarks(dev);
3082 mutex_lock(&dev->struct_mutex);
3083 intel_update_fbc(dev);
3084 intel_clear_scanline_wait(dev);
3085 mutex_unlock(&dev->struct_mutex);
3088 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091 int pipe = intel_crtc->pipe;
3092 int plane = intel_crtc->plane;
3094 /* XXX: When our outputs are all unaware of DPMS modes other than off
3095 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3098 case DRM_MODE_DPMS_ON:
3099 case DRM_MODE_DPMS_STANDBY:
3100 case DRM_MODE_DPMS_SUSPEND:
3101 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3102 ironlake_crtc_enable(crtc);
3105 case DRM_MODE_DPMS_OFF:
3106 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3107 ironlake_crtc_disable(crtc);
3112 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3114 if (!enable && intel_crtc->overlay) {
3115 struct drm_device *dev = intel_crtc->base.dev;
3116 struct drm_i915_private *dev_priv = dev->dev_private;
3118 mutex_lock(&dev->struct_mutex);
3119 dev_priv->mm.interruptible = false;
3120 (void) intel_overlay_switch_off(intel_crtc->overlay);
3121 dev_priv->mm.interruptible = true;
3122 mutex_unlock(&dev->struct_mutex);
3125 /* Let userspace switch the overlay on again. In most cases userspace
3126 * has to recompute where to put it anyway.
3130 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3132 struct drm_device *dev = crtc->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135 int pipe = intel_crtc->pipe;
3136 int plane = intel_crtc->plane;
3138 if (intel_crtc->active)
3141 intel_crtc->active = true;
3142 intel_update_watermarks(dev);
3144 intel_enable_pll(dev_priv, pipe);
3145 intel_enable_pipe(dev_priv, pipe, false);
3146 intel_enable_plane(dev_priv, plane, pipe);
3148 intel_crtc_load_lut(crtc);
3149 intel_update_fbc(dev);
3151 /* Give the overlay scaler a chance to enable if it's on this pipe */
3152 intel_crtc_dpms_overlay(intel_crtc, true);
3153 intel_crtc_update_cursor(crtc, true);
3156 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3158 struct drm_device *dev = crtc->dev;
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3161 int pipe = intel_crtc->pipe;
3162 int plane = intel_crtc->plane;
3164 if (!intel_crtc->active)
3167 /* Give the overlay scaler a chance to disable if it's on this pipe */
3168 intel_crtc_wait_for_pending_flips(crtc);
3169 drm_vblank_off(dev, pipe);
3170 intel_crtc_dpms_overlay(intel_crtc, false);
3171 intel_crtc_update_cursor(crtc, false);
3173 if (dev_priv->cfb_plane == plane)
3174 intel_disable_fbc(dev);
3176 intel_disable_plane(dev_priv, plane, pipe);
3177 intel_disable_pipe(dev_priv, pipe);
3178 intel_disable_pll(dev_priv, pipe);
3180 intel_crtc->active = false;
3181 intel_update_fbc(dev);
3182 intel_update_watermarks(dev);
3183 intel_clear_scanline_wait(dev);
3186 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3188 /* XXX: When our outputs are all unaware of DPMS modes other than off
3189 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3192 case DRM_MODE_DPMS_ON:
3193 case DRM_MODE_DPMS_STANDBY:
3194 case DRM_MODE_DPMS_SUSPEND:
3195 i9xx_crtc_enable(crtc);
3197 case DRM_MODE_DPMS_OFF:
3198 i9xx_crtc_disable(crtc);
3204 * Sets the power management mode of the pipe and plane.
3206 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3208 struct drm_device *dev = crtc->dev;
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210 struct drm_i915_master_private *master_priv;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 int pipe = intel_crtc->pipe;
3215 if (intel_crtc->dpms_mode == mode)
3218 intel_crtc->dpms_mode = mode;
3220 dev_priv->display.dpms(crtc, mode);
3222 if (!dev->primary->master)
3225 master_priv = dev->primary->master->driver_priv;
3226 if (!master_priv->sarea_priv)
3229 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3233 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3234 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3237 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3238 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3241 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3246 static void intel_crtc_disable(struct drm_crtc *crtc)
3248 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3249 struct drm_device *dev = crtc->dev;
3251 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3254 mutex_lock(&dev->struct_mutex);
3255 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3256 mutex_unlock(&dev->struct_mutex);
3260 /* Prepare for a mode set.
3262 * Note we could be a lot smarter here. We need to figure out which outputs
3263 * will be enabled, which disabled (in short, how the config will changes)
3264 * and perform the minimum necessary steps to accomplish that, e.g. updating
3265 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3266 * panel fitting is in the proper state, etc.
3268 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3270 i9xx_crtc_disable(crtc);
3273 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3275 i9xx_crtc_enable(crtc);
3278 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3280 ironlake_crtc_disable(crtc);
3283 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3285 ironlake_crtc_enable(crtc);
3288 void intel_encoder_prepare (struct drm_encoder *encoder)
3290 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3291 /* lvds has its own version of prepare see intel_lvds_prepare */
3292 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3295 void intel_encoder_commit (struct drm_encoder *encoder)
3297 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3298 /* lvds has its own version of commit see intel_lvds_commit */
3299 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3302 void intel_encoder_destroy(struct drm_encoder *encoder)
3304 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3306 drm_encoder_cleanup(encoder);
3307 kfree(intel_encoder);
3310 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3311 struct drm_display_mode *mode,
3312 struct drm_display_mode *adjusted_mode)
3314 struct drm_device *dev = crtc->dev;
3316 if (HAS_PCH_SPLIT(dev)) {
3317 /* FDI link clock is fixed at 2.7G */
3318 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3322 /* XXX some encoders set the crtcinfo, others don't.
3323 * Obviously we need some form of conflict resolution here...
3325 if (adjusted_mode->crtc_htotal == 0)
3326 drm_mode_set_crtcinfo(adjusted_mode, 0);
3331 static int i945_get_display_clock_speed(struct drm_device *dev)
3336 static int i915_get_display_clock_speed(struct drm_device *dev)
3341 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3346 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3350 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3352 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3355 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3356 case GC_DISPLAY_CLOCK_333_MHZ:
3359 case GC_DISPLAY_CLOCK_190_200_MHZ:
3365 static int i865_get_display_clock_speed(struct drm_device *dev)
3370 static int i855_get_display_clock_speed(struct drm_device *dev)
3373 /* Assume that the hardware is in the high speed state. This
3374 * should be the default.
3376 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3377 case GC_CLOCK_133_200:
3378 case GC_CLOCK_100_200:
3380 case GC_CLOCK_166_250:
3382 case GC_CLOCK_100_133:
3386 /* Shouldn't happen */
3390 static int i830_get_display_clock_speed(struct drm_device *dev)
3404 fdi_reduce_ratio(u32 *num, u32 *den)
3406 while (*num > 0xffffff || *den > 0xffffff) {
3413 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3414 int link_clock, struct fdi_m_n *m_n)
3416 m_n->tu = 64; /* default size */
3418 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3419 m_n->gmch_m = bits_per_pixel * pixel_clock;
3420 m_n->gmch_n = link_clock * nlanes * 8;
3421 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3423 m_n->link_m = pixel_clock;
3424 m_n->link_n = link_clock;
3425 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3429 struct intel_watermark_params {
3430 unsigned long fifo_size;
3431 unsigned long max_wm;
3432 unsigned long default_wm;
3433 unsigned long guard_size;
3434 unsigned long cacheline_size;
3437 /* Pineview has different values for various configs */
3438 static const struct intel_watermark_params pineview_display_wm = {
3439 PINEVIEW_DISPLAY_FIFO,
3443 PINEVIEW_FIFO_LINE_SIZE
3445 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3446 PINEVIEW_DISPLAY_FIFO,
3448 PINEVIEW_DFT_HPLLOFF_WM,
3450 PINEVIEW_FIFO_LINE_SIZE
3452 static const struct intel_watermark_params pineview_cursor_wm = {
3453 PINEVIEW_CURSOR_FIFO,
3454 PINEVIEW_CURSOR_MAX_WM,
3455 PINEVIEW_CURSOR_DFT_WM,
3456 PINEVIEW_CURSOR_GUARD_WM,
3457 PINEVIEW_FIFO_LINE_SIZE,
3459 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3460 PINEVIEW_CURSOR_FIFO,
3461 PINEVIEW_CURSOR_MAX_WM,
3462 PINEVIEW_CURSOR_DFT_WM,
3463 PINEVIEW_CURSOR_GUARD_WM,
3464 PINEVIEW_FIFO_LINE_SIZE
3466 static const struct intel_watermark_params g4x_wm_info = {
3473 static const struct intel_watermark_params g4x_cursor_wm_info = {
3480 static const struct intel_watermark_params i965_cursor_wm_info = {
3485 I915_FIFO_LINE_SIZE,
3487 static const struct intel_watermark_params i945_wm_info = {
3494 static const struct intel_watermark_params i915_wm_info = {
3501 static const struct intel_watermark_params i855_wm_info = {
3508 static const struct intel_watermark_params i830_wm_info = {
3516 static const struct intel_watermark_params ironlake_display_wm_info = {
3523 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3530 static const struct intel_watermark_params ironlake_display_srwm_info = {
3531 ILK_DISPLAY_SR_FIFO,
3532 ILK_DISPLAY_MAX_SRWM,
3533 ILK_DISPLAY_DFT_SRWM,
3537 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3539 ILK_CURSOR_MAX_SRWM,
3540 ILK_CURSOR_DFT_SRWM,
3545 static const struct intel_watermark_params sandybridge_display_wm_info = {
3552 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3559 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3560 SNB_DISPLAY_SR_FIFO,
3561 SNB_DISPLAY_MAX_SRWM,
3562 SNB_DISPLAY_DFT_SRWM,
3566 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3568 SNB_CURSOR_MAX_SRWM,
3569 SNB_CURSOR_DFT_SRWM,
3576 * intel_calculate_wm - calculate watermark level
3577 * @clock_in_khz: pixel clock
3578 * @wm: chip FIFO params
3579 * @pixel_size: display pixel size
3580 * @latency_ns: memory latency for the platform
3582 * Calculate the watermark level (the level at which the display plane will
3583 * start fetching from memory again). Each chip has a different display
3584 * FIFO size and allocation, so the caller needs to figure that out and pass
3585 * in the correct intel_watermark_params structure.
3587 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3588 * on the pixel size. When it reaches the watermark level, it'll start
3589 * fetching FIFO line sized based chunks from memory until the FIFO fills
3590 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3591 * will occur, and a display engine hang could result.
3593 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3594 const struct intel_watermark_params *wm,
3597 unsigned long latency_ns)
3599 long entries_required, wm_size;
3602 * Note: we need to make sure we don't overflow for various clock &
3604 * clocks go from a few thousand to several hundred thousand.
3605 * latency is usually a few thousand
3607 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3609 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3611 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3613 wm_size = fifo_size - (entries_required + wm->guard_size);
3615 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3617 /* Don't promote wm_size to unsigned... */
3618 if (wm_size > (long)wm->max_wm)
3619 wm_size = wm->max_wm;
3621 wm_size = wm->default_wm;
3625 struct cxsr_latency {
3628 unsigned long fsb_freq;
3629 unsigned long mem_freq;
3630 unsigned long display_sr;
3631 unsigned long display_hpll_disable;
3632 unsigned long cursor_sr;
3633 unsigned long cursor_hpll_disable;
3636 static const struct cxsr_latency cxsr_latency_table[] = {
3637 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3638 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3639 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3640 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3641 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3643 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3644 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3645 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3646 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3647 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3649 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3650 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3651 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3652 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3653 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3655 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3656 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3657 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3658 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3659 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3661 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3662 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3663 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3664 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3665 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3667 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3668 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3669 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3670 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3671 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3674 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3679 const struct cxsr_latency *latency;
3682 if (fsb == 0 || mem == 0)
3685 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3686 latency = &cxsr_latency_table[i];
3687 if (is_desktop == latency->is_desktop &&
3688 is_ddr3 == latency->is_ddr3 &&
3689 fsb == latency->fsb_freq && mem == latency->mem_freq)
3693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3698 static void pineview_disable_cxsr(struct drm_device *dev)
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3702 /* deactivate cxsr */
3703 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3707 * Latency for FIFO fetches is dependent on several factors:
3708 * - memory configuration (speed, channels)
3710 * - current MCH state
3711 * It can be fairly high in some situations, so here we assume a fairly
3712 * pessimal value. It's a tradeoff between extra memory fetches (if we
3713 * set this value too high, the FIFO will fetch frequently to stay full)
3714 * and power consumption (set it too low to save power and we might see
3715 * FIFO underruns and display "flicker").
3717 * A value of 5us seems to be a good balance; safe for very low end
3718 * platforms but not overly aggressive on lower latency configs.
3720 static const int latency_ns = 5000;
3722 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 uint32_t dsparb = I915_READ(DSPARB);
3728 size = dsparb & 0x7f;
3730 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3732 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3733 plane ? "B" : "A", size);
3738 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 uint32_t dsparb = I915_READ(DSPARB);
3744 size = dsparb & 0x1ff;
3746 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3747 size >>= 1; /* Convert to cachelines */
3749 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3750 plane ? "B" : "A", size);
3755 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 uint32_t dsparb = I915_READ(DSPARB);
3761 size = dsparb & 0x7f;
3762 size >>= 2; /* Convert to cachelines */
3764 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3771 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 uint32_t dsparb = I915_READ(DSPARB);
3777 size = dsparb & 0x7f;
3778 size >>= 1; /* Convert to cachelines */
3780 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3781 plane ? "B" : "A", size);
3786 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3788 struct drm_crtc *crtc, *enabled = NULL;
3790 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3791 if (crtc->enabled && crtc->fb) {
3801 static void pineview_update_wm(struct drm_device *dev)
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct drm_crtc *crtc;
3805 const struct cxsr_latency *latency;
3809 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3810 dev_priv->fsb_freq, dev_priv->mem_freq);
3812 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3813 pineview_disable_cxsr(dev);
3817 crtc = single_enabled_crtc(dev);
3819 int clock = crtc->mode.clock;
3820 int pixel_size = crtc->fb->bits_per_pixel / 8;
3823 wm = intel_calculate_wm(clock, &pineview_display_wm,
3824 pineview_display_wm.fifo_size,
3825 pixel_size, latency->display_sr);
3826 reg = I915_READ(DSPFW1);
3827 reg &= ~DSPFW_SR_MASK;
3828 reg |= wm << DSPFW_SR_SHIFT;
3829 I915_WRITE(DSPFW1, reg);
3830 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3833 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3834 pineview_display_wm.fifo_size,
3835 pixel_size, latency->cursor_sr);
3836 reg = I915_READ(DSPFW3);
3837 reg &= ~DSPFW_CURSOR_SR_MASK;
3838 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3839 I915_WRITE(DSPFW3, reg);
3841 /* Display HPLL off SR */
3842 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3843 pineview_display_hplloff_wm.fifo_size,
3844 pixel_size, latency->display_hpll_disable);
3845 reg = I915_READ(DSPFW3);
3846 reg &= ~DSPFW_HPLL_SR_MASK;
3847 reg |= wm & DSPFW_HPLL_SR_MASK;
3848 I915_WRITE(DSPFW3, reg);
3850 /* cursor HPLL off SR */
3851 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3852 pineview_display_hplloff_wm.fifo_size,
3853 pixel_size, latency->cursor_hpll_disable);
3854 reg = I915_READ(DSPFW3);
3855 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3856 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3857 I915_WRITE(DSPFW3, reg);
3858 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3862 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3863 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3865 pineview_disable_cxsr(dev);
3866 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3870 static bool g4x_compute_wm0(struct drm_device *dev,
3872 const struct intel_watermark_params *display,
3873 int display_latency_ns,
3874 const struct intel_watermark_params *cursor,
3875 int cursor_latency_ns,
3879 struct drm_crtc *crtc;
3880 int htotal, hdisplay, clock, pixel_size;
3881 int line_time_us, line_count;
3882 int entries, tlb_miss;
3884 crtc = intel_get_crtc_for_plane(dev, plane);
3885 if (crtc->fb == NULL || !crtc->enabled) {
3886 *cursor_wm = cursor->guard_size;
3887 *plane_wm = display->guard_size;
3891 htotal = crtc->mode.htotal;
3892 hdisplay = crtc->mode.hdisplay;
3893 clock = crtc->mode.clock;
3894 pixel_size = crtc->fb->bits_per_pixel / 8;
3896 /* Use the small buffer method to calculate plane watermark */
3897 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3898 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3900 entries += tlb_miss;
3901 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3902 *plane_wm = entries + display->guard_size;
3903 if (*plane_wm > (int)display->max_wm)
3904 *plane_wm = display->max_wm;
3906 /* Use the large buffer method to calculate cursor watermark */
3907 line_time_us = ((htotal * 1000) / clock);
3908 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3909 entries = line_count * 64 * pixel_size;
3910 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3912 entries += tlb_miss;
3913 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3914 *cursor_wm = entries + cursor->guard_size;
3915 if (*cursor_wm > (int)cursor->max_wm)
3916 *cursor_wm = (int)cursor->max_wm;
3922 * Check the wm result.
3924 * If any calculated watermark values is larger than the maximum value that
3925 * can be programmed into the associated watermark register, that watermark
3928 static bool g4x_check_srwm(struct drm_device *dev,
3929 int display_wm, int cursor_wm,
3930 const struct intel_watermark_params *display,
3931 const struct intel_watermark_params *cursor)
3933 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3934 display_wm, cursor_wm);
3936 if (display_wm > display->max_wm) {
3937 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3938 display_wm, display->max_wm);
3942 if (cursor_wm > cursor->max_wm) {
3943 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3944 cursor_wm, cursor->max_wm);
3948 if (!(display_wm || cursor_wm)) {
3949 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3956 static bool g4x_compute_srwm(struct drm_device *dev,
3959 const struct intel_watermark_params *display,
3960 const struct intel_watermark_params *cursor,
3961 int *display_wm, int *cursor_wm)
3963 struct drm_crtc *crtc;
3964 int hdisplay, htotal, pixel_size, clock;
3965 unsigned long line_time_us;
3966 int line_count, line_size;
3971 *display_wm = *cursor_wm = 0;
3975 crtc = intel_get_crtc_for_plane(dev, plane);
3976 hdisplay = crtc->mode.hdisplay;
3977 htotal = crtc->mode.htotal;
3978 clock = crtc->mode.clock;
3979 pixel_size = crtc->fb->bits_per_pixel / 8;
3981 line_time_us = (htotal * 1000) / clock;
3982 line_count = (latency_ns / line_time_us + 1000) / 1000;
3983 line_size = hdisplay * pixel_size;
3985 /* Use the minimum of the small and large buffer method for primary */
3986 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3987 large = line_count * line_size;
3989 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3990 *display_wm = entries + display->guard_size;
3992 /* calculate the self-refresh watermark for display cursor */
3993 entries = line_count * pixel_size * 64;
3994 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3995 *cursor_wm = entries + cursor->guard_size;
3997 return g4x_check_srwm(dev,
3998 *display_wm, *cursor_wm,
4002 #define single_plane_enabled(mask) is_power_of_2(mask)
4004 static void g4x_update_wm(struct drm_device *dev)
4006 static const int sr_latency_ns = 12000;
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4009 int plane_sr, cursor_sr;
4010 unsigned int enabled = 0;
4012 if (g4x_compute_wm0(dev, 0,
4013 &g4x_wm_info, latency_ns,
4014 &g4x_cursor_wm_info, latency_ns,
4015 &planea_wm, &cursora_wm))
4018 if (g4x_compute_wm0(dev, 1,
4019 &g4x_wm_info, latency_ns,
4020 &g4x_cursor_wm_info, latency_ns,
4021 &planeb_wm, &cursorb_wm))
4024 plane_sr = cursor_sr = 0;
4025 if (single_plane_enabled(enabled) &&
4026 g4x_compute_srwm(dev, ffs(enabled) - 1,
4029 &g4x_cursor_wm_info,
4030 &plane_sr, &cursor_sr))
4031 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4033 I915_WRITE(FW_BLC_SELF,
4034 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4036 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4037 planea_wm, cursora_wm,
4038 planeb_wm, cursorb_wm,
4039 plane_sr, cursor_sr);
4042 (plane_sr << DSPFW_SR_SHIFT) |
4043 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4044 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4047 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4048 (cursora_wm << DSPFW_CURSORA_SHIFT));
4049 /* HPLL off in SR has some issues on G4x... disable it */
4051 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4052 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4055 static void i965_update_wm(struct drm_device *dev)
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4058 struct drm_crtc *crtc;
4062 /* Calc sr entries for one plane configs */
4063 crtc = single_enabled_crtc(dev);
4065 /* self-refresh has much higher latency */
4066 static const int sr_latency_ns = 12000;
4067 int clock = crtc->mode.clock;
4068 int htotal = crtc->mode.htotal;
4069 int hdisplay = crtc->mode.hdisplay;
4070 int pixel_size = crtc->fb->bits_per_pixel / 8;
4071 unsigned long line_time_us;
4074 line_time_us = ((htotal * 1000) / clock);
4076 /* Use ns/us then divide to preserve precision */
4077 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4078 pixel_size * hdisplay;
4079 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4080 srwm = I965_FIFO_SIZE - entries;
4084 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4087 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4089 entries = DIV_ROUND_UP(entries,
4090 i965_cursor_wm_info.cacheline_size);
4091 cursor_sr = i965_cursor_wm_info.fifo_size -
4092 (entries + i965_cursor_wm_info.guard_size);
4094 if (cursor_sr > i965_cursor_wm_info.max_wm)
4095 cursor_sr = i965_cursor_wm_info.max_wm;
4097 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4098 "cursor %d\n", srwm, cursor_sr);
4100 if (IS_CRESTLINE(dev))
4101 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4103 /* Turn off self refresh if both pipes are enabled */
4104 if (IS_CRESTLINE(dev))
4105 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4109 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4112 /* 965 has limitations... */
4113 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4114 (8 << 16) | (8 << 8) | (8 << 0));
4115 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4116 /* update cursor SR watermark */
4117 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4120 static void i9xx_update_wm(struct drm_device *dev)
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 const struct intel_watermark_params *wm_info;
4128 int planea_wm, planeb_wm;
4129 struct drm_crtc *crtc, *enabled = NULL;
4132 wm_info = &i945_wm_info;
4133 else if (!IS_GEN2(dev))
4134 wm_info = &i915_wm_info;
4136 wm_info = &i855_wm_info;
4138 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4139 crtc = intel_get_crtc_for_plane(dev, 0);
4140 if (crtc->enabled && crtc->fb) {
4141 planea_wm = intel_calculate_wm(crtc->mode.clock,
4143 crtc->fb->bits_per_pixel / 8,
4147 planea_wm = fifo_size - wm_info->guard_size;
4149 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4150 crtc = intel_get_crtc_for_plane(dev, 1);
4151 if (crtc->enabled && crtc->fb) {
4152 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4154 crtc->fb->bits_per_pixel / 8,
4156 if (enabled == NULL)
4161 planeb_wm = fifo_size - wm_info->guard_size;
4163 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4166 * Overlay gets an aggressive default since video jitter is bad.
4170 /* Play safe and disable self-refresh before adjusting watermarks. */
4171 if (IS_I945G(dev) || IS_I945GM(dev))
4172 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4173 else if (IS_I915GM(dev))
4174 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4176 /* Calc sr entries for one plane configs */
4177 if (HAS_FW_BLC(dev) && enabled) {
4178 /* self-refresh has much higher latency */
4179 static const int sr_latency_ns = 6000;
4180 int clock = enabled->mode.clock;
4181 int htotal = enabled->mode.htotal;
4182 int hdisplay = enabled->mode.hdisplay;
4183 int pixel_size = enabled->fb->bits_per_pixel / 8;
4184 unsigned long line_time_us;
4187 line_time_us = (htotal * 1000) / clock;
4189 /* Use ns/us then divide to preserve precision */
4190 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4191 pixel_size * hdisplay;
4192 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4193 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4194 srwm = wm_info->fifo_size - entries;
4198 if (IS_I945G(dev) || IS_I945GM(dev))
4199 I915_WRITE(FW_BLC_SELF,
4200 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4201 else if (IS_I915GM(dev))
4202 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4205 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4206 planea_wm, planeb_wm, cwm, srwm);
4208 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4209 fwater_hi = (cwm & 0x1f);
4211 /* Set request length to 8 cachelines per fetch */
4212 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4213 fwater_hi = fwater_hi | (1 << 8);
4215 I915_WRITE(FW_BLC, fwater_lo);
4216 I915_WRITE(FW_BLC2, fwater_hi);
4218 if (HAS_FW_BLC(dev)) {
4220 if (IS_I945G(dev) || IS_I945GM(dev))
4221 I915_WRITE(FW_BLC_SELF,
4222 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4223 else if (IS_I915GM(dev))
4224 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4225 DRM_DEBUG_KMS("memory self refresh enabled\n");
4227 DRM_DEBUG_KMS("memory self refresh disabled\n");
4231 static void i830_update_wm(struct drm_device *dev)
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234 struct drm_crtc *crtc;
4238 crtc = single_enabled_crtc(dev);
4242 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4243 dev_priv->display.get_fifo_size(dev, 0),
4244 crtc->fb->bits_per_pixel / 8,
4246 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4247 fwater_lo |= (3<<8) | planea_wm;
4249 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4251 I915_WRITE(FW_BLC, fwater_lo);
4254 #define ILK_LP0_PLANE_LATENCY 700
4255 #define ILK_LP0_CURSOR_LATENCY 1300
4258 * Check the wm result.
4260 * If any calculated watermark values is larger than the maximum value that
4261 * can be programmed into the associated watermark register, that watermark
4264 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4265 int fbc_wm, int display_wm, int cursor_wm,
4266 const struct intel_watermark_params *display,
4267 const struct intel_watermark_params *cursor)
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4271 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4272 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4274 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4275 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4276 fbc_wm, SNB_FBC_MAX_SRWM, level);
4278 /* fbc has it's own way to disable FBC WM */
4279 I915_WRITE(DISP_ARB_CTL,
4280 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4284 if (display_wm > display->max_wm) {
4285 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4286 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4290 if (cursor_wm > cursor->max_wm) {
4291 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4292 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4296 if (!(fbc_wm || display_wm || cursor_wm)) {
4297 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4305 * Compute watermark values of WM[1-3],
4307 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4309 const struct intel_watermark_params *display,
4310 const struct intel_watermark_params *cursor,
4311 int *fbc_wm, int *display_wm, int *cursor_wm)
4313 struct drm_crtc *crtc;
4314 unsigned long line_time_us;
4315 int hdisplay, htotal, pixel_size, clock;
4316 int line_count, line_size;
4321 *fbc_wm = *display_wm = *cursor_wm = 0;
4325 crtc = intel_get_crtc_for_plane(dev, plane);
4326 hdisplay = crtc->mode.hdisplay;
4327 htotal = crtc->mode.htotal;
4328 clock = crtc->mode.clock;
4329 pixel_size = crtc->fb->bits_per_pixel / 8;
4331 line_time_us = (htotal * 1000) / clock;
4332 line_count = (latency_ns / line_time_us + 1000) / 1000;
4333 line_size = hdisplay * pixel_size;
4335 /* Use the minimum of the small and large buffer method for primary */
4336 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4337 large = line_count * line_size;
4339 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4340 *display_wm = entries + display->guard_size;
4344 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4346 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4348 /* calculate the self-refresh watermark for display cursor */
4349 entries = line_count * pixel_size * 64;
4350 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4351 *cursor_wm = entries + cursor->guard_size;
4353 return ironlake_check_srwm(dev, level,
4354 *fbc_wm, *display_wm, *cursor_wm,
4358 static void ironlake_update_wm(struct drm_device *dev)
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 int fbc_wm, plane_wm, cursor_wm;
4362 unsigned int enabled;
4365 if (g4x_compute_wm0(dev, 0,
4366 &ironlake_display_wm_info,
4367 ILK_LP0_PLANE_LATENCY,
4368 &ironlake_cursor_wm_info,
4369 ILK_LP0_CURSOR_LATENCY,
4370 &plane_wm, &cursor_wm)) {
4371 I915_WRITE(WM0_PIPEA_ILK,
4372 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4373 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4374 " plane %d, " "cursor: %d\n",
4375 plane_wm, cursor_wm);
4379 if (g4x_compute_wm0(dev, 1,
4380 &ironlake_display_wm_info,
4381 ILK_LP0_PLANE_LATENCY,
4382 &ironlake_cursor_wm_info,
4383 ILK_LP0_CURSOR_LATENCY,
4384 &plane_wm, &cursor_wm)) {
4385 I915_WRITE(WM0_PIPEB_ILK,
4386 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4387 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4388 " plane %d, cursor: %d\n",
4389 plane_wm, cursor_wm);
4394 * Calculate and update the self-refresh watermark only when one
4395 * display plane is used.
4397 I915_WRITE(WM3_LP_ILK, 0);
4398 I915_WRITE(WM2_LP_ILK, 0);
4399 I915_WRITE(WM1_LP_ILK, 0);
4401 if (!single_plane_enabled(enabled))
4403 enabled = ffs(enabled) - 1;
4406 if (!ironlake_compute_srwm(dev, 1, enabled,
4407 ILK_READ_WM1_LATENCY() * 500,
4408 &ironlake_display_srwm_info,
4409 &ironlake_cursor_srwm_info,
4410 &fbc_wm, &plane_wm, &cursor_wm))
4413 I915_WRITE(WM1_LP_ILK,
4415 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4416 (fbc_wm << WM1_LP_FBC_SHIFT) |
4417 (plane_wm << WM1_LP_SR_SHIFT) |
4421 if (!ironlake_compute_srwm(dev, 2, enabled,
4422 ILK_READ_WM2_LATENCY() * 500,
4423 &ironlake_display_srwm_info,
4424 &ironlake_cursor_srwm_info,
4425 &fbc_wm, &plane_wm, &cursor_wm))
4428 I915_WRITE(WM2_LP_ILK,
4430 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4431 (fbc_wm << WM1_LP_FBC_SHIFT) |
4432 (plane_wm << WM1_LP_SR_SHIFT) |
4436 * WM3 is unsupported on ILK, probably because we don't have latency
4437 * data for that power state
4441 static void sandybridge_update_wm(struct drm_device *dev)
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4445 int fbc_wm, plane_wm, cursor_wm;
4446 unsigned int enabled;
4449 if (g4x_compute_wm0(dev, 0,
4450 &sandybridge_display_wm_info, latency,
4451 &sandybridge_cursor_wm_info, latency,
4452 &plane_wm, &cursor_wm)) {
4453 I915_WRITE(WM0_PIPEA_ILK,
4454 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4455 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4456 " plane %d, " "cursor: %d\n",
4457 plane_wm, cursor_wm);
4461 if (g4x_compute_wm0(dev, 1,
4462 &sandybridge_display_wm_info, latency,
4463 &sandybridge_cursor_wm_info, latency,
4464 &plane_wm, &cursor_wm)) {
4465 I915_WRITE(WM0_PIPEB_ILK,
4466 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4467 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4468 " plane %d, cursor: %d\n",
4469 plane_wm, cursor_wm);
4474 * Calculate and update the self-refresh watermark only when one
4475 * display plane is used.
4477 * SNB support 3 levels of watermark.
4479 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4480 * and disabled in the descending order
4483 I915_WRITE(WM3_LP_ILK, 0);
4484 I915_WRITE(WM2_LP_ILK, 0);
4485 I915_WRITE(WM1_LP_ILK, 0);
4487 if (!single_plane_enabled(enabled))
4489 enabled = ffs(enabled) - 1;
4492 if (!ironlake_compute_srwm(dev, 1, enabled,
4493 SNB_READ_WM1_LATENCY() * 500,
4494 &sandybridge_display_srwm_info,
4495 &sandybridge_cursor_srwm_info,
4496 &fbc_wm, &plane_wm, &cursor_wm))
4499 I915_WRITE(WM1_LP_ILK,
4501 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4502 (fbc_wm << WM1_LP_FBC_SHIFT) |
4503 (plane_wm << WM1_LP_SR_SHIFT) |
4507 if (!ironlake_compute_srwm(dev, 2, enabled,
4508 SNB_READ_WM2_LATENCY() * 500,
4509 &sandybridge_display_srwm_info,
4510 &sandybridge_cursor_srwm_info,
4511 &fbc_wm, &plane_wm, &cursor_wm))
4514 I915_WRITE(WM2_LP_ILK,
4516 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4517 (fbc_wm << WM1_LP_FBC_SHIFT) |
4518 (plane_wm << WM1_LP_SR_SHIFT) |
4522 if (!ironlake_compute_srwm(dev, 3, enabled,
4523 SNB_READ_WM3_LATENCY() * 500,
4524 &sandybridge_display_srwm_info,
4525 &sandybridge_cursor_srwm_info,
4526 &fbc_wm, &plane_wm, &cursor_wm))
4529 I915_WRITE(WM3_LP_ILK,
4531 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4532 (fbc_wm << WM1_LP_FBC_SHIFT) |
4533 (plane_wm << WM1_LP_SR_SHIFT) |
4538 * intel_update_watermarks - update FIFO watermark values based on current modes
4540 * Calculate watermark values for the various WM regs based on current mode
4541 * and plane configuration.
4543 * There are several cases to deal with here:
4544 * - normal (i.e. non-self-refresh)
4545 * - self-refresh (SR) mode
4546 * - lines are large relative to FIFO size (buffer can hold up to 2)
4547 * - lines are small relative to FIFO size (buffer can hold more than 2
4548 * lines), so need to account for TLB latency
4550 * The normal calculation is:
4551 * watermark = dotclock * bytes per pixel * latency
4552 * where latency is platform & configuration dependent (we assume pessimal
4555 * The SR calculation is:
4556 * watermark = (trunc(latency/line time)+1) * surface width *
4559 * line time = htotal / dotclock
4560 * surface width = hdisplay for normal plane and 64 for cursor
4561 * and latency is assumed to be high, as above.
4563 * The final value programmed to the register should always be rounded up,
4564 * and include an extra 2 entries to account for clock crossings.
4566 * We don't use the sprite, so we can ignore that. And on Crestline we have
4567 * to set the non-SR watermarks to 8.
4569 static void intel_update_watermarks(struct drm_device *dev)
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4573 if (dev_priv->display.update_wm)
4574 dev_priv->display.update_wm(dev);
4577 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4579 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4580 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4584 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4585 * @crtc: CRTC structure
4587 * A pipe may be connected to one or more outputs. Based on the depth of the
4588 * attached framebuffer, choose a good color depth to use on the pipe.
4590 * If possible, match the pipe depth to the fb depth. In some cases, this
4591 * isn't ideal, because the connected output supports a lesser or restricted
4592 * set of depths. Resolve that here:
4593 * LVDS typically supports only 6bpc, so clamp down in that case
4594 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4595 * Displays may support a restricted set as well, check EDID and clamp as
4599 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4600 * true if they don't match).
4602 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4603 unsigned int *pipe_bpp)
4605 struct drm_device *dev = crtc->dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 struct drm_encoder *encoder;
4608 struct drm_connector *connector;
4609 unsigned int display_bpc = UINT_MAX, bpc;
4611 /* Walk the encoders & connectors on this crtc, get min bpc */
4612 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4613 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4615 if (encoder->crtc != crtc)
4618 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4619 unsigned int lvds_bpc;
4621 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4627 if (lvds_bpc < display_bpc) {
4628 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4629 display_bpc = lvds_bpc;
4634 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4635 /* Use VBT settings if we have an eDP panel */
4636 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4638 if (edp_bpc < display_bpc) {
4639 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4640 display_bpc = edp_bpc;
4645 /* Not one of the known troublemakers, check the EDID */
4646 list_for_each_entry(connector, &dev->mode_config.connector_list,
4648 if (connector->encoder != encoder)
4651 /* Don't use an invalid EDID bpc value */
4652 if (connector->display_info.bpc &&
4653 connector->display_info.bpc < display_bpc) {
4654 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4655 display_bpc = connector->display_info.bpc;
4660 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4661 * through, clamp it down. (Note: >12bpc will be caught below.)
4663 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4664 if (display_bpc > 8 && display_bpc < 12) {
4665 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4668 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4675 * We could just drive the pipe at the highest bpc all the time and
4676 * enable dithering as needed, but that costs bandwidth. So choose
4677 * the minimum value that expresses the full color range of the fb but
4678 * also stays within the max display bpc discovered above.
4681 switch (crtc->fb->depth) {
4683 bpc = 8; /* since we go through a colormap */
4687 bpc = 6; /* min is 18bpp */
4690 bpc = min((unsigned int)8, display_bpc);
4693 bpc = min((unsigned int)10, display_bpc);
4696 bpc = min((unsigned int)12, display_bpc);
4699 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4700 bpc = min((unsigned int)8, display_bpc);
4704 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4707 *pipe_bpp = bpc * 3;
4709 return display_bpc != bpc;
4712 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4713 struct drm_display_mode *mode,
4714 struct drm_display_mode *adjusted_mode,
4716 struct drm_framebuffer *old_fb)
4718 struct drm_device *dev = crtc->dev;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4721 int pipe = intel_crtc->pipe;
4722 int plane = intel_crtc->plane;
4723 int refclk, num_connectors = 0;
4724 intel_clock_t clock, reduced_clock;
4725 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4726 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4727 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4728 struct drm_mode_config *mode_config = &dev->mode_config;
4729 struct intel_encoder *encoder;
4730 const intel_limit_t *limit;
4735 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4736 if (encoder->base.crtc != crtc)
4739 switch (encoder->type) {
4740 case INTEL_OUTPUT_LVDS:
4743 case INTEL_OUTPUT_SDVO:
4744 case INTEL_OUTPUT_HDMI:
4746 if (encoder->needs_tv_clock)
4749 case INTEL_OUTPUT_DVO:
4752 case INTEL_OUTPUT_TVOUT:
4755 case INTEL_OUTPUT_ANALOG:
4758 case INTEL_OUTPUT_DISPLAYPORT:
4766 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4767 refclk = dev_priv->lvds_ssc_freq * 1000;
4768 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4770 } else if (!IS_GEN2(dev)) {
4777 * Returns a set of divisors for the desired target clock with the given
4778 * refclk, or FALSE. The returned values represent the clock equation:
4779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4781 limit = intel_limit(crtc, refclk);
4782 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4784 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4788 /* Ensure that the cursor is valid for the new mode before changing... */
4789 intel_crtc_update_cursor(crtc, true);
4791 if (is_lvds && dev_priv->lvds_downclock_avail) {
4792 has_reduced_clock = limit->find_pll(limit, crtc,
4793 dev_priv->lvds_downclock,
4796 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4798 * If the different P is found, it means that we can't
4799 * switch the display clock by using the FP0/FP1.
4800 * In such case we will disable the LVDS downclock
4803 DRM_DEBUG_KMS("Different P is found for "
4804 "LVDS clock/downclock\n");
4805 has_reduced_clock = 0;
4808 /* SDVO TV has fixed PLL values depend on its clock range,
4809 this mirrors vbios setting. */
4810 if (is_sdvo && is_tv) {
4811 if (adjusted_mode->clock >= 100000
4812 && adjusted_mode->clock < 140500) {
4818 } else if (adjusted_mode->clock >= 140500
4819 && adjusted_mode->clock <= 200000) {
4828 if (IS_PINEVIEW(dev)) {
4829 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4830 if (has_reduced_clock)
4831 fp2 = (1 << reduced_clock.n) << 16 |
4832 reduced_clock.m1 << 8 | reduced_clock.m2;
4834 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4835 if (has_reduced_clock)
4836 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4840 dpll = DPLL_VGA_MODE_DIS;
4842 if (!IS_GEN2(dev)) {
4844 dpll |= DPLLB_MODE_LVDS;
4846 dpll |= DPLLB_MODE_DAC_SERIAL;
4848 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4849 if (pixel_multiplier > 1) {
4850 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4851 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4853 dpll |= DPLL_DVO_HIGH_SPEED;
4856 dpll |= DPLL_DVO_HIGH_SPEED;
4858 /* compute bitmask from p1 value */
4859 if (IS_PINEVIEW(dev))
4860 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4862 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4863 if (IS_G4X(dev) && has_reduced_clock)
4864 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4868 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4871 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4874 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4877 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4880 if (INTEL_INFO(dev)->gen >= 4)
4881 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4884 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4887 dpll |= PLL_P1_DIVIDE_BY_TWO;
4889 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4891 dpll |= PLL_P2_DIVIDE_BY_4;
4895 if (is_sdvo && is_tv)
4896 dpll |= PLL_REF_INPUT_TVCLKINBC;
4898 /* XXX: just matching BIOS for now */
4899 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4901 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4902 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4904 dpll |= PLL_REF_INPUT_DREFCLK;
4906 /* setup pipeconf */
4907 pipeconf = I915_READ(PIPECONF(pipe));
4909 /* Set up the display plane register */
4910 dspcntr = DISPPLANE_GAMMA_ENABLE;
4912 /* Ironlake's plane is forced to pipe, bit 24 is to
4913 enable color space conversion */
4915 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4917 dspcntr |= DISPPLANE_SEL_PIPE_B;
4919 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4920 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4923 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4927 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4928 pipeconf |= PIPECONF_DOUBLE_WIDE;
4930 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4933 dpll |= DPLL_VCO_ENABLE;
4935 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4936 drm_mode_debug_printmodeline(mode);
4938 I915_WRITE(FP0(pipe), fp);
4939 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4941 POSTING_READ(DPLL(pipe));
4944 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4945 * This is an exception to the general rule that mode_set doesn't turn
4949 temp = I915_READ(LVDS);
4950 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4952 temp |= LVDS_PIPEB_SELECT;
4954 temp &= ~LVDS_PIPEB_SELECT;
4956 /* set the corresponsding LVDS_BORDER bit */
4957 temp |= dev_priv->lvds_border_bits;
4958 /* Set the B0-B3 data pairs corresponding to whether we're going to
4959 * set the DPLLs for dual-channel mode or not.
4962 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4964 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4966 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4967 * appropriately here, but we need to look more thoroughly into how
4968 * panels behave in the two modes.
4970 /* set the dithering flag on LVDS as needed */
4971 if (INTEL_INFO(dev)->gen >= 4) {
4972 if (dev_priv->lvds_dither)
4973 temp |= LVDS_ENABLE_DITHER;
4975 temp &= ~LVDS_ENABLE_DITHER;
4977 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4978 lvds_sync |= LVDS_HSYNC_POLARITY;
4979 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4980 lvds_sync |= LVDS_VSYNC_POLARITY;
4981 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4983 char flags[2] = "-+";
4984 DRM_INFO("Changing LVDS panel from "
4985 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4986 flags[!(temp & LVDS_HSYNC_POLARITY)],
4987 flags[!(temp & LVDS_VSYNC_POLARITY)],
4988 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4989 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4990 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4993 I915_WRITE(LVDS, temp);
4997 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5000 I915_WRITE(DPLL(pipe), dpll);
5002 /* Wait for the clocks to stabilize. */
5003 POSTING_READ(DPLL(pipe));
5006 if (INTEL_INFO(dev)->gen >= 4) {
5009 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5011 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5015 I915_WRITE(DPLL_MD(pipe), temp);
5017 /* The pixel multiplier can only be updated once the
5018 * DPLL is enabled and the clocks are stable.
5020 * So write it again.
5022 I915_WRITE(DPLL(pipe), dpll);
5025 intel_crtc->lowfreq_avail = false;
5026 if (is_lvds && has_reduced_clock && i915_powersave) {
5027 I915_WRITE(FP1(pipe), fp2);
5028 intel_crtc->lowfreq_avail = true;
5029 if (HAS_PIPE_CXSR(dev)) {
5030 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5031 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5034 I915_WRITE(FP1(pipe), fp);
5035 if (HAS_PIPE_CXSR(dev)) {
5036 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5037 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5041 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5042 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5043 /* the chip adds 2 halflines automatically */
5044 adjusted_mode->crtc_vdisplay -= 1;
5045 adjusted_mode->crtc_vtotal -= 1;
5046 adjusted_mode->crtc_vblank_start -= 1;
5047 adjusted_mode->crtc_vblank_end -= 1;
5048 adjusted_mode->crtc_vsync_end -= 1;
5049 adjusted_mode->crtc_vsync_start -= 1;
5051 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5053 I915_WRITE(HTOTAL(pipe),
5054 (adjusted_mode->crtc_hdisplay - 1) |
5055 ((adjusted_mode->crtc_htotal - 1) << 16));
5056 I915_WRITE(HBLANK(pipe),
5057 (adjusted_mode->crtc_hblank_start - 1) |
5058 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5059 I915_WRITE(HSYNC(pipe),
5060 (adjusted_mode->crtc_hsync_start - 1) |
5061 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5063 I915_WRITE(VTOTAL(pipe),
5064 (adjusted_mode->crtc_vdisplay - 1) |
5065 ((adjusted_mode->crtc_vtotal - 1) << 16));
5066 I915_WRITE(VBLANK(pipe),
5067 (adjusted_mode->crtc_vblank_start - 1) |
5068 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5069 I915_WRITE(VSYNC(pipe),
5070 (adjusted_mode->crtc_vsync_start - 1) |
5071 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5073 /* pipesrc and dspsize control the size that is scaled from,
5074 * which should always be the user's requested size.
5076 I915_WRITE(DSPSIZE(plane),
5077 ((mode->vdisplay - 1) << 16) |
5078 (mode->hdisplay - 1));
5079 I915_WRITE(DSPPOS(plane), 0);
5080 I915_WRITE(PIPESRC(pipe),
5081 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5083 I915_WRITE(PIPECONF(pipe), pipeconf);
5084 POSTING_READ(PIPECONF(pipe));
5085 intel_enable_pipe(dev_priv, pipe, false);
5087 intel_wait_for_vblank(dev, pipe);
5089 I915_WRITE(DSPCNTR(plane), dspcntr);
5090 POSTING_READ(DSPCNTR(plane));
5091 intel_enable_plane(dev_priv, plane, pipe);
5093 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5095 intel_update_watermarks(dev);
5100 static void ironlake_update_pch_refclk(struct drm_device *dev)
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103 struct drm_mode_config *mode_config = &dev->mode_config;
5104 struct drm_crtc *crtc;
5105 struct intel_encoder *encoder;
5106 struct intel_encoder *has_edp_encoder = NULL;
5108 bool has_lvds = false;
5110 /* We need to take the global config into account */
5111 list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5115 list_for_each_entry(encoder, &mode_config->encoder_list,
5117 if (encoder->base.crtc != crtc)
5120 switch (encoder->type) {
5121 case INTEL_OUTPUT_LVDS:
5123 case INTEL_OUTPUT_EDP:
5124 has_edp_encoder = encoder;
5130 /* Ironlake: try to setup display ref clock before DPLL
5131 * enabling. This is only under driver's control after
5132 * PCH B stepping, previous chipset stepping should be
5133 * ignoring this setting.
5135 temp = I915_READ(PCH_DREF_CONTROL);
5136 /* Always enable nonspread source */
5137 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5138 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5139 temp &= ~DREF_SSC_SOURCE_MASK;
5140 temp |= DREF_SSC_SOURCE_ENABLE;
5141 I915_WRITE(PCH_DREF_CONTROL, temp);
5143 POSTING_READ(PCH_DREF_CONTROL);
5146 if (has_edp_encoder) {
5147 if (intel_panel_use_ssc(dev_priv)) {
5148 temp |= DREF_SSC1_ENABLE;
5149 I915_WRITE(PCH_DREF_CONTROL, temp);
5151 POSTING_READ(PCH_DREF_CONTROL);
5154 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5156 /* Enable CPU source on CPU attached eDP */
5157 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5158 if (intel_panel_use_ssc(dev_priv))
5159 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5161 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5163 /* Enable SSC on PCH eDP if needed */
5164 if (intel_panel_use_ssc(dev_priv)) {
5165 DRM_ERROR("enabling SSC on PCH\n");
5166 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5169 I915_WRITE(PCH_DREF_CONTROL, temp);
5170 POSTING_READ(PCH_DREF_CONTROL);
5175 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5176 struct drm_display_mode *mode,
5177 struct drm_display_mode *adjusted_mode,
5179 struct drm_framebuffer *old_fb)
5181 struct drm_device *dev = crtc->dev;
5182 struct drm_i915_private *dev_priv = dev->dev_private;
5183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5184 int pipe = intel_crtc->pipe;
5185 int plane = intel_crtc->plane;
5186 int refclk, num_connectors = 0;
5187 intel_clock_t clock, reduced_clock;
5188 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5189 bool ok, has_reduced_clock = false, is_sdvo = false;
5190 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5191 struct intel_encoder *has_edp_encoder = NULL;
5192 struct drm_mode_config *mode_config = &dev->mode_config;
5193 struct intel_encoder *encoder;
5194 const intel_limit_t *limit;
5196 struct fdi_m_n m_n = {0};
5199 int target_clock, pixel_multiplier, lane, link_bw, factor;
5200 unsigned int pipe_bpp;
5203 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5204 if (encoder->base.crtc != crtc)
5207 switch (encoder->type) {
5208 case INTEL_OUTPUT_LVDS:
5211 case INTEL_OUTPUT_SDVO:
5212 case INTEL_OUTPUT_HDMI:
5214 if (encoder->needs_tv_clock)
5217 case INTEL_OUTPUT_TVOUT:
5220 case INTEL_OUTPUT_ANALOG:
5223 case INTEL_OUTPUT_DISPLAYPORT:
5226 case INTEL_OUTPUT_EDP:
5227 has_edp_encoder = encoder;
5234 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5235 refclk = dev_priv->lvds_ssc_freq * 1000;
5236 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5240 if (!has_edp_encoder ||
5241 intel_encoder_is_pch_edp(&has_edp_encoder->base))
5242 refclk = 120000; /* 120Mhz refclk */
5246 * Returns a set of divisors for the desired target clock with the given
5247 * refclk, or FALSE. The returned values represent the clock equation:
5248 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5250 limit = intel_limit(crtc, refclk);
5251 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5253 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5257 /* Ensure that the cursor is valid for the new mode before changing... */
5258 intel_crtc_update_cursor(crtc, true);
5260 if (is_lvds && dev_priv->lvds_downclock_avail) {
5261 has_reduced_clock = limit->find_pll(limit, crtc,
5262 dev_priv->lvds_downclock,
5265 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5267 * If the different P is found, it means that we can't
5268 * switch the display clock by using the FP0/FP1.
5269 * In such case we will disable the LVDS downclock
5272 DRM_DEBUG_KMS("Different P is found for "
5273 "LVDS clock/downclock\n");
5274 has_reduced_clock = 0;
5277 /* SDVO TV has fixed PLL values depend on its clock range,
5278 this mirrors vbios setting. */
5279 if (is_sdvo && is_tv) {
5280 if (adjusted_mode->clock >= 100000
5281 && adjusted_mode->clock < 140500) {
5287 } else if (adjusted_mode->clock >= 140500
5288 && adjusted_mode->clock <= 200000) {
5298 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5300 /* CPU eDP doesn't require FDI link, so just set DP M/N
5301 according to current link config */
5302 if (has_edp_encoder &&
5303 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5304 target_clock = mode->clock;
5305 intel_edp_link_config(has_edp_encoder,
5308 /* [e]DP over FDI requires target mode clock
5309 instead of link clock */
5310 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5311 target_clock = mode->clock;
5313 target_clock = adjusted_mode->clock;
5315 /* FDI is a binary signal running at ~2.7GHz, encoding
5316 * each output octet as 10 bits. The actual frequency
5317 * is stored as a divider into a 100MHz clock, and the
5318 * mode pixel clock is stored in units of 1KHz.
5319 * Hence the bw of each lane in terms of the mode signal
5322 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5325 /* determine panel color depth */
5326 temp = I915_READ(PIPECONF(pipe));
5327 temp &= ~PIPE_BPC_MASK;
5328 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5343 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5350 intel_crtc->bpp = pipe_bpp;
5351 I915_WRITE(PIPECONF(pipe), temp);
5355 * Account for spread spectrum to avoid
5356 * oversubscribing the link. Max center spread
5357 * is 2.5%; use 5% for safety's sake.
5359 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5360 lane = bps / (link_bw * 8) + 1;
5363 intel_crtc->fdi_lanes = lane;
5365 if (pixel_multiplier > 1)
5366 link_bw *= pixel_multiplier;
5367 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5370 ironlake_update_pch_refclk(dev);
5372 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5373 if (has_reduced_clock)
5374 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5377 /* Enable autotuning of the PLL clock (if permissible) */
5380 if ((intel_panel_use_ssc(dev_priv) &&
5381 dev_priv->lvds_ssc_freq == 100) ||
5382 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5384 } else if (is_sdvo && is_tv)
5387 if (clock.m < factor * clock.n)
5393 dpll |= DPLLB_MODE_LVDS;
5395 dpll |= DPLLB_MODE_DAC_SERIAL;
5397 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5398 if (pixel_multiplier > 1) {
5399 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5401 dpll |= DPLL_DVO_HIGH_SPEED;
5403 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5404 dpll |= DPLL_DVO_HIGH_SPEED;
5406 /* compute bitmask from p1 value */
5407 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5409 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5413 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5416 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5419 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5422 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5426 if (is_sdvo && is_tv)
5427 dpll |= PLL_REF_INPUT_TVCLKINBC;
5429 /* XXX: just matching BIOS for now */
5430 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5432 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5433 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5435 dpll |= PLL_REF_INPUT_DREFCLK;
5437 /* setup pipeconf */
5438 pipeconf = I915_READ(PIPECONF(pipe));
5440 /* Set up the display plane register */
5441 dspcntr = DISPPLANE_GAMMA_ENABLE;
5443 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5444 drm_mode_debug_printmodeline(mode);
5446 /* PCH eDP needs FDI, but CPU eDP does not */
5447 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5448 I915_WRITE(PCH_FP0(pipe), fp);
5449 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5451 POSTING_READ(PCH_DPLL(pipe));
5455 /* enable transcoder DPLL */
5456 if (HAS_PCH_CPT(dev)) {
5457 temp = I915_READ(PCH_DPLL_SEL);
5460 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5463 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5466 /* FIXME: manage transcoder PLLs? */
5467 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5472 I915_WRITE(PCH_DPLL_SEL, temp);
5474 POSTING_READ(PCH_DPLL_SEL);
5478 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5479 * This is an exception to the general rule that mode_set doesn't turn
5483 temp = I915_READ(PCH_LVDS);
5484 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5486 if (HAS_PCH_CPT(dev))
5487 temp |= PORT_TRANS_B_SEL_CPT;
5489 temp |= LVDS_PIPEB_SELECT;
5491 if (HAS_PCH_CPT(dev))
5492 temp &= ~PORT_TRANS_SEL_MASK;
5494 temp &= ~LVDS_PIPEB_SELECT;
5496 /* set the corresponsding LVDS_BORDER bit */
5497 temp |= dev_priv->lvds_border_bits;
5498 /* Set the B0-B3 data pairs corresponding to whether we're going to
5499 * set the DPLLs for dual-channel mode or not.
5502 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5504 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5506 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5507 * appropriately here, but we need to look more thoroughly into how
5508 * panels behave in the two modes.
5510 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5511 lvds_sync |= LVDS_HSYNC_POLARITY;
5512 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5513 lvds_sync |= LVDS_VSYNC_POLARITY;
5514 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5516 char flags[2] = "-+";
5517 DRM_INFO("Changing LVDS panel from "
5518 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5519 flags[!(temp & LVDS_HSYNC_POLARITY)],
5520 flags[!(temp & LVDS_VSYNC_POLARITY)],
5521 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5522 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5523 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5526 I915_WRITE(PCH_LVDS, temp);
5529 pipeconf &= ~PIPECONF_DITHER_EN;
5530 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5531 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5532 pipeconf |= PIPECONF_DITHER_EN;
5533 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5535 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5536 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5538 /* For non-DP output, clear any trans DP clock recovery setting.*/
5539 I915_WRITE(TRANSDATA_M1(pipe), 0);
5540 I915_WRITE(TRANSDATA_N1(pipe), 0);
5541 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5542 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5545 if (!has_edp_encoder ||
5546 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5547 I915_WRITE(PCH_DPLL(pipe), dpll);
5549 /* Wait for the clocks to stabilize. */
5550 POSTING_READ(PCH_DPLL(pipe));
5553 /* The pixel multiplier can only be updated once the
5554 * DPLL is enabled and the clocks are stable.
5556 * So write it again.
5558 I915_WRITE(PCH_DPLL(pipe), dpll);
5561 intel_crtc->lowfreq_avail = false;
5562 if (is_lvds && has_reduced_clock && i915_powersave) {
5563 I915_WRITE(PCH_FP1(pipe), fp2);
5564 intel_crtc->lowfreq_avail = true;
5565 if (HAS_PIPE_CXSR(dev)) {
5566 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5567 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5570 I915_WRITE(PCH_FP1(pipe), fp);
5571 if (HAS_PIPE_CXSR(dev)) {
5572 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5573 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5577 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5578 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5579 /* the chip adds 2 halflines automatically */
5580 adjusted_mode->crtc_vdisplay -= 1;
5581 adjusted_mode->crtc_vtotal -= 1;
5582 adjusted_mode->crtc_vblank_start -= 1;
5583 adjusted_mode->crtc_vblank_end -= 1;
5584 adjusted_mode->crtc_vsync_end -= 1;
5585 adjusted_mode->crtc_vsync_start -= 1;
5587 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5589 I915_WRITE(HTOTAL(pipe),
5590 (adjusted_mode->crtc_hdisplay - 1) |
5591 ((adjusted_mode->crtc_htotal - 1) << 16));
5592 I915_WRITE(HBLANK(pipe),
5593 (adjusted_mode->crtc_hblank_start - 1) |
5594 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5595 I915_WRITE(HSYNC(pipe),
5596 (adjusted_mode->crtc_hsync_start - 1) |
5597 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5599 I915_WRITE(VTOTAL(pipe),
5600 (adjusted_mode->crtc_vdisplay - 1) |
5601 ((adjusted_mode->crtc_vtotal - 1) << 16));
5602 I915_WRITE(VBLANK(pipe),
5603 (adjusted_mode->crtc_vblank_start - 1) |
5604 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5605 I915_WRITE(VSYNC(pipe),
5606 (adjusted_mode->crtc_vsync_start - 1) |
5607 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5609 /* pipesrc controls the size that is scaled from, which should
5610 * always be the user's requested size.
5612 I915_WRITE(PIPESRC(pipe),
5613 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5615 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5616 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5617 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5618 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5620 if (has_edp_encoder &&
5621 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5622 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5625 I915_WRITE(PIPECONF(pipe), pipeconf);
5626 POSTING_READ(PIPECONF(pipe));
5628 intel_wait_for_vblank(dev, pipe);
5631 /* enable address swizzle for tiling buffer */
5632 temp = I915_READ(DISP_ARB_CTL);
5633 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5636 I915_WRITE(DSPCNTR(plane), dspcntr);
5637 POSTING_READ(DSPCNTR(plane));
5639 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5641 intel_update_watermarks(dev);
5646 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5647 struct drm_display_mode *mode,
5648 struct drm_display_mode *adjusted_mode,
5650 struct drm_framebuffer *old_fb)
5652 struct drm_device *dev = crtc->dev;
5653 struct drm_i915_private *dev_priv = dev->dev_private;
5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 int pipe = intel_crtc->pipe;
5658 drm_vblank_pre_modeset(dev, pipe);
5660 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5663 drm_vblank_post_modeset(dev, pipe);
5665 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5670 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5671 void intel_crtc_load_lut(struct drm_crtc *crtc)
5673 struct drm_device *dev = crtc->dev;
5674 struct drm_i915_private *dev_priv = dev->dev_private;
5675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5676 int palreg = PALETTE(intel_crtc->pipe);
5679 /* The clocks have to be on to load the palette. */
5683 /* use legacy palette for Ironlake */
5684 if (HAS_PCH_SPLIT(dev))
5685 palreg = LGC_PALETTE(intel_crtc->pipe);
5687 for (i = 0; i < 256; i++) {
5688 I915_WRITE(palreg + 4 * i,
5689 (intel_crtc->lut_r[i] << 16) |
5690 (intel_crtc->lut_g[i] << 8) |
5691 intel_crtc->lut_b[i]);
5695 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5697 struct drm_device *dev = crtc->dev;
5698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5700 bool visible = base != 0;
5703 if (intel_crtc->cursor_visible == visible)
5706 cntl = I915_READ(_CURACNTR);
5708 /* On these chipsets we can only modify the base whilst
5709 * the cursor is disabled.
5711 I915_WRITE(_CURABASE, base);
5713 cntl &= ~(CURSOR_FORMAT_MASK);
5714 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5715 cntl |= CURSOR_ENABLE |
5716 CURSOR_GAMMA_ENABLE |
5719 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5720 I915_WRITE(_CURACNTR, cntl);
5722 intel_crtc->cursor_visible = visible;
5725 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5727 struct drm_device *dev = crtc->dev;
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5730 int pipe = intel_crtc->pipe;
5731 bool visible = base != 0;
5733 if (intel_crtc->cursor_visible != visible) {
5734 uint32_t cntl = I915_READ(CURCNTR(pipe));
5736 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5737 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5738 cntl |= pipe << 28; /* Connect to correct pipe */
5740 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5741 cntl |= CURSOR_MODE_DISABLE;
5743 I915_WRITE(CURCNTR(pipe), cntl);
5745 intel_crtc->cursor_visible = visible;
5747 /* and commit changes on next vblank */
5748 I915_WRITE(CURBASE(pipe), base);
5751 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5752 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5755 struct drm_device *dev = crtc->dev;
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758 int pipe = intel_crtc->pipe;
5759 int x = intel_crtc->cursor_x;
5760 int y = intel_crtc->cursor_y;
5766 if (on && crtc->enabled && crtc->fb) {
5767 base = intel_crtc->cursor_addr;
5768 if (x > (int) crtc->fb->width)
5771 if (y > (int) crtc->fb->height)
5777 if (x + intel_crtc->cursor_width < 0)
5780 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5783 pos |= x << CURSOR_X_SHIFT;
5786 if (y + intel_crtc->cursor_height < 0)
5789 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5792 pos |= y << CURSOR_Y_SHIFT;
5794 visible = base != 0;
5795 if (!visible && !intel_crtc->cursor_visible)
5798 I915_WRITE(CURPOS(pipe), pos);
5799 if (IS_845G(dev) || IS_I865G(dev))
5800 i845_update_cursor(crtc, base);
5802 i9xx_update_cursor(crtc, base);
5805 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5808 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5809 struct drm_file *file,
5811 uint32_t width, uint32_t height)
5813 struct drm_device *dev = crtc->dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5816 struct drm_i915_gem_object *obj;
5820 DRM_DEBUG_KMS("\n");
5822 /* if we want to turn off the cursor ignore width and height */
5824 DRM_DEBUG_KMS("cursor off\n");
5827 mutex_lock(&dev->struct_mutex);
5831 /* Currently we only support 64x64 cursors */
5832 if (width != 64 || height != 64) {
5833 DRM_ERROR("we currently only support 64x64 cursors\n");
5837 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5838 if (&obj->base == NULL)
5841 if (obj->base.size < width * height * 4) {
5842 DRM_ERROR("buffer is to small\n");
5847 /* we only need to pin inside GTT if cursor is non-phy */
5848 mutex_lock(&dev->struct_mutex);
5849 if (!dev_priv->info->cursor_needs_physical) {
5850 if (obj->tiling_mode) {
5851 DRM_ERROR("cursor cannot be tiled\n");
5856 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5858 DRM_ERROR("failed to move cursor bo into the GTT\n");
5862 ret = i915_gem_object_put_fence(obj);
5864 DRM_ERROR("failed to release fence for cursor");
5868 addr = obj->gtt_offset;
5870 int align = IS_I830(dev) ? 16 * 1024 : 256;
5871 ret = i915_gem_attach_phys_object(dev, obj,
5872 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5875 DRM_ERROR("failed to attach phys object\n");
5878 addr = obj->phys_obj->handle->busaddr;
5882 I915_WRITE(CURSIZE, (height << 12) | width);
5885 if (intel_crtc->cursor_bo) {
5886 if (dev_priv->info->cursor_needs_physical) {
5887 if (intel_crtc->cursor_bo != obj)
5888 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5890 i915_gem_object_unpin(intel_crtc->cursor_bo);
5891 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5894 mutex_unlock(&dev->struct_mutex);
5896 intel_crtc->cursor_addr = addr;
5897 intel_crtc->cursor_bo = obj;
5898 intel_crtc->cursor_width = width;
5899 intel_crtc->cursor_height = height;
5901 intel_crtc_update_cursor(crtc, true);
5905 i915_gem_object_unpin(obj);
5907 mutex_unlock(&dev->struct_mutex);
5909 drm_gem_object_unreference_unlocked(&obj->base);
5913 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5917 intel_crtc->cursor_x = x;
5918 intel_crtc->cursor_y = y;
5920 intel_crtc_update_cursor(crtc, true);
5925 /** Sets the color ramps on behalf of RandR */
5926 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5927 u16 blue, int regno)
5929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931 intel_crtc->lut_r[regno] = red >> 8;
5932 intel_crtc->lut_g[regno] = green >> 8;
5933 intel_crtc->lut_b[regno] = blue >> 8;
5936 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5937 u16 *blue, int regno)
5939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5941 *red = intel_crtc->lut_r[regno] << 8;
5942 *green = intel_crtc->lut_g[regno] << 8;
5943 *blue = intel_crtc->lut_b[regno] << 8;
5946 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5947 u16 *blue, uint32_t start, uint32_t size)
5949 int end = (start + size > 256) ? 256 : start + size, i;
5950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952 for (i = start; i < end; i++) {
5953 intel_crtc->lut_r[i] = red[i] >> 8;
5954 intel_crtc->lut_g[i] = green[i] >> 8;
5955 intel_crtc->lut_b[i] = blue[i] >> 8;
5958 intel_crtc_load_lut(crtc);
5962 * Get a pipe with a simple mode set on it for doing load-based monitor
5965 * It will be up to the load-detect code to adjust the pipe as appropriate for
5966 * its requirements. The pipe will be connected to no other encoders.
5968 * Currently this code will only succeed if there is a pipe with no encoders
5969 * configured for it. In the future, it could choose to temporarily disable
5970 * some outputs to free up a pipe for its use.
5972 * \return crtc, or NULL if no pipes are available.
5975 /* VESA 640x480x72Hz mode to set on the pipe */
5976 static struct drm_display_mode load_detect_mode = {
5977 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5978 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5981 static struct drm_framebuffer *
5982 intel_framebuffer_create(struct drm_device *dev,
5983 struct drm_mode_fb_cmd *mode_cmd,
5984 struct drm_i915_gem_object *obj)
5986 struct intel_framebuffer *intel_fb;
5989 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5991 drm_gem_object_unreference_unlocked(&obj->base);
5992 return ERR_PTR(-ENOMEM);
5995 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5997 drm_gem_object_unreference_unlocked(&obj->base);
5999 return ERR_PTR(ret);
6002 return &intel_fb->base;
6006 intel_framebuffer_pitch_for_width(int width, int bpp)
6008 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6009 return ALIGN(pitch, 64);
6013 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6015 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6016 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6019 static struct drm_framebuffer *
6020 intel_framebuffer_create_for_mode(struct drm_device *dev,
6021 struct drm_display_mode *mode,
6024 struct drm_i915_gem_object *obj;
6025 struct drm_mode_fb_cmd mode_cmd;
6027 obj = i915_gem_alloc_object(dev,
6028 intel_framebuffer_size_for_mode(mode, bpp));
6030 return ERR_PTR(-ENOMEM);
6032 mode_cmd.width = mode->hdisplay;
6033 mode_cmd.height = mode->vdisplay;
6034 mode_cmd.depth = depth;
6036 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6038 return intel_framebuffer_create(dev, &mode_cmd, obj);
6041 static struct drm_framebuffer *
6042 mode_fits_in_fbdev(struct drm_device *dev,
6043 struct drm_display_mode *mode)
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 struct drm_i915_gem_object *obj;
6047 struct drm_framebuffer *fb;
6049 if (dev_priv->fbdev == NULL)
6052 obj = dev_priv->fbdev->ifb.obj;
6056 fb = &dev_priv->fbdev->ifb.base;
6057 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6058 fb->bits_per_pixel))
6061 if (obj->base.size < mode->vdisplay * fb->pitch)
6067 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6068 struct drm_connector *connector,
6069 struct drm_display_mode *mode,
6070 struct intel_load_detect_pipe *old)
6072 struct intel_crtc *intel_crtc;
6073 struct drm_crtc *possible_crtc;
6074 struct drm_encoder *encoder = &intel_encoder->base;
6075 struct drm_crtc *crtc = NULL;
6076 struct drm_device *dev = encoder->dev;
6077 struct drm_framebuffer *old_fb;
6080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6081 connector->base.id, drm_get_connector_name(connector),
6082 encoder->base.id, drm_get_encoder_name(encoder));
6085 * Algorithm gets a little messy:
6087 * - if the connector already has an assigned crtc, use it (but make
6088 * sure it's on first)
6090 * - try to find the first unused crtc that can drive this connector,
6091 * and use that if we find one
6094 /* See if we already have a CRTC for this connector */
6095 if (encoder->crtc) {
6096 crtc = encoder->crtc;
6098 intel_crtc = to_intel_crtc(crtc);
6099 old->dpms_mode = intel_crtc->dpms_mode;
6100 old->load_detect_temp = false;
6102 /* Make sure the crtc and connector are running */
6103 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6104 struct drm_encoder_helper_funcs *encoder_funcs;
6105 struct drm_crtc_helper_funcs *crtc_funcs;
6107 crtc_funcs = crtc->helper_private;
6108 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6110 encoder_funcs = encoder->helper_private;
6111 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6117 /* Find an unused one (if possible) */
6118 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6120 if (!(encoder->possible_crtcs & (1 << i)))
6122 if (!possible_crtc->enabled) {
6123 crtc = possible_crtc;
6129 * If we didn't find an unused CRTC, don't use any.
6132 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6136 encoder->crtc = crtc;
6137 connector->encoder = encoder;
6139 intel_crtc = to_intel_crtc(crtc);
6140 old->dpms_mode = intel_crtc->dpms_mode;
6141 old->load_detect_temp = true;
6142 old->release_fb = NULL;
6145 mode = &load_detect_mode;
6149 /* We need a framebuffer large enough to accommodate all accesses
6150 * that the plane may generate whilst we perform load detection.
6151 * We can not rely on the fbcon either being present (we get called
6152 * during its initialisation to detect all boot displays, or it may
6153 * not even exist) or that it is large enough to satisfy the
6156 crtc->fb = mode_fits_in_fbdev(dev, mode);
6157 if (crtc->fb == NULL) {
6158 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6159 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6160 old->release_fb = crtc->fb;
6162 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6163 if (IS_ERR(crtc->fb)) {
6164 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6169 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6170 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6171 if (old->release_fb)
6172 old->release_fb->funcs->destroy(old->release_fb);
6177 /* let the connector get through one full cycle before testing */
6178 intel_wait_for_vblank(dev, intel_crtc->pipe);
6183 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6184 struct drm_connector *connector,
6185 struct intel_load_detect_pipe *old)
6187 struct drm_encoder *encoder = &intel_encoder->base;
6188 struct drm_device *dev = encoder->dev;
6189 struct drm_crtc *crtc = encoder->crtc;
6190 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6191 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6193 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6194 connector->base.id, drm_get_connector_name(connector),
6195 encoder->base.id, drm_get_encoder_name(encoder));
6197 if (old->load_detect_temp) {
6198 connector->encoder = NULL;
6199 drm_helper_disable_unused_functions(dev);
6201 if (old->release_fb)
6202 old->release_fb->funcs->destroy(old->release_fb);
6207 /* Switch crtc and encoder back off if necessary */
6208 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6209 encoder_funcs->dpms(encoder, old->dpms_mode);
6210 crtc_funcs->dpms(crtc, old->dpms_mode);
6214 /* Returns the clock of the currently programmed mode of the given pipe. */
6215 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6217 struct drm_i915_private *dev_priv = dev->dev_private;
6218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6219 int pipe = intel_crtc->pipe;
6220 u32 dpll = I915_READ(DPLL(pipe));
6222 intel_clock_t clock;
6224 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6225 fp = I915_READ(FP0(pipe));
6227 fp = I915_READ(FP1(pipe));
6229 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6230 if (IS_PINEVIEW(dev)) {
6231 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6232 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6234 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6235 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6238 if (!IS_GEN2(dev)) {
6239 if (IS_PINEVIEW(dev))
6240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6241 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6243 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6244 DPLL_FPA01_P1_POST_DIV_SHIFT);
6246 switch (dpll & DPLL_MODE_MASK) {
6247 case DPLLB_MODE_DAC_SERIAL:
6248 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6251 case DPLLB_MODE_LVDS:
6252 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6256 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6257 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6261 /* XXX: Handle the 100Mhz refclk */
6262 intel_clock(dev, 96000, &clock);
6264 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6267 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6268 DPLL_FPA01_P1_POST_DIV_SHIFT);
6271 if ((dpll & PLL_REF_INPUT_MASK) ==
6272 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6273 /* XXX: might not be 66MHz */
6274 intel_clock(dev, 66000, &clock);
6276 intel_clock(dev, 48000, &clock);
6278 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6281 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6282 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6284 if (dpll & PLL_P2_DIVIDE_BY_4)
6289 intel_clock(dev, 48000, &clock);
6293 /* XXX: It would be nice to validate the clocks, but we can't reuse
6294 * i830PllIsValid() because it relies on the xf86_config connector
6295 * configuration being accurate, which it isn't necessarily.
6301 /** Returns the currently programmed mode of the given pipe. */
6302 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6303 struct drm_crtc *crtc)
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307 int pipe = intel_crtc->pipe;
6308 struct drm_display_mode *mode;
6309 int htot = I915_READ(HTOTAL(pipe));
6310 int hsync = I915_READ(HSYNC(pipe));
6311 int vtot = I915_READ(VTOTAL(pipe));
6312 int vsync = I915_READ(VSYNC(pipe));
6314 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6318 mode->clock = intel_crtc_clock_get(dev, crtc);
6319 mode->hdisplay = (htot & 0xffff) + 1;
6320 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6321 mode->hsync_start = (hsync & 0xffff) + 1;
6322 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6323 mode->vdisplay = (vtot & 0xffff) + 1;
6324 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6325 mode->vsync_start = (vsync & 0xffff) + 1;
6326 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6328 drm_mode_set_name(mode);
6329 drm_mode_set_crtcinfo(mode, 0);
6334 #define GPU_IDLE_TIMEOUT 500 /* ms */
6336 /* When this timer fires, we've been idle for awhile */
6337 static void intel_gpu_idle_timer(unsigned long arg)
6339 struct drm_device *dev = (struct drm_device *)arg;
6340 drm_i915_private_t *dev_priv = dev->dev_private;
6342 if (!list_empty(&dev_priv->mm.active_list)) {
6343 /* Still processing requests, so just re-arm the timer. */
6344 mod_timer(&dev_priv->idle_timer, jiffies +
6345 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6349 dev_priv->busy = false;
6350 queue_work(dev_priv->wq, &dev_priv->idle_work);
6353 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6355 static void intel_crtc_idle_timer(unsigned long arg)
6357 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6358 struct drm_crtc *crtc = &intel_crtc->base;
6359 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6360 struct intel_framebuffer *intel_fb;
6362 intel_fb = to_intel_framebuffer(crtc->fb);
6363 if (intel_fb && intel_fb->obj->active) {
6364 /* The framebuffer is still being accessed by the GPU. */
6365 mod_timer(&intel_crtc->idle_timer, jiffies +
6366 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6370 intel_crtc->busy = false;
6371 queue_work(dev_priv->wq, &dev_priv->idle_work);
6374 static void intel_increase_pllclock(struct drm_crtc *crtc)
6376 struct drm_device *dev = crtc->dev;
6377 drm_i915_private_t *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 int pipe = intel_crtc->pipe;
6380 int dpll_reg = DPLL(pipe);
6383 if (HAS_PCH_SPLIT(dev))
6386 if (!dev_priv->lvds_downclock_avail)
6389 dpll = I915_READ(dpll_reg);
6390 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6391 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6393 /* Unlock panel regs */
6394 I915_WRITE(PP_CONTROL,
6395 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6397 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6398 I915_WRITE(dpll_reg, dpll);
6399 intel_wait_for_vblank(dev, pipe);
6401 dpll = I915_READ(dpll_reg);
6402 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6403 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6405 /* ...and lock them again */
6406 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6409 /* Schedule downclock */
6410 mod_timer(&intel_crtc->idle_timer, jiffies +
6411 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6414 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6416 struct drm_device *dev = crtc->dev;
6417 drm_i915_private_t *dev_priv = dev->dev_private;
6418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419 int pipe = intel_crtc->pipe;
6420 int dpll_reg = DPLL(pipe);
6421 int dpll = I915_READ(dpll_reg);
6423 if (HAS_PCH_SPLIT(dev))
6426 if (!dev_priv->lvds_downclock_avail)
6430 * Since this is called by a timer, we should never get here in
6433 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6434 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6436 /* Unlock panel regs */
6437 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6440 dpll |= DISPLAY_RATE_SELECT_FPA1;
6441 I915_WRITE(dpll_reg, dpll);
6442 intel_wait_for_vblank(dev, pipe);
6443 dpll = I915_READ(dpll_reg);
6444 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6445 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6447 /* ...and lock them again */
6448 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6454 * intel_idle_update - adjust clocks for idleness
6455 * @work: work struct
6457 * Either the GPU or display (or both) went idle. Check the busy status
6458 * here and adjust the CRTC and GPU clocks as necessary.
6460 static void intel_idle_update(struct work_struct *work)
6462 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6464 struct drm_device *dev = dev_priv->dev;
6465 struct drm_crtc *crtc;
6466 struct intel_crtc *intel_crtc;
6468 if (!i915_powersave)
6471 mutex_lock(&dev->struct_mutex);
6473 i915_update_gfx_val(dev_priv);
6475 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6476 /* Skip inactive CRTCs */
6480 intel_crtc = to_intel_crtc(crtc);
6481 if (!intel_crtc->busy)
6482 intel_decrease_pllclock(crtc);
6486 mutex_unlock(&dev->struct_mutex);
6490 * intel_mark_busy - mark the GPU and possibly the display busy
6492 * @obj: object we're operating on
6494 * Callers can use this function to indicate that the GPU is busy processing
6495 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6496 * buffer), we'll also mark the display as busy, so we know to increase its
6499 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6501 drm_i915_private_t *dev_priv = dev->dev_private;
6502 struct drm_crtc *crtc = NULL;
6503 struct intel_framebuffer *intel_fb;
6504 struct intel_crtc *intel_crtc;
6506 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6509 if (!dev_priv->busy)
6510 dev_priv->busy = true;
6512 mod_timer(&dev_priv->idle_timer, jiffies +
6513 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6515 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6519 intel_crtc = to_intel_crtc(crtc);
6520 intel_fb = to_intel_framebuffer(crtc->fb);
6521 if (intel_fb->obj == obj) {
6522 if (!intel_crtc->busy) {
6523 /* Non-busy -> busy, upclock */
6524 intel_increase_pllclock(crtc);
6525 intel_crtc->busy = true;
6527 /* Busy -> busy, put off timer */
6528 mod_timer(&intel_crtc->idle_timer, jiffies +
6529 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6535 static void intel_crtc_destroy(struct drm_crtc *crtc)
6537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6538 struct drm_device *dev = crtc->dev;
6539 struct intel_unpin_work *work;
6540 unsigned long flags;
6542 spin_lock_irqsave(&dev->event_lock, flags);
6543 work = intel_crtc->unpin_work;
6544 intel_crtc->unpin_work = NULL;
6545 spin_unlock_irqrestore(&dev->event_lock, flags);
6548 cancel_work_sync(&work->work);
6552 drm_crtc_cleanup(crtc);
6557 static void intel_unpin_work_fn(struct work_struct *__work)
6559 struct intel_unpin_work *work =
6560 container_of(__work, struct intel_unpin_work, work);
6562 mutex_lock(&work->dev->struct_mutex);
6563 i915_gem_object_unpin(work->old_fb_obj);
6564 drm_gem_object_unreference(&work->pending_flip_obj->base);
6565 drm_gem_object_unreference(&work->old_fb_obj->base);
6567 intel_update_fbc(work->dev);
6568 mutex_unlock(&work->dev->struct_mutex);
6572 static void do_intel_finish_page_flip(struct drm_device *dev,
6573 struct drm_crtc *crtc)
6575 drm_i915_private_t *dev_priv = dev->dev_private;
6576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6577 struct intel_unpin_work *work;
6578 struct drm_i915_gem_object *obj;
6579 struct drm_pending_vblank_event *e;
6580 struct timeval tnow, tvbl;
6581 unsigned long flags;
6583 /* Ignore early vblank irqs */
6584 if (intel_crtc == NULL)
6587 do_gettimeofday(&tnow);
6589 spin_lock_irqsave(&dev->event_lock, flags);
6590 work = intel_crtc->unpin_work;
6591 if (work == NULL || !work->pending) {
6592 spin_unlock_irqrestore(&dev->event_lock, flags);
6596 intel_crtc->unpin_work = NULL;
6600 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6602 /* Called before vblank count and timestamps have
6603 * been updated for the vblank interval of flip
6604 * completion? Need to increment vblank count and
6605 * add one videorefresh duration to returned timestamp
6606 * to account for this. We assume this happened if we
6607 * get called over 0.9 frame durations after the last
6608 * timestamped vblank.
6610 * This calculation can not be used with vrefresh rates
6611 * below 5Hz (10Hz to be on the safe side) without
6612 * promoting to 64 integers.
6614 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6615 9 * crtc->framedur_ns) {
6616 e->event.sequence++;
6617 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6621 e->event.tv_sec = tvbl.tv_sec;
6622 e->event.tv_usec = tvbl.tv_usec;
6624 list_add_tail(&e->base.link,
6625 &e->base.file_priv->event_list);
6626 wake_up_interruptible(&e->base.file_priv->event_wait);
6629 drm_vblank_put(dev, intel_crtc->pipe);
6631 spin_unlock_irqrestore(&dev->event_lock, flags);
6633 obj = work->old_fb_obj;
6635 atomic_clear_mask(1 << intel_crtc->plane,
6636 &obj->pending_flip.counter);
6637 if (atomic_read(&obj->pending_flip) == 0)
6638 wake_up(&dev_priv->pending_flip_queue);
6640 schedule_work(&work->work);
6642 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6645 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6647 drm_i915_private_t *dev_priv = dev->dev_private;
6648 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6650 do_intel_finish_page_flip(dev, crtc);
6653 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6655 drm_i915_private_t *dev_priv = dev->dev_private;
6656 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6658 do_intel_finish_page_flip(dev, crtc);
6661 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6663 drm_i915_private_t *dev_priv = dev->dev_private;
6664 struct intel_crtc *intel_crtc =
6665 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6666 unsigned long flags;
6668 spin_lock_irqsave(&dev->event_lock, flags);
6669 if (intel_crtc->unpin_work) {
6670 if ((++intel_crtc->unpin_work->pending) > 1)
6671 DRM_ERROR("Prepared flip multiple times\n");
6673 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6675 spin_unlock_irqrestore(&dev->event_lock, flags);
6678 static int intel_gen2_queue_flip(struct drm_device *dev,
6679 struct drm_crtc *crtc,
6680 struct drm_framebuffer *fb,
6681 struct drm_i915_gem_object *obj)
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6685 unsigned long offset;
6689 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6693 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6694 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6696 ret = BEGIN_LP_RING(6);
6700 /* Can't queue multiple flips, so wait for the previous
6701 * one to finish before executing the next.
6703 if (intel_crtc->plane)
6704 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6706 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6707 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6709 OUT_RING(MI_DISPLAY_FLIP |
6710 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6711 OUT_RING(fb->pitch);
6712 OUT_RING(obj->gtt_offset + offset);
6719 static int intel_gen3_queue_flip(struct drm_device *dev,
6720 struct drm_crtc *crtc,
6721 struct drm_framebuffer *fb,
6722 struct drm_i915_gem_object *obj)
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6726 unsigned long offset;
6730 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6734 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6735 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6737 ret = BEGIN_LP_RING(6);
6741 if (intel_crtc->plane)
6742 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6744 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6745 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6747 OUT_RING(MI_DISPLAY_FLIP_I915 |
6748 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6749 OUT_RING(fb->pitch);
6750 OUT_RING(obj->gtt_offset + offset);
6758 static int intel_gen4_queue_flip(struct drm_device *dev,
6759 struct drm_crtc *crtc,
6760 struct drm_framebuffer *fb,
6761 struct drm_i915_gem_object *obj)
6763 struct drm_i915_private *dev_priv = dev->dev_private;
6764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6765 uint32_t pf, pipesrc;
6768 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6772 ret = BEGIN_LP_RING(4);
6776 /* i965+ uses the linear or tiled offsets from the
6777 * Display Registers (which do not change across a page-flip)
6778 * so we need only reprogram the base address.
6780 OUT_RING(MI_DISPLAY_FLIP |
6781 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6782 OUT_RING(fb->pitch);
6783 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6785 /* XXX Enabling the panel-fitter across page-flip is so far
6786 * untested on non-native modes, so ignore it for now.
6787 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6790 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6791 OUT_RING(pf | pipesrc);
6797 static int intel_gen6_queue_flip(struct drm_device *dev,
6798 struct drm_crtc *crtc,
6799 struct drm_framebuffer *fb,
6800 struct drm_i915_gem_object *obj)
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6804 uint32_t pf, pipesrc;
6807 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6811 ret = BEGIN_LP_RING(4);
6815 OUT_RING(MI_DISPLAY_FLIP |
6816 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6817 OUT_RING(fb->pitch | obj->tiling_mode);
6818 OUT_RING(obj->gtt_offset);
6820 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6821 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6822 OUT_RING(pf | pipesrc);
6829 * On gen7 we currently use the blit ring because (in early silicon at least)
6830 * the render ring doesn't give us interrpts for page flip completion, which
6831 * means clients will hang after the first flip is queued. Fortunately the
6832 * blit ring generates interrupts properly, so use it instead.
6834 static int intel_gen7_queue_flip(struct drm_device *dev,
6835 struct drm_crtc *crtc,
6836 struct drm_framebuffer *fb,
6837 struct drm_i915_gem_object *obj)
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6841 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6844 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6848 ret = intel_ring_begin(ring, 4);
6852 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6853 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6854 intel_ring_emit(ring, (obj->gtt_offset));
6855 intel_ring_emit(ring, (MI_NOOP));
6856 intel_ring_advance(ring);
6861 static int intel_default_queue_flip(struct drm_device *dev,
6862 struct drm_crtc *crtc,
6863 struct drm_framebuffer *fb,
6864 struct drm_i915_gem_object *obj)
6869 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6870 struct drm_framebuffer *fb,
6871 struct drm_pending_vblank_event *event)
6873 struct drm_device *dev = crtc->dev;
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 struct intel_framebuffer *intel_fb;
6876 struct drm_i915_gem_object *obj;
6877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6878 struct intel_unpin_work *work;
6879 unsigned long flags;
6882 work = kzalloc(sizeof *work, GFP_KERNEL);
6886 work->event = event;
6887 work->dev = crtc->dev;
6888 intel_fb = to_intel_framebuffer(crtc->fb);
6889 work->old_fb_obj = intel_fb->obj;
6890 INIT_WORK(&work->work, intel_unpin_work_fn);
6892 /* We borrow the event spin lock for protecting unpin_work */
6893 spin_lock_irqsave(&dev->event_lock, flags);
6894 if (intel_crtc->unpin_work) {
6895 spin_unlock_irqrestore(&dev->event_lock, flags);
6898 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6901 intel_crtc->unpin_work = work;
6902 spin_unlock_irqrestore(&dev->event_lock, flags);
6904 intel_fb = to_intel_framebuffer(fb);
6905 obj = intel_fb->obj;
6907 mutex_lock(&dev->struct_mutex);
6909 /* Reference the objects for the scheduled work. */
6910 drm_gem_object_reference(&work->old_fb_obj->base);
6911 drm_gem_object_reference(&obj->base);
6915 ret = drm_vblank_get(dev, intel_crtc->pipe);
6919 work->pending_flip_obj = obj;
6921 work->enable_stall_check = true;
6923 /* Block clients from rendering to the new back buffer until
6924 * the flip occurs and the object is no longer visible.
6926 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6928 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6930 goto cleanup_pending;
6932 intel_disable_fbc(dev);
6933 mutex_unlock(&dev->struct_mutex);
6935 trace_i915_flip_request(intel_crtc->plane, obj);
6940 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6942 drm_gem_object_unreference(&work->old_fb_obj->base);
6943 drm_gem_object_unreference(&obj->base);
6944 mutex_unlock(&dev->struct_mutex);
6946 spin_lock_irqsave(&dev->event_lock, flags);
6947 intel_crtc->unpin_work = NULL;
6948 spin_unlock_irqrestore(&dev->event_lock, flags);
6955 static void intel_sanitize_modesetting(struct drm_device *dev,
6956 int pipe, int plane)
6958 struct drm_i915_private *dev_priv = dev->dev_private;
6961 if (HAS_PCH_SPLIT(dev))
6964 /* Who knows what state these registers were left in by the BIOS or
6967 * If we leave the registers in a conflicting state (e.g. with the
6968 * display plane reading from the other pipe than the one we intend
6969 * to use) then when we attempt to teardown the active mode, we will
6970 * not disable the pipes and planes in the correct order -- leaving
6971 * a plane reading from a disabled pipe and possibly leading to
6972 * undefined behaviour.
6975 reg = DSPCNTR(plane);
6976 val = I915_READ(reg);
6978 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6980 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6983 /* This display plane is active and attached to the other CPU pipe. */
6986 /* Disable the plane and wait for it to stop reading from the pipe. */
6987 intel_disable_plane(dev_priv, plane, pipe);
6988 intel_disable_pipe(dev_priv, pipe);
6991 static void intel_crtc_reset(struct drm_crtc *crtc)
6993 struct drm_device *dev = crtc->dev;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6996 /* Reset flags back to the 'unknown' status so that they
6997 * will be correctly set on the initial modeset.
6999 intel_crtc->dpms_mode = -1;
7001 /* We need to fix up any BIOS configuration that conflicts with
7004 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7007 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7008 .dpms = intel_crtc_dpms,
7009 .mode_fixup = intel_crtc_mode_fixup,
7010 .mode_set = intel_crtc_mode_set,
7011 .mode_set_base = intel_pipe_set_base,
7012 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7013 .load_lut = intel_crtc_load_lut,
7014 .disable = intel_crtc_disable,
7017 static const struct drm_crtc_funcs intel_crtc_funcs = {
7018 .reset = intel_crtc_reset,
7019 .cursor_set = intel_crtc_cursor_set,
7020 .cursor_move = intel_crtc_cursor_move,
7021 .gamma_set = intel_crtc_gamma_set,
7022 .set_config = drm_crtc_helper_set_config,
7023 .destroy = intel_crtc_destroy,
7024 .page_flip = intel_crtc_page_flip,
7027 static void intel_crtc_init(struct drm_device *dev, int pipe)
7029 drm_i915_private_t *dev_priv = dev->dev_private;
7030 struct intel_crtc *intel_crtc;
7033 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7034 if (intel_crtc == NULL)
7037 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7039 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7040 for (i = 0; i < 256; i++) {
7041 intel_crtc->lut_r[i] = i;
7042 intel_crtc->lut_g[i] = i;
7043 intel_crtc->lut_b[i] = i;
7046 /* Swap pipes & planes for FBC on pre-965 */
7047 intel_crtc->pipe = pipe;
7048 intel_crtc->plane = pipe;
7049 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7050 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7051 intel_crtc->plane = !pipe;
7054 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7055 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7056 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7057 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7059 intel_crtc_reset(&intel_crtc->base);
7060 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7061 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7063 if (HAS_PCH_SPLIT(dev)) {
7064 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7065 intel_helper_funcs.commit = ironlake_crtc_commit;
7067 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7068 intel_helper_funcs.commit = i9xx_crtc_commit;
7071 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7073 intel_crtc->busy = false;
7075 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7076 (unsigned long)intel_crtc);
7079 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7080 struct drm_file *file)
7082 drm_i915_private_t *dev_priv = dev->dev_private;
7083 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7084 struct drm_mode_object *drmmode_obj;
7085 struct intel_crtc *crtc;
7088 DRM_ERROR("called with no initialization\n");
7092 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7093 DRM_MODE_OBJECT_CRTC);
7096 DRM_ERROR("no such CRTC id\n");
7100 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7101 pipe_from_crtc_id->pipe = crtc->pipe;
7106 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7108 struct intel_encoder *encoder;
7112 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7113 if (type_mask & encoder->clone_mask)
7114 index_mask |= (1 << entry);
7121 static bool has_edp_a(struct drm_device *dev)
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7125 if (!IS_MOBILE(dev))
7128 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7132 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7138 static void intel_setup_outputs(struct drm_device *dev)
7140 struct drm_i915_private *dev_priv = dev->dev_private;
7141 struct intel_encoder *encoder;
7142 bool dpd_is_edp = false;
7143 bool has_lvds = false;
7145 if (IS_MOBILE(dev) && !IS_I830(dev))
7146 has_lvds = intel_lvds_init(dev);
7147 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7148 /* disable the panel fitter on everything but LVDS */
7149 I915_WRITE(PFIT_CONTROL, 0);
7152 if (HAS_PCH_SPLIT(dev)) {
7153 dpd_is_edp = intel_dpd_is_edp(dev);
7156 intel_dp_init(dev, DP_A);
7158 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7159 intel_dp_init(dev, PCH_DP_D);
7162 intel_crt_init(dev);
7164 if (HAS_PCH_SPLIT(dev)) {
7167 if (I915_READ(HDMIB) & PORT_DETECTED) {
7168 /* PCH SDVOB multiplex with HDMIB */
7169 found = intel_sdvo_init(dev, PCH_SDVOB);
7171 intel_hdmi_init(dev, HDMIB);
7172 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7173 intel_dp_init(dev, PCH_DP_B);
7176 if (I915_READ(HDMIC) & PORT_DETECTED)
7177 intel_hdmi_init(dev, HDMIC);
7179 if (I915_READ(HDMID) & PORT_DETECTED)
7180 intel_hdmi_init(dev, HDMID);
7182 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7183 intel_dp_init(dev, PCH_DP_C);
7185 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7186 intel_dp_init(dev, PCH_DP_D);
7188 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7191 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7192 DRM_DEBUG_KMS("probing SDVOB\n");
7193 found = intel_sdvo_init(dev, SDVOB);
7194 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7195 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7196 intel_hdmi_init(dev, SDVOB);
7199 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7200 DRM_DEBUG_KMS("probing DP_B\n");
7201 intel_dp_init(dev, DP_B);
7205 /* Before G4X SDVOC doesn't have its own detect register */
7207 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7208 DRM_DEBUG_KMS("probing SDVOC\n");
7209 found = intel_sdvo_init(dev, SDVOC);
7212 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7214 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7215 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7216 intel_hdmi_init(dev, SDVOC);
7218 if (SUPPORTS_INTEGRATED_DP(dev)) {
7219 DRM_DEBUG_KMS("probing DP_C\n");
7220 intel_dp_init(dev, DP_C);
7224 if (SUPPORTS_INTEGRATED_DP(dev) &&
7225 (I915_READ(DP_D) & DP_DETECTED)) {
7226 DRM_DEBUG_KMS("probing DP_D\n");
7227 intel_dp_init(dev, DP_D);
7229 } else if (IS_GEN2(dev))
7230 intel_dvo_init(dev);
7232 if (SUPPORTS_TV(dev))
7235 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7236 encoder->base.possible_crtcs = encoder->crtc_mask;
7237 encoder->base.possible_clones =
7238 intel_encoder_clones(dev, encoder->clone_mask);
7241 /* disable all the possible outputs/crtcs before entering KMS mode */
7242 drm_helper_disable_unused_functions(dev);
7245 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7247 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7249 drm_framebuffer_cleanup(fb);
7250 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7255 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7256 struct drm_file *file,
7257 unsigned int *handle)
7259 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7260 struct drm_i915_gem_object *obj = intel_fb->obj;
7262 return drm_gem_handle_create(file, &obj->base, handle);
7265 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7266 .destroy = intel_user_framebuffer_destroy,
7267 .create_handle = intel_user_framebuffer_create_handle,
7270 int intel_framebuffer_init(struct drm_device *dev,
7271 struct intel_framebuffer *intel_fb,
7272 struct drm_mode_fb_cmd *mode_cmd,
7273 struct drm_i915_gem_object *obj)
7277 if (obj->tiling_mode == I915_TILING_Y)
7280 if (mode_cmd->pitch & 63)
7283 switch (mode_cmd->bpp) {
7286 /* Only pre-ILK can handle 5:5:5 */
7287 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7298 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7300 DRM_ERROR("framebuffer init failed %d\n", ret);
7304 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7305 intel_fb->obj = obj;
7309 static struct drm_framebuffer *
7310 intel_user_framebuffer_create(struct drm_device *dev,
7311 struct drm_file *filp,
7312 struct drm_mode_fb_cmd *mode_cmd)
7314 struct drm_i915_gem_object *obj;
7316 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7317 if (&obj->base == NULL)
7318 return ERR_PTR(-ENOENT);
7320 return intel_framebuffer_create(dev, mode_cmd, obj);
7323 static const struct drm_mode_config_funcs intel_mode_funcs = {
7324 .fb_create = intel_user_framebuffer_create,
7325 .output_poll_changed = intel_fb_output_poll_changed,
7328 static struct drm_i915_gem_object *
7329 intel_alloc_context_page(struct drm_device *dev)
7331 struct drm_i915_gem_object *ctx;
7334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7336 ctx = i915_gem_alloc_object(dev, 4096);
7338 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7342 ret = i915_gem_object_pin(ctx, 4096, true);
7344 DRM_ERROR("failed to pin power context: %d\n", ret);
7348 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7350 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7357 i915_gem_object_unpin(ctx);
7359 drm_gem_object_unreference(&ctx->base);
7360 mutex_unlock(&dev->struct_mutex);
7364 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7366 struct drm_i915_private *dev_priv = dev->dev_private;
7369 rgvswctl = I915_READ16(MEMSWCTL);
7370 if (rgvswctl & MEMCTL_CMD_STS) {
7371 DRM_DEBUG("gpu busy, RCS change rejected\n");
7372 return false; /* still busy with another command */
7375 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7376 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7377 I915_WRITE16(MEMSWCTL, rgvswctl);
7378 POSTING_READ16(MEMSWCTL);
7380 rgvswctl |= MEMCTL_CMD_STS;
7381 I915_WRITE16(MEMSWCTL, rgvswctl);
7386 void ironlake_enable_drps(struct drm_device *dev)
7388 struct drm_i915_private *dev_priv = dev->dev_private;
7389 u32 rgvmodectl = I915_READ(MEMMODECTL);
7390 u8 fmax, fmin, fstart, vstart;
7392 /* Enable temp reporting */
7393 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7394 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7396 /* 100ms RC evaluation intervals */
7397 I915_WRITE(RCUPEI, 100000);
7398 I915_WRITE(RCDNEI, 100000);
7400 /* Set max/min thresholds to 90ms and 80ms respectively */
7401 I915_WRITE(RCBMAXAVG, 90000);
7402 I915_WRITE(RCBMINAVG, 80000);
7404 I915_WRITE(MEMIHYST, 1);
7406 /* Set up min, max, and cur for interrupt handling */
7407 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7408 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7409 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7410 MEMMODE_FSTART_SHIFT;
7412 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7415 dev_priv->fmax = fmax; /* IPS callback will increase this */
7416 dev_priv->fstart = fstart;
7418 dev_priv->max_delay = fstart;
7419 dev_priv->min_delay = fmin;
7420 dev_priv->cur_delay = fstart;
7422 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7423 fmax, fmin, fstart);
7425 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7428 * Interrupts will be enabled in ironlake_irq_postinstall
7431 I915_WRITE(VIDSTART, vstart);
7432 POSTING_READ(VIDSTART);
7434 rgvmodectl |= MEMMODE_SWMODE_EN;
7435 I915_WRITE(MEMMODECTL, rgvmodectl);
7437 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7438 DRM_ERROR("stuck trying to change perf mode\n");
7441 ironlake_set_drps(dev, fstart);
7443 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7445 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7446 dev_priv->last_count2 = I915_READ(0x112f4);
7447 getrawmonotonic(&dev_priv->last_time2);
7450 void ironlake_disable_drps(struct drm_device *dev)
7452 struct drm_i915_private *dev_priv = dev->dev_private;
7453 u16 rgvswctl = I915_READ16(MEMSWCTL);
7455 /* Ack interrupts, disable EFC interrupt */
7456 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7457 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7458 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7459 I915_WRITE(DEIIR, DE_PCU_EVENT);
7460 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7462 /* Go back to the starting frequency */
7463 ironlake_set_drps(dev, dev_priv->fstart);
7465 rgvswctl |= MEMCTL_CMD_STS;
7466 I915_WRITE(MEMSWCTL, rgvswctl);
7471 void gen6_set_rps(struct drm_device *dev, u8 val)
7473 struct drm_i915_private *dev_priv = dev->dev_private;
7476 swreq = (val & 0x3ff) << 25;
7477 I915_WRITE(GEN6_RPNSWREQ, swreq);
7480 void gen6_disable_rps(struct drm_device *dev)
7482 struct drm_i915_private *dev_priv = dev->dev_private;
7484 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7485 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7486 I915_WRITE(GEN6_PMIER, 0);
7488 spin_lock_irq(&dev_priv->rps_lock);
7489 dev_priv->pm_iir = 0;
7490 spin_unlock_irq(&dev_priv->rps_lock);
7492 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7495 static unsigned long intel_pxfreq(u32 vidfreq)
7498 int div = (vidfreq & 0x3f0000) >> 16;
7499 int post = (vidfreq & 0x3000) >> 12;
7500 int pre = (vidfreq & 0x7);
7505 freq = ((div * 133333) / ((1<<post) * pre));
7510 void intel_init_emon(struct drm_device *dev)
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7517 /* Disable to program */
7521 /* Program energy weights for various events */
7522 I915_WRITE(SDEW, 0x15040d00);
7523 I915_WRITE(CSIEW0, 0x007f0000);
7524 I915_WRITE(CSIEW1, 0x1e220004);
7525 I915_WRITE(CSIEW2, 0x04000004);
7527 for (i = 0; i < 5; i++)
7528 I915_WRITE(PEW + (i * 4), 0);
7529 for (i = 0; i < 3; i++)
7530 I915_WRITE(DEW + (i * 4), 0);
7532 /* Program P-state weights to account for frequency power adjustment */
7533 for (i = 0; i < 16; i++) {
7534 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7535 unsigned long freq = intel_pxfreq(pxvidfreq);
7536 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7541 val *= (freq / 1000);
7543 val /= (127*127*900);
7545 DRM_ERROR("bad pxval: %ld\n", val);
7548 /* Render standby states get 0 weight */
7552 for (i = 0; i < 4; i++) {
7553 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7554 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7555 I915_WRITE(PXW + (i * 4), val);
7558 /* Adjust magic regs to magic values (more experimental results) */
7559 I915_WRITE(OGW0, 0);
7560 I915_WRITE(OGW1, 0);
7561 I915_WRITE(EG0, 0x00007f00);
7562 I915_WRITE(EG1, 0x0000000e);
7563 I915_WRITE(EG2, 0x000e0000);
7564 I915_WRITE(EG3, 0x68000300);
7565 I915_WRITE(EG4, 0x42000000);
7566 I915_WRITE(EG5, 0x00140031);
7570 for (i = 0; i < 8; i++)
7571 I915_WRITE(PXWL + (i * 4), 0);
7573 /* Enable PMON + select events */
7574 I915_WRITE(ECR, 0x80000019);
7576 lcfuse = I915_READ(LCFUSE02);
7578 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7581 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7583 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7584 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7585 u32 pcu_mbox, rc6_mask = 0;
7586 int cur_freq, min_freq, max_freq;
7589 /* Here begins a magic sequence of register writes to enable
7590 * auto-downclocking.
7592 * Perhaps there might be some value in exposing these to
7595 I915_WRITE(GEN6_RC_STATE, 0);
7596 mutex_lock(&dev_priv->dev->struct_mutex);
7597 gen6_gt_force_wake_get(dev_priv);
7599 /* disable the counters and set deterministic thresholds */
7600 I915_WRITE(GEN6_RC_CONTROL, 0);
7602 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7603 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7604 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7605 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7606 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7608 for (i = 0; i < I915_NUM_RINGS; i++)
7609 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7611 I915_WRITE(GEN6_RC_SLEEP, 0);
7612 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7613 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7614 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7615 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7617 if (i915_enable_rc6)
7618 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7619 GEN6_RC_CTL_RC6_ENABLE;
7621 I915_WRITE(GEN6_RC_CONTROL,
7623 GEN6_RC_CTL_EI_MODE(1) |
7624 GEN6_RC_CTL_HW_ENABLE);
7626 I915_WRITE(GEN6_RPNSWREQ,
7627 GEN6_FREQUENCY(10) |
7629 GEN6_AGGRESSIVE_TURBO);
7630 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7631 GEN6_FREQUENCY(12));
7633 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7634 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7637 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7638 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7639 I915_WRITE(GEN6_RP_UP_EI, 100000);
7640 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7641 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7642 I915_WRITE(GEN6_RP_CONTROL,
7643 GEN6_RP_MEDIA_TURBO |
7644 GEN6_RP_USE_NORMAL_FREQ |
7645 GEN6_RP_MEDIA_IS_GFX |
7647 GEN6_RP_UP_BUSY_AVG |
7648 GEN6_RP_DOWN_IDLE_CONT);
7650 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7652 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7654 I915_WRITE(GEN6_PCODE_DATA, 0);
7655 I915_WRITE(GEN6_PCODE_MAILBOX,
7657 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7658 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7660 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7662 min_freq = (rp_state_cap & 0xff0000) >> 16;
7663 max_freq = rp_state_cap & 0xff;
7664 cur_freq = (gt_perf_status & 0xff00) >> 8;
7666 /* Check for overclock support */
7667 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7669 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7670 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7671 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7672 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7674 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7675 if (pcu_mbox & (1<<31)) { /* OC supported */
7676 max_freq = pcu_mbox & 0xff;
7677 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7680 /* In units of 100MHz */
7681 dev_priv->max_delay = max_freq;
7682 dev_priv->min_delay = min_freq;
7683 dev_priv->cur_delay = cur_freq;
7685 /* requires MSI enabled */
7686 I915_WRITE(GEN6_PMIER,
7687 GEN6_PM_MBOX_EVENT |
7688 GEN6_PM_THERMAL_EVENT |
7689 GEN6_PM_RP_DOWN_TIMEOUT |
7690 GEN6_PM_RP_UP_THRESHOLD |
7691 GEN6_PM_RP_DOWN_THRESHOLD |
7692 GEN6_PM_RP_UP_EI_EXPIRED |
7693 GEN6_PM_RP_DOWN_EI_EXPIRED);
7694 spin_lock_irq(&dev_priv->rps_lock);
7695 WARN_ON(dev_priv->pm_iir != 0);
7696 I915_WRITE(GEN6_PMIMR, 0);
7697 spin_unlock_irq(&dev_priv->rps_lock);
7698 /* enable all PM interrupts */
7699 I915_WRITE(GEN6_PMINTRMSK, 0);
7701 gen6_gt_force_wake_put(dev_priv);
7702 mutex_unlock(&dev_priv->dev->struct_mutex);
7705 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7708 int gpu_freq, ia_freq, max_ia_freq;
7709 int scaling_factor = 180;
7711 max_ia_freq = cpufreq_quick_get_max(0);
7713 * Default to measured freq if none found, PCU will ensure we don't go
7717 max_ia_freq = tsc_khz;
7719 /* Convert from kHz to MHz */
7720 max_ia_freq /= 1000;
7722 mutex_lock(&dev_priv->dev->struct_mutex);
7725 * For each potential GPU frequency, load a ring frequency we'd like
7726 * to use for memory access. We do this by specifying the IA frequency
7727 * the PCU should use as a reference to determine the ring frequency.
7729 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7731 int diff = dev_priv->max_delay - gpu_freq;
7734 * For GPU frequencies less than 750MHz, just use the lowest
7737 if (gpu_freq < min_freq)
7740 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7741 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7743 I915_WRITE(GEN6_PCODE_DATA,
7744 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7746 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7747 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7748 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7749 GEN6_PCODE_READY) == 0, 10)) {
7750 DRM_ERROR("pcode write of freq table timed out\n");
7755 mutex_unlock(&dev_priv->dev->struct_mutex);
7758 static void ironlake_init_clock_gating(struct drm_device *dev)
7760 struct drm_i915_private *dev_priv = dev->dev_private;
7761 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7763 /* Required for FBC */
7764 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7765 DPFCRUNIT_CLOCK_GATE_DISABLE |
7766 DPFDUNIT_CLOCK_GATE_DISABLE;
7767 /* Required for CxSR */
7768 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7770 I915_WRITE(PCH_3DCGDIS0,
7771 MARIUNIT_CLOCK_GATE_DISABLE |
7772 SVSMUNIT_CLOCK_GATE_DISABLE);
7773 I915_WRITE(PCH_3DCGDIS1,
7774 VFMUNIT_CLOCK_GATE_DISABLE);
7776 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7779 * According to the spec the following bits should be set in
7780 * order to enable memory self-refresh
7781 * The bit 22/21 of 0x42004
7782 * The bit 5 of 0x42020
7783 * The bit 15 of 0x45000
7785 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7786 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7787 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7788 I915_WRITE(ILK_DSPCLK_GATE,
7789 (I915_READ(ILK_DSPCLK_GATE) |
7790 ILK_DPARB_CLK_GATE));
7791 I915_WRITE(DISP_ARB_CTL,
7792 (I915_READ(DISP_ARB_CTL) |
7794 I915_WRITE(WM3_LP_ILK, 0);
7795 I915_WRITE(WM2_LP_ILK, 0);
7796 I915_WRITE(WM1_LP_ILK, 0);
7799 * Based on the document from hardware guys the following bits
7800 * should be set unconditionally in order to enable FBC.
7801 * The bit 22 of 0x42000
7802 * The bit 22 of 0x42004
7803 * The bit 7,8,9 of 0x42020.
7805 if (IS_IRONLAKE_M(dev)) {
7806 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7807 I915_READ(ILK_DISPLAY_CHICKEN1) |
7809 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7810 I915_READ(ILK_DISPLAY_CHICKEN2) |
7812 I915_WRITE(ILK_DSPCLK_GATE,
7813 I915_READ(ILK_DSPCLK_GATE) |
7819 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7820 I915_READ(ILK_DISPLAY_CHICKEN2) |
7821 ILK_ELPIN_409_SELECT);
7822 I915_WRITE(_3D_CHICKEN2,
7823 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7824 _3D_CHICKEN2_WM_READ_PIPELINED);
7827 static void gen6_init_clock_gating(struct drm_device *dev)
7829 struct drm_i915_private *dev_priv = dev->dev_private;
7831 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7833 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7835 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7836 I915_READ(ILK_DISPLAY_CHICKEN2) |
7837 ILK_ELPIN_409_SELECT);
7839 I915_WRITE(WM3_LP_ILK, 0);
7840 I915_WRITE(WM2_LP_ILK, 0);
7841 I915_WRITE(WM1_LP_ILK, 0);
7844 * According to the spec the following bits should be
7845 * set in order to enable memory self-refresh and fbc:
7846 * The bit21 and bit22 of 0x42000
7847 * The bit21 and bit22 of 0x42004
7848 * The bit5 and bit7 of 0x42020
7849 * The bit14 of 0x70180
7850 * The bit14 of 0x71180
7852 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7853 I915_READ(ILK_DISPLAY_CHICKEN1) |
7854 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7855 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7856 I915_READ(ILK_DISPLAY_CHICKEN2) |
7857 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7858 I915_WRITE(ILK_DSPCLK_GATE,
7859 I915_READ(ILK_DSPCLK_GATE) |
7860 ILK_DPARB_CLK_GATE |
7863 for_each_pipe(pipe) {
7864 I915_WRITE(DSPCNTR(pipe),
7865 I915_READ(DSPCNTR(pipe)) |
7866 DISPPLANE_TRICKLE_FEED_DISABLE);
7867 intel_flush_display_plane(dev_priv, pipe);
7871 static void ivybridge_init_clock_gating(struct drm_device *dev)
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7875 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7877 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7879 I915_WRITE(WM3_LP_ILK, 0);
7880 I915_WRITE(WM2_LP_ILK, 0);
7881 I915_WRITE(WM1_LP_ILK, 0);
7883 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7885 for_each_pipe(pipe) {
7886 I915_WRITE(DSPCNTR(pipe),
7887 I915_READ(DSPCNTR(pipe)) |
7888 DISPPLANE_TRICKLE_FEED_DISABLE);
7889 intel_flush_display_plane(dev_priv, pipe);
7893 static void g4x_init_clock_gating(struct drm_device *dev)
7895 struct drm_i915_private *dev_priv = dev->dev_private;
7896 uint32_t dspclk_gate;
7898 I915_WRITE(RENCLK_GATE_D1, 0);
7899 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7900 GS_UNIT_CLOCK_GATE_DISABLE |
7901 CL_UNIT_CLOCK_GATE_DISABLE);
7902 I915_WRITE(RAMCLK_GATE_D, 0);
7903 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7904 OVRUNIT_CLOCK_GATE_DISABLE |
7905 OVCUNIT_CLOCK_GATE_DISABLE;
7907 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7908 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7911 static void crestline_init_clock_gating(struct drm_device *dev)
7913 struct drm_i915_private *dev_priv = dev->dev_private;
7915 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7916 I915_WRITE(RENCLK_GATE_D2, 0);
7917 I915_WRITE(DSPCLK_GATE_D, 0);
7918 I915_WRITE(RAMCLK_GATE_D, 0);
7919 I915_WRITE16(DEUC, 0);
7922 static void broadwater_init_clock_gating(struct drm_device *dev)
7924 struct drm_i915_private *dev_priv = dev->dev_private;
7926 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7927 I965_RCC_CLOCK_GATE_DISABLE |
7928 I965_RCPB_CLOCK_GATE_DISABLE |
7929 I965_ISC_CLOCK_GATE_DISABLE |
7930 I965_FBC_CLOCK_GATE_DISABLE);
7931 I915_WRITE(RENCLK_GATE_D2, 0);
7934 static void gen3_init_clock_gating(struct drm_device *dev)
7936 struct drm_i915_private *dev_priv = dev->dev_private;
7937 u32 dstate = I915_READ(D_STATE);
7939 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7940 DSTATE_DOT_CLOCK_GATING;
7941 I915_WRITE(D_STATE, dstate);
7944 static void i85x_init_clock_gating(struct drm_device *dev)
7946 struct drm_i915_private *dev_priv = dev->dev_private;
7948 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7951 static void i830_init_clock_gating(struct drm_device *dev)
7953 struct drm_i915_private *dev_priv = dev->dev_private;
7955 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7958 static void ibx_init_clock_gating(struct drm_device *dev)
7960 struct drm_i915_private *dev_priv = dev->dev_private;
7963 * On Ibex Peak and Cougar Point, we need to disable clock
7964 * gating for the panel power sequencer or it will fail to
7965 * start up when no ports are active.
7967 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7970 static void cpt_init_clock_gating(struct drm_device *dev)
7972 struct drm_i915_private *dev_priv = dev->dev_private;
7976 * On Ibex Peak and Cougar Point, we need to disable clock
7977 * gating for the panel power sequencer or it will fail to
7978 * start up when no ports are active.
7980 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7981 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7982 DPLS_EDP_PPS_FIX_DIS);
7983 /* Without this, mode sets may fail silently on FDI */
7985 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7988 static void ironlake_teardown_rc6(struct drm_device *dev)
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7992 if (dev_priv->renderctx) {
7993 i915_gem_object_unpin(dev_priv->renderctx);
7994 drm_gem_object_unreference(&dev_priv->renderctx->base);
7995 dev_priv->renderctx = NULL;
7998 if (dev_priv->pwrctx) {
7999 i915_gem_object_unpin(dev_priv->pwrctx);
8000 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8001 dev_priv->pwrctx = NULL;
8005 static void ironlake_disable_rc6(struct drm_device *dev)
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8009 if (I915_READ(PWRCTXA)) {
8010 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8011 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8012 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8015 I915_WRITE(PWRCTXA, 0);
8016 POSTING_READ(PWRCTXA);
8018 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8019 POSTING_READ(RSTDBYCTL);
8022 ironlake_teardown_rc6(dev);
8025 static int ironlake_setup_rc6(struct drm_device *dev)
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8029 if (dev_priv->renderctx == NULL)
8030 dev_priv->renderctx = intel_alloc_context_page(dev);
8031 if (!dev_priv->renderctx)
8034 if (dev_priv->pwrctx == NULL)
8035 dev_priv->pwrctx = intel_alloc_context_page(dev);
8036 if (!dev_priv->pwrctx) {
8037 ironlake_teardown_rc6(dev);
8044 void ironlake_enable_rc6(struct drm_device *dev)
8046 struct drm_i915_private *dev_priv = dev->dev_private;
8049 /* rc6 disabled by default due to repeated reports of hanging during
8052 if (!i915_enable_rc6)
8055 mutex_lock(&dev->struct_mutex);
8056 ret = ironlake_setup_rc6(dev);
8058 mutex_unlock(&dev->struct_mutex);
8063 * GPU can automatically power down the render unit if given a page
8066 ret = BEGIN_LP_RING(6);
8068 ironlake_teardown_rc6(dev);
8069 mutex_unlock(&dev->struct_mutex);
8073 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8074 OUT_RING(MI_SET_CONTEXT);
8075 OUT_RING(dev_priv->renderctx->gtt_offset |
8077 MI_SAVE_EXT_STATE_EN |
8078 MI_RESTORE_EXT_STATE_EN |
8079 MI_RESTORE_INHIBIT);
8080 OUT_RING(MI_SUSPEND_FLUSH);
8086 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8087 * does an implicit flush, combined with MI_FLUSH above, it should be
8088 * safe to assume that renderctx is valid
8090 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8092 DRM_ERROR("failed to enable ironlake power power savings\n");
8093 ironlake_teardown_rc6(dev);
8094 mutex_unlock(&dev->struct_mutex);
8098 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8099 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8100 mutex_unlock(&dev->struct_mutex);
8103 void intel_init_clock_gating(struct drm_device *dev)
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8107 dev_priv->display.init_clock_gating(dev);
8109 if (dev_priv->display.init_pch_clock_gating)
8110 dev_priv->display.init_pch_clock_gating(dev);
8113 /* Set up chip specific display functions */
8114 static void intel_init_display(struct drm_device *dev)
8116 struct drm_i915_private *dev_priv = dev->dev_private;
8118 /* We always want a DPMS function */
8119 if (HAS_PCH_SPLIT(dev)) {
8120 dev_priv->display.dpms = ironlake_crtc_dpms;
8121 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8122 dev_priv->display.update_plane = ironlake_update_plane;
8124 dev_priv->display.dpms = i9xx_crtc_dpms;
8125 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8126 dev_priv->display.update_plane = i9xx_update_plane;
8129 if (I915_HAS_FBC(dev)) {
8130 if (HAS_PCH_SPLIT(dev)) {
8131 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8132 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8133 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8134 } else if (IS_GM45(dev)) {
8135 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8136 dev_priv->display.enable_fbc = g4x_enable_fbc;
8137 dev_priv->display.disable_fbc = g4x_disable_fbc;
8138 } else if (IS_CRESTLINE(dev)) {
8139 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8140 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8141 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8143 /* 855GM needs testing */
8146 /* Returns the core display clock speed */
8147 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
8148 dev_priv->display.get_display_clock_speed =
8149 i945_get_display_clock_speed;
8150 else if (IS_I915G(dev))
8151 dev_priv->display.get_display_clock_speed =
8152 i915_get_display_clock_speed;
8153 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8154 dev_priv->display.get_display_clock_speed =
8155 i9xx_misc_get_display_clock_speed;
8156 else if (IS_I915GM(dev))
8157 dev_priv->display.get_display_clock_speed =
8158 i915gm_get_display_clock_speed;
8159 else if (IS_I865G(dev))
8160 dev_priv->display.get_display_clock_speed =
8161 i865_get_display_clock_speed;
8162 else if (IS_I85X(dev))
8163 dev_priv->display.get_display_clock_speed =
8164 i855_get_display_clock_speed;
8166 dev_priv->display.get_display_clock_speed =
8167 i830_get_display_clock_speed;
8169 /* For FIFO watermark updates */
8170 if (HAS_PCH_SPLIT(dev)) {
8171 if (HAS_PCH_IBX(dev))
8172 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8173 else if (HAS_PCH_CPT(dev))
8174 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8177 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8178 dev_priv->display.update_wm = ironlake_update_wm;
8180 DRM_DEBUG_KMS("Failed to get proper latency. "
8182 dev_priv->display.update_wm = NULL;
8184 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8185 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8186 } else if (IS_GEN6(dev)) {
8187 if (SNB_READ_WM0_LATENCY()) {
8188 dev_priv->display.update_wm = sandybridge_update_wm;
8190 DRM_DEBUG_KMS("Failed to read display plane latency. "
8192 dev_priv->display.update_wm = NULL;
8194 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8195 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8196 } else if (IS_IVYBRIDGE(dev)) {
8197 /* FIXME: detect B0+ stepping and use auto training */
8198 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8199 if (SNB_READ_WM0_LATENCY()) {
8200 dev_priv->display.update_wm = sandybridge_update_wm;
8202 DRM_DEBUG_KMS("Failed to read display plane latency. "
8204 dev_priv->display.update_wm = NULL;
8206 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8209 dev_priv->display.update_wm = NULL;
8210 } else if (IS_PINEVIEW(dev)) {
8211 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8214 dev_priv->mem_freq)) {
8215 DRM_INFO("failed to find known CxSR latency "
8216 "(found ddr%s fsb freq %d, mem freq %d), "
8218 (dev_priv->is_ddr3 == 1) ? "3": "2",
8219 dev_priv->fsb_freq, dev_priv->mem_freq);
8220 /* Disable CxSR and never update its watermark again */
8221 pineview_disable_cxsr(dev);
8222 dev_priv->display.update_wm = NULL;
8224 dev_priv->display.update_wm = pineview_update_wm;
8225 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8226 } else if (IS_G4X(dev)) {
8227 dev_priv->display.update_wm = g4x_update_wm;
8228 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8229 } else if (IS_GEN4(dev)) {
8230 dev_priv->display.update_wm = i965_update_wm;
8231 if (IS_CRESTLINE(dev))
8232 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8233 else if (IS_BROADWATER(dev))
8234 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8235 } else if (IS_GEN3(dev)) {
8236 dev_priv->display.update_wm = i9xx_update_wm;
8237 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8238 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8239 } else if (IS_I865G(dev)) {
8240 dev_priv->display.update_wm = i830_update_wm;
8241 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8242 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8243 } else if (IS_I85X(dev)) {
8244 dev_priv->display.update_wm = i9xx_update_wm;
8245 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8246 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8248 dev_priv->display.update_wm = i830_update_wm;
8249 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8251 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8253 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8256 /* Default just returns -ENODEV to indicate unsupported */
8257 dev_priv->display.queue_flip = intel_default_queue_flip;
8259 switch (INTEL_INFO(dev)->gen) {
8261 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8265 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8270 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8274 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8277 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8283 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8284 * resume, or other times. This quirk makes sure that's the case for
8287 static void quirk_pipea_force (struct drm_device *dev)
8289 struct drm_i915_private *dev_priv = dev->dev_private;
8291 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8292 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8296 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8298 static void quirk_ssc_force_disable(struct drm_device *dev)
8300 struct drm_i915_private *dev_priv = dev->dev_private;
8301 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8304 struct intel_quirk {
8306 int subsystem_vendor;
8307 int subsystem_device;
8308 void (*hook)(struct drm_device *dev);
8311 struct intel_quirk intel_quirks[] = {
8312 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8313 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8314 /* HP Mini needs pipe A force quirk (LP: #322104) */
8315 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8317 /* Thinkpad R31 needs pipe A force quirk */
8318 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8319 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8320 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8322 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8323 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8324 /* ThinkPad X40 needs pipe A force quirk */
8326 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8327 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8329 /* 855 & before need to leave pipe A & dpll A up */
8330 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8331 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8333 /* Lenovo U160 cannot use SSC on LVDS */
8334 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8336 /* Sony Vaio Y cannot use SSC on LVDS */
8337 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8340 static void intel_init_quirks(struct drm_device *dev)
8342 struct pci_dev *d = dev->pdev;
8345 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8346 struct intel_quirk *q = &intel_quirks[i];
8348 if (d->device == q->device &&
8349 (d->subsystem_vendor == q->subsystem_vendor ||
8350 q->subsystem_vendor == PCI_ANY_ID) &&
8351 (d->subsystem_device == q->subsystem_device ||
8352 q->subsystem_device == PCI_ANY_ID))
8357 /* Disable the VGA plane that we never use */
8358 static void i915_disable_vga(struct drm_device *dev)
8360 struct drm_i915_private *dev_priv = dev->dev_private;
8364 if (HAS_PCH_SPLIT(dev))
8365 vga_reg = CPU_VGACNTRL;
8369 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8370 outb(1, VGA_SR_INDEX);
8371 sr1 = inb(VGA_SR_DATA);
8372 outb(sr1 | 1<<5, VGA_SR_DATA);
8373 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8376 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8377 POSTING_READ(vga_reg);
8380 void intel_modeset_init(struct drm_device *dev)
8382 struct drm_i915_private *dev_priv = dev->dev_private;
8385 drm_mode_config_init(dev);
8387 dev->mode_config.min_width = 0;
8388 dev->mode_config.min_height = 0;
8390 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8392 intel_init_quirks(dev);
8394 intel_init_display(dev);
8397 dev->mode_config.max_width = 2048;
8398 dev->mode_config.max_height = 2048;
8399 } else if (IS_GEN3(dev)) {
8400 dev->mode_config.max_width = 4096;
8401 dev->mode_config.max_height = 4096;
8403 dev->mode_config.max_width = 8192;
8404 dev->mode_config.max_height = 8192;
8406 dev->mode_config.fb_base = dev->agp->base;
8408 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8409 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8411 for (i = 0; i < dev_priv->num_pipe; i++) {
8412 intel_crtc_init(dev, i);
8415 /* Just disable it once at startup */
8416 i915_disable_vga(dev);
8417 intel_setup_outputs(dev);
8419 intel_init_clock_gating(dev);
8421 if (IS_IRONLAKE_M(dev)) {
8422 ironlake_enable_drps(dev);
8423 intel_init_emon(dev);
8426 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8427 gen6_enable_rps(dev_priv);
8428 gen6_update_ring_freq(dev_priv);
8431 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8432 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8433 (unsigned long)dev);
8436 void intel_modeset_gem_init(struct drm_device *dev)
8438 if (IS_IRONLAKE_M(dev))
8439 ironlake_enable_rc6(dev);
8441 intel_setup_overlay(dev);
8444 void intel_modeset_cleanup(struct drm_device *dev)
8446 struct drm_i915_private *dev_priv = dev->dev_private;
8447 struct drm_crtc *crtc;
8448 struct intel_crtc *intel_crtc;
8450 drm_kms_helper_poll_fini(dev);
8451 mutex_lock(&dev->struct_mutex);
8453 intel_unregister_dsm_handler();
8456 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8457 /* Skip inactive CRTCs */
8461 intel_crtc = to_intel_crtc(crtc);
8462 intel_increase_pllclock(crtc);
8465 intel_disable_fbc(dev);
8467 if (IS_IRONLAKE_M(dev))
8468 ironlake_disable_drps(dev);
8469 if (IS_GEN6(dev) || IS_GEN7(dev))
8470 gen6_disable_rps(dev);
8472 if (IS_IRONLAKE_M(dev))
8473 ironlake_disable_rc6(dev);
8475 mutex_unlock(&dev->struct_mutex);
8477 /* Disable the irq before mode object teardown, for the irq might
8478 * enqueue unpin/hotplug work. */
8479 drm_irq_uninstall(dev);
8480 cancel_work_sync(&dev_priv->hotplug_work);
8482 /* flush any delayed tasks or pending work */
8483 flush_scheduled_work();
8485 /* Shut off idle work before the crtcs get freed. */
8486 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8487 intel_crtc = to_intel_crtc(crtc);
8488 del_timer_sync(&intel_crtc->idle_timer);
8490 del_timer_sync(&dev_priv->idle_timer);
8491 cancel_work_sync(&dev_priv->idle_work);
8493 drm_mode_config_cleanup(dev);
8497 * Return which encoder is currently attached for connector.
8499 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8501 return &intel_attached_encoder(connector)->base;
8504 void intel_connector_attach_encoder(struct intel_connector *connector,
8505 struct intel_encoder *encoder)
8507 connector->encoder = encoder;
8508 drm_mode_connector_attach_encoder(&connector->base,
8513 * set vga decode state - true == enable VGA decode
8515 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8517 struct drm_i915_private *dev_priv = dev->dev_private;
8520 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8522 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8524 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8525 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8529 #ifdef CONFIG_DEBUG_FS
8530 #include <linux/seq_file.h>
8532 struct intel_display_error_state {
8533 struct intel_cursor_error_state {
8540 struct intel_pipe_error_state {
8552 struct intel_plane_error_state {
8563 struct intel_display_error_state *
8564 intel_display_capture_error_state(struct drm_device *dev)
8566 drm_i915_private_t *dev_priv = dev->dev_private;
8567 struct intel_display_error_state *error;
8570 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8574 for (i = 0; i < 2; i++) {
8575 error->cursor[i].control = I915_READ(CURCNTR(i));
8576 error->cursor[i].position = I915_READ(CURPOS(i));
8577 error->cursor[i].base = I915_READ(CURBASE(i));
8579 error->plane[i].control = I915_READ(DSPCNTR(i));
8580 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8581 error->plane[i].size = I915_READ(DSPSIZE(i));
8582 error->plane[i].pos= I915_READ(DSPPOS(i));
8583 error->plane[i].addr = I915_READ(DSPADDR(i));
8584 if (INTEL_INFO(dev)->gen >= 4) {
8585 error->plane[i].surface = I915_READ(DSPSURF(i));
8586 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8589 error->pipe[i].conf = I915_READ(PIPECONF(i));
8590 error->pipe[i].source = I915_READ(PIPESRC(i));
8591 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8592 error->pipe[i].hblank = I915_READ(HBLANK(i));
8593 error->pipe[i].hsync = I915_READ(HSYNC(i));
8594 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8595 error->pipe[i].vblank = I915_READ(VBLANK(i));
8596 error->pipe[i].vsync = I915_READ(VSYNC(i));
8603 intel_display_print_error_state(struct seq_file *m,
8604 struct drm_device *dev,
8605 struct intel_display_error_state *error)
8609 for (i = 0; i < 2; i++) {
8610 seq_printf(m, "Pipe [%d]:\n", i);
8611 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8612 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8613 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8614 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8615 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8616 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8617 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8618 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8620 seq_printf(m, "Plane [%d]:\n", i);
8621 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8622 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8623 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8624 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8625 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8626 if (INTEL_INFO(dev)->gen >= 4) {
8627 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8628 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8631 seq_printf(m, "Cursor [%d]:\n", i);
8632 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8633 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8634 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);