2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include "intel_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
118 .find_pll = intel_find_best_PLL,
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
132 .find_pll = intel_find_best_PLL,
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
146 .find_pll = intel_find_best_PLL,
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
160 .find_pll = intel_find_best_PLL,
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
177 .find_pll = intel_g4x_find_best_PLL,
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
191 .find_pll = intel_g4x_find_best_PLL,
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
206 .find_pll = intel_g4x_find_best_PLL,
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
221 .find_pll = intel_g4x_find_best_PLL,
224 static const intel_limit_t intel_limits_g4x_display_port = {
225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
235 .find_pll = intel_find_pll_g4x_dp,
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
251 .find_pll = intel_find_best_PLL,
254 static const intel_limit_t intel_limits_pineview_lvds = {
255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
265 .find_pll = intel_find_best_PLL,
268 /* Ironlake / Sandybridge
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
273 static const intel_limit_t intel_limits_ironlake_dac = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_g4x_find_best_PLL,
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_g4x_find_best_PLL,
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
312 .find_pll = intel_g4x_find_best_PLL,
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 .find_pll = intel_g4x_find_best_PLL,
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 .find_pll = intel_g4x_find_best_PLL,
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
355 .find_pll = intel_find_pll_ironlake_dp,
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 const intel_limit_t *limit;
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_dual_lvds_100m;
372 limit = &intel_limits_ironlake_dual_lvds;
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_single_lvds_100m;
377 limit = &intel_limits_ironlake_single_lvds;
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381 limit = &intel_limits_ironlake_display_port;
383 limit = &intel_limits_ironlake_dac;
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 /* LVDS with dual channel */
398 limit = &intel_limits_g4x_dual_channel_lvds;
400 /* LVDS with dual channel */
401 limit = &intel_limits_g4x_single_channel_lvds;
402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404 limit = &intel_limits_g4x_hdmi;
405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406 limit = &intel_limits_g4x_sdvo;
407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408 limit = &intel_limits_g4x_display_port;
409 } else /* The option is for other outputs */
410 limit = &intel_limits_i9xx_sdvo;
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
420 if (HAS_PCH_SPLIT(dev))
421 limit = intel_ironlake_limit(crtc, refclk);
422 else if (IS_G4X(dev)) {
423 limit = intel_g4x_limit(crtc);
424 } else if (IS_PINEVIEW(dev)) {
425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426 limit = &intel_limits_pineview_lvds;
428 limit = &intel_limits_pineview_sdvo;
429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
433 limit = &intel_limits_i9xx_sdvo;
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i8xx_lvds;
438 limit = &intel_limits_i8xx_dvo;
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
465 * Returns whether any output on the specified pipe is of the specified type
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
480 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526 (I915_READ(LVDS)) != 0) {
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 clock.p2 = limit->p2.p2_fast;
537 clock.p2 = limit->p2.p2_slow;
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
542 clock.p2 = limit->p2.p2_fast;
545 memset (best_clock, 0, sizeof (*best_clock));
547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
560 intel_clock(dev, refclk, &clock);
561 if (!intel_PLL_is_valid(dev, limit,
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
575 return (err != target);
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
594 if (HAS_PCH_SPLIT(dev))
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600 clock.p2 = limit->p2.p2_fast;
602 clock.p2 = limit->p2.p2_slow;
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
607 clock.p2 = limit->p2.p2_fast;
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
612 /* based on hardware requirement, prefer smaller n to precision */
613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614 /* based on hardware requirement, prefere larger m1,m2 */
615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
623 intel_clock(dev, refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
628 this_err = abs(clock.dot - target);
629 if (this_err < err_most) {
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
646 struct drm_device *dev = crtc->dev;
649 if (target < 200000) {
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
673 if (target < 200000) {
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
695 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @pipe: pipe to wait for
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int pipestat_reg = PIPESTAT(pipe);
707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723 /* Wait for vblank interrupt bit to set */
724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
727 DRM_DEBUG_KMS("vblank wait timed out\n");
731 * intel_wait_for_pipe_off - wait for pipe to turn off
733 * @pipe: pipe to wait for
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
740 * wait for the pipe register state bit to turn off
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 struct drm_i915_private *dev_priv = dev->dev_private;
751 if (INTEL_INFO(dev)->gen >= 4) {
752 int reg = PIPECONF(pipe);
754 /* Wait for the Pipe State to go off */
755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
760 int reg = PIPEDSL(pipe);
761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763 /* Wait for the display line to settle */
765 last_line = I915_READ(reg) & DSL_LINEMASK;
767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
774 static const char *state_string(bool enabled)
776 return enabled ? "on" : "off";
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
878 int pp_reg, lvds_reg;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
916 pipe_name(pipe), state_string(state), state_string(cur_state));
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
983 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
984 int reg, u32 port_sel, u32 val)
986 if ((val & DP_PORT_EN) == 0)
989 if (HAS_PCH_CPT(dev_priv->dev)) {
990 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
995 if ((val & DP_PIPE_MASK) != (pipe << 30))
1001 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, int reg, u32 port_sel)
1004 u32 val = I915_READ(reg);
1005 WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
1006 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1007 reg, pipe_name(pipe));
1010 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe, int reg)
1013 u32 val = I915_READ(reg);
1014 WARN(HDMI_PIPE_ENABLED(val, pipe),
1015 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1016 reg, pipe_name(pipe));
1019 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1025 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1026 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1027 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1030 val = I915_READ(reg);
1031 WARN(ADPA_PIPE_ENABLED(val, pipe),
1032 "PCH VGA enabled on transcoder %c, should be disabled\n",
1036 val = I915_READ(reg);
1037 WARN(LVDS_PIPE_ENABLED(val, pipe),
1038 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1041 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1042 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1043 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1047 * intel_enable_pll - enable a PLL
1048 * @dev_priv: i915 private structure
1049 * @pipe: pipe PLL to enable
1051 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1052 * make sure the PLL reg is writable first though, since the panel write
1053 * protect mechanism may be enabled.
1055 * Note! This is for pre-ILK only.
1057 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1062 /* No really, not for ILK+ */
1063 BUG_ON(dev_priv->info->gen >= 5);
1065 /* PLL is protected by panel, make sure we can write it */
1066 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1067 assert_panel_unlocked(dev_priv, pipe);
1070 val = I915_READ(reg);
1071 val |= DPLL_VCO_ENABLE;
1073 /* We do this three times for luck */
1074 I915_WRITE(reg, val);
1076 udelay(150); /* wait for warmup */
1077 I915_WRITE(reg, val);
1079 udelay(150); /* wait for warmup */
1080 I915_WRITE(reg, val);
1082 udelay(150); /* wait for warmup */
1086 * intel_disable_pll - disable a PLL
1087 * @dev_priv: i915 private structure
1088 * @pipe: pipe PLL to disable
1090 * Disable the PLL for @pipe, making sure the pipe is off first.
1092 * Note! This is for pre-ILK only.
1094 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1099 /* Don't disable pipe A or pipe A PLLs if needed */
1100 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1103 /* Make sure the pipe isn't still relying on us */
1104 assert_pipe_disabled(dev_priv, pipe);
1107 val = I915_READ(reg);
1108 val &= ~DPLL_VCO_ENABLE;
1109 I915_WRITE(reg, val);
1114 * intel_enable_pch_pll - enable PCH PLL
1115 * @dev_priv: i915 private structure
1116 * @pipe: pipe PLL to enable
1118 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1119 * drives the transcoder clock.
1121 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1127 /* PCH only available on ILK+ */
1128 BUG_ON(dev_priv->info->gen < 5);
1130 /* PCH refclock must be enabled first */
1131 assert_pch_refclk_enabled(dev_priv);
1133 reg = PCH_DPLL(pipe);
1134 val = I915_READ(reg);
1135 val |= DPLL_VCO_ENABLE;
1136 I915_WRITE(reg, val);
1141 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1147 /* PCH only available on ILK+ */
1148 BUG_ON(dev_priv->info->gen < 5);
1150 /* Make sure transcoder isn't still depending on us */
1151 assert_transcoder_disabled(dev_priv, pipe);
1153 reg = PCH_DPLL(pipe);
1154 val = I915_READ(reg);
1155 val &= ~DPLL_VCO_ENABLE;
1156 I915_WRITE(reg, val);
1161 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1167 /* PCH only available on ILK+ */
1168 BUG_ON(dev_priv->info->gen < 5);
1170 /* Make sure PCH DPLL is enabled */
1171 assert_pch_pll_enabled(dev_priv, pipe);
1173 /* FDI must be feeding us bits for PCH ports */
1174 assert_fdi_tx_enabled(dev_priv, pipe);
1175 assert_fdi_rx_enabled(dev_priv, pipe);
1177 reg = TRANSCONF(pipe);
1178 val = I915_READ(reg);
1180 if (HAS_PCH_IBX(dev_priv->dev)) {
1182 * make the BPC in transcoder be consistent with
1183 * that in pipeconf reg.
1185 val &= ~PIPE_BPC_MASK;
1186 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1188 I915_WRITE(reg, val | TRANS_ENABLE);
1189 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1190 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1193 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1199 /* FDI relies on the transcoder */
1200 assert_fdi_tx_disabled(dev_priv, pipe);
1201 assert_fdi_rx_disabled(dev_priv, pipe);
1203 /* Ports must be off as well */
1204 assert_pch_ports_disabled(dev_priv, pipe);
1206 reg = TRANSCONF(pipe);
1207 val = I915_READ(reg);
1208 val &= ~TRANS_ENABLE;
1209 I915_WRITE(reg, val);
1210 /* wait for PCH transcoder off, transcoder state */
1211 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1212 DRM_ERROR("failed to disable transcoder\n");
1216 * intel_enable_pipe - enable a pipe, asserting requirements
1217 * @dev_priv: i915 private structure
1218 * @pipe: pipe to enable
1219 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1221 * Enable @pipe, making sure that various hardware specific requirements
1222 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1224 * @pipe should be %PIPE_A or %PIPE_B.
1226 * Will wait until the pipe is actually running (i.e. first vblank) before
1229 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1236 * A pipe without a PLL won't actually be able to drive bits from
1237 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1240 if (!HAS_PCH_SPLIT(dev_priv->dev))
1241 assert_pll_enabled(dev_priv, pipe);
1244 /* if driving the PCH, we need FDI enabled */
1245 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1246 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1248 /* FIXME: assert CPU port conditions for SNB+ */
1251 reg = PIPECONF(pipe);
1252 val = I915_READ(reg);
1253 if (val & PIPECONF_ENABLE)
1256 I915_WRITE(reg, val | PIPECONF_ENABLE);
1257 intel_wait_for_vblank(dev_priv->dev, pipe);
1261 * intel_disable_pipe - disable a pipe, asserting requirements
1262 * @dev_priv: i915 private structure
1263 * @pipe: pipe to disable
1265 * Disable @pipe, making sure that various hardware specific requirements
1266 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1268 * @pipe should be %PIPE_A or %PIPE_B.
1270 * Will wait until the pipe has shut down before returning.
1272 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1279 * Make sure planes won't keep trying to pump pixels to us,
1280 * or we might hang the display.
1282 assert_planes_disabled(dev_priv, pipe);
1284 /* Don't disable pipe A or pipe A PLLs if needed */
1285 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1288 reg = PIPECONF(pipe);
1289 val = I915_READ(reg);
1290 if ((val & PIPECONF_ENABLE) == 0)
1293 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1294 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1298 * Plane regs are double buffered, going from enabled->disabled needs a
1299 * trigger in order to latch. The display address reg provides this.
1301 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1304 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1305 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1309 * intel_enable_plane - enable a display plane on a given pipe
1310 * @dev_priv: i915 private structure
1311 * @plane: plane to enable
1312 * @pipe: pipe being fed
1314 * Enable @plane on @pipe, making sure that @pipe is running first.
1316 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1317 enum plane plane, enum pipe pipe)
1322 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1323 assert_pipe_enabled(dev_priv, pipe);
1325 reg = DSPCNTR(plane);
1326 val = I915_READ(reg);
1327 if (val & DISPLAY_PLANE_ENABLE)
1330 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1331 intel_flush_display_plane(dev_priv, plane);
1332 intel_wait_for_vblank(dev_priv->dev, pipe);
1336 * intel_disable_plane - disable a display plane
1337 * @dev_priv: i915 private structure
1338 * @plane: plane to disable
1339 * @pipe: pipe consuming the data
1341 * Disable @plane; should be an independent operation.
1343 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1344 enum plane plane, enum pipe pipe)
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
1351 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1354 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1355 intel_flush_display_plane(dev_priv, plane);
1356 intel_wait_for_vblank(dev_priv->dev, pipe);
1359 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, int reg, u32 port_sel)
1362 u32 val = I915_READ(reg);
1363 if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1364 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1365 I915_WRITE(reg, val & ~DP_PORT_EN);
1369 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, int reg)
1372 u32 val = I915_READ(reg);
1373 if (HDMI_PIPE_ENABLED(val, pipe)) {
1374 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1376 I915_WRITE(reg, val & ~PORT_ENABLE);
1380 /* Disable any ports connected to this transcoder */
1381 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1386 val = I915_READ(PCH_PP_CONTROL);
1387 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1389 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1390 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1391 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1394 val = I915_READ(reg);
1395 if (ADPA_PIPE_ENABLED(val, pipe))
1396 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1399 val = I915_READ(reg);
1400 if (LVDS_PIPE_ENABLED(val, pipe)) {
1401 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1406 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1407 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1408 disable_pch_hdmi(dev_priv, pipe, HDMID);
1411 static void i8xx_disable_fbc(struct drm_device *dev)
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1416 /* Disable compression */
1417 fbc_ctl = I915_READ(FBC_CONTROL);
1418 if ((fbc_ctl & FBC_CTL_EN) == 0)
1421 fbc_ctl &= ~FBC_CTL_EN;
1422 I915_WRITE(FBC_CONTROL, fbc_ctl);
1424 /* Wait for compressing bit to clear */
1425 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1426 DRM_DEBUG_KMS("FBC idle timed out\n");
1430 DRM_DEBUG_KMS("disabled FBC\n");
1433 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1435 struct drm_device *dev = crtc->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 struct drm_framebuffer *fb = crtc->fb;
1438 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1439 struct drm_i915_gem_object *obj = intel_fb->obj;
1440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1443 u32 fbc_ctl, fbc_ctl2;
1445 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1446 if (fb->pitch < cfb_pitch)
1447 cfb_pitch = fb->pitch;
1449 /* FBC_CTL wants 64B units */
1450 cfb_pitch = (cfb_pitch / 64) - 1;
1451 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1453 /* Clear old tags */
1454 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1455 I915_WRITE(FBC_TAG + (i * 4), 0);
1458 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1460 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1461 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1464 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1466 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1467 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1468 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1469 fbc_ctl |= obj->fence_reg;
1470 I915_WRITE(FBC_CONTROL, fbc_ctl);
1472 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1473 cfb_pitch, crtc->y, intel_crtc->plane);
1476 static bool i8xx_fbc_enabled(struct drm_device *dev)
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1480 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1483 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1485 struct drm_device *dev = crtc->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 struct drm_framebuffer *fb = crtc->fb;
1488 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1489 struct drm_i915_gem_object *obj = intel_fb->obj;
1490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1491 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1492 unsigned long stall_watermark = 200;
1495 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1496 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1497 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1499 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1500 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1501 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1502 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1505 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1507 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1510 static void g4x_disable_fbc(struct drm_device *dev)
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1515 /* Disable compression */
1516 dpfc_ctl = I915_READ(DPFC_CONTROL);
1517 if (dpfc_ctl & DPFC_CTL_EN) {
1518 dpfc_ctl &= ~DPFC_CTL_EN;
1519 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1521 DRM_DEBUG_KMS("disabled FBC\n");
1525 static bool g4x_fbc_enabled(struct drm_device *dev)
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1529 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1532 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1537 /* Make sure blitter notifies FBC of writes */
1538 gen6_gt_force_wake_get(dev_priv);
1539 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1540 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1541 GEN6_BLITTER_LOCK_SHIFT;
1542 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1543 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1544 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1545 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1546 GEN6_BLITTER_LOCK_SHIFT);
1547 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1549 gen6_gt_force_wake_put(dev_priv);
1552 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1554 struct drm_device *dev = crtc->dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 struct drm_framebuffer *fb = crtc->fb;
1557 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1558 struct drm_i915_gem_object *obj = intel_fb->obj;
1559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1560 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1561 unsigned long stall_watermark = 200;
1564 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1565 dpfc_ctl &= DPFC_RESERVED;
1566 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1567 /* Set persistent mode for front-buffer rendering, ala X. */
1568 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1569 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1570 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1572 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1573 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1574 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1575 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1576 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1578 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1581 I915_WRITE(SNB_DPFC_CTL_SA,
1582 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1583 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1584 sandybridge_blit_fbc_update(dev);
1587 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1590 static void ironlake_disable_fbc(struct drm_device *dev)
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1595 /* Disable compression */
1596 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1597 if (dpfc_ctl & DPFC_CTL_EN) {
1598 dpfc_ctl &= ~DPFC_CTL_EN;
1599 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1601 DRM_DEBUG_KMS("disabled FBC\n");
1605 static bool ironlake_fbc_enabled(struct drm_device *dev)
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1609 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1612 bool intel_fbc_enabled(struct drm_device *dev)
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1616 if (!dev_priv->display.fbc_enabled)
1619 return dev_priv->display.fbc_enabled(dev);
1622 static void intel_fbc_work_fn(struct work_struct *__work)
1624 struct intel_fbc_work *work =
1625 container_of(to_delayed_work(__work),
1626 struct intel_fbc_work, work);
1627 struct drm_device *dev = work->crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1630 mutex_lock(&dev->struct_mutex);
1631 if (work == dev_priv->fbc_work) {
1632 /* Double check that we haven't switched fb without cancelling
1635 if (work->crtc->fb == work->fb) {
1636 dev_priv->display.enable_fbc(work->crtc,
1639 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1640 dev_priv->cfb_fb = work->crtc->fb->base.id;
1641 dev_priv->cfb_y = work->crtc->y;
1644 dev_priv->fbc_work = NULL;
1646 mutex_unlock(&dev->struct_mutex);
1651 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1653 if (dev_priv->fbc_work == NULL)
1656 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1658 /* Synchronisation is provided by struct_mutex and checking of
1659 * dev_priv->fbc_work, so we can perform the cancellation
1660 * entirely asynchronously.
1662 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1663 /* tasklet was killed before being run, clean up */
1664 kfree(dev_priv->fbc_work);
1666 /* Mark the work as no longer wanted so that if it does
1667 * wake-up (because the work was already running and waiting
1668 * for our mutex), it will discover that is no longer
1671 dev_priv->fbc_work = NULL;
1674 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1676 struct intel_fbc_work *work;
1677 struct drm_device *dev = crtc->dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1680 if (!dev_priv->display.enable_fbc)
1683 intel_cancel_fbc_work(dev_priv);
1685 work = kzalloc(sizeof *work, GFP_KERNEL);
1687 dev_priv->display.enable_fbc(crtc, interval);
1692 work->fb = crtc->fb;
1693 work->interval = interval;
1694 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1696 dev_priv->fbc_work = work;
1698 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1700 /* Delay the actual enabling to let pageflipping cease and the
1701 * display to settle before starting the compression. Note that
1702 * this delay also serves a second purpose: it allows for a
1703 * vblank to pass after disabling the FBC before we attempt
1704 * to modify the control registers.
1706 * A more complicated solution would involve tracking vblanks
1707 * following the termination of the page-flipping sequence
1708 * and indeed performing the enable as a co-routine and not
1709 * waiting synchronously upon the vblank.
1711 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1714 void intel_disable_fbc(struct drm_device *dev)
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1718 intel_cancel_fbc_work(dev_priv);
1720 if (!dev_priv->display.disable_fbc)
1723 dev_priv->display.disable_fbc(dev);
1724 dev_priv->cfb_plane = -1;
1728 * intel_update_fbc - enable/disable FBC as needed
1729 * @dev: the drm_device
1731 * Set up the framebuffer compression hardware at mode set time. We
1732 * enable it if possible:
1733 * - plane A only (on pre-965)
1734 * - no pixel mulitply/line duplication
1735 * - no alpha buffer discard
1737 * - framebuffer <= 2048 in width, 1536 in height
1739 * We can't assume that any compression will take place (worst case),
1740 * so the compressed buffer has to be the same size as the uncompressed
1741 * one. It also must reside (along with the line length buffer) in
1744 * We need to enable/disable FBC on a global basis.
1746 static void intel_update_fbc(struct drm_device *dev)
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 struct drm_crtc *crtc = NULL, *tmp_crtc;
1750 struct intel_crtc *intel_crtc;
1751 struct drm_framebuffer *fb;
1752 struct intel_framebuffer *intel_fb;
1753 struct drm_i915_gem_object *obj;
1755 DRM_DEBUG_KMS("\n");
1757 if (!i915_powersave)
1760 if (!I915_HAS_FBC(dev))
1764 * If FBC is already on, we just have to verify that we can
1765 * keep it that way...
1766 * Need to disable if:
1767 * - more than one pipe is active
1768 * - changing FBC params (stride, fence, mode)
1769 * - new fb is too large to fit in compressed buffer
1770 * - going to an unsupported config (interlace, pixel multiply, etc.)
1772 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1773 if (tmp_crtc->enabled && tmp_crtc->fb) {
1775 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1776 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1783 if (!crtc || crtc->fb == NULL) {
1784 DRM_DEBUG_KMS("no output, disabling\n");
1785 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1789 intel_crtc = to_intel_crtc(crtc);
1791 intel_fb = to_intel_framebuffer(fb);
1792 obj = intel_fb->obj;
1794 if (!i915_enable_fbc) {
1795 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1796 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1799 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1800 DRM_DEBUG_KMS("framebuffer too large, disabling "
1802 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1805 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1806 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1807 DRM_DEBUG_KMS("mode incompatible with compression, "
1809 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1812 if ((crtc->mode.hdisplay > 2048) ||
1813 (crtc->mode.vdisplay > 1536)) {
1814 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1815 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1818 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1819 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1820 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1824 /* The use of a CPU fence is mandatory in order to detect writes
1825 * by the CPU to the scanout and trigger updates to the FBC.
1827 if (obj->tiling_mode != I915_TILING_X ||
1828 obj->fence_reg == I915_FENCE_REG_NONE) {
1829 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1830 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1834 /* If the kernel debugger is active, always disable compression */
1835 if (in_dbg_master())
1838 /* If the scanout has not changed, don't modify the FBC settings.
1839 * Note that we make the fundamental assumption that the fb->obj
1840 * cannot be unpinned (and have its GTT offset and fence revoked)
1841 * without first being decoupled from the scanout and FBC disabled.
1843 if (dev_priv->cfb_plane == intel_crtc->plane &&
1844 dev_priv->cfb_fb == fb->base.id &&
1845 dev_priv->cfb_y == crtc->y)
1848 if (intel_fbc_enabled(dev)) {
1849 /* We update FBC along two paths, after changing fb/crtc
1850 * configuration (modeswitching) and after page-flipping
1851 * finishes. For the latter, we know that not only did
1852 * we disable the FBC at the start of the page-flip
1853 * sequence, but also more than one vblank has passed.
1855 * For the former case of modeswitching, it is possible
1856 * to switch between two FBC valid configurations
1857 * instantaneously so we do need to disable the FBC
1858 * before we can modify its control registers. We also
1859 * have to wait for the next vblank for that to take
1860 * effect. However, since we delay enabling FBC we can
1861 * assume that a vblank has passed since disabling and
1862 * that we can safely alter the registers in the deferred
1865 * In the scenario that we go from a valid to invalid
1866 * and then back to valid FBC configuration we have
1867 * no strict enforcement that a vblank occurred since
1868 * disabling the FBC. However, along all current pipe
1869 * disabling paths we do need to wait for a vblank at
1870 * some point. And we wait before enabling FBC anyway.
1872 DRM_DEBUG_KMS("disabling active FBC for update\n");
1873 intel_disable_fbc(dev);
1876 intel_enable_fbc(crtc, 500);
1880 /* Multiple disables should be harmless */
1881 if (intel_fbc_enabled(dev)) {
1882 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1883 intel_disable_fbc(dev);
1888 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1889 struct drm_i915_gem_object *obj,
1890 struct intel_ring_buffer *pipelined)
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1896 switch (obj->tiling_mode) {
1897 case I915_TILING_NONE:
1898 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1899 alignment = 128 * 1024;
1900 else if (INTEL_INFO(dev)->gen >= 4)
1901 alignment = 4 * 1024;
1903 alignment = 64 * 1024;
1906 /* pin() will align the object as required by fence */
1910 /* FIXME: Is this true? */
1911 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1917 dev_priv->mm.interruptible = false;
1918 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1920 goto err_interruptible;
1922 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1923 * fence, whereas 965+ only requires a fence if using
1924 * framebuffer compression. For simplicity, we always install
1925 * a fence as the cost is not that onerous.
1927 if (obj->tiling_mode != I915_TILING_NONE) {
1928 ret = i915_gem_object_get_fence(obj, pipelined);
1933 dev_priv->mm.interruptible = true;
1937 i915_gem_object_unpin(obj);
1939 dev_priv->mm.interruptible = true;
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
1950 struct drm_i915_gem_object *obj;
1951 int plane = intel_crtc->plane;
1952 unsigned long Start, Offset;
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1974 dspcntr |= DISPPLANE_8BPP;
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1980 dspcntr |= DISPPLANE_16BPP;
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1990 if (INTEL_INFO(dev)->gen >= 4) {
1991 if (obj->tiling_mode != I915_TILING_NONE)
1992 dspcntr |= DISPPLANE_TILED;
1994 dspcntr &= ~DISPPLANE_TILED;
1997 I915_WRITE(reg, dspcntr);
1999 Start = obj->gtt_offset;
2000 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2002 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003 Start, Offset, x, y, fb->pitch);
2004 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2005 if (INTEL_INFO(dev)->gen >= 4) {
2006 I915_WRITE(DSPSURF(plane), Start);
2007 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2008 I915_WRITE(DSPADDR(plane), Offset);
2010 I915_WRITE(DSPADDR(plane), Start + Offset);
2016 static int ironlake_update_plane(struct drm_crtc *crtc,
2017 struct drm_framebuffer *fb, int x, int y)
2019 struct drm_device *dev = crtc->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022 struct intel_framebuffer *intel_fb;
2023 struct drm_i915_gem_object *obj;
2024 int plane = intel_crtc->plane;
2025 unsigned long Start, Offset;
2034 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038 intel_fb = to_intel_framebuffer(fb);
2039 obj = intel_fb->obj;
2041 reg = DSPCNTR(plane);
2042 dspcntr = I915_READ(reg);
2043 /* Mask out pixel format bits in case we change it */
2044 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2045 switch (fb->bits_per_pixel) {
2047 dspcntr |= DISPPLANE_8BPP;
2050 if (fb->depth != 16)
2053 dspcntr |= DISPPLANE_16BPP;
2057 if (fb->depth == 24)
2058 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2059 else if (fb->depth == 30)
2060 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2065 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2069 if (obj->tiling_mode != I915_TILING_NONE)
2070 dspcntr |= DISPPLANE_TILED;
2072 dspcntr &= ~DISPPLANE_TILED;
2075 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2077 I915_WRITE(reg, dspcntr);
2079 Start = obj->gtt_offset;
2080 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2082 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2083 Start, Offset, x, y, fb->pitch);
2084 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2085 I915_WRITE(DSPSURF(plane), Start);
2086 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2087 I915_WRITE(DSPADDR(plane), Offset);
2093 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2095 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2096 int x, int y, enum mode_set_atomic state)
2098 struct drm_device *dev = crtc->dev;
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2102 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2106 intel_update_fbc(dev);
2107 intel_increase_pllclock(crtc);
2113 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2114 struct drm_framebuffer *old_fb)
2116 struct drm_device *dev = crtc->dev;
2117 struct drm_i915_master_private *master_priv;
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123 DRM_ERROR("No FB bound\n");
2127 switch (intel_crtc->plane) {
2132 DRM_ERROR("no plane for crtc\n");
2136 mutex_lock(&dev->struct_mutex);
2137 ret = intel_pin_and_fence_fb_obj(dev,
2138 to_intel_framebuffer(crtc->fb)->obj,
2141 mutex_unlock(&dev->struct_mutex);
2142 DRM_ERROR("pin & fence failed\n");
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2150 wait_event(dev_priv->pending_flip_queue,
2151 atomic_read(&dev_priv->mm.wedged) ||
2152 atomic_read(&obj->pending_flip) == 0);
2154 /* Big Hammer, we also need to ensure that any pending
2155 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2156 * current scanout is retired before unpinning the old
2159 * This should only fail upon a hung GPU, in which case we
2160 * can safely continue.
2162 ret = i915_gem_object_finish_gpu(obj);
2166 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2167 LEAVE_ATOMIC_MODE_SET);
2169 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2170 mutex_unlock(&dev->struct_mutex);
2171 DRM_ERROR("failed to update base address\n");
2176 intel_wait_for_vblank(dev, intel_crtc->pipe);
2177 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2180 mutex_unlock(&dev->struct_mutex);
2182 if (!dev->primary->master)
2185 master_priv = dev->primary->master->driver_priv;
2186 if (!master_priv->sarea_priv)
2189 if (intel_crtc->pipe) {
2190 master_priv->sarea_priv->pipeB_x = x;
2191 master_priv->sarea_priv->pipeB_y = y;
2193 master_priv->sarea_priv->pipeA_x = x;
2194 master_priv->sarea_priv->pipeA_y = y;
2200 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2202 struct drm_device *dev = crtc->dev;
2203 struct drm_i915_private *dev_priv = dev->dev_private;
2206 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2207 dpa_ctl = I915_READ(DP_A);
2208 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2210 if (clock < 200000) {
2212 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2213 /* workaround for 160Mhz:
2214 1) program 0x4600c bits 15:0 = 0x8124
2215 2) program 0x46010 bit 0 = 1
2216 3) program 0x46034 bit 24 = 1
2217 4) program 0x64000 bit 14 = 1
2219 temp = I915_READ(0x4600c);
2221 I915_WRITE(0x4600c, temp | 0x8124);
2223 temp = I915_READ(0x46010);
2224 I915_WRITE(0x46010, temp | 1);
2226 temp = I915_READ(0x46034);
2227 I915_WRITE(0x46034, temp | (1 << 24));
2229 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2231 I915_WRITE(DP_A, dpa_ctl);
2237 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2239 struct drm_device *dev = crtc->dev;
2240 struct drm_i915_private *dev_priv = dev->dev_private;
2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242 int pipe = intel_crtc->pipe;
2245 /* enable normal train */
2246 reg = FDI_TX_CTL(pipe);
2247 temp = I915_READ(reg);
2248 if (IS_IVYBRIDGE(dev)) {
2249 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2250 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2252 temp &= ~FDI_LINK_TRAIN_NONE;
2253 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2255 I915_WRITE(reg, temp);
2257 reg = FDI_RX_CTL(pipe);
2258 temp = I915_READ(reg);
2259 if (HAS_PCH_CPT(dev)) {
2260 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2261 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2263 temp &= ~FDI_LINK_TRAIN_NONE;
2264 temp |= FDI_LINK_TRAIN_NONE;
2266 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2268 /* wait one idle pattern time */
2272 /* IVB wants error correction enabled */
2273 if (IS_IVYBRIDGE(dev))
2274 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2275 FDI_FE_ERRC_ENABLE);
2278 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 u32 flags = I915_READ(SOUTH_CHICKEN1);
2283 flags |= FDI_PHASE_SYNC_OVR(pipe);
2284 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2285 flags |= FDI_PHASE_SYNC_EN(pipe);
2286 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2287 POSTING_READ(SOUTH_CHICKEN1);
2290 /* The FDI link training functions for ILK/Ibexpeak. */
2291 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2293 struct drm_device *dev = crtc->dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 int pipe = intel_crtc->pipe;
2297 int plane = intel_crtc->plane;
2298 u32 reg, temp, tries;
2300 /* FDI needs bits from pipe & plane first */
2301 assert_pipe_enabled(dev_priv, pipe);
2302 assert_plane_enabled(dev_priv, plane);
2304 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2306 reg = FDI_RX_IMR(pipe);
2307 temp = I915_READ(reg);
2308 temp &= ~FDI_RX_SYMBOL_LOCK;
2309 temp &= ~FDI_RX_BIT_LOCK;
2310 I915_WRITE(reg, temp);
2314 /* enable CPU FDI TX and PCH FDI RX */
2315 reg = FDI_TX_CTL(pipe);
2316 temp = I915_READ(reg);
2318 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2319 temp &= ~FDI_LINK_TRAIN_NONE;
2320 temp |= FDI_LINK_TRAIN_PATTERN_1;
2321 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2323 reg = FDI_RX_CTL(pipe);
2324 temp = I915_READ(reg);
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_PATTERN_1;
2327 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2332 /* Ironlake workaround, enable clock pointer after FDI enable*/
2333 if (HAS_PCH_IBX(dev)) {
2334 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2335 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2336 FDI_RX_PHASE_SYNC_POINTER_EN);
2339 reg = FDI_RX_IIR(pipe);
2340 for (tries = 0; tries < 5; tries++) {
2341 temp = I915_READ(reg);
2342 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2344 if ((temp & FDI_RX_BIT_LOCK)) {
2345 DRM_DEBUG_KMS("FDI train 1 done.\n");
2346 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2351 DRM_ERROR("FDI train 1 fail!\n");
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_PATTERN_2;
2358 I915_WRITE(reg, temp);
2360 reg = FDI_RX_CTL(pipe);
2361 temp = I915_READ(reg);
2362 temp &= ~FDI_LINK_TRAIN_NONE;
2363 temp |= FDI_LINK_TRAIN_PATTERN_2;
2364 I915_WRITE(reg, temp);
2369 reg = FDI_RX_IIR(pipe);
2370 for (tries = 0; tries < 5; tries++) {
2371 temp = I915_READ(reg);
2372 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2374 if (temp & FDI_RX_SYMBOL_LOCK) {
2375 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2376 DRM_DEBUG_KMS("FDI train 2 done.\n");
2381 DRM_ERROR("FDI train 2 fail!\n");
2383 DRM_DEBUG_KMS("FDI train done\n");
2387 static const int snb_b_fdi_train_param [] = {
2388 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2389 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2390 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2391 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2394 /* The FDI link training functions for SNB/Cougarpoint. */
2395 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2397 struct drm_device *dev = crtc->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400 int pipe = intel_crtc->pipe;
2403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2405 reg = FDI_RX_IMR(pipe);
2406 temp = I915_READ(reg);
2407 temp &= ~FDI_RX_SYMBOL_LOCK;
2408 temp &= ~FDI_RX_BIT_LOCK;
2409 I915_WRITE(reg, temp);
2414 /* enable CPU FDI TX and PCH FDI RX */
2415 reg = FDI_TX_CTL(pipe);
2416 temp = I915_READ(reg);
2418 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2419 temp &= ~FDI_LINK_TRAIN_NONE;
2420 temp |= FDI_LINK_TRAIN_PATTERN_1;
2421 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2423 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2424 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2426 reg = FDI_RX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 if (HAS_PCH_CPT(dev)) {
2429 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2430 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2435 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2440 if (HAS_PCH_CPT(dev))
2441 cpt_phase_pointer_enable(dev, pipe);
2443 for (i = 0; i < 4; i++ ) {
2444 reg = FDI_TX_CTL(pipe);
2445 temp = I915_READ(reg);
2446 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447 temp |= snb_b_fdi_train_param[i];
2448 I915_WRITE(reg, temp);
2453 reg = FDI_RX_IIR(pipe);
2454 temp = I915_READ(reg);
2455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2457 if (temp & FDI_RX_BIT_LOCK) {
2458 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2459 DRM_DEBUG_KMS("FDI train 1 done.\n");
2464 DRM_ERROR("FDI train 1 fail!\n");
2467 reg = FDI_TX_CTL(pipe);
2468 temp = I915_READ(reg);
2469 temp &= ~FDI_LINK_TRAIN_NONE;
2470 temp |= FDI_LINK_TRAIN_PATTERN_2;
2472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2476 I915_WRITE(reg, temp);
2478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
2480 if (HAS_PCH_CPT(dev)) {
2481 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_2;
2487 I915_WRITE(reg, temp);
2492 for (i = 0; i < 4; i++ ) {
2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2496 temp |= snb_b_fdi_train_param[i];
2497 I915_WRITE(reg, temp);
2502 reg = FDI_RX_IIR(pipe);
2503 temp = I915_READ(reg);
2504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2506 if (temp & FDI_RX_SYMBOL_LOCK) {
2507 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2508 DRM_DEBUG_KMS("FDI train 2 done.\n");
2513 DRM_ERROR("FDI train 2 fail!\n");
2515 DRM_DEBUG_KMS("FDI train done.\n");
2518 /* Manual link training for Ivy Bridge A0 parts */
2519 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521 struct drm_device *dev = crtc->dev;
2522 struct drm_i915_private *dev_priv = dev->dev_private;
2523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2524 int pipe = intel_crtc->pipe;
2527 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 reg = FDI_RX_IMR(pipe);
2530 temp = I915_READ(reg);
2531 temp &= ~FDI_RX_SYMBOL_LOCK;
2532 temp &= ~FDI_RX_BIT_LOCK;
2533 I915_WRITE(reg, temp);
2538 /* enable CPU FDI TX and PCH FDI RX */
2539 reg = FDI_TX_CTL(pipe);
2540 temp = I915_READ(reg);
2542 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2543 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2549 reg = FDI_RX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_AUTO;
2552 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2554 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2559 if (HAS_PCH_CPT(dev))
2560 cpt_phase_pointer_enable(dev, pipe);
2562 for (i = 0; i < 4; i++ ) {
2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= snb_b_fdi_train_param[i];
2567 I915_WRITE(reg, temp);
2572 reg = FDI_RX_IIR(pipe);
2573 temp = I915_READ(reg);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576 if (temp & FDI_RX_BIT_LOCK ||
2577 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2578 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2579 DRM_DEBUG_KMS("FDI train 1 done.\n");
2584 DRM_ERROR("FDI train 1 fail!\n");
2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2590 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2591 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2593 I915_WRITE(reg, temp);
2595 reg = FDI_RX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599 I915_WRITE(reg, temp);
2604 for (i = 0; i < 4; i++ ) {
2605 reg = FDI_TX_CTL(pipe);
2606 temp = I915_READ(reg);
2607 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608 temp |= snb_b_fdi_train_param[i];
2609 I915_WRITE(reg, temp);
2614 reg = FDI_RX_IIR(pipe);
2615 temp = I915_READ(reg);
2616 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618 if (temp & FDI_RX_SYMBOL_LOCK) {
2619 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2620 DRM_DEBUG_KMS("FDI train 2 done.\n");
2625 DRM_ERROR("FDI train 2 fail!\n");
2627 DRM_DEBUG_KMS("FDI train done.\n");
2630 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 int pipe = intel_crtc->pipe;
2638 /* Write the TU size bits so error detection works */
2639 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2640 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2642 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2643 reg = FDI_RX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~((0x7 << 19) | (0x7 << 16));
2646 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2647 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2648 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2653 /* Switch from Rawclk to PCDclk */
2654 temp = I915_READ(reg);
2655 I915_WRITE(reg, temp | FDI_PCDCLK);
2660 /* Enable CPU FDI TX PLL, always on for Ironlake */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2664 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2671 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 u32 flags = I915_READ(SOUTH_CHICKEN1);
2676 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2677 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2678 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2679 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2680 POSTING_READ(SOUTH_CHICKEN1);
2682 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2684 struct drm_device *dev = crtc->dev;
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687 int pipe = intel_crtc->pipe;
2690 /* disable CPU FDI tx and PCH FDI rx */
2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2696 reg = FDI_RX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 temp &= ~(0x7 << 16);
2699 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2700 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2705 /* Ironlake workaround, disable clock pointer after downing FDI */
2706 if (HAS_PCH_IBX(dev)) {
2707 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2708 I915_WRITE(FDI_RX_CHICKEN(pipe),
2709 I915_READ(FDI_RX_CHICKEN(pipe) &
2710 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2711 } else if (HAS_PCH_CPT(dev)) {
2712 cpt_phase_pointer_disable(dev, pipe);
2715 /* still set train pattern 1 */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_LINK_TRAIN_NONE;
2719 temp |= FDI_LINK_TRAIN_PATTERN_1;
2720 I915_WRITE(reg, temp);
2722 reg = FDI_RX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 if (HAS_PCH_CPT(dev)) {
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2728 temp &= ~FDI_LINK_TRAIN_NONE;
2729 temp |= FDI_LINK_TRAIN_PATTERN_1;
2731 /* BPC in FDI rx is consistent with that in PIPECONF */
2732 temp &= ~(0x07 << 16);
2733 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2734 I915_WRITE(reg, temp);
2741 * When we disable a pipe, we need to clear any pending scanline wait events
2742 * to avoid hanging the ring, which we assume we are waiting on.
2744 static void intel_clear_scanline_wait(struct drm_device *dev)
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_ring_buffer *ring;
2751 /* Can't break the hang on i8xx */
2754 ring = LP_RING(dev_priv);
2755 tmp = I915_READ_CTL(ring);
2756 if (tmp & RING_WAIT)
2757 I915_WRITE_CTL(ring, tmp);
2760 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2762 struct drm_i915_gem_object *obj;
2763 struct drm_i915_private *dev_priv;
2765 if (crtc->fb == NULL)
2768 obj = to_intel_framebuffer(crtc->fb)->obj;
2769 dev_priv = crtc->dev->dev_private;
2770 wait_event(dev_priv->pending_flip_queue,
2771 atomic_read(&obj->pending_flip) == 0);
2774 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_mode_config *mode_config = &dev->mode_config;
2778 struct intel_encoder *encoder;
2781 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2782 * must be driven by its own crtc; no sharing is possible.
2784 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2785 if (encoder->base.crtc != crtc)
2788 switch (encoder->type) {
2789 case INTEL_OUTPUT_EDP:
2790 if (!intel_encoder_is_pch_edp(&encoder->base))
2800 * Enable PCH resources required for PCH ports:
2802 * - FDI training & RX/TX
2803 * - update transcoder timings
2804 * - DP transcoding bits
2807 static void ironlake_pch_enable(struct drm_crtc *crtc)
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812 int pipe = intel_crtc->pipe;
2815 /* For PCH output, training FDI link */
2816 dev_priv->display.fdi_link_train(crtc);
2818 intel_enable_pch_pll(dev_priv, pipe);
2820 if (HAS_PCH_CPT(dev)) {
2821 /* Be sure PCH DPLL SEL is set */
2822 temp = I915_READ(PCH_DPLL_SEL);
2823 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2824 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2825 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2826 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2827 I915_WRITE(PCH_DPLL_SEL, temp);
2830 /* set transcoder timing, panel must allow it */
2831 assert_panel_unlocked(dev_priv, pipe);
2832 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2833 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2834 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2836 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2837 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2838 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2840 intel_fdi_normal_train(crtc);
2842 /* For PCH DP, enable TRANS_DP_CTL */
2843 if (HAS_PCH_CPT(dev) &&
2844 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2845 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2846 reg = TRANS_DP_CTL(pipe);
2847 temp = I915_READ(reg);
2848 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2849 TRANS_DP_SYNC_MASK |
2851 temp |= (TRANS_DP_OUTPUT_ENABLE |
2852 TRANS_DP_ENH_FRAMING);
2853 temp |= bpc << 9; /* same format but at 11:9 */
2855 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2856 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2857 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2858 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2860 switch (intel_trans_dp_port_sel(crtc)) {
2862 temp |= TRANS_DP_PORT_SEL_B;
2865 temp |= TRANS_DP_PORT_SEL_C;
2868 temp |= TRANS_DP_PORT_SEL_D;
2871 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2872 temp |= TRANS_DP_PORT_SEL_B;
2876 I915_WRITE(reg, temp);
2879 intel_enable_transcoder(dev_priv, pipe);
2882 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2884 struct drm_device *dev = crtc->dev;
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2887 int pipe = intel_crtc->pipe;
2888 int plane = intel_crtc->plane;
2892 if (intel_crtc->active)
2895 intel_crtc->active = true;
2896 intel_update_watermarks(dev);
2898 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2899 temp = I915_READ(PCH_LVDS);
2900 if ((temp & LVDS_PORT_EN) == 0)
2901 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2904 is_pch_port = intel_crtc_driving_pch(crtc);
2907 ironlake_fdi_pll_enable(crtc);
2909 ironlake_fdi_disable(crtc);
2911 /* Enable panel fitting for LVDS */
2912 if (dev_priv->pch_pf_size &&
2913 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2914 /* Force use of hard-coded filter coefficients
2915 * as some pre-programmed values are broken,
2918 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2919 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2920 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2924 * On ILK+ LUT must be loaded before the pipe is running but with
2927 intel_crtc_load_lut(crtc);
2929 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2930 intel_enable_plane(dev_priv, plane, pipe);
2933 ironlake_pch_enable(crtc);
2935 mutex_lock(&dev->struct_mutex);
2936 intel_update_fbc(dev);
2937 mutex_unlock(&dev->struct_mutex);
2939 intel_crtc_update_cursor(crtc, true);
2942 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2944 struct drm_device *dev = crtc->dev;
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947 int pipe = intel_crtc->pipe;
2948 int plane = intel_crtc->plane;
2951 if (!intel_crtc->active)
2954 intel_crtc_wait_for_pending_flips(crtc);
2955 drm_vblank_off(dev, pipe);
2956 intel_crtc_update_cursor(crtc, false);
2958 intel_disable_plane(dev_priv, plane, pipe);
2960 if (dev_priv->cfb_plane == plane)
2961 intel_disable_fbc(dev);
2963 intel_disable_pipe(dev_priv, pipe);
2966 I915_WRITE(PF_CTL(pipe), 0);
2967 I915_WRITE(PF_WIN_SZ(pipe), 0);
2969 ironlake_fdi_disable(crtc);
2971 /* This is a horrible layering violation; we should be doing this in
2972 * the connector/encoder ->prepare instead, but we don't always have
2973 * enough information there about the config to know whether it will
2974 * actually be necessary or just cause undesired flicker.
2976 intel_disable_pch_ports(dev_priv, pipe);
2978 intel_disable_transcoder(dev_priv, pipe);
2980 if (HAS_PCH_CPT(dev)) {
2981 /* disable TRANS_DP_CTL */
2982 reg = TRANS_DP_CTL(pipe);
2983 temp = I915_READ(reg);
2984 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2985 temp |= TRANS_DP_PORT_SEL_NONE;
2986 I915_WRITE(reg, temp);
2988 /* disable DPLL_SEL */
2989 temp = I915_READ(PCH_DPLL_SEL);
2992 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2995 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2998 /* FIXME: manage transcoder PLLs? */
2999 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3004 I915_WRITE(PCH_DPLL_SEL, temp);
3007 /* disable PCH DPLL */
3008 intel_disable_pch_pll(dev_priv, pipe);
3010 /* Switch from PCDclk to Rawclk */
3011 reg = FDI_RX_CTL(pipe);
3012 temp = I915_READ(reg);
3013 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3015 /* Disable CPU FDI TX PLL */
3016 reg = FDI_TX_CTL(pipe);
3017 temp = I915_READ(reg);
3018 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3023 reg = FDI_RX_CTL(pipe);
3024 temp = I915_READ(reg);
3025 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3027 /* Wait for the clocks to turn off. */
3031 intel_crtc->active = false;
3032 intel_update_watermarks(dev);
3034 mutex_lock(&dev->struct_mutex);
3035 intel_update_fbc(dev);
3036 intel_clear_scanline_wait(dev);
3037 mutex_unlock(&dev->struct_mutex);
3040 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043 int pipe = intel_crtc->pipe;
3044 int plane = intel_crtc->plane;
3046 /* XXX: When our outputs are all unaware of DPMS modes other than off
3047 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3050 case DRM_MODE_DPMS_ON:
3051 case DRM_MODE_DPMS_STANDBY:
3052 case DRM_MODE_DPMS_SUSPEND:
3053 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3054 ironlake_crtc_enable(crtc);
3057 case DRM_MODE_DPMS_OFF:
3058 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3059 ironlake_crtc_disable(crtc);
3064 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3066 if (!enable && intel_crtc->overlay) {
3067 struct drm_device *dev = intel_crtc->base.dev;
3068 struct drm_i915_private *dev_priv = dev->dev_private;
3070 mutex_lock(&dev->struct_mutex);
3071 dev_priv->mm.interruptible = false;
3072 (void) intel_overlay_switch_off(intel_crtc->overlay);
3073 dev_priv->mm.interruptible = true;
3074 mutex_unlock(&dev->struct_mutex);
3077 /* Let userspace switch the overlay on again. In most cases userspace
3078 * has to recompute where to put it anyway.
3082 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3084 struct drm_device *dev = crtc->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087 int pipe = intel_crtc->pipe;
3088 int plane = intel_crtc->plane;
3090 if (intel_crtc->active)
3093 intel_crtc->active = true;
3094 intel_update_watermarks(dev);
3096 intel_enable_pll(dev_priv, pipe);
3097 intel_enable_pipe(dev_priv, pipe, false);
3098 intel_enable_plane(dev_priv, plane, pipe);
3100 intel_crtc_load_lut(crtc);
3101 intel_update_fbc(dev);
3103 /* Give the overlay scaler a chance to enable if it's on this pipe */
3104 intel_crtc_dpms_overlay(intel_crtc, true);
3105 intel_crtc_update_cursor(crtc, true);
3108 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3110 struct drm_device *dev = crtc->dev;
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3113 int pipe = intel_crtc->pipe;
3114 int plane = intel_crtc->plane;
3116 if (!intel_crtc->active)
3119 /* Give the overlay scaler a chance to disable if it's on this pipe */
3120 intel_crtc_wait_for_pending_flips(crtc);
3121 drm_vblank_off(dev, pipe);
3122 intel_crtc_dpms_overlay(intel_crtc, false);
3123 intel_crtc_update_cursor(crtc, false);
3125 if (dev_priv->cfb_plane == plane)
3126 intel_disable_fbc(dev);
3128 intel_disable_plane(dev_priv, plane, pipe);
3129 intel_disable_pipe(dev_priv, pipe);
3130 intel_disable_pll(dev_priv, pipe);
3132 intel_crtc->active = false;
3133 intel_update_fbc(dev);
3134 intel_update_watermarks(dev);
3135 intel_clear_scanline_wait(dev);
3138 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3140 /* XXX: When our outputs are all unaware of DPMS modes other than off
3141 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3144 case DRM_MODE_DPMS_ON:
3145 case DRM_MODE_DPMS_STANDBY:
3146 case DRM_MODE_DPMS_SUSPEND:
3147 i9xx_crtc_enable(crtc);
3149 case DRM_MODE_DPMS_OFF:
3150 i9xx_crtc_disable(crtc);
3156 * Sets the power management mode of the pipe and plane.
3158 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3160 struct drm_device *dev = crtc->dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 struct drm_i915_master_private *master_priv;
3163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3164 int pipe = intel_crtc->pipe;
3167 if (intel_crtc->dpms_mode == mode)
3170 intel_crtc->dpms_mode = mode;
3172 dev_priv->display.dpms(crtc, mode);
3174 if (!dev->primary->master)
3177 master_priv = dev->primary->master->driver_priv;
3178 if (!master_priv->sarea_priv)
3181 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3185 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3186 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3189 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3190 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3193 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3198 static void intel_crtc_disable(struct drm_crtc *crtc)
3200 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3201 struct drm_device *dev = crtc->dev;
3203 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3206 mutex_lock(&dev->struct_mutex);
3207 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3208 mutex_unlock(&dev->struct_mutex);
3212 /* Prepare for a mode set.
3214 * Note we could be a lot smarter here. We need to figure out which outputs
3215 * will be enabled, which disabled (in short, how the config will changes)
3216 * and perform the minimum necessary steps to accomplish that, e.g. updating
3217 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3218 * panel fitting is in the proper state, etc.
3220 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3222 i9xx_crtc_disable(crtc);
3225 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3227 i9xx_crtc_enable(crtc);
3230 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3232 ironlake_crtc_disable(crtc);
3235 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3237 ironlake_crtc_enable(crtc);
3240 void intel_encoder_prepare (struct drm_encoder *encoder)
3242 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3243 /* lvds has its own version of prepare see intel_lvds_prepare */
3244 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3247 void intel_encoder_commit (struct drm_encoder *encoder)
3249 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3250 /* lvds has its own version of commit see intel_lvds_commit */
3251 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3254 void intel_encoder_destroy(struct drm_encoder *encoder)
3256 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3258 drm_encoder_cleanup(encoder);
3259 kfree(intel_encoder);
3262 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3263 struct drm_display_mode *mode,
3264 struct drm_display_mode *adjusted_mode)
3266 struct drm_device *dev = crtc->dev;
3268 if (HAS_PCH_SPLIT(dev)) {
3269 /* FDI link clock is fixed at 2.7G */
3270 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3274 /* XXX some encoders set the crtcinfo, others don't.
3275 * Obviously we need some form of conflict resolution here...
3277 if (adjusted_mode->crtc_htotal == 0)
3278 drm_mode_set_crtcinfo(adjusted_mode, 0);
3283 static int i945_get_display_clock_speed(struct drm_device *dev)
3288 static int i915_get_display_clock_speed(struct drm_device *dev)
3293 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3298 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3302 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3304 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3307 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3308 case GC_DISPLAY_CLOCK_333_MHZ:
3311 case GC_DISPLAY_CLOCK_190_200_MHZ:
3317 static int i865_get_display_clock_speed(struct drm_device *dev)
3322 static int i855_get_display_clock_speed(struct drm_device *dev)
3325 /* Assume that the hardware is in the high speed state. This
3326 * should be the default.
3328 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3329 case GC_CLOCK_133_200:
3330 case GC_CLOCK_100_200:
3332 case GC_CLOCK_166_250:
3334 case GC_CLOCK_100_133:
3338 /* Shouldn't happen */
3342 static int i830_get_display_clock_speed(struct drm_device *dev)
3356 fdi_reduce_ratio(u32 *num, u32 *den)
3358 while (*num > 0xffffff || *den > 0xffffff) {
3365 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3366 int link_clock, struct fdi_m_n *m_n)
3368 m_n->tu = 64; /* default size */
3370 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3371 m_n->gmch_m = bits_per_pixel * pixel_clock;
3372 m_n->gmch_n = link_clock * nlanes * 8;
3373 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3375 m_n->link_m = pixel_clock;
3376 m_n->link_n = link_clock;
3377 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3381 struct intel_watermark_params {
3382 unsigned long fifo_size;
3383 unsigned long max_wm;
3384 unsigned long default_wm;
3385 unsigned long guard_size;
3386 unsigned long cacheline_size;
3389 /* Pineview has different values for various configs */
3390 static const struct intel_watermark_params pineview_display_wm = {
3391 PINEVIEW_DISPLAY_FIFO,
3395 PINEVIEW_FIFO_LINE_SIZE
3397 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3398 PINEVIEW_DISPLAY_FIFO,
3400 PINEVIEW_DFT_HPLLOFF_WM,
3402 PINEVIEW_FIFO_LINE_SIZE
3404 static const struct intel_watermark_params pineview_cursor_wm = {
3405 PINEVIEW_CURSOR_FIFO,
3406 PINEVIEW_CURSOR_MAX_WM,
3407 PINEVIEW_CURSOR_DFT_WM,
3408 PINEVIEW_CURSOR_GUARD_WM,
3409 PINEVIEW_FIFO_LINE_SIZE,
3411 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3412 PINEVIEW_CURSOR_FIFO,
3413 PINEVIEW_CURSOR_MAX_WM,
3414 PINEVIEW_CURSOR_DFT_WM,
3415 PINEVIEW_CURSOR_GUARD_WM,
3416 PINEVIEW_FIFO_LINE_SIZE
3418 static const struct intel_watermark_params g4x_wm_info = {
3425 static const struct intel_watermark_params g4x_cursor_wm_info = {
3432 static const struct intel_watermark_params i965_cursor_wm_info = {
3437 I915_FIFO_LINE_SIZE,
3439 static const struct intel_watermark_params i945_wm_info = {
3446 static const struct intel_watermark_params i915_wm_info = {
3453 static const struct intel_watermark_params i855_wm_info = {
3460 static const struct intel_watermark_params i830_wm_info = {
3468 static const struct intel_watermark_params ironlake_display_wm_info = {
3475 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3482 static const struct intel_watermark_params ironlake_display_srwm_info = {
3483 ILK_DISPLAY_SR_FIFO,
3484 ILK_DISPLAY_MAX_SRWM,
3485 ILK_DISPLAY_DFT_SRWM,
3489 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3491 ILK_CURSOR_MAX_SRWM,
3492 ILK_CURSOR_DFT_SRWM,
3497 static const struct intel_watermark_params sandybridge_display_wm_info = {
3504 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3511 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3512 SNB_DISPLAY_SR_FIFO,
3513 SNB_DISPLAY_MAX_SRWM,
3514 SNB_DISPLAY_DFT_SRWM,
3518 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3520 SNB_CURSOR_MAX_SRWM,
3521 SNB_CURSOR_DFT_SRWM,
3528 * intel_calculate_wm - calculate watermark level
3529 * @clock_in_khz: pixel clock
3530 * @wm: chip FIFO params
3531 * @pixel_size: display pixel size
3532 * @latency_ns: memory latency for the platform
3534 * Calculate the watermark level (the level at which the display plane will
3535 * start fetching from memory again). Each chip has a different display
3536 * FIFO size and allocation, so the caller needs to figure that out and pass
3537 * in the correct intel_watermark_params structure.
3539 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3540 * on the pixel size. When it reaches the watermark level, it'll start
3541 * fetching FIFO line sized based chunks from memory until the FIFO fills
3542 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3543 * will occur, and a display engine hang could result.
3545 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3546 const struct intel_watermark_params *wm,
3549 unsigned long latency_ns)
3551 long entries_required, wm_size;
3554 * Note: we need to make sure we don't overflow for various clock &
3556 * clocks go from a few thousand to several hundred thousand.
3557 * latency is usually a few thousand
3559 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3561 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3563 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3565 wm_size = fifo_size - (entries_required + wm->guard_size);
3567 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3569 /* Don't promote wm_size to unsigned... */
3570 if (wm_size > (long)wm->max_wm)
3571 wm_size = wm->max_wm;
3573 wm_size = wm->default_wm;
3577 struct cxsr_latency {
3580 unsigned long fsb_freq;
3581 unsigned long mem_freq;
3582 unsigned long display_sr;
3583 unsigned long display_hpll_disable;
3584 unsigned long cursor_sr;
3585 unsigned long cursor_hpll_disable;
3588 static const struct cxsr_latency cxsr_latency_table[] = {
3589 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3590 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3591 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3592 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3593 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3595 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3596 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3597 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3598 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3599 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3601 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3602 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3603 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3604 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3605 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3607 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3608 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3609 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3610 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3611 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3613 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3614 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3615 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3616 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3617 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3619 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3620 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3621 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3622 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3623 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3626 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3631 const struct cxsr_latency *latency;
3634 if (fsb == 0 || mem == 0)
3637 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3638 latency = &cxsr_latency_table[i];
3639 if (is_desktop == latency->is_desktop &&
3640 is_ddr3 == latency->is_ddr3 &&
3641 fsb == latency->fsb_freq && mem == latency->mem_freq)
3645 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3650 static void pineview_disable_cxsr(struct drm_device *dev)
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3654 /* deactivate cxsr */
3655 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3659 * Latency for FIFO fetches is dependent on several factors:
3660 * - memory configuration (speed, channels)
3662 * - current MCH state
3663 * It can be fairly high in some situations, so here we assume a fairly
3664 * pessimal value. It's a tradeoff between extra memory fetches (if we
3665 * set this value too high, the FIFO will fetch frequently to stay full)
3666 * and power consumption (set it too low to save power and we might see
3667 * FIFO underruns and display "flicker").
3669 * A value of 5us seems to be a good balance; safe for very low end
3670 * platforms but not overly aggressive on lower latency configs.
3672 static const int latency_ns = 5000;
3674 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 uint32_t dsparb = I915_READ(DSPARB);
3680 size = dsparb & 0x7f;
3682 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3684 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3685 plane ? "B" : "A", size);
3690 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 uint32_t dsparb = I915_READ(DSPARB);
3696 size = dsparb & 0x1ff;
3698 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3699 size >>= 1; /* Convert to cachelines */
3701 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3702 plane ? "B" : "A", size);
3707 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710 uint32_t dsparb = I915_READ(DSPARB);
3713 size = dsparb & 0x7f;
3714 size >>= 2; /* Convert to cachelines */
3716 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3723 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 uint32_t dsparb = I915_READ(DSPARB);
3729 size = dsparb & 0x7f;
3730 size >>= 1; /* Convert to cachelines */
3732 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3733 plane ? "B" : "A", size);
3738 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3740 struct drm_crtc *crtc, *enabled = NULL;
3742 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3743 if (crtc->enabled && crtc->fb) {
3753 static void pineview_update_wm(struct drm_device *dev)
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct drm_crtc *crtc;
3757 const struct cxsr_latency *latency;
3761 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3762 dev_priv->fsb_freq, dev_priv->mem_freq);
3764 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3765 pineview_disable_cxsr(dev);
3769 crtc = single_enabled_crtc(dev);
3771 int clock = crtc->mode.clock;
3772 int pixel_size = crtc->fb->bits_per_pixel / 8;
3775 wm = intel_calculate_wm(clock, &pineview_display_wm,
3776 pineview_display_wm.fifo_size,
3777 pixel_size, latency->display_sr);
3778 reg = I915_READ(DSPFW1);
3779 reg &= ~DSPFW_SR_MASK;
3780 reg |= wm << DSPFW_SR_SHIFT;
3781 I915_WRITE(DSPFW1, reg);
3782 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3785 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3786 pineview_display_wm.fifo_size,
3787 pixel_size, latency->cursor_sr);
3788 reg = I915_READ(DSPFW3);
3789 reg &= ~DSPFW_CURSOR_SR_MASK;
3790 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3791 I915_WRITE(DSPFW3, reg);
3793 /* Display HPLL off SR */
3794 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3795 pineview_display_hplloff_wm.fifo_size,
3796 pixel_size, latency->display_hpll_disable);
3797 reg = I915_READ(DSPFW3);
3798 reg &= ~DSPFW_HPLL_SR_MASK;
3799 reg |= wm & DSPFW_HPLL_SR_MASK;
3800 I915_WRITE(DSPFW3, reg);
3802 /* cursor HPLL off SR */
3803 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3804 pineview_display_hplloff_wm.fifo_size,
3805 pixel_size, latency->cursor_hpll_disable);
3806 reg = I915_READ(DSPFW3);
3807 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3808 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3809 I915_WRITE(DSPFW3, reg);
3810 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3814 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3815 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3817 pineview_disable_cxsr(dev);
3818 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3822 static bool g4x_compute_wm0(struct drm_device *dev,
3824 const struct intel_watermark_params *display,
3825 int display_latency_ns,
3826 const struct intel_watermark_params *cursor,
3827 int cursor_latency_ns,
3831 struct drm_crtc *crtc;
3832 int htotal, hdisplay, clock, pixel_size;
3833 int line_time_us, line_count;
3834 int entries, tlb_miss;
3836 crtc = intel_get_crtc_for_plane(dev, plane);
3837 if (crtc->fb == NULL || !crtc->enabled) {
3838 *cursor_wm = cursor->guard_size;
3839 *plane_wm = display->guard_size;
3843 htotal = crtc->mode.htotal;
3844 hdisplay = crtc->mode.hdisplay;
3845 clock = crtc->mode.clock;
3846 pixel_size = crtc->fb->bits_per_pixel / 8;
3848 /* Use the small buffer method to calculate plane watermark */
3849 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3850 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3852 entries += tlb_miss;
3853 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3854 *plane_wm = entries + display->guard_size;
3855 if (*plane_wm > (int)display->max_wm)
3856 *plane_wm = display->max_wm;
3858 /* Use the large buffer method to calculate cursor watermark */
3859 line_time_us = ((htotal * 1000) / clock);
3860 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3861 entries = line_count * 64 * pixel_size;
3862 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3864 entries += tlb_miss;
3865 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3866 *cursor_wm = entries + cursor->guard_size;
3867 if (*cursor_wm > (int)cursor->max_wm)
3868 *cursor_wm = (int)cursor->max_wm;
3874 * Check the wm result.
3876 * If any calculated watermark values is larger than the maximum value that
3877 * can be programmed into the associated watermark register, that watermark
3880 static bool g4x_check_srwm(struct drm_device *dev,
3881 int display_wm, int cursor_wm,
3882 const struct intel_watermark_params *display,
3883 const struct intel_watermark_params *cursor)
3885 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3886 display_wm, cursor_wm);
3888 if (display_wm > display->max_wm) {
3889 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3890 display_wm, display->max_wm);
3894 if (cursor_wm > cursor->max_wm) {
3895 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3896 cursor_wm, cursor->max_wm);
3900 if (!(display_wm || cursor_wm)) {
3901 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3908 static bool g4x_compute_srwm(struct drm_device *dev,
3911 const struct intel_watermark_params *display,
3912 const struct intel_watermark_params *cursor,
3913 int *display_wm, int *cursor_wm)
3915 struct drm_crtc *crtc;
3916 int hdisplay, htotal, pixel_size, clock;
3917 unsigned long line_time_us;
3918 int line_count, line_size;
3923 *display_wm = *cursor_wm = 0;
3927 crtc = intel_get_crtc_for_plane(dev, plane);
3928 hdisplay = crtc->mode.hdisplay;
3929 htotal = crtc->mode.htotal;
3930 clock = crtc->mode.clock;
3931 pixel_size = crtc->fb->bits_per_pixel / 8;
3933 line_time_us = (htotal * 1000) / clock;
3934 line_count = (latency_ns / line_time_us + 1000) / 1000;
3935 line_size = hdisplay * pixel_size;
3937 /* Use the minimum of the small and large buffer method for primary */
3938 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3939 large = line_count * line_size;
3941 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3942 *display_wm = entries + display->guard_size;
3944 /* calculate the self-refresh watermark for display cursor */
3945 entries = line_count * pixel_size * 64;
3946 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3947 *cursor_wm = entries + cursor->guard_size;
3949 return g4x_check_srwm(dev,
3950 *display_wm, *cursor_wm,
3954 #define single_plane_enabled(mask) is_power_of_2(mask)
3956 static void g4x_update_wm(struct drm_device *dev)
3958 static const int sr_latency_ns = 12000;
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3960 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3961 int plane_sr, cursor_sr;
3962 unsigned int enabled = 0;
3964 if (g4x_compute_wm0(dev, 0,
3965 &g4x_wm_info, latency_ns,
3966 &g4x_cursor_wm_info, latency_ns,
3967 &planea_wm, &cursora_wm))
3970 if (g4x_compute_wm0(dev, 1,
3971 &g4x_wm_info, latency_ns,
3972 &g4x_cursor_wm_info, latency_ns,
3973 &planeb_wm, &cursorb_wm))
3976 plane_sr = cursor_sr = 0;
3977 if (single_plane_enabled(enabled) &&
3978 g4x_compute_srwm(dev, ffs(enabled) - 1,
3981 &g4x_cursor_wm_info,
3982 &plane_sr, &cursor_sr))
3983 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3985 I915_WRITE(FW_BLC_SELF,
3986 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3988 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3989 planea_wm, cursora_wm,
3990 planeb_wm, cursorb_wm,
3991 plane_sr, cursor_sr);
3994 (plane_sr << DSPFW_SR_SHIFT) |
3995 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3996 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3999 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4000 (cursora_wm << DSPFW_CURSORA_SHIFT));
4001 /* HPLL off in SR has some issues on G4x... disable it */
4003 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4004 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4007 static void i965_update_wm(struct drm_device *dev)
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 struct drm_crtc *crtc;
4014 /* Calc sr entries for one plane configs */
4015 crtc = single_enabled_crtc(dev);
4017 /* self-refresh has much higher latency */
4018 static const int sr_latency_ns = 12000;
4019 int clock = crtc->mode.clock;
4020 int htotal = crtc->mode.htotal;
4021 int hdisplay = crtc->mode.hdisplay;
4022 int pixel_size = crtc->fb->bits_per_pixel / 8;
4023 unsigned long line_time_us;
4026 line_time_us = ((htotal * 1000) / clock);
4028 /* Use ns/us then divide to preserve precision */
4029 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4030 pixel_size * hdisplay;
4031 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4032 srwm = I965_FIFO_SIZE - entries;
4036 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4039 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4041 entries = DIV_ROUND_UP(entries,
4042 i965_cursor_wm_info.cacheline_size);
4043 cursor_sr = i965_cursor_wm_info.fifo_size -
4044 (entries + i965_cursor_wm_info.guard_size);
4046 if (cursor_sr > i965_cursor_wm_info.max_wm)
4047 cursor_sr = i965_cursor_wm_info.max_wm;
4049 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4050 "cursor %d\n", srwm, cursor_sr);
4052 if (IS_CRESTLINE(dev))
4053 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4055 /* Turn off self refresh if both pipes are enabled */
4056 if (IS_CRESTLINE(dev))
4057 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4061 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4064 /* 965 has limitations... */
4065 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4066 (8 << 16) | (8 << 8) | (8 << 0));
4067 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4068 /* update cursor SR watermark */
4069 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4072 static void i9xx_update_wm(struct drm_device *dev)
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 const struct intel_watermark_params *wm_info;
4080 int planea_wm, planeb_wm;
4081 struct drm_crtc *crtc, *enabled = NULL;
4084 wm_info = &i945_wm_info;
4085 else if (!IS_GEN2(dev))
4086 wm_info = &i915_wm_info;
4088 wm_info = &i855_wm_info;
4090 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4091 crtc = intel_get_crtc_for_plane(dev, 0);
4092 if (crtc->enabled && crtc->fb) {
4093 planea_wm = intel_calculate_wm(crtc->mode.clock,
4095 crtc->fb->bits_per_pixel / 8,
4099 planea_wm = fifo_size - wm_info->guard_size;
4101 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4102 crtc = intel_get_crtc_for_plane(dev, 1);
4103 if (crtc->enabled && crtc->fb) {
4104 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4106 crtc->fb->bits_per_pixel / 8,
4108 if (enabled == NULL)
4113 planeb_wm = fifo_size - wm_info->guard_size;
4115 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4118 * Overlay gets an aggressive default since video jitter is bad.
4122 /* Play safe and disable self-refresh before adjusting watermarks. */
4123 if (IS_I945G(dev) || IS_I945GM(dev))
4124 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4125 else if (IS_I915GM(dev))
4126 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4128 /* Calc sr entries for one plane configs */
4129 if (HAS_FW_BLC(dev) && enabled) {
4130 /* self-refresh has much higher latency */
4131 static const int sr_latency_ns = 6000;
4132 int clock = enabled->mode.clock;
4133 int htotal = enabled->mode.htotal;
4134 int hdisplay = enabled->mode.hdisplay;
4135 int pixel_size = enabled->fb->bits_per_pixel / 8;
4136 unsigned long line_time_us;
4139 line_time_us = (htotal * 1000) / clock;
4141 /* Use ns/us then divide to preserve precision */
4142 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4143 pixel_size * hdisplay;
4144 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4145 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4146 srwm = wm_info->fifo_size - entries;
4150 if (IS_I945G(dev) || IS_I945GM(dev))
4151 I915_WRITE(FW_BLC_SELF,
4152 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4153 else if (IS_I915GM(dev))
4154 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4157 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4158 planea_wm, planeb_wm, cwm, srwm);
4160 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4161 fwater_hi = (cwm & 0x1f);
4163 /* Set request length to 8 cachelines per fetch */
4164 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4165 fwater_hi = fwater_hi | (1 << 8);
4167 I915_WRITE(FW_BLC, fwater_lo);
4168 I915_WRITE(FW_BLC2, fwater_hi);
4170 if (HAS_FW_BLC(dev)) {
4172 if (IS_I945G(dev) || IS_I945GM(dev))
4173 I915_WRITE(FW_BLC_SELF,
4174 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4175 else if (IS_I915GM(dev))
4176 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4177 DRM_DEBUG_KMS("memory self refresh enabled\n");
4179 DRM_DEBUG_KMS("memory self refresh disabled\n");
4183 static void i830_update_wm(struct drm_device *dev)
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4186 struct drm_crtc *crtc;
4190 crtc = single_enabled_crtc(dev);
4194 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4195 dev_priv->display.get_fifo_size(dev, 0),
4196 crtc->fb->bits_per_pixel / 8,
4198 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4199 fwater_lo |= (3<<8) | planea_wm;
4201 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4203 I915_WRITE(FW_BLC, fwater_lo);
4206 #define ILK_LP0_PLANE_LATENCY 700
4207 #define ILK_LP0_CURSOR_LATENCY 1300
4210 * Check the wm result.
4212 * If any calculated watermark values is larger than the maximum value that
4213 * can be programmed into the associated watermark register, that watermark
4216 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4217 int fbc_wm, int display_wm, int cursor_wm,
4218 const struct intel_watermark_params *display,
4219 const struct intel_watermark_params *cursor)
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4223 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4224 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4226 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4227 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4228 fbc_wm, SNB_FBC_MAX_SRWM, level);
4230 /* fbc has it's own way to disable FBC WM */
4231 I915_WRITE(DISP_ARB_CTL,
4232 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4236 if (display_wm > display->max_wm) {
4237 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4238 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4242 if (cursor_wm > cursor->max_wm) {
4243 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4244 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4248 if (!(fbc_wm || display_wm || cursor_wm)) {
4249 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4257 * Compute watermark values of WM[1-3],
4259 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4261 const struct intel_watermark_params *display,
4262 const struct intel_watermark_params *cursor,
4263 int *fbc_wm, int *display_wm, int *cursor_wm)
4265 struct drm_crtc *crtc;
4266 unsigned long line_time_us;
4267 int hdisplay, htotal, pixel_size, clock;
4268 int line_count, line_size;
4273 *fbc_wm = *display_wm = *cursor_wm = 0;
4277 crtc = intel_get_crtc_for_plane(dev, plane);
4278 hdisplay = crtc->mode.hdisplay;
4279 htotal = crtc->mode.htotal;
4280 clock = crtc->mode.clock;
4281 pixel_size = crtc->fb->bits_per_pixel / 8;
4283 line_time_us = (htotal * 1000) / clock;
4284 line_count = (latency_ns / line_time_us + 1000) / 1000;
4285 line_size = hdisplay * pixel_size;
4287 /* Use the minimum of the small and large buffer method for primary */
4288 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4289 large = line_count * line_size;
4291 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4292 *display_wm = entries + display->guard_size;
4296 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4298 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4300 /* calculate the self-refresh watermark for display cursor */
4301 entries = line_count * pixel_size * 64;
4302 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4303 *cursor_wm = entries + cursor->guard_size;
4305 return ironlake_check_srwm(dev, level,
4306 *fbc_wm, *display_wm, *cursor_wm,
4310 static void ironlake_update_wm(struct drm_device *dev)
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int fbc_wm, plane_wm, cursor_wm;
4314 unsigned int enabled;
4317 if (g4x_compute_wm0(dev, 0,
4318 &ironlake_display_wm_info,
4319 ILK_LP0_PLANE_LATENCY,
4320 &ironlake_cursor_wm_info,
4321 ILK_LP0_CURSOR_LATENCY,
4322 &plane_wm, &cursor_wm)) {
4323 I915_WRITE(WM0_PIPEA_ILK,
4324 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4325 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4326 " plane %d, " "cursor: %d\n",
4327 plane_wm, cursor_wm);
4331 if (g4x_compute_wm0(dev, 1,
4332 &ironlake_display_wm_info,
4333 ILK_LP0_PLANE_LATENCY,
4334 &ironlake_cursor_wm_info,
4335 ILK_LP0_CURSOR_LATENCY,
4336 &plane_wm, &cursor_wm)) {
4337 I915_WRITE(WM0_PIPEB_ILK,
4338 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4339 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4340 " plane %d, cursor: %d\n",
4341 plane_wm, cursor_wm);
4346 * Calculate and update the self-refresh watermark only when one
4347 * display plane is used.
4349 I915_WRITE(WM3_LP_ILK, 0);
4350 I915_WRITE(WM2_LP_ILK, 0);
4351 I915_WRITE(WM1_LP_ILK, 0);
4353 if (!single_plane_enabled(enabled))
4355 enabled = ffs(enabled) - 1;
4358 if (!ironlake_compute_srwm(dev, 1, enabled,
4359 ILK_READ_WM1_LATENCY() * 500,
4360 &ironlake_display_srwm_info,
4361 &ironlake_cursor_srwm_info,
4362 &fbc_wm, &plane_wm, &cursor_wm))
4365 I915_WRITE(WM1_LP_ILK,
4367 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4368 (fbc_wm << WM1_LP_FBC_SHIFT) |
4369 (plane_wm << WM1_LP_SR_SHIFT) |
4373 if (!ironlake_compute_srwm(dev, 2, enabled,
4374 ILK_READ_WM2_LATENCY() * 500,
4375 &ironlake_display_srwm_info,
4376 &ironlake_cursor_srwm_info,
4377 &fbc_wm, &plane_wm, &cursor_wm))
4380 I915_WRITE(WM2_LP_ILK,
4382 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4383 (fbc_wm << WM1_LP_FBC_SHIFT) |
4384 (plane_wm << WM1_LP_SR_SHIFT) |
4388 * WM3 is unsupported on ILK, probably because we don't have latency
4389 * data for that power state
4393 static void sandybridge_update_wm(struct drm_device *dev)
4395 struct drm_i915_private *dev_priv = dev->dev_private;
4396 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4397 int fbc_wm, plane_wm, cursor_wm;
4398 unsigned int enabled;
4401 if (g4x_compute_wm0(dev, 0,
4402 &sandybridge_display_wm_info, latency,
4403 &sandybridge_cursor_wm_info, latency,
4404 &plane_wm, &cursor_wm)) {
4405 I915_WRITE(WM0_PIPEA_ILK,
4406 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4407 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4408 " plane %d, " "cursor: %d\n",
4409 plane_wm, cursor_wm);
4413 if (g4x_compute_wm0(dev, 1,
4414 &sandybridge_display_wm_info, latency,
4415 &sandybridge_cursor_wm_info, latency,
4416 &plane_wm, &cursor_wm)) {
4417 I915_WRITE(WM0_PIPEB_ILK,
4418 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4419 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4420 " plane %d, cursor: %d\n",
4421 plane_wm, cursor_wm);
4426 * Calculate and update the self-refresh watermark only when one
4427 * display plane is used.
4429 * SNB support 3 levels of watermark.
4431 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4432 * and disabled in the descending order
4435 I915_WRITE(WM3_LP_ILK, 0);
4436 I915_WRITE(WM2_LP_ILK, 0);
4437 I915_WRITE(WM1_LP_ILK, 0);
4439 if (!single_plane_enabled(enabled))
4441 enabled = ffs(enabled) - 1;
4444 if (!ironlake_compute_srwm(dev, 1, enabled,
4445 SNB_READ_WM1_LATENCY() * 500,
4446 &sandybridge_display_srwm_info,
4447 &sandybridge_cursor_srwm_info,
4448 &fbc_wm, &plane_wm, &cursor_wm))
4451 I915_WRITE(WM1_LP_ILK,
4453 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4454 (fbc_wm << WM1_LP_FBC_SHIFT) |
4455 (plane_wm << WM1_LP_SR_SHIFT) |
4459 if (!ironlake_compute_srwm(dev, 2, enabled,
4460 SNB_READ_WM2_LATENCY() * 500,
4461 &sandybridge_display_srwm_info,
4462 &sandybridge_cursor_srwm_info,
4463 &fbc_wm, &plane_wm, &cursor_wm))
4466 I915_WRITE(WM2_LP_ILK,
4468 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4469 (fbc_wm << WM1_LP_FBC_SHIFT) |
4470 (plane_wm << WM1_LP_SR_SHIFT) |
4474 if (!ironlake_compute_srwm(dev, 3, enabled,
4475 SNB_READ_WM3_LATENCY() * 500,
4476 &sandybridge_display_srwm_info,
4477 &sandybridge_cursor_srwm_info,
4478 &fbc_wm, &plane_wm, &cursor_wm))
4481 I915_WRITE(WM3_LP_ILK,
4483 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4484 (fbc_wm << WM1_LP_FBC_SHIFT) |
4485 (plane_wm << WM1_LP_SR_SHIFT) |
4490 * intel_update_watermarks - update FIFO watermark values based on current modes
4492 * Calculate watermark values for the various WM regs based on current mode
4493 * and plane configuration.
4495 * There are several cases to deal with here:
4496 * - normal (i.e. non-self-refresh)
4497 * - self-refresh (SR) mode
4498 * - lines are large relative to FIFO size (buffer can hold up to 2)
4499 * - lines are small relative to FIFO size (buffer can hold more than 2
4500 * lines), so need to account for TLB latency
4502 * The normal calculation is:
4503 * watermark = dotclock * bytes per pixel * latency
4504 * where latency is platform & configuration dependent (we assume pessimal
4507 * The SR calculation is:
4508 * watermark = (trunc(latency/line time)+1) * surface width *
4511 * line time = htotal / dotclock
4512 * surface width = hdisplay for normal plane and 64 for cursor
4513 * and latency is assumed to be high, as above.
4515 * The final value programmed to the register should always be rounded up,
4516 * and include an extra 2 entries to account for clock crossings.
4518 * We don't use the sprite, so we can ignore that. And on Crestline we have
4519 * to set the non-SR watermarks to 8.
4521 static void intel_update_watermarks(struct drm_device *dev)
4523 struct drm_i915_private *dev_priv = dev->dev_private;
4525 if (dev_priv->display.update_wm)
4526 dev_priv->display.update_wm(dev);
4529 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4531 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4532 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4536 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4537 * @crtc: CRTC structure
4539 * A pipe may be connected to one or more outputs. Based on the depth of the
4540 * attached framebuffer, choose a good color depth to use on the pipe.
4542 * If possible, match the pipe depth to the fb depth. In some cases, this
4543 * isn't ideal, because the connected output supports a lesser or restricted
4544 * set of depths. Resolve that here:
4545 * LVDS typically supports only 6bpc, so clamp down in that case
4546 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4547 * Displays may support a restricted set as well, check EDID and clamp as
4551 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4552 * true if they don't match).
4554 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4555 unsigned int *pipe_bpp)
4557 struct drm_device *dev = crtc->dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 struct drm_encoder *encoder;
4560 struct drm_connector *connector;
4561 unsigned int display_bpc = UINT_MAX, bpc;
4563 /* Walk the encoders & connectors on this crtc, get min bpc */
4564 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4565 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4567 if (encoder->crtc != crtc)
4570 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4571 unsigned int lvds_bpc;
4573 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4579 if (lvds_bpc < display_bpc) {
4580 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4581 display_bpc = lvds_bpc;
4586 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4587 /* Use VBT settings if we have an eDP panel */
4588 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4590 if (edp_bpc < display_bpc) {
4591 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4592 display_bpc = edp_bpc;
4597 /* Not one of the known troublemakers, check the EDID */
4598 list_for_each_entry(connector, &dev->mode_config.connector_list,
4600 if (connector->encoder != encoder)
4603 /* Don't use an invalid EDID bpc value */
4604 if (connector->display_info.bpc &&
4605 connector->display_info.bpc < display_bpc) {
4606 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4607 display_bpc = connector->display_info.bpc;
4612 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4613 * through, clamp it down. (Note: >12bpc will be caught below.)
4615 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4616 if (display_bpc > 8 && display_bpc < 12) {
4617 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4620 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4627 * We could just drive the pipe at the highest bpc all the time and
4628 * enable dithering as needed, but that costs bandwidth. So choose
4629 * the minimum value that expresses the full color range of the fb but
4630 * also stays within the max display bpc discovered above.
4633 switch (crtc->fb->depth) {
4635 bpc = 8; /* since we go through a colormap */
4639 bpc = 6; /* min is 18bpp */
4642 bpc = min((unsigned int)8, display_bpc);
4645 bpc = min((unsigned int)10, display_bpc);
4648 bpc = min((unsigned int)12, display_bpc);
4651 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4652 bpc = min((unsigned int)8, display_bpc);
4656 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4659 *pipe_bpp = bpc * 3;
4661 return display_bpc != bpc;
4664 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4665 struct drm_display_mode *mode,
4666 struct drm_display_mode *adjusted_mode,
4668 struct drm_framebuffer *old_fb)
4670 struct drm_device *dev = crtc->dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4673 int pipe = intel_crtc->pipe;
4674 int plane = intel_crtc->plane;
4675 int refclk, num_connectors = 0;
4676 intel_clock_t clock, reduced_clock;
4677 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4678 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4679 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4680 struct drm_mode_config *mode_config = &dev->mode_config;
4681 struct intel_encoder *encoder;
4682 const intel_limit_t *limit;
4687 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4688 if (encoder->base.crtc != crtc)
4691 switch (encoder->type) {
4692 case INTEL_OUTPUT_LVDS:
4695 case INTEL_OUTPUT_SDVO:
4696 case INTEL_OUTPUT_HDMI:
4698 if (encoder->needs_tv_clock)
4701 case INTEL_OUTPUT_DVO:
4704 case INTEL_OUTPUT_TVOUT:
4707 case INTEL_OUTPUT_ANALOG:
4710 case INTEL_OUTPUT_DISPLAYPORT:
4718 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4719 refclk = dev_priv->lvds_ssc_freq * 1000;
4720 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4722 } else if (!IS_GEN2(dev)) {
4729 * Returns a set of divisors for the desired target clock with the given
4730 * refclk, or FALSE. The returned values represent the clock equation:
4731 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4733 limit = intel_limit(crtc, refclk);
4734 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4736 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4740 /* Ensure that the cursor is valid for the new mode before changing... */
4741 intel_crtc_update_cursor(crtc, true);
4743 if (is_lvds && dev_priv->lvds_downclock_avail) {
4744 has_reduced_clock = limit->find_pll(limit, crtc,
4745 dev_priv->lvds_downclock,
4748 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4750 * If the different P is found, it means that we can't
4751 * switch the display clock by using the FP0/FP1.
4752 * In such case we will disable the LVDS downclock
4755 DRM_DEBUG_KMS("Different P is found for "
4756 "LVDS clock/downclock\n");
4757 has_reduced_clock = 0;
4760 /* SDVO TV has fixed PLL values depend on its clock range,
4761 this mirrors vbios setting. */
4762 if (is_sdvo && is_tv) {
4763 if (adjusted_mode->clock >= 100000
4764 && adjusted_mode->clock < 140500) {
4770 } else if (adjusted_mode->clock >= 140500
4771 && adjusted_mode->clock <= 200000) {
4780 if (IS_PINEVIEW(dev)) {
4781 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4782 if (has_reduced_clock)
4783 fp2 = (1 << reduced_clock.n) << 16 |
4784 reduced_clock.m1 << 8 | reduced_clock.m2;
4786 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4787 if (has_reduced_clock)
4788 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4792 dpll = DPLL_VGA_MODE_DIS;
4794 if (!IS_GEN2(dev)) {
4796 dpll |= DPLLB_MODE_LVDS;
4798 dpll |= DPLLB_MODE_DAC_SERIAL;
4800 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4801 if (pixel_multiplier > 1) {
4802 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4803 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4805 dpll |= DPLL_DVO_HIGH_SPEED;
4808 dpll |= DPLL_DVO_HIGH_SPEED;
4810 /* compute bitmask from p1 value */
4811 if (IS_PINEVIEW(dev))
4812 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4814 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4815 if (IS_G4X(dev) && has_reduced_clock)
4816 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4820 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4823 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4826 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4829 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4832 if (INTEL_INFO(dev)->gen >= 4)
4833 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4836 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4839 dpll |= PLL_P1_DIVIDE_BY_TWO;
4841 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4843 dpll |= PLL_P2_DIVIDE_BY_4;
4847 if (is_sdvo && is_tv)
4848 dpll |= PLL_REF_INPUT_TVCLKINBC;
4850 /* XXX: just matching BIOS for now */
4851 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4853 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4854 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4856 dpll |= PLL_REF_INPUT_DREFCLK;
4858 /* setup pipeconf */
4859 pipeconf = I915_READ(PIPECONF(pipe));
4861 /* Set up the display plane register */
4862 dspcntr = DISPPLANE_GAMMA_ENABLE;
4864 /* Ironlake's plane is forced to pipe, bit 24 is to
4865 enable color space conversion */
4867 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4869 dspcntr |= DISPPLANE_SEL_PIPE_B;
4871 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4872 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4875 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4879 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4880 pipeconf |= PIPECONF_DOUBLE_WIDE;
4882 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4885 dpll |= DPLL_VCO_ENABLE;
4887 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4888 drm_mode_debug_printmodeline(mode);
4890 I915_WRITE(FP0(pipe), fp);
4891 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4893 POSTING_READ(DPLL(pipe));
4896 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4897 * This is an exception to the general rule that mode_set doesn't turn
4901 temp = I915_READ(LVDS);
4902 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4904 temp |= LVDS_PIPEB_SELECT;
4906 temp &= ~LVDS_PIPEB_SELECT;
4908 /* set the corresponsding LVDS_BORDER bit */
4909 temp |= dev_priv->lvds_border_bits;
4910 /* Set the B0-B3 data pairs corresponding to whether we're going to
4911 * set the DPLLs for dual-channel mode or not.
4914 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4916 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4918 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4919 * appropriately here, but we need to look more thoroughly into how
4920 * panels behave in the two modes.
4922 /* set the dithering flag on LVDS as needed */
4923 if (INTEL_INFO(dev)->gen >= 4) {
4924 if (dev_priv->lvds_dither)
4925 temp |= LVDS_ENABLE_DITHER;
4927 temp &= ~LVDS_ENABLE_DITHER;
4929 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4930 lvds_sync |= LVDS_HSYNC_POLARITY;
4931 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4932 lvds_sync |= LVDS_VSYNC_POLARITY;
4933 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4935 char flags[2] = "-+";
4936 DRM_INFO("Changing LVDS panel from "
4937 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4938 flags[!(temp & LVDS_HSYNC_POLARITY)],
4939 flags[!(temp & LVDS_VSYNC_POLARITY)],
4940 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4941 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4942 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4945 I915_WRITE(LVDS, temp);
4949 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4952 I915_WRITE(DPLL(pipe), dpll);
4954 /* Wait for the clocks to stabilize. */
4955 POSTING_READ(DPLL(pipe));
4958 if (INTEL_INFO(dev)->gen >= 4) {
4961 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4963 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4967 I915_WRITE(DPLL_MD(pipe), temp);
4969 /* The pixel multiplier can only be updated once the
4970 * DPLL is enabled and the clocks are stable.
4972 * So write it again.
4974 I915_WRITE(DPLL(pipe), dpll);
4977 intel_crtc->lowfreq_avail = false;
4978 if (is_lvds && has_reduced_clock && i915_powersave) {
4979 I915_WRITE(FP1(pipe), fp2);
4980 intel_crtc->lowfreq_avail = true;
4981 if (HAS_PIPE_CXSR(dev)) {
4982 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4983 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4986 I915_WRITE(FP1(pipe), fp);
4987 if (HAS_PIPE_CXSR(dev)) {
4988 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4989 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4993 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4994 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4995 /* the chip adds 2 halflines automatically */
4996 adjusted_mode->crtc_vdisplay -= 1;
4997 adjusted_mode->crtc_vtotal -= 1;
4998 adjusted_mode->crtc_vblank_start -= 1;
4999 adjusted_mode->crtc_vblank_end -= 1;
5000 adjusted_mode->crtc_vsync_end -= 1;
5001 adjusted_mode->crtc_vsync_start -= 1;
5003 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5005 I915_WRITE(HTOTAL(pipe),
5006 (adjusted_mode->crtc_hdisplay - 1) |
5007 ((adjusted_mode->crtc_htotal - 1) << 16));
5008 I915_WRITE(HBLANK(pipe),
5009 (adjusted_mode->crtc_hblank_start - 1) |
5010 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5011 I915_WRITE(HSYNC(pipe),
5012 (adjusted_mode->crtc_hsync_start - 1) |
5013 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5015 I915_WRITE(VTOTAL(pipe),
5016 (adjusted_mode->crtc_vdisplay - 1) |
5017 ((adjusted_mode->crtc_vtotal - 1) << 16));
5018 I915_WRITE(VBLANK(pipe),
5019 (adjusted_mode->crtc_vblank_start - 1) |
5020 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5021 I915_WRITE(VSYNC(pipe),
5022 (adjusted_mode->crtc_vsync_start - 1) |
5023 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5025 /* pipesrc and dspsize control the size that is scaled from,
5026 * which should always be the user's requested size.
5028 I915_WRITE(DSPSIZE(plane),
5029 ((mode->vdisplay - 1) << 16) |
5030 (mode->hdisplay - 1));
5031 I915_WRITE(DSPPOS(plane), 0);
5032 I915_WRITE(PIPESRC(pipe),
5033 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5035 I915_WRITE(PIPECONF(pipe), pipeconf);
5036 POSTING_READ(PIPECONF(pipe));
5037 intel_enable_pipe(dev_priv, pipe, false);
5039 intel_wait_for_vblank(dev, pipe);
5041 I915_WRITE(DSPCNTR(plane), dspcntr);
5042 POSTING_READ(DSPCNTR(plane));
5043 intel_enable_plane(dev_priv, plane, pipe);
5045 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5047 intel_update_watermarks(dev);
5052 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5053 struct drm_display_mode *mode,
5054 struct drm_display_mode *adjusted_mode,
5056 struct drm_framebuffer *old_fb)
5058 struct drm_device *dev = crtc->dev;
5059 struct drm_i915_private *dev_priv = dev->dev_private;
5060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5061 int pipe = intel_crtc->pipe;
5062 int plane = intel_crtc->plane;
5063 int refclk, num_connectors = 0;
5064 intel_clock_t clock, reduced_clock;
5065 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5066 bool ok, has_reduced_clock = false, is_sdvo = false;
5067 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5068 struct intel_encoder *has_edp_encoder = NULL;
5069 struct drm_mode_config *mode_config = &dev->mode_config;
5070 struct intel_encoder *encoder;
5071 const intel_limit_t *limit;
5073 struct fdi_m_n m_n = {0};
5076 int target_clock, pixel_multiplier, lane, link_bw, factor;
5077 unsigned int pipe_bpp;
5080 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5081 if (encoder->base.crtc != crtc)
5084 switch (encoder->type) {
5085 case INTEL_OUTPUT_LVDS:
5088 case INTEL_OUTPUT_SDVO:
5089 case INTEL_OUTPUT_HDMI:
5091 if (encoder->needs_tv_clock)
5094 case INTEL_OUTPUT_TVOUT:
5097 case INTEL_OUTPUT_ANALOG:
5100 case INTEL_OUTPUT_DISPLAYPORT:
5103 case INTEL_OUTPUT_EDP:
5104 has_edp_encoder = encoder;
5111 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5112 refclk = dev_priv->lvds_ssc_freq * 1000;
5113 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5117 if (!has_edp_encoder ||
5118 intel_encoder_is_pch_edp(&has_edp_encoder->base))
5119 refclk = 120000; /* 120Mhz refclk */
5123 * Returns a set of divisors for the desired target clock with the given
5124 * refclk, or FALSE. The returned values represent the clock equation:
5125 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5127 limit = intel_limit(crtc, refclk);
5128 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5130 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5134 /* Ensure that the cursor is valid for the new mode before changing... */
5135 intel_crtc_update_cursor(crtc, true);
5137 if (is_lvds && dev_priv->lvds_downclock_avail) {
5138 has_reduced_clock = limit->find_pll(limit, crtc,
5139 dev_priv->lvds_downclock,
5142 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5144 * If the different P is found, it means that we can't
5145 * switch the display clock by using the FP0/FP1.
5146 * In such case we will disable the LVDS downclock
5149 DRM_DEBUG_KMS("Different P is found for "
5150 "LVDS clock/downclock\n");
5151 has_reduced_clock = 0;
5154 /* SDVO TV has fixed PLL values depend on its clock range,
5155 this mirrors vbios setting. */
5156 if (is_sdvo && is_tv) {
5157 if (adjusted_mode->clock >= 100000
5158 && adjusted_mode->clock < 140500) {
5164 } else if (adjusted_mode->clock >= 140500
5165 && adjusted_mode->clock <= 200000) {
5175 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5177 /* CPU eDP doesn't require FDI link, so just set DP M/N
5178 according to current link config */
5179 if (has_edp_encoder &&
5180 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5181 target_clock = mode->clock;
5182 intel_edp_link_config(has_edp_encoder,
5185 /* [e]DP over FDI requires target mode clock
5186 instead of link clock */
5187 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5188 target_clock = mode->clock;
5190 target_clock = adjusted_mode->clock;
5192 /* FDI is a binary signal running at ~2.7GHz, encoding
5193 * each output octet as 10 bits. The actual frequency
5194 * is stored as a divider into a 100MHz clock, and the
5195 * mode pixel clock is stored in units of 1KHz.
5196 * Hence the bw of each lane in terms of the mode signal
5199 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5202 /* determine panel color depth */
5203 temp = I915_READ(PIPECONF(pipe));
5204 temp &= ~PIPE_BPC_MASK;
5205 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5220 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5227 intel_crtc->bpp = pipe_bpp;
5228 I915_WRITE(PIPECONF(pipe), temp);
5232 * Account for spread spectrum to avoid
5233 * oversubscribing the link. Max center spread
5234 * is 2.5%; use 5% for safety's sake.
5236 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5237 lane = bps / (link_bw * 8) + 1;
5240 intel_crtc->fdi_lanes = lane;
5242 if (pixel_multiplier > 1)
5243 link_bw *= pixel_multiplier;
5244 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5247 /* Ironlake: try to setup display ref clock before DPLL
5248 * enabling. This is only under driver's control after
5249 * PCH B stepping, previous chipset stepping should be
5250 * ignoring this setting.
5252 temp = I915_READ(PCH_DREF_CONTROL);
5253 /* Always enable nonspread source */
5254 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5255 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5256 temp &= ~DREF_SSC_SOURCE_MASK;
5257 temp |= DREF_SSC_SOURCE_ENABLE;
5258 I915_WRITE(PCH_DREF_CONTROL, temp);
5260 POSTING_READ(PCH_DREF_CONTROL);
5263 if (has_edp_encoder) {
5264 if (intel_panel_use_ssc(dev_priv)) {
5265 temp |= DREF_SSC1_ENABLE;
5266 I915_WRITE(PCH_DREF_CONTROL, temp);
5268 POSTING_READ(PCH_DREF_CONTROL);
5271 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5273 /* Enable CPU source on CPU attached eDP */
5274 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5275 if (intel_panel_use_ssc(dev_priv))
5276 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5278 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5280 /* Enable SSC on PCH eDP if needed */
5281 if (intel_panel_use_ssc(dev_priv)) {
5282 DRM_ERROR("enabling SSC on PCH\n");
5283 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5286 I915_WRITE(PCH_DREF_CONTROL, temp);
5287 POSTING_READ(PCH_DREF_CONTROL);
5291 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5292 if (has_reduced_clock)
5293 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5296 /* Enable autotuning of the PLL clock (if permissible) */
5299 if ((intel_panel_use_ssc(dev_priv) &&
5300 dev_priv->lvds_ssc_freq == 100) ||
5301 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5303 } else if (is_sdvo && is_tv)
5306 if (clock.m < factor * clock.n)
5312 dpll |= DPLLB_MODE_LVDS;
5314 dpll |= DPLLB_MODE_DAC_SERIAL;
5316 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5317 if (pixel_multiplier > 1) {
5318 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5320 dpll |= DPLL_DVO_HIGH_SPEED;
5322 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5323 dpll |= DPLL_DVO_HIGH_SPEED;
5325 /* compute bitmask from p1 value */
5326 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5328 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5332 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5335 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5338 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5341 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5345 if (is_sdvo && is_tv)
5346 dpll |= PLL_REF_INPUT_TVCLKINBC;
5348 /* XXX: just matching BIOS for now */
5349 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5351 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5352 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5354 dpll |= PLL_REF_INPUT_DREFCLK;
5356 /* setup pipeconf */
5357 pipeconf = I915_READ(PIPECONF(pipe));
5359 /* Set up the display plane register */
5360 dspcntr = DISPPLANE_GAMMA_ENABLE;
5362 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5363 drm_mode_debug_printmodeline(mode);
5365 /* PCH eDP needs FDI, but CPU eDP does not */
5366 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5367 I915_WRITE(PCH_FP0(pipe), fp);
5368 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5370 POSTING_READ(PCH_DPLL(pipe));
5374 /* enable transcoder DPLL */
5375 if (HAS_PCH_CPT(dev)) {
5376 temp = I915_READ(PCH_DPLL_SEL);
5379 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5382 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5385 /* FIXME: manage transcoder PLLs? */
5386 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5391 I915_WRITE(PCH_DPLL_SEL, temp);
5393 POSTING_READ(PCH_DPLL_SEL);
5397 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5398 * This is an exception to the general rule that mode_set doesn't turn
5402 temp = I915_READ(PCH_LVDS);
5403 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5405 if (HAS_PCH_CPT(dev))
5406 temp |= PORT_TRANS_B_SEL_CPT;
5408 temp |= LVDS_PIPEB_SELECT;
5410 if (HAS_PCH_CPT(dev))
5411 temp &= ~PORT_TRANS_SEL_MASK;
5413 temp &= ~LVDS_PIPEB_SELECT;
5415 /* set the corresponsding LVDS_BORDER bit */
5416 temp |= dev_priv->lvds_border_bits;
5417 /* Set the B0-B3 data pairs corresponding to whether we're going to
5418 * set the DPLLs for dual-channel mode or not.
5421 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5423 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5425 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5426 * appropriately here, but we need to look more thoroughly into how
5427 * panels behave in the two modes.
5429 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5430 lvds_sync |= LVDS_HSYNC_POLARITY;
5431 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5432 lvds_sync |= LVDS_VSYNC_POLARITY;
5433 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5435 char flags[2] = "-+";
5436 DRM_INFO("Changing LVDS panel from "
5437 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5438 flags[!(temp & LVDS_HSYNC_POLARITY)],
5439 flags[!(temp & LVDS_VSYNC_POLARITY)],
5440 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5441 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5442 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5445 I915_WRITE(PCH_LVDS, temp);
5448 pipeconf &= ~PIPECONF_DITHER_EN;
5449 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5450 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5451 pipeconf |= PIPECONF_DITHER_EN;
5452 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5454 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5455 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5457 /* For non-DP output, clear any trans DP clock recovery setting.*/
5458 I915_WRITE(TRANSDATA_M1(pipe), 0);
5459 I915_WRITE(TRANSDATA_N1(pipe), 0);
5460 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5461 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5464 if (!has_edp_encoder ||
5465 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5466 I915_WRITE(PCH_DPLL(pipe), dpll);
5468 /* Wait for the clocks to stabilize. */
5469 POSTING_READ(PCH_DPLL(pipe));
5472 /* The pixel multiplier can only be updated once the
5473 * DPLL is enabled and the clocks are stable.
5475 * So write it again.
5477 I915_WRITE(PCH_DPLL(pipe), dpll);
5480 intel_crtc->lowfreq_avail = false;
5481 if (is_lvds && has_reduced_clock && i915_powersave) {
5482 I915_WRITE(PCH_FP1(pipe), fp2);
5483 intel_crtc->lowfreq_avail = true;
5484 if (HAS_PIPE_CXSR(dev)) {
5485 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5486 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5489 I915_WRITE(PCH_FP1(pipe), fp);
5490 if (HAS_PIPE_CXSR(dev)) {
5491 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5492 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5496 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5497 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5498 /* the chip adds 2 halflines automatically */
5499 adjusted_mode->crtc_vdisplay -= 1;
5500 adjusted_mode->crtc_vtotal -= 1;
5501 adjusted_mode->crtc_vblank_start -= 1;
5502 adjusted_mode->crtc_vblank_end -= 1;
5503 adjusted_mode->crtc_vsync_end -= 1;
5504 adjusted_mode->crtc_vsync_start -= 1;
5506 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5508 I915_WRITE(HTOTAL(pipe),
5509 (adjusted_mode->crtc_hdisplay - 1) |
5510 ((adjusted_mode->crtc_htotal - 1) << 16));
5511 I915_WRITE(HBLANK(pipe),
5512 (adjusted_mode->crtc_hblank_start - 1) |
5513 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5514 I915_WRITE(HSYNC(pipe),
5515 (adjusted_mode->crtc_hsync_start - 1) |
5516 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5518 I915_WRITE(VTOTAL(pipe),
5519 (adjusted_mode->crtc_vdisplay - 1) |
5520 ((adjusted_mode->crtc_vtotal - 1) << 16));
5521 I915_WRITE(VBLANK(pipe),
5522 (adjusted_mode->crtc_vblank_start - 1) |
5523 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5524 I915_WRITE(VSYNC(pipe),
5525 (adjusted_mode->crtc_vsync_start - 1) |
5526 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5528 /* pipesrc controls the size that is scaled from, which should
5529 * always be the user's requested size.
5531 I915_WRITE(PIPESRC(pipe),
5532 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5534 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5535 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5536 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5537 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5539 if (has_edp_encoder &&
5540 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5541 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5544 I915_WRITE(PIPECONF(pipe), pipeconf);
5545 POSTING_READ(PIPECONF(pipe));
5547 intel_wait_for_vblank(dev, pipe);
5550 /* enable address swizzle for tiling buffer */
5551 temp = I915_READ(DISP_ARB_CTL);
5552 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5555 I915_WRITE(DSPCNTR(plane), dspcntr);
5556 POSTING_READ(DSPCNTR(plane));
5558 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5560 intel_update_watermarks(dev);
5565 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5566 struct drm_display_mode *mode,
5567 struct drm_display_mode *adjusted_mode,
5569 struct drm_framebuffer *old_fb)
5571 struct drm_device *dev = crtc->dev;
5572 struct drm_i915_private *dev_priv = dev->dev_private;
5573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5574 int pipe = intel_crtc->pipe;
5577 drm_vblank_pre_modeset(dev, pipe);
5579 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5582 drm_vblank_post_modeset(dev, pipe);
5584 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5589 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5590 void intel_crtc_load_lut(struct drm_crtc *crtc)
5592 struct drm_device *dev = crtc->dev;
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5595 int palreg = PALETTE(intel_crtc->pipe);
5598 /* The clocks have to be on to load the palette. */
5602 /* use legacy palette for Ironlake */
5603 if (HAS_PCH_SPLIT(dev))
5604 palreg = LGC_PALETTE(intel_crtc->pipe);
5606 for (i = 0; i < 256; i++) {
5607 I915_WRITE(palreg + 4 * i,
5608 (intel_crtc->lut_r[i] << 16) |
5609 (intel_crtc->lut_g[i] << 8) |
5610 intel_crtc->lut_b[i]);
5614 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5616 struct drm_device *dev = crtc->dev;
5617 struct drm_i915_private *dev_priv = dev->dev_private;
5618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5619 bool visible = base != 0;
5622 if (intel_crtc->cursor_visible == visible)
5625 cntl = I915_READ(_CURACNTR);
5627 /* On these chipsets we can only modify the base whilst
5628 * the cursor is disabled.
5630 I915_WRITE(_CURABASE, base);
5632 cntl &= ~(CURSOR_FORMAT_MASK);
5633 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5634 cntl |= CURSOR_ENABLE |
5635 CURSOR_GAMMA_ENABLE |
5638 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5639 I915_WRITE(_CURACNTR, cntl);
5641 intel_crtc->cursor_visible = visible;
5644 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5646 struct drm_device *dev = crtc->dev;
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5649 int pipe = intel_crtc->pipe;
5650 bool visible = base != 0;
5652 if (intel_crtc->cursor_visible != visible) {
5653 uint32_t cntl = I915_READ(CURCNTR(pipe));
5655 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5656 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5657 cntl |= pipe << 28; /* Connect to correct pipe */
5659 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5660 cntl |= CURSOR_MODE_DISABLE;
5662 I915_WRITE(CURCNTR(pipe), cntl);
5664 intel_crtc->cursor_visible = visible;
5666 /* and commit changes on next vblank */
5667 I915_WRITE(CURBASE(pipe), base);
5670 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5671 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5674 struct drm_device *dev = crtc->dev;
5675 struct drm_i915_private *dev_priv = dev->dev_private;
5676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5677 int pipe = intel_crtc->pipe;
5678 int x = intel_crtc->cursor_x;
5679 int y = intel_crtc->cursor_y;
5685 if (on && crtc->enabled && crtc->fb) {
5686 base = intel_crtc->cursor_addr;
5687 if (x > (int) crtc->fb->width)
5690 if (y > (int) crtc->fb->height)
5696 if (x + intel_crtc->cursor_width < 0)
5699 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5702 pos |= x << CURSOR_X_SHIFT;
5705 if (y + intel_crtc->cursor_height < 0)
5708 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5711 pos |= y << CURSOR_Y_SHIFT;
5713 visible = base != 0;
5714 if (!visible && !intel_crtc->cursor_visible)
5717 I915_WRITE(CURPOS(pipe), pos);
5718 if (IS_845G(dev) || IS_I865G(dev))
5719 i845_update_cursor(crtc, base);
5721 i9xx_update_cursor(crtc, base);
5724 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5727 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5728 struct drm_file *file,
5730 uint32_t width, uint32_t height)
5732 struct drm_device *dev = crtc->dev;
5733 struct drm_i915_private *dev_priv = dev->dev_private;
5734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5735 struct drm_i915_gem_object *obj;
5739 DRM_DEBUG_KMS("\n");
5741 /* if we want to turn off the cursor ignore width and height */
5743 DRM_DEBUG_KMS("cursor off\n");
5746 mutex_lock(&dev->struct_mutex);
5750 /* Currently we only support 64x64 cursors */
5751 if (width != 64 || height != 64) {
5752 DRM_ERROR("we currently only support 64x64 cursors\n");
5756 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5757 if (&obj->base == NULL)
5760 if (obj->base.size < width * height * 4) {
5761 DRM_ERROR("buffer is to small\n");
5766 /* we only need to pin inside GTT if cursor is non-phy */
5767 mutex_lock(&dev->struct_mutex);
5768 if (!dev_priv->info->cursor_needs_physical) {
5769 if (obj->tiling_mode) {
5770 DRM_ERROR("cursor cannot be tiled\n");
5775 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5777 DRM_ERROR("failed to move cursor bo into the GTT\n");
5781 ret = i915_gem_object_put_fence(obj);
5783 DRM_ERROR("failed to release fence for cursor");
5787 addr = obj->gtt_offset;
5789 int align = IS_I830(dev) ? 16 * 1024 : 256;
5790 ret = i915_gem_attach_phys_object(dev, obj,
5791 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5794 DRM_ERROR("failed to attach phys object\n");
5797 addr = obj->phys_obj->handle->busaddr;
5801 I915_WRITE(CURSIZE, (height << 12) | width);
5804 if (intel_crtc->cursor_bo) {
5805 if (dev_priv->info->cursor_needs_physical) {
5806 if (intel_crtc->cursor_bo != obj)
5807 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5809 i915_gem_object_unpin(intel_crtc->cursor_bo);
5810 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5813 mutex_unlock(&dev->struct_mutex);
5815 intel_crtc->cursor_addr = addr;
5816 intel_crtc->cursor_bo = obj;
5817 intel_crtc->cursor_width = width;
5818 intel_crtc->cursor_height = height;
5820 intel_crtc_update_cursor(crtc, true);
5824 i915_gem_object_unpin(obj);
5826 mutex_unlock(&dev->struct_mutex);
5828 drm_gem_object_unreference_unlocked(&obj->base);
5832 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5836 intel_crtc->cursor_x = x;
5837 intel_crtc->cursor_y = y;
5839 intel_crtc_update_cursor(crtc, true);
5844 /** Sets the color ramps on behalf of RandR */
5845 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5846 u16 blue, int regno)
5848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5850 intel_crtc->lut_r[regno] = red >> 8;
5851 intel_crtc->lut_g[regno] = green >> 8;
5852 intel_crtc->lut_b[regno] = blue >> 8;
5855 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5856 u16 *blue, int regno)
5858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5860 *red = intel_crtc->lut_r[regno] << 8;
5861 *green = intel_crtc->lut_g[regno] << 8;
5862 *blue = intel_crtc->lut_b[regno] << 8;
5865 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5866 u16 *blue, uint32_t start, uint32_t size)
5868 int end = (start + size > 256) ? 256 : start + size, i;
5869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5871 for (i = start; i < end; i++) {
5872 intel_crtc->lut_r[i] = red[i] >> 8;
5873 intel_crtc->lut_g[i] = green[i] >> 8;
5874 intel_crtc->lut_b[i] = blue[i] >> 8;
5877 intel_crtc_load_lut(crtc);
5881 * Get a pipe with a simple mode set on it for doing load-based monitor
5884 * It will be up to the load-detect code to adjust the pipe as appropriate for
5885 * its requirements. The pipe will be connected to no other encoders.
5887 * Currently this code will only succeed if there is a pipe with no encoders
5888 * configured for it. In the future, it could choose to temporarily disable
5889 * some outputs to free up a pipe for its use.
5891 * \return crtc, or NULL if no pipes are available.
5894 /* VESA 640x480x72Hz mode to set on the pipe */
5895 static struct drm_display_mode load_detect_mode = {
5896 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5897 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5900 static struct drm_framebuffer *
5901 intel_framebuffer_create(struct drm_device *dev,
5902 struct drm_mode_fb_cmd *mode_cmd,
5903 struct drm_i915_gem_object *obj)
5905 struct intel_framebuffer *intel_fb;
5908 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5910 drm_gem_object_unreference_unlocked(&obj->base);
5911 return ERR_PTR(-ENOMEM);
5914 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5916 drm_gem_object_unreference_unlocked(&obj->base);
5918 return ERR_PTR(ret);
5921 return &intel_fb->base;
5925 intel_framebuffer_pitch_for_width(int width, int bpp)
5927 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5928 return ALIGN(pitch, 64);
5932 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5934 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5935 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5938 static struct drm_framebuffer *
5939 intel_framebuffer_create_for_mode(struct drm_device *dev,
5940 struct drm_display_mode *mode,
5943 struct drm_i915_gem_object *obj;
5944 struct drm_mode_fb_cmd mode_cmd;
5946 obj = i915_gem_alloc_object(dev,
5947 intel_framebuffer_size_for_mode(mode, bpp));
5949 return ERR_PTR(-ENOMEM);
5951 mode_cmd.width = mode->hdisplay;
5952 mode_cmd.height = mode->vdisplay;
5953 mode_cmd.depth = depth;
5955 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5957 return intel_framebuffer_create(dev, &mode_cmd, obj);
5960 static struct drm_framebuffer *
5961 mode_fits_in_fbdev(struct drm_device *dev,
5962 struct drm_display_mode *mode)
5964 struct drm_i915_private *dev_priv = dev->dev_private;
5965 struct drm_i915_gem_object *obj;
5966 struct drm_framebuffer *fb;
5968 if (dev_priv->fbdev == NULL)
5971 obj = dev_priv->fbdev->ifb.obj;
5975 fb = &dev_priv->fbdev->ifb.base;
5976 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5977 fb->bits_per_pixel))
5980 if (obj->base.size < mode->vdisplay * fb->pitch)
5986 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5987 struct drm_connector *connector,
5988 struct drm_display_mode *mode,
5989 struct intel_load_detect_pipe *old)
5991 struct intel_crtc *intel_crtc;
5992 struct drm_crtc *possible_crtc;
5993 struct drm_encoder *encoder = &intel_encoder->base;
5994 struct drm_crtc *crtc = NULL;
5995 struct drm_device *dev = encoder->dev;
5996 struct drm_framebuffer *old_fb;
5999 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6000 connector->base.id, drm_get_connector_name(connector),
6001 encoder->base.id, drm_get_encoder_name(encoder));
6004 * Algorithm gets a little messy:
6006 * - if the connector already has an assigned crtc, use it (but make
6007 * sure it's on first)
6009 * - try to find the first unused crtc that can drive this connector,
6010 * and use that if we find one
6013 /* See if we already have a CRTC for this connector */
6014 if (encoder->crtc) {
6015 crtc = encoder->crtc;
6017 intel_crtc = to_intel_crtc(crtc);
6018 old->dpms_mode = intel_crtc->dpms_mode;
6019 old->load_detect_temp = false;
6021 /* Make sure the crtc and connector are running */
6022 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6023 struct drm_encoder_helper_funcs *encoder_funcs;
6024 struct drm_crtc_helper_funcs *crtc_funcs;
6026 crtc_funcs = crtc->helper_private;
6027 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6029 encoder_funcs = encoder->helper_private;
6030 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6036 /* Find an unused one (if possible) */
6037 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6039 if (!(encoder->possible_crtcs & (1 << i)))
6041 if (!possible_crtc->enabled) {
6042 crtc = possible_crtc;
6048 * If we didn't find an unused CRTC, don't use any.
6051 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6055 encoder->crtc = crtc;
6056 connector->encoder = encoder;
6058 intel_crtc = to_intel_crtc(crtc);
6059 old->dpms_mode = intel_crtc->dpms_mode;
6060 old->load_detect_temp = true;
6061 old->release_fb = NULL;
6064 mode = &load_detect_mode;
6068 /* We need a framebuffer large enough to accommodate all accesses
6069 * that the plane may generate whilst we perform load detection.
6070 * We can not rely on the fbcon either being present (we get called
6071 * during its initialisation to detect all boot displays, or it may
6072 * not even exist) or that it is large enough to satisfy the
6075 crtc->fb = mode_fits_in_fbdev(dev, mode);
6076 if (crtc->fb == NULL) {
6077 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6078 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6079 old->release_fb = crtc->fb;
6081 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6082 if (IS_ERR(crtc->fb)) {
6083 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6088 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6089 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6090 if (old->release_fb)
6091 old->release_fb->funcs->destroy(old->release_fb);
6096 /* let the connector get through one full cycle before testing */
6097 intel_wait_for_vblank(dev, intel_crtc->pipe);
6102 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6103 struct drm_connector *connector,
6104 struct intel_load_detect_pipe *old)
6106 struct drm_encoder *encoder = &intel_encoder->base;
6107 struct drm_device *dev = encoder->dev;
6108 struct drm_crtc *crtc = encoder->crtc;
6109 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6110 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6112 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6113 connector->base.id, drm_get_connector_name(connector),
6114 encoder->base.id, drm_get_encoder_name(encoder));
6116 if (old->load_detect_temp) {
6117 connector->encoder = NULL;
6118 drm_helper_disable_unused_functions(dev);
6120 if (old->release_fb)
6121 old->release_fb->funcs->destroy(old->release_fb);
6126 /* Switch crtc and encoder back off if necessary */
6127 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6128 encoder_funcs->dpms(encoder, old->dpms_mode);
6129 crtc_funcs->dpms(crtc, old->dpms_mode);
6133 /* Returns the clock of the currently programmed mode of the given pipe. */
6134 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138 int pipe = intel_crtc->pipe;
6139 u32 dpll = I915_READ(DPLL(pipe));
6141 intel_clock_t clock;
6143 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6144 fp = I915_READ(FP0(pipe));
6146 fp = I915_READ(FP1(pipe));
6148 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6149 if (IS_PINEVIEW(dev)) {
6150 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6151 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6153 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6154 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6157 if (!IS_GEN2(dev)) {
6158 if (IS_PINEVIEW(dev))
6159 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6160 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6162 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6163 DPLL_FPA01_P1_POST_DIV_SHIFT);
6165 switch (dpll & DPLL_MODE_MASK) {
6166 case DPLLB_MODE_DAC_SERIAL:
6167 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6170 case DPLLB_MODE_LVDS:
6171 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6175 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6176 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6180 /* XXX: Handle the 100Mhz refclk */
6181 intel_clock(dev, 96000, &clock);
6183 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6186 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6187 DPLL_FPA01_P1_POST_DIV_SHIFT);
6190 if ((dpll & PLL_REF_INPUT_MASK) ==
6191 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6192 /* XXX: might not be 66MHz */
6193 intel_clock(dev, 66000, &clock);
6195 intel_clock(dev, 48000, &clock);
6197 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6200 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6201 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6203 if (dpll & PLL_P2_DIVIDE_BY_4)
6208 intel_clock(dev, 48000, &clock);
6212 /* XXX: It would be nice to validate the clocks, but we can't reuse
6213 * i830PllIsValid() because it relies on the xf86_config connector
6214 * configuration being accurate, which it isn't necessarily.
6220 /** Returns the currently programmed mode of the given pipe. */
6221 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6222 struct drm_crtc *crtc)
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226 int pipe = intel_crtc->pipe;
6227 struct drm_display_mode *mode;
6228 int htot = I915_READ(HTOTAL(pipe));
6229 int hsync = I915_READ(HSYNC(pipe));
6230 int vtot = I915_READ(VTOTAL(pipe));
6231 int vsync = I915_READ(VSYNC(pipe));
6233 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6237 mode->clock = intel_crtc_clock_get(dev, crtc);
6238 mode->hdisplay = (htot & 0xffff) + 1;
6239 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6240 mode->hsync_start = (hsync & 0xffff) + 1;
6241 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6242 mode->vdisplay = (vtot & 0xffff) + 1;
6243 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6244 mode->vsync_start = (vsync & 0xffff) + 1;
6245 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6247 drm_mode_set_name(mode);
6248 drm_mode_set_crtcinfo(mode, 0);
6253 #define GPU_IDLE_TIMEOUT 500 /* ms */
6255 /* When this timer fires, we've been idle for awhile */
6256 static void intel_gpu_idle_timer(unsigned long arg)
6258 struct drm_device *dev = (struct drm_device *)arg;
6259 drm_i915_private_t *dev_priv = dev->dev_private;
6261 if (!list_empty(&dev_priv->mm.active_list)) {
6262 /* Still processing requests, so just re-arm the timer. */
6263 mod_timer(&dev_priv->idle_timer, jiffies +
6264 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6268 dev_priv->busy = false;
6269 queue_work(dev_priv->wq, &dev_priv->idle_work);
6272 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6274 static void intel_crtc_idle_timer(unsigned long arg)
6276 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6277 struct drm_crtc *crtc = &intel_crtc->base;
6278 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6279 struct intel_framebuffer *intel_fb;
6281 intel_fb = to_intel_framebuffer(crtc->fb);
6282 if (intel_fb && intel_fb->obj->active) {
6283 /* The framebuffer is still being accessed by the GPU. */
6284 mod_timer(&intel_crtc->idle_timer, jiffies +
6285 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6289 intel_crtc->busy = false;
6290 queue_work(dev_priv->wq, &dev_priv->idle_work);
6293 static void intel_increase_pllclock(struct drm_crtc *crtc)
6295 struct drm_device *dev = crtc->dev;
6296 drm_i915_private_t *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298 int pipe = intel_crtc->pipe;
6299 int dpll_reg = DPLL(pipe);
6302 if (HAS_PCH_SPLIT(dev))
6305 if (!dev_priv->lvds_downclock_avail)
6308 dpll = I915_READ(dpll_reg);
6309 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6310 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6312 /* Unlock panel regs */
6313 I915_WRITE(PP_CONTROL,
6314 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6316 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6317 I915_WRITE(dpll_reg, dpll);
6318 intel_wait_for_vblank(dev, pipe);
6320 dpll = I915_READ(dpll_reg);
6321 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6322 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6324 /* ...and lock them again */
6325 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6328 /* Schedule downclock */
6329 mod_timer(&intel_crtc->idle_timer, jiffies +
6330 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6333 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6335 struct drm_device *dev = crtc->dev;
6336 drm_i915_private_t *dev_priv = dev->dev_private;
6337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338 int pipe = intel_crtc->pipe;
6339 int dpll_reg = DPLL(pipe);
6340 int dpll = I915_READ(dpll_reg);
6342 if (HAS_PCH_SPLIT(dev))
6345 if (!dev_priv->lvds_downclock_avail)
6349 * Since this is called by a timer, we should never get here in
6352 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6353 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6355 /* Unlock panel regs */
6356 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6359 dpll |= DISPLAY_RATE_SELECT_FPA1;
6360 I915_WRITE(dpll_reg, dpll);
6361 intel_wait_for_vblank(dev, pipe);
6362 dpll = I915_READ(dpll_reg);
6363 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6364 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6366 /* ...and lock them again */
6367 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6373 * intel_idle_update - adjust clocks for idleness
6374 * @work: work struct
6376 * Either the GPU or display (or both) went idle. Check the busy status
6377 * here and adjust the CRTC and GPU clocks as necessary.
6379 static void intel_idle_update(struct work_struct *work)
6381 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6383 struct drm_device *dev = dev_priv->dev;
6384 struct drm_crtc *crtc;
6385 struct intel_crtc *intel_crtc;
6387 if (!i915_powersave)
6390 mutex_lock(&dev->struct_mutex);
6392 i915_update_gfx_val(dev_priv);
6394 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6395 /* Skip inactive CRTCs */
6399 intel_crtc = to_intel_crtc(crtc);
6400 if (!intel_crtc->busy)
6401 intel_decrease_pllclock(crtc);
6405 mutex_unlock(&dev->struct_mutex);
6409 * intel_mark_busy - mark the GPU and possibly the display busy
6411 * @obj: object we're operating on
6413 * Callers can use this function to indicate that the GPU is busy processing
6414 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6415 * buffer), we'll also mark the display as busy, so we know to increase its
6418 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6420 drm_i915_private_t *dev_priv = dev->dev_private;
6421 struct drm_crtc *crtc = NULL;
6422 struct intel_framebuffer *intel_fb;
6423 struct intel_crtc *intel_crtc;
6425 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6428 if (!dev_priv->busy)
6429 dev_priv->busy = true;
6431 mod_timer(&dev_priv->idle_timer, jiffies +
6432 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6434 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6438 intel_crtc = to_intel_crtc(crtc);
6439 intel_fb = to_intel_framebuffer(crtc->fb);
6440 if (intel_fb->obj == obj) {
6441 if (!intel_crtc->busy) {
6442 /* Non-busy -> busy, upclock */
6443 intel_increase_pllclock(crtc);
6444 intel_crtc->busy = true;
6446 /* Busy -> busy, put off timer */
6447 mod_timer(&intel_crtc->idle_timer, jiffies +
6448 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6454 static void intel_crtc_destroy(struct drm_crtc *crtc)
6456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457 struct drm_device *dev = crtc->dev;
6458 struct intel_unpin_work *work;
6459 unsigned long flags;
6461 spin_lock_irqsave(&dev->event_lock, flags);
6462 work = intel_crtc->unpin_work;
6463 intel_crtc->unpin_work = NULL;
6464 spin_unlock_irqrestore(&dev->event_lock, flags);
6467 cancel_work_sync(&work->work);
6471 drm_crtc_cleanup(crtc);
6476 static void intel_unpin_work_fn(struct work_struct *__work)
6478 struct intel_unpin_work *work =
6479 container_of(__work, struct intel_unpin_work, work);
6481 mutex_lock(&work->dev->struct_mutex);
6482 i915_gem_object_unpin(work->old_fb_obj);
6483 drm_gem_object_unreference(&work->pending_flip_obj->base);
6484 drm_gem_object_unreference(&work->old_fb_obj->base);
6486 intel_update_fbc(work->dev);
6487 mutex_unlock(&work->dev->struct_mutex);
6491 static void do_intel_finish_page_flip(struct drm_device *dev,
6492 struct drm_crtc *crtc)
6494 drm_i915_private_t *dev_priv = dev->dev_private;
6495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6496 struct intel_unpin_work *work;
6497 struct drm_i915_gem_object *obj;
6498 struct drm_pending_vblank_event *e;
6499 struct timeval tnow, tvbl;
6500 unsigned long flags;
6502 /* Ignore early vblank irqs */
6503 if (intel_crtc == NULL)
6506 do_gettimeofday(&tnow);
6508 spin_lock_irqsave(&dev->event_lock, flags);
6509 work = intel_crtc->unpin_work;
6510 if (work == NULL || !work->pending) {
6511 spin_unlock_irqrestore(&dev->event_lock, flags);
6515 intel_crtc->unpin_work = NULL;
6519 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6521 /* Called before vblank count and timestamps have
6522 * been updated for the vblank interval of flip
6523 * completion? Need to increment vblank count and
6524 * add one videorefresh duration to returned timestamp
6525 * to account for this. We assume this happened if we
6526 * get called over 0.9 frame durations after the last
6527 * timestamped vblank.
6529 * This calculation can not be used with vrefresh rates
6530 * below 5Hz (10Hz to be on the safe side) without
6531 * promoting to 64 integers.
6533 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6534 9 * crtc->framedur_ns) {
6535 e->event.sequence++;
6536 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6540 e->event.tv_sec = tvbl.tv_sec;
6541 e->event.tv_usec = tvbl.tv_usec;
6543 list_add_tail(&e->base.link,
6544 &e->base.file_priv->event_list);
6545 wake_up_interruptible(&e->base.file_priv->event_wait);
6548 drm_vblank_put(dev, intel_crtc->pipe);
6550 spin_unlock_irqrestore(&dev->event_lock, flags);
6552 obj = work->old_fb_obj;
6554 atomic_clear_mask(1 << intel_crtc->plane,
6555 &obj->pending_flip.counter);
6556 if (atomic_read(&obj->pending_flip) == 0)
6557 wake_up(&dev_priv->pending_flip_queue);
6559 schedule_work(&work->work);
6561 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6564 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6566 drm_i915_private_t *dev_priv = dev->dev_private;
6567 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6569 do_intel_finish_page_flip(dev, crtc);
6572 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6574 drm_i915_private_t *dev_priv = dev->dev_private;
6575 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6577 do_intel_finish_page_flip(dev, crtc);
6580 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6582 drm_i915_private_t *dev_priv = dev->dev_private;
6583 struct intel_crtc *intel_crtc =
6584 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6585 unsigned long flags;
6587 spin_lock_irqsave(&dev->event_lock, flags);
6588 if (intel_crtc->unpin_work) {
6589 if ((++intel_crtc->unpin_work->pending) > 1)
6590 DRM_ERROR("Prepared flip multiple times\n");
6592 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6594 spin_unlock_irqrestore(&dev->event_lock, flags);
6597 static int intel_gen2_queue_flip(struct drm_device *dev,
6598 struct drm_crtc *crtc,
6599 struct drm_framebuffer *fb,
6600 struct drm_i915_gem_object *obj)
6602 struct drm_i915_private *dev_priv = dev->dev_private;
6603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6604 unsigned long offset;
6608 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6612 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6613 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6615 ret = BEGIN_LP_RING(6);
6619 /* Can't queue multiple flips, so wait for the previous
6620 * one to finish before executing the next.
6622 if (intel_crtc->plane)
6623 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6625 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6626 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6628 OUT_RING(MI_DISPLAY_FLIP |
6629 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6630 OUT_RING(fb->pitch);
6631 OUT_RING(obj->gtt_offset + offset);
6638 static int intel_gen3_queue_flip(struct drm_device *dev,
6639 struct drm_crtc *crtc,
6640 struct drm_framebuffer *fb,
6641 struct drm_i915_gem_object *obj)
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645 unsigned long offset;
6649 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6653 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6654 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6656 ret = BEGIN_LP_RING(6);
6660 if (intel_crtc->plane)
6661 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6663 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6664 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6666 OUT_RING(MI_DISPLAY_FLIP_I915 |
6667 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6668 OUT_RING(fb->pitch);
6669 OUT_RING(obj->gtt_offset + offset);
6677 static int intel_gen4_queue_flip(struct drm_device *dev,
6678 struct drm_crtc *crtc,
6679 struct drm_framebuffer *fb,
6680 struct drm_i915_gem_object *obj)
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684 uint32_t pf, pipesrc;
6687 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6691 ret = BEGIN_LP_RING(4);
6695 /* i965+ uses the linear or tiled offsets from the
6696 * Display Registers (which do not change across a page-flip)
6697 * so we need only reprogram the base address.
6699 OUT_RING(MI_DISPLAY_FLIP |
6700 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6701 OUT_RING(fb->pitch);
6702 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6704 /* XXX Enabling the panel-fitter across page-flip is so far
6705 * untested on non-native modes, so ignore it for now.
6706 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6709 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6710 OUT_RING(pf | pipesrc);
6716 static int intel_gen6_queue_flip(struct drm_device *dev,
6717 struct drm_crtc *crtc,
6718 struct drm_framebuffer *fb,
6719 struct drm_i915_gem_object *obj)
6721 struct drm_i915_private *dev_priv = dev->dev_private;
6722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6723 uint32_t pf, pipesrc;
6726 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6730 ret = BEGIN_LP_RING(4);
6734 OUT_RING(MI_DISPLAY_FLIP |
6735 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6736 OUT_RING(fb->pitch | obj->tiling_mode);
6737 OUT_RING(obj->gtt_offset);
6739 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6740 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6741 OUT_RING(pf | pipesrc);
6748 * On gen7 we currently use the blit ring because (in early silicon at least)
6749 * the render ring doesn't give us interrpts for page flip completion, which
6750 * means clients will hang after the first flip is queued. Fortunately the
6751 * blit ring generates interrupts properly, so use it instead.
6753 static int intel_gen7_queue_flip(struct drm_device *dev,
6754 struct drm_crtc *crtc,
6755 struct drm_framebuffer *fb,
6756 struct drm_i915_gem_object *obj)
6758 struct drm_i915_private *dev_priv = dev->dev_private;
6759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6760 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6763 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6767 ret = intel_ring_begin(ring, 4);
6771 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6772 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6773 intel_ring_emit(ring, (obj->gtt_offset));
6774 intel_ring_emit(ring, (MI_NOOP));
6775 intel_ring_advance(ring);
6780 static int intel_default_queue_flip(struct drm_device *dev,
6781 struct drm_crtc *crtc,
6782 struct drm_framebuffer *fb,
6783 struct drm_i915_gem_object *obj)
6788 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6789 struct drm_framebuffer *fb,
6790 struct drm_pending_vblank_event *event)
6792 struct drm_device *dev = crtc->dev;
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794 struct intel_framebuffer *intel_fb;
6795 struct drm_i915_gem_object *obj;
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 struct intel_unpin_work *work;
6798 unsigned long flags;
6801 work = kzalloc(sizeof *work, GFP_KERNEL);
6805 work->event = event;
6806 work->dev = crtc->dev;
6807 intel_fb = to_intel_framebuffer(crtc->fb);
6808 work->old_fb_obj = intel_fb->obj;
6809 INIT_WORK(&work->work, intel_unpin_work_fn);
6811 /* We borrow the event spin lock for protecting unpin_work */
6812 spin_lock_irqsave(&dev->event_lock, flags);
6813 if (intel_crtc->unpin_work) {
6814 spin_unlock_irqrestore(&dev->event_lock, flags);
6817 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6820 intel_crtc->unpin_work = work;
6821 spin_unlock_irqrestore(&dev->event_lock, flags);
6823 intel_fb = to_intel_framebuffer(fb);
6824 obj = intel_fb->obj;
6826 mutex_lock(&dev->struct_mutex);
6828 /* Reference the objects for the scheduled work. */
6829 drm_gem_object_reference(&work->old_fb_obj->base);
6830 drm_gem_object_reference(&obj->base);
6834 ret = drm_vblank_get(dev, intel_crtc->pipe);
6838 work->pending_flip_obj = obj;
6840 work->enable_stall_check = true;
6842 /* Block clients from rendering to the new back buffer until
6843 * the flip occurs and the object is no longer visible.
6845 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6847 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6849 goto cleanup_pending;
6851 intel_disable_fbc(dev);
6852 mutex_unlock(&dev->struct_mutex);
6854 trace_i915_flip_request(intel_crtc->plane, obj);
6859 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6861 drm_gem_object_unreference(&work->old_fb_obj->base);
6862 drm_gem_object_unreference(&obj->base);
6863 mutex_unlock(&dev->struct_mutex);
6865 spin_lock_irqsave(&dev->event_lock, flags);
6866 intel_crtc->unpin_work = NULL;
6867 spin_unlock_irqrestore(&dev->event_lock, flags);
6874 static void intel_sanitize_modesetting(struct drm_device *dev,
6875 int pipe, int plane)
6877 struct drm_i915_private *dev_priv = dev->dev_private;
6880 if (HAS_PCH_SPLIT(dev))
6883 /* Who knows what state these registers were left in by the BIOS or
6886 * If we leave the registers in a conflicting state (e.g. with the
6887 * display plane reading from the other pipe than the one we intend
6888 * to use) then when we attempt to teardown the active mode, we will
6889 * not disable the pipes and planes in the correct order -- leaving
6890 * a plane reading from a disabled pipe and possibly leading to
6891 * undefined behaviour.
6894 reg = DSPCNTR(plane);
6895 val = I915_READ(reg);
6897 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6899 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6902 /* This display plane is active and attached to the other CPU pipe. */
6905 /* Disable the plane and wait for it to stop reading from the pipe. */
6906 intel_disable_plane(dev_priv, plane, pipe);
6907 intel_disable_pipe(dev_priv, pipe);
6910 static void intel_crtc_reset(struct drm_crtc *crtc)
6912 struct drm_device *dev = crtc->dev;
6913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6915 /* Reset flags back to the 'unknown' status so that they
6916 * will be correctly set on the initial modeset.
6918 intel_crtc->dpms_mode = -1;
6920 /* We need to fix up any BIOS configuration that conflicts with
6923 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6926 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6927 .dpms = intel_crtc_dpms,
6928 .mode_fixup = intel_crtc_mode_fixup,
6929 .mode_set = intel_crtc_mode_set,
6930 .mode_set_base = intel_pipe_set_base,
6931 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6932 .load_lut = intel_crtc_load_lut,
6933 .disable = intel_crtc_disable,
6936 static const struct drm_crtc_funcs intel_crtc_funcs = {
6937 .reset = intel_crtc_reset,
6938 .cursor_set = intel_crtc_cursor_set,
6939 .cursor_move = intel_crtc_cursor_move,
6940 .gamma_set = intel_crtc_gamma_set,
6941 .set_config = drm_crtc_helper_set_config,
6942 .destroy = intel_crtc_destroy,
6943 .page_flip = intel_crtc_page_flip,
6946 static void intel_crtc_init(struct drm_device *dev, int pipe)
6948 drm_i915_private_t *dev_priv = dev->dev_private;
6949 struct intel_crtc *intel_crtc;
6952 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6953 if (intel_crtc == NULL)
6956 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6958 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6959 for (i = 0; i < 256; i++) {
6960 intel_crtc->lut_r[i] = i;
6961 intel_crtc->lut_g[i] = i;
6962 intel_crtc->lut_b[i] = i;
6965 /* Swap pipes & planes for FBC on pre-965 */
6966 intel_crtc->pipe = pipe;
6967 intel_crtc->plane = pipe;
6968 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6969 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6970 intel_crtc->plane = !pipe;
6973 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6974 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6975 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6976 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6978 intel_crtc_reset(&intel_crtc->base);
6979 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6980 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6982 if (HAS_PCH_SPLIT(dev)) {
6983 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6984 intel_helper_funcs.commit = ironlake_crtc_commit;
6986 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6987 intel_helper_funcs.commit = i9xx_crtc_commit;
6990 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6992 intel_crtc->busy = false;
6994 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6995 (unsigned long)intel_crtc);
6998 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6999 struct drm_file *file)
7001 drm_i915_private_t *dev_priv = dev->dev_private;
7002 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7003 struct drm_mode_object *drmmode_obj;
7004 struct intel_crtc *crtc;
7007 DRM_ERROR("called with no initialization\n");
7011 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7012 DRM_MODE_OBJECT_CRTC);
7015 DRM_ERROR("no such CRTC id\n");
7019 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7020 pipe_from_crtc_id->pipe = crtc->pipe;
7025 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7027 struct intel_encoder *encoder;
7031 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7032 if (type_mask & encoder->clone_mask)
7033 index_mask |= (1 << entry);
7040 static bool has_edp_a(struct drm_device *dev)
7042 struct drm_i915_private *dev_priv = dev->dev_private;
7044 if (!IS_MOBILE(dev))
7047 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7051 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7057 static void intel_setup_outputs(struct drm_device *dev)
7059 struct drm_i915_private *dev_priv = dev->dev_private;
7060 struct intel_encoder *encoder;
7061 bool dpd_is_edp = false;
7062 bool has_lvds = false;
7064 if (IS_MOBILE(dev) && !IS_I830(dev))
7065 has_lvds = intel_lvds_init(dev);
7066 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7067 /* disable the panel fitter on everything but LVDS */
7068 I915_WRITE(PFIT_CONTROL, 0);
7071 if (HAS_PCH_SPLIT(dev)) {
7072 dpd_is_edp = intel_dpd_is_edp(dev);
7075 intel_dp_init(dev, DP_A);
7077 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7078 intel_dp_init(dev, PCH_DP_D);
7081 intel_crt_init(dev);
7083 if (HAS_PCH_SPLIT(dev)) {
7086 if (I915_READ(HDMIB) & PORT_DETECTED) {
7087 /* PCH SDVOB multiplex with HDMIB */
7088 found = intel_sdvo_init(dev, PCH_SDVOB);
7090 intel_hdmi_init(dev, HDMIB);
7091 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7092 intel_dp_init(dev, PCH_DP_B);
7095 if (I915_READ(HDMIC) & PORT_DETECTED)
7096 intel_hdmi_init(dev, HDMIC);
7098 if (I915_READ(HDMID) & PORT_DETECTED)
7099 intel_hdmi_init(dev, HDMID);
7101 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7102 intel_dp_init(dev, PCH_DP_C);
7104 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7105 intel_dp_init(dev, PCH_DP_D);
7107 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7110 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7111 DRM_DEBUG_KMS("probing SDVOB\n");
7112 found = intel_sdvo_init(dev, SDVOB);
7113 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7114 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7115 intel_hdmi_init(dev, SDVOB);
7118 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7119 DRM_DEBUG_KMS("probing DP_B\n");
7120 intel_dp_init(dev, DP_B);
7124 /* Before G4X SDVOC doesn't have its own detect register */
7126 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7127 DRM_DEBUG_KMS("probing SDVOC\n");
7128 found = intel_sdvo_init(dev, SDVOC);
7131 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7133 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7134 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7135 intel_hdmi_init(dev, SDVOC);
7137 if (SUPPORTS_INTEGRATED_DP(dev)) {
7138 DRM_DEBUG_KMS("probing DP_C\n");
7139 intel_dp_init(dev, DP_C);
7143 if (SUPPORTS_INTEGRATED_DP(dev) &&
7144 (I915_READ(DP_D) & DP_DETECTED)) {
7145 DRM_DEBUG_KMS("probing DP_D\n");
7146 intel_dp_init(dev, DP_D);
7148 } else if (IS_GEN2(dev))
7149 intel_dvo_init(dev);
7151 if (SUPPORTS_TV(dev))
7154 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7155 encoder->base.possible_crtcs = encoder->crtc_mask;
7156 encoder->base.possible_clones =
7157 intel_encoder_clones(dev, encoder->clone_mask);
7160 intel_panel_setup_backlight(dev);
7162 /* disable all the possible outputs/crtcs before entering KMS mode */
7163 drm_helper_disable_unused_functions(dev);
7166 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7168 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7170 drm_framebuffer_cleanup(fb);
7171 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7176 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7177 struct drm_file *file,
7178 unsigned int *handle)
7180 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7181 struct drm_i915_gem_object *obj = intel_fb->obj;
7183 return drm_gem_handle_create(file, &obj->base, handle);
7186 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7187 .destroy = intel_user_framebuffer_destroy,
7188 .create_handle = intel_user_framebuffer_create_handle,
7191 int intel_framebuffer_init(struct drm_device *dev,
7192 struct intel_framebuffer *intel_fb,
7193 struct drm_mode_fb_cmd *mode_cmd,
7194 struct drm_i915_gem_object *obj)
7198 if (obj->tiling_mode == I915_TILING_Y)
7201 if (mode_cmd->pitch & 63)
7204 switch (mode_cmd->bpp) {
7207 /* Only pre-ILK can handle 5:5:5 */
7208 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7219 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7221 DRM_ERROR("framebuffer init failed %d\n", ret);
7225 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7226 intel_fb->obj = obj;
7230 static struct drm_framebuffer *
7231 intel_user_framebuffer_create(struct drm_device *dev,
7232 struct drm_file *filp,
7233 struct drm_mode_fb_cmd *mode_cmd)
7235 struct drm_i915_gem_object *obj;
7237 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7238 if (&obj->base == NULL)
7239 return ERR_PTR(-ENOENT);
7241 return intel_framebuffer_create(dev, mode_cmd, obj);
7244 static const struct drm_mode_config_funcs intel_mode_funcs = {
7245 .fb_create = intel_user_framebuffer_create,
7246 .output_poll_changed = intel_fb_output_poll_changed,
7249 static struct drm_i915_gem_object *
7250 intel_alloc_context_page(struct drm_device *dev)
7252 struct drm_i915_gem_object *ctx;
7255 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7257 ctx = i915_gem_alloc_object(dev, 4096);
7259 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7263 ret = i915_gem_object_pin(ctx, 4096, true);
7265 DRM_ERROR("failed to pin power context: %d\n", ret);
7269 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7271 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7278 i915_gem_object_unpin(ctx);
7280 drm_gem_object_unreference(&ctx->base);
7281 mutex_unlock(&dev->struct_mutex);
7285 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7290 rgvswctl = I915_READ16(MEMSWCTL);
7291 if (rgvswctl & MEMCTL_CMD_STS) {
7292 DRM_DEBUG("gpu busy, RCS change rejected\n");
7293 return false; /* still busy with another command */
7296 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7297 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7298 I915_WRITE16(MEMSWCTL, rgvswctl);
7299 POSTING_READ16(MEMSWCTL);
7301 rgvswctl |= MEMCTL_CMD_STS;
7302 I915_WRITE16(MEMSWCTL, rgvswctl);
7307 void ironlake_enable_drps(struct drm_device *dev)
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 u32 rgvmodectl = I915_READ(MEMMODECTL);
7311 u8 fmax, fmin, fstart, vstart;
7313 /* Enable temp reporting */
7314 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7315 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7317 /* 100ms RC evaluation intervals */
7318 I915_WRITE(RCUPEI, 100000);
7319 I915_WRITE(RCDNEI, 100000);
7321 /* Set max/min thresholds to 90ms and 80ms respectively */
7322 I915_WRITE(RCBMAXAVG, 90000);
7323 I915_WRITE(RCBMINAVG, 80000);
7325 I915_WRITE(MEMIHYST, 1);
7327 /* Set up min, max, and cur for interrupt handling */
7328 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7329 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7330 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7331 MEMMODE_FSTART_SHIFT;
7333 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7336 dev_priv->fmax = fmax; /* IPS callback will increase this */
7337 dev_priv->fstart = fstart;
7339 dev_priv->max_delay = fstart;
7340 dev_priv->min_delay = fmin;
7341 dev_priv->cur_delay = fstart;
7343 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7344 fmax, fmin, fstart);
7346 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7349 * Interrupts will be enabled in ironlake_irq_postinstall
7352 I915_WRITE(VIDSTART, vstart);
7353 POSTING_READ(VIDSTART);
7355 rgvmodectl |= MEMMODE_SWMODE_EN;
7356 I915_WRITE(MEMMODECTL, rgvmodectl);
7358 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7359 DRM_ERROR("stuck trying to change perf mode\n");
7362 ironlake_set_drps(dev, fstart);
7364 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7366 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7367 dev_priv->last_count2 = I915_READ(0x112f4);
7368 getrawmonotonic(&dev_priv->last_time2);
7371 void ironlake_disable_drps(struct drm_device *dev)
7373 struct drm_i915_private *dev_priv = dev->dev_private;
7374 u16 rgvswctl = I915_READ16(MEMSWCTL);
7376 /* Ack interrupts, disable EFC interrupt */
7377 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7378 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7379 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7380 I915_WRITE(DEIIR, DE_PCU_EVENT);
7381 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7383 /* Go back to the starting frequency */
7384 ironlake_set_drps(dev, dev_priv->fstart);
7386 rgvswctl |= MEMCTL_CMD_STS;
7387 I915_WRITE(MEMSWCTL, rgvswctl);
7392 void gen6_set_rps(struct drm_device *dev, u8 val)
7394 struct drm_i915_private *dev_priv = dev->dev_private;
7397 swreq = (val & 0x3ff) << 25;
7398 I915_WRITE(GEN6_RPNSWREQ, swreq);
7401 void gen6_disable_rps(struct drm_device *dev)
7403 struct drm_i915_private *dev_priv = dev->dev_private;
7405 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7406 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7407 I915_WRITE(GEN6_PMIER, 0);
7409 spin_lock_irq(&dev_priv->rps_lock);
7410 dev_priv->pm_iir = 0;
7411 spin_unlock_irq(&dev_priv->rps_lock);
7413 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7416 static unsigned long intel_pxfreq(u32 vidfreq)
7419 int div = (vidfreq & 0x3f0000) >> 16;
7420 int post = (vidfreq & 0x3000) >> 12;
7421 int pre = (vidfreq & 0x7);
7426 freq = ((div * 133333) / ((1<<post) * pre));
7431 void intel_init_emon(struct drm_device *dev)
7433 struct drm_i915_private *dev_priv = dev->dev_private;
7438 /* Disable to program */
7442 /* Program energy weights for various events */
7443 I915_WRITE(SDEW, 0x15040d00);
7444 I915_WRITE(CSIEW0, 0x007f0000);
7445 I915_WRITE(CSIEW1, 0x1e220004);
7446 I915_WRITE(CSIEW2, 0x04000004);
7448 for (i = 0; i < 5; i++)
7449 I915_WRITE(PEW + (i * 4), 0);
7450 for (i = 0; i < 3; i++)
7451 I915_WRITE(DEW + (i * 4), 0);
7453 /* Program P-state weights to account for frequency power adjustment */
7454 for (i = 0; i < 16; i++) {
7455 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7456 unsigned long freq = intel_pxfreq(pxvidfreq);
7457 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7462 val *= (freq / 1000);
7464 val /= (127*127*900);
7466 DRM_ERROR("bad pxval: %ld\n", val);
7469 /* Render standby states get 0 weight */
7473 for (i = 0; i < 4; i++) {
7474 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7475 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7476 I915_WRITE(PXW + (i * 4), val);
7479 /* Adjust magic regs to magic values (more experimental results) */
7480 I915_WRITE(OGW0, 0);
7481 I915_WRITE(OGW1, 0);
7482 I915_WRITE(EG0, 0x00007f00);
7483 I915_WRITE(EG1, 0x0000000e);
7484 I915_WRITE(EG2, 0x000e0000);
7485 I915_WRITE(EG3, 0x68000300);
7486 I915_WRITE(EG4, 0x42000000);
7487 I915_WRITE(EG5, 0x00140031);
7491 for (i = 0; i < 8; i++)
7492 I915_WRITE(PXWL + (i * 4), 0);
7494 /* Enable PMON + select events */
7495 I915_WRITE(ECR, 0x80000019);
7497 lcfuse = I915_READ(LCFUSE02);
7499 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7502 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7504 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7505 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7506 u32 pcu_mbox, rc6_mask = 0;
7507 int cur_freq, min_freq, max_freq;
7510 /* Here begins a magic sequence of register writes to enable
7511 * auto-downclocking.
7513 * Perhaps there might be some value in exposing these to
7516 I915_WRITE(GEN6_RC_STATE, 0);
7517 mutex_lock(&dev_priv->dev->struct_mutex);
7518 gen6_gt_force_wake_get(dev_priv);
7520 /* disable the counters and set deterministic thresholds */
7521 I915_WRITE(GEN6_RC_CONTROL, 0);
7523 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7524 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7525 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7526 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7527 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7529 for (i = 0; i < I915_NUM_RINGS; i++)
7530 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7532 I915_WRITE(GEN6_RC_SLEEP, 0);
7533 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7534 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7535 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7536 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7538 if (i915_enable_rc6)
7539 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7540 GEN6_RC_CTL_RC6_ENABLE;
7542 I915_WRITE(GEN6_RC_CONTROL,
7544 GEN6_RC_CTL_EI_MODE(1) |
7545 GEN6_RC_CTL_HW_ENABLE);
7547 I915_WRITE(GEN6_RPNSWREQ,
7548 GEN6_FREQUENCY(10) |
7550 GEN6_AGGRESSIVE_TURBO);
7551 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7552 GEN6_FREQUENCY(12));
7554 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7555 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7558 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7559 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7560 I915_WRITE(GEN6_RP_UP_EI, 100000);
7561 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7562 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7563 I915_WRITE(GEN6_RP_CONTROL,
7564 GEN6_RP_MEDIA_TURBO |
7565 GEN6_RP_USE_NORMAL_FREQ |
7566 GEN6_RP_MEDIA_IS_GFX |
7568 GEN6_RP_UP_BUSY_AVG |
7569 GEN6_RP_DOWN_IDLE_CONT);
7571 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7573 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7575 I915_WRITE(GEN6_PCODE_DATA, 0);
7576 I915_WRITE(GEN6_PCODE_MAILBOX,
7578 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7579 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7581 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7583 min_freq = (rp_state_cap & 0xff0000) >> 16;
7584 max_freq = rp_state_cap & 0xff;
7585 cur_freq = (gt_perf_status & 0xff00) >> 8;
7587 /* Check for overclock support */
7588 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7590 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7591 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7592 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7593 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7595 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7596 if (pcu_mbox & (1<<31)) { /* OC supported */
7597 max_freq = pcu_mbox & 0xff;
7598 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7601 /* In units of 100MHz */
7602 dev_priv->max_delay = max_freq;
7603 dev_priv->min_delay = min_freq;
7604 dev_priv->cur_delay = cur_freq;
7606 /* requires MSI enabled */
7607 I915_WRITE(GEN6_PMIER,
7608 GEN6_PM_MBOX_EVENT |
7609 GEN6_PM_THERMAL_EVENT |
7610 GEN6_PM_RP_DOWN_TIMEOUT |
7611 GEN6_PM_RP_UP_THRESHOLD |
7612 GEN6_PM_RP_DOWN_THRESHOLD |
7613 GEN6_PM_RP_UP_EI_EXPIRED |
7614 GEN6_PM_RP_DOWN_EI_EXPIRED);
7615 spin_lock_irq(&dev_priv->rps_lock);
7616 WARN_ON(dev_priv->pm_iir != 0);
7617 I915_WRITE(GEN6_PMIMR, 0);
7618 spin_unlock_irq(&dev_priv->rps_lock);
7619 /* enable all PM interrupts */
7620 I915_WRITE(GEN6_PMINTRMSK, 0);
7622 gen6_gt_force_wake_put(dev_priv);
7623 mutex_unlock(&dev_priv->dev->struct_mutex);
7626 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7629 int gpu_freq, ia_freq, max_ia_freq;
7630 int scaling_factor = 180;
7632 max_ia_freq = cpufreq_quick_get_max(0);
7634 * Default to measured freq if none found, PCU will ensure we don't go
7638 max_ia_freq = tsc_khz;
7640 /* Convert from kHz to MHz */
7641 max_ia_freq /= 1000;
7643 mutex_lock(&dev_priv->dev->struct_mutex);
7646 * For each potential GPU frequency, load a ring frequency we'd like
7647 * to use for memory access. We do this by specifying the IA frequency
7648 * the PCU should use as a reference to determine the ring frequency.
7650 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7652 int diff = dev_priv->max_delay - gpu_freq;
7655 * For GPU frequencies less than 750MHz, just use the lowest
7658 if (gpu_freq < min_freq)
7661 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7662 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7664 I915_WRITE(GEN6_PCODE_DATA,
7665 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7667 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7668 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7669 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7670 GEN6_PCODE_READY) == 0, 10)) {
7671 DRM_ERROR("pcode write of freq table timed out\n");
7676 mutex_unlock(&dev_priv->dev->struct_mutex);
7679 static void ironlake_init_clock_gating(struct drm_device *dev)
7681 struct drm_i915_private *dev_priv = dev->dev_private;
7682 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7684 /* Required for FBC */
7685 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7686 DPFCRUNIT_CLOCK_GATE_DISABLE |
7687 DPFDUNIT_CLOCK_GATE_DISABLE;
7688 /* Required for CxSR */
7689 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7691 I915_WRITE(PCH_3DCGDIS0,
7692 MARIUNIT_CLOCK_GATE_DISABLE |
7693 SVSMUNIT_CLOCK_GATE_DISABLE);
7694 I915_WRITE(PCH_3DCGDIS1,
7695 VFMUNIT_CLOCK_GATE_DISABLE);
7697 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7700 * According to the spec the following bits should be set in
7701 * order to enable memory self-refresh
7702 * The bit 22/21 of 0x42004
7703 * The bit 5 of 0x42020
7704 * The bit 15 of 0x45000
7706 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7707 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7708 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7709 I915_WRITE(ILK_DSPCLK_GATE,
7710 (I915_READ(ILK_DSPCLK_GATE) |
7711 ILK_DPARB_CLK_GATE));
7712 I915_WRITE(DISP_ARB_CTL,
7713 (I915_READ(DISP_ARB_CTL) |
7715 I915_WRITE(WM3_LP_ILK, 0);
7716 I915_WRITE(WM2_LP_ILK, 0);
7717 I915_WRITE(WM1_LP_ILK, 0);
7720 * Based on the document from hardware guys the following bits
7721 * should be set unconditionally in order to enable FBC.
7722 * The bit 22 of 0x42000
7723 * The bit 22 of 0x42004
7724 * The bit 7,8,9 of 0x42020.
7726 if (IS_IRONLAKE_M(dev)) {
7727 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7728 I915_READ(ILK_DISPLAY_CHICKEN1) |
7730 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7731 I915_READ(ILK_DISPLAY_CHICKEN2) |
7733 I915_WRITE(ILK_DSPCLK_GATE,
7734 I915_READ(ILK_DSPCLK_GATE) |
7740 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7741 I915_READ(ILK_DISPLAY_CHICKEN2) |
7742 ILK_ELPIN_409_SELECT);
7743 I915_WRITE(_3D_CHICKEN2,
7744 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7745 _3D_CHICKEN2_WM_READ_PIPELINED);
7748 static void gen6_init_clock_gating(struct drm_device *dev)
7750 struct drm_i915_private *dev_priv = dev->dev_private;
7752 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7754 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7756 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7757 I915_READ(ILK_DISPLAY_CHICKEN2) |
7758 ILK_ELPIN_409_SELECT);
7760 I915_WRITE(WM3_LP_ILK, 0);
7761 I915_WRITE(WM2_LP_ILK, 0);
7762 I915_WRITE(WM1_LP_ILK, 0);
7765 * According to the spec the following bits should be
7766 * set in order to enable memory self-refresh and fbc:
7767 * The bit21 and bit22 of 0x42000
7768 * The bit21 and bit22 of 0x42004
7769 * The bit5 and bit7 of 0x42020
7770 * The bit14 of 0x70180
7771 * The bit14 of 0x71180
7773 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7774 I915_READ(ILK_DISPLAY_CHICKEN1) |
7775 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7776 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7777 I915_READ(ILK_DISPLAY_CHICKEN2) |
7778 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7779 I915_WRITE(ILK_DSPCLK_GATE,
7780 I915_READ(ILK_DSPCLK_GATE) |
7781 ILK_DPARB_CLK_GATE |
7784 for_each_pipe(pipe) {
7785 I915_WRITE(DSPCNTR(pipe),
7786 I915_READ(DSPCNTR(pipe)) |
7787 DISPPLANE_TRICKLE_FEED_DISABLE);
7788 intel_flush_display_plane(dev_priv, pipe);
7792 static void ivybridge_init_clock_gating(struct drm_device *dev)
7794 struct drm_i915_private *dev_priv = dev->dev_private;
7796 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7798 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7800 I915_WRITE(WM3_LP_ILK, 0);
7801 I915_WRITE(WM2_LP_ILK, 0);
7802 I915_WRITE(WM1_LP_ILK, 0);
7804 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7806 for_each_pipe(pipe) {
7807 I915_WRITE(DSPCNTR(pipe),
7808 I915_READ(DSPCNTR(pipe)) |
7809 DISPPLANE_TRICKLE_FEED_DISABLE);
7810 intel_flush_display_plane(dev_priv, pipe);
7814 static void g4x_init_clock_gating(struct drm_device *dev)
7816 struct drm_i915_private *dev_priv = dev->dev_private;
7817 uint32_t dspclk_gate;
7819 I915_WRITE(RENCLK_GATE_D1, 0);
7820 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7821 GS_UNIT_CLOCK_GATE_DISABLE |
7822 CL_UNIT_CLOCK_GATE_DISABLE);
7823 I915_WRITE(RAMCLK_GATE_D, 0);
7824 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7825 OVRUNIT_CLOCK_GATE_DISABLE |
7826 OVCUNIT_CLOCK_GATE_DISABLE;
7828 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7829 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7832 static void crestline_init_clock_gating(struct drm_device *dev)
7834 struct drm_i915_private *dev_priv = dev->dev_private;
7836 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7837 I915_WRITE(RENCLK_GATE_D2, 0);
7838 I915_WRITE(DSPCLK_GATE_D, 0);
7839 I915_WRITE(RAMCLK_GATE_D, 0);
7840 I915_WRITE16(DEUC, 0);
7843 static void broadwater_init_clock_gating(struct drm_device *dev)
7845 struct drm_i915_private *dev_priv = dev->dev_private;
7847 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7848 I965_RCC_CLOCK_GATE_DISABLE |
7849 I965_RCPB_CLOCK_GATE_DISABLE |
7850 I965_ISC_CLOCK_GATE_DISABLE |
7851 I965_FBC_CLOCK_GATE_DISABLE);
7852 I915_WRITE(RENCLK_GATE_D2, 0);
7855 static void gen3_init_clock_gating(struct drm_device *dev)
7857 struct drm_i915_private *dev_priv = dev->dev_private;
7858 u32 dstate = I915_READ(D_STATE);
7860 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7861 DSTATE_DOT_CLOCK_GATING;
7862 I915_WRITE(D_STATE, dstate);
7865 static void i85x_init_clock_gating(struct drm_device *dev)
7867 struct drm_i915_private *dev_priv = dev->dev_private;
7869 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7872 static void i830_init_clock_gating(struct drm_device *dev)
7874 struct drm_i915_private *dev_priv = dev->dev_private;
7876 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7879 static void ibx_init_clock_gating(struct drm_device *dev)
7881 struct drm_i915_private *dev_priv = dev->dev_private;
7884 * On Ibex Peak and Cougar Point, we need to disable clock
7885 * gating for the panel power sequencer or it will fail to
7886 * start up when no ports are active.
7888 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7891 static void cpt_init_clock_gating(struct drm_device *dev)
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7897 * On Ibex Peak and Cougar Point, we need to disable clock
7898 * gating for the panel power sequencer or it will fail to
7899 * start up when no ports are active.
7901 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7902 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7903 DPLS_EDP_PPS_FIX_DIS);
7904 /* Without this, mode sets may fail silently on FDI */
7906 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7909 static void ironlake_teardown_rc6(struct drm_device *dev)
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7913 if (dev_priv->renderctx) {
7914 i915_gem_object_unpin(dev_priv->renderctx);
7915 drm_gem_object_unreference(&dev_priv->renderctx->base);
7916 dev_priv->renderctx = NULL;
7919 if (dev_priv->pwrctx) {
7920 i915_gem_object_unpin(dev_priv->pwrctx);
7921 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7922 dev_priv->pwrctx = NULL;
7926 static void ironlake_disable_rc6(struct drm_device *dev)
7928 struct drm_i915_private *dev_priv = dev->dev_private;
7930 if (I915_READ(PWRCTXA)) {
7931 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7932 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7933 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7936 I915_WRITE(PWRCTXA, 0);
7937 POSTING_READ(PWRCTXA);
7939 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7940 POSTING_READ(RSTDBYCTL);
7943 ironlake_teardown_rc6(dev);
7946 static int ironlake_setup_rc6(struct drm_device *dev)
7948 struct drm_i915_private *dev_priv = dev->dev_private;
7950 if (dev_priv->renderctx == NULL)
7951 dev_priv->renderctx = intel_alloc_context_page(dev);
7952 if (!dev_priv->renderctx)
7955 if (dev_priv->pwrctx == NULL)
7956 dev_priv->pwrctx = intel_alloc_context_page(dev);
7957 if (!dev_priv->pwrctx) {
7958 ironlake_teardown_rc6(dev);
7965 void ironlake_enable_rc6(struct drm_device *dev)
7967 struct drm_i915_private *dev_priv = dev->dev_private;
7970 /* rc6 disabled by default due to repeated reports of hanging during
7973 if (!i915_enable_rc6)
7976 mutex_lock(&dev->struct_mutex);
7977 ret = ironlake_setup_rc6(dev);
7979 mutex_unlock(&dev->struct_mutex);
7984 * GPU can automatically power down the render unit if given a page
7987 ret = BEGIN_LP_RING(6);
7989 ironlake_teardown_rc6(dev);
7990 mutex_unlock(&dev->struct_mutex);
7994 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7995 OUT_RING(MI_SET_CONTEXT);
7996 OUT_RING(dev_priv->renderctx->gtt_offset |
7998 MI_SAVE_EXT_STATE_EN |
7999 MI_RESTORE_EXT_STATE_EN |
8000 MI_RESTORE_INHIBIT);
8001 OUT_RING(MI_SUSPEND_FLUSH);
8007 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8008 * does an implicit flush, combined with MI_FLUSH above, it should be
8009 * safe to assume that renderctx is valid
8011 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8013 DRM_ERROR("failed to enable ironlake power power savings\n");
8014 ironlake_teardown_rc6(dev);
8015 mutex_unlock(&dev->struct_mutex);
8019 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8020 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8021 mutex_unlock(&dev->struct_mutex);
8024 void intel_init_clock_gating(struct drm_device *dev)
8026 struct drm_i915_private *dev_priv = dev->dev_private;
8028 dev_priv->display.init_clock_gating(dev);
8030 if (dev_priv->display.init_pch_clock_gating)
8031 dev_priv->display.init_pch_clock_gating(dev);
8034 /* Set up chip specific display functions */
8035 static void intel_init_display(struct drm_device *dev)
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8039 /* We always want a DPMS function */
8040 if (HAS_PCH_SPLIT(dev)) {
8041 dev_priv->display.dpms = ironlake_crtc_dpms;
8042 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8043 dev_priv->display.update_plane = ironlake_update_plane;
8045 dev_priv->display.dpms = i9xx_crtc_dpms;
8046 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8047 dev_priv->display.update_plane = i9xx_update_plane;
8050 if (I915_HAS_FBC(dev)) {
8051 if (HAS_PCH_SPLIT(dev)) {
8052 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8053 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8054 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8055 } else if (IS_GM45(dev)) {
8056 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8057 dev_priv->display.enable_fbc = g4x_enable_fbc;
8058 dev_priv->display.disable_fbc = g4x_disable_fbc;
8059 } else if (IS_CRESTLINE(dev)) {
8060 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8061 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8062 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8064 /* 855GM needs testing */
8067 /* Returns the core display clock speed */
8068 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
8069 dev_priv->display.get_display_clock_speed =
8070 i945_get_display_clock_speed;
8071 else if (IS_I915G(dev))
8072 dev_priv->display.get_display_clock_speed =
8073 i915_get_display_clock_speed;
8074 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8075 dev_priv->display.get_display_clock_speed =
8076 i9xx_misc_get_display_clock_speed;
8077 else if (IS_I915GM(dev))
8078 dev_priv->display.get_display_clock_speed =
8079 i915gm_get_display_clock_speed;
8080 else if (IS_I865G(dev))
8081 dev_priv->display.get_display_clock_speed =
8082 i865_get_display_clock_speed;
8083 else if (IS_I85X(dev))
8084 dev_priv->display.get_display_clock_speed =
8085 i855_get_display_clock_speed;
8087 dev_priv->display.get_display_clock_speed =
8088 i830_get_display_clock_speed;
8090 /* For FIFO watermark updates */
8091 if (HAS_PCH_SPLIT(dev)) {
8092 if (HAS_PCH_IBX(dev))
8093 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8094 else if (HAS_PCH_CPT(dev))
8095 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8098 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8099 dev_priv->display.update_wm = ironlake_update_wm;
8101 DRM_DEBUG_KMS("Failed to get proper latency. "
8103 dev_priv->display.update_wm = NULL;
8105 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8106 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8107 } else if (IS_GEN6(dev)) {
8108 if (SNB_READ_WM0_LATENCY()) {
8109 dev_priv->display.update_wm = sandybridge_update_wm;
8111 DRM_DEBUG_KMS("Failed to read display plane latency. "
8113 dev_priv->display.update_wm = NULL;
8115 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8116 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8117 } else if (IS_IVYBRIDGE(dev)) {
8118 /* FIXME: detect B0+ stepping and use auto training */
8119 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8120 if (SNB_READ_WM0_LATENCY()) {
8121 dev_priv->display.update_wm = sandybridge_update_wm;
8123 DRM_DEBUG_KMS("Failed to read display plane latency. "
8125 dev_priv->display.update_wm = NULL;
8127 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8130 dev_priv->display.update_wm = NULL;
8131 } else if (IS_PINEVIEW(dev)) {
8132 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8135 dev_priv->mem_freq)) {
8136 DRM_INFO("failed to find known CxSR latency "
8137 "(found ddr%s fsb freq %d, mem freq %d), "
8139 (dev_priv->is_ddr3 == 1) ? "3": "2",
8140 dev_priv->fsb_freq, dev_priv->mem_freq);
8141 /* Disable CxSR and never update its watermark again */
8142 pineview_disable_cxsr(dev);
8143 dev_priv->display.update_wm = NULL;
8145 dev_priv->display.update_wm = pineview_update_wm;
8146 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8147 } else if (IS_G4X(dev)) {
8148 dev_priv->display.update_wm = g4x_update_wm;
8149 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8150 } else if (IS_GEN4(dev)) {
8151 dev_priv->display.update_wm = i965_update_wm;
8152 if (IS_CRESTLINE(dev))
8153 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8154 else if (IS_BROADWATER(dev))
8155 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8156 } else if (IS_GEN3(dev)) {
8157 dev_priv->display.update_wm = i9xx_update_wm;
8158 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8159 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8160 } else if (IS_I865G(dev)) {
8161 dev_priv->display.update_wm = i830_update_wm;
8162 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8163 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8164 } else if (IS_I85X(dev)) {
8165 dev_priv->display.update_wm = i9xx_update_wm;
8166 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8167 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8169 dev_priv->display.update_wm = i830_update_wm;
8170 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8172 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8174 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8177 /* Default just returns -ENODEV to indicate unsupported */
8178 dev_priv->display.queue_flip = intel_default_queue_flip;
8180 switch (INTEL_INFO(dev)->gen) {
8182 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8186 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8191 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8195 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8198 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8204 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8205 * resume, or other times. This quirk makes sure that's the case for
8208 static void quirk_pipea_force (struct drm_device *dev)
8210 struct drm_i915_private *dev_priv = dev->dev_private;
8212 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8213 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8217 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8219 static void quirk_ssc_force_disable(struct drm_device *dev)
8221 struct drm_i915_private *dev_priv = dev->dev_private;
8222 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8225 struct intel_quirk {
8227 int subsystem_vendor;
8228 int subsystem_device;
8229 void (*hook)(struct drm_device *dev);
8232 struct intel_quirk intel_quirks[] = {
8233 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8234 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8235 /* HP Mini needs pipe A force quirk (LP: #322104) */
8236 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8238 /* Thinkpad R31 needs pipe A force quirk */
8239 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8240 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8241 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8243 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8244 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8245 /* ThinkPad X40 needs pipe A force quirk */
8247 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8248 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8250 /* 855 & before need to leave pipe A & dpll A up */
8251 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8252 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8254 /* Lenovo U160 cannot use SSC on LVDS */
8255 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8257 /* Sony Vaio Y cannot use SSC on LVDS */
8258 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8261 static void intel_init_quirks(struct drm_device *dev)
8263 struct pci_dev *d = dev->pdev;
8266 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8267 struct intel_quirk *q = &intel_quirks[i];
8269 if (d->device == q->device &&
8270 (d->subsystem_vendor == q->subsystem_vendor ||
8271 q->subsystem_vendor == PCI_ANY_ID) &&
8272 (d->subsystem_device == q->subsystem_device ||
8273 q->subsystem_device == PCI_ANY_ID))
8278 /* Disable the VGA plane that we never use */
8279 static void i915_disable_vga(struct drm_device *dev)
8281 struct drm_i915_private *dev_priv = dev->dev_private;
8285 if (HAS_PCH_SPLIT(dev))
8286 vga_reg = CPU_VGACNTRL;
8290 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8291 outb(1, VGA_SR_INDEX);
8292 sr1 = inb(VGA_SR_DATA);
8293 outb(sr1 | 1<<5, VGA_SR_DATA);
8294 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8297 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8298 POSTING_READ(vga_reg);
8301 void intel_modeset_init(struct drm_device *dev)
8303 struct drm_i915_private *dev_priv = dev->dev_private;
8306 drm_mode_config_init(dev);
8308 dev->mode_config.min_width = 0;
8309 dev->mode_config.min_height = 0;
8311 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8313 intel_init_quirks(dev);
8315 intel_init_display(dev);
8318 dev->mode_config.max_width = 2048;
8319 dev->mode_config.max_height = 2048;
8320 } else if (IS_GEN3(dev)) {
8321 dev->mode_config.max_width = 4096;
8322 dev->mode_config.max_height = 4096;
8324 dev->mode_config.max_width = 8192;
8325 dev->mode_config.max_height = 8192;
8327 dev->mode_config.fb_base = dev->agp->base;
8329 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8330 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8332 for (i = 0; i < dev_priv->num_pipe; i++) {
8333 intel_crtc_init(dev, i);
8336 /* Just disable it once at startup */
8337 i915_disable_vga(dev);
8338 intel_setup_outputs(dev);
8340 intel_init_clock_gating(dev);
8342 if (IS_IRONLAKE_M(dev)) {
8343 ironlake_enable_drps(dev);
8344 intel_init_emon(dev);
8347 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8348 gen6_enable_rps(dev_priv);
8349 gen6_update_ring_freq(dev_priv);
8352 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8353 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8354 (unsigned long)dev);
8357 void intel_modeset_gem_init(struct drm_device *dev)
8359 if (IS_IRONLAKE_M(dev))
8360 ironlake_enable_rc6(dev);
8362 intel_setup_overlay(dev);
8365 void intel_modeset_cleanup(struct drm_device *dev)
8367 struct drm_i915_private *dev_priv = dev->dev_private;
8368 struct drm_crtc *crtc;
8369 struct intel_crtc *intel_crtc;
8371 drm_kms_helper_poll_fini(dev);
8372 mutex_lock(&dev->struct_mutex);
8374 intel_unregister_dsm_handler();
8377 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8378 /* Skip inactive CRTCs */
8382 intel_crtc = to_intel_crtc(crtc);
8383 intel_increase_pllclock(crtc);
8386 intel_disable_fbc(dev);
8388 if (IS_IRONLAKE_M(dev))
8389 ironlake_disable_drps(dev);
8390 if (IS_GEN6(dev) || IS_GEN7(dev))
8391 gen6_disable_rps(dev);
8393 if (IS_IRONLAKE_M(dev))
8394 ironlake_disable_rc6(dev);
8396 mutex_unlock(&dev->struct_mutex);
8398 /* Disable the irq before mode object teardown, for the irq might
8399 * enqueue unpin/hotplug work. */
8400 drm_irq_uninstall(dev);
8401 cancel_work_sync(&dev_priv->hotplug_work);
8403 /* flush any delayed tasks or pending work */
8404 flush_scheduled_work();
8406 /* Shut off idle work before the crtcs get freed. */
8407 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8408 intel_crtc = to_intel_crtc(crtc);
8409 del_timer_sync(&intel_crtc->idle_timer);
8411 del_timer_sync(&dev_priv->idle_timer);
8412 cancel_work_sync(&dev_priv->idle_work);
8414 drm_mode_config_cleanup(dev);
8418 * Return which encoder is currently attached for connector.
8420 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8422 return &intel_attached_encoder(connector)->base;
8425 void intel_connector_attach_encoder(struct intel_connector *connector,
8426 struct intel_encoder *encoder)
8428 connector->encoder = encoder;
8429 drm_mode_connector_attach_encoder(&connector->base,
8434 * set vga decode state - true == enable VGA decode
8436 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8438 struct drm_i915_private *dev_priv = dev->dev_private;
8441 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8443 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8445 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8446 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8450 #ifdef CONFIG_DEBUG_FS
8451 #include <linux/seq_file.h>
8453 struct intel_display_error_state {
8454 struct intel_cursor_error_state {
8461 struct intel_pipe_error_state {
8473 struct intel_plane_error_state {
8484 struct intel_display_error_state *
8485 intel_display_capture_error_state(struct drm_device *dev)
8487 drm_i915_private_t *dev_priv = dev->dev_private;
8488 struct intel_display_error_state *error;
8491 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8495 for (i = 0; i < 2; i++) {
8496 error->cursor[i].control = I915_READ(CURCNTR(i));
8497 error->cursor[i].position = I915_READ(CURPOS(i));
8498 error->cursor[i].base = I915_READ(CURBASE(i));
8500 error->plane[i].control = I915_READ(DSPCNTR(i));
8501 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8502 error->plane[i].size = I915_READ(DSPSIZE(i));
8503 error->plane[i].pos= I915_READ(DSPPOS(i));
8504 error->plane[i].addr = I915_READ(DSPADDR(i));
8505 if (INTEL_INFO(dev)->gen >= 4) {
8506 error->plane[i].surface = I915_READ(DSPSURF(i));
8507 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8510 error->pipe[i].conf = I915_READ(PIPECONF(i));
8511 error->pipe[i].source = I915_READ(PIPESRC(i));
8512 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8513 error->pipe[i].hblank = I915_READ(HBLANK(i));
8514 error->pipe[i].hsync = I915_READ(HSYNC(i));
8515 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8516 error->pipe[i].vblank = I915_READ(VBLANK(i));
8517 error->pipe[i].vsync = I915_READ(VSYNC(i));
8524 intel_display_print_error_state(struct seq_file *m,
8525 struct drm_device *dev,
8526 struct intel_display_error_state *error)
8530 for (i = 0; i < 2; i++) {
8531 seq_printf(m, "Pipe [%d]:\n", i);
8532 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8533 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8534 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8535 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8536 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8537 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8538 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8539 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8541 seq_printf(m, "Plane [%d]:\n", i);
8542 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8543 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8544 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8545 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8546 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8547 if (INTEL_INFO(dev)->gen >= 4) {
8548 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8549 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8552 seq_printf(m, "Cursor [%d]:\n", i);
8553 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8554 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8555 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);