2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include "intel_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
118 .find_pll = intel_find_best_PLL,
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
132 .find_pll = intel_find_best_PLL,
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
146 .find_pll = intel_find_best_PLL,
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
160 .find_pll = intel_find_best_PLL,
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
177 .find_pll = intel_g4x_find_best_PLL,
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
191 .find_pll = intel_g4x_find_best_PLL,
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
206 .find_pll = intel_g4x_find_best_PLL,
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
221 .find_pll = intel_g4x_find_best_PLL,
224 static const intel_limit_t intel_limits_g4x_display_port = {
225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
235 .find_pll = intel_find_pll_g4x_dp,
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
251 .find_pll = intel_find_best_PLL,
254 static const intel_limit_t intel_limits_pineview_lvds = {
255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
265 .find_pll = intel_find_best_PLL,
268 /* Ironlake / Sandybridge
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
273 static const intel_limit_t intel_limits_ironlake_dac = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_g4x_find_best_PLL,
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_g4x_find_best_PLL,
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
312 .find_pll = intel_g4x_find_best_PLL,
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 .find_pll = intel_g4x_find_best_PLL,
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 .find_pll = intel_g4x_find_best_PLL,
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
355 .find_pll = intel_find_pll_ironlake_dp,
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 const intel_limit_t *limit;
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_dual_lvds_100m;
372 limit = &intel_limits_ironlake_dual_lvds;
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_single_lvds_100m;
377 limit = &intel_limits_ironlake_single_lvds;
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381 limit = &intel_limits_ironlake_display_port;
383 limit = &intel_limits_ironlake_dac;
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 /* LVDS with dual channel */
398 limit = &intel_limits_g4x_dual_channel_lvds;
400 /* LVDS with dual channel */
401 limit = &intel_limits_g4x_single_channel_lvds;
402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404 limit = &intel_limits_g4x_hdmi;
405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406 limit = &intel_limits_g4x_sdvo;
407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408 limit = &intel_limits_g4x_display_port;
409 } else /* The option is for other outputs */
410 limit = &intel_limits_i9xx_sdvo;
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
420 if (HAS_PCH_SPLIT(dev))
421 limit = intel_ironlake_limit(crtc, refclk);
422 else if (IS_G4X(dev)) {
423 limit = intel_g4x_limit(crtc);
424 } else if (IS_PINEVIEW(dev)) {
425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426 limit = &intel_limits_pineview_lvds;
428 limit = &intel_limits_pineview_sdvo;
429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
433 limit = &intel_limits_i9xx_sdvo;
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i8xx_lvds;
438 limit = &intel_limits_i8xx_dvo;
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
465 * Returns whether any output on the specified pipe is of the specified type
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
480 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526 (I915_READ(LVDS)) != 0) {
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 clock.p2 = limit->p2.p2_fast;
537 clock.p2 = limit->p2.p2_slow;
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
542 clock.p2 = limit->p2.p2_fast;
545 memset (best_clock, 0, sizeof (*best_clock));
547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
560 intel_clock(dev, refclk, &clock);
561 if (!intel_PLL_is_valid(dev, limit,
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
575 return (err != target);
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
594 if (HAS_PCH_SPLIT(dev))
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600 clock.p2 = limit->p2.p2_fast;
602 clock.p2 = limit->p2.p2_slow;
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
607 clock.p2 = limit->p2.p2_fast;
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
612 /* based on hardware requirement, prefer smaller n to precision */
613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614 /* based on hardware requirement, prefere larger m1,m2 */
615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
623 intel_clock(dev, refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
628 this_err = abs(clock.dot - target);
629 if (this_err < err_most) {
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
646 struct drm_device *dev = crtc->dev;
649 if (target < 200000) {
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
673 if (target < 200000) {
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
695 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @pipe: pipe to wait for
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int pipestat_reg = PIPESTAT(pipe);
707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723 /* Wait for vblank interrupt bit to set */
724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
727 DRM_DEBUG_KMS("vblank wait timed out\n");
731 * intel_wait_for_pipe_off - wait for pipe to turn off
733 * @pipe: pipe to wait for
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
740 * wait for the pipe register state bit to turn off
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 struct drm_i915_private *dev_priv = dev->dev_private;
751 if (INTEL_INFO(dev)->gen >= 4) {
752 int reg = PIPECONF(pipe);
754 /* Wait for the Pipe State to go off */
755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
760 int reg = PIPEDSL(pipe);
761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763 /* Wait for the display line to settle */
765 last_line = I915_READ(reg) & DSL_LINEMASK;
767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
774 static const char *state_string(bool enabled)
776 return enabled ? "on" : "off";
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
878 int pp_reg, lvds_reg;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
916 pipe_name(pipe), state_string(state), state_string(cur_state));
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
989 reg, pipe_name(pipe));
992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
998 reg, pipe_name(pipe));
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1012 val = I915_READ(reg);
1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
1018 val = I915_READ(reg);
1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1037 * Note! This is for pre-ILK only.
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1064 udelay(150); /* wait for warmup */
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1074 * Note! This is for pre-ILK only.
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1175 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1198 * intel_enable_pipe - enable a pipe, asserting requirements
1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1206 * @pipe should be %PIPE_A or %PIPE_B.
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1211 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1230 /* FIXME: assert CPU port conditions for SNB+ */
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
1235 if (val & PIPECONF_ENABLE)
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1243 * intel_disable_pipe - disable a pipe, asserting requirements
1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1250 * @pipe should be %PIPE_A or %PIPE_B.
1252 * Will wait until the pipe has shut down before returning.
1254 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1264 assert_planes_disabled(dev_priv, pipe);
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
1272 if ((val & PIPECONF_ENABLE) == 0)
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1287 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
1298 if (val & DISPLAY_PLANE_ENABLE)
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1309 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1322 * Disable @plane; should be an independent operation.
1324 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1340 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1348 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1356 /* Disable any ports connected to this transcoder */
1357 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1387 static void i8xx_disable_fbc(struct drm_device *dev)
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1392 /* Disable compression */
1393 fbc_ctl = I915_READ(FBC_CONTROL);
1394 if ((fbc_ctl & FBC_CTL_EN) == 0)
1397 fbc_ctl &= ~FBC_CTL_EN;
1398 I915_WRITE(FBC_CONTROL, fbc_ctl);
1400 /* Wait for compressing bit to clear */
1401 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402 DRM_DEBUG_KMS("FBC idle timed out\n");
1406 DRM_DEBUG_KMS("disabled FBC\n");
1409 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1411 struct drm_device *dev = crtc->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_framebuffer *fb = crtc->fb;
1414 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1415 struct drm_i915_gem_object *obj = intel_fb->obj;
1416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1419 u32 fbc_ctl, fbc_ctl2;
1421 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1422 if (fb->pitch < cfb_pitch)
1423 cfb_pitch = fb->pitch;
1425 /* FBC_CTL wants 64B units */
1426 cfb_pitch = (cfb_pitch / 64) - 1;
1427 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1429 /* Clear old tags */
1430 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1431 I915_WRITE(FBC_TAG + (i * 4), 0);
1434 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1436 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1437 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1440 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1442 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1443 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1444 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1445 fbc_ctl |= obj->fence_reg;
1446 I915_WRITE(FBC_CONTROL, fbc_ctl);
1448 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1449 cfb_pitch, crtc->y, intel_crtc->plane);
1452 static bool i8xx_fbc_enabled(struct drm_device *dev)
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1456 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1459 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1461 struct drm_device *dev = crtc->dev;
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 struct drm_framebuffer *fb = crtc->fb;
1464 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1465 struct drm_i915_gem_object *obj = intel_fb->obj;
1466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1467 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1468 unsigned long stall_watermark = 200;
1471 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1472 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1473 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1475 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1476 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1477 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1478 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1481 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1483 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1486 static void g4x_disable_fbc(struct drm_device *dev)
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1491 /* Disable compression */
1492 dpfc_ctl = I915_READ(DPFC_CONTROL);
1493 if (dpfc_ctl & DPFC_CTL_EN) {
1494 dpfc_ctl &= ~DPFC_CTL_EN;
1495 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1497 DRM_DEBUG_KMS("disabled FBC\n");
1501 static bool g4x_fbc_enabled(struct drm_device *dev)
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1505 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1508 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1513 /* Make sure blitter notifies FBC of writes */
1514 gen6_gt_force_wake_get(dev_priv);
1515 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1516 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1517 GEN6_BLITTER_LOCK_SHIFT;
1518 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1519 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1520 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1521 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1522 GEN6_BLITTER_LOCK_SHIFT);
1523 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1524 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1525 gen6_gt_force_wake_put(dev_priv);
1528 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1530 struct drm_device *dev = crtc->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct drm_framebuffer *fb = crtc->fb;
1533 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1534 struct drm_i915_gem_object *obj = intel_fb->obj;
1535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1536 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1537 unsigned long stall_watermark = 200;
1540 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1541 dpfc_ctl &= DPFC_RESERVED;
1542 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1543 /* Set persistent mode for front-buffer rendering, ala X. */
1544 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1545 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1546 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1548 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1549 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1550 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1551 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1552 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1554 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1557 I915_WRITE(SNB_DPFC_CTL_SA,
1558 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1559 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1560 sandybridge_blit_fbc_update(dev);
1563 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1566 static void ironlake_disable_fbc(struct drm_device *dev)
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1571 /* Disable compression */
1572 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1573 if (dpfc_ctl & DPFC_CTL_EN) {
1574 dpfc_ctl &= ~DPFC_CTL_EN;
1575 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1577 DRM_DEBUG_KMS("disabled FBC\n");
1581 static bool ironlake_fbc_enabled(struct drm_device *dev)
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1585 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1588 bool intel_fbc_enabled(struct drm_device *dev)
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1592 if (!dev_priv->display.fbc_enabled)
1595 return dev_priv->display.fbc_enabled(dev);
1598 static void intel_fbc_work_fn(struct work_struct *__work)
1600 struct intel_fbc_work *work =
1601 container_of(to_delayed_work(__work),
1602 struct intel_fbc_work, work);
1603 struct drm_device *dev = work->crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1606 mutex_lock(&dev->struct_mutex);
1607 if (work == dev_priv->fbc_work) {
1608 /* Double check that we haven't switched fb without cancelling
1611 if (work->crtc->fb == work->fb) {
1612 dev_priv->display.enable_fbc(work->crtc,
1615 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1616 dev_priv->cfb_fb = work->crtc->fb->base.id;
1617 dev_priv->cfb_y = work->crtc->y;
1620 dev_priv->fbc_work = NULL;
1622 mutex_unlock(&dev->struct_mutex);
1627 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1629 if (dev_priv->fbc_work == NULL)
1632 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1634 /* Synchronisation is provided by struct_mutex and checking of
1635 * dev_priv->fbc_work, so we can perform the cancellation
1636 * entirely asynchronously.
1638 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1639 /* tasklet was killed before being run, clean up */
1640 kfree(dev_priv->fbc_work);
1642 /* Mark the work as no longer wanted so that if it does
1643 * wake-up (because the work was already running and waiting
1644 * for our mutex), it will discover that is no longer
1647 dev_priv->fbc_work = NULL;
1650 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1652 struct intel_fbc_work *work;
1653 struct drm_device *dev = crtc->dev;
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1656 if (!dev_priv->display.enable_fbc)
1659 intel_cancel_fbc_work(dev_priv);
1661 work = kzalloc(sizeof *work, GFP_KERNEL);
1663 dev_priv->display.enable_fbc(crtc, interval);
1668 work->fb = crtc->fb;
1669 work->interval = interval;
1670 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1672 dev_priv->fbc_work = work;
1674 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1676 /* Delay the actual enabling to let pageflipping cease and the
1677 * display to settle before starting the compression. Note that
1678 * this delay also serves a second purpose: it allows for a
1679 * vblank to pass after disabling the FBC before we attempt
1680 * to modify the control registers.
1682 * A more complicated solution would involve tracking vblanks
1683 * following the termination of the page-flipping sequence
1684 * and indeed performing the enable as a co-routine and not
1685 * waiting synchronously upon the vblank.
1687 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1690 void intel_disable_fbc(struct drm_device *dev)
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1694 intel_cancel_fbc_work(dev_priv);
1696 if (!dev_priv->display.disable_fbc)
1699 dev_priv->display.disable_fbc(dev);
1700 dev_priv->cfb_plane = -1;
1704 * intel_update_fbc - enable/disable FBC as needed
1705 * @dev: the drm_device
1707 * Set up the framebuffer compression hardware at mode set time. We
1708 * enable it if possible:
1709 * - plane A only (on pre-965)
1710 * - no pixel mulitply/line duplication
1711 * - no alpha buffer discard
1713 * - framebuffer <= 2048 in width, 1536 in height
1715 * We can't assume that any compression will take place (worst case),
1716 * so the compressed buffer has to be the same size as the uncompressed
1717 * one. It also must reside (along with the line length buffer) in
1720 * We need to enable/disable FBC on a global basis.
1722 static void intel_update_fbc(struct drm_device *dev)
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 struct drm_crtc *crtc = NULL, *tmp_crtc;
1726 struct intel_crtc *intel_crtc;
1727 struct drm_framebuffer *fb;
1728 struct intel_framebuffer *intel_fb;
1729 struct drm_i915_gem_object *obj;
1731 DRM_DEBUG_KMS("\n");
1733 if (!i915_powersave)
1736 if (!I915_HAS_FBC(dev))
1740 * If FBC is already on, we just have to verify that we can
1741 * keep it that way...
1742 * Need to disable if:
1743 * - more than one pipe is active
1744 * - changing FBC params (stride, fence, mode)
1745 * - new fb is too large to fit in compressed buffer
1746 * - going to an unsupported config (interlace, pixel multiply, etc.)
1748 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1749 if (tmp_crtc->enabled && tmp_crtc->fb) {
1751 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1752 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1759 if (!crtc || crtc->fb == NULL) {
1760 DRM_DEBUG_KMS("no output, disabling\n");
1761 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1765 intel_crtc = to_intel_crtc(crtc);
1767 intel_fb = to_intel_framebuffer(fb);
1768 obj = intel_fb->obj;
1770 if (!i915_enable_fbc) {
1771 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1772 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1775 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1776 DRM_DEBUG_KMS("framebuffer too large, disabling "
1778 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1781 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1782 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1783 DRM_DEBUG_KMS("mode incompatible with compression, "
1785 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1788 if ((crtc->mode.hdisplay > 2048) ||
1789 (crtc->mode.vdisplay > 1536)) {
1790 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1791 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1794 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1795 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1796 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1800 /* The use of a CPU fence is mandatory in order to detect writes
1801 * by the CPU to the scanout and trigger updates to the FBC.
1803 if (obj->tiling_mode != I915_TILING_X ||
1804 obj->fence_reg == I915_FENCE_REG_NONE) {
1805 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1806 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1810 /* If the kernel debugger is active, always disable compression */
1811 if (in_dbg_master())
1814 /* If the scanout has not changed, don't modify the FBC settings.
1815 * Note that we make the fundamental assumption that the fb->obj
1816 * cannot be unpinned (and have its GTT offset and fence revoked)
1817 * without first being decoupled from the scanout and FBC disabled.
1819 if (dev_priv->cfb_plane == intel_crtc->plane &&
1820 dev_priv->cfb_fb == fb->base.id &&
1821 dev_priv->cfb_y == crtc->y)
1824 if (intel_fbc_enabled(dev)) {
1825 /* We update FBC along two paths, after changing fb/crtc
1826 * configuration (modeswitching) and after page-flipping
1827 * finishes. For the latter, we know that not only did
1828 * we disable the FBC at the start of the page-flip
1829 * sequence, but also more than one vblank has passed.
1831 * For the former case of modeswitching, it is possible
1832 * to switch between two FBC valid configurations
1833 * instantaneously so we do need to disable the FBC
1834 * before we can modify its control registers. We also
1835 * have to wait for the next vblank for that to take
1836 * effect. However, since we delay enabling FBC we can
1837 * assume that a vblank has passed since disabling and
1838 * that we can safely alter the registers in the deferred
1841 * In the scenario that we go from a valid to invalid
1842 * and then back to valid FBC configuration we have
1843 * no strict enforcement that a vblank occurred since
1844 * disabling the FBC. However, along all current pipe
1845 * disabling paths we do need to wait for a vblank at
1846 * some point. And we wait before enabling FBC anyway.
1848 DRM_DEBUG_KMS("disabling active FBC for update\n");
1849 intel_disable_fbc(dev);
1852 intel_enable_fbc(crtc, 500);
1856 /* Multiple disables should be harmless */
1857 if (intel_fbc_enabled(dev)) {
1858 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1859 intel_disable_fbc(dev);
1864 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1865 struct drm_i915_gem_object *obj,
1866 struct intel_ring_buffer *pipelined)
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1872 switch (obj->tiling_mode) {
1873 case I915_TILING_NONE:
1874 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1875 alignment = 128 * 1024;
1876 else if (INTEL_INFO(dev)->gen >= 4)
1877 alignment = 4 * 1024;
1879 alignment = 64 * 1024;
1882 /* pin() will align the object as required by fence */
1886 /* FIXME: Is this true? */
1887 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1893 dev_priv->mm.interruptible = false;
1894 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1896 goto err_interruptible;
1898 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899 * fence, whereas 965+ only requires a fence if using
1900 * framebuffer compression. For simplicity, we always install
1901 * a fence as the cost is not that onerous.
1903 if (obj->tiling_mode != I915_TILING_NONE) {
1904 ret = i915_gem_object_get_fence(obj, pipelined);
1909 dev_priv->mm.interruptible = true;
1913 i915_gem_object_unpin(obj);
1915 dev_priv->mm.interruptible = true;
1919 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1922 struct drm_device *dev = crtc->dev;
1923 struct drm_i915_private *dev_priv = dev->dev_private;
1924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1925 struct intel_framebuffer *intel_fb;
1926 struct drm_i915_gem_object *obj;
1927 int plane = intel_crtc->plane;
1928 unsigned long Start, Offset;
1937 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1941 intel_fb = to_intel_framebuffer(fb);
1942 obj = intel_fb->obj;
1944 reg = DSPCNTR(plane);
1945 dspcntr = I915_READ(reg);
1946 /* Mask out pixel format bits in case we change it */
1947 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1948 switch (fb->bits_per_pixel) {
1950 dspcntr |= DISPPLANE_8BPP;
1953 if (fb->depth == 15)
1954 dspcntr |= DISPPLANE_15_16BPP;
1956 dspcntr |= DISPPLANE_16BPP;
1960 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1963 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1966 if (INTEL_INFO(dev)->gen >= 4) {
1967 if (obj->tiling_mode != I915_TILING_NONE)
1968 dspcntr |= DISPPLANE_TILED;
1970 dspcntr &= ~DISPPLANE_TILED;
1973 I915_WRITE(reg, dspcntr);
1975 Start = obj->gtt_offset;
1976 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1978 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1979 Start, Offset, x, y, fb->pitch);
1980 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1981 if (INTEL_INFO(dev)->gen >= 4) {
1982 I915_WRITE(DSPSURF(plane), Start);
1983 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1984 I915_WRITE(DSPADDR(plane), Offset);
1986 I915_WRITE(DSPADDR(plane), Start + Offset);
1992 static int ironlake_update_plane(struct drm_crtc *crtc,
1993 struct drm_framebuffer *fb, int x, int y)
1995 struct drm_device *dev = crtc->dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998 struct intel_framebuffer *intel_fb;
1999 struct drm_i915_gem_object *obj;
2000 int plane = intel_crtc->plane;
2001 unsigned long Start, Offset;
2010 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2014 intel_fb = to_intel_framebuffer(fb);
2015 obj = intel_fb->obj;
2017 reg = DSPCNTR(plane);
2018 dspcntr = I915_READ(reg);
2019 /* Mask out pixel format bits in case we change it */
2020 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021 switch (fb->bits_per_pixel) {
2023 dspcntr |= DISPPLANE_8BPP;
2026 if (fb->depth != 16)
2029 dspcntr |= DISPPLANE_16BPP;
2033 if (fb->depth == 24)
2034 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2035 else if (fb->depth == 30)
2036 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2041 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2045 if (obj->tiling_mode != I915_TILING_NONE)
2046 dspcntr |= DISPPLANE_TILED;
2048 dspcntr &= ~DISPPLANE_TILED;
2051 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2053 I915_WRITE(reg, dspcntr);
2055 Start = obj->gtt_offset;
2056 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2058 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059 Start, Offset, x, y, fb->pitch);
2060 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2061 I915_WRITE(DSPSURF(plane), Start);
2062 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063 I915_WRITE(DSPADDR(plane), Offset);
2069 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2071 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2072 int x, int y, enum mode_set_atomic state)
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2078 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2082 intel_update_fbc(dev);
2083 intel_increase_pllclock(crtc);
2089 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2090 struct drm_framebuffer *old_fb)
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_master_private *master_priv;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2099 DRM_DEBUG_KMS("No FB bound\n");
2103 switch (intel_crtc->plane) {
2111 mutex_lock(&dev->struct_mutex);
2112 ret = intel_pin_and_fence_fb_obj(dev,
2113 to_intel_framebuffer(crtc->fb)->obj,
2116 mutex_unlock(&dev->struct_mutex);
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2124 wait_event(dev_priv->pending_flip_queue,
2125 atomic_read(&dev_priv->mm.wedged) ||
2126 atomic_read(&obj->pending_flip) == 0);
2128 /* Big Hammer, we also need to ensure that any pending
2129 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2130 * current scanout is retired before unpinning the old
2133 * This should only fail upon a hung GPU, in which case we
2134 * can safely continue.
2136 ret = i915_gem_object_finish_gpu(obj);
2140 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2141 LEAVE_ATOMIC_MODE_SET);
2143 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2144 mutex_unlock(&dev->struct_mutex);
2149 intel_wait_for_vblank(dev, intel_crtc->pipe);
2150 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2153 mutex_unlock(&dev->struct_mutex);
2155 if (!dev->primary->master)
2158 master_priv = dev->primary->master->driver_priv;
2159 if (!master_priv->sarea_priv)
2162 if (intel_crtc->pipe) {
2163 master_priv->sarea_priv->pipeB_x = x;
2164 master_priv->sarea_priv->pipeB_y = y;
2166 master_priv->sarea_priv->pipeA_x = x;
2167 master_priv->sarea_priv->pipeA_y = y;
2173 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2179 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2180 dpa_ctl = I915_READ(DP_A);
2181 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2183 if (clock < 200000) {
2185 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2186 /* workaround for 160Mhz:
2187 1) program 0x4600c bits 15:0 = 0x8124
2188 2) program 0x46010 bit 0 = 1
2189 3) program 0x46034 bit 24 = 1
2190 4) program 0x64000 bit 14 = 1
2192 temp = I915_READ(0x4600c);
2194 I915_WRITE(0x4600c, temp | 0x8124);
2196 temp = I915_READ(0x46010);
2197 I915_WRITE(0x46010, temp | 1);
2199 temp = I915_READ(0x46034);
2200 I915_WRITE(0x46034, temp | (1 << 24));
2202 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2204 I915_WRITE(DP_A, dpa_ctl);
2210 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2212 struct drm_device *dev = crtc->dev;
2213 struct drm_i915_private *dev_priv = dev->dev_private;
2214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215 int pipe = intel_crtc->pipe;
2218 /* enable normal train */
2219 reg = FDI_TX_CTL(pipe);
2220 temp = I915_READ(reg);
2221 if (IS_IVYBRIDGE(dev)) {
2222 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2223 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2225 temp &= ~FDI_LINK_TRAIN_NONE;
2226 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2228 I915_WRITE(reg, temp);
2230 reg = FDI_RX_CTL(pipe);
2231 temp = I915_READ(reg);
2232 if (HAS_PCH_CPT(dev)) {
2233 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2234 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2236 temp &= ~FDI_LINK_TRAIN_NONE;
2237 temp |= FDI_LINK_TRAIN_NONE;
2239 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2241 /* wait one idle pattern time */
2245 /* IVB wants error correction enabled */
2246 if (IS_IVYBRIDGE(dev))
2247 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2248 FDI_FE_ERRC_ENABLE);
2251 /* The FDI link training functions for ILK/Ibexpeak. */
2252 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2254 struct drm_device *dev = crtc->dev;
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257 int pipe = intel_crtc->pipe;
2258 int plane = intel_crtc->plane;
2259 u32 reg, temp, tries;
2261 /* FDI needs bits from pipe & plane first */
2262 assert_pipe_enabled(dev_priv, pipe);
2263 assert_plane_enabled(dev_priv, plane);
2265 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2267 reg = FDI_RX_IMR(pipe);
2268 temp = I915_READ(reg);
2269 temp &= ~FDI_RX_SYMBOL_LOCK;
2270 temp &= ~FDI_RX_BIT_LOCK;
2271 I915_WRITE(reg, temp);
2275 /* enable CPU FDI TX and PCH FDI RX */
2276 reg = FDI_TX_CTL(pipe);
2277 temp = I915_READ(reg);
2279 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_PATTERN_1;
2282 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 temp &= ~FDI_LINK_TRAIN_NONE;
2287 temp |= FDI_LINK_TRAIN_PATTERN_1;
2288 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2293 /* Ironlake workaround, enable clock pointer after FDI enable*/
2294 if (HAS_PCH_IBX(dev)) {
2295 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2296 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2297 FDI_RX_PHASE_SYNC_POINTER_EN);
2300 reg = FDI_RX_IIR(pipe);
2301 for (tries = 0; tries < 5; tries++) {
2302 temp = I915_READ(reg);
2303 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2305 if ((temp & FDI_RX_BIT_LOCK)) {
2306 DRM_DEBUG_KMS("FDI train 1 done.\n");
2307 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2312 DRM_ERROR("FDI train 1 fail!\n");
2315 reg = FDI_TX_CTL(pipe);
2316 temp = I915_READ(reg);
2317 temp &= ~FDI_LINK_TRAIN_NONE;
2318 temp |= FDI_LINK_TRAIN_PATTERN_2;
2319 I915_WRITE(reg, temp);
2321 reg = FDI_RX_CTL(pipe);
2322 temp = I915_READ(reg);
2323 temp &= ~FDI_LINK_TRAIN_NONE;
2324 temp |= FDI_LINK_TRAIN_PATTERN_2;
2325 I915_WRITE(reg, temp);
2330 reg = FDI_RX_IIR(pipe);
2331 for (tries = 0; tries < 5; tries++) {
2332 temp = I915_READ(reg);
2333 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2335 if (temp & FDI_RX_SYMBOL_LOCK) {
2336 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2337 DRM_DEBUG_KMS("FDI train 2 done.\n");
2342 DRM_ERROR("FDI train 2 fail!\n");
2344 DRM_DEBUG_KMS("FDI train done\n");
2348 static const int snb_b_fdi_train_param [] = {
2349 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2350 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2351 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2352 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2355 /* The FDI link training functions for SNB/Cougarpoint. */
2356 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2358 struct drm_device *dev = crtc->dev;
2359 struct drm_i915_private *dev_priv = dev->dev_private;
2360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2361 int pipe = intel_crtc->pipe;
2364 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2366 reg = FDI_RX_IMR(pipe);
2367 temp = I915_READ(reg);
2368 temp &= ~FDI_RX_SYMBOL_LOCK;
2369 temp &= ~FDI_RX_BIT_LOCK;
2370 I915_WRITE(reg, temp);
2375 /* enable CPU FDI TX and PCH FDI RX */
2376 reg = FDI_TX_CTL(pipe);
2377 temp = I915_READ(reg);
2379 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2380 temp &= ~FDI_LINK_TRAIN_NONE;
2381 temp |= FDI_LINK_TRAIN_PATTERN_1;
2382 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2384 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2385 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 if (HAS_PCH_CPT(dev)) {
2390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2393 temp &= ~FDI_LINK_TRAIN_NONE;
2394 temp |= FDI_LINK_TRAIN_PATTERN_1;
2396 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2401 for (i = 0; i < 4; i++ ) {
2402 reg = FDI_TX_CTL(pipe);
2403 temp = I915_READ(reg);
2404 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2405 temp |= snb_b_fdi_train_param[i];
2406 I915_WRITE(reg, temp);
2411 reg = FDI_RX_IIR(pipe);
2412 temp = I915_READ(reg);
2413 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415 if (temp & FDI_RX_BIT_LOCK) {
2416 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2422 DRM_ERROR("FDI train 1 fail!\n");
2425 reg = FDI_TX_CTL(pipe);
2426 temp = I915_READ(reg);
2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_2;
2430 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2432 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2434 I915_WRITE(reg, temp);
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 if (HAS_PCH_CPT(dev)) {
2439 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_PATTERN_2;
2445 I915_WRITE(reg, temp);
2450 for (i = 0; i < 4; i++ ) {
2451 reg = FDI_TX_CTL(pipe);
2452 temp = I915_READ(reg);
2453 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454 temp |= snb_b_fdi_train_param[i];
2455 I915_WRITE(reg, temp);
2460 reg = FDI_RX_IIR(pipe);
2461 temp = I915_READ(reg);
2462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464 if (temp & FDI_RX_SYMBOL_LOCK) {
2465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2466 DRM_DEBUG_KMS("FDI train 2 done.\n");
2471 DRM_ERROR("FDI train 2 fail!\n");
2473 DRM_DEBUG_KMS("FDI train done.\n");
2476 /* Manual link training for Ivy Bridge A0 parts */
2477 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2479 struct drm_device *dev = crtc->dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482 int pipe = intel_crtc->pipe;
2485 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2487 reg = FDI_RX_IMR(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~FDI_RX_SYMBOL_LOCK;
2490 temp &= ~FDI_RX_BIT_LOCK;
2491 I915_WRITE(reg, temp);
2496 /* enable CPU FDI TX and PCH FDI RX */
2497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
2500 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2501 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
2509 temp &= ~FDI_LINK_TRAIN_AUTO;
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517 for (i = 0; i < 4; i++ ) {
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2521 temp |= snb_b_fdi_train_param[i];
2522 I915_WRITE(reg, temp);
2527 reg = FDI_RX_IIR(pipe);
2528 temp = I915_READ(reg);
2529 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2531 if (temp & FDI_RX_BIT_LOCK ||
2532 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2533 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2534 DRM_DEBUG_KMS("FDI train 1 done.\n");
2539 DRM_ERROR("FDI train 1 fail!\n");
2542 reg = FDI_TX_CTL(pipe);
2543 temp = I915_READ(reg);
2544 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2545 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2548 I915_WRITE(reg, temp);
2550 reg = FDI_RX_CTL(pipe);
2551 temp = I915_READ(reg);
2552 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2554 I915_WRITE(reg, temp);
2559 for (i = 0; i < 4; i++ ) {
2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
2562 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563 temp |= snb_b_fdi_train_param[i];
2564 I915_WRITE(reg, temp);
2569 reg = FDI_RX_IIR(pipe);
2570 temp = I915_READ(reg);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2580 DRM_ERROR("FDI train 2 fail!\n");
2582 DRM_DEBUG_KMS("FDI train done.\n");
2585 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2587 struct drm_device *dev = crtc->dev;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2590 int pipe = intel_crtc->pipe;
2593 /* Write the TU size bits so error detection works */
2594 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2595 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2597 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2598 reg = FDI_RX_CTL(pipe);
2599 temp = I915_READ(reg);
2600 temp &= ~((0x7 << 19) | (0x7 << 16));
2601 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2602 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2603 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2608 /* Switch from Rawclk to PCDclk */
2609 temp = I915_READ(reg);
2610 I915_WRITE(reg, temp | FDI_PCDCLK);
2615 /* Enable CPU FDI TX PLL, always on for Ironlake */
2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2619 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2626 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2628 struct drm_device *dev = crtc->dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631 int pipe = intel_crtc->pipe;
2634 /* disable CPU FDI tx and PCH FDI rx */
2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2640 reg = FDI_RX_CTL(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~(0x7 << 16);
2643 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2644 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2649 /* Ironlake workaround, disable clock pointer after downing FDI */
2650 if (HAS_PCH_IBX(dev)) {
2651 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2652 I915_WRITE(FDI_RX_CHICKEN(pipe),
2653 I915_READ(FDI_RX_CHICKEN(pipe) &
2654 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2657 /* still set train pattern 1 */
2658 reg = FDI_TX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_NONE;
2661 temp |= FDI_LINK_TRAIN_PATTERN_1;
2662 I915_WRITE(reg, temp);
2664 reg = FDI_RX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 if (HAS_PCH_CPT(dev)) {
2667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2670 temp &= ~FDI_LINK_TRAIN_NONE;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1;
2673 /* BPC in FDI rx is consistent with that in PIPECONF */
2674 temp &= ~(0x07 << 16);
2675 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2676 I915_WRITE(reg, temp);
2683 * When we disable a pipe, we need to clear any pending scanline wait events
2684 * to avoid hanging the ring, which we assume we are waiting on.
2686 static void intel_clear_scanline_wait(struct drm_device *dev)
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_ring_buffer *ring;
2693 /* Can't break the hang on i8xx */
2696 ring = LP_RING(dev_priv);
2697 tmp = I915_READ_CTL(ring);
2698 if (tmp & RING_WAIT)
2699 I915_WRITE_CTL(ring, tmp);
2702 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2704 struct drm_i915_gem_object *obj;
2705 struct drm_i915_private *dev_priv;
2707 if (crtc->fb == NULL)
2710 obj = to_intel_framebuffer(crtc->fb)->obj;
2711 dev_priv = crtc->dev->dev_private;
2712 wait_event(dev_priv->pending_flip_queue,
2713 atomic_read(&obj->pending_flip) == 0);
2716 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2718 struct drm_device *dev = crtc->dev;
2719 struct drm_mode_config *mode_config = &dev->mode_config;
2720 struct intel_encoder *encoder;
2723 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2724 * must be driven by its own crtc; no sharing is possible.
2726 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2727 if (encoder->base.crtc != crtc)
2730 switch (encoder->type) {
2731 case INTEL_OUTPUT_EDP:
2732 if (!intel_encoder_is_pch_edp(&encoder->base))
2742 * Enable PCH resources required for PCH ports:
2744 * - FDI training & RX/TX
2745 * - update transcoder timings
2746 * - DP transcoding bits
2749 static void ironlake_pch_enable(struct drm_crtc *crtc)
2751 struct drm_device *dev = crtc->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int pipe = intel_crtc->pipe;
2757 /* For PCH output, training FDI link */
2758 dev_priv->display.fdi_link_train(crtc);
2760 intel_enable_pch_pll(dev_priv, pipe);
2762 if (HAS_PCH_CPT(dev)) {
2763 /* Be sure PCH DPLL SEL is set */
2764 temp = I915_READ(PCH_DPLL_SEL);
2765 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2766 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2767 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2768 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2769 I915_WRITE(PCH_DPLL_SEL, temp);
2772 /* set transcoder timing, panel must allow it */
2773 assert_panel_unlocked(dev_priv, pipe);
2774 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2775 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2776 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2778 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2779 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2780 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2782 intel_fdi_normal_train(crtc);
2784 /* For PCH DP, enable TRANS_DP_CTL */
2785 if (HAS_PCH_CPT(dev) &&
2786 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2787 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2788 reg = TRANS_DP_CTL(pipe);
2789 temp = I915_READ(reg);
2790 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2791 TRANS_DP_SYNC_MASK |
2793 temp |= (TRANS_DP_OUTPUT_ENABLE |
2794 TRANS_DP_ENH_FRAMING);
2795 temp |= bpc << 9; /* same format but at 11:9 */
2797 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2798 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2799 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2800 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2802 switch (intel_trans_dp_port_sel(crtc)) {
2804 temp |= TRANS_DP_PORT_SEL_B;
2807 temp |= TRANS_DP_PORT_SEL_C;
2810 temp |= TRANS_DP_PORT_SEL_D;
2813 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2814 temp |= TRANS_DP_PORT_SEL_B;
2818 I915_WRITE(reg, temp);
2821 intel_enable_transcoder(dev_priv, pipe);
2824 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2826 struct drm_device *dev = crtc->dev;
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2829 int pipe = intel_crtc->pipe;
2830 int plane = intel_crtc->plane;
2834 if (intel_crtc->active)
2837 intel_crtc->active = true;
2838 intel_update_watermarks(dev);
2840 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2841 temp = I915_READ(PCH_LVDS);
2842 if ((temp & LVDS_PORT_EN) == 0)
2843 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2846 is_pch_port = intel_crtc_driving_pch(crtc);
2849 ironlake_fdi_pll_enable(crtc);
2851 ironlake_fdi_disable(crtc);
2853 /* Enable panel fitting for LVDS */
2854 if (dev_priv->pch_pf_size &&
2855 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2856 /* Force use of hard-coded filter coefficients
2857 * as some pre-programmed values are broken,
2860 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2861 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2862 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2865 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2866 intel_enable_plane(dev_priv, plane, pipe);
2869 ironlake_pch_enable(crtc);
2871 intel_crtc_load_lut(crtc);
2873 mutex_lock(&dev->struct_mutex);
2874 intel_update_fbc(dev);
2875 mutex_unlock(&dev->struct_mutex);
2877 intel_crtc_update_cursor(crtc, true);
2880 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2882 struct drm_device *dev = crtc->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 int pipe = intel_crtc->pipe;
2886 int plane = intel_crtc->plane;
2889 if (!intel_crtc->active)
2892 intel_crtc_wait_for_pending_flips(crtc);
2893 drm_vblank_off(dev, pipe);
2894 intel_crtc_update_cursor(crtc, false);
2896 intel_disable_plane(dev_priv, plane, pipe);
2898 if (dev_priv->cfb_plane == plane)
2899 intel_disable_fbc(dev);
2901 intel_disable_pipe(dev_priv, pipe);
2904 I915_WRITE(PF_CTL(pipe), 0);
2905 I915_WRITE(PF_WIN_SZ(pipe), 0);
2907 ironlake_fdi_disable(crtc);
2909 /* This is a horrible layering violation; we should be doing this in
2910 * the connector/encoder ->prepare instead, but we don't always have
2911 * enough information there about the config to know whether it will
2912 * actually be necessary or just cause undesired flicker.
2914 intel_disable_pch_ports(dev_priv, pipe);
2916 intel_disable_transcoder(dev_priv, pipe);
2918 if (HAS_PCH_CPT(dev)) {
2919 /* disable TRANS_DP_CTL */
2920 reg = TRANS_DP_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2923 temp |= TRANS_DP_PORT_SEL_NONE;
2924 I915_WRITE(reg, temp);
2926 /* disable DPLL_SEL */
2927 temp = I915_READ(PCH_DPLL_SEL);
2930 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2933 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2936 /* FIXME: manage transcoder PLLs? */
2937 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2942 I915_WRITE(PCH_DPLL_SEL, temp);
2945 /* disable PCH DPLL */
2946 intel_disable_pch_pll(dev_priv, pipe);
2948 /* Switch from PCDclk to Rawclk */
2949 reg = FDI_RX_CTL(pipe);
2950 temp = I915_READ(reg);
2951 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2953 /* Disable CPU FDI TX PLL */
2954 reg = FDI_TX_CTL(pipe);
2955 temp = I915_READ(reg);
2956 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2961 reg = FDI_RX_CTL(pipe);
2962 temp = I915_READ(reg);
2963 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2965 /* Wait for the clocks to turn off. */
2969 intel_crtc->active = false;
2970 intel_update_watermarks(dev);
2972 mutex_lock(&dev->struct_mutex);
2973 intel_update_fbc(dev);
2974 intel_clear_scanline_wait(dev);
2975 mutex_unlock(&dev->struct_mutex);
2978 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2981 int pipe = intel_crtc->pipe;
2982 int plane = intel_crtc->plane;
2984 /* XXX: When our outputs are all unaware of DPMS modes other than off
2985 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2988 case DRM_MODE_DPMS_ON:
2989 case DRM_MODE_DPMS_STANDBY:
2990 case DRM_MODE_DPMS_SUSPEND:
2991 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2992 ironlake_crtc_enable(crtc);
2995 case DRM_MODE_DPMS_OFF:
2996 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2997 ironlake_crtc_disable(crtc);
3002 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3004 if (!enable && intel_crtc->overlay) {
3005 struct drm_device *dev = intel_crtc->base.dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3008 mutex_lock(&dev->struct_mutex);
3009 dev_priv->mm.interruptible = false;
3010 (void) intel_overlay_switch_off(intel_crtc->overlay);
3011 dev_priv->mm.interruptible = true;
3012 mutex_unlock(&dev->struct_mutex);
3015 /* Let userspace switch the overlay on again. In most cases userspace
3016 * has to recompute where to put it anyway.
3020 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3022 struct drm_device *dev = crtc->dev;
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3025 int pipe = intel_crtc->pipe;
3026 int plane = intel_crtc->plane;
3028 if (intel_crtc->active)
3031 intel_crtc->active = true;
3032 intel_update_watermarks(dev);
3034 intel_enable_pll(dev_priv, pipe);
3035 intel_enable_pipe(dev_priv, pipe, false);
3036 intel_enable_plane(dev_priv, plane, pipe);
3038 intel_crtc_load_lut(crtc);
3039 intel_update_fbc(dev);
3041 /* Give the overlay scaler a chance to enable if it's on this pipe */
3042 intel_crtc_dpms_overlay(intel_crtc, true);
3043 intel_crtc_update_cursor(crtc, true);
3046 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3048 struct drm_device *dev = crtc->dev;
3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3051 int pipe = intel_crtc->pipe;
3052 int plane = intel_crtc->plane;
3054 if (!intel_crtc->active)
3057 /* Give the overlay scaler a chance to disable if it's on this pipe */
3058 intel_crtc_wait_for_pending_flips(crtc);
3059 drm_vblank_off(dev, pipe);
3060 intel_crtc_dpms_overlay(intel_crtc, false);
3061 intel_crtc_update_cursor(crtc, false);
3063 if (dev_priv->cfb_plane == plane)
3064 intel_disable_fbc(dev);
3066 intel_disable_plane(dev_priv, plane, pipe);
3067 intel_disable_pipe(dev_priv, pipe);
3068 intel_disable_pll(dev_priv, pipe);
3070 intel_crtc->active = false;
3071 intel_update_fbc(dev);
3072 intel_update_watermarks(dev);
3073 intel_clear_scanline_wait(dev);
3076 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3078 /* XXX: When our outputs are all unaware of DPMS modes other than off
3079 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3082 case DRM_MODE_DPMS_ON:
3083 case DRM_MODE_DPMS_STANDBY:
3084 case DRM_MODE_DPMS_SUSPEND:
3085 i9xx_crtc_enable(crtc);
3087 case DRM_MODE_DPMS_OFF:
3088 i9xx_crtc_disable(crtc);
3094 * Sets the power management mode of the pipe and plane.
3096 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct drm_i915_master_private *master_priv;
3101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102 int pipe = intel_crtc->pipe;
3105 if (intel_crtc->dpms_mode == mode)
3108 intel_crtc->dpms_mode = mode;
3110 dev_priv->display.dpms(crtc, mode);
3112 if (!dev->primary->master)
3115 master_priv = dev->primary->master->driver_priv;
3116 if (!master_priv->sarea_priv)
3119 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3123 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3124 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3127 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3128 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3131 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3136 static void intel_crtc_disable(struct drm_crtc *crtc)
3138 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3139 struct drm_device *dev = crtc->dev;
3141 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3144 mutex_lock(&dev->struct_mutex);
3145 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3146 mutex_unlock(&dev->struct_mutex);
3150 /* Prepare for a mode set.
3152 * Note we could be a lot smarter here. We need to figure out which outputs
3153 * will be enabled, which disabled (in short, how the config will changes)
3154 * and perform the minimum necessary steps to accomplish that, e.g. updating
3155 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3156 * panel fitting is in the proper state, etc.
3158 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3160 i9xx_crtc_disable(crtc);
3163 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3165 i9xx_crtc_enable(crtc);
3168 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3170 ironlake_crtc_disable(crtc);
3173 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3175 ironlake_crtc_enable(crtc);
3178 void intel_encoder_prepare (struct drm_encoder *encoder)
3180 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3181 /* lvds has its own version of prepare see intel_lvds_prepare */
3182 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3185 void intel_encoder_commit (struct drm_encoder *encoder)
3187 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3188 /* lvds has its own version of commit see intel_lvds_commit */
3189 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3192 void intel_encoder_destroy(struct drm_encoder *encoder)
3194 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3196 drm_encoder_cleanup(encoder);
3197 kfree(intel_encoder);
3200 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3201 struct drm_display_mode *mode,
3202 struct drm_display_mode *adjusted_mode)
3204 struct drm_device *dev = crtc->dev;
3206 if (HAS_PCH_SPLIT(dev)) {
3207 /* FDI link clock is fixed at 2.7G */
3208 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3212 /* XXX some encoders set the crtcinfo, others don't.
3213 * Obviously we need some form of conflict resolution here...
3215 if (adjusted_mode->crtc_htotal == 0)
3216 drm_mode_set_crtcinfo(adjusted_mode, 0);
3221 static int i945_get_display_clock_speed(struct drm_device *dev)
3226 static int i915_get_display_clock_speed(struct drm_device *dev)
3231 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3236 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3240 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3242 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3245 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3246 case GC_DISPLAY_CLOCK_333_MHZ:
3249 case GC_DISPLAY_CLOCK_190_200_MHZ:
3255 static int i865_get_display_clock_speed(struct drm_device *dev)
3260 static int i855_get_display_clock_speed(struct drm_device *dev)
3263 /* Assume that the hardware is in the high speed state. This
3264 * should be the default.
3266 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3267 case GC_CLOCK_133_200:
3268 case GC_CLOCK_100_200:
3270 case GC_CLOCK_166_250:
3272 case GC_CLOCK_100_133:
3276 /* Shouldn't happen */
3280 static int i830_get_display_clock_speed(struct drm_device *dev)
3294 fdi_reduce_ratio(u32 *num, u32 *den)
3296 while (*num > 0xffffff || *den > 0xffffff) {
3303 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3304 int link_clock, struct fdi_m_n *m_n)
3306 m_n->tu = 64; /* default size */
3308 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3309 m_n->gmch_m = bits_per_pixel * pixel_clock;
3310 m_n->gmch_n = link_clock * nlanes * 8;
3311 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3313 m_n->link_m = pixel_clock;
3314 m_n->link_n = link_clock;
3315 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3319 struct intel_watermark_params {
3320 unsigned long fifo_size;
3321 unsigned long max_wm;
3322 unsigned long default_wm;
3323 unsigned long guard_size;
3324 unsigned long cacheline_size;
3327 /* Pineview has different values for various configs */
3328 static const struct intel_watermark_params pineview_display_wm = {
3329 PINEVIEW_DISPLAY_FIFO,
3333 PINEVIEW_FIFO_LINE_SIZE
3335 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3336 PINEVIEW_DISPLAY_FIFO,
3338 PINEVIEW_DFT_HPLLOFF_WM,
3340 PINEVIEW_FIFO_LINE_SIZE
3342 static const struct intel_watermark_params pineview_cursor_wm = {
3343 PINEVIEW_CURSOR_FIFO,
3344 PINEVIEW_CURSOR_MAX_WM,
3345 PINEVIEW_CURSOR_DFT_WM,
3346 PINEVIEW_CURSOR_GUARD_WM,
3347 PINEVIEW_FIFO_LINE_SIZE,
3349 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3350 PINEVIEW_CURSOR_FIFO,
3351 PINEVIEW_CURSOR_MAX_WM,
3352 PINEVIEW_CURSOR_DFT_WM,
3353 PINEVIEW_CURSOR_GUARD_WM,
3354 PINEVIEW_FIFO_LINE_SIZE
3356 static const struct intel_watermark_params g4x_wm_info = {
3363 static const struct intel_watermark_params g4x_cursor_wm_info = {
3370 static const struct intel_watermark_params i965_cursor_wm_info = {
3375 I915_FIFO_LINE_SIZE,
3377 static const struct intel_watermark_params i945_wm_info = {
3384 static const struct intel_watermark_params i915_wm_info = {
3391 static const struct intel_watermark_params i855_wm_info = {
3398 static const struct intel_watermark_params i830_wm_info = {
3406 static const struct intel_watermark_params ironlake_display_wm_info = {
3413 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3420 static const struct intel_watermark_params ironlake_display_srwm_info = {
3421 ILK_DISPLAY_SR_FIFO,
3422 ILK_DISPLAY_MAX_SRWM,
3423 ILK_DISPLAY_DFT_SRWM,
3427 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3429 ILK_CURSOR_MAX_SRWM,
3430 ILK_CURSOR_DFT_SRWM,
3435 static const struct intel_watermark_params sandybridge_display_wm_info = {
3442 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3449 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3450 SNB_DISPLAY_SR_FIFO,
3451 SNB_DISPLAY_MAX_SRWM,
3452 SNB_DISPLAY_DFT_SRWM,
3456 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3458 SNB_CURSOR_MAX_SRWM,
3459 SNB_CURSOR_DFT_SRWM,
3466 * intel_calculate_wm - calculate watermark level
3467 * @clock_in_khz: pixel clock
3468 * @wm: chip FIFO params
3469 * @pixel_size: display pixel size
3470 * @latency_ns: memory latency for the platform
3472 * Calculate the watermark level (the level at which the display plane will
3473 * start fetching from memory again). Each chip has a different display
3474 * FIFO size and allocation, so the caller needs to figure that out and pass
3475 * in the correct intel_watermark_params structure.
3477 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3478 * on the pixel size. When it reaches the watermark level, it'll start
3479 * fetching FIFO line sized based chunks from memory until the FIFO fills
3480 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3481 * will occur, and a display engine hang could result.
3483 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3484 const struct intel_watermark_params *wm,
3487 unsigned long latency_ns)
3489 long entries_required, wm_size;
3492 * Note: we need to make sure we don't overflow for various clock &
3494 * clocks go from a few thousand to several hundred thousand.
3495 * latency is usually a few thousand
3497 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3499 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3501 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3503 wm_size = fifo_size - (entries_required + wm->guard_size);
3505 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3507 /* Don't promote wm_size to unsigned... */
3508 if (wm_size > (long)wm->max_wm)
3509 wm_size = wm->max_wm;
3511 wm_size = wm->default_wm;
3515 struct cxsr_latency {
3518 unsigned long fsb_freq;
3519 unsigned long mem_freq;
3520 unsigned long display_sr;
3521 unsigned long display_hpll_disable;
3522 unsigned long cursor_sr;
3523 unsigned long cursor_hpll_disable;
3526 static const struct cxsr_latency cxsr_latency_table[] = {
3527 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3528 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3529 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3530 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3531 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3533 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3534 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3535 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3536 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3537 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3539 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3540 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3541 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3542 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3543 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3545 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3546 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3547 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3548 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3549 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3551 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3552 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3553 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3554 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3555 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3557 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3558 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3559 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3560 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3561 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3564 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3569 const struct cxsr_latency *latency;
3572 if (fsb == 0 || mem == 0)
3575 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3576 latency = &cxsr_latency_table[i];
3577 if (is_desktop == latency->is_desktop &&
3578 is_ddr3 == latency->is_ddr3 &&
3579 fsb == latency->fsb_freq && mem == latency->mem_freq)
3583 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3588 static void pineview_disable_cxsr(struct drm_device *dev)
3590 struct drm_i915_private *dev_priv = dev->dev_private;
3592 /* deactivate cxsr */
3593 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3597 * Latency for FIFO fetches is dependent on several factors:
3598 * - memory configuration (speed, channels)
3600 * - current MCH state
3601 * It can be fairly high in some situations, so here we assume a fairly
3602 * pessimal value. It's a tradeoff between extra memory fetches (if we
3603 * set this value too high, the FIFO will fetch frequently to stay full)
3604 * and power consumption (set it too low to save power and we might see
3605 * FIFO underruns and display "flicker").
3607 * A value of 5us seems to be a good balance; safe for very low end
3608 * platforms but not overly aggressive on lower latency configs.
3610 static const int latency_ns = 5000;
3612 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 uint32_t dsparb = I915_READ(DSPARB);
3618 size = dsparb & 0x7f;
3620 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3622 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3623 plane ? "B" : "A", size);
3628 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3630 struct drm_i915_private *dev_priv = dev->dev_private;
3631 uint32_t dsparb = I915_READ(DSPARB);
3634 size = dsparb & 0x1ff;
3636 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3637 size >>= 1; /* Convert to cachelines */
3639 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3640 plane ? "B" : "A", size);
3645 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3647 struct drm_i915_private *dev_priv = dev->dev_private;
3648 uint32_t dsparb = I915_READ(DSPARB);
3651 size = dsparb & 0x7f;
3652 size >>= 2; /* Convert to cachelines */
3654 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3661 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664 uint32_t dsparb = I915_READ(DSPARB);
3667 size = dsparb & 0x7f;
3668 size >>= 1; /* Convert to cachelines */
3670 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3671 plane ? "B" : "A", size);
3676 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3678 struct drm_crtc *crtc, *enabled = NULL;
3680 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3681 if (crtc->enabled && crtc->fb) {
3691 static void pineview_update_wm(struct drm_device *dev)
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct drm_crtc *crtc;
3695 const struct cxsr_latency *latency;
3699 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3700 dev_priv->fsb_freq, dev_priv->mem_freq);
3702 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3703 pineview_disable_cxsr(dev);
3707 crtc = single_enabled_crtc(dev);
3709 int clock = crtc->mode.clock;
3710 int pixel_size = crtc->fb->bits_per_pixel / 8;
3713 wm = intel_calculate_wm(clock, &pineview_display_wm,
3714 pineview_display_wm.fifo_size,
3715 pixel_size, latency->display_sr);
3716 reg = I915_READ(DSPFW1);
3717 reg &= ~DSPFW_SR_MASK;
3718 reg |= wm << DSPFW_SR_SHIFT;
3719 I915_WRITE(DSPFW1, reg);
3720 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3723 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3724 pineview_display_wm.fifo_size,
3725 pixel_size, latency->cursor_sr);
3726 reg = I915_READ(DSPFW3);
3727 reg &= ~DSPFW_CURSOR_SR_MASK;
3728 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3729 I915_WRITE(DSPFW3, reg);
3731 /* Display HPLL off SR */
3732 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3733 pineview_display_hplloff_wm.fifo_size,
3734 pixel_size, latency->display_hpll_disable);
3735 reg = I915_READ(DSPFW3);
3736 reg &= ~DSPFW_HPLL_SR_MASK;
3737 reg |= wm & DSPFW_HPLL_SR_MASK;
3738 I915_WRITE(DSPFW3, reg);
3740 /* cursor HPLL off SR */
3741 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3742 pineview_display_hplloff_wm.fifo_size,
3743 pixel_size, latency->cursor_hpll_disable);
3744 reg = I915_READ(DSPFW3);
3745 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3746 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3747 I915_WRITE(DSPFW3, reg);
3748 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3752 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3753 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3755 pineview_disable_cxsr(dev);
3756 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3760 static bool g4x_compute_wm0(struct drm_device *dev,
3762 const struct intel_watermark_params *display,
3763 int display_latency_ns,
3764 const struct intel_watermark_params *cursor,
3765 int cursor_latency_ns,
3769 struct drm_crtc *crtc;
3770 int htotal, hdisplay, clock, pixel_size;
3771 int line_time_us, line_count;
3772 int entries, tlb_miss;
3774 crtc = intel_get_crtc_for_plane(dev, plane);
3775 if (crtc->fb == NULL || !crtc->enabled) {
3776 *cursor_wm = cursor->guard_size;
3777 *plane_wm = display->guard_size;
3781 htotal = crtc->mode.htotal;
3782 hdisplay = crtc->mode.hdisplay;
3783 clock = crtc->mode.clock;
3784 pixel_size = crtc->fb->bits_per_pixel / 8;
3786 /* Use the small buffer method to calculate plane watermark */
3787 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3788 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3790 entries += tlb_miss;
3791 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3792 *plane_wm = entries + display->guard_size;
3793 if (*plane_wm > (int)display->max_wm)
3794 *plane_wm = display->max_wm;
3796 /* Use the large buffer method to calculate cursor watermark */
3797 line_time_us = ((htotal * 1000) / clock);
3798 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3799 entries = line_count * 64 * pixel_size;
3800 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3802 entries += tlb_miss;
3803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3804 *cursor_wm = entries + cursor->guard_size;
3805 if (*cursor_wm > (int)cursor->max_wm)
3806 *cursor_wm = (int)cursor->max_wm;
3812 * Check the wm result.
3814 * If any calculated watermark values is larger than the maximum value that
3815 * can be programmed into the associated watermark register, that watermark
3818 static bool g4x_check_srwm(struct drm_device *dev,
3819 int display_wm, int cursor_wm,
3820 const struct intel_watermark_params *display,
3821 const struct intel_watermark_params *cursor)
3823 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3824 display_wm, cursor_wm);
3826 if (display_wm > display->max_wm) {
3827 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3828 display_wm, display->max_wm);
3832 if (cursor_wm > cursor->max_wm) {
3833 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3834 cursor_wm, cursor->max_wm);
3838 if (!(display_wm || cursor_wm)) {
3839 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3846 static bool g4x_compute_srwm(struct drm_device *dev,
3849 const struct intel_watermark_params *display,
3850 const struct intel_watermark_params *cursor,
3851 int *display_wm, int *cursor_wm)
3853 struct drm_crtc *crtc;
3854 int hdisplay, htotal, pixel_size, clock;
3855 unsigned long line_time_us;
3856 int line_count, line_size;
3861 *display_wm = *cursor_wm = 0;
3865 crtc = intel_get_crtc_for_plane(dev, plane);
3866 hdisplay = crtc->mode.hdisplay;
3867 htotal = crtc->mode.htotal;
3868 clock = crtc->mode.clock;
3869 pixel_size = crtc->fb->bits_per_pixel / 8;
3871 line_time_us = (htotal * 1000) / clock;
3872 line_count = (latency_ns / line_time_us + 1000) / 1000;
3873 line_size = hdisplay * pixel_size;
3875 /* Use the minimum of the small and large buffer method for primary */
3876 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3877 large = line_count * line_size;
3879 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3880 *display_wm = entries + display->guard_size;
3882 /* calculate the self-refresh watermark for display cursor */
3883 entries = line_count * pixel_size * 64;
3884 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3885 *cursor_wm = entries + cursor->guard_size;
3887 return g4x_check_srwm(dev,
3888 *display_wm, *cursor_wm,
3892 #define single_plane_enabled(mask) is_power_of_2(mask)
3894 static void g4x_update_wm(struct drm_device *dev)
3896 static const int sr_latency_ns = 12000;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3899 int plane_sr, cursor_sr;
3900 unsigned int enabled = 0;
3902 if (g4x_compute_wm0(dev, 0,
3903 &g4x_wm_info, latency_ns,
3904 &g4x_cursor_wm_info, latency_ns,
3905 &planea_wm, &cursora_wm))
3908 if (g4x_compute_wm0(dev, 1,
3909 &g4x_wm_info, latency_ns,
3910 &g4x_cursor_wm_info, latency_ns,
3911 &planeb_wm, &cursorb_wm))
3914 plane_sr = cursor_sr = 0;
3915 if (single_plane_enabled(enabled) &&
3916 g4x_compute_srwm(dev, ffs(enabled) - 1,
3919 &g4x_cursor_wm_info,
3920 &plane_sr, &cursor_sr))
3921 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3923 I915_WRITE(FW_BLC_SELF,
3924 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3926 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3927 planea_wm, cursora_wm,
3928 planeb_wm, cursorb_wm,
3929 plane_sr, cursor_sr);
3932 (plane_sr << DSPFW_SR_SHIFT) |
3933 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3934 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3937 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3938 (cursora_wm << DSPFW_CURSORA_SHIFT));
3939 /* HPLL off in SR has some issues on G4x... disable it */
3941 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3942 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3945 static void i965_update_wm(struct drm_device *dev)
3947 struct drm_i915_private *dev_priv = dev->dev_private;
3948 struct drm_crtc *crtc;
3952 /* Calc sr entries for one plane configs */
3953 crtc = single_enabled_crtc(dev);
3955 /* self-refresh has much higher latency */
3956 static const int sr_latency_ns = 12000;
3957 int clock = crtc->mode.clock;
3958 int htotal = crtc->mode.htotal;
3959 int hdisplay = crtc->mode.hdisplay;
3960 int pixel_size = crtc->fb->bits_per_pixel / 8;
3961 unsigned long line_time_us;
3964 line_time_us = ((htotal * 1000) / clock);
3966 /* Use ns/us then divide to preserve precision */
3967 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3968 pixel_size * hdisplay;
3969 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3970 srwm = I965_FIFO_SIZE - entries;
3974 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3977 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3979 entries = DIV_ROUND_UP(entries,
3980 i965_cursor_wm_info.cacheline_size);
3981 cursor_sr = i965_cursor_wm_info.fifo_size -
3982 (entries + i965_cursor_wm_info.guard_size);
3984 if (cursor_sr > i965_cursor_wm_info.max_wm)
3985 cursor_sr = i965_cursor_wm_info.max_wm;
3987 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3988 "cursor %d\n", srwm, cursor_sr);
3990 if (IS_CRESTLINE(dev))
3991 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3993 /* Turn off self refresh if both pipes are enabled */
3994 if (IS_CRESTLINE(dev))
3995 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3999 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4002 /* 965 has limitations... */
4003 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4004 (8 << 16) | (8 << 8) | (8 << 0));
4005 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4006 /* update cursor SR watermark */
4007 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4010 static void i9xx_update_wm(struct drm_device *dev)
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 const struct intel_watermark_params *wm_info;
4018 int planea_wm, planeb_wm;
4019 struct drm_crtc *crtc, *enabled = NULL;
4022 wm_info = &i945_wm_info;
4023 else if (!IS_GEN2(dev))
4024 wm_info = &i915_wm_info;
4026 wm_info = &i855_wm_info;
4028 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4029 crtc = intel_get_crtc_for_plane(dev, 0);
4030 if (crtc->enabled && crtc->fb) {
4031 planea_wm = intel_calculate_wm(crtc->mode.clock,
4033 crtc->fb->bits_per_pixel / 8,
4037 planea_wm = fifo_size - wm_info->guard_size;
4039 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4040 crtc = intel_get_crtc_for_plane(dev, 1);
4041 if (crtc->enabled && crtc->fb) {
4042 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4044 crtc->fb->bits_per_pixel / 8,
4046 if (enabled == NULL)
4051 planeb_wm = fifo_size - wm_info->guard_size;
4053 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4056 * Overlay gets an aggressive default since video jitter is bad.
4060 /* Play safe and disable self-refresh before adjusting watermarks. */
4061 if (IS_I945G(dev) || IS_I945GM(dev))
4062 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4063 else if (IS_I915GM(dev))
4064 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4066 /* Calc sr entries for one plane configs */
4067 if (HAS_FW_BLC(dev) && enabled) {
4068 /* self-refresh has much higher latency */
4069 static const int sr_latency_ns = 6000;
4070 int clock = enabled->mode.clock;
4071 int htotal = enabled->mode.htotal;
4072 int hdisplay = enabled->mode.hdisplay;
4073 int pixel_size = enabled->fb->bits_per_pixel / 8;
4074 unsigned long line_time_us;
4077 line_time_us = (htotal * 1000) / clock;
4079 /* Use ns/us then divide to preserve precision */
4080 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4081 pixel_size * hdisplay;
4082 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4083 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4084 srwm = wm_info->fifo_size - entries;
4088 if (IS_I945G(dev) || IS_I945GM(dev))
4089 I915_WRITE(FW_BLC_SELF,
4090 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4091 else if (IS_I915GM(dev))
4092 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4095 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4096 planea_wm, planeb_wm, cwm, srwm);
4098 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4099 fwater_hi = (cwm & 0x1f);
4101 /* Set request length to 8 cachelines per fetch */
4102 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4103 fwater_hi = fwater_hi | (1 << 8);
4105 I915_WRITE(FW_BLC, fwater_lo);
4106 I915_WRITE(FW_BLC2, fwater_hi);
4108 if (HAS_FW_BLC(dev)) {
4110 if (IS_I945G(dev) || IS_I945GM(dev))
4111 I915_WRITE(FW_BLC_SELF,
4112 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4113 else if (IS_I915GM(dev))
4114 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4115 DRM_DEBUG_KMS("memory self refresh enabled\n");
4117 DRM_DEBUG_KMS("memory self refresh disabled\n");
4121 static void i830_update_wm(struct drm_device *dev)
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct drm_crtc *crtc;
4128 crtc = single_enabled_crtc(dev);
4132 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4133 dev_priv->display.get_fifo_size(dev, 0),
4134 crtc->fb->bits_per_pixel / 8,
4136 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4137 fwater_lo |= (3<<8) | planea_wm;
4139 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4141 I915_WRITE(FW_BLC, fwater_lo);
4144 #define ILK_LP0_PLANE_LATENCY 700
4145 #define ILK_LP0_CURSOR_LATENCY 1300
4148 * Check the wm result.
4150 * If any calculated watermark values is larger than the maximum value that
4151 * can be programmed into the associated watermark register, that watermark
4154 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4155 int fbc_wm, int display_wm, int cursor_wm,
4156 const struct intel_watermark_params *display,
4157 const struct intel_watermark_params *cursor)
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4161 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4162 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4164 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4165 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4166 fbc_wm, SNB_FBC_MAX_SRWM, level);
4168 /* fbc has it's own way to disable FBC WM */
4169 I915_WRITE(DISP_ARB_CTL,
4170 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4174 if (display_wm > display->max_wm) {
4175 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4176 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4180 if (cursor_wm > cursor->max_wm) {
4181 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4182 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4186 if (!(fbc_wm || display_wm || cursor_wm)) {
4187 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4195 * Compute watermark values of WM[1-3],
4197 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4199 const struct intel_watermark_params *display,
4200 const struct intel_watermark_params *cursor,
4201 int *fbc_wm, int *display_wm, int *cursor_wm)
4203 struct drm_crtc *crtc;
4204 unsigned long line_time_us;
4205 int hdisplay, htotal, pixel_size, clock;
4206 int line_count, line_size;
4211 *fbc_wm = *display_wm = *cursor_wm = 0;
4215 crtc = intel_get_crtc_for_plane(dev, plane);
4216 hdisplay = crtc->mode.hdisplay;
4217 htotal = crtc->mode.htotal;
4218 clock = crtc->mode.clock;
4219 pixel_size = crtc->fb->bits_per_pixel / 8;
4221 line_time_us = (htotal * 1000) / clock;
4222 line_count = (latency_ns / line_time_us + 1000) / 1000;
4223 line_size = hdisplay * pixel_size;
4225 /* Use the minimum of the small and large buffer method for primary */
4226 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4227 large = line_count * line_size;
4229 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4230 *display_wm = entries + display->guard_size;
4234 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4236 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4238 /* calculate the self-refresh watermark for display cursor */
4239 entries = line_count * pixel_size * 64;
4240 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4241 *cursor_wm = entries + cursor->guard_size;
4243 return ironlake_check_srwm(dev, level,
4244 *fbc_wm, *display_wm, *cursor_wm,
4248 static void ironlake_update_wm(struct drm_device *dev)
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 int fbc_wm, plane_wm, cursor_wm;
4252 unsigned int enabled;
4255 if (g4x_compute_wm0(dev, 0,
4256 &ironlake_display_wm_info,
4257 ILK_LP0_PLANE_LATENCY,
4258 &ironlake_cursor_wm_info,
4259 ILK_LP0_CURSOR_LATENCY,
4260 &plane_wm, &cursor_wm)) {
4261 I915_WRITE(WM0_PIPEA_ILK,
4262 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4263 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4264 " plane %d, " "cursor: %d\n",
4265 plane_wm, cursor_wm);
4269 if (g4x_compute_wm0(dev, 1,
4270 &ironlake_display_wm_info,
4271 ILK_LP0_PLANE_LATENCY,
4272 &ironlake_cursor_wm_info,
4273 ILK_LP0_CURSOR_LATENCY,
4274 &plane_wm, &cursor_wm)) {
4275 I915_WRITE(WM0_PIPEB_ILK,
4276 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4277 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4278 " plane %d, cursor: %d\n",
4279 plane_wm, cursor_wm);
4284 * Calculate and update the self-refresh watermark only when one
4285 * display plane is used.
4287 I915_WRITE(WM3_LP_ILK, 0);
4288 I915_WRITE(WM2_LP_ILK, 0);
4289 I915_WRITE(WM1_LP_ILK, 0);
4291 if (!single_plane_enabled(enabled))
4293 enabled = ffs(enabled) - 1;
4296 if (!ironlake_compute_srwm(dev, 1, enabled,
4297 ILK_READ_WM1_LATENCY() * 500,
4298 &ironlake_display_srwm_info,
4299 &ironlake_cursor_srwm_info,
4300 &fbc_wm, &plane_wm, &cursor_wm))
4303 I915_WRITE(WM1_LP_ILK,
4305 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4306 (fbc_wm << WM1_LP_FBC_SHIFT) |
4307 (plane_wm << WM1_LP_SR_SHIFT) |
4311 if (!ironlake_compute_srwm(dev, 2, enabled,
4312 ILK_READ_WM2_LATENCY() * 500,
4313 &ironlake_display_srwm_info,
4314 &ironlake_cursor_srwm_info,
4315 &fbc_wm, &plane_wm, &cursor_wm))
4318 I915_WRITE(WM2_LP_ILK,
4320 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4321 (fbc_wm << WM1_LP_FBC_SHIFT) |
4322 (plane_wm << WM1_LP_SR_SHIFT) |
4326 * WM3 is unsupported on ILK, probably because we don't have latency
4327 * data for that power state
4331 static void sandybridge_update_wm(struct drm_device *dev)
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4335 int fbc_wm, plane_wm, cursor_wm;
4336 unsigned int enabled;
4339 if (g4x_compute_wm0(dev, 0,
4340 &sandybridge_display_wm_info, latency,
4341 &sandybridge_cursor_wm_info, latency,
4342 &plane_wm, &cursor_wm)) {
4343 I915_WRITE(WM0_PIPEA_ILK,
4344 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4345 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4346 " plane %d, " "cursor: %d\n",
4347 plane_wm, cursor_wm);
4351 if (g4x_compute_wm0(dev, 1,
4352 &sandybridge_display_wm_info, latency,
4353 &sandybridge_cursor_wm_info, latency,
4354 &plane_wm, &cursor_wm)) {
4355 I915_WRITE(WM0_PIPEB_ILK,
4356 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4357 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4358 " plane %d, cursor: %d\n",
4359 plane_wm, cursor_wm);
4364 * Calculate and update the self-refresh watermark only when one
4365 * display plane is used.
4367 * SNB support 3 levels of watermark.
4369 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4370 * and disabled in the descending order
4373 I915_WRITE(WM3_LP_ILK, 0);
4374 I915_WRITE(WM2_LP_ILK, 0);
4375 I915_WRITE(WM1_LP_ILK, 0);
4377 if (!single_plane_enabled(enabled))
4379 enabled = ffs(enabled) - 1;
4382 if (!ironlake_compute_srwm(dev, 1, enabled,
4383 SNB_READ_WM1_LATENCY() * 500,
4384 &sandybridge_display_srwm_info,
4385 &sandybridge_cursor_srwm_info,
4386 &fbc_wm, &plane_wm, &cursor_wm))
4389 I915_WRITE(WM1_LP_ILK,
4391 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4392 (fbc_wm << WM1_LP_FBC_SHIFT) |
4393 (plane_wm << WM1_LP_SR_SHIFT) |
4397 if (!ironlake_compute_srwm(dev, 2, enabled,
4398 SNB_READ_WM2_LATENCY() * 500,
4399 &sandybridge_display_srwm_info,
4400 &sandybridge_cursor_srwm_info,
4401 &fbc_wm, &plane_wm, &cursor_wm))
4404 I915_WRITE(WM2_LP_ILK,
4406 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4407 (fbc_wm << WM1_LP_FBC_SHIFT) |
4408 (plane_wm << WM1_LP_SR_SHIFT) |
4412 if (!ironlake_compute_srwm(dev, 3, enabled,
4413 SNB_READ_WM3_LATENCY() * 500,
4414 &sandybridge_display_srwm_info,
4415 &sandybridge_cursor_srwm_info,
4416 &fbc_wm, &plane_wm, &cursor_wm))
4419 I915_WRITE(WM3_LP_ILK,
4421 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4422 (fbc_wm << WM1_LP_FBC_SHIFT) |
4423 (plane_wm << WM1_LP_SR_SHIFT) |
4428 * intel_update_watermarks - update FIFO watermark values based on current modes
4430 * Calculate watermark values for the various WM regs based on current mode
4431 * and plane configuration.
4433 * There are several cases to deal with here:
4434 * - normal (i.e. non-self-refresh)
4435 * - self-refresh (SR) mode
4436 * - lines are large relative to FIFO size (buffer can hold up to 2)
4437 * - lines are small relative to FIFO size (buffer can hold more than 2
4438 * lines), so need to account for TLB latency
4440 * The normal calculation is:
4441 * watermark = dotclock * bytes per pixel * latency
4442 * where latency is platform & configuration dependent (we assume pessimal
4445 * The SR calculation is:
4446 * watermark = (trunc(latency/line time)+1) * surface width *
4449 * line time = htotal / dotclock
4450 * surface width = hdisplay for normal plane and 64 for cursor
4451 * and latency is assumed to be high, as above.
4453 * The final value programmed to the register should always be rounded up,
4454 * and include an extra 2 entries to account for clock crossings.
4456 * We don't use the sprite, so we can ignore that. And on Crestline we have
4457 * to set the non-SR watermarks to 8.
4459 static void intel_update_watermarks(struct drm_device *dev)
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4463 if (dev_priv->display.update_wm)
4464 dev_priv->display.update_wm(dev);
4467 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4469 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4470 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4474 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4475 * @crtc: CRTC structure
4477 * A pipe may be connected to one or more outputs. Based on the depth of the
4478 * attached framebuffer, choose a good color depth to use on the pipe.
4480 * If possible, match the pipe depth to the fb depth. In some cases, this
4481 * isn't ideal, because the connected output supports a lesser or restricted
4482 * set of depths. Resolve that here:
4483 * LVDS typically supports only 6bpc, so clamp down in that case
4484 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4485 * Displays may support a restricted set as well, check EDID and clamp as
4489 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4490 * true if they don't match).
4492 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4493 unsigned int *pipe_bpp)
4495 struct drm_device *dev = crtc->dev;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 struct drm_encoder *encoder;
4498 struct drm_connector *connector;
4499 unsigned int display_bpc = UINT_MAX, bpc;
4501 /* Walk the encoders & connectors on this crtc, get min bpc */
4502 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4503 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4505 if (encoder->crtc != crtc)
4508 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4509 unsigned int lvds_bpc;
4511 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4517 if (lvds_bpc < display_bpc) {
4518 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4519 display_bpc = lvds_bpc;
4524 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4525 /* Use VBT settings if we have an eDP panel */
4526 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4528 if (edp_bpc < display_bpc) {
4529 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4530 display_bpc = edp_bpc;
4535 /* Not one of the known troublemakers, check the EDID */
4536 list_for_each_entry(connector, &dev->mode_config.connector_list,
4538 if (connector->encoder != encoder)
4541 if (connector->display_info.bpc < display_bpc) {
4542 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4543 display_bpc = connector->display_info.bpc;
4548 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4549 * through, clamp it down. (Note: >12bpc will be caught below.)
4551 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4552 if (display_bpc > 8 && display_bpc < 12) {
4553 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4556 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4563 * We could just drive the pipe at the highest bpc all the time and
4564 * enable dithering as needed, but that costs bandwidth. So choose
4565 * the minimum value that expresses the full color range of the fb but
4566 * also stays within the max display bpc discovered above.
4569 switch (crtc->fb->depth) {
4571 bpc = 8; /* since we go through a colormap */
4575 bpc = 6; /* min is 18bpp */
4578 bpc = min((unsigned int)8, display_bpc);
4581 bpc = min((unsigned int)10, display_bpc);
4584 bpc = min((unsigned int)12, display_bpc);
4587 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4588 bpc = min((unsigned int)8, display_bpc);
4592 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4595 *pipe_bpp = bpc * 3;
4597 return display_bpc != bpc;
4600 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4601 struct drm_display_mode *mode,
4602 struct drm_display_mode *adjusted_mode,
4604 struct drm_framebuffer *old_fb)
4606 struct drm_device *dev = crtc->dev;
4607 struct drm_i915_private *dev_priv = dev->dev_private;
4608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4609 int pipe = intel_crtc->pipe;
4610 int plane = intel_crtc->plane;
4611 int refclk, num_connectors = 0;
4612 intel_clock_t clock, reduced_clock;
4613 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4614 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4615 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4616 struct drm_mode_config *mode_config = &dev->mode_config;
4617 struct intel_encoder *encoder;
4618 const intel_limit_t *limit;
4623 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4624 if (encoder->base.crtc != crtc)
4627 switch (encoder->type) {
4628 case INTEL_OUTPUT_LVDS:
4631 case INTEL_OUTPUT_SDVO:
4632 case INTEL_OUTPUT_HDMI:
4634 if (encoder->needs_tv_clock)
4637 case INTEL_OUTPUT_DVO:
4640 case INTEL_OUTPUT_TVOUT:
4643 case INTEL_OUTPUT_ANALOG:
4646 case INTEL_OUTPUT_DISPLAYPORT:
4654 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4655 refclk = dev_priv->lvds_ssc_freq * 1000;
4656 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4658 } else if (!IS_GEN2(dev)) {
4665 * Returns a set of divisors for the desired target clock with the given
4666 * refclk, or FALSE. The returned values represent the clock equation:
4667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4669 limit = intel_limit(crtc, refclk);
4670 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4672 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4676 /* Ensure that the cursor is valid for the new mode before changing... */
4677 intel_crtc_update_cursor(crtc, true);
4679 if (is_lvds && dev_priv->lvds_downclock_avail) {
4680 has_reduced_clock = limit->find_pll(limit, crtc,
4681 dev_priv->lvds_downclock,
4684 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4686 * If the different P is found, it means that we can't
4687 * switch the display clock by using the FP0/FP1.
4688 * In such case we will disable the LVDS downclock
4691 DRM_DEBUG_KMS("Different P is found for "
4692 "LVDS clock/downclock\n");
4693 has_reduced_clock = 0;
4696 /* SDVO TV has fixed PLL values depend on its clock range,
4697 this mirrors vbios setting. */
4698 if (is_sdvo && is_tv) {
4699 if (adjusted_mode->clock >= 100000
4700 && adjusted_mode->clock < 140500) {
4706 } else if (adjusted_mode->clock >= 140500
4707 && adjusted_mode->clock <= 200000) {
4716 if (IS_PINEVIEW(dev)) {
4717 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4718 if (has_reduced_clock)
4719 fp2 = (1 << reduced_clock.n) << 16 |
4720 reduced_clock.m1 << 8 | reduced_clock.m2;
4722 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4723 if (has_reduced_clock)
4724 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4728 dpll = DPLL_VGA_MODE_DIS;
4730 if (!IS_GEN2(dev)) {
4732 dpll |= DPLLB_MODE_LVDS;
4734 dpll |= DPLLB_MODE_DAC_SERIAL;
4736 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4737 if (pixel_multiplier > 1) {
4738 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4739 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4741 dpll |= DPLL_DVO_HIGH_SPEED;
4744 dpll |= DPLL_DVO_HIGH_SPEED;
4746 /* compute bitmask from p1 value */
4747 if (IS_PINEVIEW(dev))
4748 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4750 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4751 if (IS_G4X(dev) && has_reduced_clock)
4752 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4756 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4759 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4762 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4765 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4768 if (INTEL_INFO(dev)->gen >= 4)
4769 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4772 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4775 dpll |= PLL_P1_DIVIDE_BY_TWO;
4777 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4779 dpll |= PLL_P2_DIVIDE_BY_4;
4783 if (is_sdvo && is_tv)
4784 dpll |= PLL_REF_INPUT_TVCLKINBC;
4786 /* XXX: just matching BIOS for now */
4787 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4789 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4790 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4792 dpll |= PLL_REF_INPUT_DREFCLK;
4794 /* setup pipeconf */
4795 pipeconf = I915_READ(PIPECONF(pipe));
4797 /* Set up the display plane register */
4798 dspcntr = DISPPLANE_GAMMA_ENABLE;
4800 /* Ironlake's plane is forced to pipe, bit 24 is to
4801 enable color space conversion */
4803 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4805 dspcntr |= DISPPLANE_SEL_PIPE_B;
4807 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4808 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4811 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4815 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4816 pipeconf |= PIPECONF_DOUBLE_WIDE;
4818 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4821 dpll |= DPLL_VCO_ENABLE;
4823 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4824 drm_mode_debug_printmodeline(mode);
4826 I915_WRITE(FP0(pipe), fp);
4827 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4829 POSTING_READ(DPLL(pipe));
4832 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4833 * This is an exception to the general rule that mode_set doesn't turn
4837 temp = I915_READ(LVDS);
4838 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4840 temp |= LVDS_PIPEB_SELECT;
4842 temp &= ~LVDS_PIPEB_SELECT;
4844 /* set the corresponsding LVDS_BORDER bit */
4845 temp |= dev_priv->lvds_border_bits;
4846 /* Set the B0-B3 data pairs corresponding to whether we're going to
4847 * set the DPLLs for dual-channel mode or not.
4850 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4852 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4854 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4855 * appropriately here, but we need to look more thoroughly into how
4856 * panels behave in the two modes.
4858 /* set the dithering flag on LVDS as needed */
4859 if (INTEL_INFO(dev)->gen >= 4) {
4860 if (dev_priv->lvds_dither)
4861 temp |= LVDS_ENABLE_DITHER;
4863 temp &= ~LVDS_ENABLE_DITHER;
4865 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4866 lvds_sync |= LVDS_HSYNC_POLARITY;
4867 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4868 lvds_sync |= LVDS_VSYNC_POLARITY;
4869 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4871 char flags[2] = "-+";
4872 DRM_INFO("Changing LVDS panel from "
4873 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4874 flags[!(temp & LVDS_HSYNC_POLARITY)],
4875 flags[!(temp & LVDS_VSYNC_POLARITY)],
4876 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4877 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4878 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4881 I915_WRITE(LVDS, temp);
4885 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4888 I915_WRITE(DPLL(pipe), dpll);
4890 /* Wait for the clocks to stabilize. */
4891 POSTING_READ(DPLL(pipe));
4894 if (INTEL_INFO(dev)->gen >= 4) {
4897 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4899 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4903 I915_WRITE(DPLL_MD(pipe), temp);
4905 /* The pixel multiplier can only be updated once the
4906 * DPLL is enabled and the clocks are stable.
4908 * So write it again.
4910 I915_WRITE(DPLL(pipe), dpll);
4913 intel_crtc->lowfreq_avail = false;
4914 if (is_lvds && has_reduced_clock && i915_powersave) {
4915 I915_WRITE(FP1(pipe), fp2);
4916 intel_crtc->lowfreq_avail = true;
4917 if (HAS_PIPE_CXSR(dev)) {
4918 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4919 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4922 I915_WRITE(FP1(pipe), fp);
4923 if (HAS_PIPE_CXSR(dev)) {
4924 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4925 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4929 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4930 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4931 /* the chip adds 2 halflines automatically */
4932 adjusted_mode->crtc_vdisplay -= 1;
4933 adjusted_mode->crtc_vtotal -= 1;
4934 adjusted_mode->crtc_vblank_start -= 1;
4935 adjusted_mode->crtc_vblank_end -= 1;
4936 adjusted_mode->crtc_vsync_end -= 1;
4937 adjusted_mode->crtc_vsync_start -= 1;
4939 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4941 I915_WRITE(HTOTAL(pipe),
4942 (adjusted_mode->crtc_hdisplay - 1) |
4943 ((adjusted_mode->crtc_htotal - 1) << 16));
4944 I915_WRITE(HBLANK(pipe),
4945 (adjusted_mode->crtc_hblank_start - 1) |
4946 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4947 I915_WRITE(HSYNC(pipe),
4948 (adjusted_mode->crtc_hsync_start - 1) |
4949 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4951 I915_WRITE(VTOTAL(pipe),
4952 (adjusted_mode->crtc_vdisplay - 1) |
4953 ((adjusted_mode->crtc_vtotal - 1) << 16));
4954 I915_WRITE(VBLANK(pipe),
4955 (adjusted_mode->crtc_vblank_start - 1) |
4956 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4957 I915_WRITE(VSYNC(pipe),
4958 (adjusted_mode->crtc_vsync_start - 1) |
4959 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4961 /* pipesrc and dspsize control the size that is scaled from,
4962 * which should always be the user's requested size.
4964 I915_WRITE(DSPSIZE(plane),
4965 ((mode->vdisplay - 1) << 16) |
4966 (mode->hdisplay - 1));
4967 I915_WRITE(DSPPOS(plane), 0);
4968 I915_WRITE(PIPESRC(pipe),
4969 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4971 I915_WRITE(PIPECONF(pipe), pipeconf);
4972 POSTING_READ(PIPECONF(pipe));
4973 intel_enable_pipe(dev_priv, pipe, false);
4975 intel_wait_for_vblank(dev, pipe);
4977 I915_WRITE(DSPCNTR(plane), dspcntr);
4978 POSTING_READ(DSPCNTR(plane));
4979 intel_enable_plane(dev_priv, plane, pipe);
4981 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4983 intel_update_watermarks(dev);
4988 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4989 struct drm_display_mode *mode,
4990 struct drm_display_mode *adjusted_mode,
4992 struct drm_framebuffer *old_fb)
4994 struct drm_device *dev = crtc->dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997 int pipe = intel_crtc->pipe;
4998 int plane = intel_crtc->plane;
4999 int refclk, num_connectors = 0;
5000 intel_clock_t clock, reduced_clock;
5001 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5002 bool ok, has_reduced_clock = false, is_sdvo = false;
5003 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5004 struct intel_encoder *has_edp_encoder = NULL;
5005 struct drm_mode_config *mode_config = &dev->mode_config;
5006 struct intel_encoder *encoder;
5007 const intel_limit_t *limit;
5009 struct fdi_m_n m_n = {0};
5012 int target_clock, pixel_multiplier, lane, link_bw, factor;
5013 unsigned int pipe_bpp;
5016 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5017 if (encoder->base.crtc != crtc)
5020 switch (encoder->type) {
5021 case INTEL_OUTPUT_LVDS:
5024 case INTEL_OUTPUT_SDVO:
5025 case INTEL_OUTPUT_HDMI:
5027 if (encoder->needs_tv_clock)
5030 case INTEL_OUTPUT_TVOUT:
5033 case INTEL_OUTPUT_ANALOG:
5036 case INTEL_OUTPUT_DISPLAYPORT:
5039 case INTEL_OUTPUT_EDP:
5040 has_edp_encoder = encoder;
5047 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5048 refclk = dev_priv->lvds_ssc_freq * 1000;
5049 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5053 if (!has_edp_encoder ||
5054 intel_encoder_is_pch_edp(&has_edp_encoder->base))
5055 refclk = 120000; /* 120Mhz refclk */
5059 * Returns a set of divisors for the desired target clock with the given
5060 * refclk, or FALSE. The returned values represent the clock equation:
5061 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5063 limit = intel_limit(crtc, refclk);
5064 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5066 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5070 /* Ensure that the cursor is valid for the new mode before changing... */
5071 intel_crtc_update_cursor(crtc, true);
5073 if (is_lvds && dev_priv->lvds_downclock_avail) {
5074 has_reduced_clock = limit->find_pll(limit, crtc,
5075 dev_priv->lvds_downclock,
5078 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5080 * If the different P is found, it means that we can't
5081 * switch the display clock by using the FP0/FP1.
5082 * In such case we will disable the LVDS downclock
5085 DRM_DEBUG_KMS("Different P is found for "
5086 "LVDS clock/downclock\n");
5087 has_reduced_clock = 0;
5090 /* SDVO TV has fixed PLL values depend on its clock range,
5091 this mirrors vbios setting. */
5092 if (is_sdvo && is_tv) {
5093 if (adjusted_mode->clock >= 100000
5094 && adjusted_mode->clock < 140500) {
5100 } else if (adjusted_mode->clock >= 140500
5101 && adjusted_mode->clock <= 200000) {
5111 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5113 /* CPU eDP doesn't require FDI link, so just set DP M/N
5114 according to current link config */
5115 if (has_edp_encoder &&
5116 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5117 target_clock = mode->clock;
5118 intel_edp_link_config(has_edp_encoder,
5121 /* [e]DP over FDI requires target mode clock
5122 instead of link clock */
5123 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5124 target_clock = mode->clock;
5126 target_clock = adjusted_mode->clock;
5128 /* FDI is a binary signal running at ~2.7GHz, encoding
5129 * each output octet as 10 bits. The actual frequency
5130 * is stored as a divider into a 100MHz clock, and the
5131 * mode pixel clock is stored in units of 1KHz.
5132 * Hence the bw of each lane in terms of the mode signal
5135 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5138 /* determine panel color depth */
5139 temp = I915_READ(PIPECONF(pipe));
5140 temp &= ~PIPE_BPC_MASK;
5141 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5156 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5162 intel_crtc->bpp = pipe_bpp;
5163 I915_WRITE(PIPECONF(pipe), temp);
5167 * Account for spread spectrum to avoid
5168 * oversubscribing the link. Max center spread
5169 * is 2.5%; use 5% for safety's sake.
5171 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5172 lane = bps / (link_bw * 8) + 1;
5175 intel_crtc->fdi_lanes = lane;
5177 if (pixel_multiplier > 1)
5178 link_bw *= pixel_multiplier;
5179 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5182 /* Ironlake: try to setup display ref clock before DPLL
5183 * enabling. This is only under driver's control after
5184 * PCH B stepping, previous chipset stepping should be
5185 * ignoring this setting.
5187 temp = I915_READ(PCH_DREF_CONTROL);
5188 /* Always enable nonspread source */
5189 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5190 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5191 temp &= ~DREF_SSC_SOURCE_MASK;
5192 temp |= DREF_SSC_SOURCE_ENABLE;
5193 I915_WRITE(PCH_DREF_CONTROL, temp);
5195 POSTING_READ(PCH_DREF_CONTROL);
5198 if (has_edp_encoder) {
5199 if (intel_panel_use_ssc(dev_priv)) {
5200 temp |= DREF_SSC1_ENABLE;
5201 I915_WRITE(PCH_DREF_CONTROL, temp);
5203 POSTING_READ(PCH_DREF_CONTROL);
5206 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5208 /* Enable CPU source on CPU attached eDP */
5209 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5210 if (intel_panel_use_ssc(dev_priv))
5211 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5213 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5215 /* Enable SSC on PCH eDP if needed */
5216 if (intel_panel_use_ssc(dev_priv)) {
5217 DRM_ERROR("enabling SSC on PCH\n");
5218 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5221 I915_WRITE(PCH_DREF_CONTROL, temp);
5222 POSTING_READ(PCH_DREF_CONTROL);
5226 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5227 if (has_reduced_clock)
5228 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5231 /* Enable autotuning of the PLL clock (if permissible) */
5234 if ((intel_panel_use_ssc(dev_priv) &&
5235 dev_priv->lvds_ssc_freq == 100) ||
5236 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5238 } else if (is_sdvo && is_tv)
5241 if (clock.m1 < factor * clock.n)
5247 dpll |= DPLLB_MODE_LVDS;
5249 dpll |= DPLLB_MODE_DAC_SERIAL;
5251 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5252 if (pixel_multiplier > 1) {
5253 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5255 dpll |= DPLL_DVO_HIGH_SPEED;
5257 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5258 dpll |= DPLL_DVO_HIGH_SPEED;
5260 /* compute bitmask from p1 value */
5261 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5263 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5267 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5270 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5273 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5276 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5280 if (is_sdvo && is_tv)
5281 dpll |= PLL_REF_INPUT_TVCLKINBC;
5283 /* XXX: just matching BIOS for now */
5284 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5286 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5287 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5289 dpll |= PLL_REF_INPUT_DREFCLK;
5291 /* setup pipeconf */
5292 pipeconf = I915_READ(PIPECONF(pipe));
5294 /* Set up the display plane register */
5295 dspcntr = DISPPLANE_GAMMA_ENABLE;
5297 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5298 drm_mode_debug_printmodeline(mode);
5300 /* PCH eDP needs FDI, but CPU eDP does not */
5301 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5302 I915_WRITE(PCH_FP0(pipe), fp);
5303 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5305 POSTING_READ(PCH_DPLL(pipe));
5309 /* enable transcoder DPLL */
5310 if (HAS_PCH_CPT(dev)) {
5311 temp = I915_READ(PCH_DPLL_SEL);
5314 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5317 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5320 /* FIXME: manage transcoder PLLs? */
5321 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5326 I915_WRITE(PCH_DPLL_SEL, temp);
5328 POSTING_READ(PCH_DPLL_SEL);
5332 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5333 * This is an exception to the general rule that mode_set doesn't turn
5337 temp = I915_READ(PCH_LVDS);
5338 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5340 if (HAS_PCH_CPT(dev))
5341 temp |= PORT_TRANS_B_SEL_CPT;
5343 temp |= LVDS_PIPEB_SELECT;
5345 if (HAS_PCH_CPT(dev))
5346 temp &= ~PORT_TRANS_SEL_MASK;
5348 temp &= ~LVDS_PIPEB_SELECT;
5350 /* set the corresponsding LVDS_BORDER bit */
5351 temp |= dev_priv->lvds_border_bits;
5352 /* Set the B0-B3 data pairs corresponding to whether we're going to
5353 * set the DPLLs for dual-channel mode or not.
5356 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5358 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5360 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5361 * appropriately here, but we need to look more thoroughly into how
5362 * panels behave in the two modes.
5364 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5365 lvds_sync |= LVDS_HSYNC_POLARITY;
5366 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5367 lvds_sync |= LVDS_VSYNC_POLARITY;
5368 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5370 char flags[2] = "-+";
5371 DRM_INFO("Changing LVDS panel from "
5372 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5373 flags[!(temp & LVDS_HSYNC_POLARITY)],
5374 flags[!(temp & LVDS_VSYNC_POLARITY)],
5375 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5376 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5377 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5380 I915_WRITE(PCH_LVDS, temp);
5383 pipeconf &= ~PIPECONF_DITHER_EN;
5384 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5385 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5386 pipeconf |= PIPECONF_DITHER_EN;
5387 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5389 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5390 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5392 /* For non-DP output, clear any trans DP clock recovery setting.*/
5393 I915_WRITE(TRANSDATA_M1(pipe), 0);
5394 I915_WRITE(TRANSDATA_N1(pipe), 0);
5395 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5396 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5399 if (!has_edp_encoder ||
5400 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5401 I915_WRITE(PCH_DPLL(pipe), dpll);
5403 /* Wait for the clocks to stabilize. */
5404 POSTING_READ(PCH_DPLL(pipe));
5407 /* The pixel multiplier can only be updated once the
5408 * DPLL is enabled and the clocks are stable.
5410 * So write it again.
5412 I915_WRITE(PCH_DPLL(pipe), dpll);
5415 intel_crtc->lowfreq_avail = false;
5416 if (is_lvds && has_reduced_clock && i915_powersave) {
5417 I915_WRITE(PCH_FP1(pipe), fp2);
5418 intel_crtc->lowfreq_avail = true;
5419 if (HAS_PIPE_CXSR(dev)) {
5420 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5421 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5424 I915_WRITE(PCH_FP1(pipe), fp);
5425 if (HAS_PIPE_CXSR(dev)) {
5426 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5427 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5431 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5432 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5433 /* the chip adds 2 halflines automatically */
5434 adjusted_mode->crtc_vdisplay -= 1;
5435 adjusted_mode->crtc_vtotal -= 1;
5436 adjusted_mode->crtc_vblank_start -= 1;
5437 adjusted_mode->crtc_vblank_end -= 1;
5438 adjusted_mode->crtc_vsync_end -= 1;
5439 adjusted_mode->crtc_vsync_start -= 1;
5441 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5443 I915_WRITE(HTOTAL(pipe),
5444 (adjusted_mode->crtc_hdisplay - 1) |
5445 ((adjusted_mode->crtc_htotal - 1) << 16));
5446 I915_WRITE(HBLANK(pipe),
5447 (adjusted_mode->crtc_hblank_start - 1) |
5448 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5449 I915_WRITE(HSYNC(pipe),
5450 (adjusted_mode->crtc_hsync_start - 1) |
5451 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5453 I915_WRITE(VTOTAL(pipe),
5454 (adjusted_mode->crtc_vdisplay - 1) |
5455 ((adjusted_mode->crtc_vtotal - 1) << 16));
5456 I915_WRITE(VBLANK(pipe),
5457 (adjusted_mode->crtc_vblank_start - 1) |
5458 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5459 I915_WRITE(VSYNC(pipe),
5460 (adjusted_mode->crtc_vsync_start - 1) |
5461 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5463 /* pipesrc controls the size that is scaled from, which should
5464 * always be the user's requested size.
5466 I915_WRITE(PIPESRC(pipe),
5467 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5469 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5470 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5471 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5472 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5474 if (has_edp_encoder &&
5475 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5476 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5479 I915_WRITE(PIPECONF(pipe), pipeconf);
5480 POSTING_READ(PIPECONF(pipe));
5482 intel_wait_for_vblank(dev, pipe);
5485 /* enable address swizzle for tiling buffer */
5486 temp = I915_READ(DISP_ARB_CTL);
5487 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5490 I915_WRITE(DSPCNTR(plane), dspcntr);
5491 POSTING_READ(DSPCNTR(plane));
5493 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5495 intel_update_watermarks(dev);
5500 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5501 struct drm_display_mode *mode,
5502 struct drm_display_mode *adjusted_mode,
5504 struct drm_framebuffer *old_fb)
5506 struct drm_device *dev = crtc->dev;
5507 struct drm_i915_private *dev_priv = dev->dev_private;
5508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5509 int pipe = intel_crtc->pipe;
5512 drm_vblank_pre_modeset(dev, pipe);
5514 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5517 drm_vblank_post_modeset(dev, pipe);
5522 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5523 void intel_crtc_load_lut(struct drm_crtc *crtc)
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5528 int palreg = PALETTE(intel_crtc->pipe);
5531 /* The clocks have to be on to load the palette. */
5535 /* use legacy palette for Ironlake */
5536 if (HAS_PCH_SPLIT(dev))
5537 palreg = LGC_PALETTE(intel_crtc->pipe);
5539 for (i = 0; i < 256; i++) {
5540 I915_WRITE(palreg + 4 * i,
5541 (intel_crtc->lut_r[i] << 16) |
5542 (intel_crtc->lut_g[i] << 8) |
5543 intel_crtc->lut_b[i]);
5547 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5549 struct drm_device *dev = crtc->dev;
5550 struct drm_i915_private *dev_priv = dev->dev_private;
5551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5552 bool visible = base != 0;
5555 if (intel_crtc->cursor_visible == visible)
5558 cntl = I915_READ(_CURACNTR);
5560 /* On these chipsets we can only modify the base whilst
5561 * the cursor is disabled.
5563 I915_WRITE(_CURABASE, base);
5565 cntl &= ~(CURSOR_FORMAT_MASK);
5566 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5567 cntl |= CURSOR_ENABLE |
5568 CURSOR_GAMMA_ENABLE |
5571 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5572 I915_WRITE(_CURACNTR, cntl);
5574 intel_crtc->cursor_visible = visible;
5577 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5579 struct drm_device *dev = crtc->dev;
5580 struct drm_i915_private *dev_priv = dev->dev_private;
5581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5582 int pipe = intel_crtc->pipe;
5583 bool visible = base != 0;
5585 if (intel_crtc->cursor_visible != visible) {
5586 uint32_t cntl = I915_READ(CURCNTR(pipe));
5588 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5589 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5590 cntl |= pipe << 28; /* Connect to correct pipe */
5592 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5593 cntl |= CURSOR_MODE_DISABLE;
5595 I915_WRITE(CURCNTR(pipe), cntl);
5597 intel_crtc->cursor_visible = visible;
5599 /* and commit changes on next vblank */
5600 I915_WRITE(CURBASE(pipe), base);
5603 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5604 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5607 struct drm_device *dev = crtc->dev;
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5610 int pipe = intel_crtc->pipe;
5611 int x = intel_crtc->cursor_x;
5612 int y = intel_crtc->cursor_y;
5618 if (on && crtc->enabled && crtc->fb) {
5619 base = intel_crtc->cursor_addr;
5620 if (x > (int) crtc->fb->width)
5623 if (y > (int) crtc->fb->height)
5629 if (x + intel_crtc->cursor_width < 0)
5632 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5635 pos |= x << CURSOR_X_SHIFT;
5638 if (y + intel_crtc->cursor_height < 0)
5641 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5644 pos |= y << CURSOR_Y_SHIFT;
5646 visible = base != 0;
5647 if (!visible && !intel_crtc->cursor_visible)
5650 I915_WRITE(CURPOS(pipe), pos);
5651 if (IS_845G(dev) || IS_I865G(dev))
5652 i845_update_cursor(crtc, base);
5654 i9xx_update_cursor(crtc, base);
5657 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5660 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5661 struct drm_file *file,
5663 uint32_t width, uint32_t height)
5665 struct drm_device *dev = crtc->dev;
5666 struct drm_i915_private *dev_priv = dev->dev_private;
5667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5668 struct drm_i915_gem_object *obj;
5672 DRM_DEBUG_KMS("\n");
5674 /* if we want to turn off the cursor ignore width and height */
5676 DRM_DEBUG_KMS("cursor off\n");
5679 mutex_lock(&dev->struct_mutex);
5683 /* Currently we only support 64x64 cursors */
5684 if (width != 64 || height != 64) {
5685 DRM_ERROR("we currently only support 64x64 cursors\n");
5689 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5690 if (&obj->base == NULL)
5693 if (obj->base.size < width * height * 4) {
5694 DRM_ERROR("buffer is to small\n");
5699 /* we only need to pin inside GTT if cursor is non-phy */
5700 mutex_lock(&dev->struct_mutex);
5701 if (!dev_priv->info->cursor_needs_physical) {
5702 if (obj->tiling_mode) {
5703 DRM_ERROR("cursor cannot be tiled\n");
5708 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5710 DRM_ERROR("failed to move cursor bo into the GTT\n");
5714 ret = i915_gem_object_put_fence(obj);
5716 DRM_ERROR("failed to release fence for cursor");
5720 addr = obj->gtt_offset;
5722 int align = IS_I830(dev) ? 16 * 1024 : 256;
5723 ret = i915_gem_attach_phys_object(dev, obj,
5724 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5727 DRM_ERROR("failed to attach phys object\n");
5730 addr = obj->phys_obj->handle->busaddr;
5734 I915_WRITE(CURSIZE, (height << 12) | width);
5737 if (intel_crtc->cursor_bo) {
5738 if (dev_priv->info->cursor_needs_physical) {
5739 if (intel_crtc->cursor_bo != obj)
5740 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5742 i915_gem_object_unpin(intel_crtc->cursor_bo);
5743 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5746 mutex_unlock(&dev->struct_mutex);
5748 intel_crtc->cursor_addr = addr;
5749 intel_crtc->cursor_bo = obj;
5750 intel_crtc->cursor_width = width;
5751 intel_crtc->cursor_height = height;
5753 intel_crtc_update_cursor(crtc, true);
5757 i915_gem_object_unpin(obj);
5759 mutex_unlock(&dev->struct_mutex);
5761 drm_gem_object_unreference_unlocked(&obj->base);
5765 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5769 intel_crtc->cursor_x = x;
5770 intel_crtc->cursor_y = y;
5772 intel_crtc_update_cursor(crtc, true);
5777 /** Sets the color ramps on behalf of RandR */
5778 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5779 u16 blue, int regno)
5781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5783 intel_crtc->lut_r[regno] = red >> 8;
5784 intel_crtc->lut_g[regno] = green >> 8;
5785 intel_crtc->lut_b[regno] = blue >> 8;
5788 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5789 u16 *blue, int regno)
5791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5793 *red = intel_crtc->lut_r[regno] << 8;
5794 *green = intel_crtc->lut_g[regno] << 8;
5795 *blue = intel_crtc->lut_b[regno] << 8;
5798 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5799 u16 *blue, uint32_t start, uint32_t size)
5801 int end = (start + size > 256) ? 256 : start + size, i;
5802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804 for (i = start; i < end; i++) {
5805 intel_crtc->lut_r[i] = red[i] >> 8;
5806 intel_crtc->lut_g[i] = green[i] >> 8;
5807 intel_crtc->lut_b[i] = blue[i] >> 8;
5810 intel_crtc_load_lut(crtc);
5814 * Get a pipe with a simple mode set on it for doing load-based monitor
5817 * It will be up to the load-detect code to adjust the pipe as appropriate for
5818 * its requirements. The pipe will be connected to no other encoders.
5820 * Currently this code will only succeed if there is a pipe with no encoders
5821 * configured for it. In the future, it could choose to temporarily disable
5822 * some outputs to free up a pipe for its use.
5824 * \return crtc, or NULL if no pipes are available.
5827 /* VESA 640x480x72Hz mode to set on the pipe */
5828 static struct drm_display_mode load_detect_mode = {
5829 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5830 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5833 static struct drm_framebuffer *
5834 intel_framebuffer_create(struct drm_device *dev,
5835 struct drm_mode_fb_cmd *mode_cmd,
5836 struct drm_i915_gem_object *obj)
5838 struct intel_framebuffer *intel_fb;
5841 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5843 drm_gem_object_unreference_unlocked(&obj->base);
5844 return ERR_PTR(-ENOMEM);
5847 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5849 drm_gem_object_unreference_unlocked(&obj->base);
5851 return ERR_PTR(ret);
5854 return &intel_fb->base;
5858 intel_framebuffer_pitch_for_width(int width, int bpp)
5860 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5861 return ALIGN(pitch, 64);
5865 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5867 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5868 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5871 static struct drm_framebuffer *
5872 intel_framebuffer_create_for_mode(struct drm_device *dev,
5873 struct drm_display_mode *mode,
5876 struct drm_i915_gem_object *obj;
5877 struct drm_mode_fb_cmd mode_cmd;
5879 obj = i915_gem_alloc_object(dev,
5880 intel_framebuffer_size_for_mode(mode, bpp));
5882 return ERR_PTR(-ENOMEM);
5884 mode_cmd.width = mode->hdisplay;
5885 mode_cmd.height = mode->vdisplay;
5886 mode_cmd.depth = depth;
5888 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5890 return intel_framebuffer_create(dev, &mode_cmd, obj);
5893 static struct drm_framebuffer *
5894 mode_fits_in_fbdev(struct drm_device *dev,
5895 struct drm_display_mode *mode)
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 struct drm_i915_gem_object *obj;
5899 struct drm_framebuffer *fb;
5901 if (dev_priv->fbdev == NULL)
5904 obj = dev_priv->fbdev->ifb.obj;
5908 fb = &dev_priv->fbdev->ifb.base;
5909 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5910 fb->bits_per_pixel))
5913 if (obj->base.size < mode->vdisplay * fb->pitch)
5919 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5920 struct drm_connector *connector,
5921 struct drm_display_mode *mode,
5922 struct intel_load_detect_pipe *old)
5924 struct intel_crtc *intel_crtc;
5925 struct drm_crtc *possible_crtc;
5926 struct drm_encoder *encoder = &intel_encoder->base;
5927 struct drm_crtc *crtc = NULL;
5928 struct drm_device *dev = encoder->dev;
5929 struct drm_framebuffer *old_fb;
5932 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5933 connector->base.id, drm_get_connector_name(connector),
5934 encoder->base.id, drm_get_encoder_name(encoder));
5937 * Algorithm gets a little messy:
5939 * - if the connector already has an assigned crtc, use it (but make
5940 * sure it's on first)
5942 * - try to find the first unused crtc that can drive this connector,
5943 * and use that if we find one
5946 /* See if we already have a CRTC for this connector */
5947 if (encoder->crtc) {
5948 crtc = encoder->crtc;
5950 intel_crtc = to_intel_crtc(crtc);
5951 old->dpms_mode = intel_crtc->dpms_mode;
5952 old->load_detect_temp = false;
5954 /* Make sure the crtc and connector are running */
5955 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5956 struct drm_encoder_helper_funcs *encoder_funcs;
5957 struct drm_crtc_helper_funcs *crtc_funcs;
5959 crtc_funcs = crtc->helper_private;
5960 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5962 encoder_funcs = encoder->helper_private;
5963 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5969 /* Find an unused one (if possible) */
5970 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5972 if (!(encoder->possible_crtcs & (1 << i)))
5974 if (!possible_crtc->enabled) {
5975 crtc = possible_crtc;
5981 * If we didn't find an unused CRTC, don't use any.
5984 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5988 encoder->crtc = crtc;
5989 connector->encoder = encoder;
5991 intel_crtc = to_intel_crtc(crtc);
5992 old->dpms_mode = intel_crtc->dpms_mode;
5993 old->load_detect_temp = true;
5994 old->release_fb = NULL;
5997 mode = &load_detect_mode;
6001 /* We need a framebuffer large enough to accommodate all accesses
6002 * that the plane may generate whilst we perform load detection.
6003 * We can not rely on the fbcon either being present (we get called
6004 * during its initialisation to detect all boot displays, or it may
6005 * not even exist) or that it is large enough to satisfy the
6008 crtc->fb = mode_fits_in_fbdev(dev, mode);
6009 if (crtc->fb == NULL) {
6010 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6011 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6012 old->release_fb = crtc->fb;
6014 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6015 if (IS_ERR(crtc->fb)) {
6016 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6021 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6022 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6023 if (old->release_fb)
6024 old->release_fb->funcs->destroy(old->release_fb);
6029 /* let the connector get through one full cycle before testing */
6030 intel_wait_for_vblank(dev, intel_crtc->pipe);
6035 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6036 struct drm_connector *connector,
6037 struct intel_load_detect_pipe *old)
6039 struct drm_encoder *encoder = &intel_encoder->base;
6040 struct drm_device *dev = encoder->dev;
6041 struct drm_crtc *crtc = encoder->crtc;
6042 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6043 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6045 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6046 connector->base.id, drm_get_connector_name(connector),
6047 encoder->base.id, drm_get_encoder_name(encoder));
6049 if (old->load_detect_temp) {
6050 connector->encoder = NULL;
6051 drm_helper_disable_unused_functions(dev);
6053 if (old->release_fb)
6054 old->release_fb->funcs->destroy(old->release_fb);
6059 /* Switch crtc and encoder back off if necessary */
6060 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6061 encoder_funcs->dpms(encoder, old->dpms_mode);
6062 crtc_funcs->dpms(crtc, old->dpms_mode);
6066 /* Returns the clock of the currently programmed mode of the given pipe. */
6067 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6069 struct drm_i915_private *dev_priv = dev->dev_private;
6070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6071 int pipe = intel_crtc->pipe;
6072 u32 dpll = I915_READ(DPLL(pipe));
6074 intel_clock_t clock;
6076 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6077 fp = I915_READ(FP0(pipe));
6079 fp = I915_READ(FP1(pipe));
6081 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6082 if (IS_PINEVIEW(dev)) {
6083 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6084 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6086 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6087 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6090 if (!IS_GEN2(dev)) {
6091 if (IS_PINEVIEW(dev))
6092 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6093 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6095 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6096 DPLL_FPA01_P1_POST_DIV_SHIFT);
6098 switch (dpll & DPLL_MODE_MASK) {
6099 case DPLLB_MODE_DAC_SERIAL:
6100 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6103 case DPLLB_MODE_LVDS:
6104 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6108 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6109 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6113 /* XXX: Handle the 100Mhz refclk */
6114 intel_clock(dev, 96000, &clock);
6116 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6119 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6120 DPLL_FPA01_P1_POST_DIV_SHIFT);
6123 if ((dpll & PLL_REF_INPUT_MASK) ==
6124 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6125 /* XXX: might not be 66MHz */
6126 intel_clock(dev, 66000, &clock);
6128 intel_clock(dev, 48000, &clock);
6130 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6133 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6134 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6136 if (dpll & PLL_P2_DIVIDE_BY_4)
6141 intel_clock(dev, 48000, &clock);
6145 /* XXX: It would be nice to validate the clocks, but we can't reuse
6146 * i830PllIsValid() because it relies on the xf86_config connector
6147 * configuration being accurate, which it isn't necessarily.
6153 /** Returns the currently programmed mode of the given pipe. */
6154 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6155 struct drm_crtc *crtc)
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159 int pipe = intel_crtc->pipe;
6160 struct drm_display_mode *mode;
6161 int htot = I915_READ(HTOTAL(pipe));
6162 int hsync = I915_READ(HSYNC(pipe));
6163 int vtot = I915_READ(VTOTAL(pipe));
6164 int vsync = I915_READ(VSYNC(pipe));
6166 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6170 mode->clock = intel_crtc_clock_get(dev, crtc);
6171 mode->hdisplay = (htot & 0xffff) + 1;
6172 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6173 mode->hsync_start = (hsync & 0xffff) + 1;
6174 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6175 mode->vdisplay = (vtot & 0xffff) + 1;
6176 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6177 mode->vsync_start = (vsync & 0xffff) + 1;
6178 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6180 drm_mode_set_name(mode);
6181 drm_mode_set_crtcinfo(mode, 0);
6186 #define GPU_IDLE_TIMEOUT 500 /* ms */
6188 /* When this timer fires, we've been idle for awhile */
6189 static void intel_gpu_idle_timer(unsigned long arg)
6191 struct drm_device *dev = (struct drm_device *)arg;
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6194 if (!list_empty(&dev_priv->mm.active_list)) {
6195 /* Still processing requests, so just re-arm the timer. */
6196 mod_timer(&dev_priv->idle_timer, jiffies +
6197 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6201 dev_priv->busy = false;
6202 queue_work(dev_priv->wq, &dev_priv->idle_work);
6205 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6207 static void intel_crtc_idle_timer(unsigned long arg)
6209 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6210 struct drm_crtc *crtc = &intel_crtc->base;
6211 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6212 struct intel_framebuffer *intel_fb;
6214 intel_fb = to_intel_framebuffer(crtc->fb);
6215 if (intel_fb && intel_fb->obj->active) {
6216 /* The framebuffer is still being accessed by the GPU. */
6217 mod_timer(&intel_crtc->idle_timer, jiffies +
6218 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6222 intel_crtc->busy = false;
6223 queue_work(dev_priv->wq, &dev_priv->idle_work);
6226 static void intel_increase_pllclock(struct drm_crtc *crtc)
6228 struct drm_device *dev = crtc->dev;
6229 drm_i915_private_t *dev_priv = dev->dev_private;
6230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6231 int pipe = intel_crtc->pipe;
6232 int dpll_reg = DPLL(pipe);
6235 if (HAS_PCH_SPLIT(dev))
6238 if (!dev_priv->lvds_downclock_avail)
6241 dpll = I915_READ(dpll_reg);
6242 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6243 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6245 /* Unlock panel regs */
6246 I915_WRITE(PP_CONTROL,
6247 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6249 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6250 I915_WRITE(dpll_reg, dpll);
6251 intel_wait_for_vblank(dev, pipe);
6253 dpll = I915_READ(dpll_reg);
6254 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6255 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6257 /* ...and lock them again */
6258 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6261 /* Schedule downclock */
6262 mod_timer(&intel_crtc->idle_timer, jiffies +
6263 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6266 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6268 struct drm_device *dev = crtc->dev;
6269 drm_i915_private_t *dev_priv = dev->dev_private;
6270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6271 int pipe = intel_crtc->pipe;
6272 int dpll_reg = DPLL(pipe);
6273 int dpll = I915_READ(dpll_reg);
6275 if (HAS_PCH_SPLIT(dev))
6278 if (!dev_priv->lvds_downclock_avail)
6282 * Since this is called by a timer, we should never get here in
6285 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6286 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6288 /* Unlock panel regs */
6289 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6292 dpll |= DISPLAY_RATE_SELECT_FPA1;
6293 I915_WRITE(dpll_reg, dpll);
6294 intel_wait_for_vblank(dev, pipe);
6295 dpll = I915_READ(dpll_reg);
6296 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6297 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6299 /* ...and lock them again */
6300 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6306 * intel_idle_update - adjust clocks for idleness
6307 * @work: work struct
6309 * Either the GPU or display (or both) went idle. Check the busy status
6310 * here and adjust the CRTC and GPU clocks as necessary.
6312 static void intel_idle_update(struct work_struct *work)
6314 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6316 struct drm_device *dev = dev_priv->dev;
6317 struct drm_crtc *crtc;
6318 struct intel_crtc *intel_crtc;
6320 if (!i915_powersave)
6323 mutex_lock(&dev->struct_mutex);
6325 i915_update_gfx_val(dev_priv);
6327 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6328 /* Skip inactive CRTCs */
6332 intel_crtc = to_intel_crtc(crtc);
6333 if (!intel_crtc->busy)
6334 intel_decrease_pllclock(crtc);
6338 mutex_unlock(&dev->struct_mutex);
6342 * intel_mark_busy - mark the GPU and possibly the display busy
6344 * @obj: object we're operating on
6346 * Callers can use this function to indicate that the GPU is busy processing
6347 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6348 * buffer), we'll also mark the display as busy, so we know to increase its
6351 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6353 drm_i915_private_t *dev_priv = dev->dev_private;
6354 struct drm_crtc *crtc = NULL;
6355 struct intel_framebuffer *intel_fb;
6356 struct intel_crtc *intel_crtc;
6358 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6361 if (!dev_priv->busy)
6362 dev_priv->busy = true;
6364 mod_timer(&dev_priv->idle_timer, jiffies +
6365 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6367 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6371 intel_crtc = to_intel_crtc(crtc);
6372 intel_fb = to_intel_framebuffer(crtc->fb);
6373 if (intel_fb->obj == obj) {
6374 if (!intel_crtc->busy) {
6375 /* Non-busy -> busy, upclock */
6376 intel_increase_pllclock(crtc);
6377 intel_crtc->busy = true;
6379 /* Busy -> busy, put off timer */
6380 mod_timer(&intel_crtc->idle_timer, jiffies +
6381 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6387 static void intel_crtc_destroy(struct drm_crtc *crtc)
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 struct drm_device *dev = crtc->dev;
6391 struct intel_unpin_work *work;
6392 unsigned long flags;
6394 spin_lock_irqsave(&dev->event_lock, flags);
6395 work = intel_crtc->unpin_work;
6396 intel_crtc->unpin_work = NULL;
6397 spin_unlock_irqrestore(&dev->event_lock, flags);
6400 cancel_work_sync(&work->work);
6404 drm_crtc_cleanup(crtc);
6409 static void intel_unpin_work_fn(struct work_struct *__work)
6411 struct intel_unpin_work *work =
6412 container_of(__work, struct intel_unpin_work, work);
6414 mutex_lock(&work->dev->struct_mutex);
6415 i915_gem_object_unpin(work->old_fb_obj);
6416 drm_gem_object_unreference(&work->pending_flip_obj->base);
6417 drm_gem_object_unreference(&work->old_fb_obj->base);
6419 intel_update_fbc(work->dev);
6420 mutex_unlock(&work->dev->struct_mutex);
6424 static void do_intel_finish_page_flip(struct drm_device *dev,
6425 struct drm_crtc *crtc)
6427 drm_i915_private_t *dev_priv = dev->dev_private;
6428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6429 struct intel_unpin_work *work;
6430 struct drm_i915_gem_object *obj;
6431 struct drm_pending_vblank_event *e;
6432 struct timeval tnow, tvbl;
6433 unsigned long flags;
6435 /* Ignore early vblank irqs */
6436 if (intel_crtc == NULL)
6439 do_gettimeofday(&tnow);
6441 spin_lock_irqsave(&dev->event_lock, flags);
6442 work = intel_crtc->unpin_work;
6443 if (work == NULL || !work->pending) {
6444 spin_unlock_irqrestore(&dev->event_lock, flags);
6448 intel_crtc->unpin_work = NULL;
6452 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6454 /* Called before vblank count and timestamps have
6455 * been updated for the vblank interval of flip
6456 * completion? Need to increment vblank count and
6457 * add one videorefresh duration to returned timestamp
6458 * to account for this. We assume this happened if we
6459 * get called over 0.9 frame durations after the last
6460 * timestamped vblank.
6462 * This calculation can not be used with vrefresh rates
6463 * below 5Hz (10Hz to be on the safe side) without
6464 * promoting to 64 integers.
6466 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6467 9 * crtc->framedur_ns) {
6468 e->event.sequence++;
6469 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6473 e->event.tv_sec = tvbl.tv_sec;
6474 e->event.tv_usec = tvbl.tv_usec;
6476 list_add_tail(&e->base.link,
6477 &e->base.file_priv->event_list);
6478 wake_up_interruptible(&e->base.file_priv->event_wait);
6481 drm_vblank_put(dev, intel_crtc->pipe);
6483 spin_unlock_irqrestore(&dev->event_lock, flags);
6485 obj = work->old_fb_obj;
6487 atomic_clear_mask(1 << intel_crtc->plane,
6488 &obj->pending_flip.counter);
6489 if (atomic_read(&obj->pending_flip) == 0)
6490 wake_up(&dev_priv->pending_flip_queue);
6492 schedule_work(&work->work);
6494 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6497 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6499 drm_i915_private_t *dev_priv = dev->dev_private;
6500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6502 do_intel_finish_page_flip(dev, crtc);
6505 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6507 drm_i915_private_t *dev_priv = dev->dev_private;
6508 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6510 do_intel_finish_page_flip(dev, crtc);
6513 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6515 drm_i915_private_t *dev_priv = dev->dev_private;
6516 struct intel_crtc *intel_crtc =
6517 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6518 unsigned long flags;
6520 spin_lock_irqsave(&dev->event_lock, flags);
6521 if (intel_crtc->unpin_work) {
6522 if ((++intel_crtc->unpin_work->pending) > 1)
6523 DRM_ERROR("Prepared flip multiple times\n");
6525 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6527 spin_unlock_irqrestore(&dev->event_lock, flags);
6530 static int intel_gen2_queue_flip(struct drm_device *dev,
6531 struct drm_crtc *crtc,
6532 struct drm_framebuffer *fb,
6533 struct drm_i915_gem_object *obj)
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6537 unsigned long offset;
6541 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6545 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6546 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6548 ret = BEGIN_LP_RING(6);
6552 /* Can't queue multiple flips, so wait for the previous
6553 * one to finish before executing the next.
6555 if (intel_crtc->plane)
6556 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6558 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6559 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6561 OUT_RING(MI_DISPLAY_FLIP |
6562 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6563 OUT_RING(fb->pitch);
6564 OUT_RING(obj->gtt_offset + offset);
6571 static int intel_gen3_queue_flip(struct drm_device *dev,
6572 struct drm_crtc *crtc,
6573 struct drm_framebuffer *fb,
6574 struct drm_i915_gem_object *obj)
6576 struct drm_i915_private *dev_priv = dev->dev_private;
6577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6578 unsigned long offset;
6582 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6586 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6587 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6589 ret = BEGIN_LP_RING(6);
6593 if (intel_crtc->plane)
6594 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6596 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6597 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6599 OUT_RING(MI_DISPLAY_FLIP_I915 |
6600 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6601 OUT_RING(fb->pitch);
6602 OUT_RING(obj->gtt_offset + offset);
6610 static int intel_gen4_queue_flip(struct drm_device *dev,
6611 struct drm_crtc *crtc,
6612 struct drm_framebuffer *fb,
6613 struct drm_i915_gem_object *obj)
6615 struct drm_i915_private *dev_priv = dev->dev_private;
6616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6617 uint32_t pf, pipesrc;
6620 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6624 ret = BEGIN_LP_RING(4);
6628 /* i965+ uses the linear or tiled offsets from the
6629 * Display Registers (which do not change across a page-flip)
6630 * so we need only reprogram the base address.
6632 OUT_RING(MI_DISPLAY_FLIP |
6633 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6634 OUT_RING(fb->pitch);
6635 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6637 /* XXX Enabling the panel-fitter across page-flip is so far
6638 * untested on non-native modes, so ignore it for now.
6639 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6642 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6643 OUT_RING(pf | pipesrc);
6649 static int intel_gen6_queue_flip(struct drm_device *dev,
6650 struct drm_crtc *crtc,
6651 struct drm_framebuffer *fb,
6652 struct drm_i915_gem_object *obj)
6654 struct drm_i915_private *dev_priv = dev->dev_private;
6655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6656 uint32_t pf, pipesrc;
6659 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6663 ret = BEGIN_LP_RING(4);
6667 OUT_RING(MI_DISPLAY_FLIP |
6668 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6669 OUT_RING(fb->pitch | obj->tiling_mode);
6670 OUT_RING(obj->gtt_offset);
6672 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6673 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6674 OUT_RING(pf | pipesrc);
6681 * On gen7 we currently use the blit ring because (in early silicon at least)
6682 * the render ring doesn't give us interrpts for page flip completion, which
6683 * means clients will hang after the first flip is queued. Fortunately the
6684 * blit ring generates interrupts properly, so use it instead.
6686 static int intel_gen7_queue_flip(struct drm_device *dev,
6687 struct drm_crtc *crtc,
6688 struct drm_framebuffer *fb,
6689 struct drm_i915_gem_object *obj)
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6693 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6696 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6700 ret = intel_ring_begin(ring, 4);
6704 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6705 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6706 intel_ring_emit(ring, (obj->gtt_offset));
6707 intel_ring_emit(ring, (MI_NOOP));
6708 intel_ring_advance(ring);
6713 static int intel_default_queue_flip(struct drm_device *dev,
6714 struct drm_crtc *crtc,
6715 struct drm_framebuffer *fb,
6716 struct drm_i915_gem_object *obj)
6721 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6722 struct drm_framebuffer *fb,
6723 struct drm_pending_vblank_event *event)
6725 struct drm_device *dev = crtc->dev;
6726 struct drm_i915_private *dev_priv = dev->dev_private;
6727 struct intel_framebuffer *intel_fb;
6728 struct drm_i915_gem_object *obj;
6729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730 struct intel_unpin_work *work;
6731 unsigned long flags;
6734 work = kzalloc(sizeof *work, GFP_KERNEL);
6738 work->event = event;
6739 work->dev = crtc->dev;
6740 intel_fb = to_intel_framebuffer(crtc->fb);
6741 work->old_fb_obj = intel_fb->obj;
6742 INIT_WORK(&work->work, intel_unpin_work_fn);
6744 /* We borrow the event spin lock for protecting unpin_work */
6745 spin_lock_irqsave(&dev->event_lock, flags);
6746 if (intel_crtc->unpin_work) {
6747 spin_unlock_irqrestore(&dev->event_lock, flags);
6750 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6753 intel_crtc->unpin_work = work;
6754 spin_unlock_irqrestore(&dev->event_lock, flags);
6756 intel_fb = to_intel_framebuffer(fb);
6757 obj = intel_fb->obj;
6759 mutex_lock(&dev->struct_mutex);
6761 /* Reference the objects for the scheduled work. */
6762 drm_gem_object_reference(&work->old_fb_obj->base);
6763 drm_gem_object_reference(&obj->base);
6767 ret = drm_vblank_get(dev, intel_crtc->pipe);
6771 work->pending_flip_obj = obj;
6773 work->enable_stall_check = true;
6775 /* Block clients from rendering to the new back buffer until
6776 * the flip occurs and the object is no longer visible.
6778 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6780 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6782 goto cleanup_pending;
6784 intel_disable_fbc(dev);
6785 mutex_unlock(&dev->struct_mutex);
6787 trace_i915_flip_request(intel_crtc->plane, obj);
6792 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6794 drm_gem_object_unreference(&work->old_fb_obj->base);
6795 drm_gem_object_unreference(&obj->base);
6796 mutex_unlock(&dev->struct_mutex);
6798 spin_lock_irqsave(&dev->event_lock, flags);
6799 intel_crtc->unpin_work = NULL;
6800 spin_unlock_irqrestore(&dev->event_lock, flags);
6807 static void intel_sanitize_modesetting(struct drm_device *dev,
6808 int pipe, int plane)
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6813 if (HAS_PCH_SPLIT(dev))
6816 /* Who knows what state these registers were left in by the BIOS or
6819 * If we leave the registers in a conflicting state (e.g. with the
6820 * display plane reading from the other pipe than the one we intend
6821 * to use) then when we attempt to teardown the active mode, we will
6822 * not disable the pipes and planes in the correct order -- leaving
6823 * a plane reading from a disabled pipe and possibly leading to
6824 * undefined behaviour.
6827 reg = DSPCNTR(plane);
6828 val = I915_READ(reg);
6830 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6832 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6835 /* This display plane is active and attached to the other CPU pipe. */
6838 /* Disable the plane and wait for it to stop reading from the pipe. */
6839 intel_disable_plane(dev_priv, plane, pipe);
6840 intel_disable_pipe(dev_priv, pipe);
6843 static void intel_crtc_reset(struct drm_crtc *crtc)
6845 struct drm_device *dev = crtc->dev;
6846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6848 /* Reset flags back to the 'unknown' status so that they
6849 * will be correctly set on the initial modeset.
6851 intel_crtc->dpms_mode = -1;
6853 /* We need to fix up any BIOS configuration that conflicts with
6856 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6859 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6860 .dpms = intel_crtc_dpms,
6861 .mode_fixup = intel_crtc_mode_fixup,
6862 .mode_set = intel_crtc_mode_set,
6863 .mode_set_base = intel_pipe_set_base,
6864 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6865 .load_lut = intel_crtc_load_lut,
6866 .disable = intel_crtc_disable,
6869 static const struct drm_crtc_funcs intel_crtc_funcs = {
6870 .reset = intel_crtc_reset,
6871 .cursor_set = intel_crtc_cursor_set,
6872 .cursor_move = intel_crtc_cursor_move,
6873 .gamma_set = intel_crtc_gamma_set,
6874 .set_config = drm_crtc_helper_set_config,
6875 .destroy = intel_crtc_destroy,
6876 .page_flip = intel_crtc_page_flip,
6879 static void intel_crtc_init(struct drm_device *dev, int pipe)
6881 drm_i915_private_t *dev_priv = dev->dev_private;
6882 struct intel_crtc *intel_crtc;
6885 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6886 if (intel_crtc == NULL)
6889 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6891 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6892 for (i = 0; i < 256; i++) {
6893 intel_crtc->lut_r[i] = i;
6894 intel_crtc->lut_g[i] = i;
6895 intel_crtc->lut_b[i] = i;
6898 /* Swap pipes & planes for FBC on pre-965 */
6899 intel_crtc->pipe = pipe;
6900 intel_crtc->plane = pipe;
6901 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6902 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6903 intel_crtc->plane = !pipe;
6906 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6907 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6908 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6909 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6911 intel_crtc_reset(&intel_crtc->base);
6912 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6913 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6915 if (HAS_PCH_SPLIT(dev)) {
6916 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6917 intel_helper_funcs.commit = ironlake_crtc_commit;
6919 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6920 intel_helper_funcs.commit = i9xx_crtc_commit;
6923 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6925 intel_crtc->busy = false;
6927 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6928 (unsigned long)intel_crtc);
6931 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6932 struct drm_file *file)
6934 drm_i915_private_t *dev_priv = dev->dev_private;
6935 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6936 struct drm_mode_object *drmmode_obj;
6937 struct intel_crtc *crtc;
6940 DRM_ERROR("called with no initialization\n");
6944 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6945 DRM_MODE_OBJECT_CRTC);
6948 DRM_ERROR("no such CRTC id\n");
6952 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6953 pipe_from_crtc_id->pipe = crtc->pipe;
6958 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6960 struct intel_encoder *encoder;
6964 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6965 if (type_mask & encoder->clone_mask)
6966 index_mask |= (1 << entry);
6973 static bool has_edp_a(struct drm_device *dev)
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6977 if (!IS_MOBILE(dev))
6980 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6984 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6990 static void intel_setup_outputs(struct drm_device *dev)
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993 struct intel_encoder *encoder;
6994 bool dpd_is_edp = false;
6995 bool has_lvds = false;
6997 if (IS_MOBILE(dev) && !IS_I830(dev))
6998 has_lvds = intel_lvds_init(dev);
6999 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7000 /* disable the panel fitter on everything but LVDS */
7001 I915_WRITE(PFIT_CONTROL, 0);
7004 if (HAS_PCH_SPLIT(dev)) {
7005 dpd_is_edp = intel_dpd_is_edp(dev);
7008 intel_dp_init(dev, DP_A);
7010 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7011 intel_dp_init(dev, PCH_DP_D);
7014 intel_crt_init(dev);
7016 if (HAS_PCH_SPLIT(dev)) {
7019 if (I915_READ(HDMIB) & PORT_DETECTED) {
7020 /* PCH SDVOB multiplex with HDMIB */
7021 found = intel_sdvo_init(dev, PCH_SDVOB);
7023 intel_hdmi_init(dev, HDMIB);
7024 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7025 intel_dp_init(dev, PCH_DP_B);
7028 if (I915_READ(HDMIC) & PORT_DETECTED)
7029 intel_hdmi_init(dev, HDMIC);
7031 if (I915_READ(HDMID) & PORT_DETECTED)
7032 intel_hdmi_init(dev, HDMID);
7034 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7035 intel_dp_init(dev, PCH_DP_C);
7037 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7038 intel_dp_init(dev, PCH_DP_D);
7040 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7043 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7044 DRM_DEBUG_KMS("probing SDVOB\n");
7045 found = intel_sdvo_init(dev, SDVOB);
7046 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7047 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7048 intel_hdmi_init(dev, SDVOB);
7051 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7052 DRM_DEBUG_KMS("probing DP_B\n");
7053 intel_dp_init(dev, DP_B);
7057 /* Before G4X SDVOC doesn't have its own detect register */
7059 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7060 DRM_DEBUG_KMS("probing SDVOC\n");
7061 found = intel_sdvo_init(dev, SDVOC);
7064 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7066 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7067 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7068 intel_hdmi_init(dev, SDVOC);
7070 if (SUPPORTS_INTEGRATED_DP(dev)) {
7071 DRM_DEBUG_KMS("probing DP_C\n");
7072 intel_dp_init(dev, DP_C);
7076 if (SUPPORTS_INTEGRATED_DP(dev) &&
7077 (I915_READ(DP_D) & DP_DETECTED)) {
7078 DRM_DEBUG_KMS("probing DP_D\n");
7079 intel_dp_init(dev, DP_D);
7081 } else if (IS_GEN2(dev))
7082 intel_dvo_init(dev);
7084 if (SUPPORTS_TV(dev))
7087 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7088 encoder->base.possible_crtcs = encoder->crtc_mask;
7089 encoder->base.possible_clones =
7090 intel_encoder_clones(dev, encoder->clone_mask);
7093 intel_panel_setup_backlight(dev);
7095 /* disable all the possible outputs/crtcs before entering KMS mode */
7096 drm_helper_disable_unused_functions(dev);
7099 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7101 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7103 drm_framebuffer_cleanup(fb);
7104 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7109 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7110 struct drm_file *file,
7111 unsigned int *handle)
7113 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7114 struct drm_i915_gem_object *obj = intel_fb->obj;
7116 return drm_gem_handle_create(file, &obj->base, handle);
7119 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7120 .destroy = intel_user_framebuffer_destroy,
7121 .create_handle = intel_user_framebuffer_create_handle,
7124 int intel_framebuffer_init(struct drm_device *dev,
7125 struct intel_framebuffer *intel_fb,
7126 struct drm_mode_fb_cmd *mode_cmd,
7127 struct drm_i915_gem_object *obj)
7131 if (obj->tiling_mode == I915_TILING_Y)
7134 if (mode_cmd->pitch & 63)
7137 switch (mode_cmd->bpp) {
7140 /* Only pre-ILK can handle 5:5:5 */
7141 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7152 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7154 DRM_ERROR("framebuffer init failed %d\n", ret);
7158 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7159 intel_fb->obj = obj;
7163 static struct drm_framebuffer *
7164 intel_user_framebuffer_create(struct drm_device *dev,
7165 struct drm_file *filp,
7166 struct drm_mode_fb_cmd *mode_cmd)
7168 struct drm_i915_gem_object *obj;
7170 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7171 if (&obj->base == NULL)
7172 return ERR_PTR(-ENOENT);
7174 return intel_framebuffer_create(dev, mode_cmd, obj);
7177 static const struct drm_mode_config_funcs intel_mode_funcs = {
7178 .fb_create = intel_user_framebuffer_create,
7179 .output_poll_changed = intel_fb_output_poll_changed,
7182 static struct drm_i915_gem_object *
7183 intel_alloc_context_page(struct drm_device *dev)
7185 struct drm_i915_gem_object *ctx;
7188 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7190 ctx = i915_gem_alloc_object(dev, 4096);
7192 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7196 ret = i915_gem_object_pin(ctx, 4096, true);
7198 DRM_ERROR("failed to pin power context: %d\n", ret);
7202 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7204 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7211 i915_gem_object_unpin(ctx);
7213 drm_gem_object_unreference(&ctx->base);
7214 mutex_unlock(&dev->struct_mutex);
7218 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7223 rgvswctl = I915_READ16(MEMSWCTL);
7224 if (rgvswctl & MEMCTL_CMD_STS) {
7225 DRM_DEBUG("gpu busy, RCS change rejected\n");
7226 return false; /* still busy with another command */
7229 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7230 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7231 I915_WRITE16(MEMSWCTL, rgvswctl);
7232 POSTING_READ16(MEMSWCTL);
7234 rgvswctl |= MEMCTL_CMD_STS;
7235 I915_WRITE16(MEMSWCTL, rgvswctl);
7240 void ironlake_enable_drps(struct drm_device *dev)
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 u32 rgvmodectl = I915_READ(MEMMODECTL);
7244 u8 fmax, fmin, fstart, vstart;
7246 /* Enable temp reporting */
7247 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7248 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7250 /* 100ms RC evaluation intervals */
7251 I915_WRITE(RCUPEI, 100000);
7252 I915_WRITE(RCDNEI, 100000);
7254 /* Set max/min thresholds to 90ms and 80ms respectively */
7255 I915_WRITE(RCBMAXAVG, 90000);
7256 I915_WRITE(RCBMINAVG, 80000);
7258 I915_WRITE(MEMIHYST, 1);
7260 /* Set up min, max, and cur for interrupt handling */
7261 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7262 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7263 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7264 MEMMODE_FSTART_SHIFT;
7266 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7269 dev_priv->fmax = fmax; /* IPS callback will increase this */
7270 dev_priv->fstart = fstart;
7272 dev_priv->max_delay = fstart;
7273 dev_priv->min_delay = fmin;
7274 dev_priv->cur_delay = fstart;
7276 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7277 fmax, fmin, fstart);
7279 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7282 * Interrupts will be enabled in ironlake_irq_postinstall
7285 I915_WRITE(VIDSTART, vstart);
7286 POSTING_READ(VIDSTART);
7288 rgvmodectl |= MEMMODE_SWMODE_EN;
7289 I915_WRITE(MEMMODECTL, rgvmodectl);
7291 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7292 DRM_ERROR("stuck trying to change perf mode\n");
7295 ironlake_set_drps(dev, fstart);
7297 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7299 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7300 dev_priv->last_count2 = I915_READ(0x112f4);
7301 getrawmonotonic(&dev_priv->last_time2);
7304 void ironlake_disable_drps(struct drm_device *dev)
7306 struct drm_i915_private *dev_priv = dev->dev_private;
7307 u16 rgvswctl = I915_READ16(MEMSWCTL);
7309 /* Ack interrupts, disable EFC interrupt */
7310 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7311 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7312 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7313 I915_WRITE(DEIIR, DE_PCU_EVENT);
7314 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7316 /* Go back to the starting frequency */
7317 ironlake_set_drps(dev, dev_priv->fstart);
7319 rgvswctl |= MEMCTL_CMD_STS;
7320 I915_WRITE(MEMSWCTL, rgvswctl);
7325 void gen6_set_rps(struct drm_device *dev, u8 val)
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7330 swreq = (val & 0x3ff) << 25;
7331 I915_WRITE(GEN6_RPNSWREQ, swreq);
7334 void gen6_disable_rps(struct drm_device *dev)
7336 struct drm_i915_private *dev_priv = dev->dev_private;
7338 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7339 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7340 I915_WRITE(GEN6_PMIER, 0);
7342 spin_lock_irq(&dev_priv->rps_lock);
7343 dev_priv->pm_iir = 0;
7344 spin_unlock_irq(&dev_priv->rps_lock);
7346 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7349 static unsigned long intel_pxfreq(u32 vidfreq)
7352 int div = (vidfreq & 0x3f0000) >> 16;
7353 int post = (vidfreq & 0x3000) >> 12;
7354 int pre = (vidfreq & 0x7);
7359 freq = ((div * 133333) / ((1<<post) * pre));
7364 void intel_init_emon(struct drm_device *dev)
7366 struct drm_i915_private *dev_priv = dev->dev_private;
7371 /* Disable to program */
7375 /* Program energy weights for various events */
7376 I915_WRITE(SDEW, 0x15040d00);
7377 I915_WRITE(CSIEW0, 0x007f0000);
7378 I915_WRITE(CSIEW1, 0x1e220004);
7379 I915_WRITE(CSIEW2, 0x04000004);
7381 for (i = 0; i < 5; i++)
7382 I915_WRITE(PEW + (i * 4), 0);
7383 for (i = 0; i < 3; i++)
7384 I915_WRITE(DEW + (i * 4), 0);
7386 /* Program P-state weights to account for frequency power adjustment */
7387 for (i = 0; i < 16; i++) {
7388 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7389 unsigned long freq = intel_pxfreq(pxvidfreq);
7390 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7395 val *= (freq / 1000);
7397 val /= (127*127*900);
7399 DRM_ERROR("bad pxval: %ld\n", val);
7402 /* Render standby states get 0 weight */
7406 for (i = 0; i < 4; i++) {
7407 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7408 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7409 I915_WRITE(PXW + (i * 4), val);
7412 /* Adjust magic regs to magic values (more experimental results) */
7413 I915_WRITE(OGW0, 0);
7414 I915_WRITE(OGW1, 0);
7415 I915_WRITE(EG0, 0x00007f00);
7416 I915_WRITE(EG1, 0x0000000e);
7417 I915_WRITE(EG2, 0x000e0000);
7418 I915_WRITE(EG3, 0x68000300);
7419 I915_WRITE(EG4, 0x42000000);
7420 I915_WRITE(EG5, 0x00140031);
7424 for (i = 0; i < 8; i++)
7425 I915_WRITE(PXWL + (i * 4), 0);
7427 /* Enable PMON + select events */
7428 I915_WRITE(ECR, 0x80000019);
7430 lcfuse = I915_READ(LCFUSE02);
7432 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7435 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7437 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7438 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7439 u32 pcu_mbox, rc6_mask = 0;
7440 int cur_freq, min_freq, max_freq;
7443 /* Here begins a magic sequence of register writes to enable
7444 * auto-downclocking.
7446 * Perhaps there might be some value in exposing these to
7449 I915_WRITE(GEN6_RC_STATE, 0);
7450 mutex_lock(&dev_priv->dev->struct_mutex);
7451 gen6_gt_force_wake_get(dev_priv);
7453 /* disable the counters and set deterministic thresholds */
7454 I915_WRITE(GEN6_RC_CONTROL, 0);
7456 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7457 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7458 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7459 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7460 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7462 for (i = 0; i < I915_NUM_RINGS; i++)
7463 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7465 I915_WRITE(GEN6_RC_SLEEP, 0);
7466 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7467 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7468 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7469 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7471 if (i915_enable_rc6)
7472 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7473 GEN6_RC_CTL_RC6_ENABLE;
7475 I915_WRITE(GEN6_RC_CONTROL,
7477 GEN6_RC_CTL_EI_MODE(1) |
7478 GEN6_RC_CTL_HW_ENABLE);
7480 I915_WRITE(GEN6_RPNSWREQ,
7481 GEN6_FREQUENCY(10) |
7483 GEN6_AGGRESSIVE_TURBO);
7484 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7485 GEN6_FREQUENCY(12));
7487 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7488 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7491 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7492 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7493 I915_WRITE(GEN6_RP_UP_EI, 100000);
7494 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7495 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7496 I915_WRITE(GEN6_RP_CONTROL,
7497 GEN6_RP_MEDIA_TURBO |
7498 GEN6_RP_USE_NORMAL_FREQ |
7499 GEN6_RP_MEDIA_IS_GFX |
7501 GEN6_RP_UP_BUSY_AVG |
7502 GEN6_RP_DOWN_IDLE_CONT);
7504 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7506 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7508 I915_WRITE(GEN6_PCODE_DATA, 0);
7509 I915_WRITE(GEN6_PCODE_MAILBOX,
7511 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7512 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7514 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7516 min_freq = (rp_state_cap & 0xff0000) >> 16;
7517 max_freq = rp_state_cap & 0xff;
7518 cur_freq = (gt_perf_status & 0xff00) >> 8;
7520 /* Check for overclock support */
7521 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7523 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7524 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7525 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7526 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7528 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7529 if (pcu_mbox & (1<<31)) { /* OC supported */
7530 max_freq = pcu_mbox & 0xff;
7531 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7534 /* In units of 100MHz */
7535 dev_priv->max_delay = max_freq;
7536 dev_priv->min_delay = min_freq;
7537 dev_priv->cur_delay = cur_freq;
7539 /* requires MSI enabled */
7540 I915_WRITE(GEN6_PMIER,
7541 GEN6_PM_MBOX_EVENT |
7542 GEN6_PM_THERMAL_EVENT |
7543 GEN6_PM_RP_DOWN_TIMEOUT |
7544 GEN6_PM_RP_UP_THRESHOLD |
7545 GEN6_PM_RP_DOWN_THRESHOLD |
7546 GEN6_PM_RP_UP_EI_EXPIRED |
7547 GEN6_PM_RP_DOWN_EI_EXPIRED);
7548 spin_lock_irq(&dev_priv->rps_lock);
7549 WARN_ON(dev_priv->pm_iir != 0);
7550 I915_WRITE(GEN6_PMIMR, 0);
7551 spin_unlock_irq(&dev_priv->rps_lock);
7552 /* enable all PM interrupts */
7553 I915_WRITE(GEN6_PMINTRMSK, 0);
7555 gen6_gt_force_wake_put(dev_priv);
7556 mutex_unlock(&dev_priv->dev->struct_mutex);
7559 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7562 int gpu_freq, ia_freq, max_ia_freq;
7563 int scaling_factor = 180;
7565 max_ia_freq = cpufreq_quick_get_max(0);
7567 * Default to measured freq if none found, PCU will ensure we don't go
7571 max_ia_freq = tsc_khz;
7573 /* Convert from kHz to MHz */
7574 max_ia_freq /= 1000;
7576 mutex_lock(&dev_priv->dev->struct_mutex);
7579 * For each potential GPU frequency, load a ring frequency we'd like
7580 * to use for memory access. We do this by specifying the IA frequency
7581 * the PCU should use as a reference to determine the ring frequency.
7583 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7585 int diff = dev_priv->max_delay - gpu_freq;
7588 * For GPU frequencies less than 750MHz, just use the lowest
7591 if (gpu_freq < min_freq)
7594 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7595 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7597 I915_WRITE(GEN6_PCODE_DATA,
7598 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7600 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7601 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7602 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7603 GEN6_PCODE_READY) == 0, 10)) {
7604 DRM_ERROR("pcode write of freq table timed out\n");
7609 mutex_unlock(&dev_priv->dev->struct_mutex);
7612 static void ironlake_init_clock_gating(struct drm_device *dev)
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7617 /* Required for FBC */
7618 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7619 DPFCRUNIT_CLOCK_GATE_DISABLE |
7620 DPFDUNIT_CLOCK_GATE_DISABLE;
7621 /* Required for CxSR */
7622 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7624 I915_WRITE(PCH_3DCGDIS0,
7625 MARIUNIT_CLOCK_GATE_DISABLE |
7626 SVSMUNIT_CLOCK_GATE_DISABLE);
7627 I915_WRITE(PCH_3DCGDIS1,
7628 VFMUNIT_CLOCK_GATE_DISABLE);
7630 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7633 * According to the spec the following bits should be set in
7634 * order to enable memory self-refresh
7635 * The bit 22/21 of 0x42004
7636 * The bit 5 of 0x42020
7637 * The bit 15 of 0x45000
7639 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7640 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7641 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7642 I915_WRITE(ILK_DSPCLK_GATE,
7643 (I915_READ(ILK_DSPCLK_GATE) |
7644 ILK_DPARB_CLK_GATE));
7645 I915_WRITE(DISP_ARB_CTL,
7646 (I915_READ(DISP_ARB_CTL) |
7648 I915_WRITE(WM3_LP_ILK, 0);
7649 I915_WRITE(WM2_LP_ILK, 0);
7650 I915_WRITE(WM1_LP_ILK, 0);
7653 * Based on the document from hardware guys the following bits
7654 * should be set unconditionally in order to enable FBC.
7655 * The bit 22 of 0x42000
7656 * The bit 22 of 0x42004
7657 * The bit 7,8,9 of 0x42020.
7659 if (IS_IRONLAKE_M(dev)) {
7660 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7661 I915_READ(ILK_DISPLAY_CHICKEN1) |
7663 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7664 I915_READ(ILK_DISPLAY_CHICKEN2) |
7666 I915_WRITE(ILK_DSPCLK_GATE,
7667 I915_READ(ILK_DSPCLK_GATE) |
7673 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7674 I915_READ(ILK_DISPLAY_CHICKEN2) |
7675 ILK_ELPIN_409_SELECT);
7676 I915_WRITE(_3D_CHICKEN2,
7677 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7678 _3D_CHICKEN2_WM_READ_PIPELINED);
7681 static void gen6_init_clock_gating(struct drm_device *dev)
7683 struct drm_i915_private *dev_priv = dev->dev_private;
7685 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7687 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7689 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7690 I915_READ(ILK_DISPLAY_CHICKEN2) |
7691 ILK_ELPIN_409_SELECT);
7693 I915_WRITE(WM3_LP_ILK, 0);
7694 I915_WRITE(WM2_LP_ILK, 0);
7695 I915_WRITE(WM1_LP_ILK, 0);
7698 * According to the spec the following bits should be
7699 * set in order to enable memory self-refresh and fbc:
7700 * The bit21 and bit22 of 0x42000
7701 * The bit21 and bit22 of 0x42004
7702 * The bit5 and bit7 of 0x42020
7703 * The bit14 of 0x70180
7704 * The bit14 of 0x71180
7706 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7707 I915_READ(ILK_DISPLAY_CHICKEN1) |
7708 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7709 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7710 I915_READ(ILK_DISPLAY_CHICKEN2) |
7711 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7712 I915_WRITE(ILK_DSPCLK_GATE,
7713 I915_READ(ILK_DSPCLK_GATE) |
7714 ILK_DPARB_CLK_GATE |
7718 I915_WRITE(DSPCNTR(pipe),
7719 I915_READ(DSPCNTR(pipe)) |
7720 DISPPLANE_TRICKLE_FEED_DISABLE);
7723 static void ivybridge_init_clock_gating(struct drm_device *dev)
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7727 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7729 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7731 I915_WRITE(WM3_LP_ILK, 0);
7732 I915_WRITE(WM2_LP_ILK, 0);
7733 I915_WRITE(WM1_LP_ILK, 0);
7735 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7738 I915_WRITE(DSPCNTR(pipe),
7739 I915_READ(DSPCNTR(pipe)) |
7740 DISPPLANE_TRICKLE_FEED_DISABLE);
7743 static void g4x_init_clock_gating(struct drm_device *dev)
7745 struct drm_i915_private *dev_priv = dev->dev_private;
7746 uint32_t dspclk_gate;
7748 I915_WRITE(RENCLK_GATE_D1, 0);
7749 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7750 GS_UNIT_CLOCK_GATE_DISABLE |
7751 CL_UNIT_CLOCK_GATE_DISABLE);
7752 I915_WRITE(RAMCLK_GATE_D, 0);
7753 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7754 OVRUNIT_CLOCK_GATE_DISABLE |
7755 OVCUNIT_CLOCK_GATE_DISABLE;
7757 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7758 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7761 static void crestline_init_clock_gating(struct drm_device *dev)
7763 struct drm_i915_private *dev_priv = dev->dev_private;
7765 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7766 I915_WRITE(RENCLK_GATE_D2, 0);
7767 I915_WRITE(DSPCLK_GATE_D, 0);
7768 I915_WRITE(RAMCLK_GATE_D, 0);
7769 I915_WRITE16(DEUC, 0);
7772 static void broadwater_init_clock_gating(struct drm_device *dev)
7774 struct drm_i915_private *dev_priv = dev->dev_private;
7776 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7777 I965_RCC_CLOCK_GATE_DISABLE |
7778 I965_RCPB_CLOCK_GATE_DISABLE |
7779 I965_ISC_CLOCK_GATE_DISABLE |
7780 I965_FBC_CLOCK_GATE_DISABLE);
7781 I915_WRITE(RENCLK_GATE_D2, 0);
7784 static void gen3_init_clock_gating(struct drm_device *dev)
7786 struct drm_i915_private *dev_priv = dev->dev_private;
7787 u32 dstate = I915_READ(D_STATE);
7789 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7790 DSTATE_DOT_CLOCK_GATING;
7791 I915_WRITE(D_STATE, dstate);
7794 static void i85x_init_clock_gating(struct drm_device *dev)
7796 struct drm_i915_private *dev_priv = dev->dev_private;
7798 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7801 static void i830_init_clock_gating(struct drm_device *dev)
7803 struct drm_i915_private *dev_priv = dev->dev_private;
7805 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7808 static void ibx_init_clock_gating(struct drm_device *dev)
7810 struct drm_i915_private *dev_priv = dev->dev_private;
7813 * On Ibex Peak and Cougar Point, we need to disable clock
7814 * gating for the panel power sequencer or it will fail to
7815 * start up when no ports are active.
7817 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7820 static void cpt_init_clock_gating(struct drm_device *dev)
7822 struct drm_i915_private *dev_priv = dev->dev_private;
7825 * On Ibex Peak and Cougar Point, we need to disable clock
7826 * gating for the panel power sequencer or it will fail to
7827 * start up when no ports are active.
7829 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7830 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7831 DPLS_EDP_PPS_FIX_DIS);
7834 static void ironlake_teardown_rc6(struct drm_device *dev)
7836 struct drm_i915_private *dev_priv = dev->dev_private;
7838 if (dev_priv->renderctx) {
7839 i915_gem_object_unpin(dev_priv->renderctx);
7840 drm_gem_object_unreference(&dev_priv->renderctx->base);
7841 dev_priv->renderctx = NULL;
7844 if (dev_priv->pwrctx) {
7845 i915_gem_object_unpin(dev_priv->pwrctx);
7846 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7847 dev_priv->pwrctx = NULL;
7851 static void ironlake_disable_rc6(struct drm_device *dev)
7853 struct drm_i915_private *dev_priv = dev->dev_private;
7855 if (I915_READ(PWRCTXA)) {
7856 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7857 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7858 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7861 I915_WRITE(PWRCTXA, 0);
7862 POSTING_READ(PWRCTXA);
7864 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7865 POSTING_READ(RSTDBYCTL);
7868 ironlake_teardown_rc6(dev);
7871 static int ironlake_setup_rc6(struct drm_device *dev)
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7875 if (dev_priv->renderctx == NULL)
7876 dev_priv->renderctx = intel_alloc_context_page(dev);
7877 if (!dev_priv->renderctx)
7880 if (dev_priv->pwrctx == NULL)
7881 dev_priv->pwrctx = intel_alloc_context_page(dev);
7882 if (!dev_priv->pwrctx) {
7883 ironlake_teardown_rc6(dev);
7890 void ironlake_enable_rc6(struct drm_device *dev)
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7895 /* rc6 disabled by default due to repeated reports of hanging during
7898 if (!i915_enable_rc6)
7901 mutex_lock(&dev->struct_mutex);
7902 ret = ironlake_setup_rc6(dev);
7904 mutex_unlock(&dev->struct_mutex);
7909 * GPU can automatically power down the render unit if given a page
7912 ret = BEGIN_LP_RING(6);
7914 ironlake_teardown_rc6(dev);
7915 mutex_unlock(&dev->struct_mutex);
7919 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7920 OUT_RING(MI_SET_CONTEXT);
7921 OUT_RING(dev_priv->renderctx->gtt_offset |
7923 MI_SAVE_EXT_STATE_EN |
7924 MI_RESTORE_EXT_STATE_EN |
7925 MI_RESTORE_INHIBIT);
7926 OUT_RING(MI_SUSPEND_FLUSH);
7932 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7933 * does an implicit flush, combined with MI_FLUSH above, it should be
7934 * safe to assume that renderctx is valid
7936 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7938 DRM_ERROR("failed to enable ironlake power power savings\n");
7939 ironlake_teardown_rc6(dev);
7940 mutex_unlock(&dev->struct_mutex);
7944 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7945 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7946 mutex_unlock(&dev->struct_mutex);
7949 void intel_init_clock_gating(struct drm_device *dev)
7951 struct drm_i915_private *dev_priv = dev->dev_private;
7953 dev_priv->display.init_clock_gating(dev);
7955 if (dev_priv->display.init_pch_clock_gating)
7956 dev_priv->display.init_pch_clock_gating(dev);
7959 /* Set up chip specific display functions */
7960 static void intel_init_display(struct drm_device *dev)
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7964 /* We always want a DPMS function */
7965 if (HAS_PCH_SPLIT(dev)) {
7966 dev_priv->display.dpms = ironlake_crtc_dpms;
7967 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7968 dev_priv->display.update_plane = ironlake_update_plane;
7970 dev_priv->display.dpms = i9xx_crtc_dpms;
7971 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7972 dev_priv->display.update_plane = i9xx_update_plane;
7975 if (I915_HAS_FBC(dev)) {
7976 if (HAS_PCH_SPLIT(dev)) {
7977 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7978 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7979 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7980 } else if (IS_GM45(dev)) {
7981 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7982 dev_priv->display.enable_fbc = g4x_enable_fbc;
7983 dev_priv->display.disable_fbc = g4x_disable_fbc;
7984 } else if (IS_CRESTLINE(dev)) {
7985 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7986 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7987 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7989 /* 855GM needs testing */
7992 /* Returns the core display clock speed */
7993 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7994 dev_priv->display.get_display_clock_speed =
7995 i945_get_display_clock_speed;
7996 else if (IS_I915G(dev))
7997 dev_priv->display.get_display_clock_speed =
7998 i915_get_display_clock_speed;
7999 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8000 dev_priv->display.get_display_clock_speed =
8001 i9xx_misc_get_display_clock_speed;
8002 else if (IS_I915GM(dev))
8003 dev_priv->display.get_display_clock_speed =
8004 i915gm_get_display_clock_speed;
8005 else if (IS_I865G(dev))
8006 dev_priv->display.get_display_clock_speed =
8007 i865_get_display_clock_speed;
8008 else if (IS_I85X(dev))
8009 dev_priv->display.get_display_clock_speed =
8010 i855_get_display_clock_speed;
8012 dev_priv->display.get_display_clock_speed =
8013 i830_get_display_clock_speed;
8015 /* For FIFO watermark updates */
8016 if (HAS_PCH_SPLIT(dev)) {
8017 if (HAS_PCH_IBX(dev))
8018 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8019 else if (HAS_PCH_CPT(dev))
8020 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8023 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8024 dev_priv->display.update_wm = ironlake_update_wm;
8026 DRM_DEBUG_KMS("Failed to get proper latency. "
8028 dev_priv->display.update_wm = NULL;
8030 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8031 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8032 } else if (IS_GEN6(dev)) {
8033 if (SNB_READ_WM0_LATENCY()) {
8034 dev_priv->display.update_wm = sandybridge_update_wm;
8036 DRM_DEBUG_KMS("Failed to read display plane latency. "
8038 dev_priv->display.update_wm = NULL;
8040 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8041 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8042 } else if (IS_IVYBRIDGE(dev)) {
8043 /* FIXME: detect B0+ stepping and use auto training */
8044 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8045 if (SNB_READ_WM0_LATENCY()) {
8046 dev_priv->display.update_wm = sandybridge_update_wm;
8048 DRM_DEBUG_KMS("Failed to read display plane latency. "
8050 dev_priv->display.update_wm = NULL;
8052 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8055 dev_priv->display.update_wm = NULL;
8056 } else if (IS_PINEVIEW(dev)) {
8057 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8060 dev_priv->mem_freq)) {
8061 DRM_INFO("failed to find known CxSR latency "
8062 "(found ddr%s fsb freq %d, mem freq %d), "
8064 (dev_priv->is_ddr3 == 1) ? "3": "2",
8065 dev_priv->fsb_freq, dev_priv->mem_freq);
8066 /* Disable CxSR and never update its watermark again */
8067 pineview_disable_cxsr(dev);
8068 dev_priv->display.update_wm = NULL;
8070 dev_priv->display.update_wm = pineview_update_wm;
8071 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8072 } else if (IS_G4X(dev)) {
8073 dev_priv->display.update_wm = g4x_update_wm;
8074 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8075 } else if (IS_GEN4(dev)) {
8076 dev_priv->display.update_wm = i965_update_wm;
8077 if (IS_CRESTLINE(dev))
8078 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8079 else if (IS_BROADWATER(dev))
8080 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8081 } else if (IS_GEN3(dev)) {
8082 dev_priv->display.update_wm = i9xx_update_wm;
8083 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8084 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8085 } else if (IS_I865G(dev)) {
8086 dev_priv->display.update_wm = i830_update_wm;
8087 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8088 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8089 } else if (IS_I85X(dev)) {
8090 dev_priv->display.update_wm = i9xx_update_wm;
8091 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8092 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8094 dev_priv->display.update_wm = i830_update_wm;
8095 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8097 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8099 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8102 /* Default just returns -ENODEV to indicate unsupported */
8103 dev_priv->display.queue_flip = intel_default_queue_flip;
8105 switch (INTEL_INFO(dev)->gen) {
8107 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8111 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8116 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8120 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8123 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8129 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8130 * resume, or other times. This quirk makes sure that's the case for
8133 static void quirk_pipea_force (struct drm_device *dev)
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8137 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8138 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8142 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8144 static void quirk_ssc_force_disable(struct drm_device *dev)
8146 struct drm_i915_private *dev_priv = dev->dev_private;
8147 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8150 struct intel_quirk {
8152 int subsystem_vendor;
8153 int subsystem_device;
8154 void (*hook)(struct drm_device *dev);
8157 struct intel_quirk intel_quirks[] = {
8158 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8159 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8160 /* HP Mini needs pipe A force quirk (LP: #322104) */
8161 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8163 /* Thinkpad R31 needs pipe A force quirk */
8164 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8165 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8166 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8168 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8169 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8170 /* ThinkPad X40 needs pipe A force quirk */
8172 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8173 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8175 /* 855 & before need to leave pipe A & dpll A up */
8176 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8177 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8179 /* Lenovo U160 cannot use SSC on LVDS */
8180 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8183 static void intel_init_quirks(struct drm_device *dev)
8185 struct pci_dev *d = dev->pdev;
8188 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8189 struct intel_quirk *q = &intel_quirks[i];
8191 if (d->device == q->device &&
8192 (d->subsystem_vendor == q->subsystem_vendor ||
8193 q->subsystem_vendor == PCI_ANY_ID) &&
8194 (d->subsystem_device == q->subsystem_device ||
8195 q->subsystem_device == PCI_ANY_ID))
8200 /* Disable the VGA plane that we never use */
8201 static void i915_disable_vga(struct drm_device *dev)
8203 struct drm_i915_private *dev_priv = dev->dev_private;
8207 if (HAS_PCH_SPLIT(dev))
8208 vga_reg = CPU_VGACNTRL;
8212 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8213 outb(1, VGA_SR_INDEX);
8214 sr1 = inb(VGA_SR_DATA);
8215 outb(sr1 | 1<<5, VGA_SR_DATA);
8216 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8219 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8220 POSTING_READ(vga_reg);
8223 void intel_modeset_init(struct drm_device *dev)
8225 struct drm_i915_private *dev_priv = dev->dev_private;
8228 drm_mode_config_init(dev);
8230 dev->mode_config.min_width = 0;
8231 dev->mode_config.min_height = 0;
8233 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8235 intel_init_quirks(dev);
8237 intel_init_display(dev);
8240 dev->mode_config.max_width = 2048;
8241 dev->mode_config.max_height = 2048;
8242 } else if (IS_GEN3(dev)) {
8243 dev->mode_config.max_width = 4096;
8244 dev->mode_config.max_height = 4096;
8246 dev->mode_config.max_width = 8192;
8247 dev->mode_config.max_height = 8192;
8249 dev->mode_config.fb_base = dev->agp->base;
8251 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8252 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8254 for (i = 0; i < dev_priv->num_pipe; i++) {
8255 intel_crtc_init(dev, i);
8258 /* Just disable it once at startup */
8259 i915_disable_vga(dev);
8260 intel_setup_outputs(dev);
8262 intel_init_clock_gating(dev);
8264 if (IS_IRONLAKE_M(dev)) {
8265 ironlake_enable_drps(dev);
8266 intel_init_emon(dev);
8269 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8270 gen6_enable_rps(dev_priv);
8271 gen6_update_ring_freq(dev_priv);
8274 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8275 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8276 (unsigned long)dev);
8279 void intel_modeset_gem_init(struct drm_device *dev)
8281 if (IS_IRONLAKE_M(dev))
8282 ironlake_enable_rc6(dev);
8284 intel_setup_overlay(dev);
8287 void intel_modeset_cleanup(struct drm_device *dev)
8289 struct drm_i915_private *dev_priv = dev->dev_private;
8290 struct drm_crtc *crtc;
8291 struct intel_crtc *intel_crtc;
8293 drm_kms_helper_poll_fini(dev);
8294 mutex_lock(&dev->struct_mutex);
8296 intel_unregister_dsm_handler();
8299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8300 /* Skip inactive CRTCs */
8304 intel_crtc = to_intel_crtc(crtc);
8305 intel_increase_pllclock(crtc);
8308 intel_disable_fbc(dev);
8310 if (IS_IRONLAKE_M(dev))
8311 ironlake_disable_drps(dev);
8312 if (IS_GEN6(dev) || IS_GEN7(dev))
8313 gen6_disable_rps(dev);
8315 if (IS_IRONLAKE_M(dev))
8316 ironlake_disable_rc6(dev);
8318 mutex_unlock(&dev->struct_mutex);
8320 /* Disable the irq before mode object teardown, for the irq might
8321 * enqueue unpin/hotplug work. */
8322 drm_irq_uninstall(dev);
8323 cancel_work_sync(&dev_priv->hotplug_work);
8325 /* flush any delayed tasks or pending work */
8326 flush_scheduled_work();
8328 /* Shut off idle work before the crtcs get freed. */
8329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8330 intel_crtc = to_intel_crtc(crtc);
8331 del_timer_sync(&intel_crtc->idle_timer);
8333 del_timer_sync(&dev_priv->idle_timer);
8334 cancel_work_sync(&dev_priv->idle_work);
8336 drm_mode_config_cleanup(dev);
8340 * Return which encoder is currently attached for connector.
8342 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8344 return &intel_attached_encoder(connector)->base;
8347 void intel_connector_attach_encoder(struct intel_connector *connector,
8348 struct intel_encoder *encoder)
8350 connector->encoder = encoder;
8351 drm_mode_connector_attach_encoder(&connector->base,
8356 * set vga decode state - true == enable VGA decode
8358 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8360 struct drm_i915_private *dev_priv = dev->dev_private;
8363 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8365 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8367 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8368 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8372 #ifdef CONFIG_DEBUG_FS
8373 #include <linux/seq_file.h>
8375 struct intel_display_error_state {
8376 struct intel_cursor_error_state {
8383 struct intel_pipe_error_state {
8395 struct intel_plane_error_state {
8406 struct intel_display_error_state *
8407 intel_display_capture_error_state(struct drm_device *dev)
8409 drm_i915_private_t *dev_priv = dev->dev_private;
8410 struct intel_display_error_state *error;
8413 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8417 for (i = 0; i < 2; i++) {
8418 error->cursor[i].control = I915_READ(CURCNTR(i));
8419 error->cursor[i].position = I915_READ(CURPOS(i));
8420 error->cursor[i].base = I915_READ(CURBASE(i));
8422 error->plane[i].control = I915_READ(DSPCNTR(i));
8423 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8424 error->plane[i].size = I915_READ(DSPSIZE(i));
8425 error->plane[i].pos= I915_READ(DSPPOS(i));
8426 error->plane[i].addr = I915_READ(DSPADDR(i));
8427 if (INTEL_INFO(dev)->gen >= 4) {
8428 error->plane[i].surface = I915_READ(DSPSURF(i));
8429 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8432 error->pipe[i].conf = I915_READ(PIPECONF(i));
8433 error->pipe[i].source = I915_READ(PIPESRC(i));
8434 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8435 error->pipe[i].hblank = I915_READ(HBLANK(i));
8436 error->pipe[i].hsync = I915_READ(HSYNC(i));
8437 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8438 error->pipe[i].vblank = I915_READ(VBLANK(i));
8439 error->pipe[i].vsync = I915_READ(VSYNC(i));
8446 intel_display_print_error_state(struct seq_file *m,
8447 struct drm_device *dev,
8448 struct intel_display_error_state *error)
8452 for (i = 0; i < 2; i++) {
8453 seq_printf(m, "Pipe [%d]:\n", i);
8454 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8455 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8456 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8457 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8458 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8459 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8460 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8461 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8463 seq_printf(m, "Plane [%d]:\n", i);
8464 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8465 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8466 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8467 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8468 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8469 if (INTEL_INFO(dev)->gen >= 4) {
8470 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8471 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8474 seq_printf(m, "Cursor [%d]:\n", i);
8475 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8476 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8477 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);