drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 /* FDI */
  80 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  81
  82 static bool
  83 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  84                     int target, int refclk, intel_clock_t *best_clock);
  85 static bool
  86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87                         int target, int refclk, intel_clock_t *best_clock);
  88
  89 static bool
  90 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  91                       int target, int refclk, intel_clock_t *best_clock);
  92 static bool
  93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                            int target, int refclk, intel_clock_t *best_clock);
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dvo = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 930000, .max = 1400000 },
 109         .n = { .min = 3, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117         .find_pll = intel_find_best_PLL,
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 930000, .max = 1400000 },
 123         .n = { .min = 3, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131         .find_pll = intel_find_best_PLL,
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 10, .max = 22 },
 140         .m2 = { .min = 5, .max = 9 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145         .find_pll = intel_find_best_PLL,
 146 };
 147
 148 static const intel_limit_t intel_limits_i9xx_lvds = {
 149         .dot = { .min = 20000, .max = 400000 },
 150         .vco = { .min = 1400000, .max = 2800000 },
 151         .n = { .min = 1, .max = 6 },
 152         .m = { .min = 70, .max = 120 },
 153         .m1 = { .min = 10, .max = 22 },
 154         .m2 = { .min = 5, .max = 9 },
 155         .p = { .min = 7, .max = 98 },
 156         .p1 = { .min = 1, .max = 8 },
 157         .p2 = { .dot_limit = 112000,
 158                 .p2_slow = 14, .p2_fast = 7 },
 159         .find_pll = intel_find_best_PLL,
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176         .find_pll = intel_g4x_find_best_PLL,
 177 };
 178
 179 static const intel_limit_t intel_limits_g4x_hdmi = {
 180         .dot = { .min = 22000, .max = 400000 },
 181         .vco = { .min = 1750000, .max = 3500000},
 182         .n = { .min = 1, .max = 4 },
 183         .m = { .min = 104, .max = 138 },
 184         .m1 = { .min = 16, .max = 23 },
 185         .m2 = { .min = 5, .max = 11 },
 186         .p = { .min = 5, .max = 80 },
 187         .p1 = { .min = 1, .max = 8},
 188         .p2 = { .dot_limit = 165000,
 189                 .p2_slow = 10, .p2_fast = 5 },
 190         .find_pll = intel_g4x_find_best_PLL,
 191 };
 192
 193 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 194         .dot = { .min = 20000, .max = 115000 },
 195         .vco = { .min = 1750000, .max = 3500000 },
 196         .n = { .min = 1, .max = 3 },
 197         .m = { .min = 104, .max = 138 },
 198         .m1 = { .min = 17, .max = 23 },
 199         .m2 = { .min = 5, .max = 11 },
 200         .p = { .min = 28, .max = 112 },
 201         .p1 = { .min = 2, .max = 8 },
 202         .p2 = { .dot_limit = 0,
 203                 .p2_slow = 14, .p2_fast = 14
 204         },
 205         .find_pll = intel_g4x_find_best_PLL,
 206 };
 207
 208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 209         .dot = { .min = 80000, .max = 224000 },
 210         .vco = { .min = 1750000, .max = 3500000 },
 211         .n = { .min = 1, .max = 3 },
 212         .m = { .min = 104, .max = 138 },
 213         .m1 = { .min = 17, .max = 23 },
 214         .m2 = { .min = 5, .max = 11 },
 215         .p = { .min = 14, .max = 42 },
 216         .p1 = { .min = 2, .max = 6 },
 217         .p2 = { .dot_limit = 0,
 218                 .p2_slow = 7, .p2_fast = 7
 219         },
 220         .find_pll = intel_g4x_find_best_PLL,
 221 };
 222
 223 static const intel_limit_t intel_limits_g4x_display_port = {
 224         .dot = { .min = 161670, .max = 227000 },
 225         .vco = { .min = 1750000, .max = 3500000},
 226         .n = { .min = 1, .max = 2 },
 227         .m = { .min = 97, .max = 108 },
 228         .m1 = { .min = 0x10, .max = 0x12 },
 229         .m2 = { .min = 0x05, .max = 0x06 },
 230         .p = { .min = 10, .max = 20 },
 231         .p1 = { .min = 1, .max = 2},
 232         .p2 = { .dot_limit = 0,
 233                 .p2_slow = 10, .p2_fast = 10 },
 234         .find_pll = intel_find_pll_g4x_dp,
 235 };
 236
 237 static const intel_limit_t intel_limits_pineview_sdvo = {
 238         .dot = { .min = 20000, .max = 400000},
 239         .vco = { .min = 1700000, .max = 3500000 },
 240         /* Pineview's Ncounter is a ring counter */
 241         .n = { .min = 3, .max = 6 },
 242         .m = { .min = 2, .max = 256 },
 243         /* Pineview only has one combined m divider, which we treat as m2. */
 244         .m1 = { .min = 0, .max = 0 },
 245         .m2 = { .min = 0, .max = 254 },
 246         .p = { .min = 5, .max = 80 },
 247         .p1 = { .min = 1, .max = 8 },
 248         .p2 = { .dot_limit = 200000,
 249                 .p2_slow = 10, .p2_fast = 5 },
 250         .find_pll = intel_find_best_PLL,
 251 };
 252
 253 static const intel_limit_t intel_limits_pineview_lvds = {
 254         .dot = { .min = 20000, .max = 400000 },
 255         .vco = { .min = 1700000, .max = 3500000 },
 256         .n = { .min = 3, .max = 6 },
 257         .m = { .min = 2, .max = 256 },
 258         .m1 = { .min = 0, .max = 0 },
 259         .m2 = { .min = 0, .max = 254 },
 260         .p = { .min = 7, .max = 112 },
 261         .p1 = { .min = 1, .max = 8 },
 262         .p2 = { .dot_limit = 112000,
 263                 .p2_slow = 14, .p2_fast = 14 },
 264         .find_pll = intel_find_best_PLL,
 265 };
 266
 267 /* Ironlake / Sandybridge
 268  *
 269  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 270  * the range value for them is (actual_value - 2).
 271  */
 272 static const intel_limit_t intel_limits_ironlake_dac = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 5 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283         .find_pll = intel_g4x_find_best_PLL,
 284 };
 285
 286 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 3 },
 290         .m = { .min = 79, .max = 118 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297         .find_pll = intel_g4x_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 56 },
 308         .p1 = { .min = 2, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311         .find_pll = intel_g4x_find_best_PLL,
 312 };
 313
 314 /* LVDS 100mhz refclk limits. */
 315 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 316         .dot = { .min = 25000, .max = 350000 },
 317         .vco = { .min = 1760000, .max = 3510000 },
 318         .n = { .min = 1, .max = 2 },
 319         .m = { .min = 79, .max = 126 },
 320         .m1 = { .min = 12, .max = 22 },
 321         .m2 = { .min = 5, .max = 9 },
 322         .p = { .min = 28, .max = 112 },
 323         .p1 = { .min = 2,.max = 8 },
 324         .p2 = { .dot_limit = 225000,
 325                 .p2_slow = 14, .p2_fast = 14 },
 326         .find_pll = intel_g4x_find_best_PLL,
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 126 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 42 },
 337         .p1 = { .min = 2,.max = 6 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340         .find_pll = intel_g4x_find_best_PLL,
 341 };
 342
 343 static const intel_limit_t intel_limits_ironlake_display_port = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000},
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 81, .max = 90 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 10, .max = 20 },
 351         .p1 = { .min = 1, .max = 2},
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 10, .p2_fast = 10 },
 354         .find_pll = intel_find_pll_ironlake_dp,
 355 };
 356
 357 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 358                                                 int refclk)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         const intel_limit_t *limit;
 363
 364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 365                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 366                     LVDS_CLKB_POWER_UP) {
 367                         /* LVDS dual channel */
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_dual_lvds;
 372                 } else {
 373                         if (refclk == 100000)
 374                                 limit = &intel_limits_ironlake_single_lvds_100m;
 375                         else
 376                                 limit = &intel_limits_ironlake_single_lvds;
 377                 }
 378         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 379                         HAS_eDP)
 380                 limit = &intel_limits_ironlake_display_port;
 381         else
 382                 limit = &intel_limits_ironlake_dac;
 383
 384         return limit;
 385 }
 386
 387 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 388 {
 389         struct drm_device *dev = crtc->dev;
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         const intel_limit_t *limit;
 392
 393         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 394                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 395                     LVDS_CLKB_POWER_UP)
 396                         /* LVDS with dual channel */
 397                         limit = &intel_limits_g4x_dual_channel_lvds;
 398                 else
 399                         /* LVDS with dual channel */
 400                         limit = &intel_limits_g4x_single_channel_lvds;
 401         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 402                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 403                 limit = &intel_limits_g4x_hdmi;
 404         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 405                 limit = &intel_limits_g4x_sdvo;
 406         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 407                 limit = &intel_limits_g4x_display_port;
 408         } else /* The option is for other outputs */
 409                 limit = &intel_limits_i9xx_sdvo;
 410
 411         return limit;
 412 }
 413
 414 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         const intel_limit_t *limit;
 418
 419         if (HAS_PCH_SPLIT(dev))
 420                 limit = intel_ironlake_limit(crtc, refclk);
 421         else if (IS_G4X(dev)) {
 422                 limit = intel_g4x_limit(crtc);
 423         } else if (IS_PINEVIEW(dev)) {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_pineview_lvds;
 426                 else
 427                         limit = &intel_limits_pineview_sdvo;
 428         } else if (!IS_GEN2(dev)) {
 429                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 430                         limit = &intel_limits_i9xx_lvds;
 431                 else
 432                         limit = &intel_limits_i9xx_sdvo;
 433         } else {
 434                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 435                         limit = &intel_limits_i8xx_lvds;
 436                 else
 437                         limit = &intel_limits_i8xx_dvo;
 438         }
 439         return limit;
 440 }
 441
 442 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 443 static void pineview_clock(int refclk, intel_clock_t *clock)
 444 {
 445         clock->m = clock->m2 + 2;
 446         clock->p = clock->p1 * clock->p2;
 447         clock->vco = refclk * clock->m / clock->n;
 448         clock->dot = clock->vco / clock->p;
 449 }
 450
 451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 452 {
 453         if (IS_PINEVIEW(dev)) {
 454                 pineview_clock(refclk, clock);
 455                 return;
 456         }
 457         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 458         clock->p = clock->p1 * clock->p2;
 459         clock->vco = refclk * clock->m / (clock->n + 2);
 460         clock->dot = clock->vco / clock->p;
 461 }
 462
 463 /**
 464  * Returns whether any output on the specified pipe is of the specified type
 465  */
 466 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         struct drm_mode_config *mode_config = &dev->mode_config;
 470         struct intel_encoder *encoder;
 471
 472         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 473                 if (encoder->base.crtc == crtc && encoder->type == type)
 474                         return true;
 475
 476         return false;
 477 }
 478
 479 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 480 /**
 481  * Returns whether the given set of divisors are valid for a given refclk with
 482  * the given connectors.
 483  */
 484
 485 static bool intel_PLL_is_valid(struct drm_device *dev,
 486                                const intel_limit_t *limit,
 487                                const intel_clock_t *clock)
 488 {
 489         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 490                 INTELPllInvalid ("p1 out of range\n");
 491         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 492                 INTELPllInvalid ("p out of range\n");
 493         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 494                 INTELPllInvalid ("m2 out of range\n");
 495         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 496                 INTELPllInvalid ("m1 out of range\n");
 497         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 498                 INTELPllInvalid ("m1 <= m2\n");
 499         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 500                 INTELPllInvalid ("m out of range\n");
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid ("n out of range\n");
 503         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 504                 INTELPllInvalid ("vco out of range\n");
 505         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 506          * connector, etc., rather than just a single range.
 507          */
 508         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 509                 INTELPllInvalid ("dot out of range\n");
 510
 511         return true;
 512 }
 513
 514 static bool
 515 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 516                     int target, int refclk, intel_clock_t *best_clock)
 517
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         intel_clock_t clock;
 522         int err = target;
 523
 524         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 525             (I915_READ(LVDS)) != 0) {
 526                 /*
 527                  * For LVDS, if the panel is on, just rely on its current
 528                  * settings for dual-channel.  We haven't figured out how to
 529                  * reliably set up different single/dual channel state, if we
 530                  * even can.
 531                  */
 532                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 533                     LVDS_CLKB_POWER_UP)
 534                         clock.p2 = limit->p2.p2_fast;
 535                 else
 536                         clock.p2 = limit->p2.p2_slow;
 537         } else {
 538                 if (target < limit->p2.dot_limit)
 539                         clock.p2 = limit->p2.p2_slow;
 540                 else
 541                         clock.p2 = limit->p2.p2_fast;
 542         }
 543
 544         memset (best_clock, 0, sizeof (*best_clock));
 545
 546         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 547              clock.m1++) {
 548                 for (clock.m2 = limit->m2.min;
 549                      clock.m2 <= limit->m2.max; clock.m2++) {
 550                         /* m1 is always 0 in Pineview */
 551                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 552                                 break;
 553                         for (clock.n = limit->n.min;
 554                              clock.n <= limit->n.max; clock.n++) {
 555                                 for (clock.p1 = limit->p1.min;
 556                                         clock.p1 <= limit->p1.max; clock.p1++) {
 557                                         int this_err;
 558
 559                                         intel_clock(dev, refclk, &clock);
 560                                         if (!intel_PLL_is_valid(dev, limit,
 561                                                                 &clock))
 562                                                 continue;
 563
 564                                         this_err = abs(clock.dot - target);
 565                                         if (this_err < err) {
 566                                                 *best_clock = clock;
 567                                                 err = this_err;
 568                                         }
 569                                 }
 570                         }
 571                 }
 572         }
 573
 574         return (err != target);
 575 }
 576
 577 static bool
 578 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                         int target, int refclk, intel_clock_t *best_clock)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct drm_i915_private *dev_priv = dev->dev_private;
 583         intel_clock_t clock;
 584         int max_n;
 585         bool found;
 586         /* approximately equals target * 0.00585 */
 587         int err_most = (target >> 8) + (target >> 9);
 588         found = false;
 589
 590         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 591                 int lvds_reg;
 592
 593                 if (HAS_PCH_SPLIT(dev))
 594                         lvds_reg = PCH_LVDS;
 595                 else
 596                         lvds_reg = LVDS;
 597                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 598                     LVDS_CLKB_POWER_UP)
 599                         clock.p2 = limit->p2.p2_fast;
 600                 else
 601                         clock.p2 = limit->p2.p2_slow;
 602         } else {
 603                 if (target < limit->p2.dot_limit)
 604                         clock.p2 = limit->p2.p2_slow;
 605                 else
 606                         clock.p2 = limit->p2.p2_fast;
 607         }
 608
 609         memset(best_clock, 0, sizeof(*best_clock));
 610         max_n = limit->n.max;
 611         /* based on hardware requirement, prefer smaller n to precision */
 612         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 613                 /* based on hardware requirement, prefere larger m1,m2 */
 614                 for (clock.m1 = limit->m1.max;
 615                      clock.m1 >= limit->m1.min; clock.m1--) {
 616                         for (clock.m2 = limit->m2.max;
 617                              clock.m2 >= limit->m2.min; clock.m2--) {
 618                                 for (clock.p1 = limit->p1.max;
 619                                      clock.p1 >= limit->p1.min; clock.p1--) {
 620                                         int this_err;
 621
 622                                         intel_clock(dev, refclk, &clock);
 623                                         if (!intel_PLL_is_valid(dev, limit,
 624                                                                 &clock))
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err_most) {
 629                                                 *best_clock = clock;
 630                                                 err_most = this_err;
 631                                                 max_n = clock.n;
 632                                                 found = true;
 633                                         }
 634                                 }
 635                         }
 636                 }
 637         }
 638         return found;
 639 }
 640
 641 static bool
 642 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                            int target, int refclk, intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647
 648         if (target < 200000) {
 649                 clock.n = 1;
 650                 clock.p1 = 2;
 651                 clock.p2 = 10;
 652                 clock.m1 = 12;
 653                 clock.m2 = 9;
 654         } else {
 655                 clock.n = 2;
 656                 clock.p1 = 1;
 657                 clock.p2 = 10;
 658                 clock.m1 = 14;
 659                 clock.m2 = 8;
 660         }
 661         intel_clock(dev, refclk, &clock);
 662         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 663         return true;
 664 }
 665
 666 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 667 static bool
 668 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                       int target, int refclk, intel_clock_t *best_clock)
 670 {
 671         intel_clock_t clock;
 672         if (target < 200000) {
 673                 clock.p1 = 2;
 674                 clock.p2 = 10;
 675                 clock.n = 2;
 676                 clock.m1 = 23;
 677                 clock.m2 = 8;
 678         } else {
 679                 clock.p1 = 1;
 680                 clock.p2 = 10;
 681                 clock.n = 1;
 682                 clock.m1 = 14;
 683                 clock.m2 = 2;
 684         }
 685         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 686         clock.p = (clock.p1 * clock.p2);
 687         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 688         clock.vco = 0;
 689         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 690         return true;
 691 }
 692
 693 /**
 694  * intel_wait_for_vblank - wait for vblank on a given pipe
 695  * @dev: drm device
 696  * @pipe: pipe to wait for
 697  *
 698  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 699  * mode setting code.
 700  */
 701 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         int pipestat_reg = PIPESTAT(pipe);
 705
 706         /* Clear existing vblank status. Note this will clear any other
 707          * sticky status fields as well.
 708          *
 709          * This races with i915_driver_irq_handler() with the result
 710          * that either function could miss a vblank event.  Here it is not
 711          * fatal, as we will either wait upon the next vblank interrupt or
 712          * timeout.  Generally speaking intel_wait_for_vblank() is only
 713          * called during modeset at which time the GPU should be idle and
 714          * should *not* be performing page flips and thus not waiting on
 715          * vblanks...
 716          * Currently, the result of us stealing a vblank from the irq
 717          * handler is that a single frame will be skipped during swapbuffers.
 718          */
 719         I915_WRITE(pipestat_reg,
 720                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 721
 722         /* Wait for vblank interrupt bit to set */
 723         if (wait_for(I915_READ(pipestat_reg) &
 724                      PIPE_VBLANK_INTERRUPT_STATUS,
 725                      50))
 726                 DRM_DEBUG_KMS("vblank wait timed out\n");
 727 }
 728
 729 /*
 730  * intel_wait_for_pipe_off - wait for pipe to turn off
 731  * @dev: drm device
 732  * @pipe: pipe to wait for
 733  *
 734  * After disabling a pipe, we can't wait for vblank in the usual way,
 735  * spinning on the vblank interrupt status bit, since we won't actually
 736  * see an interrupt when the pipe is disabled.
 737  *
 738  * On Gen4 and above:
 739  *   wait for the pipe register state bit to turn off
 740  *
 741  * Otherwise:
 742  *   wait for the display line value to settle (it usually
 743  *   ends up stopping at the start of the next frame).
 744  *
 745  */
 746 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 747 {
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749
 750         if (INTEL_INFO(dev)->gen >= 4) {
 751                 int reg = PIPECONF(pipe);
 752
 753                 /* Wait for the Pipe State to go off */
 754                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 755                              100))
 756                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 757         } else {
 758                 u32 last_line;
 759                 int reg = PIPEDSL(pipe);
 760                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 761
 762                 /* Wait for the display line to settle */
 763                 do {
 764                         last_line = I915_READ(reg) & DSL_LINEMASK;
 765                         mdelay(5);
 766                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 767                          time_after(timeout, jiffies));
 768                 if (time_after(jiffies, timeout))
 769                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 770         }
 771 }
 772
 773 static const char *state_string(bool enabled)
 774 {
 775         return enabled ? "on" : "off";
 776 }
 777
 778 /* Only for pre-ILK configs */
 779 static void assert_pll(struct drm_i915_private *dev_priv,
 780                        enum pipe pipe, bool state)
 781 {
 782         int reg;
 783         u32 val;
 784         bool cur_state;
 785
 786         reg = DPLL(pipe);
 787         val = I915_READ(reg);
 788         cur_state = !!(val & DPLL_VCO_ENABLE);
 789         WARN(cur_state != state,
 790              "PLL state assertion failure (expected %s, current %s)\n",
 791              state_string(state), state_string(cur_state));
 792 }
 793 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 794 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 795
 796 /* For ILK+ */
 797 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 798                            enum pipe pipe, bool state)
 799 {
 800         int reg;
 801         u32 val;
 802         bool cur_state;
 803
 804         reg = PCH_DPLL(pipe);
 805         val = I915_READ(reg);
 806         cur_state = !!(val & DPLL_VCO_ENABLE);
 807         WARN(cur_state != state,
 808              "PCH PLL state assertion failure (expected %s, current %s)\n",
 809              state_string(state), state_string(cur_state));
 810 }
 811 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 812 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 813
 814 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 815                           enum pipe pipe, bool state)
 816 {
 817         int reg;
 818         u32 val;
 819         bool cur_state;
 820
 821         reg = FDI_TX_CTL(pipe);
 822         val = I915_READ(reg);
 823         cur_state = !!(val & FDI_TX_ENABLE);
 824         WARN(cur_state != state,
 825              "FDI TX state assertion failure (expected %s, current %s)\n",
 826              state_string(state), state_string(cur_state));
 827 }
 828 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 829 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 830
 831 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 832                           enum pipe pipe, bool state)
 833 {
 834         int reg;
 835         u32 val;
 836         bool cur_state;
 837
 838         reg = FDI_RX_CTL(pipe);
 839         val = I915_READ(reg);
 840         cur_state = !!(val & FDI_RX_ENABLE);
 841         WARN(cur_state != state,
 842              "FDI RX state assertion failure (expected %s, current %s)\n",
 843              state_string(state), state_string(cur_state));
 844 }
 845 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 846 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 847
 848 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 849                                       enum pipe pipe)
 850 {
 851         int reg;
 852         u32 val;
 853
 854         /* ILK FDI PLL is always enabled */
 855         if (dev_priv->info->gen == 5)
 856                 return;
 857
 858         reg = FDI_TX_CTL(pipe);
 859         val = I915_READ(reg);
 860         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 861 }
 862
 863 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         reg = FDI_RX_CTL(pipe);
 870         val = I915_READ(reg);
 871         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 872 }
 873
 874 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 875                                   enum pipe pipe)
 876 {
 877         int pp_reg, lvds_reg;
 878         u32 val;
 879         enum pipe panel_pipe = PIPE_A;
 880         bool locked = locked;
 881
 882         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 883                 pp_reg = PCH_PP_CONTROL;
 884                 lvds_reg = PCH_LVDS;
 885         } else {
 886                 pp_reg = PP_CONTROL;
 887                 lvds_reg = LVDS;
 888         }
 889
 890         val = I915_READ(pp_reg);
 891         if (!(val & PANEL_POWER_ON) ||
 892             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 893                 locked = false;
 894
 895         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 896                 panel_pipe = PIPE_B;
 897
 898         WARN(panel_pipe == pipe && locked,
 899              "panel assertion failure, pipe %c regs locked\n",
 900              pipe_name(pipe));
 901 }
 902
 903 static void assert_pipe(struct drm_i915_private *dev_priv,
 904                         enum pipe pipe, bool state)
 905 {
 906         int reg;
 907         u32 val;
 908         bool cur_state;
 909
 910         reg = PIPECONF(pipe);
 911         val = I915_READ(reg);
 912         cur_state = !!(val & PIPECONF_ENABLE);
 913         WARN(cur_state != state,
 914              "pipe %c assertion failure (expected %s, current %s)\n",
 915              pipe_name(pipe), state_string(state), state_string(cur_state));
 916 }
 917 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 918 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 919
 920 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 921                                  enum plane plane)
 922 {
 923         int reg;
 924         u32 val;
 925
 926         reg = DSPCNTR(plane);
 927         val = I915_READ(reg);
 928         WARN(!(val & DISPLAY_PLANE_ENABLE),
 929              "plane %c assertion failure, should be active but is disabled\n",
 930              plane_name(plane));
 931 }
 932
 933 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 934                                    enum pipe pipe)
 935 {
 936         int reg, i;
 937         u32 val;
 938         int cur_pipe;
 939
 940         /* Planes are fixed to pipes on ILK+ */
 941         if (HAS_PCH_SPLIT(dev_priv->dev))
 942                 return;
 943
 944         /* Need to check both planes against the pipe */
 945         for (i = 0; i < 2; i++) {
 946                 reg = DSPCNTR(i);
 947                 val = I915_READ(reg);
 948                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 949                         DISPPLANE_SEL_PIPE_SHIFT;
 950                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 951                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 952                      plane_name(i), pipe_name(pipe));
 953         }
 954 }
 955
 956 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 957 {
 958         u32 val;
 959         bool enabled;
 960
 961         val = I915_READ(PCH_DREF_CONTROL);
 962         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 963                             DREF_SUPERSPREAD_SOURCE_MASK));
 964         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 965 }
 966
 967 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 968                                        enum pipe pipe)
 969 {
 970         int reg;
 971         u32 val;
 972         bool enabled;
 973
 974         reg = TRANSCONF(pipe);
 975         val = I915_READ(reg);
 976         enabled = !!(val & TRANS_ENABLE);
 977         WARN(enabled,
 978              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 979              pipe_name(pipe));
 980 }
 981
 982 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
 983                             int reg, u32 port_sel, u32 val)
 984 {
 985         if ((val & DP_PORT_EN) == 0)
 986                 return false;
 987
 988         if (HAS_PCH_CPT(dev_priv->dev)) {
 989                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
 990                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 991                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 992                         return false;
 993         } else {
 994                 if ((val & DP_PIPE_MASK) != (pipe << 30))
 995                         return false;
 996         }
 997         return true;
 998 }
 999
1000 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1001                                    enum pipe pipe, int reg, u32 port_sel)
1002 {
1003         u32 val = I915_READ(reg);
1004         WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
1005              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1006              reg, pipe_name(pipe));
1007 }
1008
1009 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1010                                      enum pipe pipe, int reg)
1011 {
1012         u32 val = I915_READ(reg);
1013         WARN(HDMI_PIPE_ENABLED(val, pipe),
1014              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1015              reg, pipe_name(pipe));
1016 }
1017
1018 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1019                                       enum pipe pipe)
1020 {
1021         int reg;
1022         u32 val;
1023
1024         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1025         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1026         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1027
1028         reg = PCH_ADPA;
1029         val = I915_READ(reg);
1030         WARN(ADPA_PIPE_ENABLED(val, pipe),
1031              "PCH VGA enabled on transcoder %c, should be disabled\n",
1032              pipe_name(pipe));
1033
1034         reg = PCH_LVDS;
1035         val = I915_READ(reg);
1036         WARN(LVDS_PIPE_ENABLED(val, pipe),
1037              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1038              pipe_name(pipe));
1039
1040         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1041         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1042         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1043 }
1044
1045 /**
1046  * intel_enable_pll - enable a PLL
1047  * @dev_priv: i915 private structure
1048  * @pipe: pipe PLL to enable
1049  *
1050  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1051  * make sure the PLL reg is writable first though, since the panel write
1052  * protect mechanism may be enabled.
1053  *
1054  * Note!  This is for pre-ILK only.
1055  */
1056 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1057 {
1058         int reg;
1059         u32 val;
1060
1061         /* No really, not for ILK+ */
1062         BUG_ON(dev_priv->info->gen >= 5);
1063
1064         /* PLL is protected by panel, make sure we can write it */
1065         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1066                 assert_panel_unlocked(dev_priv, pipe);
1067
1068         reg = DPLL(pipe);
1069         val = I915_READ(reg);
1070         val |= DPLL_VCO_ENABLE;
1071
1072         /* We do this three times for luck */
1073         I915_WRITE(reg, val);
1074         POSTING_READ(reg);
1075         udelay(150); /* wait for warmup */
1076         I915_WRITE(reg, val);
1077         POSTING_READ(reg);
1078         udelay(150); /* wait for warmup */
1079         I915_WRITE(reg, val);
1080         POSTING_READ(reg);
1081         udelay(150); /* wait for warmup */
1082 }
1083
1084 /**
1085  * intel_disable_pll - disable a PLL
1086  * @dev_priv: i915 private structure
1087  * @pipe: pipe PLL to disable
1088  *
1089  * Disable the PLL for @pipe, making sure the pipe is off first.
1090  *
1091  * Note!  This is for pre-ILK only.
1092  */
1093 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1094 {
1095         int reg;
1096         u32 val;
1097
1098         /* Don't disable pipe A or pipe A PLLs if needed */
1099         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1100                 return;
1101
1102         /* Make sure the pipe isn't still relying on us */
1103         assert_pipe_disabled(dev_priv, pipe);
1104
1105         reg = DPLL(pipe);
1106         val = I915_READ(reg);
1107         val &= ~DPLL_VCO_ENABLE;
1108         I915_WRITE(reg, val);
1109         POSTING_READ(reg);
1110 }
1111
1112 /**
1113  * intel_enable_pch_pll - enable PCH PLL
1114  * @dev_priv: i915 private structure
1115  * @pipe: pipe PLL to enable
1116  *
1117  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1118  * drives the transcoder clock.
1119  */
1120 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1121                                  enum pipe pipe)
1122 {
1123         int reg;
1124         u32 val;
1125
1126         /* PCH only available on ILK+ */
1127         BUG_ON(dev_priv->info->gen < 5);
1128
1129         /* PCH refclock must be enabled first */
1130         assert_pch_refclk_enabled(dev_priv);
1131
1132         reg = PCH_DPLL(pipe);
1133         val = I915_READ(reg);
1134         val |= DPLL_VCO_ENABLE;
1135         I915_WRITE(reg, val);
1136         POSTING_READ(reg);
1137         udelay(200);
1138 }
1139
1140 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1141                                   enum pipe pipe)
1142 {
1143         int reg;
1144         u32 val;
1145
1146         /* PCH only available on ILK+ */
1147         BUG_ON(dev_priv->info->gen < 5);
1148
1149         /* Make sure transcoder isn't still depending on us */
1150         assert_transcoder_disabled(dev_priv, pipe);
1151
1152         reg = PCH_DPLL(pipe);
1153         val = I915_READ(reg);
1154         val &= ~DPLL_VCO_ENABLE;
1155         I915_WRITE(reg, val);
1156         POSTING_READ(reg);
1157         udelay(200);
1158 }
1159
1160 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1161                                     enum pipe pipe)
1162 {
1163         int reg;
1164         u32 val;
1165
1166         /* PCH only available on ILK+ */
1167         BUG_ON(dev_priv->info->gen < 5);
1168
1169         /* Make sure PCH DPLL is enabled */
1170         assert_pch_pll_enabled(dev_priv, pipe);
1171
1172         /* FDI must be feeding us bits for PCH ports */
1173         assert_fdi_tx_enabled(dev_priv, pipe);
1174         assert_fdi_rx_enabled(dev_priv, pipe);
1175
1176         reg = TRANSCONF(pipe);
1177         val = I915_READ(reg);
1178         /*
1179          * make the BPC in transcoder be consistent with
1180          * that in pipeconf reg.
1181          */
1182         val &= ~PIPE_BPC_MASK;
1183         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1184         I915_WRITE(reg, val | TRANS_ENABLE);
1185         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1186                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1187 }
1188
1189 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1190                                      enum pipe pipe)
1191 {
1192         int reg;
1193         u32 val;
1194
1195         /* FDI relies on the transcoder */
1196         assert_fdi_tx_disabled(dev_priv, pipe);
1197         assert_fdi_rx_disabled(dev_priv, pipe);
1198
1199         /* Ports must be off as well */
1200         assert_pch_ports_disabled(dev_priv, pipe);
1201
1202         reg = TRANSCONF(pipe);
1203         val = I915_READ(reg);
1204         val &= ~TRANS_ENABLE;
1205         I915_WRITE(reg, val);
1206         /* wait for PCH transcoder off, transcoder state */
1207         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1208                 DRM_ERROR("failed to disable transcoder\n");
1209 }
1210
1211 /**
1212  * intel_enable_pipe - enable a pipe, asserting requirements
1213  * @dev_priv: i915 private structure
1214  * @pipe: pipe to enable
1215  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1216  *
1217  * Enable @pipe, making sure that various hardware specific requirements
1218  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1219  *
1220  * @pipe should be %PIPE_A or %PIPE_B.
1221  *
1222  * Will wait until the pipe is actually running (i.e. first vblank) before
1223  * returning.
1224  */
1225 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1226                               bool pch_port)
1227 {
1228         int reg;
1229         u32 val;
1230
1231         /*
1232          * A pipe without a PLL won't actually be able to drive bits from
1233          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1234          * need the check.
1235          */
1236         if (!HAS_PCH_SPLIT(dev_priv->dev))
1237                 assert_pll_enabled(dev_priv, pipe);
1238         else {
1239                 if (pch_port) {
1240                         /* if driving the PCH, we need FDI enabled */
1241                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1242                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1243                 }
1244                 /* FIXME: assert CPU port conditions for SNB+ */
1245         }
1246
1247         reg = PIPECONF(pipe);
1248         val = I915_READ(reg);
1249         if (val & PIPECONF_ENABLE)
1250                 return;
1251
1252         I915_WRITE(reg, val | PIPECONF_ENABLE);
1253         intel_wait_for_vblank(dev_priv->dev, pipe);
1254 }
1255
1256 /**
1257  * intel_disable_pipe - disable a pipe, asserting requirements
1258  * @dev_priv: i915 private structure
1259  * @pipe: pipe to disable
1260  *
1261  * Disable @pipe, making sure that various hardware specific requirements
1262  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1263  *
1264  * @pipe should be %PIPE_A or %PIPE_B.
1265  *
1266  * Will wait until the pipe has shut down before returning.
1267  */
1268 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1269                                enum pipe pipe)
1270 {
1271         int reg;
1272         u32 val;
1273
1274         /*
1275          * Make sure planes won't keep trying to pump pixels to us,
1276          * or we might hang the display.
1277          */
1278         assert_planes_disabled(dev_priv, pipe);
1279
1280         /* Don't disable pipe A or pipe A PLLs if needed */
1281         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1282                 return;
1283
1284         reg = PIPECONF(pipe);
1285         val = I915_READ(reg);
1286         if ((val & PIPECONF_ENABLE) == 0)
1287                 return;
1288
1289         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1290         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1291 }
1292
1293 /*
1294  * Plane regs are double buffered, going from enabled->disabled needs a
1295  * trigger in order to latch.  The display address reg provides this.
1296  */
1297 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1298                                       enum plane plane)
1299 {
1300         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1301         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1302 }
1303
1304 /**
1305  * intel_enable_plane - enable a display plane on a given pipe
1306  * @dev_priv: i915 private structure
1307  * @plane: plane to enable
1308  * @pipe: pipe being fed
1309  *
1310  * Enable @plane on @pipe, making sure that @pipe is running first.
1311  */
1312 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1313                                enum plane plane, enum pipe pipe)
1314 {
1315         int reg;
1316         u32 val;
1317
1318         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1319         assert_pipe_enabled(dev_priv, pipe);
1320
1321         reg = DSPCNTR(plane);
1322         val = I915_READ(reg);
1323         if (val & DISPLAY_PLANE_ENABLE)
1324                 return;
1325
1326         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1327         intel_flush_display_plane(dev_priv, plane);
1328         intel_wait_for_vblank(dev_priv->dev, pipe);
1329 }
1330
1331 /**
1332  * intel_disable_plane - disable a display plane
1333  * @dev_priv: i915 private structure
1334  * @plane: plane to disable
1335  * @pipe: pipe consuming the data
1336  *
1337  * Disable @plane; should be an independent operation.
1338  */
1339 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1340                                 enum plane plane, enum pipe pipe)
1341 {
1342         int reg;
1343         u32 val;
1344
1345         reg = DSPCNTR(plane);
1346         val = I915_READ(reg);
1347         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1348                 return;
1349
1350         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1351         intel_flush_display_plane(dev_priv, plane);
1352         intel_wait_for_vblank(dev_priv->dev, pipe);
1353 }
1354
1355 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1356                            enum pipe pipe, int reg, u32 port_sel)
1357 {
1358         u32 val = I915_READ(reg);
1359         if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1360                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1361                 I915_WRITE(reg, val & ~DP_PORT_EN);
1362         }
1363 }
1364
1365 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1366                              enum pipe pipe, int reg)
1367 {
1368         u32 val = I915_READ(reg);
1369         if (HDMI_PIPE_ENABLED(val, pipe)) {
1370                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1371                               reg, pipe);
1372                 I915_WRITE(reg, val & ~PORT_ENABLE);
1373         }
1374 }
1375
1376 /* Disable any ports connected to this transcoder */
1377 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1378                                     enum pipe pipe)
1379 {
1380         u32 reg, val;
1381
1382         val = I915_READ(PCH_PP_CONTROL);
1383         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1384
1385         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1386         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1387         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1388
1389         reg = PCH_ADPA;
1390         val = I915_READ(reg);
1391         if (ADPA_PIPE_ENABLED(val, pipe))
1392                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1393
1394         reg = PCH_LVDS;
1395         val = I915_READ(reg);
1396         if (LVDS_PIPE_ENABLED(val, pipe)) {
1397                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1398                 POSTING_READ(reg);
1399                 udelay(100);
1400         }
1401
1402         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1403         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1404         disable_pch_hdmi(dev_priv, pipe, HDMID);
1405 }
1406
1407 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1408 {
1409         struct drm_device *dev = crtc->dev;
1410         struct drm_i915_private *dev_priv = dev->dev_private;
1411         struct drm_framebuffer *fb = crtc->fb;
1412         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1413         struct drm_i915_gem_object *obj = intel_fb->obj;
1414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1415         int plane, i;
1416         u32 fbc_ctl, fbc_ctl2;
1417
1418         if (fb->pitch == dev_priv->cfb_pitch &&
1419             obj->fence_reg == dev_priv->cfb_fence &&
1420             intel_crtc->plane == dev_priv->cfb_plane &&
1421             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1422                 return;
1423
1424         i8xx_disable_fbc(dev);
1425
1426         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1427
1428         if (fb->pitch < dev_priv->cfb_pitch)
1429                 dev_priv->cfb_pitch = fb->pitch;
1430
1431         /* FBC_CTL wants 64B units */
1432         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1433         dev_priv->cfb_fence = obj->fence_reg;
1434         dev_priv->cfb_plane = intel_crtc->plane;
1435         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1436
1437         /* Clear old tags */
1438         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1439                 I915_WRITE(FBC_TAG + (i * 4), 0);
1440
1441         /* Set it up... */
1442         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1443         if (obj->tiling_mode != I915_TILING_NONE)
1444                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1445         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1446         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1447
1448         /* enable it... */
1449         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1450         if (IS_I945GM(dev))
1451                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1452         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1453         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1454         if (obj->tiling_mode != I915_TILING_NONE)
1455                 fbc_ctl |= dev_priv->cfb_fence;
1456         I915_WRITE(FBC_CONTROL, fbc_ctl);
1457
1458         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1459                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1460 }
1461
1462 void i8xx_disable_fbc(struct drm_device *dev)
1463 {
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465         u32 fbc_ctl;
1466
1467         /* Disable compression */
1468         fbc_ctl = I915_READ(FBC_CONTROL);
1469         if ((fbc_ctl & FBC_CTL_EN) == 0)
1470                 return;
1471
1472         fbc_ctl &= ~FBC_CTL_EN;
1473         I915_WRITE(FBC_CONTROL, fbc_ctl);
1474
1475         /* Wait for compressing bit to clear */
1476         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1477                 DRM_DEBUG_KMS("FBC idle timed out\n");
1478                 return;
1479         }
1480
1481         DRM_DEBUG_KMS("disabled FBC\n");
1482 }
1483
1484 static bool i8xx_fbc_enabled(struct drm_device *dev)
1485 {
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487
1488         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1489 }
1490
1491 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1492 {
1493         struct drm_device *dev = crtc->dev;
1494         struct drm_i915_private *dev_priv = dev->dev_private;
1495         struct drm_framebuffer *fb = crtc->fb;
1496         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1497         struct drm_i915_gem_object *obj = intel_fb->obj;
1498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1500         unsigned long stall_watermark = 200;
1501         u32 dpfc_ctl;
1502
1503         dpfc_ctl = I915_READ(DPFC_CONTROL);
1504         if (dpfc_ctl & DPFC_CTL_EN) {
1505                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1506                     dev_priv->cfb_fence == obj->fence_reg &&
1507                     dev_priv->cfb_plane == intel_crtc->plane &&
1508                     dev_priv->cfb_y == crtc->y)
1509                         return;
1510
1511                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1512                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1513         }
1514
1515         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1516         dev_priv->cfb_fence = obj->fence_reg;
1517         dev_priv->cfb_plane = intel_crtc->plane;
1518         dev_priv->cfb_y = crtc->y;
1519
1520         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1521         if (obj->tiling_mode != I915_TILING_NONE) {
1522                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1523                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1524         } else {
1525                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1526         }
1527
1528         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1529                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1530                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1531         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1532
1533         /* enable it... */
1534         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1535
1536         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1537 }
1538
1539 void g4x_disable_fbc(struct drm_device *dev)
1540 {
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         u32 dpfc_ctl;
1543
1544         /* Disable compression */
1545         dpfc_ctl = I915_READ(DPFC_CONTROL);
1546         if (dpfc_ctl & DPFC_CTL_EN) {
1547                 dpfc_ctl &= ~DPFC_CTL_EN;
1548                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1549
1550                 DRM_DEBUG_KMS("disabled FBC\n");
1551         }
1552 }
1553
1554 static bool g4x_fbc_enabled(struct drm_device *dev)
1555 {
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557
1558         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1559 }
1560
1561 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1562 {
1563         struct drm_i915_private *dev_priv = dev->dev_private;
1564         u32 blt_ecoskpd;
1565
1566         /* Make sure blitter notifies FBC of writes */
1567         gen6_gt_force_wake_get(dev_priv);
1568         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1569         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1570                 GEN6_BLITTER_LOCK_SHIFT;
1571         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1572         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1573         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1574         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1575                          GEN6_BLITTER_LOCK_SHIFT);
1576         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1577         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1578         gen6_gt_force_wake_put(dev_priv);
1579 }
1580
1581 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1582 {
1583         struct drm_device *dev = crtc->dev;
1584         struct drm_i915_private *dev_priv = dev->dev_private;
1585         struct drm_framebuffer *fb = crtc->fb;
1586         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1587         struct drm_i915_gem_object *obj = intel_fb->obj;
1588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1589         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1590         unsigned long stall_watermark = 200;
1591         u32 dpfc_ctl;
1592
1593         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1594         if (dpfc_ctl & DPFC_CTL_EN) {
1595                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1596                     dev_priv->cfb_fence == obj->fence_reg &&
1597                     dev_priv->cfb_plane == intel_crtc->plane &&
1598                     dev_priv->cfb_offset == obj->gtt_offset &&
1599                     dev_priv->cfb_y == crtc->y)
1600                         return;
1601
1602                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1603                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1604         }
1605
1606         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1607         dev_priv->cfb_fence = obj->fence_reg;
1608         dev_priv->cfb_plane = intel_crtc->plane;
1609         dev_priv->cfb_offset = obj->gtt_offset;
1610         dev_priv->cfb_y = crtc->y;
1611
1612         dpfc_ctl &= DPFC_RESERVED;
1613         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1614         if (obj->tiling_mode != I915_TILING_NONE) {
1615                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1616                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1617         } else {
1618                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1619         }
1620
1621         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1622                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1623                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1624         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1625         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1626         /* enable it... */
1627         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1628
1629         if (IS_GEN6(dev)) {
1630                 I915_WRITE(SNB_DPFC_CTL_SA,
1631                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1632                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1633                 sandybridge_blit_fbc_update(dev);
1634         }
1635
1636         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1637 }
1638
1639 void ironlake_disable_fbc(struct drm_device *dev)
1640 {
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642         u32 dpfc_ctl;
1643
1644         /* Disable compression */
1645         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1646         if (dpfc_ctl & DPFC_CTL_EN) {
1647                 dpfc_ctl &= ~DPFC_CTL_EN;
1648                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1649
1650                 DRM_DEBUG_KMS("disabled FBC\n");
1651         }
1652 }
1653
1654 static bool ironlake_fbc_enabled(struct drm_device *dev)
1655 {
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1659 }
1660
1661 bool intel_fbc_enabled(struct drm_device *dev)
1662 {
1663         struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665         if (!dev_priv->display.fbc_enabled)
1666                 return false;
1667
1668         return dev_priv->display.fbc_enabled(dev);
1669 }
1670
1671 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1672 {
1673         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1674
1675         if (!dev_priv->display.enable_fbc)
1676                 return;
1677
1678         dev_priv->display.enable_fbc(crtc, interval);
1679 }
1680
1681 void intel_disable_fbc(struct drm_device *dev)
1682 {
1683         struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685         if (!dev_priv->display.disable_fbc)
1686                 return;
1687
1688         dev_priv->display.disable_fbc(dev);
1689 }
1690
1691 /**
1692  * intel_update_fbc - enable/disable FBC as needed
1693  * @dev: the drm_device
1694  *
1695  * Set up the framebuffer compression hardware at mode set time.  We
1696  * enable it if possible:
1697  *   - plane A only (on pre-965)
1698  *   - no pixel mulitply/line duplication
1699  *   - no alpha buffer discard
1700  *   - no dual wide
1701  *   - framebuffer <= 2048 in width, 1536 in height
1702  *
1703  * We can't assume that any compression will take place (worst case),
1704  * so the compressed buffer has to be the same size as the uncompressed
1705  * one.  It also must reside (along with the line length buffer) in
1706  * stolen memory.
1707  *
1708  * We need to enable/disable FBC on a global basis.
1709  */
1710 static void intel_update_fbc(struct drm_device *dev)
1711 {
1712         struct drm_i915_private *dev_priv = dev->dev_private;
1713         struct drm_crtc *crtc = NULL, *tmp_crtc;
1714         struct intel_crtc *intel_crtc;
1715         struct drm_framebuffer *fb;
1716         struct intel_framebuffer *intel_fb;
1717         struct drm_i915_gem_object *obj;
1718
1719         DRM_DEBUG_KMS("\n");
1720
1721         if (!i915_powersave)
1722                 return;
1723
1724         if (!I915_HAS_FBC(dev))
1725                 return;
1726
1727         /*
1728          * If FBC is already on, we just have to verify that we can
1729          * keep it that way...
1730          * Need to disable if:
1731          *   - more than one pipe is active
1732          *   - changing FBC params (stride, fence, mode)
1733          *   - new fb is too large to fit in compressed buffer
1734          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1735          */
1736         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1737                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1738                         if (crtc) {
1739                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1740                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1741                                 goto out_disable;
1742                         }
1743                         crtc = tmp_crtc;
1744                 }
1745         }
1746
1747         if (!crtc || crtc->fb == NULL) {
1748                 DRM_DEBUG_KMS("no output, disabling\n");
1749                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1750                 goto out_disable;
1751         }
1752
1753         intel_crtc = to_intel_crtc(crtc);
1754         fb = crtc->fb;
1755         intel_fb = to_intel_framebuffer(fb);
1756         obj = intel_fb->obj;
1757
1758         if (!i915_enable_fbc) {
1759                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1760                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1761                 goto out_disable;
1762         }
1763         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1764                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1765                               "compression\n");
1766                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1767                 goto out_disable;
1768         }
1769         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1770             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1771                 DRM_DEBUG_KMS("mode incompatible with compression, "
1772                               "disabling\n");
1773                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1774                 goto out_disable;
1775         }
1776         if ((crtc->mode.hdisplay > 2048) ||
1777             (crtc->mode.vdisplay > 1536)) {
1778                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1779                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1780                 goto out_disable;
1781         }
1782         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1783                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1784                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1785                 goto out_disable;
1786         }
1787         if (obj->tiling_mode != I915_TILING_X) {
1788                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1789                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1790                 goto out_disable;
1791         }
1792
1793         /* If the kernel debugger is active, always disable compression */
1794         if (in_dbg_master())
1795                 goto out_disable;
1796
1797         intel_enable_fbc(crtc, 500);
1798         return;
1799
1800 out_disable:
1801         /* Multiple disables should be harmless */
1802         if (intel_fbc_enabled(dev)) {
1803                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1804                 intel_disable_fbc(dev);
1805         }
1806 }
1807
1808 int
1809 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1810                            struct drm_i915_gem_object *obj,
1811                            struct intel_ring_buffer *pipelined)
1812 {
1813         struct drm_i915_private *dev_priv = dev->dev_private;
1814         u32 alignment;
1815         int ret;
1816
1817         switch (obj->tiling_mode) {
1818         case I915_TILING_NONE:
1819                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1820                         alignment = 128 * 1024;
1821                 else if (INTEL_INFO(dev)->gen >= 4)
1822                         alignment = 4 * 1024;
1823                 else
1824                         alignment = 64 * 1024;
1825                 break;
1826         case I915_TILING_X:
1827                 /* pin() will align the object as required by fence */
1828                 alignment = 0;
1829                 break;
1830         case I915_TILING_Y:
1831                 /* FIXME: Is this true? */
1832                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1833                 return -EINVAL;
1834         default:
1835                 BUG();
1836         }
1837
1838         dev_priv->mm.interruptible = false;
1839         ret = i915_gem_object_pin(obj, alignment, true);
1840         if (ret)
1841                 goto err_interruptible;
1842
1843         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1844         if (ret)
1845                 goto err_unpin;
1846
1847         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1848          * fence, whereas 965+ only requires a fence if using
1849          * framebuffer compression.  For simplicity, we always install
1850          * a fence as the cost is not that onerous.
1851          */
1852         if (obj->tiling_mode != I915_TILING_NONE) {
1853                 ret = i915_gem_object_get_fence(obj, pipelined);
1854                 if (ret)
1855                         goto err_unpin;
1856         }
1857
1858         dev_priv->mm.interruptible = true;
1859         return 0;
1860
1861 err_unpin:
1862         i915_gem_object_unpin(obj);
1863 err_interruptible:
1864         dev_priv->mm.interruptible = true;
1865         return ret;
1866 }
1867
1868 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1869 static int
1870 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1871                            int x, int y, enum mode_set_atomic state)
1872 {
1873         struct drm_device *dev = crtc->dev;
1874         struct drm_i915_private *dev_priv = dev->dev_private;
1875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1876         struct intel_framebuffer *intel_fb;
1877         struct drm_i915_gem_object *obj;
1878         int plane = intel_crtc->plane;
1879         unsigned long Start, Offset;
1880         u32 dspcntr;
1881         u32 reg;
1882
1883         switch (plane) {
1884         case 0:
1885         case 1:
1886                 break;
1887         default:
1888                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1889                 return -EINVAL;
1890         }
1891
1892         intel_fb = to_intel_framebuffer(fb);
1893         obj = intel_fb->obj;
1894
1895         reg = DSPCNTR(plane);
1896         dspcntr = I915_READ(reg);
1897         /* Mask out pixel format bits in case we change it */
1898         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1899         switch (fb->bits_per_pixel) {
1900         case 8:
1901                 dspcntr |= DISPPLANE_8BPP;
1902                 break;
1903         case 16:
1904                 if (fb->depth == 15)
1905                         dspcntr |= DISPPLANE_15_16BPP;
1906                 else
1907                         dspcntr |= DISPPLANE_16BPP;
1908                 break;
1909         case 24:
1910         case 32:
1911                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1912                 break;
1913         default:
1914                 DRM_ERROR("Unknown color depth\n");
1915                 return -EINVAL;
1916         }
1917         if (INTEL_INFO(dev)->gen >= 4) {
1918                 if (obj->tiling_mode != I915_TILING_NONE)
1919                         dspcntr |= DISPPLANE_TILED;
1920                 else
1921                         dspcntr &= ~DISPPLANE_TILED;
1922         }
1923
1924         if (HAS_PCH_SPLIT(dev))
1925                 /* must disable */
1926                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1927
1928         I915_WRITE(reg, dspcntr);
1929
1930         Start = obj->gtt_offset;
1931         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1932
1933         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1934                       Start, Offset, x, y, fb->pitch);
1935         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1936         if (INTEL_INFO(dev)->gen >= 4) {
1937                 I915_WRITE(DSPSURF(plane), Start);
1938                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1939                 I915_WRITE(DSPADDR(plane), Offset);
1940         } else
1941                 I915_WRITE(DSPADDR(plane), Start + Offset);
1942         POSTING_READ(reg);
1943
1944         intel_update_fbc(dev);
1945         intel_increase_pllclock(crtc);
1946
1947         return 0;
1948 }
1949
1950 static int
1951 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1952                     struct drm_framebuffer *old_fb)
1953 {
1954         struct drm_device *dev = crtc->dev;
1955         struct drm_i915_master_private *master_priv;
1956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1957         int ret;
1958
1959         /* no fb bound */
1960         if (!crtc->fb) {
1961                 DRM_ERROR("No FB bound\n");
1962                 return 0;
1963         }
1964
1965         switch (intel_crtc->plane) {
1966         case 0:
1967         case 1:
1968                 break;
1969         default:
1970                 DRM_ERROR("no plane for crtc\n");
1971                 return -EINVAL;
1972         }
1973
1974         mutex_lock(&dev->struct_mutex);
1975         ret = intel_pin_and_fence_fb_obj(dev,
1976                                          to_intel_framebuffer(crtc->fb)->obj,
1977                                          NULL);
1978         if (ret != 0) {
1979                 mutex_unlock(&dev->struct_mutex);
1980                 DRM_ERROR("pin & fence failed\n");
1981                 return ret;
1982         }
1983
1984         if (old_fb) {
1985                 struct drm_i915_private *dev_priv = dev->dev_private;
1986                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1987
1988                 wait_event(dev_priv->pending_flip_queue,
1989                            atomic_read(&dev_priv->mm.wedged) ||
1990                            atomic_read(&obj->pending_flip) == 0);
1991
1992                 /* Big Hammer, we also need to ensure that any pending
1993                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1994                  * current scanout is retired before unpinning the old
1995                  * framebuffer.
1996                  *
1997                  * This should only fail upon a hung GPU, in which case we
1998                  * can safely continue.
1999                  */
2000                 ret = i915_gem_object_flush_gpu(obj);
2001                 (void) ret;
2002         }
2003
2004         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2005                                          LEAVE_ATOMIC_MODE_SET);
2006         if (ret) {
2007                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2008                 mutex_unlock(&dev->struct_mutex);
2009                 DRM_ERROR("failed to update base address\n");
2010                 return ret;
2011         }
2012
2013         if (old_fb) {
2014                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2015                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2016         }
2017
2018         mutex_unlock(&dev->struct_mutex);
2019
2020         if (!dev->primary->master)
2021                 return 0;
2022
2023         master_priv = dev->primary->master->driver_priv;
2024         if (!master_priv->sarea_priv)
2025                 return 0;
2026
2027         if (intel_crtc->pipe) {
2028                 master_priv->sarea_priv->pipeB_x = x;
2029                 master_priv->sarea_priv->pipeB_y = y;
2030         } else {
2031                 master_priv->sarea_priv->pipeA_x = x;
2032                 master_priv->sarea_priv->pipeA_y = y;
2033         }
2034
2035         return 0;
2036 }
2037
2038 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2039 {
2040         struct drm_device *dev = crtc->dev;
2041         struct drm_i915_private *dev_priv = dev->dev_private;
2042         u32 dpa_ctl;
2043
2044         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2045         dpa_ctl = I915_READ(DP_A);
2046         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2047
2048         if (clock < 200000) {
2049                 u32 temp;
2050                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2051                 /* workaround for 160Mhz:
2052                    1) program 0x4600c bits 15:0 = 0x8124
2053                    2) program 0x46010 bit 0 = 1
2054                    3) program 0x46034 bit 24 = 1
2055                    4) program 0x64000 bit 14 = 1
2056                    */
2057                 temp = I915_READ(0x4600c);
2058                 temp &= 0xffff0000;
2059                 I915_WRITE(0x4600c, temp | 0x8124);
2060
2061                 temp = I915_READ(0x46010);
2062                 I915_WRITE(0x46010, temp | 1);
2063
2064                 temp = I915_READ(0x46034);
2065                 I915_WRITE(0x46034, temp | (1 << 24));
2066         } else {
2067                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2068         }
2069         I915_WRITE(DP_A, dpa_ctl);
2070
2071         POSTING_READ(DP_A);
2072         udelay(500);
2073 }
2074
2075 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2076 {
2077         struct drm_device *dev = crtc->dev;
2078         struct drm_i915_private *dev_priv = dev->dev_private;
2079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080         int pipe = intel_crtc->pipe;
2081         u32 reg, temp;
2082
2083         /* enable normal train */
2084         reg = FDI_TX_CTL(pipe);
2085         temp = I915_READ(reg);
2086         if (IS_IVYBRIDGE(dev)) {
2087                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2088                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2089         } else {
2090                 temp &= ~FDI_LINK_TRAIN_NONE;
2091                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2092         }
2093         I915_WRITE(reg, temp);
2094
2095         reg = FDI_RX_CTL(pipe);
2096         temp = I915_READ(reg);
2097         if (HAS_PCH_CPT(dev)) {
2098                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2099                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2100         } else {
2101                 temp &= ~FDI_LINK_TRAIN_NONE;
2102                 temp |= FDI_LINK_TRAIN_NONE;
2103         }
2104         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2105
2106         /* wait one idle pattern time */
2107         POSTING_READ(reg);
2108         udelay(1000);
2109
2110         /* IVB wants error correction enabled */
2111         if (IS_IVYBRIDGE(dev))
2112                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2113                            FDI_FE_ERRC_ENABLE);
2114 }
2115
2116 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2117 {
2118         struct drm_i915_private *dev_priv = dev->dev_private;
2119         u32 flags = I915_READ(SOUTH_CHICKEN1);
2120
2121         flags |= FDI_PHASE_SYNC_OVR(pipe);
2122         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2123         flags |= FDI_PHASE_SYNC_EN(pipe);
2124         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2125         POSTING_READ(SOUTH_CHICKEN1);
2126 }
2127
2128 /* The FDI link training functions for ILK/Ibexpeak. */
2129 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2130 {
2131         struct drm_device *dev = crtc->dev;
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134         int pipe = intel_crtc->pipe;
2135         int plane = intel_crtc->plane;
2136         u32 reg, temp, tries;
2137
2138         /* FDI needs bits from pipe & plane first */
2139         assert_pipe_enabled(dev_priv, pipe);
2140         assert_plane_enabled(dev_priv, plane);
2141
2142         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2143            for train result */
2144         reg = FDI_RX_IMR(pipe);
2145         temp = I915_READ(reg);
2146         temp &= ~FDI_RX_SYMBOL_LOCK;
2147         temp &= ~FDI_RX_BIT_LOCK;
2148         I915_WRITE(reg, temp);
2149         I915_READ(reg);
2150         udelay(150);
2151
2152         /* enable CPU FDI TX and PCH FDI RX */
2153         reg = FDI_TX_CTL(pipe);
2154         temp = I915_READ(reg);
2155         temp &= ~(7 << 19);
2156         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2157         temp &= ~FDI_LINK_TRAIN_NONE;
2158         temp |= FDI_LINK_TRAIN_PATTERN_1;
2159         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2160
2161         reg = FDI_RX_CTL(pipe);
2162         temp = I915_READ(reg);
2163         temp &= ~FDI_LINK_TRAIN_NONE;
2164         temp |= FDI_LINK_TRAIN_PATTERN_1;
2165         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2166
2167         POSTING_READ(reg);
2168         udelay(150);
2169
2170         /* Ironlake workaround, enable clock pointer after FDI enable*/
2171         if (HAS_PCH_IBX(dev)) {
2172                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2173                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2174                            FDI_RX_PHASE_SYNC_POINTER_EN);
2175         }
2176
2177         reg = FDI_RX_IIR(pipe);
2178         for (tries = 0; tries < 5; tries++) {
2179                 temp = I915_READ(reg);
2180                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2181
2182                 if ((temp & FDI_RX_BIT_LOCK)) {
2183                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2184                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2185                         break;
2186                 }
2187         }
2188         if (tries == 5)
2189                 DRM_ERROR("FDI train 1 fail!\n");
2190
2191         /* Train 2 */
2192         reg = FDI_TX_CTL(pipe);
2193         temp = I915_READ(reg);
2194         temp &= ~FDI_LINK_TRAIN_NONE;
2195         temp |= FDI_LINK_TRAIN_PATTERN_2;
2196         I915_WRITE(reg, temp);
2197
2198         reg = FDI_RX_CTL(pipe);
2199         temp = I915_READ(reg);
2200         temp &= ~FDI_LINK_TRAIN_NONE;
2201         temp |= FDI_LINK_TRAIN_PATTERN_2;
2202         I915_WRITE(reg, temp);
2203
2204         POSTING_READ(reg);
2205         udelay(150);
2206
2207         reg = FDI_RX_IIR(pipe);
2208         for (tries = 0; tries < 5; tries++) {
2209                 temp = I915_READ(reg);
2210                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2211
2212                 if (temp & FDI_RX_SYMBOL_LOCK) {
2213                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2214                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2215                         break;
2216                 }
2217         }
2218         if (tries == 5)
2219                 DRM_ERROR("FDI train 2 fail!\n");
2220
2221         DRM_DEBUG_KMS("FDI train done\n");
2222
2223 }
2224
2225 static const int snb_b_fdi_train_param [] = {
2226         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2227         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2228         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2229         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2230 };
2231
2232 /* The FDI link training functions for SNB/Cougarpoint. */
2233 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2234 {
2235         struct drm_device *dev = crtc->dev;
2236         struct drm_i915_private *dev_priv = dev->dev_private;
2237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2238         int pipe = intel_crtc->pipe;
2239         u32 reg, temp, i;
2240
2241         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2242            for train result */
2243         reg = FDI_RX_IMR(pipe);
2244         temp = I915_READ(reg);
2245         temp &= ~FDI_RX_SYMBOL_LOCK;
2246         temp &= ~FDI_RX_BIT_LOCK;
2247         I915_WRITE(reg, temp);
2248
2249         POSTING_READ(reg);
2250         udelay(150);
2251
2252         /* enable CPU FDI TX and PCH FDI RX */
2253         reg = FDI_TX_CTL(pipe);
2254         temp = I915_READ(reg);
2255         temp &= ~(7 << 19);
2256         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2257         temp &= ~FDI_LINK_TRAIN_NONE;
2258         temp |= FDI_LINK_TRAIN_PATTERN_1;
2259         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2260         /* SNB-B */
2261         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2262         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2263
2264         reg = FDI_RX_CTL(pipe);
2265         temp = I915_READ(reg);
2266         if (HAS_PCH_CPT(dev)) {
2267                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2268                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2269         } else {
2270                 temp &= ~FDI_LINK_TRAIN_NONE;
2271                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2272         }
2273         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2274
2275         POSTING_READ(reg);
2276         udelay(150);
2277
2278         if (HAS_PCH_CPT(dev))
2279                 cpt_phase_pointer_enable(dev, pipe);
2280
2281         for (i = 0; i < 4; i++ ) {
2282                 reg = FDI_TX_CTL(pipe);
2283                 temp = I915_READ(reg);
2284                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2285                 temp |= snb_b_fdi_train_param[i];
2286                 I915_WRITE(reg, temp);
2287
2288                 POSTING_READ(reg);
2289                 udelay(500);
2290
2291                 reg = FDI_RX_IIR(pipe);
2292                 temp = I915_READ(reg);
2293                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2294
2295                 if (temp & FDI_RX_BIT_LOCK) {
2296                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2297                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2298                         break;
2299                 }
2300         }
2301         if (i == 4)
2302                 DRM_ERROR("FDI train 1 fail!\n");
2303
2304         /* Train 2 */
2305         reg = FDI_TX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         temp &= ~FDI_LINK_TRAIN_NONE;
2308         temp |= FDI_LINK_TRAIN_PATTERN_2;
2309         if (IS_GEN6(dev)) {
2310                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2311                 /* SNB-B */
2312                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2313         }
2314         I915_WRITE(reg, temp);
2315
2316         reg = FDI_RX_CTL(pipe);
2317         temp = I915_READ(reg);
2318         if (HAS_PCH_CPT(dev)) {
2319                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2320                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2321         } else {
2322                 temp &= ~FDI_LINK_TRAIN_NONE;
2323                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2324         }
2325         I915_WRITE(reg, temp);
2326
2327         POSTING_READ(reg);
2328         udelay(150);
2329
2330         for (i = 0; i < 4; i++ ) {
2331                 reg = FDI_TX_CTL(pipe);
2332                 temp = I915_READ(reg);
2333                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2334                 temp |= snb_b_fdi_train_param[i];
2335                 I915_WRITE(reg, temp);
2336
2337                 POSTING_READ(reg);
2338                 udelay(500);
2339
2340                 reg = FDI_RX_IIR(pipe);
2341                 temp = I915_READ(reg);
2342                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2343
2344                 if (temp & FDI_RX_SYMBOL_LOCK) {
2345                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2346                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2347                         break;
2348                 }
2349         }
2350         if (i == 4)
2351                 DRM_ERROR("FDI train 2 fail!\n");
2352
2353         DRM_DEBUG_KMS("FDI train done.\n");
2354 }
2355
2356 /* Manual link training for Ivy Bridge A0 parts */
2357 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2358 {
2359         struct drm_device *dev = crtc->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362         int pipe = intel_crtc->pipe;
2363         u32 reg, temp, i;
2364
2365         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2366            for train result */
2367         reg = FDI_RX_IMR(pipe);
2368         temp = I915_READ(reg);
2369         temp &= ~FDI_RX_SYMBOL_LOCK;
2370         temp &= ~FDI_RX_BIT_LOCK;
2371         I915_WRITE(reg, temp);
2372
2373         POSTING_READ(reg);
2374         udelay(150);
2375
2376         /* enable CPU FDI TX and PCH FDI RX */
2377         reg = FDI_TX_CTL(pipe);
2378         temp = I915_READ(reg);
2379         temp &= ~(7 << 19);
2380         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2381         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2382         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2383         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2384         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2385         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_LINK_TRAIN_AUTO;
2390         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2392         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2393
2394         POSTING_READ(reg);
2395         udelay(150);
2396
2397         if (HAS_PCH_CPT(dev))
2398                 cpt_phase_pointer_enable(dev, pipe);
2399
2400         for (i = 0; i < 4; i++ ) {
2401                 reg = FDI_TX_CTL(pipe);
2402                 temp = I915_READ(reg);
2403                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2404                 temp |= snb_b_fdi_train_param[i];
2405                 I915_WRITE(reg, temp);
2406
2407                 POSTING_READ(reg);
2408                 udelay(500);
2409
2410                 reg = FDI_RX_IIR(pipe);
2411                 temp = I915_READ(reg);
2412                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2413
2414                 if (temp & FDI_RX_BIT_LOCK ||
2415                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2416                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         break;
2419                 }
2420         }
2421         if (i == 4)
2422                 DRM_ERROR("FDI train 1 fail!\n");
2423
2424         /* Train 2 */
2425         reg = FDI_TX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2428         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2429         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2430         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2431         I915_WRITE(reg, temp);
2432
2433         reg = FDI_RX_CTL(pipe);
2434         temp = I915_READ(reg);
2435         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2436         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2437         I915_WRITE(reg, temp);
2438
2439         POSTING_READ(reg);
2440         udelay(150);
2441
2442         for (i = 0; i < 4; i++ ) {
2443                 reg = FDI_TX_CTL(pipe);
2444                 temp = I915_READ(reg);
2445                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2446                 temp |= snb_b_fdi_train_param[i];
2447                 I915_WRITE(reg, temp);
2448
2449                 POSTING_READ(reg);
2450                 udelay(500);
2451
2452                 reg = FDI_RX_IIR(pipe);
2453                 temp = I915_READ(reg);
2454                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2455
2456                 if (temp & FDI_RX_SYMBOL_LOCK) {
2457                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2458                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2459                         break;
2460                 }
2461         }
2462         if (i == 4)
2463                 DRM_ERROR("FDI train 2 fail!\n");
2464
2465         DRM_DEBUG_KMS("FDI train done.\n");
2466 }
2467
2468 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2469 {
2470         struct drm_device *dev = crtc->dev;
2471         struct drm_i915_private *dev_priv = dev->dev_private;
2472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2473         int pipe = intel_crtc->pipe;
2474         u32 reg, temp;
2475
2476         /* Write the TU size bits so error detection works */
2477         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2478                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2479
2480         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2481         reg = FDI_RX_CTL(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~((0x7 << 19) | (0x7 << 16));
2484         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2485         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2486         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2487
2488         POSTING_READ(reg);
2489         udelay(200);
2490
2491         /* Switch from Rawclk to PCDclk */
2492         temp = I915_READ(reg);
2493         I915_WRITE(reg, temp | FDI_PCDCLK);
2494
2495         POSTING_READ(reg);
2496         udelay(200);
2497
2498         /* Enable CPU FDI TX PLL, always on for Ironlake */
2499         reg = FDI_TX_CTL(pipe);
2500         temp = I915_READ(reg);
2501         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2502                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2503
2504                 POSTING_READ(reg);
2505                 udelay(100);
2506         }
2507 }
2508
2509 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2510 {
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512         u32 flags = I915_READ(SOUTH_CHICKEN1);
2513
2514         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2515         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2516         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2517         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2518         POSTING_READ(SOUTH_CHICKEN1);
2519 }
2520 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2521 {
2522         struct drm_device *dev = crtc->dev;
2523         struct drm_i915_private *dev_priv = dev->dev_private;
2524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525         int pipe = intel_crtc->pipe;
2526         u32 reg, temp;
2527
2528         /* disable CPU FDI tx and PCH FDI rx */
2529         reg = FDI_TX_CTL(pipe);
2530         temp = I915_READ(reg);
2531         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2532         POSTING_READ(reg);
2533
2534         reg = FDI_RX_CTL(pipe);
2535         temp = I915_READ(reg);
2536         temp &= ~(0x7 << 16);
2537         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2538         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2539
2540         POSTING_READ(reg);
2541         udelay(100);
2542
2543         /* Ironlake workaround, disable clock pointer after downing FDI */
2544         if (HAS_PCH_IBX(dev)) {
2545                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2546                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2547                            I915_READ(FDI_RX_CHICKEN(pipe) &
2548                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2549         } else if (HAS_PCH_CPT(dev)) {
2550                 cpt_phase_pointer_disable(dev, pipe);
2551         }
2552
2553         /* still set train pattern 1 */
2554         reg = FDI_TX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~FDI_LINK_TRAIN_NONE;
2557         temp |= FDI_LINK_TRAIN_PATTERN_1;
2558         I915_WRITE(reg, temp);
2559
2560         reg = FDI_RX_CTL(pipe);
2561         temp = I915_READ(reg);
2562         if (HAS_PCH_CPT(dev)) {
2563                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2564                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2565         } else {
2566                 temp &= ~FDI_LINK_TRAIN_NONE;
2567                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2568         }
2569         /* BPC in FDI rx is consistent with that in PIPECONF */
2570         temp &= ~(0x07 << 16);
2571         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2572         I915_WRITE(reg, temp);
2573
2574         POSTING_READ(reg);
2575         udelay(100);
2576 }
2577
2578 /*
2579  * When we disable a pipe, we need to clear any pending scanline wait events
2580  * to avoid hanging the ring, which we assume we are waiting on.
2581  */
2582 static void intel_clear_scanline_wait(struct drm_device *dev)
2583 {
2584         struct drm_i915_private *dev_priv = dev->dev_private;
2585         struct intel_ring_buffer *ring;
2586         u32 tmp;
2587
2588         if (IS_GEN2(dev))
2589                 /* Can't break the hang on i8xx */
2590                 return;
2591
2592         ring = LP_RING(dev_priv);
2593         tmp = I915_READ_CTL(ring);
2594         if (tmp & RING_WAIT)
2595                 I915_WRITE_CTL(ring, tmp);
2596 }
2597
2598 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2599 {
2600         struct drm_i915_gem_object *obj;
2601         struct drm_i915_private *dev_priv;
2602
2603         if (crtc->fb == NULL)
2604                 return;
2605
2606         obj = to_intel_framebuffer(crtc->fb)->obj;
2607         dev_priv = crtc->dev->dev_private;
2608         wait_event(dev_priv->pending_flip_queue,
2609                    atomic_read(&obj->pending_flip) == 0);
2610 }
2611
2612 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615         struct drm_mode_config *mode_config = &dev->mode_config;
2616         struct intel_encoder *encoder;
2617
2618         /*
2619          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2620          * must be driven by its own crtc; no sharing is possible.
2621          */
2622         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2623                 if (encoder->base.crtc != crtc)
2624                         continue;
2625
2626                 switch (encoder->type) {
2627                 case INTEL_OUTPUT_EDP:
2628                         if (!intel_encoder_is_pch_edp(&encoder->base))
2629                                 return false;
2630                         continue;
2631                 }
2632         }
2633
2634         return true;
2635 }
2636
2637 /*
2638  * Enable PCH resources required for PCH ports:
2639  *   - PCH PLLs
2640  *   - FDI training & RX/TX
2641  *   - update transcoder timings
2642  *   - DP transcoding bits
2643  *   - transcoder
2644  */
2645 static void ironlake_pch_enable(struct drm_crtc *crtc)
2646 {
2647         struct drm_device *dev = crtc->dev;
2648         struct drm_i915_private *dev_priv = dev->dev_private;
2649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650         int pipe = intel_crtc->pipe;
2651         u32 reg, temp;
2652
2653         /* For PCH output, training FDI link */
2654         dev_priv->display.fdi_link_train(crtc);
2655
2656         intel_enable_pch_pll(dev_priv, pipe);
2657
2658         if (HAS_PCH_CPT(dev)) {
2659                 /* Be sure PCH DPLL SEL is set */
2660                 temp = I915_READ(PCH_DPLL_SEL);
2661                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2662                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2663                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2664                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2665                 I915_WRITE(PCH_DPLL_SEL, temp);
2666         }
2667
2668         /* set transcoder timing, panel must allow it */
2669         assert_panel_unlocked(dev_priv, pipe);
2670         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2671         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2672         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2673
2674         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2675         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2676         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2677
2678         intel_fdi_normal_train(crtc);
2679
2680         /* For PCH DP, enable TRANS_DP_CTL */
2681         if (HAS_PCH_CPT(dev) &&
2682             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2683                 reg = TRANS_DP_CTL(pipe);
2684                 temp = I915_READ(reg);
2685                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2686                           TRANS_DP_SYNC_MASK |
2687                           TRANS_DP_BPC_MASK);
2688                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2689                          TRANS_DP_ENH_FRAMING);
2690                 temp |= TRANS_DP_8BPC;
2691
2692                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2693                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2694                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2695                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2696
2697                 switch (intel_trans_dp_port_sel(crtc)) {
2698                 case PCH_DP_B:
2699                         temp |= TRANS_DP_PORT_SEL_B;
2700                         break;
2701                 case PCH_DP_C:
2702                         temp |= TRANS_DP_PORT_SEL_C;
2703                         break;
2704                 case PCH_DP_D:
2705                         temp |= TRANS_DP_PORT_SEL_D;
2706                         break;
2707                 default:
2708                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2709                         temp |= TRANS_DP_PORT_SEL_B;
2710                         break;
2711                 }
2712
2713                 I915_WRITE(reg, temp);
2714         }
2715
2716         intel_enable_transcoder(dev_priv, pipe);
2717 }
2718
2719 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2720 {
2721         struct drm_device *dev = crtc->dev;
2722         struct drm_i915_private *dev_priv = dev->dev_private;
2723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724         int pipe = intel_crtc->pipe;
2725         int plane = intel_crtc->plane;
2726         u32 temp;
2727         bool is_pch_port;
2728
2729         if (intel_crtc->active)
2730                 return;
2731
2732         intel_crtc->active = true;
2733         intel_update_watermarks(dev);
2734
2735         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2736                 temp = I915_READ(PCH_LVDS);
2737                 if ((temp & LVDS_PORT_EN) == 0)
2738                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2739         }
2740
2741         is_pch_port = intel_crtc_driving_pch(crtc);
2742
2743         if (is_pch_port)
2744                 ironlake_fdi_pll_enable(crtc);
2745         else
2746                 ironlake_fdi_disable(crtc);
2747
2748         /* Enable panel fitting for LVDS */
2749         if (dev_priv->pch_pf_size &&
2750             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2751                 /* Force use of hard-coded filter coefficients
2752                  * as some pre-programmed values are broken,
2753                  * e.g. x201.
2754                  */
2755                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2756                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2757                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2758         }
2759
2760         /*
2761          * On ILK+ LUT must be loaded before the pipe is running but with
2762          * clocks enabled
2763          */
2764         intel_crtc_load_lut(crtc);
2765
2766         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2767         intel_enable_plane(dev_priv, plane, pipe);
2768
2769         if (is_pch_port)
2770                 ironlake_pch_enable(crtc);
2771
2772         mutex_lock(&dev->struct_mutex);
2773         intel_update_fbc(dev);
2774         mutex_unlock(&dev->struct_mutex);
2775
2776         intel_crtc_update_cursor(crtc, true);
2777 }
2778
2779 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2780 {
2781         struct drm_device *dev = crtc->dev;
2782         struct drm_i915_private *dev_priv = dev->dev_private;
2783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2784         int pipe = intel_crtc->pipe;
2785         int plane = intel_crtc->plane;
2786         u32 reg, temp;
2787
2788         if (!intel_crtc->active)
2789                 return;
2790
2791         intel_crtc_wait_for_pending_flips(crtc);
2792         drm_vblank_off(dev, pipe);
2793         intel_crtc_update_cursor(crtc, false);
2794
2795         intel_disable_plane(dev_priv, plane, pipe);
2796
2797         if (dev_priv->cfb_plane == plane &&
2798             dev_priv->display.disable_fbc)
2799                 dev_priv->display.disable_fbc(dev);
2800
2801         intel_disable_pipe(dev_priv, pipe);
2802
2803         /* Disable PF */
2804         I915_WRITE(PF_CTL(pipe), 0);
2805         I915_WRITE(PF_WIN_SZ(pipe), 0);
2806
2807         ironlake_fdi_disable(crtc);
2808
2809         /* This is a horrible layering violation; we should be doing this in
2810          * the connector/encoder ->prepare instead, but we don't always have
2811          * enough information there about the config to know whether it will
2812          * actually be necessary or just cause undesired flicker.
2813          */
2814         intel_disable_pch_ports(dev_priv, pipe);
2815
2816         intel_disable_transcoder(dev_priv, pipe);
2817
2818         if (HAS_PCH_CPT(dev)) {
2819                 /* disable TRANS_DP_CTL */
2820                 reg = TRANS_DP_CTL(pipe);
2821                 temp = I915_READ(reg);
2822                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2823                 temp |= TRANS_DP_PORT_SEL_NONE;
2824                 I915_WRITE(reg, temp);
2825
2826                 /* disable DPLL_SEL */
2827                 temp = I915_READ(PCH_DPLL_SEL);
2828                 switch (pipe) {
2829                 case 0:
2830                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2831                         break;
2832                 case 1:
2833                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2834                         break;
2835                 case 2:
2836                         /* FIXME: manage transcoder PLLs? */
2837                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2838                         break;
2839                 default:
2840                         BUG(); /* wtf */
2841                 }
2842                 I915_WRITE(PCH_DPLL_SEL, temp);
2843         }
2844
2845         /* disable PCH DPLL */
2846         intel_disable_pch_pll(dev_priv, pipe);
2847
2848         /* Switch from PCDclk to Rawclk */
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2852
2853         /* Disable CPU FDI TX PLL */
2854         reg = FDI_TX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2857
2858         POSTING_READ(reg);
2859         udelay(100);
2860
2861         reg = FDI_RX_CTL(pipe);
2862         temp = I915_READ(reg);
2863         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2864
2865         /* Wait for the clocks to turn off. */
2866         POSTING_READ(reg);
2867         udelay(100);
2868
2869         intel_crtc->active = false;
2870         intel_update_watermarks(dev);
2871
2872         mutex_lock(&dev->struct_mutex);
2873         intel_update_fbc(dev);
2874         intel_clear_scanline_wait(dev);
2875         mutex_unlock(&dev->struct_mutex);
2876 }
2877
2878 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2879 {
2880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2881         int pipe = intel_crtc->pipe;
2882         int plane = intel_crtc->plane;
2883
2884         /* XXX: When our outputs are all unaware of DPMS modes other than off
2885          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2886          */
2887         switch (mode) {
2888         case DRM_MODE_DPMS_ON:
2889         case DRM_MODE_DPMS_STANDBY:
2890         case DRM_MODE_DPMS_SUSPEND:
2891                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2892                 ironlake_crtc_enable(crtc);
2893                 break;
2894
2895         case DRM_MODE_DPMS_OFF:
2896                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2897                 ironlake_crtc_disable(crtc);
2898                 break;
2899         }
2900 }
2901
2902 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2903 {
2904         if (!enable && intel_crtc->overlay) {
2905                 struct drm_device *dev = intel_crtc->base.dev;
2906                 struct drm_i915_private *dev_priv = dev->dev_private;
2907
2908                 mutex_lock(&dev->struct_mutex);
2909                 dev_priv->mm.interruptible = false;
2910                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2911                 dev_priv->mm.interruptible = true;
2912                 mutex_unlock(&dev->struct_mutex);
2913         }
2914
2915         /* Let userspace switch the overlay on again. In most cases userspace
2916          * has to recompute where to put it anyway.
2917          */
2918 }
2919
2920 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2921 {
2922         struct drm_device *dev = crtc->dev;
2923         struct drm_i915_private *dev_priv = dev->dev_private;
2924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2925         int pipe = intel_crtc->pipe;
2926         int plane = intel_crtc->plane;
2927
2928         if (intel_crtc->active)
2929                 return;
2930
2931         intel_crtc->active = true;
2932         intel_update_watermarks(dev);
2933
2934         intel_enable_pll(dev_priv, pipe);
2935         intel_enable_pipe(dev_priv, pipe, false);
2936         intel_enable_plane(dev_priv, plane, pipe);
2937
2938         intel_crtc_load_lut(crtc);
2939         intel_update_fbc(dev);
2940
2941         /* Give the overlay scaler a chance to enable if it's on this pipe */
2942         intel_crtc_dpms_overlay(intel_crtc, true);
2943         intel_crtc_update_cursor(crtc, true);
2944 }
2945
2946 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2947 {
2948         struct drm_device *dev = crtc->dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951         int pipe = intel_crtc->pipe;
2952         int plane = intel_crtc->plane;
2953
2954         if (!intel_crtc->active)
2955                 return;
2956
2957         /* Give the overlay scaler a chance to disable if it's on this pipe */
2958         intel_crtc_wait_for_pending_flips(crtc);
2959         drm_vblank_off(dev, pipe);
2960         intel_crtc_dpms_overlay(intel_crtc, false);
2961         intel_crtc_update_cursor(crtc, false);
2962
2963         if (dev_priv->cfb_plane == plane &&
2964             dev_priv->display.disable_fbc)
2965                 dev_priv->display.disable_fbc(dev);
2966
2967         intel_disable_plane(dev_priv, plane, pipe);
2968         intel_disable_pipe(dev_priv, pipe);
2969         intel_disable_pll(dev_priv, pipe);
2970
2971         intel_crtc->active = false;
2972         intel_update_fbc(dev);
2973         intel_update_watermarks(dev);
2974         intel_clear_scanline_wait(dev);
2975 }
2976
2977 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2978 {
2979         /* XXX: When our outputs are all unaware of DPMS modes other than off
2980          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2981          */
2982         switch (mode) {
2983         case DRM_MODE_DPMS_ON:
2984         case DRM_MODE_DPMS_STANDBY:
2985         case DRM_MODE_DPMS_SUSPEND:
2986                 i9xx_crtc_enable(crtc);
2987                 break;
2988         case DRM_MODE_DPMS_OFF:
2989                 i9xx_crtc_disable(crtc);
2990                 break;
2991         }
2992 }
2993
2994 /**
2995  * Sets the power management mode of the pipe and plane.
2996  */
2997 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2998 {
2999         struct drm_device *dev = crtc->dev;
3000         struct drm_i915_private *dev_priv = dev->dev_private;
3001         struct drm_i915_master_private *master_priv;
3002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003         int pipe = intel_crtc->pipe;
3004         bool enabled;
3005
3006         if (intel_crtc->dpms_mode == mode)
3007                 return;
3008
3009         intel_crtc->dpms_mode = mode;
3010
3011         dev_priv->display.dpms(crtc, mode);
3012
3013         if (!dev->primary->master)
3014                 return;
3015
3016         master_priv = dev->primary->master->driver_priv;
3017         if (!master_priv->sarea_priv)
3018                 return;
3019
3020         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3021
3022         switch (pipe) {
3023         case 0:
3024                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3025                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3026                 break;
3027         case 1:
3028                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3029                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3030                 break;
3031         default:
3032                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3033                 break;
3034         }
3035 }
3036
3037 static void intel_crtc_disable(struct drm_crtc *crtc)
3038 {
3039         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3040         struct drm_device *dev = crtc->dev;
3041
3042         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3043
3044         if (crtc->fb) {
3045                 mutex_lock(&dev->struct_mutex);
3046                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3047                 mutex_unlock(&dev->struct_mutex);
3048         }
3049 }
3050
3051 /* Prepare for a mode set.
3052  *
3053  * Note we could be a lot smarter here.  We need to figure out which outputs
3054  * will be enabled, which disabled (in short, how the config will changes)
3055  * and perform the minimum necessary steps to accomplish that, e.g. updating
3056  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3057  * panel fitting is in the proper state, etc.
3058  */
3059 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3060 {
3061         i9xx_crtc_disable(crtc);
3062 }
3063
3064 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3065 {
3066         i9xx_crtc_enable(crtc);
3067 }
3068
3069 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3070 {
3071         ironlake_crtc_disable(crtc);
3072 }
3073
3074 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3075 {
3076         ironlake_crtc_enable(crtc);
3077 }
3078
3079 void intel_encoder_prepare (struct drm_encoder *encoder)
3080 {
3081         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3082         /* lvds has its own version of prepare see intel_lvds_prepare */
3083         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3084 }
3085
3086 void intel_encoder_commit (struct drm_encoder *encoder)
3087 {
3088         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3089         /* lvds has its own version of commit see intel_lvds_commit */
3090         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3091 }
3092
3093 void intel_encoder_destroy(struct drm_encoder *encoder)
3094 {
3095         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3096
3097         drm_encoder_cleanup(encoder);
3098         kfree(intel_encoder);
3099 }
3100
3101 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3102                                   struct drm_display_mode *mode,
3103                                   struct drm_display_mode *adjusted_mode)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106
3107         if (HAS_PCH_SPLIT(dev)) {
3108                 /* FDI link clock is fixed at 2.7G */
3109                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3110                         return false;
3111         }
3112
3113         /* XXX some encoders set the crtcinfo, others don't.
3114          * Obviously we need some form of conflict resolution here...
3115          */
3116         if (adjusted_mode->crtc_htotal == 0)
3117                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3118
3119         return true;
3120 }
3121
3122 static int i945_get_display_clock_speed(struct drm_device *dev)
3123 {
3124         return 400000;
3125 }
3126
3127 static int i915_get_display_clock_speed(struct drm_device *dev)
3128 {
3129         return 333000;
3130 }
3131
3132 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3133 {
3134         return 200000;
3135 }
3136
3137 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3138 {
3139         u16 gcfgc = 0;
3140
3141         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3142
3143         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3144                 return 133000;
3145         else {
3146                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3147                 case GC_DISPLAY_CLOCK_333_MHZ:
3148                         return 333000;
3149                 default:
3150                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3151                         return 190000;
3152                 }
3153         }
3154 }
3155
3156 static int i865_get_display_clock_speed(struct drm_device *dev)
3157 {
3158         return 266000;
3159 }
3160
3161 static int i855_get_display_clock_speed(struct drm_device *dev)
3162 {
3163         u16 hpllcc = 0;
3164         /* Assume that the hardware is in the high speed state.  This
3165          * should be the default.
3166          */
3167         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3168         case GC_CLOCK_133_200:
3169         case GC_CLOCK_100_200:
3170                 return 200000;
3171         case GC_CLOCK_166_250:
3172                 return 250000;
3173         case GC_CLOCK_100_133:
3174                 return 133000;
3175         }
3176
3177         /* Shouldn't happen */
3178         return 0;
3179 }
3180
3181 static int i830_get_display_clock_speed(struct drm_device *dev)
3182 {
3183         return 133000;
3184 }
3185
3186 struct fdi_m_n {
3187         u32        tu;
3188         u32        gmch_m;
3189         u32        gmch_n;
3190         u32        link_m;
3191         u32        link_n;
3192 };
3193
3194 static void
3195 fdi_reduce_ratio(u32 *num, u32 *den)
3196 {
3197         while (*num > 0xffffff || *den > 0xffffff) {
3198                 *num >>= 1;
3199                 *den >>= 1;
3200         }
3201 }
3202
3203 static void
3204 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3205                      int link_clock, struct fdi_m_n *m_n)
3206 {
3207         m_n->tu = 64; /* default size */
3208
3209         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3210         m_n->gmch_m = bits_per_pixel * pixel_clock;
3211         m_n->gmch_n = link_clock * nlanes * 8;
3212         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3213
3214         m_n->link_m = pixel_clock;
3215         m_n->link_n = link_clock;
3216         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3217 }
3218
3219
3220 struct intel_watermark_params {
3221         unsigned long fifo_size;
3222         unsigned long max_wm;
3223         unsigned long default_wm;
3224         unsigned long guard_size;
3225         unsigned long cacheline_size;
3226 };
3227
3228 /* Pineview has different values for various configs */
3229 static const struct intel_watermark_params pineview_display_wm = {
3230         PINEVIEW_DISPLAY_FIFO,
3231         PINEVIEW_MAX_WM,
3232         PINEVIEW_DFT_WM,
3233         PINEVIEW_GUARD_WM,
3234         PINEVIEW_FIFO_LINE_SIZE
3235 };
3236 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3237         PINEVIEW_DISPLAY_FIFO,
3238         PINEVIEW_MAX_WM,
3239         PINEVIEW_DFT_HPLLOFF_WM,
3240         PINEVIEW_GUARD_WM,
3241         PINEVIEW_FIFO_LINE_SIZE
3242 };
3243 static const struct intel_watermark_params pineview_cursor_wm = {
3244         PINEVIEW_CURSOR_FIFO,
3245         PINEVIEW_CURSOR_MAX_WM,
3246         PINEVIEW_CURSOR_DFT_WM,
3247         PINEVIEW_CURSOR_GUARD_WM,
3248         PINEVIEW_FIFO_LINE_SIZE,
3249 };
3250 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3251         PINEVIEW_CURSOR_FIFO,
3252         PINEVIEW_CURSOR_MAX_WM,
3253         PINEVIEW_CURSOR_DFT_WM,
3254         PINEVIEW_CURSOR_GUARD_WM,
3255         PINEVIEW_FIFO_LINE_SIZE
3256 };
3257 static const struct intel_watermark_params g4x_wm_info = {
3258         G4X_FIFO_SIZE,
3259         G4X_MAX_WM,
3260         G4X_MAX_WM,
3261         2,
3262         G4X_FIFO_LINE_SIZE,
3263 };
3264 static const struct intel_watermark_params g4x_cursor_wm_info = {
3265         I965_CURSOR_FIFO,
3266         I965_CURSOR_MAX_WM,
3267         I965_CURSOR_DFT_WM,
3268         2,
3269         G4X_FIFO_LINE_SIZE,
3270 };
3271 static const struct intel_watermark_params i965_cursor_wm_info = {
3272         I965_CURSOR_FIFO,
3273         I965_CURSOR_MAX_WM,
3274         I965_CURSOR_DFT_WM,
3275         2,
3276         I915_FIFO_LINE_SIZE,
3277 };
3278 static const struct intel_watermark_params i945_wm_info = {
3279         I945_FIFO_SIZE,
3280         I915_MAX_WM,
3281         1,
3282         2,
3283         I915_FIFO_LINE_SIZE
3284 };
3285 static const struct intel_watermark_params i915_wm_info = {
3286         I915_FIFO_SIZE,
3287         I915_MAX_WM,
3288         1,
3289         2,
3290         I915_FIFO_LINE_SIZE
3291 };
3292 static const struct intel_watermark_params i855_wm_info = {
3293         I855GM_FIFO_SIZE,
3294         I915_MAX_WM,
3295         1,
3296         2,
3297         I830_FIFO_LINE_SIZE
3298 };
3299 static const struct intel_watermark_params i830_wm_info = {
3300         I830_FIFO_SIZE,
3301         I915_MAX_WM,
3302         1,
3303         2,
3304         I830_FIFO_LINE_SIZE
3305 };
3306
3307 static const struct intel_watermark_params ironlake_display_wm_info = {
3308         ILK_DISPLAY_FIFO,
3309         ILK_DISPLAY_MAXWM,
3310         ILK_DISPLAY_DFTWM,
3311         2,
3312         ILK_FIFO_LINE_SIZE
3313 };
3314 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3315         ILK_CURSOR_FIFO,
3316         ILK_CURSOR_MAXWM,
3317         ILK_CURSOR_DFTWM,
3318         2,
3319         ILK_FIFO_LINE_SIZE
3320 };
3321 static const struct intel_watermark_params ironlake_display_srwm_info = {
3322         ILK_DISPLAY_SR_FIFO,
3323         ILK_DISPLAY_MAX_SRWM,
3324         ILK_DISPLAY_DFT_SRWM,
3325         2,
3326         ILK_FIFO_LINE_SIZE
3327 };
3328 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3329         ILK_CURSOR_SR_FIFO,
3330         ILK_CURSOR_MAX_SRWM,
3331         ILK_CURSOR_DFT_SRWM,
3332         2,
3333         ILK_FIFO_LINE_SIZE
3334 };
3335
3336 static const struct intel_watermark_params sandybridge_display_wm_info = {
3337         SNB_DISPLAY_FIFO,
3338         SNB_DISPLAY_MAXWM,
3339         SNB_DISPLAY_DFTWM,
3340         2,
3341         SNB_FIFO_LINE_SIZE
3342 };
3343 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3344         SNB_CURSOR_FIFO,
3345         SNB_CURSOR_MAXWM,
3346         SNB_CURSOR_DFTWM,
3347         2,
3348         SNB_FIFO_LINE_SIZE
3349 };
3350 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3351         SNB_DISPLAY_SR_FIFO,
3352         SNB_DISPLAY_MAX_SRWM,
3353         SNB_DISPLAY_DFT_SRWM,
3354         2,
3355         SNB_FIFO_LINE_SIZE
3356 };
3357 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3358         SNB_CURSOR_SR_FIFO,
3359         SNB_CURSOR_MAX_SRWM,
3360         SNB_CURSOR_DFT_SRWM,
3361         2,
3362         SNB_FIFO_LINE_SIZE
3363 };
3364
3365
3366 /**
3367  * intel_calculate_wm - calculate watermark level
3368  * @clock_in_khz: pixel clock
3369  * @wm: chip FIFO params
3370  * @pixel_size: display pixel size
3371  * @latency_ns: memory latency for the platform
3372  *
3373  * Calculate the watermark level (the level at which the display plane will
3374  * start fetching from memory again).  Each chip has a different display
3375  * FIFO size and allocation, so the caller needs to figure that out and pass
3376  * in the correct intel_watermark_params structure.
3377  *
3378  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3379  * on the pixel size.  When it reaches the watermark level, it'll start
3380  * fetching FIFO line sized based chunks from memory until the FIFO fills
3381  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3382  * will occur, and a display engine hang could result.
3383  */
3384 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3385                                         const struct intel_watermark_params *wm,
3386                                         int fifo_size,
3387                                         int pixel_size,
3388                                         unsigned long latency_ns)
3389 {
3390         long entries_required, wm_size;
3391
3392         /*
3393          * Note: we need to make sure we don't overflow for various clock &
3394          * latency values.
3395          * clocks go from a few thousand to several hundred thousand.
3396          * latency is usually a few thousand
3397          */
3398         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3399                 1000;
3400         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3401
3402         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3403
3404         wm_size = fifo_size - (entries_required + wm->guard_size);
3405
3406         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3407
3408         /* Don't promote wm_size to unsigned... */
3409         if (wm_size > (long)wm->max_wm)
3410                 wm_size = wm->max_wm;
3411         if (wm_size <= 0)
3412                 wm_size = wm->default_wm;
3413         return wm_size;
3414 }
3415
3416 struct cxsr_latency {
3417         int is_desktop;
3418         int is_ddr3;
3419         unsigned long fsb_freq;
3420         unsigned long mem_freq;
3421         unsigned long display_sr;
3422         unsigned long display_hpll_disable;
3423         unsigned long cursor_sr;
3424         unsigned long cursor_hpll_disable;
3425 };
3426
3427 static const struct cxsr_latency cxsr_latency_table[] = {
3428         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3429         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3430         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3431         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3432         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3433
3434         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3435         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3436         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3437         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3438         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3439
3440         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3441         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3442         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3443         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3444         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3445
3446         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3447         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3448         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3449         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3450         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3451
3452         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3453         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3454         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3455         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3456         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3457
3458         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3459         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3460         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3461         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3462         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3463 };
3464
3465 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3466                                                          int is_ddr3,
3467                                                          int fsb,
3468                                                          int mem)
3469 {
3470         const struct cxsr_latency *latency;
3471         int i;
3472
3473         if (fsb == 0 || mem == 0)
3474                 return NULL;
3475
3476         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3477                 latency = &cxsr_latency_table[i];
3478                 if (is_desktop == latency->is_desktop &&
3479                     is_ddr3 == latency->is_ddr3 &&
3480                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3481                         return latency;
3482         }
3483
3484         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3485
3486         return NULL;
3487 }
3488
3489 static void pineview_disable_cxsr(struct drm_device *dev)
3490 {
3491         struct drm_i915_private *dev_priv = dev->dev_private;
3492
3493         /* deactivate cxsr */
3494         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3495 }
3496
3497 /*
3498  * Latency for FIFO fetches is dependent on several factors:
3499  *   - memory configuration (speed, channels)
3500  *   - chipset
3501  *   - current MCH state
3502  * It can be fairly high in some situations, so here we assume a fairly
3503  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3504  * set this value too high, the FIFO will fetch frequently to stay full)
3505  * and power consumption (set it too low to save power and we might see
3506  * FIFO underruns and display "flicker").
3507  *
3508  * A value of 5us seems to be a good balance; safe for very low end
3509  * platforms but not overly aggressive on lower latency configs.
3510  */
3511 static const int latency_ns = 5000;
3512
3513 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3514 {
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         uint32_t dsparb = I915_READ(DSPARB);
3517         int size;
3518
3519         size = dsparb & 0x7f;
3520         if (plane)
3521                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3522
3523         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3524                       plane ? "B" : "A", size);
3525
3526         return size;
3527 }
3528
3529 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3530 {
3531         struct drm_i915_private *dev_priv = dev->dev_private;
3532         uint32_t dsparb = I915_READ(DSPARB);
3533         int size;
3534
3535         size = dsparb & 0x1ff;
3536         if (plane)
3537                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3538         size >>= 1; /* Convert to cachelines */
3539
3540         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3541                       plane ? "B" : "A", size);
3542
3543         return size;
3544 }
3545
3546 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3547 {
3548         struct drm_i915_private *dev_priv = dev->dev_private;
3549         uint32_t dsparb = I915_READ(DSPARB);
3550         int size;
3551
3552         size = dsparb & 0x7f;
3553         size >>= 2; /* Convert to cachelines */
3554
3555         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3556                       plane ? "B" : "A",
3557                       size);
3558
3559         return size;
3560 }
3561
3562 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3563 {
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565         uint32_t dsparb = I915_READ(DSPARB);
3566         int size;
3567
3568         size = dsparb & 0x7f;
3569         size >>= 1; /* Convert to cachelines */
3570
3571         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3572                       plane ? "B" : "A", size);
3573
3574         return size;
3575 }
3576
3577 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3578 {
3579         struct drm_crtc *crtc, *enabled = NULL;
3580
3581         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3582                 if (crtc->enabled && crtc->fb) {
3583                         if (enabled)
3584                                 return NULL;
3585                         enabled = crtc;
3586                 }
3587         }
3588
3589         return enabled;
3590 }
3591
3592 static void pineview_update_wm(struct drm_device *dev)
3593 {
3594         struct drm_i915_private *dev_priv = dev->dev_private;
3595         struct drm_crtc *crtc;
3596         const struct cxsr_latency *latency;
3597         u32 reg;
3598         unsigned long wm;
3599
3600         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3601                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3602         if (!latency) {
3603                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3604                 pineview_disable_cxsr(dev);
3605                 return;
3606         }
3607
3608         crtc = single_enabled_crtc(dev);
3609         if (crtc) {
3610                 int clock = crtc->mode.clock;
3611                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3612
3613                 /* Display SR */
3614                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3615                                         pineview_display_wm.fifo_size,
3616                                         pixel_size, latency->display_sr);
3617                 reg = I915_READ(DSPFW1);
3618                 reg &= ~DSPFW_SR_MASK;
3619                 reg |= wm << DSPFW_SR_SHIFT;
3620                 I915_WRITE(DSPFW1, reg);
3621                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3622
3623                 /* cursor SR */
3624                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3625                                         pineview_display_wm.fifo_size,
3626                                         pixel_size, latency->cursor_sr);
3627                 reg = I915_READ(DSPFW3);
3628                 reg &= ~DSPFW_CURSOR_SR_MASK;
3629                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3630                 I915_WRITE(DSPFW3, reg);
3631
3632                 /* Display HPLL off SR */
3633                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3634                                         pineview_display_hplloff_wm.fifo_size,
3635                                         pixel_size, latency->display_hpll_disable);
3636                 reg = I915_READ(DSPFW3);
3637                 reg &= ~DSPFW_HPLL_SR_MASK;
3638                 reg |= wm & DSPFW_HPLL_SR_MASK;
3639                 I915_WRITE(DSPFW3, reg);
3640
3641                 /* cursor HPLL off SR */
3642                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3643                                         pineview_display_hplloff_wm.fifo_size,
3644                                         pixel_size, latency->cursor_hpll_disable);
3645                 reg = I915_READ(DSPFW3);
3646                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3647                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3648                 I915_WRITE(DSPFW3, reg);
3649                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3650
3651                 /* activate cxsr */
3652                 I915_WRITE(DSPFW3,
3653                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3654                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3655         } else {
3656                 pineview_disable_cxsr(dev);
3657                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3658         }
3659 }
3660
3661 static bool g4x_compute_wm0(struct drm_device *dev,
3662                             int plane,
3663                             const struct intel_watermark_params *display,
3664                             int display_latency_ns,
3665                             const struct intel_watermark_params *cursor,
3666                             int cursor_latency_ns,
3667                             int *plane_wm,
3668                             int *cursor_wm)
3669 {
3670         struct drm_crtc *crtc;
3671         int htotal, hdisplay, clock, pixel_size;
3672         int line_time_us, line_count;
3673         int entries, tlb_miss;
3674
3675         crtc = intel_get_crtc_for_plane(dev, plane);
3676         if (crtc->fb == NULL || !crtc->enabled) {
3677                 *cursor_wm = cursor->guard_size;
3678                 *plane_wm = display->guard_size;
3679                 return false;
3680         }
3681
3682         htotal = crtc->mode.htotal;
3683         hdisplay = crtc->mode.hdisplay;
3684         clock = crtc->mode.clock;
3685         pixel_size = crtc->fb->bits_per_pixel / 8;
3686
3687         /* Use the small buffer method to calculate plane watermark */
3688         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3689         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3690         if (tlb_miss > 0)
3691                 entries += tlb_miss;
3692         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3693         *plane_wm = entries + display->guard_size;
3694         if (*plane_wm > (int)display->max_wm)
3695                 *plane_wm = display->max_wm;
3696
3697         /* Use the large buffer method to calculate cursor watermark */
3698         line_time_us = ((htotal * 1000) / clock);
3699         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3700         entries = line_count * 64 * pixel_size;
3701         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3702         if (tlb_miss > 0)
3703                 entries += tlb_miss;
3704         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3705         *cursor_wm = entries + cursor->guard_size;
3706         if (*cursor_wm > (int)cursor->max_wm)
3707                 *cursor_wm = (int)cursor->max_wm;
3708
3709         return true;
3710 }
3711
3712 /*
3713  * Check the wm result.
3714  *
3715  * If any calculated watermark values is larger than the maximum value that
3716  * can be programmed into the associated watermark register, that watermark
3717  * must be disabled.
3718  */
3719 static bool g4x_check_srwm(struct drm_device *dev,
3720                            int display_wm, int cursor_wm,
3721                            const struct intel_watermark_params *display,
3722                            const struct intel_watermark_params *cursor)
3723 {
3724         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3725                       display_wm, cursor_wm);
3726
3727         if (display_wm > display->max_wm) {
3728                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3729                               display_wm, display->max_wm);
3730                 return false;
3731         }
3732
3733         if (cursor_wm > cursor->max_wm) {
3734                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3735                               cursor_wm, cursor->max_wm);
3736                 return false;
3737         }
3738
3739         if (!(display_wm || cursor_wm)) {
3740                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3741                 return false;
3742         }
3743
3744         return true;
3745 }
3746
3747 static bool g4x_compute_srwm(struct drm_device *dev,
3748                              int plane,
3749                              int latency_ns,
3750                              const struct intel_watermark_params *display,
3751                              const struct intel_watermark_params *cursor,
3752                              int *display_wm, int *cursor_wm)
3753 {
3754         struct drm_crtc *crtc;
3755         int hdisplay, htotal, pixel_size, clock;
3756         unsigned long line_time_us;
3757         int line_count, line_size;
3758         int small, large;
3759         int entries;
3760
3761         if (!latency_ns) {
3762                 *display_wm = *cursor_wm = 0;
3763                 return false;
3764         }
3765
3766         crtc = intel_get_crtc_for_plane(dev, plane);
3767         hdisplay = crtc->mode.hdisplay;
3768         htotal = crtc->mode.htotal;
3769         clock = crtc->mode.clock;
3770         pixel_size = crtc->fb->bits_per_pixel / 8;
3771
3772         line_time_us = (htotal * 1000) / clock;
3773         line_count = (latency_ns / line_time_us + 1000) / 1000;
3774         line_size = hdisplay * pixel_size;
3775
3776         /* Use the minimum of the small and large buffer method for primary */
3777         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3778         large = line_count * line_size;
3779
3780         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3781         *display_wm = entries + display->guard_size;
3782
3783         /* calculate the self-refresh watermark for display cursor */
3784         entries = line_count * pixel_size * 64;
3785         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3786         *cursor_wm = entries + cursor->guard_size;
3787
3788         return g4x_check_srwm(dev,
3789                               *display_wm, *cursor_wm,
3790                               display, cursor);
3791 }
3792
3793 #define single_plane_enabled(mask) is_power_of_2(mask)
3794
3795 static void g4x_update_wm(struct drm_device *dev)
3796 {
3797         static const int sr_latency_ns = 12000;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3800         int plane_sr, cursor_sr;
3801         unsigned int enabled = 0;
3802
3803         if (g4x_compute_wm0(dev, 0,
3804                             &g4x_wm_info, latency_ns,
3805                             &g4x_cursor_wm_info, latency_ns,
3806                             &planea_wm, &cursora_wm))
3807                 enabled |= 1;
3808
3809         if (g4x_compute_wm0(dev, 1,
3810                             &g4x_wm_info, latency_ns,
3811                             &g4x_cursor_wm_info, latency_ns,
3812                             &planeb_wm, &cursorb_wm))
3813                 enabled |= 2;
3814
3815         plane_sr = cursor_sr = 0;
3816         if (single_plane_enabled(enabled) &&
3817             g4x_compute_srwm(dev, ffs(enabled) - 1,
3818                              sr_latency_ns,
3819                              &g4x_wm_info,
3820                              &g4x_cursor_wm_info,
3821                              &plane_sr, &cursor_sr))
3822                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3823         else
3824                 I915_WRITE(FW_BLC_SELF,
3825                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3826
3827         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3828                       planea_wm, cursora_wm,
3829                       planeb_wm, cursorb_wm,
3830                       plane_sr, cursor_sr);
3831
3832         I915_WRITE(DSPFW1,
3833                    (plane_sr << DSPFW_SR_SHIFT) |
3834                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3835                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3836                    planea_wm);
3837         I915_WRITE(DSPFW2,
3838                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3839                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3840         /* HPLL off in SR has some issues on G4x... disable it */
3841         I915_WRITE(DSPFW3,
3842                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3843                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3844 }
3845
3846 static void i965_update_wm(struct drm_device *dev)
3847 {
3848         struct drm_i915_private *dev_priv = dev->dev_private;
3849         struct drm_crtc *crtc;
3850         int srwm = 1;
3851         int cursor_sr = 16;
3852
3853         /* Calc sr entries for one plane configs */
3854         crtc = single_enabled_crtc(dev);
3855         if (crtc) {
3856                 /* self-refresh has much higher latency */
3857                 static const int sr_latency_ns = 12000;
3858                 int clock = crtc->mode.clock;
3859                 int htotal = crtc->mode.htotal;
3860                 int hdisplay = crtc->mode.hdisplay;
3861                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3862                 unsigned long line_time_us;
3863                 int entries;
3864
3865                 line_time_us = ((htotal * 1000) / clock);
3866
3867                 /* Use ns/us then divide to preserve precision */
3868                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3869                         pixel_size * hdisplay;
3870                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3871                 srwm = I965_FIFO_SIZE - entries;
3872                 if (srwm < 0)
3873                         srwm = 1;
3874                 srwm &= 0x1ff;
3875                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3876                               entries, srwm);
3877
3878                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3879                         pixel_size * 64;
3880                 entries = DIV_ROUND_UP(entries,
3881                                           i965_cursor_wm_info.cacheline_size);
3882                 cursor_sr = i965_cursor_wm_info.fifo_size -
3883                         (entries + i965_cursor_wm_info.guard_size);
3884
3885                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3886                         cursor_sr = i965_cursor_wm_info.max_wm;
3887
3888                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3889                               "cursor %d\n", srwm, cursor_sr);
3890
3891                 if (IS_CRESTLINE(dev))
3892                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3893         } else {
3894                 /* Turn off self refresh if both pipes are enabled */
3895                 if (IS_CRESTLINE(dev))
3896                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3897                                    & ~FW_BLC_SELF_EN);
3898         }
3899
3900         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3901                       srwm);
3902
3903         /* 965 has limitations... */
3904         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3905                    (8 << 16) | (8 << 8) | (8 << 0));
3906         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3907         /* update cursor SR watermark */
3908         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3909 }
3910
3911 static void i9xx_update_wm(struct drm_device *dev)
3912 {
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         const struct intel_watermark_params *wm_info;
3915         uint32_t fwater_lo;
3916         uint32_t fwater_hi;
3917         int cwm, srwm = 1;
3918         int fifo_size;
3919         int planea_wm, planeb_wm;
3920         struct drm_crtc *crtc, *enabled = NULL;
3921
3922         if (IS_I945GM(dev))
3923                 wm_info = &i945_wm_info;
3924         else if (!IS_GEN2(dev))
3925                 wm_info = &i915_wm_info;
3926         else
3927                 wm_info = &i855_wm_info;
3928
3929         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3930         crtc = intel_get_crtc_for_plane(dev, 0);
3931         if (crtc->enabled && crtc->fb) {
3932                 planea_wm = intel_calculate_wm(crtc->mode.clock,
3933                                                wm_info, fifo_size,
3934                                                crtc->fb->bits_per_pixel / 8,
3935                                                latency_ns);
3936                 enabled = crtc;
3937         } else
3938                 planea_wm = fifo_size - wm_info->guard_size;
3939
3940         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3941         crtc = intel_get_crtc_for_plane(dev, 1);
3942         if (crtc->enabled && crtc->fb) {
3943                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3944                                                wm_info, fifo_size,
3945                                                crtc->fb->bits_per_pixel / 8,
3946                                                latency_ns);
3947                 if (enabled == NULL)
3948                         enabled = crtc;
3949                 else
3950                         enabled = NULL;
3951         } else
3952                 planeb_wm = fifo_size - wm_info->guard_size;
3953
3954         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3955
3956         /*
3957          * Overlay gets an aggressive default since video jitter is bad.
3958          */
3959         cwm = 2;
3960
3961         /* Play safe and disable self-refresh before adjusting watermarks. */
3962         if (IS_I945G(dev) || IS_I945GM(dev))
3963                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3964         else if (IS_I915GM(dev))
3965                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3966
3967         /* Calc sr entries for one plane configs */
3968         if (HAS_FW_BLC(dev) && enabled) {
3969                 /* self-refresh has much higher latency */
3970                 static const int sr_latency_ns = 6000;
3971                 int clock = enabled->mode.clock;
3972                 int htotal = enabled->mode.htotal;
3973                 int hdisplay = enabled->mode.hdisplay;
3974                 int pixel_size = enabled->fb->bits_per_pixel / 8;
3975                 unsigned long line_time_us;
3976                 int entries;
3977
3978                 line_time_us = (htotal * 1000) / clock;
3979
3980                 /* Use ns/us then divide to preserve precision */
3981                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3982                         pixel_size * hdisplay;
3983                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3984                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3985                 srwm = wm_info->fifo_size - entries;
3986                 if (srwm < 0)
3987                         srwm = 1;
3988
3989                 if (IS_I945G(dev) || IS_I945GM(dev))
3990                         I915_WRITE(FW_BLC_SELF,
3991                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3992                 else if (IS_I915GM(dev))
3993                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3994         }
3995
3996         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3997                       planea_wm, planeb_wm, cwm, srwm);
3998
3999         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4000         fwater_hi = (cwm & 0x1f);
4001
4002         /* Set request length to 8 cachelines per fetch */
4003         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4004         fwater_hi = fwater_hi | (1 << 8);
4005
4006         I915_WRITE(FW_BLC, fwater_lo);
4007         I915_WRITE(FW_BLC2, fwater_hi);
4008
4009         if (HAS_FW_BLC(dev)) {
4010                 if (enabled) {
4011                         if (IS_I945G(dev) || IS_I945GM(dev))
4012                                 I915_WRITE(FW_BLC_SELF,
4013                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4014                         else if (IS_I915GM(dev))
4015                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4016                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4017                 } else
4018                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4019         }
4020 }
4021
4022 static void i830_update_wm(struct drm_device *dev)
4023 {
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         struct drm_crtc *crtc;
4026         uint32_t fwater_lo;
4027         int planea_wm;
4028
4029         crtc = single_enabled_crtc(dev);
4030         if (crtc == NULL)
4031                 return;
4032
4033         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4034                                        dev_priv->display.get_fifo_size(dev, 0),
4035                                        crtc->fb->bits_per_pixel / 8,
4036                                        latency_ns);
4037         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4038         fwater_lo |= (3<<8) | planea_wm;
4039
4040         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4041
4042         I915_WRITE(FW_BLC, fwater_lo);
4043 }
4044
4045 #define ILK_LP0_PLANE_LATENCY           700
4046 #define ILK_LP0_CURSOR_LATENCY          1300
4047
4048 /*
4049  * Check the wm result.
4050  *
4051  * If any calculated watermark values is larger than the maximum value that
4052  * can be programmed into the associated watermark register, that watermark
4053  * must be disabled.
4054  */
4055 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4056                                 int fbc_wm, int display_wm, int cursor_wm,
4057                                 const struct intel_watermark_params *display,
4058                                 const struct intel_watermark_params *cursor)
4059 {
4060         struct drm_i915_private *dev_priv = dev->dev_private;
4061
4062         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4063                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4064
4065         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4066                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4067                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4068
4069                 /* fbc has it's own way to disable FBC WM */
4070                 I915_WRITE(DISP_ARB_CTL,
4071                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4072                 return false;
4073         }
4074
4075         if (display_wm > display->max_wm) {
4076                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4077                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4078                 return false;
4079         }
4080
4081         if (cursor_wm > cursor->max_wm) {
4082                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4083                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4084                 return false;
4085         }
4086
4087         if (!(fbc_wm || display_wm || cursor_wm)) {
4088                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4089                 return false;
4090         }
4091
4092         return true;
4093 }
4094
4095 /*
4096  * Compute watermark values of WM[1-3],
4097  */
4098 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4099                                   int latency_ns,
4100                                   const struct intel_watermark_params *display,
4101                                   const struct intel_watermark_params *cursor,
4102                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4103 {
4104         struct drm_crtc *crtc;
4105         unsigned long line_time_us;
4106         int hdisplay, htotal, pixel_size, clock;
4107         int line_count, line_size;
4108         int small, large;
4109         int entries;
4110
4111         if (!latency_ns) {
4112                 *fbc_wm = *display_wm = *cursor_wm = 0;
4113                 return false;
4114         }
4115
4116         crtc = intel_get_crtc_for_plane(dev, plane);
4117         hdisplay = crtc->mode.hdisplay;
4118         htotal = crtc->mode.htotal;
4119         clock = crtc->mode.clock;
4120         pixel_size = crtc->fb->bits_per_pixel / 8;
4121
4122         line_time_us = (htotal * 1000) / clock;
4123         line_count = (latency_ns / line_time_us + 1000) / 1000;
4124         line_size = hdisplay * pixel_size;
4125
4126         /* Use the minimum of the small and large buffer method for primary */
4127         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4128         large = line_count * line_size;
4129
4130         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4131         *display_wm = entries + display->guard_size;
4132
4133         /*
4134          * Spec says:
4135          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4136          */
4137         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4138
4139         /* calculate the self-refresh watermark for display cursor */
4140         entries = line_count * pixel_size * 64;
4141         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4142         *cursor_wm = entries + cursor->guard_size;
4143
4144         return ironlake_check_srwm(dev, level,
4145                                    *fbc_wm, *display_wm, *cursor_wm,
4146                                    display, cursor);
4147 }
4148
4149 static void ironlake_update_wm(struct drm_device *dev)
4150 {
4151         struct drm_i915_private *dev_priv = dev->dev_private;
4152         int fbc_wm, plane_wm, cursor_wm;
4153         unsigned int enabled;
4154
4155         enabled = 0;
4156         if (g4x_compute_wm0(dev, 0,
4157                             &ironlake_display_wm_info,
4158                             ILK_LP0_PLANE_LATENCY,
4159                             &ironlake_cursor_wm_info,
4160                             ILK_LP0_CURSOR_LATENCY,
4161                             &plane_wm, &cursor_wm)) {
4162                 I915_WRITE(WM0_PIPEA_ILK,
4163                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4164                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4165                               " plane %d, " "cursor: %d\n",
4166                               plane_wm, cursor_wm);
4167                 enabled |= 1;
4168         }
4169
4170         if (g4x_compute_wm0(dev, 1,
4171                             &ironlake_display_wm_info,
4172                             ILK_LP0_PLANE_LATENCY,
4173                             &ironlake_cursor_wm_info,
4174                             ILK_LP0_CURSOR_LATENCY,
4175                             &plane_wm, &cursor_wm)) {
4176                 I915_WRITE(WM0_PIPEB_ILK,
4177                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4178                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4179                               " plane %d, cursor: %d\n",
4180                               plane_wm, cursor_wm);
4181                 enabled |= 2;
4182         }
4183
4184         /*
4185          * Calculate and update the self-refresh watermark only when one
4186          * display plane is used.
4187          */
4188         I915_WRITE(WM3_LP_ILK, 0);
4189         I915_WRITE(WM2_LP_ILK, 0);
4190         I915_WRITE(WM1_LP_ILK, 0);
4191
4192         if (!single_plane_enabled(enabled))
4193                 return;
4194         enabled = ffs(enabled) - 1;
4195
4196         /* WM1 */
4197         if (!ironlake_compute_srwm(dev, 1, enabled,
4198                                    ILK_READ_WM1_LATENCY() * 500,
4199                                    &ironlake_display_srwm_info,
4200                                    &ironlake_cursor_srwm_info,
4201                                    &fbc_wm, &plane_wm, &cursor_wm))
4202                 return;
4203
4204         I915_WRITE(WM1_LP_ILK,
4205                    WM1_LP_SR_EN |
4206                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4207                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4208                    (plane_wm << WM1_LP_SR_SHIFT) |
4209                    cursor_wm);
4210
4211         /* WM2 */
4212         if (!ironlake_compute_srwm(dev, 2, enabled,
4213                                    ILK_READ_WM2_LATENCY() * 500,
4214                                    &ironlake_display_srwm_info,
4215                                    &ironlake_cursor_srwm_info,
4216                                    &fbc_wm, &plane_wm, &cursor_wm))
4217                 return;
4218
4219         I915_WRITE(WM2_LP_ILK,
4220                    WM2_LP_EN |
4221                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4222                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4223                    (plane_wm << WM1_LP_SR_SHIFT) |
4224                    cursor_wm);
4225
4226         /*
4227          * WM3 is unsupported on ILK, probably because we don't have latency
4228          * data for that power state
4229          */
4230 }
4231
4232 static void sandybridge_update_wm(struct drm_device *dev)
4233 {
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4236         int fbc_wm, plane_wm, cursor_wm;
4237         unsigned int enabled;
4238
4239         enabled = 0;
4240         if (g4x_compute_wm0(dev, 0,
4241                             &sandybridge_display_wm_info, latency,
4242                             &sandybridge_cursor_wm_info, latency,
4243                             &plane_wm, &cursor_wm)) {
4244                 I915_WRITE(WM0_PIPEA_ILK,
4245                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4246                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4247                               " plane %d, " "cursor: %d\n",
4248                               plane_wm, cursor_wm);
4249                 enabled |= 1;
4250         }
4251
4252         if (g4x_compute_wm0(dev, 1,
4253                             &sandybridge_display_wm_info, latency,
4254                             &sandybridge_cursor_wm_info, latency,
4255                             &plane_wm, &cursor_wm)) {
4256                 I915_WRITE(WM0_PIPEB_ILK,
4257                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4258                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4259                               " plane %d, cursor: %d\n",
4260                               plane_wm, cursor_wm);
4261                 enabled |= 2;
4262         }
4263
4264         /*
4265          * Calculate and update the self-refresh watermark only when one
4266          * display plane is used.
4267          *
4268          * SNB support 3 levels of watermark.
4269          *
4270          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4271          * and disabled in the descending order
4272          *
4273          */
4274         I915_WRITE(WM3_LP_ILK, 0);
4275         I915_WRITE(WM2_LP_ILK, 0);
4276         I915_WRITE(WM1_LP_ILK, 0);
4277
4278         if (!single_plane_enabled(enabled))
4279                 return;
4280         enabled = ffs(enabled) - 1;
4281
4282         /* WM1 */
4283         if (!ironlake_compute_srwm(dev, 1, enabled,
4284                                    SNB_READ_WM1_LATENCY() * 500,
4285                                    &sandybridge_display_srwm_info,
4286                                    &sandybridge_cursor_srwm_info,
4287                                    &fbc_wm, &plane_wm, &cursor_wm))
4288                 return;
4289
4290         I915_WRITE(WM1_LP_ILK,
4291                    WM1_LP_SR_EN |
4292                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4293                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4294                    (plane_wm << WM1_LP_SR_SHIFT) |
4295                    cursor_wm);
4296
4297         /* WM2 */
4298         if (!ironlake_compute_srwm(dev, 2, enabled,
4299                                    SNB_READ_WM2_LATENCY() * 500,
4300                                    &sandybridge_display_srwm_info,
4301                                    &sandybridge_cursor_srwm_info,
4302                                    &fbc_wm, &plane_wm, &cursor_wm))
4303                 return;
4304
4305         I915_WRITE(WM2_LP_ILK,
4306                    WM2_LP_EN |
4307                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4308                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4309                    (plane_wm << WM1_LP_SR_SHIFT) |
4310                    cursor_wm);
4311
4312         /* WM3 */
4313         if (!ironlake_compute_srwm(dev, 3, enabled,
4314                                    SNB_READ_WM3_LATENCY() * 500,
4315                                    &sandybridge_display_srwm_info,
4316                                    &sandybridge_cursor_srwm_info,
4317                                    &fbc_wm, &plane_wm, &cursor_wm))
4318                 return;
4319
4320         I915_WRITE(WM3_LP_ILK,
4321                    WM3_LP_EN |
4322                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4323                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4324                    (plane_wm << WM1_LP_SR_SHIFT) |
4325                    cursor_wm);
4326 }
4327
4328 /**
4329  * intel_update_watermarks - update FIFO watermark values based on current modes
4330  *
4331  * Calculate watermark values for the various WM regs based on current mode
4332  * and plane configuration.
4333  *
4334  * There are several cases to deal with here:
4335  *   - normal (i.e. non-self-refresh)
4336  *   - self-refresh (SR) mode
4337  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4338  *   - lines are small relative to FIFO size (buffer can hold more than 2
4339  *     lines), so need to account for TLB latency
4340  *
4341  *   The normal calculation is:
4342  *     watermark = dotclock * bytes per pixel * latency
4343  *   where latency is platform & configuration dependent (we assume pessimal
4344  *   values here).
4345  *
4346  *   The SR calculation is:
4347  *     watermark = (trunc(latency/line time)+1) * surface width *
4348  *       bytes per pixel
4349  *   where
4350  *     line time = htotal / dotclock
4351  *     surface width = hdisplay for normal plane and 64 for cursor
4352  *   and latency is assumed to be high, as above.
4353  *
4354  * The final value programmed to the register should always be rounded up,
4355  * and include an extra 2 entries to account for clock crossings.
4356  *
4357  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4358  * to set the non-SR watermarks to 8.
4359  */
4360 static void intel_update_watermarks(struct drm_device *dev)
4361 {
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363
4364         if (dev_priv->display.update_wm)
4365                 dev_priv->display.update_wm(dev);
4366 }
4367
4368 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4369 {
4370         return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4371                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4372 }
4373
4374 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4375                               struct drm_display_mode *mode,
4376                               struct drm_display_mode *adjusted_mode,
4377                               int x, int y,
4378                               struct drm_framebuffer *old_fb)
4379 {
4380         struct drm_device *dev = crtc->dev;
4381         struct drm_i915_private *dev_priv = dev->dev_private;
4382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4383         int pipe = intel_crtc->pipe;
4384         int plane = intel_crtc->plane;
4385         int refclk, num_connectors = 0;
4386         intel_clock_t clock, reduced_clock;
4387         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4388         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4389         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4390         struct drm_mode_config *mode_config = &dev->mode_config;
4391         struct intel_encoder *encoder;
4392         const intel_limit_t *limit;
4393         int ret;
4394         u32 temp;
4395         u32 lvds_sync = 0;
4396
4397         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4398                 if (encoder->base.crtc != crtc)
4399                         continue;
4400
4401                 switch (encoder->type) {
4402                 case INTEL_OUTPUT_LVDS:
4403                         is_lvds = true;
4404                         break;
4405                 case INTEL_OUTPUT_SDVO:
4406                 case INTEL_OUTPUT_HDMI:
4407                         is_sdvo = true;
4408                         if (encoder->needs_tv_clock)
4409                                 is_tv = true;
4410                         break;
4411                 case INTEL_OUTPUT_DVO:
4412                         is_dvo = true;
4413                         break;
4414                 case INTEL_OUTPUT_TVOUT:
4415                         is_tv = true;
4416                         break;
4417                 case INTEL_OUTPUT_ANALOG:
4418                         is_crt = true;
4419                         break;
4420                 case INTEL_OUTPUT_DISPLAYPORT:
4421                         is_dp = true;
4422                         break;
4423                 }
4424
4425                 num_connectors++;
4426         }
4427
4428         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4429                 refclk = dev_priv->lvds_ssc_freq * 1000;
4430                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4431                               refclk / 1000);
4432         } else if (!IS_GEN2(dev)) {
4433                 refclk = 96000;
4434         } else {
4435                 refclk = 48000;
4436         }
4437
4438         /*
4439          * Returns a set of divisors for the desired target clock with the given
4440          * refclk, or FALSE.  The returned values represent the clock equation:
4441          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4442          */
4443         limit = intel_limit(crtc, refclk);
4444         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4445         if (!ok) {
4446                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4447                 return -EINVAL;
4448         }
4449
4450         /* Ensure that the cursor is valid for the new mode before changing... */
4451         intel_crtc_update_cursor(crtc, true);
4452
4453         if (is_lvds && dev_priv->lvds_downclock_avail) {
4454                 has_reduced_clock = limit->find_pll(limit, crtc,
4455                                                     dev_priv->lvds_downclock,
4456                                                     refclk,
4457                                                     &reduced_clock);
4458                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4459                         /*
4460                          * If the different P is found, it means that we can't
4461                          * switch the display clock by using the FP0/FP1.
4462                          * In such case we will disable the LVDS downclock
4463                          * feature.
4464                          */
4465                         DRM_DEBUG_KMS("Different P is found for "
4466                                       "LVDS clock/downclock\n");
4467                         has_reduced_clock = 0;
4468                 }
4469         }
4470         /* SDVO TV has fixed PLL values depend on its clock range,
4471            this mirrors vbios setting. */
4472         if (is_sdvo && is_tv) {
4473                 if (adjusted_mode->clock >= 100000
4474                     && adjusted_mode->clock < 140500) {
4475                         clock.p1 = 2;
4476                         clock.p2 = 10;
4477                         clock.n = 3;
4478                         clock.m1 = 16;
4479                         clock.m2 = 8;
4480                 } else if (adjusted_mode->clock >= 140500
4481                            && adjusted_mode->clock <= 200000) {
4482                         clock.p1 = 1;
4483                         clock.p2 = 10;
4484                         clock.n = 6;
4485                         clock.m1 = 12;
4486                         clock.m2 = 8;
4487                 }
4488         }
4489
4490         if (IS_PINEVIEW(dev)) {
4491                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4492                 if (has_reduced_clock)
4493                         fp2 = (1 << reduced_clock.n) << 16 |
4494                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4495         } else {
4496                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4497                 if (has_reduced_clock)
4498                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4499                                 reduced_clock.m2;
4500         }
4501
4502         dpll = DPLL_VGA_MODE_DIS;
4503
4504         if (!IS_GEN2(dev)) {
4505                 if (is_lvds)
4506                         dpll |= DPLLB_MODE_LVDS;
4507                 else
4508                         dpll |= DPLLB_MODE_DAC_SERIAL;
4509                 if (is_sdvo) {
4510                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4511                         if (pixel_multiplier > 1) {
4512                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4513                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4514                         }
4515                         dpll |= DPLL_DVO_HIGH_SPEED;
4516                 }
4517                 if (is_dp)
4518                         dpll |= DPLL_DVO_HIGH_SPEED;
4519
4520                 /* compute bitmask from p1 value */
4521                 if (IS_PINEVIEW(dev))
4522                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4523                 else {
4524                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4525                         if (IS_G4X(dev) && has_reduced_clock)
4526                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4527                 }
4528                 switch (clock.p2) {
4529                 case 5:
4530                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4531                         break;
4532                 case 7:
4533                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4534                         break;
4535                 case 10:
4536                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4537                         break;
4538                 case 14:
4539                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4540                         break;
4541                 }
4542                 if (INTEL_INFO(dev)->gen >= 4)
4543                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4544         } else {
4545                 if (is_lvds) {
4546                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4547                 } else {
4548                         if (clock.p1 == 2)
4549                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4550                         else
4551                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4552                         if (clock.p2 == 4)
4553                                 dpll |= PLL_P2_DIVIDE_BY_4;
4554                 }
4555         }
4556
4557         if (is_sdvo && is_tv)
4558                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4559         else if (is_tv)
4560                 /* XXX: just matching BIOS for now */
4561                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4562                 dpll |= 3;
4563         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4564                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4565         else
4566                 dpll |= PLL_REF_INPUT_DREFCLK;
4567
4568         /* setup pipeconf */
4569         pipeconf = I915_READ(PIPECONF(pipe));
4570
4571         /* Set up the display plane register */
4572         dspcntr = DISPPLANE_GAMMA_ENABLE;
4573
4574         /* Ironlake's plane is forced to pipe, bit 24 is to
4575            enable color space conversion */
4576         if (pipe == 0)
4577                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4578         else
4579                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4580
4581         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4582                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4583                  * core speed.
4584                  *
4585                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4586                  * pipe == 0 check?
4587                  */
4588                 if (mode->clock >
4589                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4590                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4591                 else
4592                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4593         }
4594
4595         dpll |= DPLL_VCO_ENABLE;
4596
4597         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4598         drm_mode_debug_printmodeline(mode);
4599
4600         I915_WRITE(FP0(pipe), fp);
4601         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4602
4603         POSTING_READ(DPLL(pipe));
4604         udelay(150);
4605
4606         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4607          * This is an exception to the general rule that mode_set doesn't turn
4608          * things on.
4609          */
4610         if (is_lvds) {
4611                 temp = I915_READ(LVDS);
4612                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4613                 if (pipe == 1) {
4614                         temp |= LVDS_PIPEB_SELECT;
4615                 } else {
4616                         temp &= ~LVDS_PIPEB_SELECT;
4617                 }
4618                 /* set the corresponsding LVDS_BORDER bit */
4619                 temp |= dev_priv->lvds_border_bits;
4620                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4621                  * set the DPLLs for dual-channel mode or not.
4622                  */
4623                 if (clock.p2 == 7)
4624                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4625                 else
4626                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4627
4628                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4629                  * appropriately here, but we need to look more thoroughly into how
4630                  * panels behave in the two modes.
4631                  */
4632                 /* set the dithering flag on LVDS as needed */
4633                 if (INTEL_INFO(dev)->gen >= 4) {
4634                         if (dev_priv->lvds_dither)
4635                                 temp |= LVDS_ENABLE_DITHER;
4636                         else
4637                                 temp &= ~LVDS_ENABLE_DITHER;
4638                 }
4639                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4640                         lvds_sync |= LVDS_HSYNC_POLARITY;
4641                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4642                         lvds_sync |= LVDS_VSYNC_POLARITY;
4643                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4644                     != lvds_sync) {
4645                         char flags[2] = "-+";
4646                         DRM_INFO("Changing LVDS panel from "
4647                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4648                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4649                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4650                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4651                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4652                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4653                         temp |= lvds_sync;
4654                 }
4655                 I915_WRITE(LVDS, temp);
4656         }
4657
4658         if (is_dp) {
4659                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4660         }
4661
4662         I915_WRITE(DPLL(pipe), dpll);
4663
4664         /* Wait for the clocks to stabilize. */
4665         POSTING_READ(DPLL(pipe));
4666         udelay(150);
4667
4668         if (INTEL_INFO(dev)->gen >= 4) {
4669                 temp = 0;
4670                 if (is_sdvo) {
4671                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4672                         if (temp > 1)
4673                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4674                         else
4675                                 temp = 0;
4676                 }
4677                 I915_WRITE(DPLL_MD(pipe), temp);
4678         } else {
4679                 /* The pixel multiplier can only be updated once the
4680                  * DPLL is enabled and the clocks are stable.
4681                  *
4682                  * So write it again.
4683                  */
4684                 I915_WRITE(DPLL(pipe), dpll);
4685         }
4686
4687         intel_crtc->lowfreq_avail = false;
4688         if (is_lvds && has_reduced_clock && i915_powersave) {
4689                 I915_WRITE(FP1(pipe), fp2);
4690                 intel_crtc->lowfreq_avail = true;
4691                 if (HAS_PIPE_CXSR(dev)) {
4692                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4693                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4694                 }
4695         } else {
4696                 I915_WRITE(FP1(pipe), fp);
4697                 if (HAS_PIPE_CXSR(dev)) {
4698                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4699                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4700                 }
4701         }
4702
4703         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4704                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4705                 /* the chip adds 2 halflines automatically */
4706                 adjusted_mode->crtc_vdisplay -= 1;
4707                 adjusted_mode->crtc_vtotal -= 1;
4708                 adjusted_mode->crtc_vblank_start -= 1;
4709                 adjusted_mode->crtc_vblank_end -= 1;
4710                 adjusted_mode->crtc_vsync_end -= 1;
4711                 adjusted_mode->crtc_vsync_start -= 1;
4712         } else
4713                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4714
4715         I915_WRITE(HTOTAL(pipe),
4716                    (adjusted_mode->crtc_hdisplay - 1) |
4717                    ((adjusted_mode->crtc_htotal - 1) << 16));
4718         I915_WRITE(HBLANK(pipe),
4719                    (adjusted_mode->crtc_hblank_start - 1) |
4720                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4721         I915_WRITE(HSYNC(pipe),
4722                    (adjusted_mode->crtc_hsync_start - 1) |
4723                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4724
4725         I915_WRITE(VTOTAL(pipe),
4726                    (adjusted_mode->crtc_vdisplay - 1) |
4727                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4728         I915_WRITE(VBLANK(pipe),
4729                    (adjusted_mode->crtc_vblank_start - 1) |
4730                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4731         I915_WRITE(VSYNC(pipe),
4732                    (adjusted_mode->crtc_vsync_start - 1) |
4733                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4734
4735         /* pipesrc and dspsize control the size that is scaled from,
4736          * which should always be the user's requested size.
4737          */
4738         I915_WRITE(DSPSIZE(plane),
4739                    ((mode->vdisplay - 1) << 16) |
4740                    (mode->hdisplay - 1));
4741         I915_WRITE(DSPPOS(plane), 0);
4742         I915_WRITE(PIPESRC(pipe),
4743                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4744
4745         I915_WRITE(PIPECONF(pipe), pipeconf);
4746         POSTING_READ(PIPECONF(pipe));
4747         intel_enable_pipe(dev_priv, pipe, false);
4748
4749         intel_wait_for_vblank(dev, pipe);
4750
4751         I915_WRITE(DSPCNTR(plane), dspcntr);
4752         POSTING_READ(DSPCNTR(plane));
4753         intel_enable_plane(dev_priv, plane, pipe);
4754
4755         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4756
4757         intel_update_watermarks(dev);
4758
4759         return ret;
4760 }
4761
4762 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4763                                   struct drm_display_mode *mode,
4764                                   struct drm_display_mode *adjusted_mode,
4765                                   int x, int y,
4766                                   struct drm_framebuffer *old_fb)
4767 {
4768         struct drm_device *dev = crtc->dev;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771         int pipe = intel_crtc->pipe;
4772         int plane = intel_crtc->plane;
4773         int refclk, num_connectors = 0;
4774         intel_clock_t clock, reduced_clock;
4775         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4776         bool ok, has_reduced_clock = false, is_sdvo = false;
4777         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4778         struct intel_encoder *has_edp_encoder = NULL;
4779         struct drm_mode_config *mode_config = &dev->mode_config;
4780         struct intel_encoder *encoder;
4781         const intel_limit_t *limit;
4782         int ret;
4783         struct fdi_m_n m_n = {0};
4784         u32 temp;
4785         u32 lvds_sync = 0;
4786         int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4787
4788         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4789                 if (encoder->base.crtc != crtc)
4790                         continue;
4791
4792                 switch (encoder->type) {
4793                 case INTEL_OUTPUT_LVDS:
4794                         is_lvds = true;
4795                         break;
4796                 case INTEL_OUTPUT_SDVO:
4797                 case INTEL_OUTPUT_HDMI:
4798                         is_sdvo = true;
4799                         if (encoder->needs_tv_clock)
4800                                 is_tv = true;
4801                         break;
4802                 case INTEL_OUTPUT_TVOUT:
4803                         is_tv = true;
4804                         break;
4805                 case INTEL_OUTPUT_ANALOG:
4806                         is_crt = true;
4807                         break;
4808                 case INTEL_OUTPUT_DISPLAYPORT:
4809                         is_dp = true;
4810                         break;
4811                 case INTEL_OUTPUT_EDP:
4812                         has_edp_encoder = encoder;
4813                         break;
4814                 }
4815
4816                 num_connectors++;
4817         }
4818
4819         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4820                 refclk = dev_priv->lvds_ssc_freq * 1000;
4821                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4822                               refclk / 1000);
4823         } else {
4824                 refclk = 96000;
4825                 if (!has_edp_encoder ||
4826                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
4827                         refclk = 120000; /* 120Mhz refclk */
4828         }
4829
4830         /*
4831          * Returns a set of divisors for the desired target clock with the given
4832          * refclk, or FALSE.  The returned values represent the clock equation:
4833          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4834          */
4835         limit = intel_limit(crtc, refclk);
4836         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4837         if (!ok) {
4838                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4839                 return -EINVAL;
4840         }
4841
4842         /* Ensure that the cursor is valid for the new mode before changing... */
4843         intel_crtc_update_cursor(crtc, true);
4844
4845         if (is_lvds && dev_priv->lvds_downclock_avail) {
4846                 has_reduced_clock = limit->find_pll(limit, crtc,
4847                                                     dev_priv->lvds_downclock,
4848                                                     refclk,
4849                                                     &reduced_clock);
4850                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4851                         /*
4852                          * If the different P is found, it means that we can't
4853                          * switch the display clock by using the FP0/FP1.
4854                          * In such case we will disable the LVDS downclock
4855                          * feature.
4856                          */
4857                         DRM_DEBUG_KMS("Different P is found for "
4858                                       "LVDS clock/downclock\n");
4859                         has_reduced_clock = 0;
4860                 }
4861         }
4862         /* SDVO TV has fixed PLL values depend on its clock range,
4863            this mirrors vbios setting. */
4864         if (is_sdvo && is_tv) {
4865                 if (adjusted_mode->clock >= 100000
4866                     && adjusted_mode->clock < 140500) {
4867                         clock.p1 = 2;
4868                         clock.p2 = 10;
4869                         clock.n = 3;
4870                         clock.m1 = 16;
4871                         clock.m2 = 8;
4872                 } else if (adjusted_mode->clock >= 140500
4873                            && adjusted_mode->clock <= 200000) {
4874                         clock.p1 = 1;
4875                         clock.p2 = 10;
4876                         clock.n = 6;
4877                         clock.m1 = 12;
4878                         clock.m2 = 8;
4879                 }
4880         }
4881
4882         /* FDI link */
4883         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4884         lane = 0;
4885         /* CPU eDP doesn't require FDI link, so just set DP M/N
4886            according to current link config */
4887         if (has_edp_encoder &&
4888             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4889                 target_clock = mode->clock;
4890                 intel_edp_link_config(has_edp_encoder,
4891                                       &lane, &link_bw);
4892         } else {
4893                 /* [e]DP over FDI requires target mode clock
4894                    instead of link clock */
4895                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4896                         target_clock = mode->clock;
4897                 else
4898                         target_clock = adjusted_mode->clock;
4899
4900                 /* FDI is a binary signal running at ~2.7GHz, encoding
4901                  * each output octet as 10 bits. The actual frequency
4902                  * is stored as a divider into a 100MHz clock, and the
4903                  * mode pixel clock is stored in units of 1KHz.
4904                  * Hence the bw of each lane in terms of the mode signal
4905                  * is:
4906                  */
4907                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4908         }
4909
4910         /* determine panel color depth */
4911         temp = I915_READ(PIPECONF(pipe));
4912         temp &= ~PIPE_BPC_MASK;
4913         if (is_lvds) {
4914                 /* the BPC will be 6 if it is 18-bit LVDS panel */
4915                 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4916                         temp |= PIPE_8BPC;
4917                 else
4918                         temp |= PIPE_6BPC;
4919         } else if (has_edp_encoder) {
4920                 switch (dev_priv->edp.bpp/3) {
4921                 case 8:
4922                         temp |= PIPE_8BPC;
4923                         break;
4924                 case 10:
4925                         temp |= PIPE_10BPC;
4926                         break;
4927                 case 6:
4928                         temp |= PIPE_6BPC;
4929                         break;
4930                 case 12:
4931                         temp |= PIPE_12BPC;
4932                         break;
4933                 }
4934         } else
4935                 temp |= PIPE_8BPC;
4936         I915_WRITE(PIPECONF(pipe), temp);
4937
4938         switch (temp & PIPE_BPC_MASK) {
4939         case PIPE_8BPC:
4940                 bpp = 24;
4941                 break;
4942         case PIPE_10BPC:
4943                 bpp = 30;
4944                 break;
4945         case PIPE_6BPC:
4946                 bpp = 18;
4947                 break;
4948         case PIPE_12BPC:
4949                 bpp = 36;
4950                 break;
4951         default:
4952                 DRM_ERROR("unknown pipe bpc value\n");
4953                 bpp = 24;
4954         }
4955
4956         if (!lane) {
4957                 /*
4958                  * Account for spread spectrum to avoid
4959                  * oversubscribing the link. Max center spread
4960                  * is 2.5%; use 5% for safety's sake.
4961                  */
4962                 u32 bps = target_clock * bpp * 21 / 20;
4963                 lane = bps / (link_bw * 8) + 1;
4964         }
4965
4966         intel_crtc->fdi_lanes = lane;
4967
4968         if (pixel_multiplier > 1)
4969                 link_bw *= pixel_multiplier;
4970         ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4971
4972         /* Ironlake: try to setup display ref clock before DPLL
4973          * enabling. This is only under driver's control after
4974          * PCH B stepping, previous chipset stepping should be
4975          * ignoring this setting.
4976          */
4977         temp = I915_READ(PCH_DREF_CONTROL);
4978         /* Always enable nonspread source */
4979         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4980         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4981         temp &= ~DREF_SSC_SOURCE_MASK;
4982         temp |= DREF_SSC_SOURCE_ENABLE;
4983         I915_WRITE(PCH_DREF_CONTROL, temp);
4984
4985         POSTING_READ(PCH_DREF_CONTROL);
4986         udelay(200);
4987
4988         if (has_edp_encoder) {
4989                 if (intel_panel_use_ssc(dev_priv)) {
4990                         temp |= DREF_SSC1_ENABLE;
4991                         I915_WRITE(PCH_DREF_CONTROL, temp);
4992
4993                         POSTING_READ(PCH_DREF_CONTROL);
4994                         udelay(200);
4995                 }
4996                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4997
4998                 /* Enable CPU source on CPU attached eDP */
4999                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5000                         if (intel_panel_use_ssc(dev_priv))
5001                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5002                         else
5003                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5004                 } else {
5005                         /* Enable SSC on PCH eDP if needed */
5006                         if (intel_panel_use_ssc(dev_priv)) {
5007                                 DRM_ERROR("enabling SSC on PCH\n");
5008                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5009                         }
5010                 }
5011                 I915_WRITE(PCH_DREF_CONTROL, temp);
5012                 POSTING_READ(PCH_DREF_CONTROL);
5013                 udelay(200);
5014         }
5015
5016         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5017         if (has_reduced_clock)
5018                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5019                         reduced_clock.m2;
5020
5021         /* Enable autotuning of the PLL clock (if permissible) */
5022         factor = 21;
5023         if (is_lvds) {
5024                 if ((intel_panel_use_ssc(dev_priv) &&
5025                      dev_priv->lvds_ssc_freq == 100) ||
5026                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5027                         factor = 25;
5028         } else if (is_sdvo && is_tv)
5029                 factor = 20;
5030
5031         if (clock.m < factor * clock.n)
5032                 fp |= FP_CB_TUNE;
5033
5034         dpll = 0;
5035
5036         if (is_lvds)
5037                 dpll |= DPLLB_MODE_LVDS;
5038         else
5039                 dpll |= DPLLB_MODE_DAC_SERIAL;
5040         if (is_sdvo) {
5041                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5042                 if (pixel_multiplier > 1) {
5043                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5044                 }
5045                 dpll |= DPLL_DVO_HIGH_SPEED;
5046         }
5047         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5048                 dpll |= DPLL_DVO_HIGH_SPEED;
5049
5050         /* compute bitmask from p1 value */
5051         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5052         /* also FPA1 */
5053         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5054
5055         switch (clock.p2) {
5056         case 5:
5057                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5058                 break;
5059         case 7:
5060                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5061                 break;
5062         case 10:
5063                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5064                 break;
5065         case 14:
5066                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5067                 break;
5068         }
5069
5070         if (is_sdvo && is_tv)
5071                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5072         else if (is_tv)
5073                 /* XXX: just matching BIOS for now */
5074                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5075                 dpll |= 3;
5076         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5077                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5078         else
5079                 dpll |= PLL_REF_INPUT_DREFCLK;
5080
5081         /* setup pipeconf */
5082         pipeconf = I915_READ(PIPECONF(pipe));
5083
5084         /* Set up the display plane register */
5085         dspcntr = DISPPLANE_GAMMA_ENABLE;
5086
5087         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5088         drm_mode_debug_printmodeline(mode);
5089
5090         /* PCH eDP needs FDI, but CPU eDP does not */
5091         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5092                 I915_WRITE(PCH_FP0(pipe), fp);
5093                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5094
5095                 POSTING_READ(PCH_DPLL(pipe));
5096                 udelay(150);
5097         }
5098
5099         /* enable transcoder DPLL */
5100         if (HAS_PCH_CPT(dev)) {
5101                 temp = I915_READ(PCH_DPLL_SEL);
5102                 switch (pipe) {
5103                 case 0:
5104                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5105                         break;
5106                 case 1:
5107                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5108                         break;
5109                 case 2:
5110                         /* FIXME: manage transcoder PLLs? */
5111                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5112                         break;
5113                 default:
5114                         BUG();
5115                 }
5116                 I915_WRITE(PCH_DPLL_SEL, temp);
5117
5118                 POSTING_READ(PCH_DPLL_SEL);
5119                 udelay(150);
5120         }
5121
5122         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5123          * This is an exception to the general rule that mode_set doesn't turn
5124          * things on.
5125          */
5126         if (is_lvds) {
5127                 temp = I915_READ(PCH_LVDS);
5128                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5129                 if (pipe == 1) {
5130                         if (HAS_PCH_CPT(dev))
5131                                 temp |= PORT_TRANS_B_SEL_CPT;
5132                         else
5133                                 temp |= LVDS_PIPEB_SELECT;
5134                 } else {
5135                         if (HAS_PCH_CPT(dev))
5136                                 temp &= ~PORT_TRANS_SEL_MASK;
5137                         else
5138                                 temp &= ~LVDS_PIPEB_SELECT;
5139                 }
5140                 /* set the corresponsding LVDS_BORDER bit */
5141                 temp |= dev_priv->lvds_border_bits;
5142                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5143                  * set the DPLLs for dual-channel mode or not.
5144                  */
5145                 if (clock.p2 == 7)
5146                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5147                 else
5148                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5149
5150                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5151                  * appropriately here, but we need to look more thoroughly into how
5152                  * panels behave in the two modes.
5153                  */
5154                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5155                         lvds_sync |= LVDS_HSYNC_POLARITY;
5156                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5157                         lvds_sync |= LVDS_VSYNC_POLARITY;
5158                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5159                     != lvds_sync) {
5160                         char flags[2] = "-+";
5161                         DRM_INFO("Changing LVDS panel from "
5162                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5163                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5164                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5165                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5166                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5167                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5168                         temp |= lvds_sync;
5169                 }
5170                 I915_WRITE(PCH_LVDS, temp);
5171         }
5172
5173         /* set the dithering flag and clear for anything other than a panel. */
5174         pipeconf &= ~PIPECONF_DITHER_EN;
5175         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5176         if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5177                 pipeconf |= PIPECONF_DITHER_EN;
5178                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5179         }
5180
5181         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5182                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5183         } else {
5184                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5185                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5186                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5187                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5188                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5189         }
5190
5191         if (!has_edp_encoder ||
5192             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5193                 I915_WRITE(PCH_DPLL(pipe), dpll);
5194
5195                 /* Wait for the clocks to stabilize. */
5196                 POSTING_READ(PCH_DPLL(pipe));
5197                 udelay(150);
5198
5199                 /* The pixel multiplier can only be updated once the
5200                  * DPLL is enabled and the clocks are stable.
5201                  *
5202                  * So write it again.
5203                  */
5204                 I915_WRITE(PCH_DPLL(pipe), dpll);
5205         }
5206
5207         intel_crtc->lowfreq_avail = false;
5208         if (is_lvds && has_reduced_clock && i915_powersave) {
5209                 I915_WRITE(PCH_FP1(pipe), fp2);
5210                 intel_crtc->lowfreq_avail = true;
5211                 if (HAS_PIPE_CXSR(dev)) {
5212                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5213                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5214                 }
5215         } else {
5216                 I915_WRITE(PCH_FP1(pipe), fp);
5217                 if (HAS_PIPE_CXSR(dev)) {
5218                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5219                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5220                 }
5221         }
5222
5223         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5224                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5225                 /* the chip adds 2 halflines automatically */
5226                 adjusted_mode->crtc_vdisplay -= 1;
5227                 adjusted_mode->crtc_vtotal -= 1;
5228                 adjusted_mode->crtc_vblank_start -= 1;
5229                 adjusted_mode->crtc_vblank_end -= 1;
5230                 adjusted_mode->crtc_vsync_end -= 1;
5231                 adjusted_mode->crtc_vsync_start -= 1;
5232         } else
5233                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5234
5235         I915_WRITE(HTOTAL(pipe),
5236                    (adjusted_mode->crtc_hdisplay - 1) |
5237                    ((adjusted_mode->crtc_htotal - 1) << 16));
5238         I915_WRITE(HBLANK(pipe),
5239                    (adjusted_mode->crtc_hblank_start - 1) |
5240                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5241         I915_WRITE(HSYNC(pipe),
5242                    (adjusted_mode->crtc_hsync_start - 1) |
5243                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5244
5245         I915_WRITE(VTOTAL(pipe),
5246                    (adjusted_mode->crtc_vdisplay - 1) |
5247                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5248         I915_WRITE(VBLANK(pipe),
5249                    (adjusted_mode->crtc_vblank_start - 1) |
5250                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5251         I915_WRITE(VSYNC(pipe),
5252                    (adjusted_mode->crtc_vsync_start - 1) |
5253                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5254
5255         /* pipesrc controls the size that is scaled from, which should
5256          * always be the user's requested size.
5257          */
5258         I915_WRITE(PIPESRC(pipe),
5259                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5260
5261         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5262         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5263         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5264         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5265
5266         if (has_edp_encoder &&
5267             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5268                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5269         }
5270
5271         I915_WRITE(PIPECONF(pipe), pipeconf);
5272         POSTING_READ(PIPECONF(pipe));
5273
5274         intel_wait_for_vblank(dev, pipe);
5275
5276         if (IS_GEN5(dev)) {
5277                 /* enable address swizzle for tiling buffer */
5278                 temp = I915_READ(DISP_ARB_CTL);
5279                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5280         }
5281
5282         I915_WRITE(DSPCNTR(plane), dspcntr);
5283         POSTING_READ(DSPCNTR(plane));
5284
5285         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5286
5287         intel_update_watermarks(dev);
5288
5289         return ret;
5290 }
5291
5292 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5293                                struct drm_display_mode *mode,
5294                                struct drm_display_mode *adjusted_mode,
5295                                int x, int y,
5296                                struct drm_framebuffer *old_fb)
5297 {
5298         struct drm_device *dev = crtc->dev;
5299         struct drm_i915_private *dev_priv = dev->dev_private;
5300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5301         int pipe = intel_crtc->pipe;
5302         int ret;
5303
5304         drm_vblank_pre_modeset(dev, pipe);
5305
5306         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5307                                               x, y, old_fb);
5308
5309         drm_vblank_post_modeset(dev, pipe);
5310
5311         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5312
5313         return ret;
5314 }
5315
5316 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5317 void intel_crtc_load_lut(struct drm_crtc *crtc)
5318 {
5319         struct drm_device *dev = crtc->dev;
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322         int palreg = PALETTE(intel_crtc->pipe);
5323         int i;
5324
5325         /* The clocks have to be on to load the palette. */
5326         if (!crtc->enabled)
5327                 return;
5328
5329         /* use legacy palette for Ironlake */
5330         if (HAS_PCH_SPLIT(dev))
5331                 palreg = LGC_PALETTE(intel_crtc->pipe);
5332
5333         for (i = 0; i < 256; i++) {
5334                 I915_WRITE(palreg + 4 * i,
5335                            (intel_crtc->lut_r[i] << 16) |
5336                            (intel_crtc->lut_g[i] << 8) |
5337                            intel_crtc->lut_b[i]);
5338         }
5339 }
5340
5341 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5346         bool visible = base != 0;
5347         u32 cntl;
5348
5349         if (intel_crtc->cursor_visible == visible)
5350                 return;
5351
5352         cntl = I915_READ(_CURACNTR);
5353         if (visible) {
5354                 /* On these chipsets we can only modify the base whilst
5355                  * the cursor is disabled.
5356                  */
5357                 I915_WRITE(_CURABASE, base);
5358
5359                 cntl &= ~(CURSOR_FORMAT_MASK);
5360                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5361                 cntl |= CURSOR_ENABLE |
5362                         CURSOR_GAMMA_ENABLE |
5363                         CURSOR_FORMAT_ARGB;
5364         } else
5365                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5366         I915_WRITE(_CURACNTR, cntl);
5367
5368         intel_crtc->cursor_visible = visible;
5369 }
5370
5371 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5372 {
5373         struct drm_device *dev = crtc->dev;
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376         int pipe = intel_crtc->pipe;
5377         bool visible = base != 0;
5378
5379         if (intel_crtc->cursor_visible != visible) {
5380                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5381                 if (base) {
5382                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5383                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5384                         cntl |= pipe << 28; /* Connect to correct pipe */
5385                 } else {
5386                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5387                         cntl |= CURSOR_MODE_DISABLE;
5388                 }
5389                 I915_WRITE(CURCNTR(pipe), cntl);
5390
5391                 intel_crtc->cursor_visible = visible;
5392         }
5393         /* and commit changes on next vblank */
5394         I915_WRITE(CURBASE(pipe), base);
5395 }
5396
5397 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5398 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5399                                      bool on)
5400 {
5401         struct drm_device *dev = crtc->dev;
5402         struct drm_i915_private *dev_priv = dev->dev_private;
5403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5404         int pipe = intel_crtc->pipe;
5405         int x = intel_crtc->cursor_x;
5406         int y = intel_crtc->cursor_y;
5407         u32 base, pos;
5408         bool visible;
5409
5410         pos = 0;
5411
5412         if (on && crtc->enabled && crtc->fb) {
5413                 base = intel_crtc->cursor_addr;
5414                 if (x > (int) crtc->fb->width)
5415                         base = 0;
5416
5417                 if (y > (int) crtc->fb->height)
5418                         base = 0;
5419         } else
5420                 base = 0;
5421
5422         if (x < 0) {
5423                 if (x + intel_crtc->cursor_width < 0)
5424                         base = 0;
5425
5426                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5427                 x = -x;
5428         }
5429         pos |= x << CURSOR_X_SHIFT;
5430
5431         if (y < 0) {
5432                 if (y + intel_crtc->cursor_height < 0)
5433                         base = 0;
5434
5435                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5436                 y = -y;
5437         }
5438         pos |= y << CURSOR_Y_SHIFT;
5439
5440         visible = base != 0;
5441         if (!visible && !intel_crtc->cursor_visible)
5442                 return;
5443
5444         I915_WRITE(CURPOS(pipe), pos);
5445         if (IS_845G(dev) || IS_I865G(dev))
5446                 i845_update_cursor(crtc, base);
5447         else
5448                 i9xx_update_cursor(crtc, base);
5449
5450         if (visible)
5451                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5452 }
5453
5454 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5455                                  struct drm_file *file,
5456                                  uint32_t handle,
5457                                  uint32_t width, uint32_t height)
5458 {
5459         struct drm_device *dev = crtc->dev;
5460         struct drm_i915_private *dev_priv = dev->dev_private;
5461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5462         struct drm_i915_gem_object *obj;
5463         uint32_t addr;
5464         int ret;
5465
5466         DRM_DEBUG_KMS("\n");
5467
5468         /* if we want to turn off the cursor ignore width and height */
5469         if (!handle) {
5470                 DRM_DEBUG_KMS("cursor off\n");
5471                 addr = 0;
5472                 obj = NULL;
5473                 mutex_lock(&dev->struct_mutex);
5474                 goto finish;
5475         }
5476
5477         /* Currently we only support 64x64 cursors */
5478         if (width != 64 || height != 64) {
5479                 DRM_ERROR("we currently only support 64x64 cursors\n");
5480                 return -EINVAL;
5481         }
5482
5483         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5484         if (&obj->base == NULL)
5485                 return -ENOENT;
5486
5487         if (obj->base.size < width * height * 4) {
5488                 DRM_ERROR("buffer is to small\n");
5489                 ret = -ENOMEM;
5490                 goto fail;
5491         }
5492
5493         /* we only need to pin inside GTT if cursor is non-phy */
5494         mutex_lock(&dev->struct_mutex);
5495         if (!dev_priv->info->cursor_needs_physical) {
5496                 if (obj->tiling_mode) {
5497                         DRM_ERROR("cursor cannot be tiled\n");
5498                         ret = -EINVAL;
5499                         goto fail_locked;
5500                 }
5501
5502                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5503                 if (ret) {
5504                         DRM_ERROR("failed to pin cursor bo\n");
5505                         goto fail_locked;
5506                 }
5507
5508                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5509                 if (ret) {
5510                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5511                         goto fail_unpin;
5512                 }
5513
5514                 ret = i915_gem_object_put_fence(obj);
5515                 if (ret) {
5516                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5517                         goto fail_unpin;
5518                 }
5519
5520                 addr = obj->gtt_offset;
5521         } else {
5522                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5523                 ret = i915_gem_attach_phys_object(dev, obj,
5524                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5525                                                   align);
5526                 if (ret) {
5527                         DRM_ERROR("failed to attach phys object\n");
5528                         goto fail_locked;
5529                 }
5530                 addr = obj->phys_obj->handle->busaddr;
5531         }
5532
5533         if (IS_GEN2(dev))
5534                 I915_WRITE(CURSIZE, (height << 12) | width);
5535
5536  finish:
5537         if (intel_crtc->cursor_bo) {
5538                 if (dev_priv->info->cursor_needs_physical) {
5539                         if (intel_crtc->cursor_bo != obj)
5540                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5541                 } else
5542                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5543                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5544         }
5545
5546         mutex_unlock(&dev->struct_mutex);
5547
5548         intel_crtc->cursor_addr = addr;
5549         intel_crtc->cursor_bo = obj;
5550         intel_crtc->cursor_width = width;
5551         intel_crtc->cursor_height = height;
5552
5553         intel_crtc_update_cursor(crtc, true);
5554
5555         return 0;
5556 fail_unpin:
5557         i915_gem_object_unpin(obj);
5558 fail_locked:
5559         mutex_unlock(&dev->struct_mutex);
5560 fail:
5561         drm_gem_object_unreference_unlocked(&obj->base);
5562         return ret;
5563 }
5564
5565 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5566 {
5567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5568
5569         intel_crtc->cursor_x = x;
5570         intel_crtc->cursor_y = y;
5571
5572         intel_crtc_update_cursor(crtc, true);
5573
5574         return 0;
5575 }
5576
5577 /** Sets the color ramps on behalf of RandR */
5578 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5579                                  u16 blue, int regno)
5580 {
5581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5582
5583         intel_crtc->lut_r[regno] = red >> 8;
5584         intel_crtc->lut_g[regno] = green >> 8;
5585         intel_crtc->lut_b[regno] = blue >> 8;
5586 }
5587
5588 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5589                              u16 *blue, int regno)
5590 {
5591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5592
5593         *red = intel_crtc->lut_r[regno] << 8;
5594         *green = intel_crtc->lut_g[regno] << 8;
5595         *blue = intel_crtc->lut_b[regno] << 8;
5596 }
5597
5598 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5599                                  u16 *blue, uint32_t start, uint32_t size)
5600 {
5601         int end = (start + size > 256) ? 256 : start + size, i;
5602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603
5604         for (i = start; i < end; i++) {
5605                 intel_crtc->lut_r[i] = red[i] >> 8;
5606                 intel_crtc->lut_g[i] = green[i] >> 8;
5607                 intel_crtc->lut_b[i] = blue[i] >> 8;
5608         }
5609
5610         intel_crtc_load_lut(crtc);
5611 }
5612
5613 /**
5614  * Get a pipe with a simple mode set on it for doing load-based monitor
5615  * detection.
5616  *
5617  * It will be up to the load-detect code to adjust the pipe as appropriate for
5618  * its requirements.  The pipe will be connected to no other encoders.
5619  *
5620  * Currently this code will only succeed if there is a pipe with no encoders
5621  * configured for it.  In the future, it could choose to temporarily disable
5622  * some outputs to free up a pipe for its use.
5623  *
5624  * \return crtc, or NULL if no pipes are available.
5625  */
5626
5627 /* VESA 640x480x72Hz mode to set on the pipe */
5628 static struct drm_display_mode load_detect_mode = {
5629         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5630                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5631 };
5632
5633 static struct drm_framebuffer *
5634 intel_framebuffer_create(struct drm_device *dev,
5635                          struct drm_mode_fb_cmd *mode_cmd,
5636                          struct drm_i915_gem_object *obj)
5637 {
5638         struct intel_framebuffer *intel_fb;
5639         int ret;
5640
5641         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5642         if (!intel_fb) {
5643                 drm_gem_object_unreference_unlocked(&obj->base);
5644                 return ERR_PTR(-ENOMEM);
5645         }
5646
5647         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5648         if (ret) {
5649                 drm_gem_object_unreference_unlocked(&obj->base);
5650                 kfree(intel_fb);
5651                 return ERR_PTR(ret);
5652         }
5653
5654         return &intel_fb->base;
5655 }
5656
5657 static u32
5658 intel_framebuffer_pitch_for_width(int width, int bpp)
5659 {
5660         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5661         return ALIGN(pitch, 64);
5662 }
5663
5664 static u32
5665 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5666 {
5667         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5668         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5669 }
5670
5671 static struct drm_framebuffer *
5672 intel_framebuffer_create_for_mode(struct drm_device *dev,
5673                                   struct drm_display_mode *mode,
5674                                   int depth, int bpp)
5675 {
5676         struct drm_i915_gem_object *obj;
5677         struct drm_mode_fb_cmd mode_cmd;
5678
5679         obj = i915_gem_alloc_object(dev,
5680                                     intel_framebuffer_size_for_mode(mode, bpp));
5681         if (obj == NULL)
5682                 return ERR_PTR(-ENOMEM);
5683
5684         mode_cmd.width = mode->hdisplay;
5685         mode_cmd.height = mode->vdisplay;
5686         mode_cmd.depth = depth;
5687         mode_cmd.bpp = bpp;
5688         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5689
5690         return intel_framebuffer_create(dev, &mode_cmd, obj);
5691 }
5692
5693 static struct drm_framebuffer *
5694 mode_fits_in_fbdev(struct drm_device *dev,
5695                    struct drm_display_mode *mode)
5696 {
5697         struct drm_i915_private *dev_priv = dev->dev_private;
5698         struct drm_i915_gem_object *obj;
5699         struct drm_framebuffer *fb;
5700
5701         if (dev_priv->fbdev == NULL)
5702                 return NULL;
5703
5704         obj = dev_priv->fbdev->ifb.obj;
5705         if (obj == NULL)
5706                 return NULL;
5707
5708         fb = &dev_priv->fbdev->ifb.base;
5709         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5710                                                           fb->bits_per_pixel))
5711                 return NULL;
5712
5713         if (obj->base.size < mode->vdisplay * fb->pitch)
5714                 return NULL;
5715
5716         return fb;
5717 }
5718
5719 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5720                                 struct drm_connector *connector,
5721                                 struct drm_display_mode *mode,
5722                                 struct intel_load_detect_pipe *old)
5723 {
5724         struct intel_crtc *intel_crtc;
5725         struct drm_crtc *possible_crtc;
5726         struct drm_encoder *encoder = &intel_encoder->base;
5727         struct drm_crtc *crtc = NULL;
5728         struct drm_device *dev = encoder->dev;
5729         struct drm_framebuffer *old_fb;
5730         int i = -1;
5731
5732         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5733                       connector->base.id, drm_get_connector_name(connector),
5734                       encoder->base.id, drm_get_encoder_name(encoder));
5735
5736         /*
5737          * Algorithm gets a little messy:
5738          *
5739          *   - if the connector already has an assigned crtc, use it (but make
5740          *     sure it's on first)
5741          *
5742          *   - try to find the first unused crtc that can drive this connector,
5743          *     and use that if we find one
5744          */
5745
5746         /* See if we already have a CRTC for this connector */
5747         if (encoder->crtc) {
5748                 crtc = encoder->crtc;
5749
5750                 intel_crtc = to_intel_crtc(crtc);
5751                 old->dpms_mode = intel_crtc->dpms_mode;
5752                 old->load_detect_temp = false;
5753
5754                 /* Make sure the crtc and connector are running */
5755                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5756                         struct drm_encoder_helper_funcs *encoder_funcs;
5757                         struct drm_crtc_helper_funcs *crtc_funcs;
5758
5759                         crtc_funcs = crtc->helper_private;
5760                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5761
5762                         encoder_funcs = encoder->helper_private;
5763                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5764                 }
5765
5766                 return true;
5767         }
5768
5769         /* Find an unused one (if possible) */
5770         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5771                 i++;
5772                 if (!(encoder->possible_crtcs & (1 << i)))
5773                         continue;
5774                 if (!possible_crtc->enabled) {
5775                         crtc = possible_crtc;
5776                         break;
5777                 }
5778         }
5779
5780         /*
5781          * If we didn't find an unused CRTC, don't use any.
5782          */
5783         if (!crtc) {
5784                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5785                 return false;
5786         }
5787
5788         encoder->crtc = crtc;
5789         connector->encoder = encoder;
5790
5791         intel_crtc = to_intel_crtc(crtc);
5792         old->dpms_mode = intel_crtc->dpms_mode;
5793         old->load_detect_temp = true;
5794         old->release_fb = NULL;
5795
5796         if (!mode)
5797                 mode = &load_detect_mode;
5798
5799         old_fb = crtc->fb;
5800
5801         /* We need a framebuffer large enough to accommodate all accesses
5802          * that the plane may generate whilst we perform load detection.
5803          * We can not rely on the fbcon either being present (we get called
5804          * during its initialisation to detect all boot displays, or it may
5805          * not even exist) or that it is large enough to satisfy the
5806          * requested mode.
5807          */
5808         crtc->fb = mode_fits_in_fbdev(dev, mode);
5809         if (crtc->fb == NULL) {
5810                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5811                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5812                 old->release_fb = crtc->fb;
5813         } else
5814                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5815         if (IS_ERR(crtc->fb)) {
5816                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5817                 crtc->fb = old_fb;
5818                 return false;
5819         }
5820
5821         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5822                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5823                 if (old->release_fb)
5824                         old->release_fb->funcs->destroy(old->release_fb);
5825                 crtc->fb = old_fb;
5826                 return false;
5827         }
5828
5829         /* let the connector get through one full cycle before testing */
5830         intel_wait_for_vblank(dev, intel_crtc->pipe);
5831
5832         return true;
5833 }
5834
5835 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5836                                     struct drm_connector *connector,
5837                                     struct intel_load_detect_pipe *old)
5838 {
5839         struct drm_encoder *encoder = &intel_encoder->base;
5840         struct drm_device *dev = encoder->dev;
5841         struct drm_crtc *crtc = encoder->crtc;
5842         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5843         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5844
5845         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5846                       connector->base.id, drm_get_connector_name(connector),
5847                       encoder->base.id, drm_get_encoder_name(encoder));
5848
5849         if (old->load_detect_temp) {
5850                 connector->encoder = NULL;
5851                 drm_helper_disable_unused_functions(dev);
5852
5853                 if (old->release_fb)
5854                         old->release_fb->funcs->destroy(old->release_fb);
5855
5856                 return;
5857         }
5858
5859         /* Switch crtc and encoder back off if necessary */
5860         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5861                 encoder_funcs->dpms(encoder, old->dpms_mode);
5862                 crtc_funcs->dpms(crtc, old->dpms_mode);
5863         }
5864 }
5865
5866 /* Returns the clock of the currently programmed mode of the given pipe. */
5867 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5868 {
5869         struct drm_i915_private *dev_priv = dev->dev_private;
5870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5871         int pipe = intel_crtc->pipe;
5872         u32 dpll = I915_READ(DPLL(pipe));
5873         u32 fp;
5874         intel_clock_t clock;
5875
5876         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5877                 fp = I915_READ(FP0(pipe));
5878         else
5879                 fp = I915_READ(FP1(pipe));
5880
5881         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5882         if (IS_PINEVIEW(dev)) {
5883                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5884                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5885         } else {
5886                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5887                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5888         }
5889
5890         if (!IS_GEN2(dev)) {
5891                 if (IS_PINEVIEW(dev))
5892                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5893                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5894                 else
5895                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5896                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5897
5898                 switch (dpll & DPLL_MODE_MASK) {
5899                 case DPLLB_MODE_DAC_SERIAL:
5900                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5901                                 5 : 10;
5902                         break;
5903                 case DPLLB_MODE_LVDS:
5904                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5905                                 7 : 14;
5906                         break;
5907                 default:
5908                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5909                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5910                         return 0;
5911                 }
5912
5913                 /* XXX: Handle the 100Mhz refclk */
5914                 intel_clock(dev, 96000, &clock);
5915         } else {
5916                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5917
5918                 if (is_lvds) {
5919                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5920                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5921                         clock.p2 = 14;
5922
5923                         if ((dpll & PLL_REF_INPUT_MASK) ==
5924                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5925                                 /* XXX: might not be 66MHz */
5926                                 intel_clock(dev, 66000, &clock);
5927                         } else
5928                                 intel_clock(dev, 48000, &clock);
5929                 } else {
5930                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5931                                 clock.p1 = 2;
5932                         else {
5933                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5934                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5935                         }
5936                         if (dpll & PLL_P2_DIVIDE_BY_4)
5937                                 clock.p2 = 4;
5938                         else
5939                                 clock.p2 = 2;
5940
5941                         intel_clock(dev, 48000, &clock);
5942                 }
5943         }
5944
5945         /* XXX: It would be nice to validate the clocks, but we can't reuse
5946          * i830PllIsValid() because it relies on the xf86_config connector
5947          * configuration being accurate, which it isn't necessarily.
5948          */
5949
5950         return clock.dot;
5951 }
5952
5953 /** Returns the currently programmed mode of the given pipe. */
5954 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5955                                              struct drm_crtc *crtc)
5956 {
5957         struct drm_i915_private *dev_priv = dev->dev_private;
5958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5959         int pipe = intel_crtc->pipe;
5960         struct drm_display_mode *mode;
5961         int htot = I915_READ(HTOTAL(pipe));
5962         int hsync = I915_READ(HSYNC(pipe));
5963         int vtot = I915_READ(VTOTAL(pipe));
5964         int vsync = I915_READ(VSYNC(pipe));
5965
5966         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5967         if (!mode)
5968                 return NULL;
5969
5970         mode->clock = intel_crtc_clock_get(dev, crtc);
5971         mode->hdisplay = (htot & 0xffff) + 1;
5972         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5973         mode->hsync_start = (hsync & 0xffff) + 1;
5974         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5975         mode->vdisplay = (vtot & 0xffff) + 1;
5976         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5977         mode->vsync_start = (vsync & 0xffff) + 1;
5978         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5979
5980         drm_mode_set_name(mode);
5981         drm_mode_set_crtcinfo(mode, 0);
5982
5983         return mode;
5984 }
5985
5986 #define GPU_IDLE_TIMEOUT 500 /* ms */
5987
5988 /* When this timer fires, we've been idle for awhile */
5989 static void intel_gpu_idle_timer(unsigned long arg)
5990 {
5991         struct drm_device *dev = (struct drm_device *)arg;
5992         drm_i915_private_t *dev_priv = dev->dev_private;
5993
5994         if (!list_empty(&dev_priv->mm.active_list)) {
5995                 /* Still processing requests, so just re-arm the timer. */
5996                 mod_timer(&dev_priv->idle_timer, jiffies +
5997                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5998                 return;
5999         }
6000
6001         dev_priv->busy = false;
6002         queue_work(dev_priv->wq, &dev_priv->idle_work);
6003 }
6004
6005 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6006
6007 static void intel_crtc_idle_timer(unsigned long arg)
6008 {
6009         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6010         struct drm_crtc *crtc = &intel_crtc->base;
6011         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6012         struct intel_framebuffer *intel_fb;
6013
6014         intel_fb = to_intel_framebuffer(crtc->fb);
6015         if (intel_fb && intel_fb->obj->active) {
6016                 /* The framebuffer is still being accessed by the GPU. */
6017                 mod_timer(&intel_crtc->idle_timer, jiffies +
6018                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6019                 return;
6020         }
6021
6022         intel_crtc->busy = false;
6023         queue_work(dev_priv->wq, &dev_priv->idle_work);
6024 }
6025
6026 static void intel_increase_pllclock(struct drm_crtc *crtc)
6027 {
6028         struct drm_device *dev = crtc->dev;
6029         drm_i915_private_t *dev_priv = dev->dev_private;
6030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031         int pipe = intel_crtc->pipe;
6032         int dpll_reg = DPLL(pipe);
6033         int dpll;
6034
6035         if (HAS_PCH_SPLIT(dev))
6036                 return;
6037
6038         if (!dev_priv->lvds_downclock_avail)
6039                 return;
6040
6041         dpll = I915_READ(dpll_reg);
6042         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6043                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6044
6045                 /* Unlock panel regs */
6046                 I915_WRITE(PP_CONTROL,
6047                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6048
6049                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6050                 I915_WRITE(dpll_reg, dpll);
6051                 intel_wait_for_vblank(dev, pipe);
6052
6053                 dpll = I915_READ(dpll_reg);
6054                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6055                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6056
6057                 /* ...and lock them again */
6058                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6059         }
6060
6061         /* Schedule downclock */
6062         mod_timer(&intel_crtc->idle_timer, jiffies +
6063                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6064 }
6065
6066 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6067 {
6068         struct drm_device *dev = crtc->dev;
6069         drm_i915_private_t *dev_priv = dev->dev_private;
6070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6071         int pipe = intel_crtc->pipe;
6072         int dpll_reg = DPLL(pipe);
6073         int dpll = I915_READ(dpll_reg);
6074
6075         if (HAS_PCH_SPLIT(dev))
6076                 return;
6077
6078         if (!dev_priv->lvds_downclock_avail)
6079                 return;
6080
6081         /*
6082          * Since this is called by a timer, we should never get here in
6083          * the manual case.
6084          */
6085         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6086                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6087
6088                 /* Unlock panel regs */
6089                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6090                            PANEL_UNLOCK_REGS);
6091
6092                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6093                 I915_WRITE(dpll_reg, dpll);
6094                 intel_wait_for_vblank(dev, pipe);
6095                 dpll = I915_READ(dpll_reg);
6096                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6097                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6098
6099                 /* ...and lock them again */
6100                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6101         }
6102
6103 }
6104
6105 /**
6106  * intel_idle_update - adjust clocks for idleness
6107  * @work: work struct
6108  *
6109  * Either the GPU or display (or both) went idle.  Check the busy status
6110  * here and adjust the CRTC and GPU clocks as necessary.
6111  */
6112 static void intel_idle_update(struct work_struct *work)
6113 {
6114         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6115                                                     idle_work);
6116         struct drm_device *dev = dev_priv->dev;
6117         struct drm_crtc *crtc;
6118         struct intel_crtc *intel_crtc;
6119
6120         if (!i915_powersave)
6121                 return;
6122
6123         mutex_lock(&dev->struct_mutex);
6124
6125         i915_update_gfx_val(dev_priv);
6126
6127         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6128                 /* Skip inactive CRTCs */
6129                 if (!crtc->fb)
6130                         continue;
6131
6132                 intel_crtc = to_intel_crtc(crtc);
6133                 if (!intel_crtc->busy)
6134                         intel_decrease_pllclock(crtc);
6135         }
6136
6137
6138         mutex_unlock(&dev->struct_mutex);
6139 }
6140
6141 /**
6142  * intel_mark_busy - mark the GPU and possibly the display busy
6143  * @dev: drm device
6144  * @obj: object we're operating on
6145  *
6146  * Callers can use this function to indicate that the GPU is busy processing
6147  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6148  * buffer), we'll also mark the display as busy, so we know to increase its
6149  * clock frequency.
6150  */
6151 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6152 {
6153         drm_i915_private_t *dev_priv = dev->dev_private;
6154         struct drm_crtc *crtc = NULL;
6155         struct intel_framebuffer *intel_fb;
6156         struct intel_crtc *intel_crtc;
6157
6158         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6159                 return;
6160
6161         if (!dev_priv->busy)
6162                 dev_priv->busy = true;
6163         else
6164                 mod_timer(&dev_priv->idle_timer, jiffies +
6165                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6166
6167         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6168                 if (!crtc->fb)
6169                         continue;
6170
6171                 intel_crtc = to_intel_crtc(crtc);
6172                 intel_fb = to_intel_framebuffer(crtc->fb);
6173                 if (intel_fb->obj == obj) {
6174                         if (!intel_crtc->busy) {
6175                                 /* Non-busy -> busy, upclock */
6176                                 intel_increase_pllclock(crtc);
6177                                 intel_crtc->busy = true;
6178                         } else {
6179                                 /* Busy -> busy, put off timer */
6180                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6181                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6182                         }
6183                 }
6184         }
6185 }
6186
6187 static void intel_crtc_destroy(struct drm_crtc *crtc)
6188 {
6189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6190         struct drm_device *dev = crtc->dev;
6191         struct intel_unpin_work *work;
6192         unsigned long flags;
6193
6194         spin_lock_irqsave(&dev->event_lock, flags);
6195         work = intel_crtc->unpin_work;
6196         intel_crtc->unpin_work = NULL;
6197         spin_unlock_irqrestore(&dev->event_lock, flags);
6198
6199         if (work) {
6200                 cancel_work_sync(&work->work);
6201                 kfree(work);
6202         }
6203
6204         drm_crtc_cleanup(crtc);
6205
6206         kfree(intel_crtc);
6207 }
6208
6209 static void intel_unpin_work_fn(struct work_struct *__work)
6210 {
6211         struct intel_unpin_work *work =
6212                 container_of(__work, struct intel_unpin_work, work);
6213
6214         mutex_lock(&work->dev->struct_mutex);
6215         i915_gem_object_unpin(work->old_fb_obj);
6216         drm_gem_object_unreference(&work->pending_flip_obj->base);
6217         drm_gem_object_unreference(&work->old_fb_obj->base);
6218
6219         mutex_unlock(&work->dev->struct_mutex);
6220         kfree(work);
6221 }
6222
6223 static void do_intel_finish_page_flip(struct drm_device *dev,
6224                                       struct drm_crtc *crtc)
6225 {
6226         drm_i915_private_t *dev_priv = dev->dev_private;
6227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6228         struct intel_unpin_work *work;
6229         struct drm_i915_gem_object *obj;
6230         struct drm_pending_vblank_event *e;
6231         struct timeval tnow, tvbl;
6232         unsigned long flags;
6233
6234         /* Ignore early vblank irqs */
6235         if (intel_crtc == NULL)
6236                 return;
6237
6238         do_gettimeofday(&tnow);
6239
6240         spin_lock_irqsave(&dev->event_lock, flags);
6241         work = intel_crtc->unpin_work;
6242         if (work == NULL || !work->pending) {
6243                 spin_unlock_irqrestore(&dev->event_lock, flags);
6244                 return;
6245         }
6246
6247         intel_crtc->unpin_work = NULL;
6248
6249         if (work->event) {
6250                 e = work->event;
6251                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6252
6253                 /* Called before vblank count and timestamps have
6254                  * been updated for the vblank interval of flip
6255                  * completion? Need to increment vblank count and
6256                  * add one videorefresh duration to returned timestamp
6257                  * to account for this. We assume this happened if we
6258                  * get called over 0.9 frame durations after the last
6259                  * timestamped vblank.
6260                  *
6261                  * This calculation can not be used with vrefresh rates
6262                  * below 5Hz (10Hz to be on the safe side) without
6263                  * promoting to 64 integers.
6264                  */
6265                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6266                     9 * crtc->framedur_ns) {
6267                         e->event.sequence++;
6268                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6269                                              crtc->framedur_ns);
6270                 }
6271
6272                 e->event.tv_sec = tvbl.tv_sec;
6273                 e->event.tv_usec = tvbl.tv_usec;
6274
6275                 list_add_tail(&e->base.link,
6276                               &e->base.file_priv->event_list);
6277                 wake_up_interruptible(&e->base.file_priv->event_wait);
6278         }
6279
6280         drm_vblank_put(dev, intel_crtc->pipe);
6281
6282         spin_unlock_irqrestore(&dev->event_lock, flags);
6283
6284         obj = work->old_fb_obj;
6285
6286         atomic_clear_mask(1 << intel_crtc->plane,
6287                           &obj->pending_flip.counter);
6288         if (atomic_read(&obj->pending_flip) == 0)
6289                 wake_up(&dev_priv->pending_flip_queue);
6290
6291         schedule_work(&work->work);
6292
6293         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6294 }
6295
6296 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6297 {
6298         drm_i915_private_t *dev_priv = dev->dev_private;
6299         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6300
6301         do_intel_finish_page_flip(dev, crtc);
6302 }
6303
6304 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6305 {
6306         drm_i915_private_t *dev_priv = dev->dev_private;
6307         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6308
6309         do_intel_finish_page_flip(dev, crtc);
6310 }
6311
6312 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6313 {
6314         drm_i915_private_t *dev_priv = dev->dev_private;
6315         struct intel_crtc *intel_crtc =
6316                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6317         unsigned long flags;
6318
6319         spin_lock_irqsave(&dev->event_lock, flags);
6320         if (intel_crtc->unpin_work) {
6321                 if ((++intel_crtc->unpin_work->pending) > 1)
6322                         DRM_ERROR("Prepared flip multiple times\n");
6323         } else {
6324                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6325         }
6326         spin_unlock_irqrestore(&dev->event_lock, flags);
6327 }
6328
6329 static int intel_gen2_queue_flip(struct drm_device *dev,
6330                                  struct drm_crtc *crtc,
6331                                  struct drm_framebuffer *fb,
6332                                  struct drm_i915_gem_object *obj)
6333 {
6334         struct drm_i915_private *dev_priv = dev->dev_private;
6335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6336         unsigned long offset;
6337         u32 flip_mask;
6338         int ret;
6339
6340         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6341         if (ret)
6342                 goto out;
6343
6344         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6345         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6346
6347         ret = BEGIN_LP_RING(6);
6348         if (ret)
6349                 goto out;
6350
6351         /* Can't queue multiple flips, so wait for the previous
6352          * one to finish before executing the next.
6353          */
6354         if (intel_crtc->plane)
6355                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6356         else
6357                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6358         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6359         OUT_RING(MI_NOOP);
6360         OUT_RING(MI_DISPLAY_FLIP |
6361                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6362         OUT_RING(fb->pitch);
6363         OUT_RING(obj->gtt_offset + offset);
6364         OUT_RING(MI_NOOP);
6365         ADVANCE_LP_RING();
6366 out:
6367         return ret;
6368 }
6369
6370 static int intel_gen3_queue_flip(struct drm_device *dev,
6371                                  struct drm_crtc *crtc,
6372                                  struct drm_framebuffer *fb,
6373                                  struct drm_i915_gem_object *obj)
6374 {
6375         struct drm_i915_private *dev_priv = dev->dev_private;
6376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377         unsigned long offset;
6378         u32 flip_mask;
6379         int ret;
6380
6381         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6382         if (ret)
6383                 goto out;
6384
6385         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6386         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6387
6388         ret = BEGIN_LP_RING(6);
6389         if (ret)
6390                 goto out;
6391
6392         if (intel_crtc->plane)
6393                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6394         else
6395                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6396         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6397         OUT_RING(MI_NOOP);
6398         OUT_RING(MI_DISPLAY_FLIP_I915 |
6399                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6400         OUT_RING(fb->pitch);
6401         OUT_RING(obj->gtt_offset + offset);
6402         OUT_RING(MI_NOOP);
6403
6404         ADVANCE_LP_RING();
6405 out:
6406         return ret;
6407 }
6408
6409 static int intel_gen4_queue_flip(struct drm_device *dev,
6410                                  struct drm_crtc *crtc,
6411                                  struct drm_framebuffer *fb,
6412                                  struct drm_i915_gem_object *obj)
6413 {
6414         struct drm_i915_private *dev_priv = dev->dev_private;
6415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416         uint32_t pf, pipesrc;
6417         int ret;
6418
6419         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6420         if (ret)
6421                 goto out;
6422
6423         ret = BEGIN_LP_RING(4);
6424         if (ret)
6425                 goto out;
6426
6427         /* i965+ uses the linear or tiled offsets from the
6428          * Display Registers (which do not change across a page-flip)
6429          * so we need only reprogram the base address.
6430          */
6431         OUT_RING(MI_DISPLAY_FLIP |
6432                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6433         OUT_RING(fb->pitch);
6434         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6435
6436         /* XXX Enabling the panel-fitter across page-flip is so far
6437          * untested on non-native modes, so ignore it for now.
6438          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6439          */
6440         pf = 0;
6441         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6442         OUT_RING(pf | pipesrc);
6443         ADVANCE_LP_RING();
6444 out:
6445         return ret;
6446 }
6447
6448 static int intel_gen6_queue_flip(struct drm_device *dev,
6449                                  struct drm_crtc *crtc,
6450                                  struct drm_framebuffer *fb,
6451                                  struct drm_i915_gem_object *obj)
6452 {
6453         struct drm_i915_private *dev_priv = dev->dev_private;
6454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455         uint32_t pf, pipesrc;
6456         int ret;
6457
6458         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6459         if (ret)
6460                 goto out;
6461
6462         ret = BEGIN_LP_RING(4);
6463         if (ret)
6464                 goto out;
6465
6466         OUT_RING(MI_DISPLAY_FLIP |
6467                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6468         OUT_RING(fb->pitch | obj->tiling_mode);
6469         OUT_RING(obj->gtt_offset);
6470
6471         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6472         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6473         OUT_RING(pf | pipesrc);
6474         ADVANCE_LP_RING();
6475 out:
6476         return ret;
6477 }
6478
6479 /*
6480  * On gen7 we currently use the blit ring because (in early silicon at least)
6481  * the render ring doesn't give us interrpts for page flip completion, which
6482  * means clients will hang after the first flip is queued.  Fortunately the
6483  * blit ring generates interrupts properly, so use it instead.
6484  */
6485 static int intel_gen7_queue_flip(struct drm_device *dev,
6486                                  struct drm_crtc *crtc,
6487                                  struct drm_framebuffer *fb,
6488                                  struct drm_i915_gem_object *obj)
6489 {
6490         struct drm_i915_private *dev_priv = dev->dev_private;
6491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6493         int ret;
6494
6495         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6496         if (ret)
6497                 goto out;
6498
6499         ret = intel_ring_begin(ring, 4);
6500         if (ret)
6501                 goto out;
6502
6503         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6504         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6505         intel_ring_emit(ring, (obj->gtt_offset));
6506         intel_ring_emit(ring, (MI_NOOP));
6507         intel_ring_advance(ring);
6508 out:
6509         return ret;
6510 }
6511
6512 static int intel_default_queue_flip(struct drm_device *dev,
6513                                     struct drm_crtc *crtc,
6514                                     struct drm_framebuffer *fb,
6515                                     struct drm_i915_gem_object *obj)
6516 {
6517         return -ENODEV;
6518 }
6519
6520 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6521                                 struct drm_framebuffer *fb,
6522                                 struct drm_pending_vblank_event *event)
6523 {
6524         struct drm_device *dev = crtc->dev;
6525         struct drm_i915_private *dev_priv = dev->dev_private;
6526         struct intel_framebuffer *intel_fb;
6527         struct drm_i915_gem_object *obj;
6528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6529         struct intel_unpin_work *work;
6530         unsigned long flags;
6531         int ret;
6532
6533         work = kzalloc(sizeof *work, GFP_KERNEL);
6534         if (work == NULL)
6535                 return -ENOMEM;
6536
6537         work->event = event;
6538         work->dev = crtc->dev;
6539         intel_fb = to_intel_framebuffer(crtc->fb);
6540         work->old_fb_obj = intel_fb->obj;
6541         INIT_WORK(&work->work, intel_unpin_work_fn);
6542
6543         /* We borrow the event spin lock for protecting unpin_work */
6544         spin_lock_irqsave(&dev->event_lock, flags);
6545         if (intel_crtc->unpin_work) {
6546                 spin_unlock_irqrestore(&dev->event_lock, flags);
6547                 kfree(work);
6548
6549                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6550                 return -EBUSY;
6551         }
6552         intel_crtc->unpin_work = work;
6553         spin_unlock_irqrestore(&dev->event_lock, flags);
6554
6555         intel_fb = to_intel_framebuffer(fb);
6556         obj = intel_fb->obj;
6557
6558         mutex_lock(&dev->struct_mutex);
6559
6560         /* Reference the objects for the scheduled work. */
6561         drm_gem_object_reference(&work->old_fb_obj->base);
6562         drm_gem_object_reference(&obj->base);
6563
6564         crtc->fb = fb;
6565
6566         ret = drm_vblank_get(dev, intel_crtc->pipe);
6567         if (ret)
6568                 goto cleanup_objs;
6569
6570         work->pending_flip_obj = obj;
6571
6572         work->enable_stall_check = true;
6573
6574         /* Block clients from rendering to the new back buffer until
6575          * the flip occurs and the object is no longer visible.
6576          */
6577         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6578
6579         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6580         if (ret)
6581                 goto cleanup_pending;
6582
6583         mutex_unlock(&dev->struct_mutex);
6584
6585         trace_i915_flip_request(intel_crtc->plane, obj);
6586
6587         return 0;
6588
6589 cleanup_pending:
6590         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6591 cleanup_objs:
6592         drm_gem_object_unreference(&work->old_fb_obj->base);
6593         drm_gem_object_unreference(&obj->base);
6594         mutex_unlock(&dev->struct_mutex);
6595
6596         spin_lock_irqsave(&dev->event_lock, flags);
6597         intel_crtc->unpin_work = NULL;
6598         spin_unlock_irqrestore(&dev->event_lock, flags);
6599
6600         kfree(work);
6601
6602         return ret;
6603 }
6604
6605 static void intel_sanitize_modesetting(struct drm_device *dev,
6606                                        int pipe, int plane)
6607 {
6608         struct drm_i915_private *dev_priv = dev->dev_private;
6609         u32 reg, val;
6610
6611         if (HAS_PCH_SPLIT(dev))
6612                 return;
6613
6614         /* Who knows what state these registers were left in by the BIOS or
6615          * grub?
6616          *
6617          * If we leave the registers in a conflicting state (e.g. with the
6618          * display plane reading from the other pipe than the one we intend
6619          * to use) then when we attempt to teardown the active mode, we will
6620          * not disable the pipes and planes in the correct order -- leaving
6621          * a plane reading from a disabled pipe and possibly leading to
6622          * undefined behaviour.
6623          */
6624
6625         reg = DSPCNTR(plane);
6626         val = I915_READ(reg);
6627
6628         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6629                 return;
6630         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6631                 return;
6632
6633         /* This display plane is active and attached to the other CPU pipe. */
6634         pipe = !pipe;
6635
6636         /* Disable the plane and wait for it to stop reading from the pipe. */
6637         intel_disable_plane(dev_priv, plane, pipe);
6638         intel_disable_pipe(dev_priv, pipe);
6639 }
6640
6641 static void intel_crtc_reset(struct drm_crtc *crtc)
6642 {
6643         struct drm_device *dev = crtc->dev;
6644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645
6646         /* Reset flags back to the 'unknown' status so that they
6647          * will be correctly set on the initial modeset.
6648          */
6649         intel_crtc->dpms_mode = -1;
6650
6651         /* We need to fix up any BIOS configuration that conflicts with
6652          * our expectations.
6653          */
6654         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6655 }
6656
6657 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6658         .dpms = intel_crtc_dpms,
6659         .mode_fixup = intel_crtc_mode_fixup,
6660         .mode_set = intel_crtc_mode_set,
6661         .mode_set_base = intel_pipe_set_base,
6662         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6663         .load_lut = intel_crtc_load_lut,
6664         .disable = intel_crtc_disable,
6665 };
6666
6667 static const struct drm_crtc_funcs intel_crtc_funcs = {
6668         .reset = intel_crtc_reset,
6669         .cursor_set = intel_crtc_cursor_set,
6670         .cursor_move = intel_crtc_cursor_move,
6671         .gamma_set = intel_crtc_gamma_set,
6672         .set_config = drm_crtc_helper_set_config,
6673         .destroy = intel_crtc_destroy,
6674         .page_flip = intel_crtc_page_flip,
6675 };
6676
6677 static void intel_crtc_init(struct drm_device *dev, int pipe)
6678 {
6679         drm_i915_private_t *dev_priv = dev->dev_private;
6680         struct intel_crtc *intel_crtc;
6681         int i;
6682
6683         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6684         if (intel_crtc == NULL)
6685                 return;
6686
6687         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6688
6689         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6690         for (i = 0; i < 256; i++) {
6691                 intel_crtc->lut_r[i] = i;
6692                 intel_crtc->lut_g[i] = i;
6693                 intel_crtc->lut_b[i] = i;
6694         }
6695
6696         /* Swap pipes & planes for FBC on pre-965 */
6697         intel_crtc->pipe = pipe;
6698         intel_crtc->plane = pipe;
6699         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6700                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6701                 intel_crtc->plane = !pipe;
6702         }
6703
6704         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6705                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6706         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6707         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6708
6709         intel_crtc_reset(&intel_crtc->base);
6710         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6711
6712         if (HAS_PCH_SPLIT(dev)) {
6713                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6714                 intel_helper_funcs.commit = ironlake_crtc_commit;
6715         } else {
6716                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6717                 intel_helper_funcs.commit = i9xx_crtc_commit;
6718         }
6719
6720         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6721
6722         intel_crtc->busy = false;
6723
6724         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6725                     (unsigned long)intel_crtc);
6726 }
6727
6728 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6729                                 struct drm_file *file)
6730 {
6731         drm_i915_private_t *dev_priv = dev->dev_private;
6732         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6733         struct drm_mode_object *drmmode_obj;
6734         struct intel_crtc *crtc;
6735
6736         if (!dev_priv) {
6737                 DRM_ERROR("called with no initialization\n");
6738                 return -EINVAL;
6739         }
6740
6741         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6742                         DRM_MODE_OBJECT_CRTC);
6743
6744         if (!drmmode_obj) {
6745                 DRM_ERROR("no such CRTC id\n");
6746                 return -EINVAL;
6747         }
6748
6749         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6750         pipe_from_crtc_id->pipe = crtc->pipe;
6751
6752         return 0;
6753 }
6754
6755 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6756 {
6757         struct intel_encoder *encoder;
6758         int index_mask = 0;
6759         int entry = 0;
6760
6761         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6762                 if (type_mask & encoder->clone_mask)
6763                         index_mask |= (1 << entry);
6764                 entry++;
6765         }
6766
6767         return index_mask;
6768 }
6769
6770 static bool has_edp_a(struct drm_device *dev)
6771 {
6772         struct drm_i915_private *dev_priv = dev->dev_private;
6773
6774         if (!IS_MOBILE(dev))
6775                 return false;
6776
6777         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6778                 return false;
6779
6780         if (IS_GEN5(dev) &&
6781             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6782                 return false;
6783
6784         return true;
6785 }
6786
6787 static void intel_setup_outputs(struct drm_device *dev)
6788 {
6789         struct drm_i915_private *dev_priv = dev->dev_private;
6790         struct intel_encoder *encoder;
6791         bool dpd_is_edp = false;
6792         bool has_lvds = false;
6793
6794         if (IS_MOBILE(dev) && !IS_I830(dev))
6795                 has_lvds = intel_lvds_init(dev);
6796         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6797                 /* disable the panel fitter on everything but LVDS */
6798                 I915_WRITE(PFIT_CONTROL, 0);
6799         }
6800
6801         if (HAS_PCH_SPLIT(dev)) {
6802                 dpd_is_edp = intel_dpd_is_edp(dev);
6803
6804                 if (has_edp_a(dev))
6805                         intel_dp_init(dev, DP_A);
6806
6807                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6808                         intel_dp_init(dev, PCH_DP_D);
6809         }
6810
6811         intel_crt_init(dev);
6812
6813         if (HAS_PCH_SPLIT(dev)) {
6814                 int found;
6815
6816                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6817                         /* PCH SDVOB multiplex with HDMIB */
6818                         found = intel_sdvo_init(dev, PCH_SDVOB);
6819                         if (!found)
6820                                 intel_hdmi_init(dev, HDMIB);
6821                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6822                                 intel_dp_init(dev, PCH_DP_B);
6823                 }
6824
6825                 if (I915_READ(HDMIC) & PORT_DETECTED)
6826                         intel_hdmi_init(dev, HDMIC);
6827
6828                 if (I915_READ(HDMID) & PORT_DETECTED)
6829                         intel_hdmi_init(dev, HDMID);
6830
6831                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6832                         intel_dp_init(dev, PCH_DP_C);
6833
6834                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6835                         intel_dp_init(dev, PCH_DP_D);
6836
6837         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6838                 bool found = false;
6839
6840                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6841                         DRM_DEBUG_KMS("probing SDVOB\n");
6842                         found = intel_sdvo_init(dev, SDVOB);
6843                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6844                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6845                                 intel_hdmi_init(dev, SDVOB);
6846                         }
6847
6848                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6849                                 DRM_DEBUG_KMS("probing DP_B\n");
6850                                 intel_dp_init(dev, DP_B);
6851                         }
6852                 }
6853
6854                 /* Before G4X SDVOC doesn't have its own detect register */
6855
6856                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6857                         DRM_DEBUG_KMS("probing SDVOC\n");
6858                         found = intel_sdvo_init(dev, SDVOC);
6859                 }
6860
6861                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6862
6863                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6864                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6865                                 intel_hdmi_init(dev, SDVOC);
6866                         }
6867                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6868                                 DRM_DEBUG_KMS("probing DP_C\n");
6869                                 intel_dp_init(dev, DP_C);
6870                         }
6871                 }
6872
6873                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6874                     (I915_READ(DP_D) & DP_DETECTED)) {
6875                         DRM_DEBUG_KMS("probing DP_D\n");
6876                         intel_dp_init(dev, DP_D);
6877                 }
6878         } else if (IS_GEN2(dev))
6879                 intel_dvo_init(dev);
6880
6881         if (SUPPORTS_TV(dev))
6882                 intel_tv_init(dev);
6883
6884         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6885                 encoder->base.possible_crtcs = encoder->crtc_mask;
6886                 encoder->base.possible_clones =
6887                         intel_encoder_clones(dev, encoder->clone_mask);
6888         }
6889
6890         intel_panel_setup_backlight(dev);
6891
6892         /* disable all the possible outputs/crtcs before entering KMS mode */
6893         drm_helper_disable_unused_functions(dev);
6894 }
6895
6896 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6897 {
6898         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6899
6900         drm_framebuffer_cleanup(fb);
6901         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6902
6903         kfree(intel_fb);
6904 }
6905
6906 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6907                                                 struct drm_file *file,
6908                                                 unsigned int *handle)
6909 {
6910         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6911         struct drm_i915_gem_object *obj = intel_fb->obj;
6912
6913         return drm_gem_handle_create(file, &obj->base, handle);
6914 }
6915
6916 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6917         .destroy = intel_user_framebuffer_destroy,
6918         .create_handle = intel_user_framebuffer_create_handle,
6919 };
6920
6921 int intel_framebuffer_init(struct drm_device *dev,
6922                            struct intel_framebuffer *intel_fb,
6923                            struct drm_mode_fb_cmd *mode_cmd,
6924                            struct drm_i915_gem_object *obj)
6925 {
6926         int ret;
6927
6928         if (obj->tiling_mode == I915_TILING_Y)
6929                 return -EINVAL;
6930
6931         if (mode_cmd->pitch & 63)
6932                 return -EINVAL;
6933
6934         switch (mode_cmd->bpp) {
6935         case 8:
6936         case 16:
6937         case 24:
6938         case 32:
6939                 break;
6940         default:
6941                 return -EINVAL;
6942         }
6943
6944         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6945         if (ret) {
6946                 DRM_ERROR("framebuffer init failed %d\n", ret);
6947                 return ret;
6948         }
6949
6950         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6951         intel_fb->obj = obj;
6952         return 0;
6953 }
6954
6955 static struct drm_framebuffer *
6956 intel_user_framebuffer_create(struct drm_device *dev,
6957                               struct drm_file *filp,
6958                               struct drm_mode_fb_cmd *mode_cmd)
6959 {
6960         struct drm_i915_gem_object *obj;
6961
6962         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6963         if (&obj->base == NULL)
6964                 return ERR_PTR(-ENOENT);
6965
6966         return intel_framebuffer_create(dev, mode_cmd, obj);
6967 }
6968
6969 static const struct drm_mode_config_funcs intel_mode_funcs = {
6970         .fb_create = intel_user_framebuffer_create,
6971         .output_poll_changed = intel_fb_output_poll_changed,
6972 };
6973
6974 static struct drm_i915_gem_object *
6975 intel_alloc_context_page(struct drm_device *dev)
6976 {
6977         struct drm_i915_gem_object *ctx;
6978         int ret;
6979
6980         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6981
6982         ctx = i915_gem_alloc_object(dev, 4096);
6983         if (!ctx) {
6984                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6985                 return NULL;
6986         }
6987
6988         ret = i915_gem_object_pin(ctx, 4096, true);
6989         if (ret) {
6990                 DRM_ERROR("failed to pin power context: %d\n", ret);
6991                 goto err_unref;
6992         }
6993
6994         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6995         if (ret) {
6996                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6997                 goto err_unpin;
6998         }
6999
7000         return ctx;
7001
7002 err_unpin:
7003         i915_gem_object_unpin(ctx);
7004 err_unref:
7005         drm_gem_object_unreference(&ctx->base);
7006         mutex_unlock(&dev->struct_mutex);
7007         return NULL;
7008 }
7009
7010 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7011 {
7012         struct drm_i915_private *dev_priv = dev->dev_private;
7013         u16 rgvswctl;
7014
7015         rgvswctl = I915_READ16(MEMSWCTL);
7016         if (rgvswctl & MEMCTL_CMD_STS) {
7017                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7018                 return false; /* still busy with another command */
7019         }
7020
7021         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7022                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7023         I915_WRITE16(MEMSWCTL, rgvswctl);
7024         POSTING_READ16(MEMSWCTL);
7025
7026         rgvswctl |= MEMCTL_CMD_STS;
7027         I915_WRITE16(MEMSWCTL, rgvswctl);
7028
7029         return true;
7030 }
7031
7032 void ironlake_enable_drps(struct drm_device *dev)
7033 {
7034         struct drm_i915_private *dev_priv = dev->dev_private;
7035         u32 rgvmodectl = I915_READ(MEMMODECTL);
7036         u8 fmax, fmin, fstart, vstart;
7037
7038         /* Enable temp reporting */
7039         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7040         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7041
7042         /* 100ms RC evaluation intervals */
7043         I915_WRITE(RCUPEI, 100000);
7044         I915_WRITE(RCDNEI, 100000);
7045
7046         /* Set max/min thresholds to 90ms and 80ms respectively */
7047         I915_WRITE(RCBMAXAVG, 90000);
7048         I915_WRITE(RCBMINAVG, 80000);
7049
7050         I915_WRITE(MEMIHYST, 1);
7051
7052         /* Set up min, max, and cur for interrupt handling */
7053         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7054         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7055         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7056                 MEMMODE_FSTART_SHIFT;
7057
7058         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7059                 PXVFREQ_PX_SHIFT;
7060
7061         dev_priv->fmax = fmax; /* IPS callback will increase this */
7062         dev_priv->fstart = fstart;
7063
7064         dev_priv->max_delay = fstart;
7065         dev_priv->min_delay = fmin;
7066         dev_priv->cur_delay = fstart;
7067
7068         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7069                          fmax, fmin, fstart);
7070
7071         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7072
7073         /*
7074          * Interrupts will be enabled in ironlake_irq_postinstall
7075          */
7076
7077         I915_WRITE(VIDSTART, vstart);
7078         POSTING_READ(VIDSTART);
7079
7080         rgvmodectl |= MEMMODE_SWMODE_EN;
7081         I915_WRITE(MEMMODECTL, rgvmodectl);
7082
7083         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7084                 DRM_ERROR("stuck trying to change perf mode\n");
7085         msleep(1);
7086
7087         ironlake_set_drps(dev, fstart);
7088
7089         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7090                 I915_READ(0x112e0);
7091         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7092         dev_priv->last_count2 = I915_READ(0x112f4);
7093         getrawmonotonic(&dev_priv->last_time2);
7094 }
7095
7096 void ironlake_disable_drps(struct drm_device *dev)
7097 {
7098         struct drm_i915_private *dev_priv = dev->dev_private;
7099         u16 rgvswctl = I915_READ16(MEMSWCTL);
7100
7101         /* Ack interrupts, disable EFC interrupt */
7102         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7103         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7104         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7105         I915_WRITE(DEIIR, DE_PCU_EVENT);
7106         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7107
7108         /* Go back to the starting frequency */
7109         ironlake_set_drps(dev, dev_priv->fstart);
7110         msleep(1);
7111         rgvswctl |= MEMCTL_CMD_STS;
7112         I915_WRITE(MEMSWCTL, rgvswctl);
7113         msleep(1);
7114
7115 }
7116
7117 void gen6_set_rps(struct drm_device *dev, u8 val)
7118 {
7119         struct drm_i915_private *dev_priv = dev->dev_private;
7120         u32 swreq;
7121
7122         swreq = (val & 0x3ff) << 25;
7123         I915_WRITE(GEN6_RPNSWREQ, swreq);
7124 }
7125
7126 void gen6_disable_rps(struct drm_device *dev)
7127 {
7128         struct drm_i915_private *dev_priv = dev->dev_private;
7129
7130         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7131         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7132         I915_WRITE(GEN6_PMIER, 0);
7133
7134         spin_lock_irq(&dev_priv->rps_lock);
7135         dev_priv->pm_iir = 0;
7136         spin_unlock_irq(&dev_priv->rps_lock);
7137
7138         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7139 }
7140
7141 static unsigned long intel_pxfreq(u32 vidfreq)
7142 {
7143         unsigned long freq;
7144         int div = (vidfreq & 0x3f0000) >> 16;
7145         int post = (vidfreq & 0x3000) >> 12;
7146         int pre = (vidfreq & 0x7);
7147
7148         if (!pre)
7149                 return 0;
7150
7151         freq = ((div * 133333) / ((1<<post) * pre));
7152
7153         return freq;
7154 }
7155
7156 void intel_init_emon(struct drm_device *dev)
7157 {
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159         u32 lcfuse;
7160         u8 pxw[16];
7161         int i;
7162
7163         /* Disable to program */
7164         I915_WRITE(ECR, 0);
7165         POSTING_READ(ECR);
7166
7167         /* Program energy weights for various events */
7168         I915_WRITE(SDEW, 0x15040d00);
7169         I915_WRITE(CSIEW0, 0x007f0000);
7170         I915_WRITE(CSIEW1, 0x1e220004);
7171         I915_WRITE(CSIEW2, 0x04000004);
7172
7173         for (i = 0; i < 5; i++)
7174                 I915_WRITE(PEW + (i * 4), 0);
7175         for (i = 0; i < 3; i++)
7176                 I915_WRITE(DEW + (i * 4), 0);
7177
7178         /* Program P-state weights to account for frequency power adjustment */
7179         for (i = 0; i < 16; i++) {
7180                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7181                 unsigned long freq = intel_pxfreq(pxvidfreq);
7182                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7183                         PXVFREQ_PX_SHIFT;
7184                 unsigned long val;
7185
7186                 val = vid * vid;
7187                 val *= (freq / 1000);
7188                 val *= 255;
7189                 val /= (127*127*900);
7190                 if (val > 0xff)
7191                         DRM_ERROR("bad pxval: %ld\n", val);
7192                 pxw[i] = val;
7193         }
7194         /* Render standby states get 0 weight */
7195         pxw[14] = 0;
7196         pxw[15] = 0;
7197
7198         for (i = 0; i < 4; i++) {
7199                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7200                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7201                 I915_WRITE(PXW + (i * 4), val);
7202         }
7203
7204         /* Adjust magic regs to magic values (more experimental results) */
7205         I915_WRITE(OGW0, 0);
7206         I915_WRITE(OGW1, 0);
7207         I915_WRITE(EG0, 0x00007f00);
7208         I915_WRITE(EG1, 0x0000000e);
7209         I915_WRITE(EG2, 0x000e0000);
7210         I915_WRITE(EG3, 0x68000300);
7211         I915_WRITE(EG4, 0x42000000);
7212         I915_WRITE(EG5, 0x00140031);
7213         I915_WRITE(EG6, 0);
7214         I915_WRITE(EG7, 0);
7215
7216         for (i = 0; i < 8; i++)
7217                 I915_WRITE(PXWL + (i * 4), 0);
7218
7219         /* Enable PMON + select events */
7220         I915_WRITE(ECR, 0x80000019);
7221
7222         lcfuse = I915_READ(LCFUSE02);
7223
7224         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7225 }
7226
7227 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7228 {
7229         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7230         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7231         u32 pcu_mbox, rc6_mask = 0;
7232         int cur_freq, min_freq, max_freq;
7233         int i;
7234
7235         /* Here begins a magic sequence of register writes to enable
7236          * auto-downclocking.
7237          *
7238          * Perhaps there might be some value in exposing these to
7239          * userspace...
7240          */
7241         I915_WRITE(GEN6_RC_STATE, 0);
7242         mutex_lock(&dev_priv->dev->struct_mutex);
7243         gen6_gt_force_wake_get(dev_priv);
7244
7245         /* disable the counters and set deterministic thresholds */
7246         I915_WRITE(GEN6_RC_CONTROL, 0);
7247
7248         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7249         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7250         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7251         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7252         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7253
7254         for (i = 0; i < I915_NUM_RINGS; i++)
7255                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7256
7257         I915_WRITE(GEN6_RC_SLEEP, 0);
7258         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7259         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7260         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7261         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7262
7263         if (i915_enable_rc6)
7264                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7265                         GEN6_RC_CTL_RC6_ENABLE;
7266
7267         I915_WRITE(GEN6_RC_CONTROL,
7268                    rc6_mask |
7269                    GEN6_RC_CTL_EI_MODE(1) |
7270                    GEN6_RC_CTL_HW_ENABLE);
7271
7272         I915_WRITE(GEN6_RPNSWREQ,
7273                    GEN6_FREQUENCY(10) |
7274                    GEN6_OFFSET(0) |
7275                    GEN6_AGGRESSIVE_TURBO);
7276         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7277                    GEN6_FREQUENCY(12));
7278
7279         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7280         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7281                    18 << 24 |
7282                    6 << 16);
7283         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7284         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7285         I915_WRITE(GEN6_RP_UP_EI, 100000);
7286         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7287         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7288         I915_WRITE(GEN6_RP_CONTROL,
7289                    GEN6_RP_MEDIA_TURBO |
7290                    GEN6_RP_USE_NORMAL_FREQ |
7291                    GEN6_RP_MEDIA_IS_GFX |
7292                    GEN6_RP_ENABLE |
7293                    GEN6_RP_UP_BUSY_AVG |
7294                    GEN6_RP_DOWN_IDLE_CONT);
7295
7296         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7297                      500))
7298                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7299
7300         I915_WRITE(GEN6_PCODE_DATA, 0);
7301         I915_WRITE(GEN6_PCODE_MAILBOX,
7302                    GEN6_PCODE_READY |
7303                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7304         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7305                      500))
7306                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7307
7308         min_freq = (rp_state_cap & 0xff0000) >> 16;
7309         max_freq = rp_state_cap & 0xff;
7310         cur_freq = (gt_perf_status & 0xff00) >> 8;
7311
7312         /* Check for overclock support */
7313         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7314                      500))
7315                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7316         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7317         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7318         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7319                      500))
7320                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7321         if (pcu_mbox & (1<<31)) { /* OC supported */
7322                 max_freq = pcu_mbox & 0xff;
7323                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7324         }
7325
7326         /* In units of 100MHz */
7327         dev_priv->max_delay = max_freq;
7328         dev_priv->min_delay = min_freq;
7329         dev_priv->cur_delay = cur_freq;
7330
7331         /* requires MSI enabled */
7332         I915_WRITE(GEN6_PMIER,
7333                    GEN6_PM_MBOX_EVENT |
7334                    GEN6_PM_THERMAL_EVENT |
7335                    GEN6_PM_RP_DOWN_TIMEOUT |
7336                    GEN6_PM_RP_UP_THRESHOLD |
7337                    GEN6_PM_RP_DOWN_THRESHOLD |
7338                    GEN6_PM_RP_UP_EI_EXPIRED |
7339                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7340         spin_lock_irq(&dev_priv->rps_lock);
7341         WARN_ON(dev_priv->pm_iir != 0);
7342         I915_WRITE(GEN6_PMIMR, 0);
7343         spin_unlock_irq(&dev_priv->rps_lock);
7344         /* enable all PM interrupts */
7345         I915_WRITE(GEN6_PMINTRMSK, 0);
7346
7347         gen6_gt_force_wake_put(dev_priv);
7348         mutex_unlock(&dev_priv->dev->struct_mutex);
7349 }
7350
7351 static void ironlake_init_clock_gating(struct drm_device *dev)
7352 {
7353         struct drm_i915_private *dev_priv = dev->dev_private;
7354         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7355
7356         /* Required for FBC */
7357         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7358                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7359                 DPFDUNIT_CLOCK_GATE_DISABLE;
7360         /* Required for CxSR */
7361         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7362
7363         I915_WRITE(PCH_3DCGDIS0,
7364                    MARIUNIT_CLOCK_GATE_DISABLE |
7365                    SVSMUNIT_CLOCK_GATE_DISABLE);
7366         I915_WRITE(PCH_3DCGDIS1,
7367                    VFMUNIT_CLOCK_GATE_DISABLE);
7368
7369         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7370
7371         /*
7372          * According to the spec the following bits should be set in
7373          * order to enable memory self-refresh
7374          * The bit 22/21 of 0x42004
7375          * The bit 5 of 0x42020
7376          * The bit 15 of 0x45000
7377          */
7378         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7379                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7380                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7381         I915_WRITE(ILK_DSPCLK_GATE,
7382                    (I915_READ(ILK_DSPCLK_GATE) |
7383                     ILK_DPARB_CLK_GATE));
7384         I915_WRITE(DISP_ARB_CTL,
7385                    (I915_READ(DISP_ARB_CTL) |
7386                     DISP_FBC_WM_DIS));
7387         I915_WRITE(WM3_LP_ILK, 0);
7388         I915_WRITE(WM2_LP_ILK, 0);
7389         I915_WRITE(WM1_LP_ILK, 0);
7390
7391         /*
7392          * Based on the document from hardware guys the following bits
7393          * should be set unconditionally in order to enable FBC.
7394          * The bit 22 of 0x42000
7395          * The bit 22 of 0x42004
7396          * The bit 7,8,9 of 0x42020.
7397          */
7398         if (IS_IRONLAKE_M(dev)) {
7399                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7400                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7401                            ILK_FBCQ_DIS);
7402                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7403                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7404                            ILK_DPARB_GATE);
7405                 I915_WRITE(ILK_DSPCLK_GATE,
7406                            I915_READ(ILK_DSPCLK_GATE) |
7407                            ILK_DPFC_DIS1 |
7408                            ILK_DPFC_DIS2 |
7409                            ILK_CLK_FBC);
7410         }
7411
7412         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7413                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7414                    ILK_ELPIN_409_SELECT);
7415         I915_WRITE(_3D_CHICKEN2,
7416                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7417                    _3D_CHICKEN2_WM_READ_PIPELINED);
7418 }
7419
7420 static void gen6_init_clock_gating(struct drm_device *dev)
7421 {
7422         struct drm_i915_private *dev_priv = dev->dev_private;
7423         int pipe;
7424         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7425
7426         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7427
7428         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7429                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7430                    ILK_ELPIN_409_SELECT);
7431
7432         I915_WRITE(WM3_LP_ILK, 0);
7433         I915_WRITE(WM2_LP_ILK, 0);
7434         I915_WRITE(WM1_LP_ILK, 0);
7435
7436         /*
7437          * According to the spec the following bits should be
7438          * set in order to enable memory self-refresh and fbc:
7439          * The bit21 and bit22 of 0x42000
7440          * The bit21 and bit22 of 0x42004
7441          * The bit5 and bit7 of 0x42020
7442          * The bit14 of 0x70180
7443          * The bit14 of 0x71180
7444          */
7445         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7446                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7447                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7448         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7449                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7450                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7451         I915_WRITE(ILK_DSPCLK_GATE,
7452                    I915_READ(ILK_DSPCLK_GATE) |
7453                    ILK_DPARB_CLK_GATE  |
7454                    ILK_DPFD_CLK_GATE);
7455
7456         for_each_pipe(pipe) {
7457                 I915_WRITE(DSPCNTR(pipe),
7458                            I915_READ(DSPCNTR(pipe)) |
7459                            DISPPLANE_TRICKLE_FEED_DISABLE);
7460                 intel_flush_display_plane(dev_priv, pipe);
7461         }
7462 }
7463
7464 static void ivybridge_init_clock_gating(struct drm_device *dev)
7465 {
7466         struct drm_i915_private *dev_priv = dev->dev_private;
7467         int pipe;
7468         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7469
7470         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7471
7472         I915_WRITE(WM3_LP_ILK, 0);
7473         I915_WRITE(WM2_LP_ILK, 0);
7474         I915_WRITE(WM1_LP_ILK, 0);
7475
7476         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7477
7478         for_each_pipe(pipe) {
7479                 I915_WRITE(DSPCNTR(pipe),
7480                            I915_READ(DSPCNTR(pipe)) |
7481                            DISPPLANE_TRICKLE_FEED_DISABLE);
7482                 intel_flush_display_plane(dev_priv, pipe);
7483         }
7484 }
7485
7486 static void g4x_init_clock_gating(struct drm_device *dev)
7487 {
7488         struct drm_i915_private *dev_priv = dev->dev_private;
7489         uint32_t dspclk_gate;
7490
7491         I915_WRITE(RENCLK_GATE_D1, 0);
7492         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7493                    GS_UNIT_CLOCK_GATE_DISABLE |
7494                    CL_UNIT_CLOCK_GATE_DISABLE);
7495         I915_WRITE(RAMCLK_GATE_D, 0);
7496         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7497                 OVRUNIT_CLOCK_GATE_DISABLE |
7498                 OVCUNIT_CLOCK_GATE_DISABLE;
7499         if (IS_GM45(dev))
7500                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7501         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7502 }
7503
7504 static void crestline_init_clock_gating(struct drm_device *dev)
7505 {
7506         struct drm_i915_private *dev_priv = dev->dev_private;
7507
7508         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7509         I915_WRITE(RENCLK_GATE_D2, 0);
7510         I915_WRITE(DSPCLK_GATE_D, 0);
7511         I915_WRITE(RAMCLK_GATE_D, 0);
7512         I915_WRITE16(DEUC, 0);
7513 }
7514
7515 static void broadwater_init_clock_gating(struct drm_device *dev)
7516 {
7517         struct drm_i915_private *dev_priv = dev->dev_private;
7518
7519         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7520                    I965_RCC_CLOCK_GATE_DISABLE |
7521                    I965_RCPB_CLOCK_GATE_DISABLE |
7522                    I965_ISC_CLOCK_GATE_DISABLE |
7523                    I965_FBC_CLOCK_GATE_DISABLE);
7524         I915_WRITE(RENCLK_GATE_D2, 0);
7525 }
7526
7527 static void gen3_init_clock_gating(struct drm_device *dev)
7528 {
7529         struct drm_i915_private *dev_priv = dev->dev_private;
7530         u32 dstate = I915_READ(D_STATE);
7531
7532         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7533                 DSTATE_DOT_CLOCK_GATING;
7534         I915_WRITE(D_STATE, dstate);
7535 }
7536
7537 static void i85x_init_clock_gating(struct drm_device *dev)
7538 {
7539         struct drm_i915_private *dev_priv = dev->dev_private;
7540
7541         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7542 }
7543
7544 static void i830_init_clock_gating(struct drm_device *dev)
7545 {
7546         struct drm_i915_private *dev_priv = dev->dev_private;
7547
7548         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7549 }
7550
7551 static void ibx_init_clock_gating(struct drm_device *dev)
7552 {
7553         struct drm_i915_private *dev_priv = dev->dev_private;
7554
7555         /*
7556          * On Ibex Peak and Cougar Point, we need to disable clock
7557          * gating for the panel power sequencer or it will fail to
7558          * start up when no ports are active.
7559          */
7560         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7561 }
7562
7563 static void cpt_init_clock_gating(struct drm_device *dev)
7564 {
7565         struct drm_i915_private *dev_priv = dev->dev_private;
7566         int pipe;
7567
7568         /*
7569          * On Ibex Peak and Cougar Point, we need to disable clock
7570          * gating for the panel power sequencer or it will fail to
7571          * start up when no ports are active.
7572          */
7573         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7574         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7575                    DPLS_EDP_PPS_FIX_DIS);
7576         /* Without this, mode sets may fail silently on FDI */
7577         for_each_pipe(pipe)
7578                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
7579 }
7580
7581 static void ironlake_teardown_rc6(struct drm_device *dev)
7582 {
7583         struct drm_i915_private *dev_priv = dev->dev_private;
7584
7585         if (dev_priv->renderctx) {
7586                 i915_gem_object_unpin(dev_priv->renderctx);
7587                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7588                 dev_priv->renderctx = NULL;
7589         }
7590
7591         if (dev_priv->pwrctx) {
7592                 i915_gem_object_unpin(dev_priv->pwrctx);
7593                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7594                 dev_priv->pwrctx = NULL;
7595         }
7596 }
7597
7598 static void ironlake_disable_rc6(struct drm_device *dev)
7599 {
7600         struct drm_i915_private *dev_priv = dev->dev_private;
7601
7602         if (I915_READ(PWRCTXA)) {
7603                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7604                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7605                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7606                          50);
7607
7608                 I915_WRITE(PWRCTXA, 0);
7609                 POSTING_READ(PWRCTXA);
7610
7611                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7612                 POSTING_READ(RSTDBYCTL);
7613         }
7614
7615         ironlake_teardown_rc6(dev);
7616 }
7617
7618 static int ironlake_setup_rc6(struct drm_device *dev)
7619 {
7620         struct drm_i915_private *dev_priv = dev->dev_private;
7621
7622         if (dev_priv->renderctx == NULL)
7623                 dev_priv->renderctx = intel_alloc_context_page(dev);
7624         if (!dev_priv->renderctx)
7625                 return -ENOMEM;
7626
7627         if (dev_priv->pwrctx == NULL)
7628                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7629         if (!dev_priv->pwrctx) {
7630                 ironlake_teardown_rc6(dev);
7631                 return -ENOMEM;
7632         }
7633
7634         return 0;
7635 }
7636
7637 void ironlake_enable_rc6(struct drm_device *dev)
7638 {
7639         struct drm_i915_private *dev_priv = dev->dev_private;
7640         int ret;
7641
7642         /* rc6 disabled by default due to repeated reports of hanging during
7643          * boot and resume.
7644          */
7645         if (!i915_enable_rc6)
7646                 return;
7647
7648         mutex_lock(&dev->struct_mutex);
7649         ret = ironlake_setup_rc6(dev);
7650         if (ret) {
7651                 mutex_unlock(&dev->struct_mutex);
7652                 return;
7653         }
7654
7655         /*
7656          * GPU can automatically power down the render unit if given a page
7657          * to save state.
7658          */
7659         ret = BEGIN_LP_RING(6);
7660         if (ret) {
7661                 ironlake_teardown_rc6(dev);
7662                 mutex_unlock(&dev->struct_mutex);
7663                 return;
7664         }
7665
7666         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7667         OUT_RING(MI_SET_CONTEXT);
7668         OUT_RING(dev_priv->renderctx->gtt_offset |
7669                  MI_MM_SPACE_GTT |
7670                  MI_SAVE_EXT_STATE_EN |
7671                  MI_RESTORE_EXT_STATE_EN |
7672                  MI_RESTORE_INHIBIT);
7673         OUT_RING(MI_SUSPEND_FLUSH);
7674         OUT_RING(MI_NOOP);
7675         OUT_RING(MI_FLUSH);
7676         ADVANCE_LP_RING();
7677
7678         /*
7679          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7680          * does an implicit flush, combined with MI_FLUSH above, it should be
7681          * safe to assume that renderctx is valid
7682          */
7683         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7684         if (ret) {
7685                 DRM_ERROR("failed to enable ironlake power power savings\n");
7686                 ironlake_teardown_rc6(dev);
7687                 mutex_unlock(&dev->struct_mutex);
7688                 return;
7689         }
7690
7691         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7692         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7693         mutex_unlock(&dev->struct_mutex);
7694 }
7695
7696 void intel_init_clock_gating(struct drm_device *dev)
7697 {
7698         struct drm_i915_private *dev_priv = dev->dev_private;
7699
7700         dev_priv->display.init_clock_gating(dev);
7701
7702         if (dev_priv->display.init_pch_clock_gating)
7703                 dev_priv->display.init_pch_clock_gating(dev);
7704 }
7705
7706 /* Set up chip specific display functions */
7707 static void intel_init_display(struct drm_device *dev)
7708 {
7709         struct drm_i915_private *dev_priv = dev->dev_private;
7710
7711         /* We always want a DPMS function */
7712         if (HAS_PCH_SPLIT(dev)) {
7713                 dev_priv->display.dpms = ironlake_crtc_dpms;
7714                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7715         } else {
7716                 dev_priv->display.dpms = i9xx_crtc_dpms;
7717                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7718         }
7719
7720         if (I915_HAS_FBC(dev)) {
7721                 if (HAS_PCH_SPLIT(dev)) {
7722                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7723                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7724                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7725                 } else if (IS_GM45(dev)) {
7726                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7727                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7728                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7729                 } else if (IS_CRESTLINE(dev)) {
7730                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7731                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7732                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7733                 }
7734                 /* 855GM needs testing */
7735         }
7736
7737         /* Returns the core display clock speed */
7738         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7739                 dev_priv->display.get_display_clock_speed =
7740                         i945_get_display_clock_speed;
7741         else if (IS_I915G(dev))
7742                 dev_priv->display.get_display_clock_speed =
7743                         i915_get_display_clock_speed;
7744         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7745                 dev_priv->display.get_display_clock_speed =
7746                         i9xx_misc_get_display_clock_speed;
7747         else if (IS_I915GM(dev))
7748                 dev_priv->display.get_display_clock_speed =
7749                         i915gm_get_display_clock_speed;
7750         else if (IS_I865G(dev))
7751                 dev_priv->display.get_display_clock_speed =
7752                         i865_get_display_clock_speed;
7753         else if (IS_I85X(dev))
7754                 dev_priv->display.get_display_clock_speed =
7755                         i855_get_display_clock_speed;
7756         else /* 852, 830 */
7757                 dev_priv->display.get_display_clock_speed =
7758                         i830_get_display_clock_speed;
7759
7760         /* For FIFO watermark updates */
7761         if (HAS_PCH_SPLIT(dev)) {
7762                 if (HAS_PCH_IBX(dev))
7763                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7764                 else if (HAS_PCH_CPT(dev))
7765                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7766
7767                 if (IS_GEN5(dev)) {
7768                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7769                                 dev_priv->display.update_wm = ironlake_update_wm;
7770                         else {
7771                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7772                                               "Disable CxSR\n");
7773                                 dev_priv->display.update_wm = NULL;
7774                         }
7775                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7776                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7777                 } else if (IS_GEN6(dev)) {
7778                         if (SNB_READ_WM0_LATENCY()) {
7779                                 dev_priv->display.update_wm = sandybridge_update_wm;
7780                         } else {
7781                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7782                                               "Disable CxSR\n");
7783                                 dev_priv->display.update_wm = NULL;
7784                         }
7785                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7786                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7787                 } else if (IS_IVYBRIDGE(dev)) {
7788                         /* FIXME: detect B0+ stepping and use auto training */
7789                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7790                         if (SNB_READ_WM0_LATENCY()) {
7791                                 dev_priv->display.update_wm = sandybridge_update_wm;
7792                         } else {
7793                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7794                                               "Disable CxSR\n");
7795                                 dev_priv->display.update_wm = NULL;
7796                         }
7797                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7798
7799                 } else
7800                         dev_priv->display.update_wm = NULL;
7801         } else if (IS_PINEVIEW(dev)) {
7802                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7803                                             dev_priv->is_ddr3,
7804                                             dev_priv->fsb_freq,
7805                                             dev_priv->mem_freq)) {
7806                         DRM_INFO("failed to find known CxSR latency "
7807                                  "(found ddr%s fsb freq %d, mem freq %d), "
7808                                  "disabling CxSR\n",
7809                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7810                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7811                         /* Disable CxSR and never update its watermark again */
7812                         pineview_disable_cxsr(dev);
7813                         dev_priv->display.update_wm = NULL;
7814                 } else
7815                         dev_priv->display.update_wm = pineview_update_wm;
7816                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7817         } else if (IS_G4X(dev)) {
7818                 dev_priv->display.update_wm = g4x_update_wm;
7819                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7820         } else if (IS_GEN4(dev)) {
7821                 dev_priv->display.update_wm = i965_update_wm;
7822                 if (IS_CRESTLINE(dev))
7823                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7824                 else if (IS_BROADWATER(dev))
7825                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7826         } else if (IS_GEN3(dev)) {
7827                 dev_priv->display.update_wm = i9xx_update_wm;
7828                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7829                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7830         } else if (IS_I865G(dev)) {
7831                 dev_priv->display.update_wm = i830_update_wm;
7832                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7833                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7834         } else if (IS_I85X(dev)) {
7835                 dev_priv->display.update_wm = i9xx_update_wm;
7836                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7837                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7838         } else {
7839                 dev_priv->display.update_wm = i830_update_wm;
7840                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7841                 if (IS_845G(dev))
7842                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7843                 else
7844                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7845         }
7846
7847         /* Default just returns -ENODEV to indicate unsupported */
7848         dev_priv->display.queue_flip = intel_default_queue_flip;
7849
7850         switch (INTEL_INFO(dev)->gen) {
7851         case 2:
7852                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7853                 break;
7854
7855         case 3:
7856                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7857                 break;
7858
7859         case 4:
7860         case 5:
7861                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7862                 break;
7863
7864         case 6:
7865                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7866                 break;
7867         case 7:
7868                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7869                 break;
7870         }
7871 }
7872
7873 /*
7874  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7875  * resume, or other times.  This quirk makes sure that's the case for
7876  * affected systems.
7877  */
7878 static void quirk_pipea_force (struct drm_device *dev)
7879 {
7880         struct drm_i915_private *dev_priv = dev->dev_private;
7881
7882         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7883         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7884 }
7885
7886 /*
7887  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7888  */
7889 static void quirk_ssc_force_disable(struct drm_device *dev)
7890 {
7891         struct drm_i915_private *dev_priv = dev->dev_private;
7892         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7893 }
7894
7895 struct intel_quirk {
7896         int device;
7897         int subsystem_vendor;
7898         int subsystem_device;
7899         void (*hook)(struct drm_device *dev);
7900 };
7901
7902 struct intel_quirk intel_quirks[] = {
7903         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7904         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7905         /* HP Mini needs pipe A force quirk (LP: #322104) */
7906         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7907
7908         /* Thinkpad R31 needs pipe A force quirk */
7909         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7910         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7911         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7912
7913         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7914         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7915         /* ThinkPad X40 needs pipe A force quirk */
7916
7917         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7918         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7919
7920         /* 855 & before need to leave pipe A & dpll A up */
7921         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7922         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7923
7924         /* Lenovo U160 cannot use SSC on LVDS */
7925         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7926
7927         /* Sony Vaio Y cannot use SSC on LVDS */
7928         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7929 };
7930
7931 static void intel_init_quirks(struct drm_device *dev)
7932 {
7933         struct pci_dev *d = dev->pdev;
7934         int i;
7935
7936         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7937                 struct intel_quirk *q = &intel_quirks[i];
7938
7939                 if (d->device == q->device &&
7940                     (d->subsystem_vendor == q->subsystem_vendor ||
7941                      q->subsystem_vendor == PCI_ANY_ID) &&
7942                     (d->subsystem_device == q->subsystem_device ||
7943                      q->subsystem_device == PCI_ANY_ID))
7944                         q->hook(dev);
7945         }
7946 }
7947
7948 /* Disable the VGA plane that we never use */
7949 static void i915_disable_vga(struct drm_device *dev)
7950 {
7951         struct drm_i915_private *dev_priv = dev->dev_private;
7952         u8 sr1;
7953         u32 vga_reg;
7954
7955         if (HAS_PCH_SPLIT(dev))
7956                 vga_reg = CPU_VGACNTRL;
7957         else
7958                 vga_reg = VGACNTRL;
7959
7960         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7961         outb(1, VGA_SR_INDEX);
7962         sr1 = inb(VGA_SR_DATA);
7963         outb(sr1 | 1<<5, VGA_SR_DATA);
7964         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7965         udelay(300);
7966
7967         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7968         POSTING_READ(vga_reg);
7969 }
7970
7971 void intel_modeset_init(struct drm_device *dev)
7972 {
7973         struct drm_i915_private *dev_priv = dev->dev_private;
7974         int i;
7975
7976         drm_mode_config_init(dev);
7977
7978         dev->mode_config.min_width = 0;
7979         dev->mode_config.min_height = 0;
7980
7981         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7982
7983         intel_init_quirks(dev);
7984
7985         intel_init_display(dev);
7986
7987         if (IS_GEN2(dev)) {
7988                 dev->mode_config.max_width = 2048;
7989                 dev->mode_config.max_height = 2048;
7990         } else if (IS_GEN3(dev)) {
7991                 dev->mode_config.max_width = 4096;
7992                 dev->mode_config.max_height = 4096;
7993         } else {
7994                 dev->mode_config.max_width = 8192;
7995                 dev->mode_config.max_height = 8192;
7996         }
7997         dev->mode_config.fb_base = dev->agp->base;
7998
7999         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8000                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8001
8002         for (i = 0; i < dev_priv->num_pipe; i++) {
8003                 intel_crtc_init(dev, i);
8004         }
8005
8006         /* Just disable it once at startup */
8007         i915_disable_vga(dev);
8008         intel_setup_outputs(dev);
8009
8010         intel_init_clock_gating(dev);
8011
8012         if (IS_IRONLAKE_M(dev)) {
8013                 ironlake_enable_drps(dev);
8014                 intel_init_emon(dev);
8015         }
8016
8017         if (IS_GEN6(dev))
8018                 gen6_enable_rps(dev_priv);
8019
8020         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8021         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8022                     (unsigned long)dev);
8023 }
8024
8025 void intel_modeset_gem_init(struct drm_device *dev)
8026 {
8027         if (IS_IRONLAKE_M(dev))
8028                 ironlake_enable_rc6(dev);
8029
8030         intel_setup_overlay(dev);
8031 }
8032
8033 void intel_modeset_cleanup(struct drm_device *dev)
8034 {
8035         struct drm_i915_private *dev_priv = dev->dev_private;
8036         struct drm_crtc *crtc;
8037         struct intel_crtc *intel_crtc;
8038
8039         drm_kms_helper_poll_fini(dev);
8040         mutex_lock(&dev->struct_mutex);
8041
8042         intel_unregister_dsm_handler();
8043
8044
8045         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8046                 /* Skip inactive CRTCs */
8047                 if (!crtc->fb)
8048                         continue;
8049
8050                 intel_crtc = to_intel_crtc(crtc);
8051                 intel_increase_pllclock(crtc);
8052         }
8053
8054         if (dev_priv->display.disable_fbc)
8055                 dev_priv->display.disable_fbc(dev);
8056
8057         if (IS_IRONLAKE_M(dev))
8058                 ironlake_disable_drps(dev);
8059         if (IS_GEN6(dev))
8060                 gen6_disable_rps(dev);
8061
8062         if (IS_IRONLAKE_M(dev))
8063                 ironlake_disable_rc6(dev);
8064
8065         mutex_unlock(&dev->struct_mutex);
8066
8067         /* Disable the irq before mode object teardown, for the irq might
8068          * enqueue unpin/hotplug work. */
8069         drm_irq_uninstall(dev);
8070         cancel_work_sync(&dev_priv->hotplug_work);
8071
8072         /* Shut off idle work before the crtcs get freed. */
8073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8074                 intel_crtc = to_intel_crtc(crtc);
8075                 del_timer_sync(&intel_crtc->idle_timer);
8076         }
8077         del_timer_sync(&dev_priv->idle_timer);
8078         cancel_work_sync(&dev_priv->idle_work);
8079
8080         drm_mode_config_cleanup(dev);
8081 }
8082
8083 /*
8084  * Return which encoder is currently attached for connector.
8085  */
8086 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8087 {
8088         return &intel_attached_encoder(connector)->base;
8089 }
8090
8091 void intel_connector_attach_encoder(struct intel_connector *connector,
8092                                     struct intel_encoder *encoder)
8093 {
8094         connector->encoder = encoder;
8095         drm_mode_connector_attach_encoder(&connector->base,
8096                                           &encoder->base);
8097 }
8098
8099 /*
8100  * set vga decode state - true == enable VGA decode
8101  */
8102 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8103 {
8104         struct drm_i915_private *dev_priv = dev->dev_private;
8105         u16 gmch_ctrl;
8106
8107         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8108         if (state)
8109                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8110         else
8111                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8112         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8113         return 0;
8114 }
8115
8116 #ifdef CONFIG_DEBUG_FS
8117 #include <linux/seq_file.h>
8118
8119 struct intel_display_error_state {
8120         struct intel_cursor_error_state {
8121                 u32 control;
8122                 u32 position;
8123                 u32 base;
8124                 u32 size;
8125         } cursor[2];
8126
8127         struct intel_pipe_error_state {
8128                 u32 conf;
8129                 u32 source;
8130
8131                 u32 htotal;
8132                 u32 hblank;
8133                 u32 hsync;
8134                 u32 vtotal;
8135                 u32 vblank;
8136                 u32 vsync;
8137         } pipe[2];
8138
8139         struct intel_plane_error_state {
8140                 u32 control;
8141                 u32 stride;
8142                 u32 size;
8143                 u32 pos;
8144                 u32 addr;
8145                 u32 surface;
8146                 u32 tile_offset;
8147         } plane[2];
8148 };
8149
8150 struct intel_display_error_state *
8151 intel_display_capture_error_state(struct drm_device *dev)
8152 {
8153         drm_i915_private_t *dev_priv = dev->dev_private;
8154         struct intel_display_error_state *error;
8155         int i;
8156
8157         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8158         if (error == NULL)
8159                 return NULL;
8160
8161         for (i = 0; i < 2; i++) {
8162                 error->cursor[i].control = I915_READ(CURCNTR(i));
8163                 error->cursor[i].position = I915_READ(CURPOS(i));
8164                 error->cursor[i].base = I915_READ(CURBASE(i));
8165
8166                 error->plane[i].control = I915_READ(DSPCNTR(i));
8167                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8168                 error->plane[i].size = I915_READ(DSPSIZE(i));
8169                 error->plane[i].pos= I915_READ(DSPPOS(i));
8170                 error->plane[i].addr = I915_READ(DSPADDR(i));
8171                 if (INTEL_INFO(dev)->gen >= 4) {
8172                         error->plane[i].surface = I915_READ(DSPSURF(i));
8173                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8174                 }
8175
8176                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8177                 error->pipe[i].source = I915_READ(PIPESRC(i));
8178                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8179                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8180                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8181                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8182                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8183                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8184         }
8185
8186         return error;
8187 }
8188
8189 void
8190 intel_display_print_error_state(struct seq_file *m,
8191                                 struct drm_device *dev,
8192                                 struct intel_display_error_state *error)
8193 {
8194         int i;
8195
8196         for (i = 0; i < 2; i++) {
8197                 seq_printf(m, "Pipe [%d]:\n", i);
8198                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8199                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8200                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8201                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8202                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8203                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8204                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8205                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8206
8207                 seq_printf(m, "Plane [%d]:\n", i);
8208                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8209                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8210                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8211                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8212                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8213                 if (INTEL_INFO(dev)->gen >= 4) {
8214                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8215                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8216                 }
8217
8218                 seq_printf(m, "Cursor [%d]:\n", i);
8219                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8220                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8221                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8222         }
8223 }
8224 #endif