2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
32 #include "intel_drv.h"
35 #include "drm_dp_helper.h"
37 #include "drm_crtc_helper.h"
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
75 #define I8XX_DOT_MIN 25000
76 #define I8XX_DOT_MAX 350000
77 #define I8XX_VCO_MIN 930000
78 #define I8XX_VCO_MAX 1400000
82 #define I8XX_M_MAX 140
83 #define I8XX_M1_MIN 18
84 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MAX 16
88 #define I8XX_P_MAX 128
90 #define I8XX_P1_MAX 33
91 #define I8XX_P1_LVDS_MIN 1
92 #define I8XX_P1_LVDS_MAX 6
93 #define I8XX_P2_SLOW 4
94 #define I8XX_P2_FAST 2
95 #define I8XX_P2_LVDS_SLOW 14
96 #define I8XX_P2_LVDS_FAST 7
97 #define I8XX_P2_SLOW_LIMIT 165000
99 #define I9XX_DOT_MIN 20000
100 #define I9XX_DOT_MAX 400000
101 #define I9XX_VCO_MIN 1400000
102 #define I9XX_VCO_MAX 2800000
103 #define PINEVIEW_VCO_MIN 1700000
104 #define PINEVIEW_VCO_MAX 3500000
107 /* Pineview's Ncounter is a ring counter */
108 #define PINEVIEW_N_MIN 3
109 #define PINEVIEW_N_MAX 6
110 #define I9XX_M_MIN 70
111 #define I9XX_M_MAX 120
112 #define PINEVIEW_M_MIN 2
113 #define PINEVIEW_M_MAX 256
114 #define I9XX_M1_MIN 10
115 #define I9XX_M1_MAX 22
116 #define I9XX_M2_MIN 5
117 #define I9XX_M2_MAX 9
118 /* Pineview M1 is reserved, and must be 0 */
119 #define PINEVIEW_M1_MIN 0
120 #define PINEVIEW_M1_MAX 0
121 #define PINEVIEW_M2_MIN 0
122 #define PINEVIEW_M2_MAX 254
123 #define I9XX_P_SDVO_DAC_MIN 5
124 #define I9XX_P_SDVO_DAC_MAX 80
125 #define I9XX_P_LVDS_MIN 7
126 #define I9XX_P_LVDS_MAX 98
127 #define PINEVIEW_P_LVDS_MIN 7
128 #define PINEVIEW_P_LVDS_MAX 112
129 #define I9XX_P1_MIN 1
130 #define I9XX_P1_MAX 8
131 #define I9XX_P2_SDVO_DAC_SLOW 10
132 #define I9XX_P2_SDVO_DAC_FAST 5
133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134 #define I9XX_P2_LVDS_SLOW 14
135 #define I9XX_P2_LVDS_FAST 7
136 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138 /*The parameter is for SDVO on G4x platform*/
139 #define G4X_DOT_SDVO_MIN 25000
140 #define G4X_DOT_SDVO_MAX 270000
141 #define G4X_VCO_MIN 1750000
142 #define G4X_VCO_MAX 3500000
143 #define G4X_N_SDVO_MIN 1
144 #define G4X_N_SDVO_MAX 4
145 #define G4X_M_SDVO_MIN 104
146 #define G4X_M_SDVO_MAX 138
147 #define G4X_M1_SDVO_MIN 17
148 #define G4X_M1_SDVO_MAX 23
149 #define G4X_M2_SDVO_MIN 5
150 #define G4X_M2_SDVO_MAX 11
151 #define G4X_P_SDVO_MIN 10
152 #define G4X_P_SDVO_MAX 30
153 #define G4X_P1_SDVO_MIN 1
154 #define G4X_P1_SDVO_MAX 3
155 #define G4X_P2_SDVO_SLOW 10
156 #define G4X_P2_SDVO_FAST 10
157 #define G4X_P2_SDVO_LIMIT 270000
159 /*The parameter is for HDMI_DAC on G4x platform*/
160 #define G4X_DOT_HDMI_DAC_MIN 22000
161 #define G4X_DOT_HDMI_DAC_MAX 400000
162 #define G4X_N_HDMI_DAC_MIN 1
163 #define G4X_N_HDMI_DAC_MAX 4
164 #define G4X_M_HDMI_DAC_MIN 104
165 #define G4X_M_HDMI_DAC_MAX 138
166 #define G4X_M1_HDMI_DAC_MIN 16
167 #define G4X_M1_HDMI_DAC_MAX 23
168 #define G4X_M2_HDMI_DAC_MIN 5
169 #define G4X_M2_HDMI_DAC_MAX 11
170 #define G4X_P_HDMI_DAC_MIN 5
171 #define G4X_P_HDMI_DAC_MAX 80
172 #define G4X_P1_HDMI_DAC_MIN 1
173 #define G4X_P1_HDMI_DAC_MAX 8
174 #define G4X_P2_HDMI_DAC_SLOW 10
175 #define G4X_P2_HDMI_DAC_FAST 5
176 #define G4X_P2_HDMI_DAC_LIMIT 165000
178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216 /*The parameter is for DISPLAY PORT on G4x platform*/
217 #define G4X_DOT_DISPLAY_PORT_MIN 161670
218 #define G4X_DOT_DISPLAY_PORT_MAX 227000
219 #define G4X_N_DISPLAY_PORT_MIN 1
220 #define G4X_N_DISPLAY_PORT_MAX 2
221 #define G4X_M_DISPLAY_PORT_MIN 97
222 #define G4X_M_DISPLAY_PORT_MAX 108
223 #define G4X_M1_DISPLAY_PORT_MIN 0x10
224 #define G4X_M1_DISPLAY_PORT_MAX 0x12
225 #define G4X_M2_DISPLAY_PORT_MIN 0x05
226 #define G4X_M2_DISPLAY_PORT_MAX 0x06
227 #define G4X_P_DISPLAY_PORT_MIN 10
228 #define G4X_P_DISPLAY_PORT_MAX 20
229 #define G4X_P1_DISPLAY_PORT_MIN 1
230 #define G4X_P1_DISPLAY_PORT_MAX 2
231 #define G4X_P2_DISPLAY_PORT_SLOW 10
232 #define G4X_P2_DISPLAY_PORT_FAST 10
233 #define G4X_P2_DISPLAY_PORT_LIMIT 0
235 /* Ironlake / Sandybridge */
236 /* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
239 #define IRONLAKE_DOT_MIN 25000
240 #define IRONLAKE_DOT_MAX 350000
241 #define IRONLAKE_VCO_MIN 1760000
242 #define IRONLAKE_VCO_MAX 3510000
243 #define IRONLAKE_M1_MIN 12
244 #define IRONLAKE_M1_MAX 22
245 #define IRONLAKE_M2_MIN 5
246 #define IRONLAKE_M2_MAX 9
247 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
249 /* We have parameter ranges for different type of outputs. */
251 /* DAC & HDMI Refclk 120Mhz */
252 #define IRONLAKE_DAC_N_MIN 1
253 #define IRONLAKE_DAC_N_MAX 5
254 #define IRONLAKE_DAC_M_MIN 79
255 #define IRONLAKE_DAC_M_MAX 127
256 #define IRONLAKE_DAC_P_MIN 5
257 #define IRONLAKE_DAC_P_MAX 80
258 #define IRONLAKE_DAC_P1_MIN 1
259 #define IRONLAKE_DAC_P1_MAX 8
260 #define IRONLAKE_DAC_P2_SLOW 10
261 #define IRONLAKE_DAC_P2_FAST 5
263 /* LVDS single-channel 120Mhz refclk */
264 #define IRONLAKE_LVDS_S_N_MIN 1
265 #define IRONLAKE_LVDS_S_N_MAX 3
266 #define IRONLAKE_LVDS_S_M_MIN 79
267 #define IRONLAKE_LVDS_S_M_MAX 118
268 #define IRONLAKE_LVDS_S_P_MIN 28
269 #define IRONLAKE_LVDS_S_P_MAX 112
270 #define IRONLAKE_LVDS_S_P1_MIN 2
271 #define IRONLAKE_LVDS_S_P1_MAX 8
272 #define IRONLAKE_LVDS_S_P2_SLOW 14
273 #define IRONLAKE_LVDS_S_P2_FAST 14
275 /* LVDS dual-channel 120Mhz refclk */
276 #define IRONLAKE_LVDS_D_N_MIN 1
277 #define IRONLAKE_LVDS_D_N_MAX 3
278 #define IRONLAKE_LVDS_D_M_MIN 79
279 #define IRONLAKE_LVDS_D_M_MAX 127
280 #define IRONLAKE_LVDS_D_P_MIN 14
281 #define IRONLAKE_LVDS_D_P_MAX 56
282 #define IRONLAKE_LVDS_D_P1_MIN 2
283 #define IRONLAKE_LVDS_D_P1_MAX 8
284 #define IRONLAKE_LVDS_D_P2_SLOW 7
285 #define IRONLAKE_LVDS_D_P2_FAST 7
287 /* LVDS single-channel 100Mhz refclk */
288 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
289 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
290 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
291 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
292 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
293 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
294 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
295 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
297 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299 /* LVDS dual-channel 100Mhz refclk */
300 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
301 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
302 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
303 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
304 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
305 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
306 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
307 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
309 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
312 #define IRONLAKE_DP_N_MIN 1
313 #define IRONLAKE_DP_N_MAX 2
314 #define IRONLAKE_DP_M_MIN 81
315 #define IRONLAKE_DP_M_MAX 90
316 #define IRONLAKE_DP_P_MIN 10
317 #define IRONLAKE_DP_P_MAX 20
318 #define IRONLAKE_DP_P2_FAST 10
319 #define IRONLAKE_DP_P2_SLOW 10
320 #define IRONLAKE_DP_P2_LIMIT 0
321 #define IRONLAKE_DP_P1_MIN 1
322 #define IRONLAKE_DP_P1_MAX 2
325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
326 int target, int refclk, intel_clock_t *best_clock);
328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
329 int target, int refclk, intel_clock_t *best_clock);
332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
338 static const intel_limit_t intel_limits_i8xx_dvo = {
339 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
340 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
341 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
342 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
343 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
344 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
345 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
346 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
347 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
348 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
349 .find_pll = intel_find_best_PLL,
352 static const intel_limit_t intel_limits_i8xx_lvds = {
353 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
354 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
355 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
356 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
357 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
358 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
359 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
360 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
361 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
362 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
363 .find_pll = intel_find_best_PLL,
366 static const intel_limit_t intel_limits_i9xx_sdvo = {
367 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
368 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
369 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
370 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
371 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
372 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
373 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
374 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
375 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
376 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
377 .find_pll = intel_find_best_PLL,
380 static const intel_limit_t intel_limits_i9xx_lvds = {
381 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
382 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
383 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
384 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
385 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
386 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
387 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
388 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
389 /* The single-channel range is 25-112Mhz, and dual-channel
390 * is 80-224Mhz. Prefer single channel as much as possible.
392 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
394 .find_pll = intel_find_best_PLL,
397 /* below parameter and function is for G4X Chipset Family*/
398 static const intel_limit_t intel_limits_g4x_sdvo = {
399 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
400 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
401 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
402 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
403 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
404 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
405 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
406 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
407 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
408 .p2_slow = G4X_P2_SDVO_SLOW,
409 .p2_fast = G4X_P2_SDVO_FAST
411 .find_pll = intel_g4x_find_best_PLL,
414 static const intel_limit_t intel_limits_g4x_hdmi = {
415 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
416 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
417 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
418 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
419 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
420 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
421 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
422 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
423 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
424 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
425 .p2_fast = G4X_P2_HDMI_DAC_FAST
427 .find_pll = intel_g4x_find_best_PLL,
430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
431 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
432 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
433 .vco = { .min = G4X_VCO_MIN,
434 .max = G4X_VCO_MAX },
435 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
436 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
437 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
438 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
439 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
440 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
441 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
442 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
443 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
444 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
445 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
447 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
448 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
449 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451 .find_pll = intel_g4x_find_best_PLL,
454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
455 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
456 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
457 .vco = { .min = G4X_VCO_MIN,
458 .max = G4X_VCO_MAX },
459 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
460 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
461 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
462 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
463 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
464 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
465 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
466 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
467 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
468 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
469 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
471 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
472 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
473 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475 .find_pll = intel_g4x_find_best_PLL,
478 static const intel_limit_t intel_limits_g4x_display_port = {
479 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
480 .max = G4X_DOT_DISPLAY_PORT_MAX },
481 .vco = { .min = G4X_VCO_MIN,
483 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
484 .max = G4X_N_DISPLAY_PORT_MAX },
485 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
486 .max = G4X_M_DISPLAY_PORT_MAX },
487 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
488 .max = G4X_M1_DISPLAY_PORT_MAX },
489 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
490 .max = G4X_M2_DISPLAY_PORT_MAX },
491 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
492 .max = G4X_P_DISPLAY_PORT_MAX },
493 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
494 .max = G4X_P1_DISPLAY_PORT_MAX},
495 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
496 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
497 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
498 .find_pll = intel_find_pll_g4x_dp,
501 static const intel_limit_t intel_limits_pineview_sdvo = {
502 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
503 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
504 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
505 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
506 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
507 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
508 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
509 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
510 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
511 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
512 .find_pll = intel_find_best_PLL,
515 static const intel_limit_t intel_limits_pineview_lvds = {
516 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
517 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
518 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
519 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
520 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
521 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
522 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
523 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
524 /* Pineview only supports single-channel mode. */
525 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
526 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
527 .find_pll = intel_find_best_PLL,
530 static const intel_limit_t intel_limits_ironlake_dac = {
531 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
532 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
533 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
534 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
535 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
536 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
537 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
538 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
539 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
540 .p2_slow = IRONLAKE_DAC_P2_SLOW,
541 .p2_fast = IRONLAKE_DAC_P2_FAST },
542 .find_pll = intel_g4x_find_best_PLL,
545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
546 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
547 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
548 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
549 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
550 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
551 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
552 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
553 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
554 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
555 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
556 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
557 .find_pll = intel_g4x_find_best_PLL,
560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
561 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
562 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
563 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
564 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
565 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
566 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
567 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
568 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
569 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
570 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
571 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
572 .find_pll = intel_g4x_find_best_PLL,
575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
576 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
577 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
578 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
579 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
580 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
581 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
582 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
583 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
584 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
585 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
586 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
587 .find_pll = intel_g4x_find_best_PLL,
590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
591 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
592 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
593 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
594 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
595 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
596 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
597 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
598 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
599 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
600 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
601 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
602 .find_pll = intel_g4x_find_best_PLL,
605 static const intel_limit_t intel_limits_ironlake_display_port = {
606 .dot = { .min = IRONLAKE_DOT_MIN,
607 .max = IRONLAKE_DOT_MAX },
608 .vco = { .min = IRONLAKE_VCO_MIN,
609 .max = IRONLAKE_VCO_MAX},
610 .n = { .min = IRONLAKE_DP_N_MIN,
611 .max = IRONLAKE_DP_N_MAX },
612 .m = { .min = IRONLAKE_DP_M_MIN,
613 .max = IRONLAKE_DP_M_MAX },
614 .m1 = { .min = IRONLAKE_M1_MIN,
615 .max = IRONLAKE_M1_MAX },
616 .m2 = { .min = IRONLAKE_M2_MIN,
617 .max = IRONLAKE_M2_MAX },
618 .p = { .min = IRONLAKE_DP_P_MIN,
619 .max = IRONLAKE_DP_P_MAX },
620 .p1 = { .min = IRONLAKE_DP_P1_MIN,
621 .max = IRONLAKE_DP_P1_MAX},
622 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
623 .p2_slow = IRONLAKE_DP_P2_SLOW,
624 .p2_fast = IRONLAKE_DP_P2_FAST },
625 .find_pll = intel_find_pll_ironlake_dp,
628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 struct drm_device *dev = crtc->dev;
631 struct drm_i915_private *dev_priv = dev->dev_private;
632 const intel_limit_t *limit;
635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
636 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
639 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
640 LVDS_CLKB_POWER_UP) {
641 /* LVDS dual channel */
643 limit = &intel_limits_ironlake_dual_lvds_100m;
645 limit = &intel_limits_ironlake_dual_lvds;
648 limit = &intel_limits_ironlake_single_lvds_100m;
650 limit = &intel_limits_ironlake_single_lvds;
652 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654 limit = &intel_limits_ironlake_display_port;
656 limit = &intel_limits_ironlake_dac;
661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 struct drm_device *dev = crtc->dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
665 const intel_limit_t *limit;
667 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
668 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670 /* LVDS with dual channel */
671 limit = &intel_limits_g4x_dual_channel_lvds;
673 /* LVDS with dual channel */
674 limit = &intel_limits_g4x_single_channel_lvds;
675 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
676 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
677 limit = &intel_limits_g4x_hdmi;
678 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
679 limit = &intel_limits_g4x_sdvo;
680 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
681 limit = &intel_limits_g4x_display_port;
682 } else /* The option is for other outputs */
683 limit = &intel_limits_i9xx_sdvo;
688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 struct drm_device *dev = crtc->dev;
691 const intel_limit_t *limit;
693 if (HAS_PCH_SPLIT(dev))
694 limit = intel_ironlake_limit(crtc);
695 else if (IS_G4X(dev)) {
696 limit = intel_g4x_limit(crtc);
697 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
698 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
699 limit = &intel_limits_i9xx_lvds;
701 limit = &intel_limits_i9xx_sdvo;
702 } else if (IS_PINEVIEW(dev)) {
703 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
704 limit = &intel_limits_pineview_lvds;
706 limit = &intel_limits_pineview_sdvo;
708 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
709 limit = &intel_limits_i8xx_lvds;
711 limit = &intel_limits_i8xx_dvo;
716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
717 static void pineview_clock(int refclk, intel_clock_t *clock)
719 clock->m = clock->m2 + 2;
720 clock->p = clock->p1 * clock->p2;
721 clock->vco = refclk * clock->m / clock->n;
722 clock->dot = clock->vco / clock->p;
725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 if (IS_PINEVIEW(dev)) {
728 pineview_clock(refclk, clock);
731 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
732 clock->p = clock->p1 * clock->p2;
733 clock->vco = refclk * clock->m / (clock->n + 2);
734 clock->dot = clock->vco / clock->p;
738 * Returns whether any output on the specified pipe is of the specified type
740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 struct drm_device *dev = crtc->dev;
743 struct drm_mode_config *mode_config = &dev->mode_config;
744 struct drm_encoder *l_entry;
746 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
747 if (l_entry && l_entry->crtc == crtc) {
748 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
749 if (intel_encoder->type == type)
756 static struct drm_connector *
757 intel_pipe_get_connector (struct drm_crtc *crtc)
759 struct drm_device *dev = crtc->dev;
760 struct drm_mode_config *mode_config = &dev->mode_config;
761 struct drm_connector *l_entry, *ret = NULL;
763 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
764 if (l_entry->encoder &&
765 l_entry->encoder->crtc == crtc) {
773 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
775 * Returns whether the given set of divisors are valid for a given refclk with
776 * the given connectors.
779 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
781 const intel_limit_t *limit = intel_limit (crtc);
782 struct drm_device *dev = crtc->dev;
784 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
785 INTELPllInvalid ("p1 out of range\n");
786 if (clock->p < limit->p.min || limit->p.max < clock->p)
787 INTELPllInvalid ("p out of range\n");
788 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
789 INTELPllInvalid ("m2 out of range\n");
790 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
791 INTELPllInvalid ("m1 out of range\n");
792 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
793 INTELPllInvalid ("m1 <= m2\n");
794 if (clock->m < limit->m.min || limit->m.max < clock->m)
795 INTELPllInvalid ("m out of range\n");
796 if (clock->n < limit->n.min || limit->n.max < clock->n)
797 INTELPllInvalid ("n out of range\n");
798 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
799 INTELPllInvalid ("vco out of range\n");
800 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
801 * connector, etc., rather than just a single range.
803 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
804 INTELPllInvalid ("dot out of range\n");
810 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
811 int target, int refclk, intel_clock_t *best_clock)
814 struct drm_device *dev = crtc->dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
819 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
820 (I915_READ(LVDS)) != 0) {
822 * For LVDS, if the panel is on, just rely on its current
823 * settings for dual-channel. We haven't figured out how to
824 * reliably set up different single/dual channel state, if we
827 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
829 clock.p2 = limit->p2.p2_fast;
831 clock.p2 = limit->p2.p2_slow;
833 if (target < limit->p2.dot_limit)
834 clock.p2 = limit->p2.p2_slow;
836 clock.p2 = limit->p2.p2_fast;
839 memset (best_clock, 0, sizeof (*best_clock));
841 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
843 for (clock.m2 = limit->m2.min;
844 clock.m2 <= limit->m2.max; clock.m2++) {
845 /* m1 is always 0 in Pineview */
846 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
848 for (clock.n = limit->n.min;
849 clock.n <= limit->n.max; clock.n++) {
850 for (clock.p1 = limit->p1.min;
851 clock.p1 <= limit->p1.max; clock.p1++) {
854 intel_clock(dev, refclk, &clock);
856 if (!intel_PLL_is_valid(crtc, &clock))
859 this_err = abs(clock.dot - target);
860 if (this_err < err) {
869 return (err != target);
873 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
874 int target, int refclk, intel_clock_t *best_clock)
876 struct drm_device *dev = crtc->dev;
877 struct drm_i915_private *dev_priv = dev->dev_private;
881 /* approximately equals target * 0.00488 */
882 int err_most = (target >> 8) + (target >> 10);
885 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
888 if (HAS_PCH_SPLIT(dev))
892 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
894 clock.p2 = limit->p2.p2_fast;
896 clock.p2 = limit->p2.p2_slow;
898 if (target < limit->p2.dot_limit)
899 clock.p2 = limit->p2.p2_slow;
901 clock.p2 = limit->p2.p2_fast;
904 memset(best_clock, 0, sizeof(*best_clock));
905 max_n = limit->n.max;
906 /* based on hardware requriment prefer smaller n to precision */
907 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
908 /* based on hardware requirment prefere larger m1,m2 */
909 for (clock.m1 = limit->m1.max;
910 clock.m1 >= limit->m1.min; clock.m1--) {
911 for (clock.m2 = limit->m2.max;
912 clock.m2 >= limit->m2.min; clock.m2--) {
913 for (clock.p1 = limit->p1.max;
914 clock.p1 >= limit->p1.min; clock.p1--) {
917 intel_clock(dev, refclk, &clock);
918 if (!intel_PLL_is_valid(crtc, &clock))
920 this_err = abs(clock.dot - target) ;
921 if (this_err < err_most) {
935 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
936 int target, int refclk, intel_clock_t *best_clock)
938 struct drm_device *dev = crtc->dev;
941 /* return directly when it is eDP */
945 if (target < 200000) {
958 intel_clock(dev, refclk, &clock);
959 memcpy(best_clock, &clock, sizeof(intel_clock_t));
963 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
965 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
966 int target, int refclk, intel_clock_t *best_clock)
969 if (target < 200000) {
982 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
983 clock.p = (clock.p1 * clock.p2);
984 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
986 memcpy(best_clock, &clock, sizeof(intel_clock_t));
991 intel_wait_for_vblank(struct drm_device *dev)
993 /* Wait for 20ms, i.e. one cycle at 50hz. */
997 /* Parameters have changed, update FBC info */
998 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1000 struct drm_device *dev = crtc->dev;
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002 struct drm_framebuffer *fb = crtc->fb;
1003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1004 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007 u32 fbc_ctl, fbc_ctl2;
1009 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1011 if (fb->pitch < dev_priv->cfb_pitch)
1012 dev_priv->cfb_pitch = fb->pitch;
1014 /* FBC_CTL wants 64B units */
1015 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1016 dev_priv->cfb_fence = obj_priv->fence_reg;
1017 dev_priv->cfb_plane = intel_crtc->plane;
1018 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1020 /* Clear old tags */
1021 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1022 I915_WRITE(FBC_TAG + (i * 4), 0);
1025 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1026 if (obj_priv->tiling_mode != I915_TILING_NONE)
1027 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1028 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1029 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1032 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1034 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1035 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1036 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1037 if (obj_priv->tiling_mode != I915_TILING_NONE)
1038 fbc_ctl |= dev_priv->cfb_fence;
1039 I915_WRITE(FBC_CONTROL, fbc_ctl);
1041 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1042 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1045 void i8xx_disable_fbc(struct drm_device *dev)
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1050 if (!I915_HAS_FBC(dev))
1053 /* Disable compression */
1054 fbc_ctl = I915_READ(FBC_CONTROL);
1055 fbc_ctl &= ~FBC_CTL_EN;
1056 I915_WRITE(FBC_CONTROL, fbc_ctl);
1058 /* Wait for compressing bit to clear */
1059 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1062 intel_wait_for_vblank(dev);
1064 DRM_DEBUG_KMS("disabled FBC\n");
1067 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1069 struct drm_device *dev = crtc->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1072 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1077 struct drm_device *dev = crtc->dev;
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 struct drm_framebuffer *fb = crtc->fb;
1080 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1085 unsigned long stall_watermark = 200;
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1092 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1097 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1100 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1107 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1109 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1112 void g4x_disable_fbc(struct drm_device *dev)
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1117 /* Disable compression */
1118 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1123 DRM_DEBUG_KMS("disabled FBC\n");
1126 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1128 struct drm_device *dev = crtc->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1131 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1135 * intel_update_fbc - enable/disable FBC as needed
1136 * @crtc: CRTC to point the compressor at
1137 * @mode: mode in use
1139 * Set up the framebuffer compression hardware at mode set time. We
1140 * enable it if possible:
1141 * - plane A only (on pre-965)
1142 * - no pixel mulitply/line duplication
1143 * - no alpha buffer discard
1145 * - framebuffer <= 2048 in width, 1536 in height
1147 * We can't assume that any compression will take place (worst case),
1148 * so the compressed buffer has to be the same size as the uncompressed
1149 * one. It also must reside (along with the line length buffer) in
1152 * We need to enable/disable FBC on a global basis.
1154 static void intel_update_fbc(struct drm_crtc *crtc,
1155 struct drm_display_mode *mode)
1157 struct drm_device *dev = crtc->dev;
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1159 struct drm_framebuffer *fb = crtc->fb;
1160 struct intel_framebuffer *intel_fb;
1161 struct drm_i915_gem_object *obj_priv;
1162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1163 int plane = intel_crtc->plane;
1165 if (!i915_powersave)
1168 if (!dev_priv->display.fbc_enabled ||
1169 !dev_priv->display.enable_fbc ||
1170 !dev_priv->display.disable_fbc)
1176 intel_fb = to_intel_framebuffer(fb);
1177 obj_priv = to_intel_bo(intel_fb->obj);
1180 * If FBC is already on, we just have to verify that we can
1181 * keep it that way...
1182 * Need to disable if:
1183 * - changing FBC params (stride, fence, mode)
1184 * - new fb is too large to fit in compressed buffer
1185 * - going to an unsupported config (interlace, pixel multiply, etc.)
1187 if (intel_fb->obj->size > dev_priv->cfb_size) {
1188 DRM_DEBUG_KMS("framebuffer too large, disabling "
1190 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1193 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1194 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1195 DRM_DEBUG_KMS("mode incompatible with compression, "
1197 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1200 if ((mode->hdisplay > 2048) ||
1201 (mode->vdisplay > 1536)) {
1202 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1203 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1206 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1207 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1208 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1211 if (obj_priv->tiling_mode != I915_TILING_X) {
1212 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1213 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1217 if (dev_priv->display.fbc_enabled(crtc)) {
1218 /* We can re-enable it in this case, but need to update pitch */
1219 if (fb->pitch > dev_priv->cfb_pitch)
1220 dev_priv->display.disable_fbc(dev);
1221 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1222 dev_priv->display.disable_fbc(dev);
1223 if (plane != dev_priv->cfb_plane)
1224 dev_priv->display.disable_fbc(dev);
1227 if (!dev_priv->display.fbc_enabled(crtc)) {
1228 /* Now try to turn it back on if possible */
1229 dev_priv->display.enable_fbc(crtc, 500);
1235 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1236 /* Multiple disables should be harmless */
1237 if (dev_priv->display.fbc_enabled(crtc))
1238 dev_priv->display.disable_fbc(dev);
1242 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1244 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1248 switch (obj_priv->tiling_mode) {
1249 case I915_TILING_NONE:
1250 alignment = 64 * 1024;
1253 /* pin() will align the object as required by fence */
1257 /* FIXME: Is this true? */
1258 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1264 ret = i915_gem_object_pin(obj, alignment);
1268 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1269 * fence, whereas 965+ only requires a fence if using
1270 * framebuffer compression. For simplicity, we always install
1271 * a fence as the cost is not that onerous.
1273 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1274 obj_priv->tiling_mode != I915_TILING_NONE) {
1275 ret = i915_gem_object_get_fence_reg(obj);
1277 i915_gem_object_unpin(obj);
1286 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1287 struct drm_framebuffer *old_fb)
1289 struct drm_device *dev = crtc->dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 struct drm_i915_master_private *master_priv;
1292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1293 struct intel_framebuffer *intel_fb;
1294 struct drm_i915_gem_object *obj_priv;
1295 struct drm_gem_object *obj;
1296 int pipe = intel_crtc->pipe;
1297 int plane = intel_crtc->plane;
1298 unsigned long Start, Offset;
1299 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1300 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1301 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1302 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1303 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1309 DRM_DEBUG_KMS("No FB bound\n");
1318 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1322 intel_fb = to_intel_framebuffer(crtc->fb);
1323 obj = intel_fb->obj;
1324 obj_priv = to_intel_bo(obj);
1326 mutex_lock(&dev->struct_mutex);
1327 ret = intel_pin_and_fence_fb_obj(dev, obj);
1329 mutex_unlock(&dev->struct_mutex);
1333 ret = i915_gem_object_set_to_display_plane(obj);
1335 i915_gem_object_unpin(obj);
1336 mutex_unlock(&dev->struct_mutex);
1340 dspcntr = I915_READ(dspcntr_reg);
1341 /* Mask out pixel format bits in case we change it */
1342 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1343 switch (crtc->fb->bits_per_pixel) {
1345 dspcntr |= DISPPLANE_8BPP;
1348 if (crtc->fb->depth == 15)
1349 dspcntr |= DISPPLANE_15_16BPP;
1351 dspcntr |= DISPPLANE_16BPP;
1355 if (crtc->fb->depth == 30)
1356 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1358 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1361 DRM_ERROR("Unknown color depth\n");
1362 i915_gem_object_unpin(obj);
1363 mutex_unlock(&dev->struct_mutex);
1366 if (IS_I965G(dev)) {
1367 if (obj_priv->tiling_mode != I915_TILING_NONE)
1368 dspcntr |= DISPPLANE_TILED;
1370 dspcntr &= ~DISPPLANE_TILED;
1373 if (HAS_PCH_SPLIT(dev))
1375 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1377 I915_WRITE(dspcntr_reg, dspcntr);
1379 Start = obj_priv->gtt_offset;
1380 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1382 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1383 I915_WRITE(dspstride, crtc->fb->pitch);
1384 if (IS_I965G(dev)) {
1385 I915_WRITE(dspbase, Offset);
1387 I915_WRITE(dspsurf, Start);
1389 I915_WRITE(dsptileoff, (y << 16) | x);
1391 I915_WRITE(dspbase, Start + Offset);
1395 if ((IS_I965G(dev) || plane == 0))
1396 intel_update_fbc(crtc, &crtc->mode);
1398 intel_wait_for_vblank(dev);
1401 intel_fb = to_intel_framebuffer(old_fb);
1402 obj_priv = to_intel_bo(intel_fb->obj);
1403 i915_gem_object_unpin(intel_fb->obj);
1405 intel_increase_pllclock(crtc, true);
1407 mutex_unlock(&dev->struct_mutex);
1409 if (!dev->primary->master)
1412 master_priv = dev->primary->master->driver_priv;
1413 if (!master_priv->sarea_priv)
1417 master_priv->sarea_priv->pipeB_x = x;
1418 master_priv->sarea_priv->pipeB_y = y;
1420 master_priv->sarea_priv->pipeA_x = x;
1421 master_priv->sarea_priv->pipeA_y = y;
1427 /* Disable the VGA plane that we never use */
1428 static void i915_disable_vga (struct drm_device *dev)
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1434 if (HAS_PCH_SPLIT(dev))
1435 vga_reg = CPU_VGACNTRL;
1439 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1442 I915_WRITE8(VGA_SR_INDEX, 1);
1443 sr1 = I915_READ8(VGA_SR_DATA);
1444 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1447 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1450 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1452 struct drm_device *dev = crtc->dev;
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1456 DRM_DEBUG_KMS("\n");
1457 dpa_ctl = I915_READ(DP_A);
1458 dpa_ctl &= ~DP_PLL_ENABLE;
1459 I915_WRITE(DP_A, dpa_ctl);
1462 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1464 struct drm_device *dev = crtc->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1468 dpa_ctl = I915_READ(DP_A);
1469 dpa_ctl |= DP_PLL_ENABLE;
1470 I915_WRITE(DP_A, dpa_ctl);
1475 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1477 struct drm_device *dev = crtc->dev;
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1481 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1482 dpa_ctl = I915_READ(DP_A);
1483 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1485 if (clock < 200000) {
1487 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1488 /* workaround for 160Mhz:
1489 1) program 0x4600c bits 15:0 = 0x8124
1490 2) program 0x46010 bit 0 = 1
1491 3) program 0x46034 bit 24 = 1
1492 4) program 0x64000 bit 14 = 1
1494 temp = I915_READ(0x4600c);
1496 I915_WRITE(0x4600c, temp | 0x8124);
1498 temp = I915_READ(0x46010);
1499 I915_WRITE(0x46010, temp | 1);
1501 temp = I915_READ(0x46034);
1502 I915_WRITE(0x46034, temp | (1 << 24));
1504 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1506 I915_WRITE(DP_A, dpa_ctl);
1511 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1513 struct drm_device *dev = crtc->dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1516 int pipe = intel_crtc->pipe;
1517 int plane = intel_crtc->plane;
1518 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1519 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1520 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1521 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1522 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1523 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1524 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1525 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1526 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1527 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1528 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1529 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1530 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1531 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1532 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1533 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1534 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1535 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1536 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1537 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1538 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1539 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1540 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1541 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1543 int tries = 5, j, n;
1546 temp = I915_READ(pipeconf_reg);
1547 pipe_bpc = temp & PIPE_BPC_MASK;
1549 /* XXX: When our outputs are all unaware of DPMS modes other than off
1550 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1553 case DRM_MODE_DPMS_ON:
1554 case DRM_MODE_DPMS_STANDBY:
1555 case DRM_MODE_DPMS_SUSPEND:
1556 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1559 temp = I915_READ(PCH_LVDS);
1560 if ((temp & LVDS_PORT_EN) == 0) {
1561 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1562 POSTING_READ(PCH_LVDS);
1567 /* enable eDP PLL */
1568 ironlake_enable_pll_edp(crtc);
1570 /* enable PCH DPLL */
1571 temp = I915_READ(pch_dpll_reg);
1572 if ((temp & DPLL_VCO_ENABLE) == 0) {
1573 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1574 I915_READ(pch_dpll_reg);
1577 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1578 temp = I915_READ(fdi_rx_reg);
1580 * make the BPC in FDI Rx be consistent with that in
1583 temp &= ~(0x7 << 16);
1584 temp |= (pipe_bpc << 11);
1585 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1587 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1588 I915_READ(fdi_rx_reg);
1591 /* Enable CPU FDI TX PLL, always on for Ironlake */
1592 temp = I915_READ(fdi_tx_reg);
1593 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1594 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1595 I915_READ(fdi_tx_reg);
1600 /* Enable panel fitting for LVDS */
1601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1602 temp = I915_READ(pf_ctl_reg);
1603 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1605 /* currently full aspect */
1606 I915_WRITE(pf_win_pos, 0);
1608 I915_WRITE(pf_win_size,
1609 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1610 (dev_priv->panel_fixed_mode->vdisplay));
1613 /* Enable CPU pipe */
1614 temp = I915_READ(pipeconf_reg);
1615 if ((temp & PIPEACONF_ENABLE) == 0) {
1616 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1617 I915_READ(pipeconf_reg);
1621 /* configure and enable CPU plane */
1622 temp = I915_READ(dspcntr_reg);
1623 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1624 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1625 /* Flush the plane changes */
1626 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1630 /* enable CPU FDI TX and PCH FDI RX */
1631 temp = I915_READ(fdi_tx_reg);
1632 temp |= FDI_TX_ENABLE;
1633 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1634 temp &= ~FDI_LINK_TRAIN_NONE;
1635 temp |= FDI_LINK_TRAIN_PATTERN_1;
1636 I915_WRITE(fdi_tx_reg, temp);
1637 I915_READ(fdi_tx_reg);
1639 temp = I915_READ(fdi_rx_reg);
1640 temp &= ~FDI_LINK_TRAIN_NONE;
1641 temp |= FDI_LINK_TRAIN_PATTERN_1;
1642 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1643 I915_READ(fdi_rx_reg);
1648 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1650 temp = I915_READ(fdi_rx_imr_reg);
1651 temp &= ~FDI_RX_SYMBOL_LOCK;
1652 temp &= ~FDI_RX_BIT_LOCK;
1653 I915_WRITE(fdi_rx_imr_reg, temp);
1654 I915_READ(fdi_rx_imr_reg);
1657 temp = I915_READ(fdi_rx_iir_reg);
1658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1660 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1661 for (j = 0; j < tries; j++) {
1662 temp = I915_READ(fdi_rx_iir_reg);
1663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1665 if (temp & FDI_RX_BIT_LOCK)
1670 I915_WRITE(fdi_rx_iir_reg,
1671 temp | FDI_RX_BIT_LOCK);
1673 DRM_DEBUG_KMS("train 1 fail\n");
1675 I915_WRITE(fdi_rx_iir_reg,
1676 temp | FDI_RX_BIT_LOCK);
1677 DRM_DEBUG_KMS("train 1 ok 2!\n");
1679 temp = I915_READ(fdi_tx_reg);
1680 temp &= ~FDI_LINK_TRAIN_NONE;
1681 temp |= FDI_LINK_TRAIN_PATTERN_2;
1682 I915_WRITE(fdi_tx_reg, temp);
1684 temp = I915_READ(fdi_rx_reg);
1685 temp &= ~FDI_LINK_TRAIN_NONE;
1686 temp |= FDI_LINK_TRAIN_PATTERN_2;
1687 I915_WRITE(fdi_rx_reg, temp);
1691 temp = I915_READ(fdi_rx_iir_reg);
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1694 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1695 for (j = 0; j < tries; j++) {
1696 temp = I915_READ(fdi_rx_iir_reg);
1697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1699 if (temp & FDI_RX_SYMBOL_LOCK)
1704 I915_WRITE(fdi_rx_iir_reg,
1705 temp | FDI_RX_SYMBOL_LOCK);
1706 DRM_DEBUG_KMS("train 2 ok 1!\n");
1708 DRM_DEBUG_KMS("train 2 fail\n");
1710 I915_WRITE(fdi_rx_iir_reg,
1711 temp | FDI_RX_SYMBOL_LOCK);
1712 DRM_DEBUG_KMS("train 2 ok 2!\n");
1714 DRM_DEBUG_KMS("train done\n");
1716 /* set transcoder timing */
1717 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1718 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1719 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1721 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1722 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1723 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1725 /* enable PCH transcoder */
1726 temp = I915_READ(transconf_reg);
1728 * make the BPC in transcoder be consistent with
1729 * that in pipeconf reg.
1731 temp &= ~PIPE_BPC_MASK;
1733 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1734 I915_READ(transconf_reg);
1736 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1741 temp = I915_READ(fdi_tx_reg);
1742 temp &= ~FDI_LINK_TRAIN_NONE;
1743 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1744 FDI_TX_ENHANCE_FRAME_ENABLE);
1745 I915_READ(fdi_tx_reg);
1747 temp = I915_READ(fdi_rx_reg);
1748 temp &= ~FDI_LINK_TRAIN_NONE;
1749 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1750 FDI_RX_ENHANCE_FRAME_ENABLE);
1751 I915_READ(fdi_rx_reg);
1753 /* wait one idle pattern time */
1758 intel_crtc_load_lut(crtc);
1761 case DRM_MODE_DPMS_OFF:
1762 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1764 drm_vblank_off(dev, pipe);
1765 /* Disable display plane */
1766 temp = I915_READ(dspcntr_reg);
1767 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1768 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1769 /* Flush the plane changes */
1770 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1771 I915_READ(dspbase_reg);
1774 i915_disable_vga(dev);
1776 /* disable cpu pipe, disable after all planes disabled */
1777 temp = I915_READ(pipeconf_reg);
1778 if ((temp & PIPEACONF_ENABLE) != 0) {
1779 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1780 I915_READ(pipeconf_reg);
1782 /* wait for cpu pipe off, pipe state */
1783 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1789 DRM_DEBUG_KMS("pipe %d off delay\n",
1795 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1800 temp = I915_READ(pf_ctl_reg);
1801 if ((temp & PF_ENABLE) != 0) {
1802 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1803 I915_READ(pf_ctl_reg);
1805 I915_WRITE(pf_win_size, 0);
1807 /* disable CPU FDI tx and PCH FDI rx */
1808 temp = I915_READ(fdi_tx_reg);
1809 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1810 I915_READ(fdi_tx_reg);
1812 temp = I915_READ(fdi_rx_reg);
1813 /* BPC in FDI rx is consistent with that in pipeconf */
1814 temp &= ~(0x07 << 16);
1815 temp |= (pipe_bpc << 11);
1816 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1817 I915_READ(fdi_rx_reg);
1821 /* still set train pattern 1 */
1822 temp = I915_READ(fdi_tx_reg);
1823 temp &= ~FDI_LINK_TRAIN_NONE;
1824 temp |= FDI_LINK_TRAIN_PATTERN_1;
1825 I915_WRITE(fdi_tx_reg, temp);
1827 temp = I915_READ(fdi_rx_reg);
1828 temp &= ~FDI_LINK_TRAIN_NONE;
1829 temp |= FDI_LINK_TRAIN_PATTERN_1;
1830 I915_WRITE(fdi_rx_reg, temp);
1834 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1835 temp = I915_READ(PCH_LVDS);
1836 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1837 I915_READ(PCH_LVDS);
1841 /* disable PCH transcoder */
1842 temp = I915_READ(transconf_reg);
1843 if ((temp & TRANS_ENABLE) != 0) {
1844 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1845 I915_READ(transconf_reg);
1847 /* wait for PCH transcoder off, transcoder state */
1848 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1854 DRM_DEBUG_KMS("transcoder %d off "
1860 temp = I915_READ(transconf_reg);
1861 /* BPC in transcoder is consistent with that in pipeconf */
1862 temp &= ~PIPE_BPC_MASK;
1864 I915_WRITE(transconf_reg, temp);
1865 I915_READ(transconf_reg);
1868 /* disable PCH DPLL */
1869 temp = I915_READ(pch_dpll_reg);
1870 if ((temp & DPLL_VCO_ENABLE) != 0) {
1871 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1872 I915_READ(pch_dpll_reg);
1876 ironlake_disable_pll_edp(crtc);
1879 temp = I915_READ(fdi_rx_reg);
1880 temp &= ~FDI_SEL_PCDCLK;
1881 I915_WRITE(fdi_rx_reg, temp);
1882 I915_READ(fdi_rx_reg);
1884 temp = I915_READ(fdi_rx_reg);
1885 temp &= ~FDI_RX_PLL_ENABLE;
1886 I915_WRITE(fdi_rx_reg, temp);
1887 I915_READ(fdi_rx_reg);
1889 /* Disable CPU FDI TX PLL */
1890 temp = I915_READ(fdi_tx_reg);
1891 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1892 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1893 I915_READ(fdi_tx_reg);
1897 /* Wait for the clocks to turn off. */
1903 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1905 struct intel_overlay *overlay;
1908 if (!enable && intel_crtc->overlay) {
1909 overlay = intel_crtc->overlay;
1910 mutex_lock(&overlay->dev->struct_mutex);
1912 ret = intel_overlay_switch_off(overlay);
1916 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1918 /* overlay doesn't react anymore. Usually
1919 * results in a black screen and an unkillable
1922 overlay->hw_wedged = HW_WEDGED;
1926 mutex_unlock(&overlay->dev->struct_mutex);
1928 /* Let userspace switch the overlay on again. In most cases userspace
1929 * has to recompute where to put it anyway. */
1934 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1936 struct drm_device *dev = crtc->dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1939 int pipe = intel_crtc->pipe;
1940 int plane = intel_crtc->plane;
1941 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1942 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1943 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1944 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1947 /* XXX: When our outputs are all unaware of DPMS modes other than off
1948 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1951 case DRM_MODE_DPMS_ON:
1952 case DRM_MODE_DPMS_STANDBY:
1953 case DRM_MODE_DPMS_SUSPEND:
1954 intel_update_watermarks(dev);
1956 /* Enable the DPLL */
1957 temp = I915_READ(dpll_reg);
1958 if ((temp & DPLL_VCO_ENABLE) == 0) {
1959 I915_WRITE(dpll_reg, temp);
1960 I915_READ(dpll_reg);
1961 /* Wait for the clocks to stabilize. */
1963 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1964 I915_READ(dpll_reg);
1965 /* Wait for the clocks to stabilize. */
1967 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1968 I915_READ(dpll_reg);
1969 /* Wait for the clocks to stabilize. */
1973 /* Enable the pipe */
1974 temp = I915_READ(pipeconf_reg);
1975 if ((temp & PIPEACONF_ENABLE) == 0)
1976 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1978 /* Enable the plane */
1979 temp = I915_READ(dspcntr_reg);
1980 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1981 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1982 /* Flush the plane changes */
1983 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1986 intel_crtc_load_lut(crtc);
1988 if ((IS_I965G(dev) || plane == 0))
1989 intel_update_fbc(crtc, &crtc->mode);
1991 /* Give the overlay scaler a chance to enable if it's on this pipe */
1992 intel_crtc_dpms_overlay(intel_crtc, true);
1994 case DRM_MODE_DPMS_OFF:
1995 intel_update_watermarks(dev);
1997 /* Give the overlay scaler a chance to disable if it's on this pipe */
1998 intel_crtc_dpms_overlay(intel_crtc, false);
1999 drm_vblank_off(dev, pipe);
2001 if (dev_priv->cfb_plane == plane &&
2002 dev_priv->display.disable_fbc)
2003 dev_priv->display.disable_fbc(dev);
2005 /* Disable the VGA plane that we never use */
2006 i915_disable_vga(dev);
2008 /* Disable display plane */
2009 temp = I915_READ(dspcntr_reg);
2010 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2011 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2012 /* Flush the plane changes */
2013 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2014 I915_READ(dspbase_reg);
2017 if (!IS_I9XX(dev)) {
2018 /* Wait for vblank for the disable to take effect */
2019 intel_wait_for_vblank(dev);
2022 /* Next, disable display pipes */
2023 temp = I915_READ(pipeconf_reg);
2024 if ((temp & PIPEACONF_ENABLE) != 0) {
2025 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2026 I915_READ(pipeconf_reg);
2029 /* Wait for vblank for the disable to take effect. */
2030 intel_wait_for_vblank(dev);
2032 temp = I915_READ(dpll_reg);
2033 if ((temp & DPLL_VCO_ENABLE) != 0) {
2034 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2035 I915_READ(dpll_reg);
2038 /* Wait for the clocks to turn off. */
2045 * Sets the power management mode of the pipe and plane.
2047 * This code should probably grow support for turning the cursor off and back
2048 * on appropriately at the same time as we're turning the pipe off/on.
2050 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2052 struct drm_device *dev = crtc->dev;
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 struct drm_i915_master_private *master_priv;
2055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056 int pipe = intel_crtc->pipe;
2059 dev_priv->display.dpms(crtc, mode);
2061 intel_crtc->dpms_mode = mode;
2063 if (!dev->primary->master)
2066 master_priv = dev->primary->master->driver_priv;
2067 if (!master_priv->sarea_priv)
2070 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2074 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2075 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2078 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2079 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2082 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2087 static void intel_crtc_prepare (struct drm_crtc *crtc)
2089 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2090 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2093 static void intel_crtc_commit (struct drm_crtc *crtc)
2095 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2096 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2099 void intel_encoder_prepare (struct drm_encoder *encoder)
2101 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2102 /* lvds has its own version of prepare see intel_lvds_prepare */
2103 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2106 void intel_encoder_commit (struct drm_encoder *encoder)
2108 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2109 /* lvds has its own version of commit see intel_lvds_commit */
2110 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2113 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2114 struct drm_display_mode *mode,
2115 struct drm_display_mode *adjusted_mode)
2117 struct drm_device *dev = crtc->dev;
2118 if (HAS_PCH_SPLIT(dev)) {
2119 /* FDI link clock is fixed at 2.7G */
2120 if (mode->clock * 3 > 27000 * 4)
2121 return MODE_CLOCK_HIGH;
2126 static int i945_get_display_clock_speed(struct drm_device *dev)
2131 static int i915_get_display_clock_speed(struct drm_device *dev)
2136 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2141 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2145 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2147 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2150 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2151 case GC_DISPLAY_CLOCK_333_MHZ:
2154 case GC_DISPLAY_CLOCK_190_200_MHZ:
2160 static int i865_get_display_clock_speed(struct drm_device *dev)
2165 static int i855_get_display_clock_speed(struct drm_device *dev)
2168 /* Assume that the hardware is in the high speed state. This
2169 * should be the default.
2171 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2172 case GC_CLOCK_133_200:
2173 case GC_CLOCK_100_200:
2175 case GC_CLOCK_166_250:
2177 case GC_CLOCK_100_133:
2181 /* Shouldn't happen */
2185 static int i830_get_display_clock_speed(struct drm_device *dev)
2191 * Return the pipe currently connected to the panel fitter,
2192 * or -1 if the panel fitter is not present or not in use
2194 int intel_panel_fitter_pipe (struct drm_device *dev)
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2199 /* i830 doesn't have a panel fitter */
2203 pfit_control = I915_READ(PFIT_CONTROL);
2205 /* See if the panel fitter is in use */
2206 if ((pfit_control & PFIT_ENABLE) == 0)
2209 /* 965 can place panel fitter on either pipe */
2211 return (pfit_control >> 29) & 0x3;
2213 /* older chips can only use pipe 1 */
2226 fdi_reduce_ratio(u32 *num, u32 *den)
2228 while (*num > 0xffffff || *den > 0xffffff) {
2234 #define DATA_N 0x800000
2235 #define LINK_N 0x80000
2238 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2239 int link_clock, struct fdi_m_n *m_n)
2243 m_n->tu = 64; /* default size */
2245 temp = (u64) DATA_N * pixel_clock;
2246 temp = div_u64(temp, link_clock);
2247 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2248 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2249 m_n->gmch_n = DATA_N;
2250 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2252 temp = (u64) LINK_N * pixel_clock;
2253 m_n->link_m = div_u64(temp, link_clock);
2254 m_n->link_n = LINK_N;
2255 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2259 struct intel_watermark_params {
2260 unsigned long fifo_size;
2261 unsigned long max_wm;
2262 unsigned long default_wm;
2263 unsigned long guard_size;
2264 unsigned long cacheline_size;
2267 /* Pineview has different values for various configs */
2268 static struct intel_watermark_params pineview_display_wm = {
2269 PINEVIEW_DISPLAY_FIFO,
2273 PINEVIEW_FIFO_LINE_SIZE
2275 static struct intel_watermark_params pineview_display_hplloff_wm = {
2276 PINEVIEW_DISPLAY_FIFO,
2278 PINEVIEW_DFT_HPLLOFF_WM,
2280 PINEVIEW_FIFO_LINE_SIZE
2282 static struct intel_watermark_params pineview_cursor_wm = {
2283 PINEVIEW_CURSOR_FIFO,
2284 PINEVIEW_CURSOR_MAX_WM,
2285 PINEVIEW_CURSOR_DFT_WM,
2286 PINEVIEW_CURSOR_GUARD_WM,
2287 PINEVIEW_FIFO_LINE_SIZE,
2289 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2290 PINEVIEW_CURSOR_FIFO,
2291 PINEVIEW_CURSOR_MAX_WM,
2292 PINEVIEW_CURSOR_DFT_WM,
2293 PINEVIEW_CURSOR_GUARD_WM,
2294 PINEVIEW_FIFO_LINE_SIZE
2296 static struct intel_watermark_params g4x_wm_info = {
2303 static struct intel_watermark_params i945_wm_info = {
2310 static struct intel_watermark_params i915_wm_info = {
2317 static struct intel_watermark_params i855_wm_info = {
2324 static struct intel_watermark_params i830_wm_info = {
2333 * intel_calculate_wm - calculate watermark level
2334 * @clock_in_khz: pixel clock
2335 * @wm: chip FIFO params
2336 * @pixel_size: display pixel size
2337 * @latency_ns: memory latency for the platform
2339 * Calculate the watermark level (the level at which the display plane will
2340 * start fetching from memory again). Each chip has a different display
2341 * FIFO size and allocation, so the caller needs to figure that out and pass
2342 * in the correct intel_watermark_params structure.
2344 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2345 * on the pixel size. When it reaches the watermark level, it'll start
2346 * fetching FIFO line sized based chunks from memory until the FIFO fills
2347 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2348 * will occur, and a display engine hang could result.
2350 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2351 struct intel_watermark_params *wm,
2353 unsigned long latency_ns)
2355 long entries_required, wm_size;
2358 * Note: we need to make sure we don't overflow for various clock &
2360 * clocks go from a few thousand to several hundred thousand.
2361 * latency is usually a few thousand
2363 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2365 entries_required /= wm->cacheline_size;
2367 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2369 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2371 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2373 /* Don't promote wm_size to unsigned... */
2374 if (wm_size > (long)wm->max_wm)
2375 wm_size = wm->max_wm;
2377 wm_size = wm->default_wm;
2381 struct cxsr_latency {
2383 unsigned long fsb_freq;
2384 unsigned long mem_freq;
2385 unsigned long display_sr;
2386 unsigned long display_hpll_disable;
2387 unsigned long cursor_sr;
2388 unsigned long cursor_hpll_disable;
2391 static struct cxsr_latency cxsr_latency_table[] = {
2392 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2393 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2394 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2396 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2397 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2398 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2400 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2401 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2402 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2404 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2405 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2406 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2408 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2409 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2410 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2412 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2413 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2414 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2417 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2421 struct cxsr_latency *latency;
2423 if (fsb == 0 || mem == 0)
2426 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2427 latency = &cxsr_latency_table[i];
2428 if (is_desktop == latency->is_desktop &&
2429 fsb == latency->fsb_freq && mem == latency->mem_freq)
2433 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2438 static void pineview_disable_cxsr(struct drm_device *dev)
2440 struct drm_i915_private *dev_priv = dev->dev_private;
2443 /* deactivate cxsr */
2444 reg = I915_READ(DSPFW3);
2445 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2446 I915_WRITE(DSPFW3, reg);
2447 DRM_INFO("Big FIFO is disabled\n");
2450 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct cxsr_latency *latency;
2458 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2459 dev_priv->mem_freq);
2461 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2462 pineview_disable_cxsr(dev);
2467 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2468 latency->display_sr);
2469 reg = I915_READ(DSPFW1);
2472 I915_WRITE(DSPFW1, reg);
2473 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2476 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2477 latency->cursor_sr);
2478 reg = I915_READ(DSPFW3);
2479 reg &= ~(0x3f << 24);
2480 reg |= (wm & 0x3f) << 24;
2481 I915_WRITE(DSPFW3, reg);
2483 /* Display HPLL off SR */
2484 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2485 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2486 reg = I915_READ(DSPFW3);
2489 I915_WRITE(DSPFW3, reg);
2491 /* cursor HPLL off SR */
2492 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2493 latency->cursor_hpll_disable);
2494 reg = I915_READ(DSPFW3);
2495 reg &= ~(0x3f << 16);
2496 reg |= (wm & 0x3f) << 16;
2497 I915_WRITE(DSPFW3, reg);
2498 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2501 reg = I915_READ(DSPFW3);
2502 reg |= PINEVIEW_SELF_REFRESH_EN;
2503 I915_WRITE(DSPFW3, reg);
2505 DRM_INFO("Big FIFO is enabled\n");
2511 * Latency for FIFO fetches is dependent on several factors:
2512 * - memory configuration (speed, channels)
2514 * - current MCH state
2515 * It can be fairly high in some situations, so here we assume a fairly
2516 * pessimal value. It's a tradeoff between extra memory fetches (if we
2517 * set this value too high, the FIFO will fetch frequently to stay full)
2518 * and power consumption (set it too low to save power and we might see
2519 * FIFO underruns and display "flicker").
2521 * A value of 5us seems to be a good balance; safe for very low end
2522 * platforms but not overly aggressive on lower latency configs.
2524 static const int latency_ns = 5000;
2526 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 uint32_t dsparb = I915_READ(DSPARB);
2533 size = dsparb & 0x7f;
2535 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2538 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2539 plane ? "B" : "A", size);
2544 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 uint32_t dsparb = I915_READ(DSPARB);
2551 size = dsparb & 0x1ff;
2553 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2555 size >>= 1; /* Convert to cachelines */
2557 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2558 plane ? "B" : "A", size);
2563 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 uint32_t dsparb = I915_READ(DSPARB);
2569 size = dsparb & 0x7f;
2570 size >>= 2; /* Convert to cachelines */
2572 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2579 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2582 uint32_t dsparb = I915_READ(DSPARB);
2585 size = dsparb & 0x7f;
2586 size >>= 1; /* Convert to cachelines */
2588 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2589 plane ? "B" : "A", size);
2594 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2595 int planeb_clock, int sr_hdisplay, int pixel_size)
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 int total_size, cacheline_size;
2599 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2600 struct intel_watermark_params planea_params, planeb_params;
2601 unsigned long line_time_us;
2602 int sr_clock, sr_entries = 0, entries_required;
2604 /* Create copies of the base settings for each pipe */
2605 planea_params = planeb_params = g4x_wm_info;
2607 /* Grab a couple of global values before we overwrite them */
2608 total_size = planea_params.fifo_size;
2609 cacheline_size = planea_params.cacheline_size;
2612 * Note: we need to make sure we don't overflow for various clock &
2614 * clocks go from a few thousand to several hundred thousand.
2615 * latency is usually a few thousand
2617 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2619 entries_required /= G4X_FIFO_LINE_SIZE;
2620 planea_wm = entries_required + planea_params.guard_size;
2622 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2624 entries_required /= G4X_FIFO_LINE_SIZE;
2625 planeb_wm = entries_required + planeb_params.guard_size;
2627 cursora_wm = cursorb_wm = 16;
2630 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2632 /* Calc sr entries for one plane configs */
2633 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2634 /* self-refresh has much higher latency */
2635 static const int sr_latency_ns = 12000;
2637 sr_clock = planea_clock ? planea_clock : planeb_clock;
2638 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2640 /* Use ns/us then divide to preserve precision */
2641 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2642 pixel_size * sr_hdisplay) / 1000;
2643 sr_entries = roundup(sr_entries / cacheline_size, 1);
2644 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2645 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2647 /* Turn off self refresh if both pipes are enabled */
2648 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2652 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2653 planea_wm, planeb_wm, sr_entries);
2658 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2659 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2660 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2661 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2662 (cursora_wm << DSPFW_CURSORA_SHIFT));
2663 /* HPLL off in SR has some issues on G4x... disable it */
2664 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2665 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2668 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2669 int planeb_clock, int sr_hdisplay, int pixel_size)
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 unsigned long line_time_us;
2673 int sr_clock, sr_entries, srwm = 1;
2675 /* Calc sr entries for one plane configs */
2676 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2677 /* self-refresh has much higher latency */
2678 static const int sr_latency_ns = 12000;
2680 sr_clock = planea_clock ? planea_clock : planeb_clock;
2681 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2683 /* Use ns/us then divide to preserve precision */
2684 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2685 pixel_size * sr_hdisplay) / 1000;
2686 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2687 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2688 srwm = I945_FIFO_SIZE - sr_entries;
2692 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2694 /* Turn off self refresh if both pipes are enabled */
2695 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2699 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2702 /* 965 has limitations... */
2703 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2705 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2708 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2709 int planeb_clock, int sr_hdisplay, int pixel_size)
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2714 int total_size, cacheline_size, cwm, srwm = 1;
2715 int planea_wm, planeb_wm;
2716 struct intel_watermark_params planea_params, planeb_params;
2717 unsigned long line_time_us;
2718 int sr_clock, sr_entries = 0;
2720 /* Create copies of the base settings for each pipe */
2721 if (IS_I965GM(dev) || IS_I945GM(dev))
2722 planea_params = planeb_params = i945_wm_info;
2723 else if (IS_I9XX(dev))
2724 planea_params = planeb_params = i915_wm_info;
2726 planea_params = planeb_params = i855_wm_info;
2728 /* Grab a couple of global values before we overwrite them */
2729 total_size = planea_params.fifo_size;
2730 cacheline_size = planea_params.cacheline_size;
2732 /* Update per-plane FIFO sizes */
2733 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2734 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2736 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2737 pixel_size, latency_ns);
2738 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2739 pixel_size, latency_ns);
2740 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2743 * Overlay gets an aggressive default since video jitter is bad.
2747 /* Calc sr entries for one plane configs */
2748 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2749 (!planea_clock || !planeb_clock)) {
2750 /* self-refresh has much higher latency */
2751 static const int sr_latency_ns = 6000;
2753 sr_clock = planea_clock ? planea_clock : planeb_clock;
2754 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2756 /* Use ns/us then divide to preserve precision */
2757 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2758 pixel_size * sr_hdisplay) / 1000;
2759 sr_entries = roundup(sr_entries / cacheline_size, 1);
2760 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2761 srwm = total_size - sr_entries;
2765 if (IS_I945G(dev) || IS_I945GM(dev))
2766 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2767 else if (IS_I915GM(dev)) {
2768 /* 915M has a smaller SRWM field */
2769 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2770 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2773 /* Turn off self refresh if both pipes are enabled */
2774 if (IS_I945G(dev) || IS_I945GM(dev)) {
2775 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2777 } else if (IS_I915GM(dev)) {
2778 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2782 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2783 planea_wm, planeb_wm, cwm, srwm);
2785 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2786 fwater_hi = (cwm & 0x1f);
2788 /* Set request length to 8 cachelines per fetch */
2789 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2790 fwater_hi = fwater_hi | (1 << 8);
2792 I915_WRITE(FW_BLC, fwater_lo);
2793 I915_WRITE(FW_BLC2, fwater_hi);
2796 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2797 int unused2, int pixel_size)
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2803 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2805 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2806 pixel_size, latency_ns);
2807 fwater_lo |= (3<<8) | planea_wm;
2809 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2811 I915_WRITE(FW_BLC, fwater_lo);
2815 * intel_update_watermarks - update FIFO watermark values based on current modes
2817 * Calculate watermark values for the various WM regs based on current mode
2818 * and plane configuration.
2820 * There are several cases to deal with here:
2821 * - normal (i.e. non-self-refresh)
2822 * - self-refresh (SR) mode
2823 * - lines are large relative to FIFO size (buffer can hold up to 2)
2824 * - lines are small relative to FIFO size (buffer can hold more than 2
2825 * lines), so need to account for TLB latency
2827 * The normal calculation is:
2828 * watermark = dotclock * bytes per pixel * latency
2829 * where latency is platform & configuration dependent (we assume pessimal
2832 * The SR calculation is:
2833 * watermark = (trunc(latency/line time)+1) * surface width *
2836 * line time = htotal / dotclock
2837 * and latency is assumed to be high, as above.
2839 * The final value programmed to the register should always be rounded up,
2840 * and include an extra 2 entries to account for clock crossings.
2842 * We don't use the sprite, so we can ignore that. And on Crestline we have
2843 * to set the non-SR watermarks to 8.
2845 static void intel_update_watermarks(struct drm_device *dev)
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 struct drm_crtc *crtc;
2849 struct intel_crtc *intel_crtc;
2850 int sr_hdisplay = 0;
2851 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2852 int enabled = 0, pixel_size = 0;
2854 if (!dev_priv->display.update_wm)
2857 /* Get the clock config from both planes */
2858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2859 intel_crtc = to_intel_crtc(crtc);
2860 if (crtc->enabled) {
2862 if (intel_crtc->plane == 0) {
2863 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2864 intel_crtc->pipe, crtc->mode.clock);
2865 planea_clock = crtc->mode.clock;
2867 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2868 intel_crtc->pipe, crtc->mode.clock);
2869 planeb_clock = crtc->mode.clock;
2871 sr_hdisplay = crtc->mode.hdisplay;
2872 sr_clock = crtc->mode.clock;
2874 pixel_size = crtc->fb->bits_per_pixel / 8;
2876 pixel_size = 4; /* by default */
2883 /* Single plane configs can enable self refresh */
2884 if (enabled == 1 && IS_PINEVIEW(dev))
2885 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2886 else if (IS_PINEVIEW(dev))
2887 pineview_disable_cxsr(dev);
2889 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2890 sr_hdisplay, pixel_size);
2893 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2894 struct drm_display_mode *mode,
2895 struct drm_display_mode *adjusted_mode,
2897 struct drm_framebuffer *old_fb)
2899 struct drm_device *dev = crtc->dev;
2900 struct drm_i915_private *dev_priv = dev->dev_private;
2901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2902 int pipe = intel_crtc->pipe;
2903 int plane = intel_crtc->plane;
2904 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2905 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2906 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2907 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2908 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2909 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2910 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2911 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2912 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2913 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2914 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2915 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2916 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2917 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2918 int refclk, num_connectors = 0;
2919 intel_clock_t clock, reduced_clock;
2920 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2921 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2922 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2923 bool is_edp = false;
2924 struct drm_mode_config *mode_config = &dev->mode_config;
2925 struct drm_encoder *encoder;
2926 struct intel_encoder *intel_encoder;
2927 const intel_limit_t *limit;
2929 struct fdi_m_n m_n = {0};
2930 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2931 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2932 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2933 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2934 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2935 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2936 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2937 int lvds_reg = LVDS;
2939 int sdvo_pixel_multiply;
2942 drm_vblank_pre_modeset(dev, pipe);
2944 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2946 if (!encoder || encoder->crtc != crtc)
2949 intel_encoder = enc_to_intel_encoder(encoder);
2951 switch (intel_encoder->type) {
2952 case INTEL_OUTPUT_LVDS:
2955 case INTEL_OUTPUT_SDVO:
2956 case INTEL_OUTPUT_HDMI:
2958 if (intel_encoder->needs_tv_clock)
2961 case INTEL_OUTPUT_DVO:
2964 case INTEL_OUTPUT_TVOUT:
2967 case INTEL_OUTPUT_ANALOG:
2970 case INTEL_OUTPUT_DISPLAYPORT:
2973 case INTEL_OUTPUT_EDP:
2981 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
2982 refclk = dev_priv->lvds_ssc_freq * 1000;
2983 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2985 } else if (IS_I9XX(dev)) {
2987 if (HAS_PCH_SPLIT(dev))
2988 refclk = 120000; /* 120Mhz refclk */
2995 * Returns a set of divisors for the desired target clock with the given
2996 * refclk, or FALSE. The returned values represent the clock equation:
2997 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2999 limit = intel_limit(crtc);
3000 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3002 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3003 drm_vblank_post_modeset(dev, pipe);
3007 if (is_lvds && dev_priv->lvds_downclock_avail) {
3008 has_reduced_clock = limit->find_pll(limit, crtc,
3009 dev_priv->lvds_downclock,
3012 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3014 * If the different P is found, it means that we can't
3015 * switch the display clock by using the FP0/FP1.
3016 * In such case we will disable the LVDS downclock
3019 DRM_DEBUG_KMS("Different P is found for "
3020 "LVDS clock/downclock\n");
3021 has_reduced_clock = 0;
3024 /* SDVO TV has fixed PLL values depend on its clock range,
3025 this mirrors vbios setting. */
3026 if (is_sdvo && is_tv) {
3027 if (adjusted_mode->clock >= 100000
3028 && adjusted_mode->clock < 140500) {
3034 } else if (adjusted_mode->clock >= 140500
3035 && adjusted_mode->clock <= 200000) {
3045 if (HAS_PCH_SPLIT(dev)) {
3046 int lane, link_bw, bpp;
3047 /* eDP doesn't require FDI link, so just set DP M/N
3048 according to current link config */
3050 struct drm_connector *edp;
3051 target_clock = mode->clock;
3052 edp = intel_pipe_get_connector(crtc);
3053 intel_edp_link_config(to_intel_encoder(edp),
3056 /* DP over FDI requires target mode clock
3057 instead of link clock */
3059 target_clock = mode->clock;
3061 target_clock = adjusted_mode->clock;
3066 /* determine panel color depth */
3067 temp = I915_READ(pipeconf_reg);
3068 temp &= ~PIPE_BPC_MASK;
3070 int lvds_reg = I915_READ(PCH_LVDS);
3071 /* the BPC will be 6 if it is 18-bit LVDS panel */
3072 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3076 } else if (is_edp) {
3077 switch (dev_priv->edp_bpp/3) {
3093 I915_WRITE(pipeconf_reg, temp);
3094 I915_READ(pipeconf_reg);
3096 switch (temp & PIPE_BPC_MASK) {
3110 DRM_ERROR("unknown pipe bpc value\n");
3114 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3117 /* Ironlake: try to setup display ref clock before DPLL
3118 * enabling. This is only under driver's control after
3119 * PCH B stepping, previous chipset stepping should be
3120 * ignoring this setting.
3122 if (HAS_PCH_SPLIT(dev)) {
3123 temp = I915_READ(PCH_DREF_CONTROL);
3124 /* Always enable nonspread source */
3125 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3126 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3127 I915_WRITE(PCH_DREF_CONTROL, temp);
3128 POSTING_READ(PCH_DREF_CONTROL);
3130 temp &= ~DREF_SSC_SOURCE_MASK;
3131 temp |= DREF_SSC_SOURCE_ENABLE;
3132 I915_WRITE(PCH_DREF_CONTROL, temp);
3133 POSTING_READ(PCH_DREF_CONTROL);
3138 if (dev_priv->lvds_use_ssc) {
3139 temp |= DREF_SSC1_ENABLE;
3140 I915_WRITE(PCH_DREF_CONTROL, temp);
3141 POSTING_READ(PCH_DREF_CONTROL);
3145 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3146 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3147 I915_WRITE(PCH_DREF_CONTROL, temp);
3148 POSTING_READ(PCH_DREF_CONTROL);
3150 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3151 I915_WRITE(PCH_DREF_CONTROL, temp);
3152 POSTING_READ(PCH_DREF_CONTROL);
3157 if (IS_PINEVIEW(dev)) {
3158 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3159 if (has_reduced_clock)
3160 fp2 = (1 << reduced_clock.n) << 16 |
3161 reduced_clock.m1 << 8 | reduced_clock.m2;
3163 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3164 if (has_reduced_clock)
3165 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3169 if (!HAS_PCH_SPLIT(dev))
3170 dpll = DPLL_VGA_MODE_DIS;
3174 dpll |= DPLLB_MODE_LVDS;
3176 dpll |= DPLLB_MODE_DAC_SERIAL;
3178 dpll |= DPLL_DVO_HIGH_SPEED;
3179 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3180 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3181 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3182 else if (HAS_PCH_SPLIT(dev))
3183 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3186 dpll |= DPLL_DVO_HIGH_SPEED;
3188 /* compute bitmask from p1 value */
3189 if (IS_PINEVIEW(dev))
3190 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3192 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3194 if (HAS_PCH_SPLIT(dev))
3195 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3196 if (IS_G4X(dev) && has_reduced_clock)
3197 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3207 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3210 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3213 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3214 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3217 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3220 dpll |= PLL_P1_DIVIDE_BY_TWO;
3222 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3224 dpll |= PLL_P2_DIVIDE_BY_4;
3228 if (is_sdvo && is_tv)
3229 dpll |= PLL_REF_INPUT_TVCLKINBC;
3231 /* XXX: just matching BIOS for now */
3232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3234 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3235 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3237 dpll |= PLL_REF_INPUT_DREFCLK;
3239 /* setup pipeconf */
3240 pipeconf = I915_READ(pipeconf_reg);
3242 /* Set up the display plane register */
3243 dspcntr = DISPPLANE_GAMMA_ENABLE;
3245 /* Ironlake's plane is forced to pipe, bit 24 is to
3246 enable color space conversion */
3247 if (!HAS_PCH_SPLIT(dev)) {
3249 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3251 dspcntr |= DISPPLANE_SEL_PIPE_B;
3254 if (pipe == 0 && !IS_I965G(dev)) {
3255 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3258 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3262 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3263 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3265 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3268 dspcntr |= DISPLAY_PLANE_ENABLE;
3269 pipeconf |= PIPEACONF_ENABLE;
3270 dpll |= DPLL_VCO_ENABLE;
3273 /* Disable the panel fitter if it was on our pipe */
3274 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3275 I915_WRITE(PFIT_CONTROL, 0);
3277 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3278 drm_mode_debug_printmodeline(mode);
3280 /* assign to Ironlake registers */
3281 if (HAS_PCH_SPLIT(dev)) {
3282 fp_reg = pch_fp_reg;
3283 dpll_reg = pch_dpll_reg;
3287 ironlake_disable_pll_edp(crtc);
3288 } else if ((dpll & DPLL_VCO_ENABLE)) {
3289 I915_WRITE(fp_reg, fp);
3290 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3291 I915_READ(dpll_reg);
3295 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3296 * This is an exception to the general rule that mode_set doesn't turn
3302 if (HAS_PCH_SPLIT(dev))
3303 lvds_reg = PCH_LVDS;
3305 lvds = I915_READ(lvds_reg);
3306 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3307 /* set the corresponsding LVDS_BORDER bit */
3308 lvds |= dev_priv->lvds_border_bits;
3309 /* Set the B0-B3 data pairs corresponding to whether we're going to
3310 * set the DPLLs for dual-channel mode or not.
3313 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3315 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3317 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3318 * appropriately here, but we need to look more thoroughly into how
3319 * panels behave in the two modes.
3321 /* set the dithering flag */
3322 if (IS_I965G(dev)) {
3323 if (dev_priv->lvds_dither) {
3324 if (HAS_PCH_SPLIT(dev))
3325 pipeconf |= PIPE_ENABLE_DITHER;
3327 lvds |= LVDS_ENABLE_DITHER;
3329 if (HAS_PCH_SPLIT(dev))
3330 pipeconf &= ~PIPE_ENABLE_DITHER;
3332 lvds &= ~LVDS_ENABLE_DITHER;
3335 I915_WRITE(lvds_reg, lvds);
3336 I915_READ(lvds_reg);
3339 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3342 I915_WRITE(fp_reg, fp);
3343 I915_WRITE(dpll_reg, dpll);
3344 I915_READ(dpll_reg);
3345 /* Wait for the clocks to stabilize. */
3348 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3350 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3351 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3352 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3354 I915_WRITE(dpll_md_reg, 0);
3356 /* write it again -- the BIOS does, after all */
3357 I915_WRITE(dpll_reg, dpll);
3359 I915_READ(dpll_reg);
3360 /* Wait for the clocks to stabilize. */
3364 if (is_lvds && has_reduced_clock && i915_powersave) {
3365 I915_WRITE(fp_reg + 4, fp2);
3366 intel_crtc->lowfreq_avail = true;
3367 if (HAS_PIPE_CXSR(dev)) {
3368 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3369 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3372 I915_WRITE(fp_reg + 4, fp);
3373 intel_crtc->lowfreq_avail = false;
3374 if (HAS_PIPE_CXSR(dev)) {
3375 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3376 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3380 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3381 ((adjusted_mode->crtc_htotal - 1) << 16));
3382 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3383 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3384 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3385 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3386 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3387 ((adjusted_mode->crtc_vtotal - 1) << 16));
3388 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3389 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3390 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3391 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3392 /* pipesrc and dspsize control the size that is scaled from, which should
3393 * always be the user's requested size.
3395 if (!HAS_PCH_SPLIT(dev)) {
3396 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3397 (mode->hdisplay - 1));
3398 I915_WRITE(dsppos_reg, 0);
3400 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3402 if (HAS_PCH_SPLIT(dev)) {
3403 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3404 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3405 I915_WRITE(link_m1_reg, m_n.link_m);
3406 I915_WRITE(link_n1_reg, m_n.link_n);
3409 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3411 /* enable FDI RX PLL too */
3412 temp = I915_READ(fdi_rx_reg);
3413 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3418 I915_WRITE(pipeconf_reg, pipeconf);
3419 I915_READ(pipeconf_reg);
3421 intel_wait_for_vblank(dev);
3423 if (IS_IRONLAKE(dev)) {
3424 /* enable address swizzle for tiling buffer */
3425 temp = I915_READ(DISP_ARB_CTL);
3426 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3429 I915_WRITE(dspcntr_reg, dspcntr);
3431 /* Flush the plane changes */
3432 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3434 if ((IS_I965G(dev) || plane == 0))
3435 intel_update_fbc(crtc, &crtc->mode);
3437 intel_update_watermarks(dev);
3439 drm_vblank_post_modeset(dev, pipe);
3444 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3445 void intel_crtc_load_lut(struct drm_crtc *crtc)
3447 struct drm_device *dev = crtc->dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3453 /* The clocks have to be on to load the palette. */
3457 /* use legacy palette for Ironlake */
3458 if (HAS_PCH_SPLIT(dev))
3459 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3462 for (i = 0; i < 256; i++) {
3463 I915_WRITE(palreg + 4 * i,
3464 (intel_crtc->lut_r[i] << 16) |
3465 (intel_crtc->lut_g[i] << 8) |
3466 intel_crtc->lut_b[i]);
3470 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3471 struct drm_file *file_priv,
3473 uint32_t width, uint32_t height)
3475 struct drm_device *dev = crtc->dev;
3476 struct drm_i915_private *dev_priv = dev->dev_private;
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 struct drm_gem_object *bo;
3479 struct drm_i915_gem_object *obj_priv;
3480 int pipe = intel_crtc->pipe;
3481 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3482 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3483 uint32_t temp = I915_READ(control);
3487 DRM_DEBUG_KMS("\n");
3489 /* if we want to turn off the cursor ignore width and height */
3491 DRM_DEBUG_KMS("cursor off\n");
3492 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3493 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3494 temp |= CURSOR_MODE_DISABLE;
3496 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3500 mutex_lock(&dev->struct_mutex);
3504 /* Currently we only support 64x64 cursors */
3505 if (width != 64 || height != 64) {
3506 DRM_ERROR("we currently only support 64x64 cursors\n");
3510 bo = drm_gem_object_lookup(dev, file_priv, handle);
3514 obj_priv = to_intel_bo(bo);
3516 if (bo->size < width * height * 4) {
3517 DRM_ERROR("buffer is to small\n");
3522 /* we only need to pin inside GTT if cursor is non-phy */
3523 mutex_lock(&dev->struct_mutex);
3524 if (!dev_priv->info->cursor_needs_physical) {
3525 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3527 DRM_ERROR("failed to pin cursor bo\n");
3530 addr = obj_priv->gtt_offset;
3532 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3534 DRM_ERROR("failed to attach phys object\n");
3537 addr = obj_priv->phys_obj->handle->busaddr;
3541 I915_WRITE(CURSIZE, (height << 12) | width);
3543 /* Hooray for CUR*CNTR differences */
3544 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3545 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3546 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3547 temp |= (pipe << 28); /* Connect to correct pipe */
3549 temp &= ~(CURSOR_FORMAT_MASK);
3550 temp |= CURSOR_ENABLE;
3551 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3555 I915_WRITE(control, temp);
3556 I915_WRITE(base, addr);
3558 if (intel_crtc->cursor_bo) {
3559 if (dev_priv->info->cursor_needs_physical) {
3560 if (intel_crtc->cursor_bo != bo)
3561 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3563 i915_gem_object_unpin(intel_crtc->cursor_bo);
3564 drm_gem_object_unreference(intel_crtc->cursor_bo);
3567 mutex_unlock(&dev->struct_mutex);
3569 intel_crtc->cursor_addr = addr;
3570 intel_crtc->cursor_bo = bo;
3574 mutex_unlock(&dev->struct_mutex);
3576 drm_gem_object_unreference_unlocked(bo);
3580 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3582 struct drm_device *dev = crtc->dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585 struct intel_framebuffer *intel_fb;
3586 int pipe = intel_crtc->pipe;
3591 intel_fb = to_intel_framebuffer(crtc->fb);
3592 intel_mark_busy(dev, intel_fb->obj);
3596 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3600 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3604 temp |= x << CURSOR_X_SHIFT;
3605 temp |= y << CURSOR_Y_SHIFT;
3607 adder = intel_crtc->cursor_addr;
3608 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3609 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3614 /** Sets the color ramps on behalf of RandR */
3615 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3616 u16 blue, int regno)
3618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620 intel_crtc->lut_r[regno] = red >> 8;
3621 intel_crtc->lut_g[regno] = green >> 8;
3622 intel_crtc->lut_b[regno] = blue >> 8;
3625 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3626 u16 *blue, int regno)
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630 *red = intel_crtc->lut_r[regno] << 8;
3631 *green = intel_crtc->lut_g[regno] << 8;
3632 *blue = intel_crtc->lut_b[regno] << 8;
3635 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3636 u16 *blue, uint32_t size)
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 for (i = 0; i < 256; i++) {
3645 intel_crtc->lut_r[i] = red[i] >> 8;
3646 intel_crtc->lut_g[i] = green[i] >> 8;
3647 intel_crtc->lut_b[i] = blue[i] >> 8;
3650 intel_crtc_load_lut(crtc);
3654 * Get a pipe with a simple mode set on it for doing load-based monitor
3657 * It will be up to the load-detect code to adjust the pipe as appropriate for
3658 * its requirements. The pipe will be connected to no other encoders.
3660 * Currently this code will only succeed if there is a pipe with no encoders
3661 * configured for it. In the future, it could choose to temporarily disable
3662 * some outputs to free up a pipe for its use.
3664 * \return crtc, or NULL if no pipes are available.
3667 /* VESA 640x480x72Hz mode to set on the pipe */
3668 static struct drm_display_mode load_detect_mode = {
3669 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3670 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3673 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3674 struct drm_display_mode *mode,
3677 struct intel_crtc *intel_crtc;
3678 struct drm_crtc *possible_crtc;
3679 struct drm_crtc *supported_crtc =NULL;
3680 struct drm_encoder *encoder = &intel_encoder->enc;
3681 struct drm_crtc *crtc = NULL;
3682 struct drm_device *dev = encoder->dev;
3683 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3684 struct drm_crtc_helper_funcs *crtc_funcs;
3688 * Algorithm gets a little messy:
3689 * - if the connector already has an assigned crtc, use it (but make
3690 * sure it's on first)
3691 * - try to find the first unused crtc that can drive this connector,
3692 * and use that if we find one
3693 * - if there are no unused crtcs available, try to use the first
3694 * one we found that supports the connector
3697 /* See if we already have a CRTC for this connector */
3698 if (encoder->crtc) {
3699 crtc = encoder->crtc;
3700 /* Make sure the crtc and connector are running */
3701 intel_crtc = to_intel_crtc(crtc);
3702 *dpms_mode = intel_crtc->dpms_mode;
3703 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3704 crtc_funcs = crtc->helper_private;
3705 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3706 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3711 /* Find an unused one (if possible) */
3712 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3714 if (!(encoder->possible_crtcs & (1 << i)))
3716 if (!possible_crtc->enabled) {
3717 crtc = possible_crtc;
3720 if (!supported_crtc)
3721 supported_crtc = possible_crtc;
3725 * If we didn't find an unused CRTC, don't use any.
3731 encoder->crtc = crtc;
3732 intel_encoder->base.encoder = encoder;
3733 intel_encoder->load_detect_temp = true;
3735 intel_crtc = to_intel_crtc(crtc);
3736 *dpms_mode = intel_crtc->dpms_mode;
3738 if (!crtc->enabled) {
3740 mode = &load_detect_mode;
3741 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3743 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3744 crtc_funcs = crtc->helper_private;
3745 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3748 /* Add this connector to the crtc */
3749 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3750 encoder_funcs->commit(encoder);
3752 /* let the connector get through one full cycle before testing */
3753 intel_wait_for_vblank(dev);
3758 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpms_mode)
3760 struct drm_encoder *encoder = &intel_encoder->enc;
3761 struct drm_device *dev = encoder->dev;
3762 struct drm_crtc *crtc = encoder->crtc;
3763 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3764 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3766 if (intel_encoder->load_detect_temp) {
3767 encoder->crtc = NULL;
3768 intel_encoder->base.encoder = NULL;
3769 intel_encoder->load_detect_temp = false;
3770 crtc->enabled = drm_helper_crtc_in_use(crtc);
3771 drm_helper_disable_unused_functions(dev);
3774 /* Switch crtc and encoder back off if necessary */
3775 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3776 if (encoder->crtc == crtc)
3777 encoder_funcs->dpms(encoder, dpms_mode);
3778 crtc_funcs->dpms(crtc, dpms_mode);
3782 /* Returns the clock of the currently programmed mode of the given pipe. */
3783 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3787 int pipe = intel_crtc->pipe;
3788 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3790 intel_clock_t clock;
3792 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3793 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3795 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3797 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3798 if (IS_PINEVIEW(dev)) {
3799 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3800 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3802 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3803 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3807 if (IS_PINEVIEW(dev))
3808 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3809 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3811 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3812 DPLL_FPA01_P1_POST_DIV_SHIFT);
3814 switch (dpll & DPLL_MODE_MASK) {
3815 case DPLLB_MODE_DAC_SERIAL:
3816 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3819 case DPLLB_MODE_LVDS:
3820 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3824 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3825 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3829 /* XXX: Handle the 100Mhz refclk */
3830 intel_clock(dev, 96000, &clock);
3832 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3835 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3836 DPLL_FPA01_P1_POST_DIV_SHIFT);
3839 if ((dpll & PLL_REF_INPUT_MASK) ==
3840 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3841 /* XXX: might not be 66MHz */
3842 intel_clock(dev, 66000, &clock);
3844 intel_clock(dev, 48000, &clock);
3846 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3849 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3850 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3852 if (dpll & PLL_P2_DIVIDE_BY_4)
3857 intel_clock(dev, 48000, &clock);
3861 /* XXX: It would be nice to validate the clocks, but we can't reuse
3862 * i830PllIsValid() because it relies on the xf86_config connector
3863 * configuration being accurate, which it isn't necessarily.
3869 /** Returns the currently programmed mode of the given pipe. */
3870 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3871 struct drm_crtc *crtc)
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875 int pipe = intel_crtc->pipe;
3876 struct drm_display_mode *mode;
3877 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3878 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3879 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3880 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3882 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3886 mode->clock = intel_crtc_clock_get(dev, crtc);
3887 mode->hdisplay = (htot & 0xffff) + 1;
3888 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3889 mode->hsync_start = (hsync & 0xffff) + 1;
3890 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3891 mode->vdisplay = (vtot & 0xffff) + 1;
3892 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3893 mode->vsync_start = (vsync & 0xffff) + 1;
3894 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3896 drm_mode_set_name(mode);
3897 drm_mode_set_crtcinfo(mode, 0);
3902 #define GPU_IDLE_TIMEOUT 500 /* ms */
3904 /* When this timer fires, we've been idle for awhile */
3905 static void intel_gpu_idle_timer(unsigned long arg)
3907 struct drm_device *dev = (struct drm_device *)arg;
3908 drm_i915_private_t *dev_priv = dev->dev_private;
3910 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3912 dev_priv->busy = false;
3914 queue_work(dev_priv->wq, &dev_priv->idle_work);
3917 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3919 static void intel_crtc_idle_timer(unsigned long arg)
3921 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3922 struct drm_crtc *crtc = &intel_crtc->base;
3923 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3925 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3927 intel_crtc->busy = false;
3929 queue_work(dev_priv->wq, &dev_priv->idle_work);
3932 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3934 struct drm_device *dev = crtc->dev;
3935 drm_i915_private_t *dev_priv = dev->dev_private;
3936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3937 int pipe = intel_crtc->pipe;
3938 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3939 int dpll = I915_READ(dpll_reg);
3941 if (HAS_PCH_SPLIT(dev))
3944 if (!dev_priv->lvds_downclock_avail)
3947 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3948 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3950 /* Unlock panel regs */
3951 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3953 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3954 I915_WRITE(dpll_reg, dpll);
3955 dpll = I915_READ(dpll_reg);
3956 intel_wait_for_vblank(dev);
3957 dpll = I915_READ(dpll_reg);
3958 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3959 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3961 /* ...and lock them again */
3962 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3965 /* Schedule downclock */
3967 mod_timer(&intel_crtc->idle_timer, jiffies +
3968 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3971 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3973 struct drm_device *dev = crtc->dev;
3974 drm_i915_private_t *dev_priv = dev->dev_private;
3975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976 int pipe = intel_crtc->pipe;
3977 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3978 int dpll = I915_READ(dpll_reg);
3980 if (HAS_PCH_SPLIT(dev))
3983 if (!dev_priv->lvds_downclock_avail)
3987 * Since this is called by a timer, we should never get here in
3990 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3991 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3993 /* Unlock panel regs */
3994 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3996 dpll |= DISPLAY_RATE_SELECT_FPA1;
3997 I915_WRITE(dpll_reg, dpll);
3998 dpll = I915_READ(dpll_reg);
3999 intel_wait_for_vblank(dev);
4000 dpll = I915_READ(dpll_reg);
4001 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4002 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4004 /* ...and lock them again */
4005 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4011 * intel_idle_update - adjust clocks for idleness
4012 * @work: work struct
4014 * Either the GPU or display (or both) went idle. Check the busy status
4015 * here and adjust the CRTC and GPU clocks as necessary.
4017 static void intel_idle_update(struct work_struct *work)
4019 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4021 struct drm_device *dev = dev_priv->dev;
4022 struct drm_crtc *crtc;
4023 struct intel_crtc *intel_crtc;
4025 if (!i915_powersave)
4028 mutex_lock(&dev->struct_mutex);
4030 if (IS_I945G(dev) || IS_I945GM(dev)) {
4031 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4032 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4035 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4036 /* Skip inactive CRTCs */
4040 intel_crtc = to_intel_crtc(crtc);
4041 if (!intel_crtc->busy)
4042 intel_decrease_pllclock(crtc);
4045 mutex_unlock(&dev->struct_mutex);
4049 * intel_mark_busy - mark the GPU and possibly the display busy
4051 * @obj: object we're operating on
4053 * Callers can use this function to indicate that the GPU is busy processing
4054 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4055 * buffer), we'll also mark the display as busy, so we know to increase its
4058 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4060 drm_i915_private_t *dev_priv = dev->dev_private;
4061 struct drm_crtc *crtc = NULL;
4062 struct intel_framebuffer *intel_fb;
4063 struct intel_crtc *intel_crtc;
4065 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4068 if (!dev_priv->busy) {
4069 if (IS_I945G(dev) || IS_I945GM(dev)) {
4072 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4073 fw_blc_self = I915_READ(FW_BLC_SELF);
4074 fw_blc_self &= ~FW_BLC_SELF_EN;
4075 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4077 dev_priv->busy = true;
4079 mod_timer(&dev_priv->idle_timer, jiffies +
4080 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4086 intel_crtc = to_intel_crtc(crtc);
4087 intel_fb = to_intel_framebuffer(crtc->fb);
4088 if (intel_fb->obj == obj) {
4089 if (!intel_crtc->busy) {
4090 if (IS_I945G(dev) || IS_I945GM(dev)) {
4093 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4094 fw_blc_self = I915_READ(FW_BLC_SELF);
4095 fw_blc_self &= ~FW_BLC_SELF_EN;
4096 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4098 /* Non-busy -> busy, upclock */
4099 intel_increase_pllclock(crtc, true);
4100 intel_crtc->busy = true;
4102 /* Busy -> busy, put off timer */
4103 mod_timer(&intel_crtc->idle_timer, jiffies +
4104 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4110 static void intel_crtc_destroy(struct drm_crtc *crtc)
4112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4114 drm_crtc_cleanup(crtc);
4118 struct intel_unpin_work {
4119 struct work_struct work;
4120 struct drm_device *dev;
4121 struct drm_gem_object *old_fb_obj;
4122 struct drm_gem_object *pending_flip_obj;
4123 struct drm_pending_vblank_event *event;
4127 static void intel_unpin_work_fn(struct work_struct *__work)
4129 struct intel_unpin_work *work =
4130 container_of(__work, struct intel_unpin_work, work);
4132 mutex_lock(&work->dev->struct_mutex);
4133 i915_gem_object_unpin(work->old_fb_obj);
4134 drm_gem_object_unreference(work->pending_flip_obj);
4135 drm_gem_object_unreference(work->old_fb_obj);
4136 mutex_unlock(&work->dev->struct_mutex);
4140 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4142 drm_i915_private_t *dev_priv = dev->dev_private;
4143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145 struct intel_unpin_work *work;
4146 struct drm_i915_gem_object *obj_priv;
4147 struct drm_pending_vblank_event *e;
4149 unsigned long flags;
4151 /* Ignore early vblank irqs */
4152 if (intel_crtc == NULL)
4155 spin_lock_irqsave(&dev->event_lock, flags);
4156 work = intel_crtc->unpin_work;
4157 if (work == NULL || !work->pending) {
4158 if (work && !work->pending) {
4159 obj_priv = to_intel_bo(work->pending_flip_obj);
4160 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4162 atomic_read(&obj_priv->pending_flip));
4164 spin_unlock_irqrestore(&dev->event_lock, flags);
4168 intel_crtc->unpin_work = NULL;
4169 drm_vblank_put(dev, intel_crtc->pipe);
4173 do_gettimeofday(&now);
4174 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4175 e->event.tv_sec = now.tv_sec;
4176 e->event.tv_usec = now.tv_usec;
4177 list_add_tail(&e->base.link,
4178 &e->base.file_priv->event_list);
4179 wake_up_interruptible(&e->base.file_priv->event_wait);
4182 spin_unlock_irqrestore(&dev->event_lock, flags);
4184 obj_priv = to_intel_bo(work->pending_flip_obj);
4186 /* Initial scanout buffer will have a 0 pending flip count */
4187 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4188 atomic_dec_and_test(&obj_priv->pending_flip))
4189 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4190 schedule_work(&work->work);
4193 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4195 drm_i915_private_t *dev_priv = dev->dev_private;
4196 struct intel_crtc *intel_crtc =
4197 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4198 unsigned long flags;
4200 spin_lock_irqsave(&dev->event_lock, flags);
4201 if (intel_crtc->unpin_work) {
4202 intel_crtc->unpin_work->pending = 1;
4204 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4206 spin_unlock_irqrestore(&dev->event_lock, flags);
4209 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4210 struct drm_framebuffer *fb,
4211 struct drm_pending_vblank_event *event)
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_framebuffer *intel_fb;
4216 struct drm_i915_gem_object *obj_priv;
4217 struct drm_gem_object *obj;
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219 struct intel_unpin_work *work;
4220 unsigned long flags;
4221 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4225 work = kzalloc(sizeof *work, GFP_KERNEL);
4229 mutex_lock(&dev->struct_mutex);
4231 work->event = event;
4232 work->dev = crtc->dev;
4233 intel_fb = to_intel_framebuffer(crtc->fb);
4234 work->old_fb_obj = intel_fb->obj;
4235 INIT_WORK(&work->work, intel_unpin_work_fn);
4237 /* We borrow the event spin lock for protecting unpin_work */
4238 spin_lock_irqsave(&dev->event_lock, flags);
4239 if (intel_crtc->unpin_work) {
4240 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4241 spin_unlock_irqrestore(&dev->event_lock, flags);
4243 mutex_unlock(&dev->struct_mutex);
4246 intel_crtc->unpin_work = work;
4247 spin_unlock_irqrestore(&dev->event_lock, flags);
4249 intel_fb = to_intel_framebuffer(fb);
4250 obj = intel_fb->obj;
4252 ret = intel_pin_and_fence_fb_obj(dev, obj);
4254 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4257 intel_crtc->unpin_work = NULL;
4258 mutex_unlock(&dev->struct_mutex);
4262 /* Reference the objects for the scheduled work. */
4263 drm_gem_object_reference(work->old_fb_obj);
4264 drm_gem_object_reference(obj);
4267 i915_gem_object_flush_write_domain(obj);
4268 drm_vblank_get(dev, intel_crtc->pipe);
4269 obj_priv = to_intel_bo(obj);
4270 atomic_inc(&obj_priv->pending_flip);
4271 work->pending_flip_obj = obj;
4274 OUT_RING(MI_DISPLAY_FLIP |
4275 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4276 OUT_RING(fb->pitch);
4277 if (IS_I965G(dev)) {
4278 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4279 pipesrc = I915_READ(pipesrc_reg);
4280 OUT_RING(pipesrc & 0x0fff0fff);
4282 OUT_RING(obj_priv->gtt_offset);
4287 mutex_unlock(&dev->struct_mutex);
4292 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4293 .dpms = intel_crtc_dpms,
4294 .mode_fixup = intel_crtc_mode_fixup,
4295 .mode_set = intel_crtc_mode_set,
4296 .mode_set_base = intel_pipe_set_base,
4297 .prepare = intel_crtc_prepare,
4298 .commit = intel_crtc_commit,
4299 .load_lut = intel_crtc_load_lut,
4302 static const struct drm_crtc_funcs intel_crtc_funcs = {
4303 .cursor_set = intel_crtc_cursor_set,
4304 .cursor_move = intel_crtc_cursor_move,
4305 .gamma_set = intel_crtc_gamma_set,
4306 .set_config = drm_crtc_helper_set_config,
4307 .destroy = intel_crtc_destroy,
4308 .page_flip = intel_crtc_page_flip,
4312 static void intel_crtc_init(struct drm_device *dev, int pipe)
4314 drm_i915_private_t *dev_priv = dev->dev_private;
4315 struct intel_crtc *intel_crtc;
4318 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4319 if (intel_crtc == NULL)
4322 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4324 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4325 intel_crtc->pipe = pipe;
4326 intel_crtc->plane = pipe;
4327 for (i = 0; i < 256; i++) {
4328 intel_crtc->lut_r[i] = i;
4329 intel_crtc->lut_g[i] = i;
4330 intel_crtc->lut_b[i] = i;
4333 /* Swap pipes & planes for FBC on pre-965 */
4334 intel_crtc->pipe = pipe;
4335 intel_crtc->plane = pipe;
4336 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4337 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4338 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4341 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4342 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4343 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4344 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4346 intel_crtc->cursor_addr = 0;
4347 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4348 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4350 intel_crtc->busy = false;
4352 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4353 (unsigned long)intel_crtc);
4356 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4357 struct drm_file *file_priv)
4359 drm_i915_private_t *dev_priv = dev->dev_private;
4360 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4361 struct drm_mode_object *drmmode_obj;
4362 struct intel_crtc *crtc;
4365 DRM_ERROR("called with no initialization\n");
4369 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4370 DRM_MODE_OBJECT_CRTC);
4373 DRM_ERROR("no such CRTC id\n");
4377 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4378 pipe_from_crtc_id->pipe = crtc->pipe;
4383 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4385 struct drm_crtc *crtc = NULL;
4387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4389 if (intel_crtc->pipe == pipe)
4395 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4398 struct drm_encoder *encoder;
4401 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4402 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4403 if (type_mask & intel_encoder->clone_mask)
4404 index_mask |= (1 << entry);
4411 static void intel_setup_outputs(struct drm_device *dev)
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414 struct drm_encoder *encoder;
4416 intel_crt_init(dev);
4418 /* Set up integrated LVDS */
4419 if (IS_MOBILE(dev) && !IS_I830(dev))
4420 intel_lvds_init(dev);
4422 if (HAS_PCH_SPLIT(dev)) {
4425 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4426 intel_dp_init(dev, DP_A);
4428 if (I915_READ(HDMIB) & PORT_DETECTED) {
4430 /* found = intel_sdvo_init(dev, HDMIB); */
4433 intel_hdmi_init(dev, HDMIB);
4434 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4435 intel_dp_init(dev, PCH_DP_B);
4438 if (I915_READ(HDMIC) & PORT_DETECTED)
4439 intel_hdmi_init(dev, HDMIC);
4441 if (I915_READ(HDMID) & PORT_DETECTED)
4442 intel_hdmi_init(dev, HDMID);
4444 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4445 intel_dp_init(dev, PCH_DP_C);
4447 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4448 intel_dp_init(dev, PCH_DP_D);
4450 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4453 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4454 DRM_DEBUG_KMS("probing SDVOB\n");
4455 found = intel_sdvo_init(dev, SDVOB);
4456 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4457 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4458 intel_hdmi_init(dev, SDVOB);
4461 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4462 DRM_DEBUG_KMS("probing DP_B\n");
4463 intel_dp_init(dev, DP_B);
4467 /* Before G4X SDVOC doesn't have its own detect register */
4469 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4470 DRM_DEBUG_KMS("probing SDVOC\n");
4471 found = intel_sdvo_init(dev, SDVOC);
4474 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4476 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4477 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4478 intel_hdmi_init(dev, SDVOC);
4480 if (SUPPORTS_INTEGRATED_DP(dev)) {
4481 DRM_DEBUG_KMS("probing DP_C\n");
4482 intel_dp_init(dev, DP_C);
4486 if (SUPPORTS_INTEGRATED_DP(dev) &&
4487 (I915_READ(DP_D) & DP_DETECTED)) {
4488 DRM_DEBUG_KMS("probing DP_D\n");
4489 intel_dp_init(dev, DP_D);
4491 } else if (IS_GEN2(dev))
4492 intel_dvo_init(dev);
4494 if (SUPPORTS_TV(dev))
4497 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4498 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4500 encoder->possible_crtcs = intel_encoder->crtc_mask;
4501 encoder->possible_clones = intel_encoder_clones(dev,
4502 intel_encoder->clone_mask);
4506 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4508 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4509 struct drm_device *dev = fb->dev;
4512 intelfb_remove(dev, fb);
4514 drm_framebuffer_cleanup(fb);
4515 drm_gem_object_unreference_unlocked(intel_fb->obj);
4520 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4521 struct drm_file *file_priv,
4522 unsigned int *handle)
4524 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4525 struct drm_gem_object *object = intel_fb->obj;
4527 return drm_gem_handle_create(file_priv, object, handle);
4530 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4531 .destroy = intel_user_framebuffer_destroy,
4532 .create_handle = intel_user_framebuffer_create_handle,
4535 int intel_framebuffer_create(struct drm_device *dev,
4536 struct drm_mode_fb_cmd *mode_cmd,
4537 struct drm_framebuffer **fb,
4538 struct drm_gem_object *obj)
4540 struct intel_framebuffer *intel_fb;
4543 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4547 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4549 DRM_ERROR("framebuffer init failed %d\n", ret);
4553 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4555 intel_fb->obj = obj;
4557 *fb = &intel_fb->base;
4563 static struct drm_framebuffer *
4564 intel_user_framebuffer_create(struct drm_device *dev,
4565 struct drm_file *filp,
4566 struct drm_mode_fb_cmd *mode_cmd)
4568 struct drm_gem_object *obj;
4569 struct drm_framebuffer *fb;
4572 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4576 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4578 drm_gem_object_unreference_unlocked(obj);
4585 static const struct drm_mode_config_funcs intel_mode_funcs = {
4586 .fb_create = intel_user_framebuffer_create,
4587 .fb_changed = intelfb_probe,
4590 static struct drm_gem_object *
4591 intel_alloc_power_context(struct drm_device *dev)
4593 struct drm_gem_object *pwrctx;
4596 pwrctx = drm_gem_object_alloc(dev, 4096);
4598 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4602 mutex_lock(&dev->struct_mutex);
4603 ret = i915_gem_object_pin(pwrctx, 4096);
4605 DRM_ERROR("failed to pin power context: %d\n", ret);
4609 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4611 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4614 mutex_unlock(&dev->struct_mutex);
4619 i915_gem_object_unpin(pwrctx);
4621 drm_gem_object_unreference(pwrctx);
4622 mutex_unlock(&dev->struct_mutex);
4626 void ironlake_enable_drps(struct drm_device *dev)
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4630 u8 fmax, fmin, fstart, vstart;
4633 /* 100ms RC evaluation intervals */
4634 I915_WRITE(RCUPEI, 100000);
4635 I915_WRITE(RCDNEI, 100000);
4637 /* Set max/min thresholds to 90ms and 80ms respectively */
4638 I915_WRITE(RCBMAXAVG, 90000);
4639 I915_WRITE(RCBMINAVG, 80000);
4641 I915_WRITE(MEMIHYST, 1);
4643 /* Set up min, max, and cur for interrupt handling */
4644 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4645 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4646 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4647 MEMMODE_FSTART_SHIFT;
4648 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4651 dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4652 dev_priv->min_delay = fmin;
4653 dev_priv->cur_delay = fstart;
4655 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4658 * Interrupts will be enabled in ironlake_irq_postinstall
4661 I915_WRITE(VIDSTART, vstart);
4662 POSTING_READ(VIDSTART);
4664 rgvmodectl |= MEMMODE_SWMODE_EN;
4665 I915_WRITE(MEMMODECTL, rgvmodectl);
4667 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4669 DRM_ERROR("stuck trying to change perf mode\n");
4676 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4677 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4678 I915_WRITE(MEMSWCTL, rgvswctl);
4679 POSTING_READ(MEMSWCTL);
4681 rgvswctl |= MEMCTL_CMD_STS;
4682 I915_WRITE(MEMSWCTL, rgvswctl);
4685 void ironlake_disable_drps(struct drm_device *dev)
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4691 /* Ack interrupts, disable EFC interrupt */
4692 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4693 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4694 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4695 I915_WRITE(DEIIR, DE_PCU_EVENT);
4696 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4698 /* Go back to the starting frequency */
4699 fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4700 MEMMODE_FSTART_SHIFT;
4701 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4702 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4703 I915_WRITE(MEMSWCTL, rgvswctl);
4705 rgvswctl |= MEMCTL_CMD_STS;
4706 I915_WRITE(MEMSWCTL, rgvswctl);
4711 void intel_init_clock_gating(struct drm_device *dev)
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4716 * Disable clock gating reported to work incorrectly according to the
4717 * specs, but enable as much else as we can.
4719 if (HAS_PCH_SPLIT(dev)) {
4720 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
4722 if (IS_IRONLAKE(dev)) {
4723 /* Required for FBC */
4724 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
4725 /* Required for CxSR */
4726 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
4728 I915_WRITE(PCH_3DCGDIS0,
4729 MARIUNIT_CLOCK_GATE_DISABLE |
4730 SVSMUNIT_CLOCK_GATE_DISABLE);
4733 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
4735 } else if (IS_G4X(dev)) {
4736 uint32_t dspclk_gate;
4737 I915_WRITE(RENCLK_GATE_D1, 0);
4738 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4739 GS_UNIT_CLOCK_GATE_DISABLE |
4740 CL_UNIT_CLOCK_GATE_DISABLE);
4741 I915_WRITE(RAMCLK_GATE_D, 0);
4742 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4743 OVRUNIT_CLOCK_GATE_DISABLE |
4744 OVCUNIT_CLOCK_GATE_DISABLE;
4746 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4747 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4748 } else if (IS_I965GM(dev)) {
4749 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4750 I915_WRITE(RENCLK_GATE_D2, 0);
4751 I915_WRITE(DSPCLK_GATE_D, 0);
4752 I915_WRITE(RAMCLK_GATE_D, 0);
4753 I915_WRITE16(DEUC, 0);
4754 } else if (IS_I965G(dev)) {
4755 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4756 I965_RCC_CLOCK_GATE_DISABLE |
4757 I965_RCPB_CLOCK_GATE_DISABLE |
4758 I965_ISC_CLOCK_GATE_DISABLE |
4759 I965_FBC_CLOCK_GATE_DISABLE);
4760 I915_WRITE(RENCLK_GATE_D2, 0);
4761 } else if (IS_I9XX(dev)) {
4762 u32 dstate = I915_READ(D_STATE);
4764 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4765 DSTATE_DOT_CLOCK_GATING;
4766 I915_WRITE(D_STATE, dstate);
4767 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4768 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4769 } else if (IS_I830(dev)) {
4770 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4774 * GPU can automatically power down the render unit if given a page
4777 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4778 struct drm_i915_gem_object *obj_priv = NULL;
4780 if (dev_priv->pwrctx) {
4781 obj_priv = to_intel_bo(dev_priv->pwrctx);
4783 struct drm_gem_object *pwrctx;
4785 pwrctx = intel_alloc_power_context(dev);
4787 dev_priv->pwrctx = pwrctx;
4788 obj_priv = to_intel_bo(pwrctx);
4793 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4794 I915_WRITE(MCHBAR_RENDER_STANDBY,
4795 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4800 /* Set up chip specific display functions */
4801 static void intel_init_display(struct drm_device *dev)
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4805 /* We always want a DPMS function */
4806 if (HAS_PCH_SPLIT(dev))
4807 dev_priv->display.dpms = ironlake_crtc_dpms;
4809 dev_priv->display.dpms = i9xx_crtc_dpms;
4811 /* Only mobile has FBC, leave pointers NULL for other chips */
4812 if (IS_MOBILE(dev)) {
4814 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4815 dev_priv->display.enable_fbc = g4x_enable_fbc;
4816 dev_priv->display.disable_fbc = g4x_disable_fbc;
4817 } else if (IS_I965GM(dev)) {
4818 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4819 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4820 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4822 /* 855GM needs testing */
4825 /* Returns the core display clock speed */
4826 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4827 dev_priv->display.get_display_clock_speed =
4828 i945_get_display_clock_speed;
4829 else if (IS_I915G(dev))
4830 dev_priv->display.get_display_clock_speed =
4831 i915_get_display_clock_speed;
4832 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4833 dev_priv->display.get_display_clock_speed =
4834 i9xx_misc_get_display_clock_speed;
4835 else if (IS_I915GM(dev))
4836 dev_priv->display.get_display_clock_speed =
4837 i915gm_get_display_clock_speed;
4838 else if (IS_I865G(dev))
4839 dev_priv->display.get_display_clock_speed =
4840 i865_get_display_clock_speed;
4841 else if (IS_I85X(dev))
4842 dev_priv->display.get_display_clock_speed =
4843 i855_get_display_clock_speed;
4845 dev_priv->display.get_display_clock_speed =
4846 i830_get_display_clock_speed;
4848 /* For FIFO watermark updates */
4849 if (HAS_PCH_SPLIT(dev))
4850 dev_priv->display.update_wm = NULL;
4851 else if (IS_G4X(dev))
4852 dev_priv->display.update_wm = g4x_update_wm;
4853 else if (IS_I965G(dev))
4854 dev_priv->display.update_wm = i965_update_wm;
4855 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4856 dev_priv->display.update_wm = i9xx_update_wm;
4857 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4860 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4861 else if (IS_845G(dev))
4862 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4864 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4865 dev_priv->display.update_wm = i830_update_wm;
4869 void intel_modeset_init(struct drm_device *dev)
4871 struct drm_i915_private *dev_priv = dev->dev_private;
4875 drm_mode_config_init(dev);
4877 dev->mode_config.min_width = 0;
4878 dev->mode_config.min_height = 0;
4880 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4882 intel_init_display(dev);
4884 if (IS_I965G(dev)) {
4885 dev->mode_config.max_width = 8192;
4886 dev->mode_config.max_height = 8192;
4887 } else if (IS_I9XX(dev)) {
4888 dev->mode_config.max_width = 4096;
4889 dev->mode_config.max_height = 4096;
4891 dev->mode_config.max_width = 2048;
4892 dev->mode_config.max_height = 2048;
4895 /* set memory base */
4897 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4899 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4901 if (IS_MOBILE(dev) || IS_I9XX(dev))
4905 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4906 num_pipe, num_pipe > 1 ? "s" : "");
4908 for (i = 0; i < num_pipe; i++) {
4909 intel_crtc_init(dev, i);
4912 intel_setup_outputs(dev);
4914 intel_init_clock_gating(dev);
4916 if (IS_IRONLAKE_M(dev))
4917 ironlake_enable_drps(dev);
4919 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4920 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4921 (unsigned long)dev);
4923 intel_setup_overlay(dev);
4925 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4927 dev_priv->mem_freq))
4928 DRM_INFO("failed to find known CxSR latency "
4929 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4930 dev_priv->fsb_freq, dev_priv->mem_freq);
4933 void intel_modeset_cleanup(struct drm_device *dev)
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 struct drm_crtc *crtc;
4937 struct intel_crtc *intel_crtc;
4939 mutex_lock(&dev->struct_mutex);
4941 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4942 /* Skip inactive CRTCs */
4946 intel_crtc = to_intel_crtc(crtc);
4947 intel_increase_pllclock(crtc, false);
4948 del_timer_sync(&intel_crtc->idle_timer);
4951 del_timer_sync(&dev_priv->idle_timer);
4953 if (dev_priv->display.disable_fbc)
4954 dev_priv->display.disable_fbc(dev);
4956 if (dev_priv->pwrctx) {
4957 struct drm_i915_gem_object *obj_priv;
4959 obj_priv = to_intel_bo(dev_priv->pwrctx);
4960 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4962 i915_gem_object_unpin(dev_priv->pwrctx);
4963 drm_gem_object_unreference(dev_priv->pwrctx);
4966 if (IS_IRONLAKE_M(dev))
4967 ironlake_disable_drps(dev);
4969 mutex_unlock(&dev->struct_mutex);
4971 drm_mode_config_cleanup(dev);
4975 /* current intel driver doesn't take advantage of encoders
4976 always give back the encoder for the connector
4978 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4980 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4982 return &intel_encoder->enc;
4986 * Return which encoder is currently attached for connector.
4988 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
4990 struct drm_mode_object *obj;
4991 struct drm_encoder *encoder;
4994 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
4995 if (connector->encoder_ids[i] == 0)
4998 obj = drm_mode_object_find(connector->dev,
4999 connector->encoder_ids[i],
5000 DRM_MODE_OBJECT_ENCODER);
5004 encoder = obj_to_encoder(obj);
5011 * set vga decode state - true == enable VGA decode
5013 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5018 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5020 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5022 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5023 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);