2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
32 #include "intel_drv.h"
37 #include "drm_crtc_helper.h"
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
77 #define I8XX_DOT_MIN 25000
78 #define I8XX_DOT_MAX 350000
79 #define I8XX_VCO_MIN 930000
80 #define I8XX_VCO_MAX 1400000
84 #define I8XX_M_MAX 140
85 #define I8XX_M1_MIN 18
86 #define I8XX_M1_MAX 26
88 #define I8XX_M2_MAX 16
90 #define I8XX_P_MAX 128
92 #define I8XX_P1_MAX 33
93 #define I8XX_P1_LVDS_MIN 1
94 #define I8XX_P1_LVDS_MAX 6
95 #define I8XX_P2_SLOW 4
96 #define I8XX_P2_FAST 2
97 #define I8XX_P2_LVDS_SLOW 14
98 #define I8XX_P2_LVDS_FAST 7
99 #define I8XX_P2_SLOW_LIMIT 165000
101 #define I9XX_DOT_MIN 20000
102 #define I9XX_DOT_MAX 400000
103 #define I9XX_VCO_MIN 1400000
104 #define I9XX_VCO_MAX 2800000
105 #define IGD_VCO_MIN 1700000
106 #define IGD_VCO_MAX 3500000
109 /* IGD's Ncounter is a ring counter */
112 #define I9XX_M_MIN 70
113 #define I9XX_M_MAX 120
115 #define IGD_M_MAX 256
116 #define I9XX_M1_MIN 10
117 #define I9XX_M1_MAX 22
118 #define I9XX_M2_MIN 5
119 #define I9XX_M2_MAX 9
120 /* IGD M1 is reserved, and must be 0 */
124 #define IGD_M2_MAX 254
125 #define I9XX_P_SDVO_DAC_MIN 5
126 #define I9XX_P_SDVO_DAC_MAX 80
127 #define I9XX_P_LVDS_MIN 7
128 #define I9XX_P_LVDS_MAX 98
129 #define IGD_P_LVDS_MIN 7
130 #define IGD_P_LVDS_MAX 112
131 #define I9XX_P1_MIN 1
132 #define I9XX_P1_MAX 8
133 #define I9XX_P2_SDVO_DAC_SLOW 10
134 #define I9XX_P2_SDVO_DAC_FAST 5
135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
136 #define I9XX_P2_LVDS_SLOW 14
137 #define I9XX_P2_LVDS_FAST 7
138 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
140 /*The parameter is for SDVO on G4x platform*/
141 #define G4X_DOT_SDVO_MIN 25000
142 #define G4X_DOT_SDVO_MAX 270000
143 #define G4X_VCO_MIN 1750000
144 #define G4X_VCO_MAX 3500000
145 #define G4X_N_SDVO_MIN 1
146 #define G4X_N_SDVO_MAX 4
147 #define G4X_M_SDVO_MIN 104
148 #define G4X_M_SDVO_MAX 138
149 #define G4X_M1_SDVO_MIN 17
150 #define G4X_M1_SDVO_MAX 23
151 #define G4X_M2_SDVO_MIN 5
152 #define G4X_M2_SDVO_MAX 11
153 #define G4X_P_SDVO_MIN 10
154 #define G4X_P_SDVO_MAX 30
155 #define G4X_P1_SDVO_MIN 1
156 #define G4X_P1_SDVO_MAX 3
157 #define G4X_P2_SDVO_SLOW 10
158 #define G4X_P2_SDVO_FAST 10
159 #define G4X_P2_SDVO_LIMIT 270000
161 /*The parameter is for HDMI_DAC on G4x platform*/
162 #define G4X_DOT_HDMI_DAC_MIN 22000
163 #define G4X_DOT_HDMI_DAC_MAX 400000
164 #define G4X_N_HDMI_DAC_MIN 1
165 #define G4X_N_HDMI_DAC_MAX 4
166 #define G4X_M_HDMI_DAC_MIN 104
167 #define G4X_M_HDMI_DAC_MAX 138
168 #define G4X_M1_HDMI_DAC_MIN 16
169 #define G4X_M1_HDMI_DAC_MAX 23
170 #define G4X_M2_HDMI_DAC_MIN 5
171 #define G4X_M2_HDMI_DAC_MAX 11
172 #define G4X_P_HDMI_DAC_MIN 5
173 #define G4X_P_HDMI_DAC_MAX 80
174 #define G4X_P1_HDMI_DAC_MIN 1
175 #define G4X_P1_HDMI_DAC_MAX 8
176 #define G4X_P2_HDMI_DAC_SLOW 10
177 #define G4X_P2_HDMI_DAC_FAST 5
178 #define G4X_P2_HDMI_DAC_LIMIT 165000
180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218 /*The parameter is for DISPLAY PORT on G4x platform*/
219 #define G4X_DOT_DISPLAY_PORT_MIN 161670
220 #define G4X_DOT_DISPLAY_PORT_MAX 227000
221 #define G4X_N_DISPLAY_PORT_MIN 1
222 #define G4X_N_DISPLAY_PORT_MAX 2
223 #define G4X_M_DISPLAY_PORT_MIN 97
224 #define G4X_M_DISPLAY_PORT_MAX 108
225 #define G4X_M1_DISPLAY_PORT_MIN 0x10
226 #define G4X_M1_DISPLAY_PORT_MAX 0x12
227 #define G4X_M2_DISPLAY_PORT_MIN 0x05
228 #define G4X_M2_DISPLAY_PORT_MAX 0x06
229 #define G4X_P_DISPLAY_PORT_MIN 10
230 #define G4X_P_DISPLAY_PORT_MAX 20
231 #define G4X_P1_DISPLAY_PORT_MIN 1
232 #define G4X_P1_DISPLAY_PORT_MAX 2
233 #define G4X_P2_DISPLAY_PORT_SLOW 10
234 #define G4X_P2_DISPLAY_PORT_FAST 10
235 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238 /* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2).
241 #define IGDNG_DOT_MIN 25000
242 #define IGDNG_DOT_MAX 350000
243 #define IGDNG_VCO_MIN 1760000
244 #define IGDNG_VCO_MAX 3510000
245 #define IGDNG_N_MIN 1
246 #define IGDNG_N_MAX 5
247 #define IGDNG_M_MIN 79
248 #define IGDNG_M_MAX 118
249 #define IGDNG_M1_MIN 12
250 #define IGDNG_M1_MAX 23
251 #define IGDNG_M2_MIN 5
252 #define IGDNG_M2_MAX 9
253 #define IGDNG_P_SDVO_DAC_MIN 5
254 #define IGDNG_P_SDVO_DAC_MAX 80
255 #define IGDNG_P_LVDS_MIN 28
256 #define IGDNG_P_LVDS_MAX 112
257 #define IGDNG_P1_MIN 1
258 #define IGDNG_P1_MAX 8
259 #define IGDNG_P2_SDVO_DAC_SLOW 10
260 #define IGDNG_P2_SDVO_DAC_FAST 5
261 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
262 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
263 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock);
269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock);
275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock);
282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock);
285 static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
287 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
288 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
289 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
290 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
291 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
292 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
293 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
300 static const intel_limit_t intel_limits_i8xx_lvds = {
301 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
302 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
303 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
304 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
305 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
306 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
307 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
308 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
315 static const intel_limit_t intel_limits_i9xx_sdvo = {
316 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
317 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
318 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
319 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
320 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
321 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
322 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
323 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
330 static const intel_limit_t intel_limits_i9xx_lvds = {
331 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
332 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
333 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
334 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
335 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
336 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
337 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
338 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
339 /* The single-channel range is 25-112Mhz, and dual-channel
340 * is 80-224Mhz. Prefer single channel as much as possible.
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
348 /* below parameter and function is for G4X Chipset Family*/
349 static const intel_limit_t intel_limits_g4x_sdvo = {
350 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
351 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
352 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
353 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
354 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
355 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
356 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
357 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
358 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
359 .p2_slow = G4X_P2_SDVO_SLOW,
360 .p2_fast = G4X_P2_SDVO_FAST
362 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
366 static const intel_limit_t intel_limits_g4x_hdmi = {
367 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
368 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
369 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
370 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
371 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
372 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
373 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
374 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
375 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
376 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
377 .p2_fast = G4X_P2_HDMI_DAC_FAST
379 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
384 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
385 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
386 .vco = { .min = G4X_VCO_MIN,
387 .max = G4X_VCO_MAX },
388 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
390 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
392 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
394 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
395 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
396 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
397 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
398 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
399 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
400 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
401 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
404 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
409 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
410 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
411 .vco = { .min = G4X_VCO_MIN,
412 .max = G4X_VCO_MAX },
413 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
414 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
415 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
416 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
417 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
418 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
419 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
420 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
421 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
422 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
423 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
424 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
425 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
426 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
429 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
433 static const intel_limit_t intel_limits_g4x_display_port = {
434 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
435 .max = G4X_DOT_DISPLAY_PORT_MAX },
436 .vco = { .min = G4X_VCO_MIN,
438 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
439 .max = G4X_N_DISPLAY_PORT_MAX },
440 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
441 .max = G4X_M_DISPLAY_PORT_MAX },
442 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
443 .max = G4X_M1_DISPLAY_PORT_MAX },
444 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
445 .max = G4X_M2_DISPLAY_PORT_MAX },
446 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
447 .max = G4X_P_DISPLAY_PORT_MAX },
448 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
449 .max = G4X_P1_DISPLAY_PORT_MAX},
450 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
451 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
452 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
453 .find_pll = intel_find_pll_g4x_dp,
456 static const intel_limit_t intel_limits_igd_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
471 static const intel_limit_t intel_limits_igd_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
487 static const intel_limit_t intel_limits_igdng_sdvo = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL,
502 static const intel_limit_t intel_limits_igdng_lvds = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL,
517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_igdng_lvds;
523 limit = &intel_limits_igdng_sdvo;
528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
530 struct drm_device *dev = crtc->dev;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 const intel_limit_t *limit;
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
535 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
537 /* LVDS with dual channel */
538 limit = &intel_limits_g4x_dual_channel_lvds;
540 /* LVDS with dual channel */
541 limit = &intel_limits_g4x_single_channel_lvds;
542 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
543 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
544 limit = &intel_limits_g4x_hdmi;
545 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
546 limit = &intel_limits_g4x_sdvo;
547 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
548 limit = &intel_limits_g4x_display_port;
549 } else /* The option is for other outputs */
550 limit = &intel_limits_i9xx_sdvo;
555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit;
561 limit = intel_igdng_limit(crtc);
562 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds;
568 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds;
573 limit = &intel_limits_igd_sdvo;
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds;
578 limit = &intel_limits_i8xx_dvo;
583 /* m1 is reserved as 0 in IGD, n is a ring counter */
584 static void igd_clock(int refclk, intel_clock_t *clock)
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 clock->vco = refclk * clock->m / clock->n;
589 clock->dot = clock->vco / clock->p;
592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
595 igd_clock(refclk, clock);
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
599 clock->p = clock->p1 * clock->p2;
600 clock->vco = refclk * clock->m / (clock->n + 2);
601 clock->dot = clock->vco / clock->p;
605 * Returns whether any output on the specified pipe is of the specified type
607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
609 struct drm_device *dev = crtc->dev;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *l_entry;
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) {
616 struct intel_output *intel_output = to_intel_output(l_entry);
617 if (intel_output->type == type)
624 struct drm_connector *
625 intel_pipe_get_output (struct drm_crtc *crtc)
627 struct drm_device *dev = crtc->dev;
628 struct drm_mode_config *mode_config = &dev->mode_config;
629 struct drm_connector *l_entry, *ret = NULL;
631 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
632 if (l_entry->encoder &&
633 l_entry->encoder->crtc == crtc) {
641 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
643 * Returns whether the given set of divisors are valid for a given refclk with
644 * the given connectors.
647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
649 const intel_limit_t *limit = intel_limit (crtc);
650 struct drm_device *dev = crtc->dev;
652 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
653 INTELPllInvalid ("p1 out of range\n");
654 if (clock->p < limit->p.min || limit->p.max < clock->p)
655 INTELPllInvalid ("p out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n");
664 if (clock->n < limit->n.min || limit->n.max < clock->n)
665 INTELPllInvalid ("n out of range\n");
666 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
667 INTELPllInvalid ("vco out of range\n");
668 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
669 * connector, etc., rather than just a single range.
671 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
672 INTELPllInvalid ("dot out of range\n");
678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *best_clock)
682 struct drm_device *dev = crtc->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
687 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
688 (I915_READ(LVDS)) != 0) {
690 * For LVDS, if the panel is on, just rely on its current
691 * settings for dual-channel. We haven't figured out how to
692 * reliably set up different single/dual channel state, if we
695 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
697 clock.p2 = limit->p2.p2_fast;
699 clock.p2 = limit->p2.p2_slow;
701 if (target < limit->p2.dot_limit)
702 clock.p2 = limit->p2.p2_slow;
704 clock.p2 = limit->p2.p2_fast;
707 memset (best_clock, 0, sizeof (*best_clock));
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714 /* m1 is always 0 in IGD */
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
717 for (clock.n = limit->n.min;
718 clock.n <= limit->n.max; clock.n++) {
721 intel_clock(dev, refclk, &clock);
723 if (!intel_PLL_is_valid(crtc, &clock))
726 this_err = abs(clock.dot - target);
727 if (this_err < err) {
736 return (err != target);
741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *best_clock)
745 struct drm_device *dev = crtc->dev;
750 memcpy(&clock, best_clock, sizeof(intel_clock_t));
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754 /* m1 is always 0 in IGD */
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
757 for (clock.n = limit->n.min; clock.n <= limit->n.max;
761 intel_clock(dev, refclk, &clock);
763 if (!intel_PLL_is_valid(crtc, &clock))
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
781 int target, int refclk, intel_clock_t *best_clock)
783 struct drm_device *dev = crtc->dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
788 /* approximately equals target * 0.00488 */
789 int err_most = (target >> 8) + (target >> 10);
792 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
793 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
795 clock.p2 = limit->p2.p2_fast;
797 clock.p2 = limit->p2.p2_slow;
799 if (target < limit->p2.dot_limit)
800 clock.p2 = limit->p2.p2_slow;
802 clock.p2 = limit->p2.p2_fast;
805 memset(best_clock, 0, sizeof(*best_clock));
806 max_n = limit->n.max;
807 /* based on hardware requriment prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirment prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
818 intel_clock(dev, refclk, &clock);
819 if (!intel_PLL_is_valid(crtc, &clock))
821 this_err = abs(clock.dot - target) ;
822 if (this_err < err_most) {
836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock)
839 struct drm_device *dev = crtc->dev;
841 if (target < 200000) {
854 intel_clock(dev, refclk, &clock);
855 memcpy(best_clock, &clock, sizeof(intel_clock_t));
860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
871 /* eDP has only 2 clock choice, no n/m/p setting */
875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
876 return intel_find_pll_igdng_dp(limit, crtc, target,
879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
880 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
882 clock.p2 = limit->p2.p2_fast;
884 clock.p2 = limit->p2.p2_slow;
886 if (target < limit->p2.dot_limit)
887 clock.p2 = limit->p2.p2_slow;
889 clock.p2 = limit->p2.p2_fast;
892 memset(best_clock, 0, sizeof(*best_clock));
893 max_n = limit->n.max;
894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 /* based on hardware requriment prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
897 /* based on hardware requirment prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
904 intel_clock(dev, refclk, &clock);
905 if (!intel_PLL_is_valid(crtc, &clock))
907 this_err = abs((10000 - (target*10000/clock.dot)));
908 if (this_err < err_most) {
913 /* found on first matching */
924 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
926 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
927 int target, int refclk, intel_clock_t *best_clock)
930 if (target < 200000) {
943 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
944 clock.p = (clock.p1 * clock.p2);
945 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
946 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 intel_wait_for_vblank(struct drm_device *dev)
953 /* Wait for 20ms, i.e. one cycle at 50hz. */
957 /* Parameters have changed, update FBC info */
958 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
960 struct drm_device *dev = crtc->dev;
961 struct drm_i915_private *dev_priv = dev->dev_private;
962 struct drm_framebuffer *fb = crtc->fb;
963 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
964 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
967 u32 fbc_ctl, fbc_ctl2;
969 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
971 if (fb->pitch < dev_priv->cfb_pitch)
972 dev_priv->cfb_pitch = fb->pitch;
974 /* FBC_CTL wants 64B units */
975 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
976 dev_priv->cfb_fence = obj_priv->fence_reg;
977 dev_priv->cfb_plane = intel_crtc->plane;
978 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
981 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
982 I915_WRITE(FBC_TAG + (i * 4), 0);
985 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
986 if (obj_priv->tiling_mode != I915_TILING_NONE)
987 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
988 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
989 I915_WRITE(FBC_FENCE_OFF, crtc->y);
992 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
993 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
994 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
995 if (obj_priv->tiling_mode != I915_TILING_NONE)
996 fbc_ctl |= dev_priv->cfb_fence;
997 I915_WRITE(FBC_CONTROL, fbc_ctl);
999 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1000 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1003 void i8xx_disable_fbc(struct drm_device *dev)
1005 struct drm_i915_private *dev_priv = dev->dev_private;
1008 /* Disable compression */
1009 fbc_ctl = I915_READ(FBC_CONTROL);
1010 fbc_ctl &= ~FBC_CTL_EN;
1011 I915_WRITE(FBC_CONTROL, fbc_ctl);
1013 /* Wait for compressing bit to clear */
1014 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1017 intel_wait_for_vblank(dev);
1019 DRM_DEBUG("disabled FBC\n");
1022 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1024 struct drm_device *dev = crtc->dev;
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1027 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1031 * intel_update_fbc - enable/disable FBC as needed
1032 * @crtc: CRTC to point the compressor at
1033 * @mode: mode in use
1035 * Set up the framebuffer compression hardware at mode set time. We
1036 * enable it if possible:
1037 * - plane A only (on pre-965)
1038 * - no pixel mulitply/line duplication
1039 * - no alpha buffer discard
1041 * - framebuffer <= 2048 in width, 1536 in height
1043 * We can't assume that any compression will take place (worst case),
1044 * so the compressed buffer has to be the same size as the uncompressed
1045 * one. It also must reside (along with the line length buffer) in
1048 * We need to enable/disable FBC on a global basis.
1050 static void intel_update_fbc(struct drm_crtc *crtc,
1051 struct drm_display_mode *mode)
1053 struct drm_device *dev = crtc->dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 struct drm_framebuffer *fb = crtc->fb;
1056 struct intel_framebuffer *intel_fb;
1057 struct drm_i915_gem_object *obj_priv;
1058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059 int plane = intel_crtc->plane;
1061 if (!i915_powersave)
1067 intel_fb = to_intel_framebuffer(fb);
1068 obj_priv = intel_fb->obj->driver_private;
1071 * If FBC is already on, we just have to verify that we can
1072 * keep it that way...
1073 * Need to disable if:
1074 * - changing FBC params (stride, fence, mode)
1075 * - new fb is too large to fit in compressed buffer
1076 * - going to an unsupported config (interlace, pixel multiply, etc.)
1078 if (intel_fb->obj->size > dev_priv->cfb_size) {
1079 DRM_DEBUG("framebuffer too large, disabling compression\n");
1082 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1083 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1084 DRM_DEBUG("mode incompatible with compression, disabling\n");
1087 if ((mode->hdisplay > 2048) ||
1088 (mode->vdisplay > 1536)) {
1089 DRM_DEBUG("mode too large for compression, disabling\n");
1092 if (IS_I9XX(dev) && plane != 0) {
1093 DRM_DEBUG("plane not 0, disabling compression\n");
1096 if (obj_priv->tiling_mode != I915_TILING_X) {
1097 DRM_DEBUG("framebuffer not tiled, disabling compression\n");
1101 if (i8xx_fbc_enabled(crtc)) {
1102 /* We can re-enable it in this case, but need to update pitch */
1103 if (fb->pitch > dev_priv->cfb_pitch)
1104 i8xx_disable_fbc(dev);
1105 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1106 i8xx_disable_fbc(dev);
1107 if (plane != dev_priv->cfb_plane)
1108 i8xx_disable_fbc(dev);
1111 if (!i8xx_fbc_enabled(crtc)) {
1112 /* Now try to turn it back on if possible */
1113 i8xx_enable_fbc(crtc, 500);
1119 DRM_DEBUG("unsupported config, disabling FBC\n");
1120 /* Multiple disables should be harmless */
1121 if (i8xx_fbc_enabled(crtc))
1122 i8xx_disable_fbc(dev);
1126 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1127 struct drm_framebuffer *old_fb)
1129 struct drm_device *dev = crtc->dev;
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 struct drm_i915_master_private *master_priv;
1132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1133 struct intel_framebuffer *intel_fb;
1134 struct drm_i915_gem_object *obj_priv;
1135 struct drm_gem_object *obj;
1136 int pipe = intel_crtc->pipe;
1137 int plane = intel_crtc->plane;
1138 unsigned long Start, Offset;
1139 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1140 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1141 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1142 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1143 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1144 u32 dspcntr, alignment;
1149 DRM_DEBUG("No FB bound\n");
1158 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1162 intel_fb = to_intel_framebuffer(crtc->fb);
1163 obj = intel_fb->obj;
1164 obj_priv = obj->driver_private;
1166 switch (obj_priv->tiling_mode) {
1167 case I915_TILING_NONE:
1168 alignment = 64 * 1024;
1171 /* pin() will align the object as required by fence */
1175 /* FIXME: Is this true? */
1176 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1182 mutex_lock(&dev->struct_mutex);
1183 ret = i915_gem_object_pin(obj, alignment);
1185 mutex_unlock(&dev->struct_mutex);
1189 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1191 i915_gem_object_unpin(obj);
1192 mutex_unlock(&dev->struct_mutex);
1196 /* Pre-i965 needs to install a fence for tiled scan-out */
1197 if (!IS_I965G(dev) &&
1198 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1199 obj_priv->tiling_mode != I915_TILING_NONE) {
1200 ret = i915_gem_object_get_fence_reg(obj);
1202 i915_gem_object_unpin(obj);
1203 mutex_unlock(&dev->struct_mutex);
1208 dspcntr = I915_READ(dspcntr_reg);
1209 /* Mask out pixel format bits in case we change it */
1210 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1211 switch (crtc->fb->bits_per_pixel) {
1213 dspcntr |= DISPPLANE_8BPP;
1216 if (crtc->fb->depth == 15)
1217 dspcntr |= DISPPLANE_15_16BPP;
1219 dspcntr |= DISPPLANE_16BPP;
1223 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1226 DRM_ERROR("Unknown color depth\n");
1227 i915_gem_object_unpin(obj);
1228 mutex_unlock(&dev->struct_mutex);
1231 if (IS_I965G(dev)) {
1232 if (obj_priv->tiling_mode != I915_TILING_NONE)
1233 dspcntr |= DISPPLANE_TILED;
1235 dspcntr &= ~DISPPLANE_TILED;
1240 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1242 I915_WRITE(dspcntr_reg, dspcntr);
1244 Start = obj_priv->gtt_offset;
1245 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1247 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1248 I915_WRITE(dspstride, crtc->fb->pitch);
1249 if (IS_I965G(dev)) {
1250 I915_WRITE(dspbase, Offset);
1252 I915_WRITE(dspsurf, Start);
1254 I915_WRITE(dsptileoff, (y << 16) | x);
1256 I915_WRITE(dspbase, Start + Offset);
1260 intel_wait_for_vblank(dev);
1263 intel_fb = to_intel_framebuffer(old_fb);
1264 obj_priv = intel_fb->obj->driver_private;
1265 i915_gem_object_unpin(intel_fb->obj);
1267 intel_increase_pllclock(crtc, true);
1269 mutex_unlock(&dev->struct_mutex);
1271 if (!dev->primary->master)
1274 master_priv = dev->primary->master->driver_priv;
1275 if (!master_priv->sarea_priv)
1279 master_priv->sarea_priv->pipeB_x = x;
1280 master_priv->sarea_priv->pipeB_y = y;
1282 master_priv->sarea_priv->pipeA_x = x;
1283 master_priv->sarea_priv->pipeA_y = y;
1286 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1287 intel_update_fbc(crtc, &crtc->mode);
1292 /* Disable the VGA plane that we never use */
1293 static void i915_disable_vga (struct drm_device *dev)
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1300 vga_reg = CPU_VGACNTRL;
1304 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1307 I915_WRITE8(VGA_SR_INDEX, 1);
1308 sr1 = I915_READ8(VGA_SR_DATA);
1309 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1312 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1315 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1317 struct drm_device *dev = crtc->dev;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1322 dpa_ctl = I915_READ(DP_A);
1323 dpa_ctl &= ~DP_PLL_ENABLE;
1324 I915_WRITE(DP_A, dpa_ctl);
1327 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1329 struct drm_device *dev = crtc->dev;
1330 struct drm_i915_private *dev_priv = dev->dev_private;
1333 dpa_ctl = I915_READ(DP_A);
1334 dpa_ctl |= DP_PLL_ENABLE;
1335 I915_WRITE(DP_A, dpa_ctl);
1340 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1342 struct drm_device *dev = crtc->dev;
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1346 DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1347 dpa_ctl = I915_READ(DP_A);
1348 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1350 if (clock < 200000) {
1352 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1353 /* workaround for 160Mhz:
1354 1) program 0x4600c bits 15:0 = 0x8124
1355 2) program 0x46010 bit 0 = 1
1356 3) program 0x46034 bit 24 = 1
1357 4) program 0x64000 bit 14 = 1
1359 temp = I915_READ(0x4600c);
1361 I915_WRITE(0x4600c, temp | 0x8124);
1363 temp = I915_READ(0x46010);
1364 I915_WRITE(0x46010, temp | 1);
1366 temp = I915_READ(0x46034);
1367 I915_WRITE(0x46034, temp | (1 << 24));
1369 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1371 I915_WRITE(DP_A, dpa_ctl);
1376 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1378 struct drm_device *dev = crtc->dev;
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1381 int pipe = intel_crtc->pipe;
1382 int plane = intel_crtc->plane;
1383 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1384 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1385 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1386 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1387 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1388 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1389 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1390 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1391 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1392 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1393 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1394 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1395 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1396 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1397 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1398 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1399 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1400 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1401 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1402 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1403 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1404 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1405 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1407 int tries = 5, j, n;
1409 /* XXX: When our outputs are all unaware of DPMS modes other than off
1410 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1413 case DRM_MODE_DPMS_ON:
1414 case DRM_MODE_DPMS_STANDBY:
1415 case DRM_MODE_DPMS_SUSPEND:
1416 DRM_DEBUG("crtc %d dpms on\n", pipe);
1418 /* enable eDP PLL */
1419 igdng_enable_pll_edp(crtc);
1421 /* enable PCH DPLL */
1422 temp = I915_READ(pch_dpll_reg);
1423 if ((temp & DPLL_VCO_ENABLE) == 0) {
1424 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1425 I915_READ(pch_dpll_reg);
1428 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1429 temp = I915_READ(fdi_rx_reg);
1430 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1432 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1433 I915_READ(fdi_rx_reg);
1436 /* Enable CPU FDI TX PLL, always on for IGDNG */
1437 temp = I915_READ(fdi_tx_reg);
1438 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1439 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1440 I915_READ(fdi_tx_reg);
1445 /* Enable CPU pipe */
1446 temp = I915_READ(pipeconf_reg);
1447 if ((temp & PIPEACONF_ENABLE) == 0) {
1448 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1449 I915_READ(pipeconf_reg);
1453 /* configure and enable CPU plane */
1454 temp = I915_READ(dspcntr_reg);
1455 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1456 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1457 /* Flush the plane changes */
1458 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1462 /* enable CPU FDI TX and PCH FDI RX */
1463 temp = I915_READ(fdi_tx_reg);
1464 temp |= FDI_TX_ENABLE;
1465 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1466 temp &= ~FDI_LINK_TRAIN_NONE;
1467 temp |= FDI_LINK_TRAIN_PATTERN_1;
1468 I915_WRITE(fdi_tx_reg, temp);
1469 I915_READ(fdi_tx_reg);
1471 temp = I915_READ(fdi_rx_reg);
1472 temp &= ~FDI_LINK_TRAIN_NONE;
1473 temp |= FDI_LINK_TRAIN_PATTERN_1;
1474 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1475 I915_READ(fdi_rx_reg);
1480 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1482 temp = I915_READ(fdi_rx_imr_reg);
1483 temp &= ~FDI_RX_SYMBOL_LOCK;
1484 temp &= ~FDI_RX_BIT_LOCK;
1485 I915_WRITE(fdi_rx_imr_reg, temp);
1486 I915_READ(fdi_rx_imr_reg);
1489 temp = I915_READ(fdi_rx_iir_reg);
1490 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1492 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1493 for (j = 0; j < tries; j++) {
1494 temp = I915_READ(fdi_rx_iir_reg);
1495 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1496 if (temp & FDI_RX_BIT_LOCK)
1501 I915_WRITE(fdi_rx_iir_reg,
1502 temp | FDI_RX_BIT_LOCK);
1504 DRM_DEBUG("train 1 fail\n");
1506 I915_WRITE(fdi_rx_iir_reg,
1507 temp | FDI_RX_BIT_LOCK);
1508 DRM_DEBUG("train 1 ok 2!\n");
1510 temp = I915_READ(fdi_tx_reg);
1511 temp &= ~FDI_LINK_TRAIN_NONE;
1512 temp |= FDI_LINK_TRAIN_PATTERN_2;
1513 I915_WRITE(fdi_tx_reg, temp);
1515 temp = I915_READ(fdi_rx_reg);
1516 temp &= ~FDI_LINK_TRAIN_NONE;
1517 temp |= FDI_LINK_TRAIN_PATTERN_2;
1518 I915_WRITE(fdi_rx_reg, temp);
1522 temp = I915_READ(fdi_rx_iir_reg);
1523 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1525 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1526 for (j = 0; j < tries; j++) {
1527 temp = I915_READ(fdi_rx_iir_reg);
1528 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1529 if (temp & FDI_RX_SYMBOL_LOCK)
1534 I915_WRITE(fdi_rx_iir_reg,
1535 temp | FDI_RX_SYMBOL_LOCK);
1536 DRM_DEBUG("train 2 ok 1!\n");
1538 DRM_DEBUG("train 2 fail\n");
1540 I915_WRITE(fdi_rx_iir_reg,
1541 temp | FDI_RX_SYMBOL_LOCK);
1542 DRM_DEBUG("train 2 ok 2!\n");
1544 DRM_DEBUG("train done\n");
1546 /* set transcoder timing */
1547 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1548 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1549 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1551 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1552 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1553 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1555 /* enable PCH transcoder */
1556 temp = I915_READ(transconf_reg);
1557 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1558 I915_READ(transconf_reg);
1560 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1565 temp = I915_READ(fdi_tx_reg);
1566 temp &= ~FDI_LINK_TRAIN_NONE;
1567 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1568 FDI_TX_ENHANCE_FRAME_ENABLE);
1569 I915_READ(fdi_tx_reg);
1571 temp = I915_READ(fdi_rx_reg);
1572 temp &= ~FDI_LINK_TRAIN_NONE;
1573 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1574 FDI_RX_ENHANCE_FRAME_ENABLE);
1575 I915_READ(fdi_rx_reg);
1577 /* wait one idle pattern time */
1582 intel_crtc_load_lut(crtc);
1585 case DRM_MODE_DPMS_OFF:
1586 DRM_DEBUG("crtc %d dpms off\n", pipe);
1588 i915_disable_vga(dev);
1590 /* Disable display plane */
1591 temp = I915_READ(dspcntr_reg);
1592 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1593 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1594 /* Flush the plane changes */
1595 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1596 I915_READ(dspbase_reg);
1599 /* disable cpu pipe, disable after all planes disabled */
1600 temp = I915_READ(pipeconf_reg);
1601 if ((temp & PIPEACONF_ENABLE) != 0) {
1602 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1603 I915_READ(pipeconf_reg);
1605 /* wait for cpu pipe off, pipe state */
1606 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1612 DRM_DEBUG("pipe %d off delay\n", pipe);
1617 DRM_DEBUG("crtc %d is disabled\n", pipe);
1620 igdng_disable_pll_edp(crtc);
1623 /* disable CPU FDI tx and PCH FDI rx */
1624 temp = I915_READ(fdi_tx_reg);
1625 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1626 I915_READ(fdi_tx_reg);
1628 temp = I915_READ(fdi_rx_reg);
1629 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1630 I915_READ(fdi_rx_reg);
1634 /* still set train pattern 1 */
1635 temp = I915_READ(fdi_tx_reg);
1636 temp &= ~FDI_LINK_TRAIN_NONE;
1637 temp |= FDI_LINK_TRAIN_PATTERN_1;
1638 I915_WRITE(fdi_tx_reg, temp);
1640 temp = I915_READ(fdi_rx_reg);
1641 temp &= ~FDI_LINK_TRAIN_NONE;
1642 temp |= FDI_LINK_TRAIN_PATTERN_1;
1643 I915_WRITE(fdi_rx_reg, temp);
1647 /* disable PCH transcoder */
1648 temp = I915_READ(transconf_reg);
1649 if ((temp & TRANS_ENABLE) != 0) {
1650 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1651 I915_READ(transconf_reg);
1653 /* wait for PCH transcoder off, transcoder state */
1654 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1660 DRM_DEBUG("transcoder %d off delay\n", pipe);
1666 /* disable PCH DPLL */
1667 temp = I915_READ(pch_dpll_reg);
1668 if ((temp & DPLL_VCO_ENABLE) != 0) {
1669 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1670 I915_READ(pch_dpll_reg);
1673 temp = I915_READ(fdi_rx_reg);
1674 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1675 temp &= ~FDI_SEL_PCDCLK;
1676 temp &= ~FDI_RX_PLL_ENABLE;
1677 I915_WRITE(fdi_rx_reg, temp);
1678 I915_READ(fdi_rx_reg);
1681 /* Disable CPU FDI TX PLL */
1682 temp = I915_READ(fdi_tx_reg);
1683 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1684 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1685 I915_READ(fdi_tx_reg);
1690 temp = I915_READ(pf_ctl_reg);
1691 if ((temp & PF_ENABLE) != 0) {
1692 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1693 I915_READ(pf_ctl_reg);
1695 I915_WRITE(pf_win_size, 0);
1697 /* Wait for the clocks to turn off. */
1703 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1705 struct drm_device *dev = crtc->dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1708 int pipe = intel_crtc->pipe;
1709 int plane = intel_crtc->plane;
1710 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1711 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1712 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1713 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1716 /* XXX: When our outputs are all unaware of DPMS modes other than off
1717 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1720 case DRM_MODE_DPMS_ON:
1721 case DRM_MODE_DPMS_STANDBY:
1722 case DRM_MODE_DPMS_SUSPEND:
1723 /* Enable the DPLL */
1724 temp = I915_READ(dpll_reg);
1725 if ((temp & DPLL_VCO_ENABLE) == 0) {
1726 I915_WRITE(dpll_reg, temp);
1727 I915_READ(dpll_reg);
1728 /* Wait for the clocks to stabilize. */
1730 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1731 I915_READ(dpll_reg);
1732 /* Wait for the clocks to stabilize. */
1734 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1735 I915_READ(dpll_reg);
1736 /* Wait for the clocks to stabilize. */
1740 /* Enable the pipe */
1741 temp = I915_READ(pipeconf_reg);
1742 if ((temp & PIPEACONF_ENABLE) == 0)
1743 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1745 /* Enable the plane */
1746 temp = I915_READ(dspcntr_reg);
1747 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1748 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1749 /* Flush the plane changes */
1750 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1753 intel_crtc_load_lut(crtc);
1755 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
1756 intel_update_fbc(crtc, &crtc->mode);
1758 /* Give the overlay scaler a chance to enable if it's on this pipe */
1759 //intel_crtc_dpms_video(crtc, true); TODO
1760 intel_update_watermarks(dev);
1762 case DRM_MODE_DPMS_OFF:
1763 intel_update_watermarks(dev);
1764 /* Give the overlay scaler a chance to disable if it's on this pipe */
1765 //intel_crtc_dpms_video(crtc, FALSE); TODO
1767 if (dev_priv->cfb_plane == plane)
1768 i8xx_disable_fbc(dev);
1770 /* Disable the VGA plane that we never use */
1771 i915_disable_vga(dev);
1773 /* Disable display plane */
1774 temp = I915_READ(dspcntr_reg);
1775 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1776 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1777 /* Flush the plane changes */
1778 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1779 I915_READ(dspbase_reg);
1782 if (!IS_I9XX(dev)) {
1783 /* Wait for vblank for the disable to take effect */
1784 intel_wait_for_vblank(dev);
1787 /* Next, disable display pipes */
1788 temp = I915_READ(pipeconf_reg);
1789 if ((temp & PIPEACONF_ENABLE) != 0) {
1790 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1791 I915_READ(pipeconf_reg);
1794 /* Wait for vblank for the disable to take effect. */
1795 intel_wait_for_vblank(dev);
1797 temp = I915_READ(dpll_reg);
1798 if ((temp & DPLL_VCO_ENABLE) != 0) {
1799 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1800 I915_READ(dpll_reg);
1803 /* Wait for the clocks to turn off. */
1810 * Sets the power management mode of the pipe and plane.
1812 * This code should probably grow support for turning the cursor off and back
1813 * on appropriately at the same time as we're turning the pipe off/on.
1815 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1817 struct drm_device *dev = crtc->dev;
1818 struct drm_i915_master_private *master_priv;
1819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1820 int pipe = intel_crtc->pipe;
1824 igdng_crtc_dpms(crtc, mode);
1826 i9xx_crtc_dpms(crtc, mode);
1828 intel_crtc->dpms_mode = mode;
1830 if (!dev->primary->master)
1833 master_priv = dev->primary->master->driver_priv;
1834 if (!master_priv->sarea_priv)
1837 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1841 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1842 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1845 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1846 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1849 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1854 static void intel_crtc_prepare (struct drm_crtc *crtc)
1856 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1857 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1860 static void intel_crtc_commit (struct drm_crtc *crtc)
1862 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1863 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1866 void intel_encoder_prepare (struct drm_encoder *encoder)
1868 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1869 /* lvds has its own version of prepare see intel_lvds_prepare */
1870 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1873 void intel_encoder_commit (struct drm_encoder *encoder)
1875 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1876 /* lvds has its own version of commit see intel_lvds_commit */
1877 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1880 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1881 struct drm_display_mode *mode,
1882 struct drm_display_mode *adjusted_mode)
1884 struct drm_device *dev = crtc->dev;
1885 if (IS_IGDNG(dev)) {
1886 /* FDI link clock is fixed at 2.7G */
1887 if (mode->clock * 3 > 27000 * 4)
1888 return MODE_CLOCK_HIGH;
1894 /** Returns the core display clock speed for i830 - i945 */
1895 static int intel_get_core_clock_speed(struct drm_device *dev)
1898 /* Core clock values taken from the published datasheets.
1899 * The 830 may go up to 166 Mhz, which we should check.
1903 else if (IS_I915G(dev))
1905 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1907 else if (IS_I915GM(dev)) {
1910 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1912 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1915 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1916 case GC_DISPLAY_CLOCK_333_MHZ:
1919 case GC_DISPLAY_CLOCK_190_200_MHZ:
1923 } else if (IS_I865G(dev))
1925 else if (IS_I855(dev)) {
1927 /* Assume that the hardware is in the high speed state. This
1928 * should be the default.
1930 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1931 case GC_CLOCK_133_200:
1932 case GC_CLOCK_100_200:
1934 case GC_CLOCK_166_250:
1936 case GC_CLOCK_100_133:
1939 } else /* 852, 830 */
1942 return 0; /* Silence gcc warning */
1946 * Return the pipe currently connected to the panel fitter,
1947 * or -1 if the panel fitter is not present or not in use
1949 static int intel_panel_fitter_pipe (struct drm_device *dev)
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1954 /* i830 doesn't have a panel fitter */
1958 pfit_control = I915_READ(PFIT_CONTROL);
1960 /* See if the panel fitter is in use */
1961 if ((pfit_control & PFIT_ENABLE) == 0)
1964 /* 965 can place panel fitter on either pipe */
1966 return (pfit_control >> 29) & 0x3;
1968 /* older chips can only use pipe 1 */
1981 fdi_reduce_ratio(u32 *num, u32 *den)
1983 while (*num > 0xffffff || *den > 0xffffff) {
1989 #define DATA_N 0x800000
1990 #define LINK_N 0x80000
1993 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1994 int pixel_clock, int link_clock,
1995 struct fdi_m_n *m_n)
1999 m_n->tu = 64; /* default size */
2001 temp = (u64) DATA_N * pixel_clock;
2002 temp = div_u64(temp, link_clock);
2003 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
2004 m_n->gmch_n = DATA_N;
2005 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2007 temp = (u64) LINK_N * pixel_clock;
2008 m_n->link_m = div_u64(temp, link_clock);
2009 m_n->link_n = LINK_N;
2010 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2014 struct intel_watermark_params {
2015 unsigned long fifo_size;
2016 unsigned long max_wm;
2017 unsigned long default_wm;
2018 unsigned long guard_size;
2019 unsigned long cacheline_size;
2022 /* IGD has different values for various configs */
2023 static struct intel_watermark_params igd_display_wm = {
2030 static struct intel_watermark_params igd_display_hplloff_wm = {
2037 static struct intel_watermark_params igd_cursor_wm = {
2041 IGD_CURSOR_GUARD_WM,
2044 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2048 IGD_CURSOR_GUARD_WM,
2051 static struct intel_watermark_params i945_wm_info = {
2058 static struct intel_watermark_params i915_wm_info = {
2065 static struct intel_watermark_params i855_wm_info = {
2072 static struct intel_watermark_params i830_wm_info = {
2081 * intel_calculate_wm - calculate watermark level
2082 * @clock_in_khz: pixel clock
2083 * @wm: chip FIFO params
2084 * @pixel_size: display pixel size
2085 * @latency_ns: memory latency for the platform
2087 * Calculate the watermark level (the level at which the display plane will
2088 * start fetching from memory again). Each chip has a different display
2089 * FIFO size and allocation, so the caller needs to figure that out and pass
2090 * in the correct intel_watermark_params structure.
2092 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2093 * on the pixel size. When it reaches the watermark level, it'll start
2094 * fetching FIFO line sized based chunks from memory until the FIFO fills
2095 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2096 * will occur, and a display engine hang could result.
2098 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2099 struct intel_watermark_params *wm,
2101 unsigned long latency_ns)
2103 long entries_required, wm_size;
2105 entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
2106 entries_required /= wm->cacheline_size;
2108 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
2110 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2112 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
2114 /* Don't promote wm_size to unsigned... */
2115 if (wm_size > (long)wm->max_wm)
2116 wm_size = wm->max_wm;
2118 wm_size = wm->default_wm;
2122 struct cxsr_latency {
2124 unsigned long fsb_freq;
2125 unsigned long mem_freq;
2126 unsigned long display_sr;
2127 unsigned long display_hpll_disable;
2128 unsigned long cursor_sr;
2129 unsigned long cursor_hpll_disable;
2132 static struct cxsr_latency cxsr_latency_table[] = {
2133 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2134 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2135 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2137 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2138 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2139 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2141 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2142 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2143 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2145 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2146 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2147 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2149 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2150 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2151 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2153 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2154 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2155 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2158 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2162 struct cxsr_latency *latency;
2164 if (fsb == 0 || mem == 0)
2167 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2168 latency = &cxsr_latency_table[i];
2169 if (is_desktop == latency->is_desktop &&
2170 fsb == latency->fsb_freq && mem == latency->mem_freq)
2173 if (i >= ARRAY_SIZE(cxsr_latency_table)) {
2174 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2180 static void igd_disable_cxsr(struct drm_device *dev)
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2185 /* deactivate cxsr */
2186 reg = I915_READ(DSPFW3);
2187 reg &= ~(IGD_SELF_REFRESH_EN);
2188 I915_WRITE(DSPFW3, reg);
2189 DRM_INFO("Big FIFO is disabled\n");
2192 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2198 struct cxsr_latency *latency;
2200 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2201 dev_priv->mem_freq);
2203 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2204 igd_disable_cxsr(dev);
2209 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2210 latency->display_sr);
2211 reg = I915_READ(DSPFW1);
2214 I915_WRITE(DSPFW1, reg);
2215 DRM_DEBUG("DSPFW1 register is %x\n", reg);
2218 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2219 latency->cursor_sr);
2220 reg = I915_READ(DSPFW3);
2221 reg &= ~(0x3f << 24);
2222 reg |= (wm & 0x3f) << 24;
2223 I915_WRITE(DSPFW3, reg);
2225 /* Display HPLL off SR */
2226 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2227 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2228 reg = I915_READ(DSPFW3);
2231 I915_WRITE(DSPFW3, reg);
2233 /* cursor HPLL off SR */
2234 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2235 latency->cursor_hpll_disable);
2236 reg = I915_READ(DSPFW3);
2237 reg &= ~(0x3f << 16);
2238 reg |= (wm & 0x3f) << 16;
2239 I915_WRITE(DSPFW3, reg);
2240 DRM_DEBUG("DSPFW3 register is %x\n", reg);
2243 reg = I915_READ(DSPFW3);
2244 reg |= IGD_SELF_REFRESH_EN;
2245 I915_WRITE(DSPFW3, reg);
2247 DRM_INFO("Big FIFO is enabled\n");
2253 * Latency for FIFO fetches is dependent on several factors:
2254 * - memory configuration (speed, channels)
2256 * - current MCH state
2257 * It can be fairly high in some situations, so here we assume a fairly
2258 * pessimal value. It's a tradeoff between extra memory fetches (if we
2259 * set this value too high, the FIFO will fetch frequently to stay full)
2260 * and power consumption (set it too low to save power and we might see
2261 * FIFO underruns and display "flicker").
2263 * A value of 5us seems to be a good balance; safe for very low end
2264 * platforms but not overly aggressive on lower latency configs.
2266 const static int latency_ns = 5000;
2268 static int intel_get_fifo_size(struct drm_device *dev, int plane)
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 uint32_t dsparb = I915_READ(DSPARB);
2276 size = dsparb & 0x7f;
2278 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2280 } else if (IS_I85X(dev)) {
2282 size = dsparb & 0x1ff;
2284 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2286 size >>= 1; /* Convert to cachelines */
2287 } else if (IS_845G(dev)) {
2288 size = dsparb & 0x7f;
2289 size >>= 2; /* Convert to cachelines */
2291 size = dsparb & 0x7f;
2292 size >>= 1; /* Convert to cachelines */
2295 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2301 static void g4x_update_wm(struct drm_device *dev)
2303 struct drm_i915_private *dev_priv = dev->dev_private;
2304 u32 fw_blc_self = I915_READ(FW_BLC_SELF);
2307 fw_blc_self |= FW_BLC_SELF_EN;
2309 fw_blc_self &= ~FW_BLC_SELF_EN;
2310 I915_WRITE(FW_BLC_SELF, fw_blc_self);
2313 static void i965_update_wm(struct drm_device *dev)
2315 struct drm_i915_private *dev_priv = dev->dev_private;
2317 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2319 /* 965 has limitations... */
2320 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2321 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2324 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2325 int planeb_clock, int sr_hdisplay, int pixel_size)
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2330 int total_size, cacheline_size, cwm, srwm = 1;
2331 int planea_wm, planeb_wm;
2332 struct intel_watermark_params planea_params, planeb_params;
2333 unsigned long line_time_us;
2334 int sr_clock, sr_entries = 0;
2336 /* Create copies of the base settings for each pipe */
2337 if (IS_I965GM(dev) || IS_I945GM(dev))
2338 planea_params = planeb_params = i945_wm_info;
2339 else if (IS_I9XX(dev))
2340 planea_params = planeb_params = i915_wm_info;
2342 planea_params = planeb_params = i855_wm_info;
2344 /* Grab a couple of global values before we overwrite them */
2345 total_size = planea_params.fifo_size;
2346 cacheline_size = planea_params.cacheline_size;
2348 /* Update per-plane FIFO sizes */
2349 planea_params.fifo_size = intel_get_fifo_size(dev, 0);
2350 planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
2352 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2353 pixel_size, latency_ns);
2354 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2355 pixel_size, latency_ns);
2356 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2359 * Overlay gets an aggressive default since video jitter is bad.
2363 /* Calc sr entries for one plane configs */
2364 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2365 (!planea_clock || !planeb_clock)) {
2366 /* self-refresh has much higher latency */
2367 const static int sr_latency_ns = 6000;
2369 sr_clock = planea_clock ? planea_clock : planeb_clock;
2370 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2372 /* Use ns/us then divide to preserve precision */
2373 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2374 pixel_size * sr_hdisplay) / 1000;
2375 sr_entries = roundup(sr_entries / cacheline_size, 1);
2376 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2377 srwm = total_size - sr_entries;
2380 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2383 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2384 planea_wm, planeb_wm, cwm, srwm);
2386 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2387 fwater_hi = (cwm & 0x1f);
2389 /* Set request length to 8 cachelines per fetch */
2390 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2391 fwater_hi = fwater_hi | (1 << 8);
2393 I915_WRITE(FW_BLC, fwater_lo);
2394 I915_WRITE(FW_BLC2, fwater_hi);
2397 static void i830_update_wm(struct drm_device *dev, int planea_clock,
2400 struct drm_i915_private *dev_priv = dev->dev_private;
2401 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2404 i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2406 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2407 pixel_size, latency_ns);
2408 fwater_lo |= (3<<8) | planea_wm;
2410 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2412 I915_WRITE(FW_BLC, fwater_lo);
2416 * intel_update_watermarks - update FIFO watermark values based on current modes
2418 * Calculate watermark values for the various WM regs based on current mode
2419 * and plane configuration.
2421 * There are several cases to deal with here:
2422 * - normal (i.e. non-self-refresh)
2423 * - self-refresh (SR) mode
2424 * - lines are large relative to FIFO size (buffer can hold up to 2)
2425 * - lines are small relative to FIFO size (buffer can hold more than 2
2426 * lines), so need to account for TLB latency
2428 * The normal calculation is:
2429 * watermark = dotclock * bytes per pixel * latency
2430 * where latency is platform & configuration dependent (we assume pessimal
2433 * The SR calculation is:
2434 * watermark = (trunc(latency/line time)+1) * surface width *
2437 * line time = htotal / dotclock
2438 * and latency is assumed to be high, as above.
2440 * The final value programmed to the register should always be rounded up,
2441 * and include an extra 2 entries to account for clock crossings.
2443 * We don't use the sprite, so we can ignore that. And on Crestline we have
2444 * to set the non-SR watermarks to 8.
2446 static void intel_update_watermarks(struct drm_device *dev)
2448 struct drm_crtc *crtc;
2449 struct intel_crtc *intel_crtc;
2450 int sr_hdisplay = 0;
2451 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2452 int enabled = 0, pixel_size = 0;
2454 /* Get the clock config from both planes */
2455 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2456 intel_crtc = to_intel_crtc(crtc);
2457 if (crtc->enabled) {
2459 if (intel_crtc->plane == 0) {
2460 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2461 intel_crtc->pipe, crtc->mode.clock);
2462 planea_clock = crtc->mode.clock;
2464 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2465 intel_crtc->pipe, crtc->mode.clock);
2466 planeb_clock = crtc->mode.clock;
2468 sr_hdisplay = crtc->mode.hdisplay;
2469 sr_clock = crtc->mode.clock;
2471 pixel_size = crtc->fb->bits_per_pixel / 8;
2473 pixel_size = 4; /* by default */
2480 /* Single plane configs can enable self refresh */
2481 if (enabled == 1 && IS_IGD(dev))
2482 igd_enable_cxsr(dev, sr_clock, pixel_size);
2483 else if (IS_IGD(dev))
2484 igd_disable_cxsr(dev);
2488 else if (IS_I965G(dev))
2489 i965_update_wm(dev);
2490 else if (IS_I9XX(dev) || IS_MOBILE(dev))
2491 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2494 i830_update_wm(dev, planea_clock, pixel_size);
2497 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2498 struct drm_display_mode *mode,
2499 struct drm_display_mode *adjusted_mode,
2501 struct drm_framebuffer *old_fb)
2503 struct drm_device *dev = crtc->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506 int pipe = intel_crtc->pipe;
2507 int plane = intel_crtc->plane;
2508 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2509 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2510 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2511 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2512 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2513 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2514 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2515 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2516 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2517 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2518 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2519 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2520 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2521 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2522 int refclk, num_outputs = 0;
2523 intel_clock_t clock, reduced_clock;
2524 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2525 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2526 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2527 bool is_edp = false;
2528 struct drm_mode_config *mode_config = &dev->mode_config;
2529 struct drm_connector *connector;
2530 const intel_limit_t *limit;
2532 struct fdi_m_n m_n = {0};
2533 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2534 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2535 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2536 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2537 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2538 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2539 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2540 int lvds_reg = LVDS;
2542 int sdvo_pixel_multiply;
2545 drm_vblank_pre_modeset(dev, pipe);
2547 list_for_each_entry(connector, &mode_config->connector_list, head) {
2548 struct intel_output *intel_output = to_intel_output(connector);
2550 if (!connector->encoder || connector->encoder->crtc != crtc)
2553 switch (intel_output->type) {
2554 case INTEL_OUTPUT_LVDS:
2557 case INTEL_OUTPUT_SDVO:
2558 case INTEL_OUTPUT_HDMI:
2560 if (intel_output->needs_tv_clock)
2563 case INTEL_OUTPUT_DVO:
2566 case INTEL_OUTPUT_TVOUT:
2569 case INTEL_OUTPUT_ANALOG:
2572 case INTEL_OUTPUT_DISPLAYPORT:
2575 case INTEL_OUTPUT_EDP:
2583 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2584 refclk = dev_priv->lvds_ssc_freq * 1000;
2585 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2586 } else if (IS_I9XX(dev)) {
2589 refclk = 120000; /* 120Mhz refclk */
2596 * Returns a set of divisors for the desired target clock with the given
2597 * refclk, or FALSE. The returned values represent the clock equation:
2598 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2600 limit = intel_limit(crtc);
2601 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2603 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2604 drm_vblank_post_modeset(dev, pipe);
2608 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2609 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2610 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2611 (adjusted_mode->clock*3/4),
2616 /* SDVO TV has fixed PLL values depend on its clock range,
2617 this mirrors vbios setting. */
2618 if (is_sdvo && is_tv) {
2619 if (adjusted_mode->clock >= 100000
2620 && adjusted_mode->clock < 140500) {
2626 } else if (adjusted_mode->clock >= 140500
2627 && adjusted_mode->clock <= 200000) {
2637 if (IS_IGDNG(dev)) {
2639 /* eDP doesn't require FDI link, so just set DP M/N
2640 according to current link config */
2642 struct drm_connector *edp;
2643 target_clock = mode->clock;
2644 edp = intel_pipe_get_output(crtc);
2645 intel_edp_link_config(to_intel_output(edp),
2648 /* DP over FDI requires target mode clock
2649 instead of link clock */
2651 target_clock = mode->clock;
2653 target_clock = adjusted_mode->clock;
2657 igdng_compute_m_n(3, lane, target_clock,
2662 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2663 if (has_reduced_clock)
2664 fp2 = (1 << reduced_clock.n) << 16 |
2665 reduced_clock.m1 << 8 | reduced_clock.m2;
2667 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2668 if (has_reduced_clock)
2669 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2674 dpll = DPLL_VGA_MODE_DIS;
2678 dpll |= DPLLB_MODE_LVDS;
2680 dpll |= DPLLB_MODE_DAC_SERIAL;
2682 dpll |= DPLL_DVO_HIGH_SPEED;
2683 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2684 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2685 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2686 else if (IS_IGDNG(dev))
2687 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2690 dpll |= DPLL_DVO_HIGH_SPEED;
2692 /* compute bitmask from p1 value */
2694 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2696 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2699 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2700 if (IS_G4X(dev) && has_reduced_clock)
2701 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2705 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2708 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2711 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2714 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2717 if (IS_I965G(dev) && !IS_IGDNG(dev))
2718 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2721 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2724 dpll |= PLL_P1_DIVIDE_BY_TWO;
2726 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2728 dpll |= PLL_P2_DIVIDE_BY_4;
2732 if (is_sdvo && is_tv)
2733 dpll |= PLL_REF_INPUT_TVCLKINBC;
2735 /* XXX: just matching BIOS for now */
2736 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2738 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2739 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2741 dpll |= PLL_REF_INPUT_DREFCLK;
2743 /* setup pipeconf */
2744 pipeconf = I915_READ(pipeconf_reg);
2746 /* Set up the display plane register */
2747 dspcntr = DISPPLANE_GAMMA_ENABLE;
2749 /* IGDNG's plane is forced to pipe, bit 24 is to
2750 enable color space conversion */
2751 if (!IS_IGDNG(dev)) {
2753 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2755 dspcntr |= DISPPLANE_SEL_PIPE_B;
2758 if (pipe == 0 && !IS_I965G(dev)) {
2759 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2762 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2765 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2766 pipeconf |= PIPEACONF_DOUBLE_WIDE;
2768 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2771 dspcntr |= DISPLAY_PLANE_ENABLE;
2772 pipeconf |= PIPEACONF_ENABLE;
2773 dpll |= DPLL_VCO_ENABLE;
2776 /* Disable the panel fitter if it was on our pipe */
2777 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2778 I915_WRITE(PFIT_CONTROL, 0);
2780 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2781 drm_mode_debug_printmodeline(mode);
2783 /* assign to IGDNG registers */
2784 if (IS_IGDNG(dev)) {
2785 fp_reg = pch_fp_reg;
2786 dpll_reg = pch_dpll_reg;
2790 igdng_disable_pll_edp(crtc);
2791 } else if ((dpll & DPLL_VCO_ENABLE)) {
2792 I915_WRITE(fp_reg, fp);
2793 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2794 I915_READ(dpll_reg);
2798 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2799 * This is an exception to the general rule that mode_set doesn't turn
2806 lvds_reg = PCH_LVDS;
2808 lvds = I915_READ(lvds_reg);
2809 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2810 /* Set the B0-B3 data pairs corresponding to whether we're going to
2811 * set the DPLLs for dual-channel mode or not.
2814 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2816 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2818 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2819 * appropriately here, but we need to look more thoroughly into how
2820 * panels behave in the two modes.
2823 I915_WRITE(lvds_reg, lvds);
2824 I915_READ(lvds_reg);
2827 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2830 I915_WRITE(fp_reg, fp);
2831 I915_WRITE(dpll_reg, dpll);
2832 I915_READ(dpll_reg);
2833 /* Wait for the clocks to stabilize. */
2836 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2838 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2839 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2840 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2842 I915_WRITE(dpll_md_reg, 0);
2844 /* write it again -- the BIOS does, after all */
2845 I915_WRITE(dpll_reg, dpll);
2847 I915_READ(dpll_reg);
2848 /* Wait for the clocks to stabilize. */
2852 if (is_lvds && has_reduced_clock && i915_powersave) {
2853 I915_WRITE(fp_reg + 4, fp2);
2854 intel_crtc->lowfreq_avail = true;
2855 if (HAS_PIPE_CXSR(dev)) {
2856 DRM_DEBUG("enabling CxSR downclocking\n");
2857 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
2860 I915_WRITE(fp_reg + 4, fp);
2861 intel_crtc->lowfreq_avail = false;
2862 if (HAS_PIPE_CXSR(dev)) {
2863 DRM_DEBUG("disabling CxSR downclocking\n");
2864 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
2868 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2869 ((adjusted_mode->crtc_htotal - 1) << 16));
2870 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2871 ((adjusted_mode->crtc_hblank_end - 1) << 16));
2872 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2873 ((adjusted_mode->crtc_hsync_end - 1) << 16));
2874 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2875 ((adjusted_mode->crtc_vtotal - 1) << 16));
2876 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2877 ((adjusted_mode->crtc_vblank_end - 1) << 16));
2878 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2879 ((adjusted_mode->crtc_vsync_end - 1) << 16));
2880 /* pipesrc and dspsize control the size that is scaled from, which should
2881 * always be the user's requested size.
2883 if (!IS_IGDNG(dev)) {
2884 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2885 (mode->hdisplay - 1));
2886 I915_WRITE(dsppos_reg, 0);
2888 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2890 if (IS_IGDNG(dev)) {
2891 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2892 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2893 I915_WRITE(link_m1_reg, m_n.link_m);
2894 I915_WRITE(link_n1_reg, m_n.link_n);
2897 igdng_set_pll_edp(crtc, adjusted_mode->clock);
2899 /* enable FDI RX PLL too */
2900 temp = I915_READ(fdi_rx_reg);
2901 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2906 I915_WRITE(pipeconf_reg, pipeconf);
2907 I915_READ(pipeconf_reg);
2909 intel_wait_for_vblank(dev);
2911 if (IS_IGDNG(dev)) {
2912 /* enable address swizzle for tiling buffer */
2913 temp = I915_READ(DISP_ARB_CTL);
2914 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
2917 I915_WRITE(dspcntr_reg, dspcntr);
2919 /* Flush the plane changes */
2920 ret = intel_pipe_set_base(crtc, x, y, old_fb);
2922 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
2923 intel_update_fbc(crtc, &crtc->mode);
2924 intel_update_watermarks(dev);
2926 drm_vblank_post_modeset(dev, pipe);
2931 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2932 void intel_crtc_load_lut(struct drm_crtc *crtc)
2934 struct drm_device *dev = crtc->dev;
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2937 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2940 /* The clocks have to be on to load the palette. */
2944 /* use legacy palette for IGDNG */
2946 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2949 for (i = 0; i < 256; i++) {
2950 I915_WRITE(palreg + 4 * i,
2951 (intel_crtc->lut_r[i] << 16) |
2952 (intel_crtc->lut_g[i] << 8) |
2953 intel_crtc->lut_b[i]);
2957 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2958 struct drm_file *file_priv,
2960 uint32_t width, uint32_t height)
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 struct drm_gem_object *bo;
2966 struct drm_i915_gem_object *obj_priv;
2967 int pipe = intel_crtc->pipe;
2968 int plane = intel_crtc->plane;
2969 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2970 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2971 uint32_t temp = I915_READ(control);
2977 /* if we want to turn off the cursor ignore width and height */
2979 DRM_DEBUG("cursor off\n");
2980 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2981 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2982 temp |= CURSOR_MODE_DISABLE;
2984 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2988 mutex_lock(&dev->struct_mutex);
2992 /* Currently we only support 64x64 cursors */
2993 if (width != 64 || height != 64) {
2994 DRM_ERROR("we currently only support 64x64 cursors\n");
2998 bo = drm_gem_object_lookup(dev, file_priv, handle);
3002 obj_priv = bo->driver_private;
3004 if (bo->size < width * height * 4) {
3005 DRM_ERROR("buffer is to small\n");
3010 /* we only need to pin inside GTT if cursor is non-phy */
3011 mutex_lock(&dev->struct_mutex);
3012 if (!dev_priv->cursor_needs_physical) {
3013 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3015 DRM_ERROR("failed to pin cursor bo\n");
3018 addr = obj_priv->gtt_offset;
3020 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3022 DRM_ERROR("failed to attach phys object\n");
3025 addr = obj_priv->phys_obj->handle->busaddr;
3029 I915_WRITE(CURSIZE, (height << 12) | width);
3031 /* Hooray for CUR*CNTR differences */
3032 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3033 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3034 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3035 temp |= (pipe << 28); /* Connect to correct pipe */
3037 temp &= ~(CURSOR_FORMAT_MASK);
3038 temp |= CURSOR_ENABLE;
3039 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3043 I915_WRITE(control, temp);
3044 I915_WRITE(base, addr);
3046 if (intel_crtc->cursor_bo) {
3047 if (dev_priv->cursor_needs_physical) {
3048 if (intel_crtc->cursor_bo != bo)
3049 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3051 i915_gem_object_unpin(intel_crtc->cursor_bo);
3052 drm_gem_object_unreference(intel_crtc->cursor_bo);
3055 if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
3056 intel_update_fbc(crtc, &crtc->mode);
3058 mutex_unlock(&dev->struct_mutex);
3060 intel_crtc->cursor_addr = addr;
3061 intel_crtc->cursor_bo = bo;
3065 mutex_lock(&dev->struct_mutex);
3067 drm_gem_object_unreference(bo);
3068 mutex_unlock(&dev->struct_mutex);
3072 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3074 struct drm_device *dev = crtc->dev;
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3077 struct intel_framebuffer *intel_fb;
3078 int pipe = intel_crtc->pipe;
3083 intel_fb = to_intel_framebuffer(crtc->fb);
3084 intel_mark_busy(dev, intel_fb->obj);
3088 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3092 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3096 temp |= x << CURSOR_X_SHIFT;
3097 temp |= y << CURSOR_Y_SHIFT;
3099 adder = intel_crtc->cursor_addr;
3100 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3101 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3106 /** Sets the color ramps on behalf of RandR */
3107 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3108 u16 blue, int regno)
3110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3112 intel_crtc->lut_r[regno] = red >> 8;
3113 intel_crtc->lut_g[regno] = green >> 8;
3114 intel_crtc->lut_b[regno] = blue >> 8;
3117 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3118 u16 *blue, uint32_t size)
3120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3126 for (i = 0; i < 256; i++) {
3127 intel_crtc->lut_r[i] = red[i] >> 8;
3128 intel_crtc->lut_g[i] = green[i] >> 8;
3129 intel_crtc->lut_b[i] = blue[i] >> 8;
3132 intel_crtc_load_lut(crtc);
3136 * Get a pipe with a simple mode set on it for doing load-based monitor
3139 * It will be up to the load-detect code to adjust the pipe as appropriate for
3140 * its requirements. The pipe will be connected to no other outputs.
3142 * Currently this code will only succeed if there is a pipe with no outputs
3143 * configured for it. In the future, it could choose to temporarily disable
3144 * some outputs to free up a pipe for its use.
3146 * \return crtc, or NULL if no pipes are available.
3149 /* VESA 640x480x72Hz mode to set on the pipe */
3150 static struct drm_display_mode load_detect_mode = {
3151 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3152 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3155 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3156 struct drm_display_mode *mode,
3159 struct intel_crtc *intel_crtc;
3160 struct drm_crtc *possible_crtc;
3161 struct drm_crtc *supported_crtc =NULL;
3162 struct drm_encoder *encoder = &intel_output->enc;
3163 struct drm_crtc *crtc = NULL;
3164 struct drm_device *dev = encoder->dev;
3165 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3166 struct drm_crtc_helper_funcs *crtc_funcs;
3170 * Algorithm gets a little messy:
3171 * - if the connector already has an assigned crtc, use it (but make
3172 * sure it's on first)
3173 * - try to find the first unused crtc that can drive this connector,
3174 * and use that if we find one
3175 * - if there are no unused crtcs available, try to use the first
3176 * one we found that supports the connector
3179 /* See if we already have a CRTC for this connector */
3180 if (encoder->crtc) {
3181 crtc = encoder->crtc;
3182 /* Make sure the crtc and connector are running */
3183 intel_crtc = to_intel_crtc(crtc);
3184 *dpms_mode = intel_crtc->dpms_mode;
3185 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3186 crtc_funcs = crtc->helper_private;
3187 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3188 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3193 /* Find an unused one (if possible) */
3194 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3196 if (!(encoder->possible_crtcs & (1 << i)))
3198 if (!possible_crtc->enabled) {
3199 crtc = possible_crtc;
3202 if (!supported_crtc)
3203 supported_crtc = possible_crtc;
3207 * If we didn't find an unused CRTC, don't use any.
3213 encoder->crtc = crtc;
3214 intel_output->base.encoder = encoder;
3215 intel_output->load_detect_temp = true;
3217 intel_crtc = to_intel_crtc(crtc);
3218 *dpms_mode = intel_crtc->dpms_mode;
3220 if (!crtc->enabled) {
3222 mode = &load_detect_mode;
3223 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3225 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3226 crtc_funcs = crtc->helper_private;
3227 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3230 /* Add this connector to the crtc */
3231 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3232 encoder_funcs->commit(encoder);
3234 /* let the connector get through one full cycle before testing */
3235 intel_wait_for_vblank(dev);
3240 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3242 struct drm_encoder *encoder = &intel_output->enc;
3243 struct drm_device *dev = encoder->dev;
3244 struct drm_crtc *crtc = encoder->crtc;
3245 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3246 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3248 if (intel_output->load_detect_temp) {
3249 encoder->crtc = NULL;
3250 intel_output->base.encoder = NULL;
3251 intel_output->load_detect_temp = false;
3252 crtc->enabled = drm_helper_crtc_in_use(crtc);
3253 drm_helper_disable_unused_functions(dev);
3256 /* Switch crtc and output back off if necessary */
3257 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3258 if (encoder->crtc == crtc)
3259 encoder_funcs->dpms(encoder, dpms_mode);
3260 crtc_funcs->dpms(crtc, dpms_mode);
3264 /* Returns the clock of the currently programmed mode of the given pipe. */
3265 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269 int pipe = intel_crtc->pipe;
3270 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3272 intel_clock_t clock;
3274 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3275 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3277 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3279 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3281 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3282 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3284 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3285 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3290 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3291 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3293 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3294 DPLL_FPA01_P1_POST_DIV_SHIFT);
3296 switch (dpll & DPLL_MODE_MASK) {
3297 case DPLLB_MODE_DAC_SERIAL:
3298 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3301 case DPLLB_MODE_LVDS:
3302 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3306 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3307 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3311 /* XXX: Handle the 100Mhz refclk */
3312 intel_clock(dev, 96000, &clock);
3314 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3317 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3318 DPLL_FPA01_P1_POST_DIV_SHIFT);
3321 if ((dpll & PLL_REF_INPUT_MASK) ==
3322 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3323 /* XXX: might not be 66MHz */
3324 intel_clock(dev, 66000, &clock);
3326 intel_clock(dev, 48000, &clock);
3328 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3331 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3332 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3334 if (dpll & PLL_P2_DIVIDE_BY_4)
3339 intel_clock(dev, 48000, &clock);
3343 /* XXX: It would be nice to validate the clocks, but we can't reuse
3344 * i830PllIsValid() because it relies on the xf86_config connector
3345 * configuration being accurate, which it isn't necessarily.
3351 /** Returns the currently programmed mode of the given pipe. */
3352 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3353 struct drm_crtc *crtc)
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
3358 struct drm_display_mode *mode;
3359 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3360 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3361 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3362 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3364 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3368 mode->clock = intel_crtc_clock_get(dev, crtc);
3369 mode->hdisplay = (htot & 0xffff) + 1;
3370 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3371 mode->hsync_start = (hsync & 0xffff) + 1;
3372 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3373 mode->vdisplay = (vtot & 0xffff) + 1;
3374 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3375 mode->vsync_start = (vsync & 0xffff) + 1;
3376 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3378 drm_mode_set_name(mode);
3379 drm_mode_set_crtcinfo(mode, 0);
3384 #define GPU_IDLE_TIMEOUT 500 /* ms */
3386 /* When this timer fires, we've been idle for awhile */
3387 static void intel_gpu_idle_timer(unsigned long arg)
3389 struct drm_device *dev = (struct drm_device *)arg;
3390 drm_i915_private_t *dev_priv = dev->dev_private;
3392 DRM_DEBUG("idle timer fired, downclocking\n");
3394 dev_priv->busy = false;
3396 queue_work(dev_priv->wq, &dev_priv->idle_work);
3399 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3401 drm_i915_private_t *dev_priv = dev->dev_private;
3406 if (!dev_priv->render_reclock_avail) {
3407 DRM_DEBUG("not reclocking render clock\n");
3411 /* Restore render clock frequency to original value */
3412 if (IS_G4X(dev) || IS_I9XX(dev))
3413 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3414 else if (IS_I85X(dev))
3415 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3416 DRM_DEBUG("increasing render clock frequency\n");
3418 /* Schedule downclock */
3420 mod_timer(&dev_priv->idle_timer, jiffies +
3421 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3424 void intel_decrease_renderclock(struct drm_device *dev)
3426 drm_i915_private_t *dev_priv = dev->dev_private;
3431 if (!dev_priv->render_reclock_avail) {
3432 DRM_DEBUG("not reclocking render clock\n");
3439 /* Adjust render clock... */
3440 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3442 /* Down to minimum... */
3443 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3444 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3446 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3447 } else if (IS_I965G(dev)) {
3450 /* Adjust render clock... */
3451 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3453 /* Down to minimum... */
3454 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3455 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3457 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3458 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3461 /* Adjust render clock... */
3462 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3464 /* Down to minimum... */
3465 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3466 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3468 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3469 } else if (IS_I915G(dev)) {
3472 /* Adjust render clock... */
3473 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3475 /* Down to minimum... */
3476 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3477 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3479 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3480 } else if (IS_I85X(dev)) {
3483 /* Adjust render clock... */
3484 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3486 /* Up to maximum... */
3487 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3488 hpllcc |= GC_CLOCK_133_200;
3490 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3492 DRM_DEBUG("decreasing render clock frequency\n");
3495 /* Note that no increase function is needed for this - increase_renderclock()
3496 * will also rewrite these bits
3498 void intel_decrease_displayclock(struct drm_device *dev)
3503 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3507 /* Adjust render clock... */
3508 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3510 /* Down to minimum... */
3514 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3518 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3520 static void intel_crtc_idle_timer(unsigned long arg)
3522 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3523 struct drm_crtc *crtc = &intel_crtc->base;
3524 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3526 DRM_DEBUG("idle timer fired, downclocking\n");
3528 intel_crtc->busy = false;
3530 queue_work(dev_priv->wq, &dev_priv->idle_work);
3533 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3535 struct drm_device *dev = crtc->dev;
3536 drm_i915_private_t *dev_priv = dev->dev_private;
3537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3538 int pipe = intel_crtc->pipe;
3539 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3540 int dpll = I915_READ(dpll_reg);
3545 if (!dev_priv->lvds_downclock_avail)
3548 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3549 DRM_DEBUG("upclocking LVDS\n");
3551 /* Unlock panel regs */
3552 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3554 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3555 I915_WRITE(dpll_reg, dpll);
3556 dpll = I915_READ(dpll_reg);
3557 intel_wait_for_vblank(dev);
3558 dpll = I915_READ(dpll_reg);
3559 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3560 DRM_DEBUG("failed to upclock LVDS!\n");
3562 /* ...and lock them again */
3563 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3566 /* Schedule downclock */
3568 mod_timer(&intel_crtc->idle_timer, jiffies +
3569 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3572 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3574 struct drm_device *dev = crtc->dev;
3575 drm_i915_private_t *dev_priv = dev->dev_private;
3576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3577 int pipe = intel_crtc->pipe;
3578 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3579 int dpll = I915_READ(dpll_reg);
3584 if (!dev_priv->lvds_downclock_avail)
3588 * Since this is called by a timer, we should never get here in
3591 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3592 DRM_DEBUG("downclocking LVDS\n");
3594 /* Unlock panel regs */
3595 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3597 dpll |= DISPLAY_RATE_SELECT_FPA1;
3598 I915_WRITE(dpll_reg, dpll);
3599 dpll = I915_READ(dpll_reg);
3600 intel_wait_for_vblank(dev);
3601 dpll = I915_READ(dpll_reg);
3602 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3603 DRM_DEBUG("failed to downclock LVDS!\n");
3605 /* ...and lock them again */
3606 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3612 * intel_idle_update - adjust clocks for idleness
3613 * @work: work struct
3615 * Either the GPU or display (or both) went idle. Check the busy status
3616 * here and adjust the CRTC and GPU clocks as necessary.
3618 static void intel_idle_update(struct work_struct *work)
3620 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3622 struct drm_device *dev = dev_priv->dev;
3623 struct drm_crtc *crtc;
3624 struct intel_crtc *intel_crtc;
3626 if (!i915_powersave)
3629 mutex_lock(&dev->struct_mutex);
3631 /* GPU isn't processing, downclock it. */
3632 if (!dev_priv->busy) {
3633 intel_decrease_renderclock(dev);
3634 intel_decrease_displayclock(dev);
3637 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3638 /* Skip inactive CRTCs */
3642 intel_crtc = to_intel_crtc(crtc);
3643 if (!intel_crtc->busy)
3644 intel_decrease_pllclock(crtc);
3647 mutex_unlock(&dev->struct_mutex);
3651 * intel_mark_busy - mark the GPU and possibly the display busy
3653 * @obj: object we're operating on
3655 * Callers can use this function to indicate that the GPU is busy processing
3656 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3657 * buffer), we'll also mark the display as busy, so we know to increase its
3660 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3662 drm_i915_private_t *dev_priv = dev->dev_private;
3663 struct drm_crtc *crtc = NULL;
3664 struct intel_framebuffer *intel_fb;
3665 struct intel_crtc *intel_crtc;
3667 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3670 dev_priv->busy = true;
3671 intel_increase_renderclock(dev, true);
3673 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3677 intel_crtc = to_intel_crtc(crtc);
3678 intel_fb = to_intel_framebuffer(crtc->fb);
3679 if (intel_fb->obj == obj) {
3680 if (!intel_crtc->busy) {
3681 /* Non-busy -> busy, upclock */
3682 intel_increase_pllclock(crtc, true);
3683 intel_crtc->busy = true;
3685 /* Busy -> busy, put off timer */
3686 mod_timer(&intel_crtc->idle_timer, jiffies +
3687 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3693 static void intel_crtc_destroy(struct drm_crtc *crtc)
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697 drm_crtc_cleanup(crtc);
3701 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3702 .dpms = intel_crtc_dpms,
3703 .mode_fixup = intel_crtc_mode_fixup,
3704 .mode_set = intel_crtc_mode_set,
3705 .mode_set_base = intel_pipe_set_base,
3706 .prepare = intel_crtc_prepare,
3707 .commit = intel_crtc_commit,
3710 static const struct drm_crtc_funcs intel_crtc_funcs = {
3711 .cursor_set = intel_crtc_cursor_set,
3712 .cursor_move = intel_crtc_cursor_move,
3713 .gamma_set = intel_crtc_gamma_set,
3714 .set_config = drm_crtc_helper_set_config,
3715 .destroy = intel_crtc_destroy,
3719 static void intel_crtc_init(struct drm_device *dev, int pipe)
3721 struct intel_crtc *intel_crtc;
3724 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3725 if (intel_crtc == NULL)
3728 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3730 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3731 intel_crtc->pipe = pipe;
3732 intel_crtc->plane = pipe;
3733 for (i = 0; i < 256; i++) {
3734 intel_crtc->lut_r[i] = i;
3735 intel_crtc->lut_g[i] = i;
3736 intel_crtc->lut_b[i] = i;
3739 /* Swap pipes & planes for FBC on pre-965 */
3740 intel_crtc->pipe = pipe;
3741 intel_crtc->plane = pipe;
3742 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
3743 DRM_DEBUG("swapping pipes & planes for FBC\n");
3744 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
3747 intel_crtc->cursor_addr = 0;
3748 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3749 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3751 intel_crtc->busy = false;
3753 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
3754 (unsigned long)intel_crtc);
3757 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3758 struct drm_file *file_priv)
3760 drm_i915_private_t *dev_priv = dev->dev_private;
3761 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3762 struct drm_mode_object *drmmode_obj;
3763 struct intel_crtc *crtc;
3766 DRM_ERROR("called with no initialization\n");
3770 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
3771 DRM_MODE_OBJECT_CRTC);
3774 DRM_ERROR("no such CRTC id\n");
3778 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
3779 pipe_from_crtc_id->pipe = crtc->pipe;
3784 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3786 struct drm_crtc *crtc = NULL;
3788 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 if (intel_crtc->pipe == pipe)
3796 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3799 struct drm_connector *connector;
3802 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3803 struct intel_output *intel_output = to_intel_output(connector);
3804 if (type_mask & intel_output->clone_mask)
3805 index_mask |= (1 << entry);
3812 static void intel_setup_outputs(struct drm_device *dev)
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 struct drm_connector *connector;
3817 intel_crt_init(dev);
3819 /* Set up integrated LVDS */
3820 if (IS_MOBILE(dev) && !IS_I830(dev))
3821 intel_lvds_init(dev);
3823 if (IS_IGDNG(dev)) {
3826 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3827 intel_dp_init(dev, DP_A);
3829 if (I915_READ(HDMIB) & PORT_DETECTED) {
3831 /* found = intel_sdvo_init(dev, HDMIB); */
3834 intel_hdmi_init(dev, HDMIB);
3835 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3836 intel_dp_init(dev, PCH_DP_B);
3839 if (I915_READ(HDMIC) & PORT_DETECTED)
3840 intel_hdmi_init(dev, HDMIC);
3842 if (I915_READ(HDMID) & PORT_DETECTED)
3843 intel_hdmi_init(dev, HDMID);
3845 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3846 intel_dp_init(dev, PCH_DP_C);
3848 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3849 intel_dp_init(dev, PCH_DP_D);
3851 } else if (IS_I9XX(dev)) {
3854 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3855 found = intel_sdvo_init(dev, SDVOB);
3856 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3857 intel_hdmi_init(dev, SDVOB);
3859 if (!found && SUPPORTS_INTEGRATED_DP(dev))
3860 intel_dp_init(dev, DP_B);
3863 /* Before G4X SDVOC doesn't have its own detect register */
3865 if (I915_READ(SDVOB) & SDVO_DETECTED)
3866 found = intel_sdvo_init(dev, SDVOC);
3868 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3870 if (SUPPORTS_INTEGRATED_HDMI(dev))
3871 intel_hdmi_init(dev, SDVOC);
3872 if (SUPPORTS_INTEGRATED_DP(dev))
3873 intel_dp_init(dev, DP_C);
3876 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3877 intel_dp_init(dev, DP_D);
3879 intel_dvo_init(dev);
3881 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3884 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3885 struct intel_output *intel_output = to_intel_output(connector);
3886 struct drm_encoder *encoder = &intel_output->enc;
3888 encoder->possible_crtcs = intel_output->crtc_mask;
3889 encoder->possible_clones = intel_connector_clones(dev,
3890 intel_output->clone_mask);
3894 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3896 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3897 struct drm_device *dev = fb->dev;
3900 intelfb_remove(dev, fb);
3902 drm_framebuffer_cleanup(fb);
3903 mutex_lock(&dev->struct_mutex);
3904 drm_gem_object_unreference(intel_fb->obj);
3905 mutex_unlock(&dev->struct_mutex);
3910 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3911 struct drm_file *file_priv,
3912 unsigned int *handle)
3914 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3915 struct drm_gem_object *object = intel_fb->obj;
3917 return drm_gem_handle_create(file_priv, object, handle);
3920 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3921 .destroy = intel_user_framebuffer_destroy,
3922 .create_handle = intel_user_framebuffer_create_handle,
3925 int intel_framebuffer_create(struct drm_device *dev,
3926 struct drm_mode_fb_cmd *mode_cmd,
3927 struct drm_framebuffer **fb,
3928 struct drm_gem_object *obj)
3930 struct intel_framebuffer *intel_fb;
3933 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3937 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3939 DRM_ERROR("framebuffer init failed %d\n", ret);
3943 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3945 intel_fb->obj = obj;
3947 *fb = &intel_fb->base;
3953 static struct drm_framebuffer *
3954 intel_user_framebuffer_create(struct drm_device *dev,
3955 struct drm_file *filp,
3956 struct drm_mode_fb_cmd *mode_cmd)
3958 struct drm_gem_object *obj;
3959 struct drm_framebuffer *fb;
3962 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3966 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3968 mutex_lock(&dev->struct_mutex);
3969 drm_gem_object_unreference(obj);
3970 mutex_unlock(&dev->struct_mutex);
3977 static const struct drm_mode_config_funcs intel_mode_funcs = {
3978 .fb_create = intel_user_framebuffer_create,
3979 .fb_changed = intelfb_probe,
3982 void intel_init_clock_gating(struct drm_device *dev)
3984 struct drm_i915_private *dev_priv = dev->dev_private;
3987 * Disable clock gating reported to work incorrectly according to the
3988 * specs, but enable as much else as we can.
3991 uint32_t dspclk_gate;
3992 I915_WRITE(RENCLK_GATE_D1, 0);
3993 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3994 GS_UNIT_CLOCK_GATE_DISABLE |
3995 CL_UNIT_CLOCK_GATE_DISABLE);
3996 I915_WRITE(RAMCLK_GATE_D, 0);
3997 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3998 OVRUNIT_CLOCK_GATE_DISABLE |
3999 OVCUNIT_CLOCK_GATE_DISABLE;
4001 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4002 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4003 } else if (IS_I965GM(dev)) {
4004 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4005 I915_WRITE(RENCLK_GATE_D2, 0);
4006 I915_WRITE(DSPCLK_GATE_D, 0);
4007 I915_WRITE(RAMCLK_GATE_D, 0);
4008 I915_WRITE16(DEUC, 0);
4009 } else if (IS_I965G(dev)) {
4010 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4011 I965_RCC_CLOCK_GATE_DISABLE |
4012 I965_RCPB_CLOCK_GATE_DISABLE |
4013 I965_ISC_CLOCK_GATE_DISABLE |
4014 I965_FBC_CLOCK_GATE_DISABLE);
4015 I915_WRITE(RENCLK_GATE_D2, 0);
4016 } else if (IS_I9XX(dev)) {
4017 u32 dstate = I915_READ(D_STATE);
4019 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4020 DSTATE_DOT_CLOCK_GATING;
4021 I915_WRITE(D_STATE, dstate);
4022 } else if (IS_I855(dev) || IS_I865G(dev)) {
4023 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4024 } else if (IS_I830(dev)) {
4025 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4029 void intel_modeset_init(struct drm_device *dev)
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4035 drm_mode_config_init(dev);
4037 dev->mode_config.min_width = 0;
4038 dev->mode_config.min_height = 0;
4040 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4042 if (IS_I965G(dev)) {
4043 dev->mode_config.max_width = 8192;
4044 dev->mode_config.max_height = 8192;
4045 } else if (IS_I9XX(dev)) {
4046 dev->mode_config.max_width = 4096;
4047 dev->mode_config.max_height = 4096;
4049 dev->mode_config.max_width = 2048;
4050 dev->mode_config.max_height = 2048;
4053 /* set memory base */
4055 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4057 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4059 if (IS_MOBILE(dev) || IS_I9XX(dev))
4063 DRM_DEBUG("%d display pipe%s available.\n",
4064 num_pipe, num_pipe > 1 ? "s" : "");
4067 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4068 else if (IS_I9XX(dev) || IS_G4X(dev))
4069 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4071 for (i = 0; i < num_pipe; i++) {
4072 intel_crtc_init(dev, i);
4075 intel_setup_outputs(dev);
4077 intel_init_clock_gating(dev);
4079 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4080 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4081 (unsigned long)dev);
4084 void intel_modeset_cleanup(struct drm_device *dev)
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct drm_crtc *crtc;
4088 struct intel_crtc *intel_crtc;
4090 mutex_lock(&dev->struct_mutex);
4092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4093 /* Skip inactive CRTCs */
4097 intel_crtc = to_intel_crtc(crtc);
4098 intel_increase_pllclock(crtc, false);
4099 del_timer_sync(&intel_crtc->idle_timer);
4102 intel_increase_renderclock(dev, false);
4103 del_timer_sync(&dev_priv->idle_timer);
4105 mutex_unlock(&dev->struct_mutex);
4107 i8xx_disable_fbc(dev);
4108 drm_mode_config_cleanup(dev);
4112 /* current intel driver doesn't take advantage of encoders
4113 always give back the encoder for the connector
4115 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4117 struct intel_output *intel_output = to_intel_output(connector);
4119 return &intel_output->enc;