drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  *
1433  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434  */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* No really, not for ILK+ */
1441         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443         /* PLL is protected by panel, make sure we can write it */
1444         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445                 assert_panel_unlocked(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val |= DPLL_VCO_ENABLE;
1450
1451         /* We do this three times for luck */
1452         I915_WRITE(reg, val);
1453         POSTING_READ(reg);
1454         udelay(150); /* wait for warmup */
1455         I915_WRITE(reg, val);
1456         POSTING_READ(reg);
1457         udelay(150); /* wait for warmup */
1458         I915_WRITE(reg, val);
1459         POSTING_READ(reg);
1460         udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464  * intel_disable_pll - disable a PLL
1465  * @dev_priv: i915 private structure
1466  * @pipe: pipe PLL to disable
1467  *
1468  * Disable the PLL for @pipe, making sure the pipe is off first.
1469  *
1470  * Note!  This is for pre-ILK only.
1471  */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* Don't disable pipe A or pipe A PLLs if needed */
1478         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479                 return;
1480
1481         /* Make sure the pipe isn't still relying on us */
1482         assert_pipe_disabled(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val &= ~DPLL_VCO_ENABLE;
1487         I915_WRITE(reg, val);
1488         POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495         unsigned long flags;
1496
1497         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499                                 100)) {
1500                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501                 goto out_unlock;
1502         }
1503
1504         I915_WRITE(SBI_ADDR,
1505                         (reg << 16));
1506         I915_WRITE(SBI_DATA,
1507                         value);
1508         I915_WRITE(SBI_CTL_STAT,
1509                         SBI_BUSY |
1510                         SBI_CTL_OP_CRWR);
1511
1512         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513                                 100)) {
1514                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515                 goto out_unlock;
1516         }
1517
1518 out_unlock:
1519         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525         unsigned long flags;
1526         u32 value = 0;
1527
1528         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530                                 100)) {
1531                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532                 goto out_unlock;
1533         }
1534
1535         I915_WRITE(SBI_ADDR,
1536                         (reg << 16));
1537         I915_WRITE(SBI_CTL_STAT,
1538                         SBI_BUSY |
1539                         SBI_CTL_OP_CRRD);
1540
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544                 goto out_unlock;
1545         }
1546
1547         value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551         return value;
1552 }
1553
1554 /**
1555  * intel_enable_pch_pll - enable PCH PLL
1556  * @dev_priv: i915 private structure
1557  * @pipe: pipe PLL to enable
1558  *
1559  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560  * drives the transcoder clock.
1561  */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565         struct intel_pch_pll *pll;
1566         int reg;
1567         u32 val;
1568
1569         /* PCH PLLs only available on ILK, SNB and IVB */
1570         BUG_ON(dev_priv->info->gen < 5);
1571         pll = intel_crtc->pch_pll;
1572         if (pll == NULL)
1573                 return;
1574
1575         if (WARN_ON(pll->refcount == 0))
1576                 return;
1577
1578         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579                       pll->pll_reg, pll->active, pll->on,
1580                       intel_crtc->base.base.id);
1581
1582         /* PCH refclock must be enabled first */
1583         assert_pch_refclk_enabled(dev_priv);
1584
1585         if (pll->active++ && pll->on) {
1586                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587                 return;
1588         }
1589
1590         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592         reg = pll->pll_reg;
1593         val = I915_READ(reg);
1594         val |= DPLL_VCO_ENABLE;
1595         I915_WRITE(reg, val);
1596         POSTING_READ(reg);
1597         udelay(200);
1598
1599         pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606         int reg;
1607         u32 val;
1608
1609         /* PCH only available on ILK+ */
1610         BUG_ON(dev_priv->info->gen < 5);
1611         if (pll == NULL)
1612                return;
1613
1614         if (WARN_ON(pll->refcount == 0))
1615                 return;
1616
1617         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618                       pll->pll_reg, pll->active, pll->on,
1619                       intel_crtc->base.base.id);
1620
1621         if (WARN_ON(pll->active == 0)) {
1622                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623                 return;
1624         }
1625
1626         if (--pll->active) {
1627                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628                 return;
1629         }
1630
1631         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633         /* Make sure transcoder isn't still depending on us */
1634         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636         reg = pll->pll_reg;
1637         val = I915_READ(reg);
1638         val &= ~DPLL_VCO_ENABLE;
1639         I915_WRITE(reg, val);
1640         POSTING_READ(reg);
1641         udelay(200);
1642
1643         pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647                                     enum pipe pipe)
1648 {
1649         int reg;
1650         u32 val, pipeconf_val;
1651         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653         /* PCH only available on ILK+ */
1654         BUG_ON(dev_priv->info->gen < 5);
1655
1656         /* Make sure PCH DPLL is enabled */
1657         assert_pch_pll_enabled(dev_priv,
1658                                to_intel_crtc(crtc)->pch_pll,
1659                                to_intel_crtc(crtc));
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667                 return;
1668         }
1669         reg = TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv->dev)) {
1674                 /*
1675                  * make the BPC in transcoder be consistent with
1676                  * that in pipeconf reg.
1677                  */
1678                 val &= ~PIPE_BPC_MASK;
1679                 val |= pipeconf_val & PIPE_BPC_MASK;
1680         }
1681
1682         val &= ~TRANS_INTERLACE_MASK;
1683         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684                 if (HAS_PCH_IBX(dev_priv->dev) &&
1685                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686                         val |= TRANS_LEGACY_INTERLACED_ILK;
1687                 else
1688                         val |= TRANS_INTERLACED;
1689         else
1690                 val |= TRANS_PROGRESSIVE;
1691
1692         I915_WRITE(reg, val | TRANS_ENABLE);
1693         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698                                      enum pipe pipe)
1699 {
1700         int reg;
1701         u32 val;
1702
1703         /* FDI relies on the transcoder */
1704         assert_fdi_tx_disabled(dev_priv, pipe);
1705         assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707         /* Ports must be off as well */
1708         assert_pch_ports_disabled(dev_priv, pipe);
1709
1710         reg = TRANSCONF(pipe);
1711         val = I915_READ(reg);
1712         val &= ~TRANS_ENABLE;
1713         I915_WRITE(reg, val);
1714         /* wait for PCH transcoder off, transcoder state */
1715         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720  * intel_enable_pipe - enable a pipe, asserting requirements
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe to enable
1723  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724  *
1725  * Enable @pipe, making sure that various hardware specific requirements
1726  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727  *
1728  * @pipe should be %PIPE_A or %PIPE_B.
1729  *
1730  * Will wait until the pipe is actually running (i.e. first vblank) before
1731  * returning.
1732  */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734                               bool pch_port)
1735 {
1736         int reg;
1737         u32 val;
1738
1739         /*
1740          * A pipe without a PLL won't actually be able to drive bits from
1741          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1742          * need the check.
1743          */
1744         if (!HAS_PCH_SPLIT(dev_priv->dev))
1745                 assert_pll_enabled(dev_priv, pipe);
1746         else {
1747                 if (pch_port) {
1748                         /* if driving the PCH, we need FDI enabled */
1749                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751                 }
1752                 /* FIXME: assert CPU port conditions for SNB+ */
1753         }
1754
1755         reg = PIPECONF(pipe);
1756         val = I915_READ(reg);
1757         if (val & PIPECONF_ENABLE)
1758                 return;
1759
1760         I915_WRITE(reg, val | PIPECONF_ENABLE);
1761         intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765  * intel_disable_pipe - disable a pipe, asserting requirements
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe to disable
1768  *
1769  * Disable @pipe, making sure that various hardware specific requirements
1770  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771  *
1772  * @pipe should be %PIPE_A or %PIPE_B.
1773  *
1774  * Will wait until the pipe has shut down before returning.
1775  */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777                                enum pipe pipe)
1778 {
1779         int reg;
1780         u32 val;
1781
1782         /*
1783          * Make sure planes won't keep trying to pump pixels to us,
1784          * or we might hang the display.
1785          */
1786         assert_planes_disabled(dev_priv, pipe);
1787
1788         /* Don't disable pipe A or pipe A PLLs if needed */
1789         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790                 return;
1791
1792         reg = PIPECONF(pipe);
1793         val = I915_READ(reg);
1794         if ((val & PIPECONF_ENABLE) == 0)
1795                 return;
1796
1797         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802  * Plane regs are double buffered, going from enabled->disabled needs a
1803  * trigger in order to latch.  The display address reg provides this.
1804  */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806                                       enum plane plane)
1807 {
1808         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813  * intel_enable_plane - enable a display plane on a given pipe
1814  * @dev_priv: i915 private structure
1815  * @plane: plane to enable
1816  * @pipe: pipe being fed
1817  *
1818  * Enable @plane on @pipe, making sure that @pipe is running first.
1819  */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane, enum pipe pipe)
1822 {
1823         int reg;
1824         u32 val;
1825
1826         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827         assert_pipe_enabled(dev_priv, pipe);
1828
1829         reg = DSPCNTR(plane);
1830         val = I915_READ(reg);
1831         if (val & DISPLAY_PLANE_ENABLE)
1832                 return;
1833
1834         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835         intel_flush_display_plane(dev_priv, plane);
1836         intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840  * intel_disable_plane - disable a display plane
1841  * @dev_priv: i915 private structure
1842  * @plane: plane to disable
1843  * @pipe: pipe consuming the data
1844  *
1845  * Disable @plane; should be an independent operation.
1846  */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848                                 enum plane plane, enum pipe pipe)
1849 {
1850         int reg;
1851         u32 val;
1852
1853         reg = DSPCNTR(plane);
1854         val = I915_READ(reg);
1855         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856                 return;
1857
1858         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859         intel_flush_display_plane(dev_priv, plane);
1860         intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864                            enum pipe pipe, int reg, u32 port_sel)
1865 {
1866         u32 val = I915_READ(reg);
1867         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869                 I915_WRITE(reg, val & ~DP_PORT_EN);
1870         }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874                              enum pipe pipe, int reg)
1875 {
1876         u32 val = I915_READ(reg);
1877         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879                               reg, pipe);
1880                 I915_WRITE(reg, val & ~PORT_ENABLE);
1881         }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886                                     enum pipe pipe)
1887 {
1888         u32 reg, val;
1889
1890         val = I915_READ(PCH_PP_CONTROL);
1891         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897         reg = PCH_ADPA;
1898         val = I915_READ(reg);
1899         if (adpa_pipe_enabled(dev_priv, pipe, val))
1900                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902         reg = PCH_LVDS;
1903         val = I915_READ(reg);
1904         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907                 POSTING_READ(reg);
1908                 udelay(100);
1909         }
1910
1911         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913         disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918                            struct drm_i915_gem_object *obj,
1919                            struct intel_ring_buffer *pipelined)
1920 {
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         u32 alignment;
1923         int ret;
1924
1925         switch (obj->tiling_mode) {
1926         case I915_TILING_NONE:
1927                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928                         alignment = 128 * 1024;
1929                 else if (INTEL_INFO(dev)->gen >= 4)
1930                         alignment = 4 * 1024;
1931                 else
1932                         alignment = 64 * 1024;
1933                 break;
1934         case I915_TILING_X:
1935                 /* pin() will align the object as required by fence */
1936                 alignment = 0;
1937                 break;
1938         case I915_TILING_Y:
1939                 /* FIXME: Is this true? */
1940                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941                 return -EINVAL;
1942         default:
1943                 BUG();
1944         }
1945
1946         dev_priv->mm.interruptible = false;
1947         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948         if (ret)
1949                 goto err_interruptible;
1950
1951         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952          * fence, whereas 965+ only requires a fence if using
1953          * framebuffer compression.  For simplicity, we always install
1954          * a fence as the cost is not that onerous.
1955          */
1956         ret = i915_gem_object_get_fence(obj);
1957         if (ret)
1958                 goto err_unpin;
1959
1960         i915_gem_object_pin_fence(obj);
1961
1962         dev_priv->mm.interruptible = true;
1963         return 0;
1964
1965 err_unpin:
1966         i915_gem_object_unpin(obj);
1967 err_interruptible:
1968         dev_priv->mm.interruptible = true;
1969         return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974         i915_gem_object_unpin_fence(obj);
1975         i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979  * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981                                                         unsigned int bpp,
1982                                                         unsigned int pitch)
1983 {
1984         int tile_rows, tiles;
1985
1986         tile_rows = *y / 8;
1987         *y %= 8;
1988         tiles = *x / (512/bpp);
1989         *x %= 512/bpp;
1990
1991         return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->bits_per_pixel) {
2024         case 8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case 16:
2028                 if (fb->depth == 15)
2029                         dspcntr |= DISPPLANE_15_16BPP;
2030                 else
2031                         dspcntr |= DISPPLANE_16BPP;
2032                 break;
2033         case 24:
2034         case 32:
2035                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036                 break;
2037         default:
2038                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039                 return -EINVAL;
2040         }
2041         if (INTEL_INFO(dev)->gen >= 4) {
2042                 if (obj->tiling_mode != I915_TILING_NONE)
2043                         dspcntr |= DISPPLANE_TILED;
2044                 else
2045                         dspcntr &= ~DISPPLANE_TILED;
2046         }
2047
2048         I915_WRITE(reg, dspcntr);
2049
2050         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052         if (INTEL_INFO(dev)->gen >= 4) {
2053                 intel_crtc->dspaddr_offset =
2054                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055                                                            fb->bits_per_pixel / 8,
2056                                                            fb->pitches[0]);
2057                 linear_offset -= intel_crtc->dspaddr_offset;
2058         } else {
2059                 intel_crtc->dspaddr_offset = linear_offset;
2060         }
2061
2062         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065         if (INTEL_INFO(dev)->gen >= 4) {
2066                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2068                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070         } else
2071                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072         POSTING_READ(reg);
2073
2074         return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078                                  struct drm_framebuffer *fb, int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long linear_offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093         case 2:
2094                 break;
2095         default:
2096                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097                 return -EINVAL;
2098         }
2099
2100         intel_fb = to_intel_framebuffer(fb);
2101         obj = intel_fb->obj;
2102
2103         reg = DSPCNTR(plane);
2104         dspcntr = I915_READ(reg);
2105         /* Mask out pixel format bits in case we change it */
2106         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107         switch (fb->bits_per_pixel) {
2108         case 8:
2109                 dspcntr |= DISPPLANE_8BPP;
2110                 break;
2111         case 16:
2112                 if (fb->depth != 16)
2113                         return -EINVAL;
2114
2115                 dspcntr |= DISPPLANE_16BPP;
2116                 break;
2117         case 24:
2118         case 32:
2119                 if (fb->depth == 24)
2120                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121                 else if (fb->depth == 30)
2122                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123                 else
2124                         return -EINVAL;
2125                 break;
2126         default:
2127                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128                 return -EINVAL;
2129         }
2130
2131         if (obj->tiling_mode != I915_TILING_NONE)
2132                 dspcntr |= DISPPLANE_TILED;
2133         else
2134                 dspcntr &= ~DISPPLANE_TILED;
2135
2136         /* must disable */
2137         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139         I915_WRITE(reg, dspcntr);
2140
2141         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142         intel_crtc->dspaddr_offset =
2143                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144                                                    fb->bits_per_pixel / 8,
2145                                                    fb->pitches[0]);
2146         linear_offset -= intel_crtc->dspaddr_offset;
2147
2148         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151         I915_MODIFY_DISPBASE(DSPSURF(plane),
2152                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2153         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154         I915_WRITE(DSPLINOFF(plane), linear_offset);
2155         POSTING_READ(reg);
2156
2157         return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163                            int x, int y, enum mode_set_atomic state)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168         if (dev_priv->display.disable_fbc)
2169                 dev_priv->display.disable_fbc(dev);
2170         intel_increase_pllclock(crtc);
2171
2172         return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180         bool was_interruptible = dev_priv->mm.interruptible;
2181         int ret;
2182
2183         wait_event(dev_priv->pending_flip_queue,
2184                    atomic_read(&dev_priv->mm.wedged) ||
2185                    atomic_read(&obj->pending_flip) == 0);
2186
2187         /* Big Hammer, we also need to ensure that any pending
2188          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189          * current scanout is retired before unpinning the old
2190          * framebuffer.
2191          *
2192          * This should only fail upon a hung GPU, in which case we
2193          * can safely continue.
2194          */
2195         dev_priv->mm.interruptible = false;
2196         ret = i915_gem_object_finish_gpu(obj);
2197         dev_priv->mm.interruptible = was_interruptible;
2198
2199         return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204                     struct drm_framebuffer *fb)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_master_private *master_priv;
2209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210         struct drm_framebuffer *old_fb;
2211         int ret;
2212
2213         /* no fb bound */
2214         if (!fb) {
2215                 DRM_ERROR("No FB bound\n");
2216                 return 0;
2217         }
2218
2219         if(intel_crtc->plane > dev_priv->num_pipe) {
2220                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221                                 intel_crtc->plane,
2222                                 dev_priv->num_pipe);
2223                 return -EINVAL;
2224         }
2225
2226         mutex_lock(&dev->struct_mutex);
2227         ret = intel_pin_and_fence_fb_obj(dev,
2228                                          to_intel_framebuffer(fb)->obj,
2229                                          NULL);
2230         if (ret != 0) {
2231                 mutex_unlock(&dev->struct_mutex);
2232                 DRM_ERROR("pin & fence failed\n");
2233                 return ret;
2234         }
2235
2236         if (crtc->fb)
2237                 intel_finish_fb(crtc->fb);
2238
2239         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2240         if (ret) {
2241                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2242                 mutex_unlock(&dev->struct_mutex);
2243                 DRM_ERROR("failed to update base address\n");
2244                 return ret;
2245         }
2246
2247         old_fb = crtc->fb;
2248         crtc->fb = fb;
2249
2250         if (old_fb) {
2251                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2252                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2253         }
2254
2255         intel_update_fbc(dev);
2256         mutex_unlock(&dev->struct_mutex);
2257
2258         if (!dev->primary->master)
2259                 return 0;
2260
2261         master_priv = dev->primary->master->driver_priv;
2262         if (!master_priv->sarea_priv)
2263                 return 0;
2264
2265         if (intel_crtc->pipe) {
2266                 master_priv->sarea_priv->pipeB_x = x;
2267                 master_priv->sarea_priv->pipeB_y = y;
2268         } else {
2269                 master_priv->sarea_priv->pipeA_x = x;
2270                 master_priv->sarea_priv->pipeA_y = y;
2271         }
2272
2273         return 0;
2274 }
2275
2276 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2277 {
2278         struct drm_device *dev = crtc->dev;
2279         struct drm_i915_private *dev_priv = dev->dev_private;
2280         u32 dpa_ctl;
2281
2282         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2283         dpa_ctl = I915_READ(DP_A);
2284         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2285
2286         if (clock < 200000) {
2287                 u32 temp;
2288                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2289                 /* workaround for 160Mhz:
2290                    1) program 0x4600c bits 15:0 = 0x8124
2291                    2) program 0x46010 bit 0 = 1
2292                    3) program 0x46034 bit 24 = 1
2293                    4) program 0x64000 bit 14 = 1
2294                    */
2295                 temp = I915_READ(0x4600c);
2296                 temp &= 0xffff0000;
2297                 I915_WRITE(0x4600c, temp | 0x8124);
2298
2299                 temp = I915_READ(0x46010);
2300                 I915_WRITE(0x46010, temp | 1);
2301
2302                 temp = I915_READ(0x46034);
2303                 I915_WRITE(0x46034, temp | (1 << 24));
2304         } else {
2305                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2306         }
2307         I915_WRITE(DP_A, dpa_ctl);
2308
2309         POSTING_READ(DP_A);
2310         udelay(500);
2311 }
2312
2313 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2314 {
2315         struct drm_device *dev = crtc->dev;
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318         int pipe = intel_crtc->pipe;
2319         u32 reg, temp;
2320
2321         /* enable normal train */
2322         reg = FDI_TX_CTL(pipe);
2323         temp = I915_READ(reg);
2324         if (IS_IVYBRIDGE(dev)) {
2325                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2326                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2327         } else {
2328                 temp &= ~FDI_LINK_TRAIN_NONE;
2329                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2330         }
2331         I915_WRITE(reg, temp);
2332
2333         reg = FDI_RX_CTL(pipe);
2334         temp = I915_READ(reg);
2335         if (HAS_PCH_CPT(dev)) {
2336                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2337                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2338         } else {
2339                 temp &= ~FDI_LINK_TRAIN_NONE;
2340                 temp |= FDI_LINK_TRAIN_NONE;
2341         }
2342         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2343
2344         /* wait one idle pattern time */
2345         POSTING_READ(reg);
2346         udelay(1000);
2347
2348         /* IVB wants error correction enabled */
2349         if (IS_IVYBRIDGE(dev))
2350                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2351                            FDI_FE_ERRC_ENABLE);
2352 }
2353
2354 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2355 {
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357         u32 flags = I915_READ(SOUTH_CHICKEN1);
2358
2359         flags |= FDI_PHASE_SYNC_OVR(pipe);
2360         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2361         flags |= FDI_PHASE_SYNC_EN(pipe);
2362         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2363         POSTING_READ(SOUTH_CHICKEN1);
2364 }
2365
2366 /* The FDI link training functions for ILK/Ibexpeak. */
2367 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2368 {
2369         struct drm_device *dev = crtc->dev;
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2372         int pipe = intel_crtc->pipe;
2373         int plane = intel_crtc->plane;
2374         u32 reg, temp, tries;
2375
2376         /* FDI needs bits from pipe & plane first */
2377         assert_pipe_enabled(dev_priv, pipe);
2378         assert_plane_enabled(dev_priv, plane);
2379
2380         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2381            for train result */
2382         reg = FDI_RX_IMR(pipe);
2383         temp = I915_READ(reg);
2384         temp &= ~FDI_RX_SYMBOL_LOCK;
2385         temp &= ~FDI_RX_BIT_LOCK;
2386         I915_WRITE(reg, temp);
2387         I915_READ(reg);
2388         udelay(150);
2389
2390         /* enable CPU FDI TX and PCH FDI RX */
2391         reg = FDI_TX_CTL(pipe);
2392         temp = I915_READ(reg);
2393         temp &= ~(7 << 19);
2394         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2395         temp &= ~FDI_LINK_TRAIN_NONE;
2396         temp |= FDI_LINK_TRAIN_PATTERN_1;
2397         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2398
2399         reg = FDI_RX_CTL(pipe);
2400         temp = I915_READ(reg);
2401         temp &= ~FDI_LINK_TRAIN_NONE;
2402         temp |= FDI_LINK_TRAIN_PATTERN_1;
2403         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2404
2405         POSTING_READ(reg);
2406         udelay(150);
2407
2408         /* Ironlake workaround, enable clock pointer after FDI enable*/
2409         if (HAS_PCH_IBX(dev)) {
2410                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2411                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2412                            FDI_RX_PHASE_SYNC_POINTER_EN);
2413         }
2414
2415         reg = FDI_RX_IIR(pipe);
2416         for (tries = 0; tries < 5; tries++) {
2417                 temp = I915_READ(reg);
2418                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2419
2420                 if ((temp & FDI_RX_BIT_LOCK)) {
2421                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2422                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2423                         break;
2424                 }
2425         }
2426         if (tries == 5)
2427                 DRM_ERROR("FDI train 1 fail!\n");
2428
2429         /* Train 2 */
2430         reg = FDI_TX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_2;
2434         I915_WRITE(reg, temp);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_2;
2440         I915_WRITE(reg, temp);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         reg = FDI_RX_IIR(pipe);
2446         for (tries = 0; tries < 5; tries++) {
2447                 temp = I915_READ(reg);
2448                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449
2450                 if (temp & FDI_RX_SYMBOL_LOCK) {
2451                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2452                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2453                         break;
2454                 }
2455         }
2456         if (tries == 5)
2457                 DRM_ERROR("FDI train 2 fail!\n");
2458
2459         DRM_DEBUG_KMS("FDI train done\n");
2460
2461 }
2462
2463 static const int snb_b_fdi_train_param[] = {
2464         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2465         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2466         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2467         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2468 };
2469
2470 /* The FDI link training functions for SNB/Cougarpoint. */
2471 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2472 {
2473         struct drm_device *dev = crtc->dev;
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476         int pipe = intel_crtc->pipe;
2477         u32 reg, temp, i, retry;
2478
2479         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480            for train result */
2481         reg = FDI_RX_IMR(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~FDI_RX_SYMBOL_LOCK;
2484         temp &= ~FDI_RX_BIT_LOCK;
2485         I915_WRITE(reg, temp);
2486
2487         POSTING_READ(reg);
2488         udelay(150);
2489
2490         /* enable CPU FDI TX and PCH FDI RX */
2491         reg = FDI_TX_CTL(pipe);
2492         temp = I915_READ(reg);
2493         temp &= ~(7 << 19);
2494         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2495         temp &= ~FDI_LINK_TRAIN_NONE;
2496         temp |= FDI_LINK_TRAIN_PATTERN_1;
2497         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498         /* SNB-B */
2499         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2500         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2501
2502         reg = FDI_RX_CTL(pipe);
2503         temp = I915_READ(reg);
2504         if (HAS_PCH_CPT(dev)) {
2505                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507         } else {
2508                 temp &= ~FDI_LINK_TRAIN_NONE;
2509                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510         }
2511         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2512
2513         POSTING_READ(reg);
2514         udelay(150);
2515
2516         if (HAS_PCH_CPT(dev))
2517                 cpt_phase_pointer_enable(dev, pipe);
2518
2519         for (i = 0; i < 4; i++) {
2520                 reg = FDI_TX_CTL(pipe);
2521                 temp = I915_READ(reg);
2522                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523                 temp |= snb_b_fdi_train_param[i];
2524                 I915_WRITE(reg, temp);
2525
2526                 POSTING_READ(reg);
2527                 udelay(500);
2528
2529                 for (retry = 0; retry < 5; retry++) {
2530                         reg = FDI_RX_IIR(pipe);
2531                         temp = I915_READ(reg);
2532                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533                         if (temp & FDI_RX_BIT_LOCK) {
2534                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2535                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2536                                 break;
2537                         }
2538                         udelay(50);
2539                 }
2540                 if (retry < 5)
2541                         break;
2542         }
2543         if (i == 4)
2544                 DRM_ERROR("FDI train 1 fail!\n");
2545
2546         /* Train 2 */
2547         reg = FDI_TX_CTL(pipe);
2548         temp = I915_READ(reg);
2549         temp &= ~FDI_LINK_TRAIN_NONE;
2550         temp |= FDI_LINK_TRAIN_PATTERN_2;
2551         if (IS_GEN6(dev)) {
2552                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553                 /* SNB-B */
2554                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2555         }
2556         I915_WRITE(reg, temp);
2557
2558         reg = FDI_RX_CTL(pipe);
2559         temp = I915_READ(reg);
2560         if (HAS_PCH_CPT(dev)) {
2561                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2563         } else {
2564                 temp &= ~FDI_LINK_TRAIN_NONE;
2565                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2566         }
2567         I915_WRITE(reg, temp);
2568
2569         POSTING_READ(reg);
2570         udelay(150);
2571
2572         for (i = 0; i < 4; i++) {
2573                 reg = FDI_TX_CTL(pipe);
2574                 temp = I915_READ(reg);
2575                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2576                 temp |= snb_b_fdi_train_param[i];
2577                 I915_WRITE(reg, temp);
2578
2579                 POSTING_READ(reg);
2580                 udelay(500);
2581
2582                 for (retry = 0; retry < 5; retry++) {
2583                         reg = FDI_RX_IIR(pipe);
2584                         temp = I915_READ(reg);
2585                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586                         if (temp & FDI_RX_SYMBOL_LOCK) {
2587                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2588                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2589                                 break;
2590                         }
2591                         udelay(50);
2592                 }
2593                 if (retry < 5)
2594                         break;
2595         }
2596         if (i == 4)
2597                 DRM_ERROR("FDI train 2 fail!\n");
2598
2599         DRM_DEBUG_KMS("FDI train done.\n");
2600 }
2601
2602 /* Manual link training for Ivy Bridge A0 parts */
2603 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2604 {
2605         struct drm_device *dev = crtc->dev;
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608         int pipe = intel_crtc->pipe;
2609         u32 reg, temp, i;
2610
2611         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2612            for train result */
2613         reg = FDI_RX_IMR(pipe);
2614         temp = I915_READ(reg);
2615         temp &= ~FDI_RX_SYMBOL_LOCK;
2616         temp &= ~FDI_RX_BIT_LOCK;
2617         I915_WRITE(reg, temp);
2618
2619         POSTING_READ(reg);
2620         udelay(150);
2621
2622         /* enable CPU FDI TX and PCH FDI RX */
2623         reg = FDI_TX_CTL(pipe);
2624         temp = I915_READ(reg);
2625         temp &= ~(7 << 19);
2626         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2628         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2629         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2631         temp |= FDI_COMPOSITE_SYNC;
2632         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2633
2634         reg = FDI_RX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_AUTO;
2637         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2638         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2639         temp |= FDI_COMPOSITE_SYNC;
2640         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         if (HAS_PCH_CPT(dev))
2646                 cpt_phase_pointer_enable(dev, pipe);
2647
2648         for (i = 0; i < 4; i++) {
2649                 reg = FDI_TX_CTL(pipe);
2650                 temp = I915_READ(reg);
2651                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652                 temp |= snb_b_fdi_train_param[i];
2653                 I915_WRITE(reg, temp);
2654
2655                 POSTING_READ(reg);
2656                 udelay(500);
2657
2658                 reg = FDI_RX_IIR(pipe);
2659                 temp = I915_READ(reg);
2660                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662                 if (temp & FDI_RX_BIT_LOCK ||
2663                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2666                         break;
2667                 }
2668         }
2669         if (i == 4)
2670                 DRM_ERROR("FDI train 1 fail!\n");
2671
2672         /* Train 2 */
2673         reg = FDI_TX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2677         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2679         I915_WRITE(reg, temp);
2680
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685         I915_WRITE(reg, temp);
2686
2687         POSTING_READ(reg);
2688         udelay(150);
2689
2690         for (i = 0; i < 4; i++) {
2691                 reg = FDI_TX_CTL(pipe);
2692                 temp = I915_READ(reg);
2693                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694                 temp |= snb_b_fdi_train_param[i];
2695                 I915_WRITE(reg, temp);
2696
2697                 POSTING_READ(reg);
2698                 udelay(500);
2699
2700                 reg = FDI_RX_IIR(pipe);
2701                 temp = I915_READ(reg);
2702                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704                 if (temp & FDI_RX_SYMBOL_LOCK) {
2705                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2706                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2707                         break;
2708                 }
2709         }
2710         if (i == 4)
2711                 DRM_ERROR("FDI train 2 fail!\n");
2712
2713         DRM_DEBUG_KMS("FDI train done.\n");
2714 }
2715
2716 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2717 {
2718         struct drm_device *dev = intel_crtc->base.dev;
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         int pipe = intel_crtc->pipe;
2721         u32 reg, temp;
2722
2723         /* Write the TU size bits so error detection works */
2724         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2725                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2726
2727         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2728         reg = FDI_RX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         temp &= ~((0x7 << 19) | (0x7 << 16));
2731         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2732         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2733         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2734
2735         POSTING_READ(reg);
2736         udelay(200);
2737
2738         /* Switch from Rawclk to PCDclk */
2739         temp = I915_READ(reg);
2740         I915_WRITE(reg, temp | FDI_PCDCLK);
2741
2742         POSTING_READ(reg);
2743         udelay(200);
2744
2745         /* On Haswell, the PLL configuration for ports and pipes is handled
2746          * separately, as part of DDI setup */
2747         if (!IS_HASWELL(dev)) {
2748                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2749                 reg = FDI_TX_CTL(pipe);
2750                 temp = I915_READ(reg);
2751                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2752                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2753
2754                         POSTING_READ(reg);
2755                         udelay(100);
2756                 }
2757         }
2758 }
2759
2760 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2761 {
2762         struct drm_device *dev = intel_crtc->base.dev;
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         int pipe = intel_crtc->pipe;
2765         u32 reg, temp;
2766
2767         /* Switch from PCDclk to Rawclk */
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2771
2772         /* Disable CPU FDI TX PLL */
2773         reg = FDI_TX_CTL(pipe);
2774         temp = I915_READ(reg);
2775         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2776
2777         POSTING_READ(reg);
2778         udelay(100);
2779
2780         reg = FDI_RX_CTL(pipe);
2781         temp = I915_READ(reg);
2782         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2783
2784         /* Wait for the clocks to turn off. */
2785         POSTING_READ(reg);
2786         udelay(100);
2787 }
2788
2789 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2790 {
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         u32 flags = I915_READ(SOUTH_CHICKEN1);
2793
2794         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2795         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2796         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2797         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2798         POSTING_READ(SOUTH_CHICKEN1);
2799 }
2800 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2801 {
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805         int pipe = intel_crtc->pipe;
2806         u32 reg, temp;
2807
2808         /* disable CPU FDI tx and PCH FDI rx */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2812         POSTING_READ(reg);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~(0x7 << 16);
2817         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2819
2820         POSTING_READ(reg);
2821         udelay(100);
2822
2823         /* Ironlake workaround, disable clock pointer after downing FDI */
2824         if (HAS_PCH_IBX(dev)) {
2825                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2826                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2827                            I915_READ(FDI_RX_CHICKEN(pipe) &
2828                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2829         } else if (HAS_PCH_CPT(dev)) {
2830                 cpt_phase_pointer_disable(dev, pipe);
2831         }
2832
2833         /* still set train pattern 1 */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~FDI_LINK_TRAIN_NONE;
2837         temp |= FDI_LINK_TRAIN_PATTERN_1;
2838         I915_WRITE(reg, temp);
2839
2840         reg = FDI_RX_CTL(pipe);
2841         temp = I915_READ(reg);
2842         if (HAS_PCH_CPT(dev)) {
2843                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845         } else {
2846                 temp &= ~FDI_LINK_TRAIN_NONE;
2847                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848         }
2849         /* BPC in FDI rx is consistent with that in PIPECONF */
2850         temp &= ~(0x07 << 16);
2851         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2852         I915_WRITE(reg, temp);
2853
2854         POSTING_READ(reg);
2855         udelay(100);
2856 }
2857
2858 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859 {
2860         struct drm_device *dev = crtc->dev;
2861
2862         if (crtc->fb == NULL)
2863                 return;
2864
2865         mutex_lock(&dev->struct_mutex);
2866         intel_finish_fb(crtc->fb);
2867         mutex_unlock(&dev->struct_mutex);
2868 }
2869
2870 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2871 {
2872         struct drm_device *dev = crtc->dev;
2873         struct intel_encoder *intel_encoder;
2874
2875         /*
2876          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2877          * must be driven by its own crtc; no sharing is possible.
2878          */
2879         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2880
2881                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2882                  * CPU handles all others */
2883                 if (IS_HASWELL(dev)) {
2884                         /* It is still unclear how this will work on PPT, so throw up a warning */
2885                         WARN_ON(!HAS_PCH_LPT(dev));
2886
2887                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2888                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2889                                 return true;
2890                         } else {
2891                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2892                                               intel_encoder->type);
2893                                 return false;
2894                         }
2895                 }
2896
2897                 switch (intel_encoder->type) {
2898                 case INTEL_OUTPUT_EDP:
2899                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2900                                 return false;
2901                         continue;
2902                 }
2903         }
2904
2905         return true;
2906 }
2907
2908 /* Program iCLKIP clock to the desired frequency */
2909 static void lpt_program_iclkip(struct drm_crtc *crtc)
2910 {
2911         struct drm_device *dev = crtc->dev;
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2914         u32 temp;
2915
2916         /* It is necessary to ungate the pixclk gate prior to programming
2917          * the divisors, and gate it back when it is done.
2918          */
2919         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2920
2921         /* Disable SSCCTL */
2922         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2923                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2924                                         SBI_SSCCTL_DISABLE);
2925
2926         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927         if (crtc->mode.clock == 20000) {
2928                 auxdiv = 1;
2929                 divsel = 0x41;
2930                 phaseinc = 0x20;
2931         } else {
2932                 /* The iCLK virtual clock root frequency is in MHz,
2933                  * but the crtc->mode.clock in in KHz. To get the divisors,
2934                  * it is necessary to divide one by another, so we
2935                  * convert the virtual clock precision to KHz here for higher
2936                  * precision.
2937                  */
2938                 u32 iclk_virtual_root_freq = 172800 * 1000;
2939                 u32 iclk_pi_range = 64;
2940                 u32 desired_divisor, msb_divisor_value, pi_value;
2941
2942                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943                 msb_divisor_value = desired_divisor / iclk_pi_range;
2944                 pi_value = desired_divisor % iclk_pi_range;
2945
2946                 auxdiv = 0;
2947                 divsel = msb_divisor_value - 2;
2948                 phaseinc = pi_value;
2949         }
2950
2951         /* This should not happen with any sane values */
2952         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956
2957         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2958                         crtc->mode.clock,
2959                         auxdiv,
2960                         divsel,
2961                         phasedir,
2962                         phaseinc);
2963
2964         /* Program SSCDIVINTPHASE6 */
2965         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2966         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2972
2973         intel_sbi_write(dev_priv,
2974                         SBI_SSCDIVINTPHASE6,
2975                         temp);
2976
2977         /* Program SSCAUXDIV */
2978         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2979         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2980         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2981         intel_sbi_write(dev_priv,
2982                         SBI_SSCAUXDIV6,
2983                         temp);
2984
2985
2986         /* Enable modulator and associated divider */
2987         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2988         temp &= ~SBI_SSCCTL_DISABLE;
2989         intel_sbi_write(dev_priv,
2990                         SBI_SSCCTL6,
2991                         temp);
2992
2993         /* Wait for initialization time */
2994         udelay(24);
2995
2996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997 }
2998
2999 /*
3000  * Enable PCH resources required for PCH ports:
3001  *   - PCH PLLs
3002  *   - FDI training & RX/TX
3003  *   - update transcoder timings
3004  *   - DP transcoding bits
3005  *   - transcoder
3006  */
3007 static void ironlake_pch_enable(struct drm_crtc *crtc)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012         int pipe = intel_crtc->pipe;
3013         u32 reg, temp;
3014
3015         assert_transcoder_disabled(dev_priv, pipe);
3016
3017         /* For PCH output, training FDI link */
3018         dev_priv->display.fdi_link_train(crtc);
3019
3020         intel_enable_pch_pll(intel_crtc);
3021
3022         if (HAS_PCH_LPT(dev)) {
3023                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3024                 lpt_program_iclkip(crtc);
3025         } else if (HAS_PCH_CPT(dev)) {
3026                 u32 sel;
3027
3028                 temp = I915_READ(PCH_DPLL_SEL);
3029                 switch (pipe) {
3030                 default:
3031                 case 0:
3032                         temp |= TRANSA_DPLL_ENABLE;
3033                         sel = TRANSA_DPLLB_SEL;
3034                         break;
3035                 case 1:
3036                         temp |= TRANSB_DPLL_ENABLE;
3037                         sel = TRANSB_DPLLB_SEL;
3038                         break;
3039                 case 2:
3040                         temp |= TRANSC_DPLL_ENABLE;
3041                         sel = TRANSC_DPLLB_SEL;
3042                         break;
3043                 }
3044                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045                         temp |= sel;
3046                 else
3047                         temp &= ~sel;
3048                 I915_WRITE(PCH_DPLL_SEL, temp);
3049         }
3050
3051         /* set transcoder timing, panel must allow it */
3052         assert_panel_unlocked(dev_priv, pipe);
3053         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3056
3057         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3060         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3061
3062         if (!IS_HASWELL(dev))
3063                 intel_fdi_normal_train(crtc);
3064
3065         /* For PCH DP, enable TRANS_DP_CTL */
3066         if (HAS_PCH_CPT(dev) &&
3067             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3068              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3069                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3070                 reg = TRANS_DP_CTL(pipe);
3071                 temp = I915_READ(reg);
3072                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3073                           TRANS_DP_SYNC_MASK |
3074                           TRANS_DP_BPC_MASK);
3075                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3076                          TRANS_DP_ENH_FRAMING);
3077                 temp |= bpc << 9; /* same format but at 11:9 */
3078
3079                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3080                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3081                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3082                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3083
3084                 switch (intel_trans_dp_port_sel(crtc)) {
3085                 case PCH_DP_B:
3086                         temp |= TRANS_DP_PORT_SEL_B;
3087                         break;
3088                 case PCH_DP_C:
3089                         temp |= TRANS_DP_PORT_SEL_C;
3090                         break;
3091                 case PCH_DP_D:
3092                         temp |= TRANS_DP_PORT_SEL_D;
3093                         break;
3094                 default:
3095                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3096                         temp |= TRANS_DP_PORT_SEL_B;
3097                         break;
3098                 }
3099
3100                 I915_WRITE(reg, temp);
3101         }
3102
3103         intel_enable_transcoder(dev_priv, pipe);
3104 }
3105
3106 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3107 {
3108         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3109
3110         if (pll == NULL)
3111                 return;
3112
3113         if (pll->refcount == 0) {
3114                 WARN(1, "bad PCH PLL refcount\n");
3115                 return;
3116         }
3117
3118         --pll->refcount;
3119         intel_crtc->pch_pll = NULL;
3120 }
3121
3122 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3123 {
3124         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3125         struct intel_pch_pll *pll;
3126         int i;
3127
3128         pll = intel_crtc->pch_pll;
3129         if (pll) {
3130                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3131                               intel_crtc->base.base.id, pll->pll_reg);
3132                 goto prepare;
3133         }
3134
3135         if (HAS_PCH_IBX(dev_priv->dev)) {
3136                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3137                 i = intel_crtc->pipe;
3138                 pll = &dev_priv->pch_plls[i];
3139
3140                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3141                               intel_crtc->base.base.id, pll->pll_reg);
3142
3143                 goto found;
3144         }
3145
3146         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147                 pll = &dev_priv->pch_plls[i];
3148
3149                 /* Only want to check enabled timings first */
3150                 if (pll->refcount == 0)
3151                         continue;
3152
3153                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3154                     fp == I915_READ(pll->fp0_reg)) {
3155                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3156                                       intel_crtc->base.base.id,
3157                                       pll->pll_reg, pll->refcount, pll->active);
3158
3159                         goto found;
3160                 }
3161         }
3162
3163         /* Ok no matching timings, maybe there's a free one? */
3164         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3165                 pll = &dev_priv->pch_plls[i];
3166                 if (pll->refcount == 0) {
3167                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3168                                       intel_crtc->base.base.id, pll->pll_reg);
3169                         goto found;
3170                 }
3171         }
3172
3173         return NULL;
3174
3175 found:
3176         intel_crtc->pch_pll = pll;
3177         pll->refcount++;
3178         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3179 prepare: /* separate function? */
3180         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3181
3182         /* Wait for the clocks to stabilize before rewriting the regs */
3183         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3184         POSTING_READ(pll->pll_reg);
3185         udelay(150);
3186
3187         I915_WRITE(pll->fp0_reg, fp);
3188         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3189         pll->on = false;
3190         return pll;
3191 }
3192
3193 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3194 {
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3197         u32 temp;
3198
3199         temp = I915_READ(dslreg);
3200         udelay(500);
3201         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3202                 /* Without this, mode sets may fail silently on FDI */
3203                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3204                 udelay(250);
3205                 I915_WRITE(tc2reg, 0);
3206                 if (wait_for(I915_READ(dslreg) != temp, 5))
3207                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3208         }
3209 }
3210
3211 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3212 {
3213         struct drm_device *dev = crtc->dev;
3214         struct drm_i915_private *dev_priv = dev->dev_private;
3215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216         struct intel_encoder *encoder;
3217         int pipe = intel_crtc->pipe;
3218         int plane = intel_crtc->plane;
3219         u32 temp;
3220         bool is_pch_port;
3221
3222         WARN_ON(!crtc->enabled);
3223
3224         /* XXX: For compatability with the crtc helper code, call the encoder's
3225          * enable function unconditionally for now. */
3226         if (intel_crtc->active)
3227                 goto encoders;
3228
3229         intel_crtc->active = true;
3230         intel_update_watermarks(dev);
3231
3232         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233                 temp = I915_READ(PCH_LVDS);
3234                 if ((temp & LVDS_PORT_EN) == 0)
3235                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3236         }
3237
3238         is_pch_port = intel_crtc_driving_pch(crtc);
3239
3240         if (is_pch_port)
3241                 ironlake_fdi_pll_enable(intel_crtc);
3242         else
3243                 ironlake_fdi_disable(crtc);
3244
3245         /* Enable panel fitting for LVDS */
3246         if (dev_priv->pch_pf_size &&
3247             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3248                 /* Force use of hard-coded filter coefficients
3249                  * as some pre-programmed values are broken,
3250                  * e.g. x201.
3251                  */
3252                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3254                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3255         }
3256
3257         /*
3258          * On ILK+ LUT must be loaded before the pipe is running but with
3259          * clocks enabled
3260          */
3261         intel_crtc_load_lut(crtc);
3262
3263         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3264         intel_enable_plane(dev_priv, plane, pipe);
3265
3266         if (is_pch_port)
3267                 ironlake_pch_enable(crtc);
3268
3269         mutex_lock(&dev->struct_mutex);
3270         intel_update_fbc(dev);
3271         mutex_unlock(&dev->struct_mutex);
3272
3273         intel_crtc_update_cursor(crtc, true);
3274
3275 encoders:
3276         for_each_encoder_on_crtc(dev, crtc, encoder)
3277                 encoder->enable(encoder);
3278
3279         if (HAS_PCH_CPT(dev))
3280                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3281 }
3282
3283 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3284 {
3285         struct drm_device *dev = crtc->dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288         struct intel_encoder *encoder;
3289         int pipe = intel_crtc->pipe;
3290         int plane = intel_crtc->plane;
3291         u32 reg, temp;
3292
3293         /* XXX: For compatability with the crtc helper code, call the encoder's
3294          * disable function unconditionally for now. */
3295         for_each_encoder_on_crtc(dev, crtc, encoder)
3296                 encoder->disable(encoder);
3297
3298         if (!intel_crtc->active)
3299                 return;
3300
3301         intel_crtc_wait_for_pending_flips(crtc);
3302         drm_vblank_off(dev, pipe);
3303         intel_crtc_update_cursor(crtc, false);
3304
3305         intel_disable_plane(dev_priv, plane, pipe);
3306
3307         if (dev_priv->cfb_plane == plane)
3308                 intel_disable_fbc(dev);
3309
3310         intel_disable_pipe(dev_priv, pipe);
3311
3312         /* Disable PF */
3313         I915_WRITE(PF_CTL(pipe), 0);
3314         I915_WRITE(PF_WIN_SZ(pipe), 0);
3315
3316         ironlake_fdi_disable(crtc);
3317
3318         /* This is a horrible layering violation; we should be doing this in
3319          * the connector/encoder ->prepare instead, but we don't always have
3320          * enough information there about the config to know whether it will
3321          * actually be necessary or just cause undesired flicker.
3322          */
3323         intel_disable_pch_ports(dev_priv, pipe);
3324
3325         intel_disable_transcoder(dev_priv, pipe);
3326
3327         if (HAS_PCH_CPT(dev)) {
3328                 /* disable TRANS_DP_CTL */
3329                 reg = TRANS_DP_CTL(pipe);
3330                 temp = I915_READ(reg);
3331                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3332                 temp |= TRANS_DP_PORT_SEL_NONE;
3333                 I915_WRITE(reg, temp);
3334
3335                 /* disable DPLL_SEL */
3336                 temp = I915_READ(PCH_DPLL_SEL);
3337                 switch (pipe) {
3338                 case 0:
3339                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3340                         break;
3341                 case 1:
3342                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3343                         break;
3344                 case 2:
3345                         /* C shares PLL A or B */
3346                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3347                         break;
3348                 default:
3349                         BUG(); /* wtf */
3350                 }
3351                 I915_WRITE(PCH_DPLL_SEL, temp);
3352         }
3353
3354         /* disable PCH DPLL */
3355         intel_disable_pch_pll(intel_crtc);
3356
3357         ironlake_fdi_pll_disable(intel_crtc);
3358
3359         intel_crtc->active = false;
3360         intel_update_watermarks(dev);
3361
3362         mutex_lock(&dev->struct_mutex);
3363         intel_update_fbc(dev);
3364         mutex_unlock(&dev->struct_mutex);
3365 }
3366
3367 static void ironlake_crtc_off(struct drm_crtc *crtc)
3368 {
3369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370         intel_put_pch_pll(intel_crtc);
3371 }
3372
3373 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3374 {
3375         if (!enable && intel_crtc->overlay) {
3376                 struct drm_device *dev = intel_crtc->base.dev;
3377                 struct drm_i915_private *dev_priv = dev->dev_private;
3378
3379                 mutex_lock(&dev->struct_mutex);
3380                 dev_priv->mm.interruptible = false;
3381                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3382                 dev_priv->mm.interruptible = true;
3383                 mutex_unlock(&dev->struct_mutex);
3384         }
3385
3386         /* Let userspace switch the overlay on again. In most cases userspace
3387          * has to recompute where to put it anyway.
3388          */
3389 }
3390
3391 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         struct intel_encoder *encoder;
3397         int pipe = intel_crtc->pipe;
3398         int plane = intel_crtc->plane;
3399
3400         WARN_ON(!crtc->enabled);
3401
3402         /* XXX: For compatability with the crtc helper code, call the encoder's
3403          * enable function unconditionally for now. */
3404         if (intel_crtc->active)
3405                 goto encoders;
3406
3407         intel_crtc->active = true;
3408         intel_update_watermarks(dev);
3409
3410         intel_enable_pll(dev_priv, pipe);
3411         intel_enable_pipe(dev_priv, pipe, false);
3412         intel_enable_plane(dev_priv, plane, pipe);
3413
3414         intel_crtc_load_lut(crtc);
3415         intel_update_fbc(dev);
3416
3417         /* Give the overlay scaler a chance to enable if it's on this pipe */
3418         intel_crtc_dpms_overlay(intel_crtc, true);
3419         intel_crtc_update_cursor(crtc, true);
3420
3421 encoders:
3422         for_each_encoder_on_crtc(dev, crtc, encoder)
3423                 encoder->enable(encoder);
3424 }
3425
3426 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3427 {
3428         struct drm_device *dev = crtc->dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431         struct intel_encoder *encoder;
3432         int pipe = intel_crtc->pipe;
3433         int plane = intel_crtc->plane;
3434
3435         /* XXX: For compatability with the crtc helper code, call the encoder's
3436          * disable function unconditionally for now. */
3437         for_each_encoder_on_crtc(dev, crtc, encoder)
3438                 encoder->disable(encoder);
3439
3440         if (!intel_crtc->active)
3441                 return;
3442
3443         /* Give the overlay scaler a chance to disable if it's on this pipe */
3444         intel_crtc_wait_for_pending_flips(crtc);
3445         drm_vblank_off(dev, pipe);
3446         intel_crtc_dpms_overlay(intel_crtc, false);
3447         intel_crtc_update_cursor(crtc, false);
3448
3449         if (dev_priv->cfb_plane == plane)
3450                 intel_disable_fbc(dev);
3451
3452         intel_disable_plane(dev_priv, plane, pipe);
3453         intel_disable_pipe(dev_priv, pipe);
3454         intel_disable_pll(dev_priv, pipe);
3455
3456         intel_crtc->active = false;
3457         intel_update_fbc(dev);
3458         intel_update_watermarks(dev);
3459 }
3460
3461 static void i9xx_crtc_off(struct drm_crtc *crtc)
3462 {
3463 }
3464
3465 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3466                                     bool enabled)
3467 {
3468         struct drm_device *dev = crtc->dev;
3469         struct drm_i915_master_private *master_priv;
3470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3471         int pipe = intel_crtc->pipe;
3472
3473         if (!dev->primary->master)
3474                 return;
3475
3476         master_priv = dev->primary->master->driver_priv;
3477         if (!master_priv->sarea_priv)
3478                 return;
3479
3480         switch (pipe) {
3481         case 0:
3482                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3483                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3484                 break;
3485         case 1:
3486                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3487                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3488                 break;
3489         default:
3490                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3491                 break;
3492         }
3493 }
3494
3495 /**
3496  * Sets the power management mode of the pipe and plane.
3497  */
3498 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3499 {
3500         struct drm_device *dev = crtc->dev;
3501         struct drm_i915_private *dev_priv = dev->dev_private;
3502         struct intel_encoder *intel_encoder;
3503         bool enable = false;
3504
3505         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3506                 enable |= intel_encoder->connectors_active;
3507
3508         if (enable)
3509                 dev_priv->display.crtc_enable(crtc);
3510         else
3511                 dev_priv->display.crtc_disable(crtc);
3512
3513         intel_crtc_update_sarea(crtc, enable);
3514 }
3515
3516 static void intel_crtc_noop(struct drm_crtc *crtc)
3517 {
3518 }
3519
3520 static void intel_crtc_disable(struct drm_crtc *crtc)
3521 {
3522         struct drm_device *dev = crtc->dev;
3523         struct drm_connector *connector;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525
3526         /* crtc should still be enabled when we disable it. */
3527         WARN_ON(!crtc->enabled);
3528
3529         dev_priv->display.crtc_disable(crtc);
3530         intel_crtc_update_sarea(crtc, false);
3531         dev_priv->display.off(crtc);
3532
3533         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3534         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3535
3536         if (crtc->fb) {
3537                 mutex_lock(&dev->struct_mutex);
3538                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3539                 mutex_unlock(&dev->struct_mutex);
3540                 crtc->fb = NULL;
3541         }
3542
3543         /* Update computed state. */
3544         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3545                 if (!connector->encoder || !connector->encoder->crtc)
3546                         continue;
3547
3548                 if (connector->encoder->crtc != crtc)
3549                         continue;
3550
3551                 connector->dpms = DRM_MODE_DPMS_OFF;
3552                 to_intel_encoder(connector->encoder)->connectors_active = false;
3553         }
3554 }
3555
3556 void intel_encoder_disable(struct drm_encoder *encoder)
3557 {
3558 }
3559
3560 void intel_encoder_destroy(struct drm_encoder *encoder)
3561 {
3562         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3563
3564         drm_encoder_cleanup(encoder);
3565         kfree(intel_encoder);
3566 }
3567
3568 /* Simple dpms helper for encodres with just one connector, no cloning and only
3569  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3570  * state of the entire output pipe. */
3571 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3572 {
3573         if (mode == DRM_MODE_DPMS_ON) {
3574                 encoder->connectors_active = true;
3575
3576                 intel_crtc_update_dpms(encoder->base.crtc);
3577         } else {
3578                 encoder->connectors_active = false;
3579
3580                 intel_crtc_update_dpms(encoder->base.crtc);
3581         }
3582 }
3583
3584 /* Cross check the actual hw state with our own modeset state tracking (and it's
3585  * internal consistency). */
3586 void intel_connector_check_state(struct intel_connector *connector)
3587 {
3588         if (connector->get_hw_state(connector)) {
3589                 struct intel_encoder *encoder = connector->encoder;
3590                 struct drm_crtc *crtc;
3591                 bool encoder_enabled;
3592                 enum pipe pipe;
3593
3594                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3595                               connector->base.base.id,
3596                               drm_get_connector_name(&connector->base));
3597
3598                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3599                      "wrong connector dpms state\n");
3600                 WARN(connector->base.encoder != &encoder->base,
3601                      "active connector not linked to encoder\n");
3602                 WARN(!encoder->connectors_active,
3603                      "encoder->connectors_active not set\n");
3604
3605                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3606                 WARN(!encoder_enabled, "encoder not enabled\n");
3607                 if (WARN_ON(!encoder->base.crtc))
3608                         return;
3609
3610                 crtc = encoder->base.crtc;
3611
3612                 WARN(!crtc->enabled, "crtc not enabled\n");
3613                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3614                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3615                      "encoder active on the wrong pipe\n");
3616         }
3617 }
3618
3619 /* Even simpler default implementation, if there's really no special case to
3620  * consider. */
3621 void intel_connector_dpms(struct drm_connector *connector, int mode)
3622 {
3623         struct intel_encoder *encoder = intel_attached_encoder(connector);
3624
3625         /* All the simple cases only support two dpms states. */
3626         if (mode != DRM_MODE_DPMS_ON)
3627                 mode = DRM_MODE_DPMS_OFF;
3628
3629         if (mode == connector->dpms)
3630                 return;
3631
3632         connector->dpms = mode;
3633
3634         /* Only need to change hw state when actually enabled */
3635         if (encoder->base.crtc)
3636                 intel_encoder_dpms(encoder, mode);
3637         else
3638                 encoder->connectors_active = false;
3639
3640         intel_connector_check_state(to_intel_connector(connector));
3641 }
3642
3643 /* Simple connector->get_hw_state implementation for encoders that support only
3644  * one connector and no cloning and hence the encoder state determines the state
3645  * of the connector. */
3646 bool intel_connector_get_hw_state(struct intel_connector *connector)
3647 {
3648         enum pipe pipe = 0;
3649         struct intel_encoder *encoder = connector->encoder;
3650
3651         return encoder->get_hw_state(encoder, &pipe);
3652 }
3653
3654 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3655                                   const struct drm_display_mode *mode,
3656                                   struct drm_display_mode *adjusted_mode)
3657 {
3658         struct drm_device *dev = crtc->dev;
3659
3660         if (HAS_PCH_SPLIT(dev)) {
3661                 /* FDI link clock is fixed at 2.7G */
3662                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3663                         return false;
3664         }
3665
3666         /* All interlaced capable intel hw wants timings in frames. Note though
3667          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3668          * timings, so we need to be careful not to clobber these.*/
3669         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3670                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3671
3672         return true;
3673 }
3674
3675 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3676 {
3677         return 400000; /* FIXME */
3678 }
3679
3680 static int i945_get_display_clock_speed(struct drm_device *dev)
3681 {
3682         return 400000;
3683 }
3684
3685 static int i915_get_display_clock_speed(struct drm_device *dev)
3686 {
3687         return 333000;
3688 }
3689
3690 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3691 {
3692         return 200000;
3693 }
3694
3695 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3696 {
3697         u16 gcfgc = 0;
3698
3699         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3700
3701         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3702                 return 133000;
3703         else {
3704                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3705                 case GC_DISPLAY_CLOCK_333_MHZ:
3706                         return 333000;
3707                 default:
3708                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3709                         return 190000;
3710                 }
3711         }
3712 }
3713
3714 static int i865_get_display_clock_speed(struct drm_device *dev)
3715 {
3716         return 266000;
3717 }
3718
3719 static int i855_get_display_clock_speed(struct drm_device *dev)
3720 {
3721         u16 hpllcc = 0;
3722         /* Assume that the hardware is in the high speed state.  This
3723          * should be the default.
3724          */
3725         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3726         case GC_CLOCK_133_200:
3727         case GC_CLOCK_100_200:
3728                 return 200000;
3729         case GC_CLOCK_166_250:
3730                 return 250000;
3731         case GC_CLOCK_100_133:
3732                 return 133000;
3733         }
3734
3735         /* Shouldn't happen */
3736         return 0;
3737 }
3738
3739 static int i830_get_display_clock_speed(struct drm_device *dev)
3740 {
3741         return 133000;
3742 }
3743
3744 struct fdi_m_n {
3745         u32        tu;
3746         u32        gmch_m;
3747         u32        gmch_n;
3748         u32        link_m;
3749         u32        link_n;
3750 };
3751
3752 static void
3753 fdi_reduce_ratio(u32 *num, u32 *den)
3754 {
3755         while (*num > 0xffffff || *den > 0xffffff) {
3756                 *num >>= 1;
3757                 *den >>= 1;
3758         }
3759 }
3760
3761 static void
3762 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3763                      int link_clock, struct fdi_m_n *m_n)
3764 {
3765         m_n->tu = 64; /* default size */
3766
3767         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3768         m_n->gmch_m = bits_per_pixel * pixel_clock;
3769         m_n->gmch_n = link_clock * nlanes * 8;
3770         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3771
3772         m_n->link_m = pixel_clock;
3773         m_n->link_n = link_clock;
3774         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3775 }
3776
3777 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3778 {
3779         if (i915_panel_use_ssc >= 0)
3780                 return i915_panel_use_ssc != 0;
3781         return dev_priv->lvds_use_ssc
3782                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3783 }
3784
3785 /**
3786  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3787  * @crtc: CRTC structure
3788  * @mode: requested mode
3789  *
3790  * A pipe may be connected to one or more outputs.  Based on the depth of the
3791  * attached framebuffer, choose a good color depth to use on the pipe.
3792  *
3793  * If possible, match the pipe depth to the fb depth.  In some cases, this
3794  * isn't ideal, because the connected output supports a lesser or restricted
3795  * set of depths.  Resolve that here:
3796  *    LVDS typically supports only 6bpc, so clamp down in that case
3797  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3798  *    Displays may support a restricted set as well, check EDID and clamp as
3799  *      appropriate.
3800  *    DP may want to dither down to 6bpc to fit larger modes
3801  *
3802  * RETURNS:
3803  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3804  * true if they don't match).
3805  */
3806 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3807                                          struct drm_framebuffer *fb,
3808                                          unsigned int *pipe_bpp,
3809                                          struct drm_display_mode *mode)
3810 {
3811         struct drm_device *dev = crtc->dev;
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813         struct drm_connector *connector;
3814         struct intel_encoder *intel_encoder;
3815         unsigned int display_bpc = UINT_MAX, bpc;
3816
3817         /* Walk the encoders & connectors on this crtc, get min bpc */
3818         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3819
3820                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3821                         unsigned int lvds_bpc;
3822
3823                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3824                             LVDS_A3_POWER_UP)
3825                                 lvds_bpc = 8;
3826                         else
3827                                 lvds_bpc = 6;
3828
3829                         if (lvds_bpc < display_bpc) {
3830                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3831                                 display_bpc = lvds_bpc;
3832                         }
3833                         continue;
3834                 }
3835
3836                 /* Not one of the known troublemakers, check the EDID */
3837                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3838                                     head) {
3839                         if (connector->encoder != &intel_encoder->base)
3840                                 continue;
3841
3842                         /* Don't use an invalid EDID bpc value */
3843                         if (connector->display_info.bpc &&
3844                             connector->display_info.bpc < display_bpc) {
3845                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3846                                 display_bpc = connector->display_info.bpc;
3847                         }
3848                 }
3849
3850                 /*
3851                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3852                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3853                  */
3854                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3855                         if (display_bpc > 8 && display_bpc < 12) {
3856                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3857                                 display_bpc = 12;
3858                         } else {
3859                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3860                                 display_bpc = 8;
3861                         }
3862                 }
3863         }
3864
3865         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3866                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3867                 display_bpc = 6;
3868         }
3869
3870         /*
3871          * We could just drive the pipe at the highest bpc all the time and
3872          * enable dithering as needed, but that costs bandwidth.  So choose
3873          * the minimum value that expresses the full color range of the fb but
3874          * also stays within the max display bpc discovered above.
3875          */
3876
3877         switch (fb->depth) {
3878         case 8:
3879                 bpc = 8; /* since we go through a colormap */
3880                 break;
3881         case 15:
3882         case 16:
3883                 bpc = 6; /* min is 18bpp */
3884                 break;
3885         case 24:
3886                 bpc = 8;
3887                 break;
3888         case 30:
3889                 bpc = 10;
3890                 break;
3891         case 48:
3892                 bpc = 12;
3893                 break;
3894         default:
3895                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3896                 bpc = min((unsigned int)8, display_bpc);
3897                 break;
3898         }
3899
3900         display_bpc = min(display_bpc, bpc);
3901
3902         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3903                       bpc, display_bpc);
3904
3905         *pipe_bpp = display_bpc * 3;
3906
3907         return display_bpc != bpc;
3908 }
3909
3910 static int vlv_get_refclk(struct drm_crtc *crtc)
3911 {
3912         struct drm_device *dev = crtc->dev;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         int refclk = 27000; /* for DP & HDMI */
3915
3916         return 100000; /* only one validated so far */
3917
3918         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3919                 refclk = 96000;
3920         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3921                 if (intel_panel_use_ssc(dev_priv))
3922                         refclk = 100000;
3923                 else
3924                         refclk = 96000;
3925         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3926                 refclk = 100000;
3927         }
3928
3929         return refclk;
3930 }
3931
3932 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3933 {
3934         struct drm_device *dev = crtc->dev;
3935         struct drm_i915_private *dev_priv = dev->dev_private;
3936         int refclk;
3937
3938         if (IS_VALLEYVIEW(dev)) {
3939                 refclk = vlv_get_refclk(crtc);
3940         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3941             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3942                 refclk = dev_priv->lvds_ssc_freq * 1000;
3943                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3944                               refclk / 1000);
3945         } else if (!IS_GEN2(dev)) {
3946                 refclk = 96000;
3947         } else {
3948                 refclk = 48000;
3949         }
3950
3951         return refclk;
3952 }
3953
3954 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3955                                       intel_clock_t *clock)
3956 {
3957         /* SDVO TV has fixed PLL values depend on its clock range,
3958            this mirrors vbios setting. */
3959         if (adjusted_mode->clock >= 100000
3960             && adjusted_mode->clock < 140500) {
3961                 clock->p1 = 2;
3962                 clock->p2 = 10;
3963                 clock->n = 3;
3964                 clock->m1 = 16;
3965                 clock->m2 = 8;
3966         } else if (adjusted_mode->clock >= 140500
3967                    && adjusted_mode->clock <= 200000) {
3968                 clock->p1 = 1;
3969                 clock->p2 = 10;
3970                 clock->n = 6;
3971                 clock->m1 = 12;
3972                 clock->m2 = 8;
3973         }
3974 }
3975
3976 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3977                                      intel_clock_t *clock,
3978                                      intel_clock_t *reduced_clock)
3979 {
3980         struct drm_device *dev = crtc->dev;
3981         struct drm_i915_private *dev_priv = dev->dev_private;
3982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3983         int pipe = intel_crtc->pipe;
3984         u32 fp, fp2 = 0;
3985
3986         if (IS_PINEVIEW(dev)) {
3987                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3988                 if (reduced_clock)
3989                         fp2 = (1 << reduced_clock->n) << 16 |
3990                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3991         } else {
3992                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3993                 if (reduced_clock)
3994                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3995                                 reduced_clock->m2;
3996         }
3997
3998         I915_WRITE(FP0(pipe), fp);
3999
4000         intel_crtc->lowfreq_avail = false;
4001         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4002             reduced_clock && i915_powersave) {
4003                 I915_WRITE(FP1(pipe), fp2);
4004                 intel_crtc->lowfreq_avail = true;
4005         } else {
4006                 I915_WRITE(FP1(pipe), fp);
4007         }
4008 }
4009
4010 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4011                               struct drm_display_mode *adjusted_mode)
4012 {
4013         struct drm_device *dev = crtc->dev;
4014         struct drm_i915_private *dev_priv = dev->dev_private;
4015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4016         int pipe = intel_crtc->pipe;
4017         u32 temp;
4018
4019         temp = I915_READ(LVDS);
4020         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4021         if (pipe == 1) {
4022                 temp |= LVDS_PIPEB_SELECT;
4023         } else {
4024                 temp &= ~LVDS_PIPEB_SELECT;
4025         }
4026         /* set the corresponsding LVDS_BORDER bit */
4027         temp |= dev_priv->lvds_border_bits;
4028         /* Set the B0-B3 data pairs corresponding to whether we're going to
4029          * set the DPLLs for dual-channel mode or not.
4030          */
4031         if (clock->p2 == 7)
4032                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4033         else
4034                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4035
4036         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4037          * appropriately here, but we need to look more thoroughly into how
4038          * panels behave in the two modes.
4039          */
4040         /* set the dithering flag on LVDS as needed */
4041         if (INTEL_INFO(dev)->gen >= 4) {
4042                 if (dev_priv->lvds_dither)
4043                         temp |= LVDS_ENABLE_DITHER;
4044                 else
4045                         temp &= ~LVDS_ENABLE_DITHER;
4046         }
4047         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4048         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4049                 temp |= LVDS_HSYNC_POLARITY;
4050         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4051                 temp |= LVDS_VSYNC_POLARITY;
4052         I915_WRITE(LVDS, temp);
4053 }
4054
4055 static void vlv_update_pll(struct drm_crtc *crtc,
4056                            struct drm_display_mode *mode,
4057                            struct drm_display_mode *adjusted_mode,
4058                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4059                            int refclk, int num_connectors)
4060 {
4061         struct drm_device *dev = crtc->dev;
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4064         int pipe = intel_crtc->pipe;
4065         u32 dpll, mdiv, pdiv;
4066         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4067         bool is_hdmi;
4068
4069         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4070
4071         bestn = clock->n;
4072         bestm1 = clock->m1;
4073         bestm2 = clock->m2;
4074         bestp1 = clock->p1;
4075         bestp2 = clock->p2;
4076
4077         /* Enable DPIO clock input */
4078         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4079                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4080         I915_WRITE(DPLL(pipe), dpll);
4081         POSTING_READ(DPLL(pipe));
4082
4083         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4084         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4085         mdiv |= ((bestn << DPIO_N_SHIFT));
4086         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4087         mdiv |= (1 << DPIO_K_SHIFT);
4088         mdiv |= DPIO_ENABLE_CALIBRATION;
4089         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4090
4091         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4092
4093         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4094                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4095                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4096         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4097
4098         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4099
4100         dpll |= DPLL_VCO_ENABLE;
4101         I915_WRITE(DPLL(pipe), dpll);
4102         POSTING_READ(DPLL(pipe));
4103         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4104                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4105
4106         if (is_hdmi) {
4107                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4108
4109                 if (temp > 1)
4110                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4111                 else
4112                         temp = 0;
4113
4114                 I915_WRITE(DPLL_MD(pipe), temp);
4115                 POSTING_READ(DPLL_MD(pipe));
4116         }
4117
4118         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4119 }
4120
4121 static void i9xx_update_pll(struct drm_crtc *crtc,
4122                             struct drm_display_mode *mode,
4123                             struct drm_display_mode *adjusted_mode,
4124                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4125                             int num_connectors)
4126 {
4127         struct drm_device *dev = crtc->dev;
4128         struct drm_i915_private *dev_priv = dev->dev_private;
4129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130         int pipe = intel_crtc->pipe;
4131         u32 dpll;
4132         bool is_sdvo;
4133
4134         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4135                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4136
4137         dpll = DPLL_VGA_MODE_DIS;
4138
4139         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4140                 dpll |= DPLLB_MODE_LVDS;
4141         else
4142                 dpll |= DPLLB_MODE_DAC_SERIAL;
4143         if (is_sdvo) {
4144                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4145                 if (pixel_multiplier > 1) {
4146                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4147                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4148                 }
4149                 dpll |= DPLL_DVO_HIGH_SPEED;
4150         }
4151         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4152                 dpll |= DPLL_DVO_HIGH_SPEED;
4153
4154         /* compute bitmask from p1 value */
4155         if (IS_PINEVIEW(dev))
4156                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4157         else {
4158                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4159                 if (IS_G4X(dev) && reduced_clock)
4160                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4161         }
4162         switch (clock->p2) {
4163         case 5:
4164                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4165                 break;
4166         case 7:
4167                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4168                 break;
4169         case 10:
4170                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4171                 break;
4172         case 14:
4173                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4174                 break;
4175         }
4176         if (INTEL_INFO(dev)->gen >= 4)
4177                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4178
4179         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4180                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4181         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4182                 /* XXX: just matching BIOS for now */
4183                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4184                 dpll |= 3;
4185         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4186                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4187                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4188         else
4189                 dpll |= PLL_REF_INPUT_DREFCLK;
4190
4191         dpll |= DPLL_VCO_ENABLE;
4192         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4193         POSTING_READ(DPLL(pipe));
4194         udelay(150);
4195
4196         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4197          * This is an exception to the general rule that mode_set doesn't turn
4198          * things on.
4199          */
4200         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4201                 intel_update_lvds(crtc, clock, adjusted_mode);
4202
4203         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4204                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4205
4206         I915_WRITE(DPLL(pipe), dpll);
4207
4208         /* Wait for the clocks to stabilize. */
4209         POSTING_READ(DPLL(pipe));
4210         udelay(150);
4211
4212         if (INTEL_INFO(dev)->gen >= 4) {
4213                 u32 temp = 0;
4214                 if (is_sdvo) {
4215                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4216                         if (temp > 1)
4217                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4218                         else
4219                                 temp = 0;
4220                 }
4221                 I915_WRITE(DPLL_MD(pipe), temp);
4222         } else {
4223                 /* The pixel multiplier can only be updated once the
4224                  * DPLL is enabled and the clocks are stable.
4225                  *
4226                  * So write it again.
4227                  */
4228                 I915_WRITE(DPLL(pipe), dpll);
4229         }
4230 }
4231
4232 static void i8xx_update_pll(struct drm_crtc *crtc,
4233                             struct drm_display_mode *adjusted_mode,
4234                             intel_clock_t *clock,
4235                             int num_connectors)
4236 {
4237         struct drm_device *dev = crtc->dev;
4238         struct drm_i915_private *dev_priv = dev->dev_private;
4239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4240         int pipe = intel_crtc->pipe;
4241         u32 dpll;
4242
4243         dpll = DPLL_VGA_MODE_DIS;
4244
4245         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4246                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4247         } else {
4248                 if (clock->p1 == 2)
4249                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4250                 else
4251                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4252                 if (clock->p2 == 4)
4253                         dpll |= PLL_P2_DIVIDE_BY_4;
4254         }
4255
4256         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4257                 /* XXX: just matching BIOS for now */
4258                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4259                 dpll |= 3;
4260         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4261                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4262                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4263         else
4264                 dpll |= PLL_REF_INPUT_DREFCLK;
4265
4266         dpll |= DPLL_VCO_ENABLE;
4267         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4268         POSTING_READ(DPLL(pipe));
4269         udelay(150);
4270
4271         I915_WRITE(DPLL(pipe), dpll);
4272
4273         /* Wait for the clocks to stabilize. */
4274         POSTING_READ(DPLL(pipe));
4275         udelay(150);
4276
4277         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4278          * This is an exception to the general rule that mode_set doesn't turn
4279          * things on.
4280          */
4281         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4282                 intel_update_lvds(crtc, clock, adjusted_mode);
4283
4284         /* The pixel multiplier can only be updated once the
4285          * DPLL is enabled and the clocks are stable.
4286          *
4287          * So write it again.
4288          */
4289         I915_WRITE(DPLL(pipe), dpll);
4290 }
4291
4292 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4293                               struct drm_display_mode *mode,
4294                               struct drm_display_mode *adjusted_mode,
4295                               int x, int y,
4296                               struct drm_framebuffer *fb)
4297 {
4298         struct drm_device *dev = crtc->dev;
4299         struct drm_i915_private *dev_priv = dev->dev_private;
4300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301         int pipe = intel_crtc->pipe;
4302         int plane = intel_crtc->plane;
4303         int refclk, num_connectors = 0;
4304         intel_clock_t clock, reduced_clock;
4305         u32 dspcntr, pipeconf, vsyncshift;
4306         bool ok, has_reduced_clock = false, is_sdvo = false;
4307         bool is_lvds = false, is_tv = false, is_dp = false;
4308         struct intel_encoder *encoder;
4309         const intel_limit_t *limit;
4310         int ret;
4311
4312         for_each_encoder_on_crtc(dev, crtc, encoder) {
4313                 switch (encoder->type) {
4314                 case INTEL_OUTPUT_LVDS:
4315                         is_lvds = true;
4316                         break;
4317                 case INTEL_OUTPUT_SDVO:
4318                 case INTEL_OUTPUT_HDMI:
4319                         is_sdvo = true;
4320                         if (encoder->needs_tv_clock)
4321                                 is_tv = true;
4322                         break;
4323                 case INTEL_OUTPUT_TVOUT:
4324                         is_tv = true;
4325                         break;
4326                 case INTEL_OUTPUT_DISPLAYPORT:
4327                         is_dp = true;
4328                         break;
4329                 }
4330
4331                 num_connectors++;
4332         }
4333
4334         refclk = i9xx_get_refclk(crtc, num_connectors);
4335
4336         /*
4337          * Returns a set of divisors for the desired target clock with the given
4338          * refclk, or FALSE.  The returned values represent the clock equation:
4339          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4340          */
4341         limit = intel_limit(crtc, refclk);
4342         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4343                              &clock);
4344         if (!ok) {
4345                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4346                 return -EINVAL;
4347         }
4348
4349         /* Ensure that the cursor is valid for the new mode before changing... */
4350         intel_crtc_update_cursor(crtc, true);
4351
4352         if (is_lvds && dev_priv->lvds_downclock_avail) {
4353                 /*
4354                  * Ensure we match the reduced clock's P to the target clock.
4355                  * If the clocks don't match, we can't switch the display clock
4356                  * by using the FP0/FP1. In such case we will disable the LVDS
4357                  * downclock feature.
4358                 */
4359                 has_reduced_clock = limit->find_pll(limit, crtc,
4360                                                     dev_priv->lvds_downclock,
4361                                                     refclk,
4362                                                     &clock,
4363                                                     &reduced_clock);
4364         }
4365
4366         if (is_sdvo && is_tv)
4367                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4368
4369         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4370                                  &reduced_clock : NULL);
4371
4372         if (IS_GEN2(dev))
4373                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4374         else if (IS_VALLEYVIEW(dev))
4375                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4376                                refclk, num_connectors);
4377         else
4378                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4379                                 has_reduced_clock ? &reduced_clock : NULL,
4380                                 num_connectors);
4381
4382         /* setup pipeconf */
4383         pipeconf = I915_READ(PIPECONF(pipe));
4384
4385         /* Set up the display plane register */
4386         dspcntr = DISPPLANE_GAMMA_ENABLE;
4387
4388         if (pipe == 0)
4389                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4390         else
4391                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4392
4393         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4394                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4395                  * core speed.
4396                  *
4397                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4398                  * pipe == 0 check?
4399                  */
4400                 if (mode->clock >
4401                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4402                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4403                 else
4404                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4405         }
4406
4407         /* default to 8bpc */
4408         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4409         if (is_dp) {
4410                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4411                         pipeconf |= PIPECONF_BPP_6 |
4412                                     PIPECONF_DITHER_EN |
4413                                     PIPECONF_DITHER_TYPE_SP;
4414                 }
4415         }
4416
4417         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4418         drm_mode_debug_printmodeline(mode);
4419
4420         if (HAS_PIPE_CXSR(dev)) {
4421                 if (intel_crtc->lowfreq_avail) {
4422                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4423                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4424                 } else {
4425                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4426                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4427                 }
4428         }
4429
4430         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4431         if (!IS_GEN2(dev) &&
4432             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4433                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4434                 /* the chip adds 2 halflines automatically */
4435                 adjusted_mode->crtc_vtotal -= 1;
4436                 adjusted_mode->crtc_vblank_end -= 1;
4437                 vsyncshift = adjusted_mode->crtc_hsync_start
4438                              - adjusted_mode->crtc_htotal/2;
4439         } else {
4440                 pipeconf |= PIPECONF_PROGRESSIVE;
4441                 vsyncshift = 0;
4442         }
4443
4444         if (!IS_GEN3(dev))
4445                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4446
4447         I915_WRITE(HTOTAL(pipe),
4448                    (adjusted_mode->crtc_hdisplay - 1) |
4449                    ((adjusted_mode->crtc_htotal - 1) << 16));
4450         I915_WRITE(HBLANK(pipe),
4451                    (adjusted_mode->crtc_hblank_start - 1) |
4452                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4453         I915_WRITE(HSYNC(pipe),
4454                    (adjusted_mode->crtc_hsync_start - 1) |
4455                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4456
4457         I915_WRITE(VTOTAL(pipe),
4458                    (adjusted_mode->crtc_vdisplay - 1) |
4459                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4460         I915_WRITE(VBLANK(pipe),
4461                    (adjusted_mode->crtc_vblank_start - 1) |
4462                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4463         I915_WRITE(VSYNC(pipe),
4464                    (adjusted_mode->crtc_vsync_start - 1) |
4465                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4466
4467         /* pipesrc and dspsize control the size that is scaled from,
4468          * which should always be the user's requested size.
4469          */
4470         I915_WRITE(DSPSIZE(plane),
4471                    ((mode->vdisplay - 1) << 16) |
4472                    (mode->hdisplay - 1));
4473         I915_WRITE(DSPPOS(plane), 0);
4474         I915_WRITE(PIPESRC(pipe),
4475                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4476
4477         I915_WRITE(PIPECONF(pipe), pipeconf);
4478         POSTING_READ(PIPECONF(pipe));
4479         intel_enable_pipe(dev_priv, pipe, false);
4480
4481         intel_wait_for_vblank(dev, pipe);
4482
4483         I915_WRITE(DSPCNTR(plane), dspcntr);
4484         POSTING_READ(DSPCNTR(plane));
4485
4486         ret = intel_pipe_set_base(crtc, x, y, fb);
4487
4488         intel_update_watermarks(dev);
4489
4490         return ret;
4491 }
4492
4493 /*
4494  * Initialize reference clocks when the driver loads
4495  */
4496 void ironlake_init_pch_refclk(struct drm_device *dev)
4497 {
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         struct drm_mode_config *mode_config = &dev->mode_config;
4500         struct intel_encoder *encoder;
4501         u32 temp;
4502         bool has_lvds = false;
4503         bool has_cpu_edp = false;
4504         bool has_pch_edp = false;
4505         bool has_panel = false;
4506         bool has_ck505 = false;
4507         bool can_ssc = false;
4508
4509         /* We need to take the global config into account */
4510         list_for_each_entry(encoder, &mode_config->encoder_list,
4511                             base.head) {
4512                 switch (encoder->type) {
4513                 case INTEL_OUTPUT_LVDS:
4514                         has_panel = true;
4515                         has_lvds = true;
4516                         break;
4517                 case INTEL_OUTPUT_EDP:
4518                         has_panel = true;
4519                         if (intel_encoder_is_pch_edp(&encoder->base))
4520                                 has_pch_edp = true;
4521                         else
4522                                 has_cpu_edp = true;
4523                         break;
4524                 }
4525         }
4526
4527         if (HAS_PCH_IBX(dev)) {
4528                 has_ck505 = dev_priv->display_clock_mode;
4529                 can_ssc = has_ck505;
4530         } else {
4531                 has_ck505 = false;
4532                 can_ssc = true;
4533         }
4534
4535         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4536                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4537                       has_ck505);
4538
4539         /* Ironlake: try to setup display ref clock before DPLL
4540          * enabling. This is only under driver's control after
4541          * PCH B stepping, previous chipset stepping should be
4542          * ignoring this setting.
4543          */
4544         temp = I915_READ(PCH_DREF_CONTROL);
4545         /* Always enable nonspread source */
4546         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4547
4548         if (has_ck505)
4549                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4550         else
4551                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4552
4553         if (has_panel) {
4554                 temp &= ~DREF_SSC_SOURCE_MASK;
4555                 temp |= DREF_SSC_SOURCE_ENABLE;
4556
4557                 /* SSC must be turned on before enabling the CPU output  */
4558                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4559                         DRM_DEBUG_KMS("Using SSC on panel\n");
4560                         temp |= DREF_SSC1_ENABLE;
4561                 } else
4562                         temp &= ~DREF_SSC1_ENABLE;
4563
4564                 /* Get SSC going before enabling the outputs */
4565                 I915_WRITE(PCH_DREF_CONTROL, temp);
4566                 POSTING_READ(PCH_DREF_CONTROL);
4567                 udelay(200);
4568
4569                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4570
4571                 /* Enable CPU source on CPU attached eDP */
4572                 if (has_cpu_edp) {
4573                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4574                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4575                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4576                         }
4577                         else
4578                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4579                 } else
4580                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4581
4582                 I915_WRITE(PCH_DREF_CONTROL, temp);
4583                 POSTING_READ(PCH_DREF_CONTROL);
4584                 udelay(200);
4585         } else {
4586                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4587
4588                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4589
4590                 /* Turn off CPU output */
4591                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4592
4593                 I915_WRITE(PCH_DREF_CONTROL, temp);
4594                 POSTING_READ(PCH_DREF_CONTROL);
4595                 udelay(200);
4596
4597                 /* Turn off the SSC source */
4598                 temp &= ~DREF_SSC_SOURCE_MASK;
4599                 temp |= DREF_SSC_SOURCE_DISABLE;
4600
4601                 /* Turn off SSC1 */
4602                 temp &= ~ DREF_SSC1_ENABLE;
4603
4604                 I915_WRITE(PCH_DREF_CONTROL, temp);
4605                 POSTING_READ(PCH_DREF_CONTROL);
4606                 udelay(200);
4607         }
4608 }
4609
4610 static int ironlake_get_refclk(struct drm_crtc *crtc)
4611 {
4612         struct drm_device *dev = crtc->dev;
4613         struct drm_i915_private *dev_priv = dev->dev_private;
4614         struct intel_encoder *encoder;
4615         struct intel_encoder *edp_encoder = NULL;
4616         int num_connectors = 0;
4617         bool is_lvds = false;
4618
4619         for_each_encoder_on_crtc(dev, crtc, encoder) {
4620                 switch (encoder->type) {
4621                 case INTEL_OUTPUT_LVDS:
4622                         is_lvds = true;
4623                         break;
4624                 case INTEL_OUTPUT_EDP:
4625                         edp_encoder = encoder;
4626                         break;
4627                 }
4628                 num_connectors++;
4629         }
4630
4631         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4632                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4633                               dev_priv->lvds_ssc_freq);
4634                 return dev_priv->lvds_ssc_freq * 1000;
4635         }
4636
4637         return 120000;
4638 }
4639
4640 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4641                                   struct drm_display_mode *mode,
4642                                   struct drm_display_mode *adjusted_mode,
4643                                   int x, int y,
4644                                   struct drm_framebuffer *fb)
4645 {
4646         struct drm_device *dev = crtc->dev;
4647         struct drm_i915_private *dev_priv = dev->dev_private;
4648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649         int pipe = intel_crtc->pipe;
4650         int plane = intel_crtc->plane;
4651         int refclk, num_connectors = 0;
4652         intel_clock_t clock, reduced_clock;
4653         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4654         bool ok, has_reduced_clock = false, is_sdvo = false;
4655         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4656         struct intel_encoder *encoder, *edp_encoder = NULL;
4657         const intel_limit_t *limit;
4658         int ret;
4659         struct fdi_m_n m_n = {0};
4660         u32 temp;
4661         int target_clock, pixel_multiplier, lane, link_bw, factor;
4662         unsigned int pipe_bpp;
4663         bool dither;
4664         bool is_cpu_edp = false, is_pch_edp = false;
4665
4666         for_each_encoder_on_crtc(dev, crtc, encoder) {
4667                 switch (encoder->type) {
4668                 case INTEL_OUTPUT_LVDS:
4669                         is_lvds = true;
4670                         break;
4671                 case INTEL_OUTPUT_SDVO:
4672                 case INTEL_OUTPUT_HDMI:
4673                         is_sdvo = true;
4674                         if (encoder->needs_tv_clock)
4675                                 is_tv = true;
4676                         break;
4677                 case INTEL_OUTPUT_TVOUT:
4678                         is_tv = true;
4679                         break;
4680                 case INTEL_OUTPUT_ANALOG:
4681                         is_crt = true;
4682                         break;
4683                 case INTEL_OUTPUT_DISPLAYPORT:
4684                         is_dp = true;
4685                         break;
4686                 case INTEL_OUTPUT_EDP:
4687                         is_dp = true;
4688                         if (intel_encoder_is_pch_edp(&encoder->base))
4689                                 is_pch_edp = true;
4690                         else
4691                                 is_cpu_edp = true;
4692                         edp_encoder = encoder;
4693                         break;
4694                 }
4695
4696                 num_connectors++;
4697         }
4698
4699         refclk = ironlake_get_refclk(crtc);
4700
4701         /*
4702          * Returns a set of divisors for the desired target clock with the given
4703          * refclk, or FALSE.  The returned values represent the clock equation:
4704          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4705          */
4706         limit = intel_limit(crtc, refclk);
4707         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4708                              &clock);
4709         if (!ok) {
4710                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4711                 return -EINVAL;
4712         }
4713
4714         /* Ensure that the cursor is valid for the new mode before changing... */
4715         intel_crtc_update_cursor(crtc, true);
4716
4717         if (is_lvds && dev_priv->lvds_downclock_avail) {
4718                 /*
4719                  * Ensure we match the reduced clock's P to the target clock.
4720                  * If the clocks don't match, we can't switch the display clock
4721                  * by using the FP0/FP1. In such case we will disable the LVDS
4722                  * downclock feature.
4723                 */
4724                 has_reduced_clock = limit->find_pll(limit, crtc,
4725                                                     dev_priv->lvds_downclock,
4726                                                     refclk,
4727                                                     &clock,
4728                                                     &reduced_clock);
4729         }
4730
4731         if (is_sdvo && is_tv)
4732                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4733
4734
4735         /* FDI link */
4736         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4737         lane = 0;
4738         /* CPU eDP doesn't require FDI link, so just set DP M/N
4739            according to current link config */
4740         if (is_cpu_edp) {
4741                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4742         } else {
4743                 /* FDI is a binary signal running at ~2.7GHz, encoding
4744                  * each output octet as 10 bits. The actual frequency
4745                  * is stored as a divider into a 100MHz clock, and the
4746                  * mode pixel clock is stored in units of 1KHz.
4747                  * Hence the bw of each lane in terms of the mode signal
4748                  * is:
4749                  */
4750                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4751         }
4752
4753         /* [e]DP over FDI requires target mode clock instead of link clock. */
4754         if (edp_encoder)
4755                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4756         else if (is_dp)
4757                 target_clock = mode->clock;
4758         else
4759                 target_clock = adjusted_mode->clock;
4760
4761         /* determine panel color depth */
4762         temp = I915_READ(PIPECONF(pipe));
4763         temp &= ~PIPE_BPC_MASK;
4764         dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
4765         switch (pipe_bpp) {
4766         case 18:
4767                 temp |= PIPE_6BPC;
4768                 break;
4769         case 24:
4770                 temp |= PIPE_8BPC;
4771                 break;
4772         case 30:
4773                 temp |= PIPE_10BPC;
4774                 break;
4775         case 36:
4776                 temp |= PIPE_12BPC;
4777                 break;
4778         default:
4779                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4780                         pipe_bpp);
4781                 temp |= PIPE_8BPC;
4782                 pipe_bpp = 24;
4783                 break;
4784         }
4785
4786         intel_crtc->bpp = pipe_bpp;
4787         I915_WRITE(PIPECONF(pipe), temp);
4788
4789         if (!lane) {
4790                 /*
4791                  * Account for spread spectrum to avoid
4792                  * oversubscribing the link. Max center spread
4793                  * is 2.5%; use 5% for safety's sake.
4794                  */
4795                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4796                 lane = bps / (link_bw * 8) + 1;
4797         }
4798
4799         intel_crtc->fdi_lanes = lane;
4800
4801         if (pixel_multiplier > 1)
4802                 link_bw *= pixel_multiplier;
4803         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4804                              &m_n);
4805
4806         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4807         if (has_reduced_clock)
4808                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4809                         reduced_clock.m2;
4810
4811         /* Enable autotuning of the PLL clock (if permissible) */
4812         factor = 21;
4813         if (is_lvds) {
4814                 if ((intel_panel_use_ssc(dev_priv) &&
4815                      dev_priv->lvds_ssc_freq == 100) ||
4816                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4817                         factor = 25;
4818         } else if (is_sdvo && is_tv)
4819                 factor = 20;
4820
4821         if (clock.m < factor * clock.n)
4822                 fp |= FP_CB_TUNE;
4823
4824         dpll = 0;
4825
4826         if (is_lvds)
4827                 dpll |= DPLLB_MODE_LVDS;
4828         else
4829                 dpll |= DPLLB_MODE_DAC_SERIAL;
4830         if (is_sdvo) {
4831                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4832                 if (pixel_multiplier > 1) {
4833                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4834                 }
4835                 dpll |= DPLL_DVO_HIGH_SPEED;
4836         }
4837         if (is_dp && !is_cpu_edp)
4838                 dpll |= DPLL_DVO_HIGH_SPEED;
4839
4840         /* compute bitmask from p1 value */
4841         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4842         /* also FPA1 */
4843         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4844
4845         switch (clock.p2) {
4846         case 5:
4847                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4848                 break;
4849         case 7:
4850                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4851                 break;
4852         case 10:
4853                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4854                 break;
4855         case 14:
4856                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4857                 break;
4858         }
4859
4860         if (is_sdvo && is_tv)
4861                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4862         else if (is_tv)
4863                 /* XXX: just matching BIOS for now */
4864                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4865                 dpll |= 3;
4866         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4867                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4868         else
4869                 dpll |= PLL_REF_INPUT_DREFCLK;
4870
4871         /* setup pipeconf */
4872         pipeconf = I915_READ(PIPECONF(pipe));
4873
4874         /* Set up the display plane register */
4875         dspcntr = DISPPLANE_GAMMA_ENABLE;
4876
4877         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4878         drm_mode_debug_printmodeline(mode);
4879
4880         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4881          * pre-Haswell/LPT generation */
4882         if (HAS_PCH_LPT(dev)) {
4883                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4884                                 pipe);
4885         } else if (!is_cpu_edp) {
4886                 struct intel_pch_pll *pll;
4887
4888                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4889                 if (pll == NULL) {
4890                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4891                                          pipe);
4892                         return -EINVAL;
4893                 }
4894         } else
4895                 intel_put_pch_pll(intel_crtc);
4896
4897         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4898          * This is an exception to the general rule that mode_set doesn't turn
4899          * things on.
4900          */
4901         if (is_lvds) {
4902                 temp = I915_READ(PCH_LVDS);
4903                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4904                 if (HAS_PCH_CPT(dev)) {
4905                         temp &= ~PORT_TRANS_SEL_MASK;
4906                         temp |= PORT_TRANS_SEL_CPT(pipe);
4907                 } else {
4908                         if (pipe == 1)
4909                                 temp |= LVDS_PIPEB_SELECT;
4910                         else
4911                                 temp &= ~LVDS_PIPEB_SELECT;
4912                 }
4913
4914                 /* set the corresponsding LVDS_BORDER bit */
4915                 temp |= dev_priv->lvds_border_bits;
4916                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4917                  * set the DPLLs for dual-channel mode or not.
4918                  */
4919                 if (clock.p2 == 7)
4920                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4921                 else
4922                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4923
4924                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4925                  * appropriately here, but we need to look more thoroughly into how
4926                  * panels behave in the two modes.
4927                  */
4928                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4929                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4930                         temp |= LVDS_HSYNC_POLARITY;
4931                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4932                         temp |= LVDS_VSYNC_POLARITY;
4933                 I915_WRITE(PCH_LVDS, temp);
4934         }
4935
4936         pipeconf &= ~PIPECONF_DITHER_EN;
4937         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4938         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4939                 pipeconf |= PIPECONF_DITHER_EN;
4940                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4941         }
4942         if (is_dp && !is_cpu_edp) {
4943                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4944         } else {
4945                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4946                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4947                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4948                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4949                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4950         }
4951
4952         if (intel_crtc->pch_pll) {
4953                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4954
4955                 /* Wait for the clocks to stabilize. */
4956                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4957                 udelay(150);
4958
4959                 /* The pixel multiplier can only be updated once the
4960                  * DPLL is enabled and the clocks are stable.
4961                  *
4962                  * So write it again.
4963                  */
4964                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4965         }
4966
4967         intel_crtc->lowfreq_avail = false;
4968         if (intel_crtc->pch_pll) {
4969                 if (is_lvds && has_reduced_clock && i915_powersave) {
4970                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4971                         intel_crtc->lowfreq_avail = true;
4972                 } else {
4973                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4974                 }
4975         }
4976
4977         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4978         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4979                 pipeconf |= PIPECONF_INTERLACED_ILK;
4980                 /* the chip adds 2 halflines automatically */
4981                 adjusted_mode->crtc_vtotal -= 1;
4982                 adjusted_mode->crtc_vblank_end -= 1;
4983                 I915_WRITE(VSYNCSHIFT(pipe),
4984                            adjusted_mode->crtc_hsync_start
4985                            - adjusted_mode->crtc_htotal/2);
4986         } else {
4987                 pipeconf |= PIPECONF_PROGRESSIVE;
4988                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4989         }
4990
4991         I915_WRITE(HTOTAL(pipe),
4992                    (adjusted_mode->crtc_hdisplay - 1) |
4993                    ((adjusted_mode->crtc_htotal - 1) << 16));
4994         I915_WRITE(HBLANK(pipe),
4995                    (adjusted_mode->crtc_hblank_start - 1) |
4996                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4997         I915_WRITE(HSYNC(pipe),
4998                    (adjusted_mode->crtc_hsync_start - 1) |
4999                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5000
5001         I915_WRITE(VTOTAL(pipe),
5002                    (adjusted_mode->crtc_vdisplay - 1) |
5003                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5004         I915_WRITE(VBLANK(pipe),
5005                    (adjusted_mode->crtc_vblank_start - 1) |
5006                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5007         I915_WRITE(VSYNC(pipe),
5008                    (adjusted_mode->crtc_vsync_start - 1) |
5009                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5010
5011         /* pipesrc controls the size that is scaled from, which should
5012          * always be the user's requested size.
5013          */
5014         I915_WRITE(PIPESRC(pipe),
5015                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5016
5017         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5018         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5019         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5020         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5021
5022         if (is_cpu_edp)
5023                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5024
5025         I915_WRITE(PIPECONF(pipe), pipeconf);
5026         POSTING_READ(PIPECONF(pipe));
5027
5028         intel_wait_for_vblank(dev, pipe);
5029
5030         I915_WRITE(DSPCNTR(plane), dspcntr);
5031         POSTING_READ(DSPCNTR(plane));
5032
5033         ret = intel_pipe_set_base(crtc, x, y, fb);
5034
5035         intel_update_watermarks(dev);
5036
5037         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5038
5039         return ret;
5040 }
5041
5042 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5043                                struct drm_display_mode *mode,
5044                                struct drm_display_mode *adjusted_mode,
5045                                int x, int y,
5046                                struct drm_framebuffer *fb)
5047 {
5048         struct drm_device *dev = crtc->dev;
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051         int pipe = intel_crtc->pipe;
5052         int ret;
5053
5054         drm_vblank_pre_modeset(dev, pipe);
5055
5056         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5057                                               x, y, fb);
5058         drm_vblank_post_modeset(dev, pipe);
5059
5060         return ret;
5061 }
5062
5063 static bool intel_eld_uptodate(struct drm_connector *connector,
5064                                int reg_eldv, uint32_t bits_eldv,
5065                                int reg_elda, uint32_t bits_elda,
5066                                int reg_edid)
5067 {
5068         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5069         uint8_t *eld = connector->eld;
5070         uint32_t i;
5071
5072         i = I915_READ(reg_eldv);
5073         i &= bits_eldv;
5074
5075         if (!eld[0])
5076                 return !i;
5077
5078         if (!i)
5079                 return false;
5080
5081         i = I915_READ(reg_elda);
5082         i &= ~bits_elda;
5083         I915_WRITE(reg_elda, i);
5084
5085         for (i = 0; i < eld[2]; i++)
5086                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5087                         return false;
5088
5089         return true;
5090 }
5091
5092 static void g4x_write_eld(struct drm_connector *connector,
5093                           struct drm_crtc *crtc)
5094 {
5095         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5096         uint8_t *eld = connector->eld;
5097         uint32_t eldv;
5098         uint32_t len;
5099         uint32_t i;
5100
5101         i = I915_READ(G4X_AUD_VID_DID);
5102
5103         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5104                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5105         else
5106                 eldv = G4X_ELDV_DEVCTG;
5107
5108         if (intel_eld_uptodate(connector,
5109                                G4X_AUD_CNTL_ST, eldv,
5110                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5111                                G4X_HDMIW_HDMIEDID))
5112                 return;
5113
5114         i = I915_READ(G4X_AUD_CNTL_ST);
5115         i &= ~(eldv | G4X_ELD_ADDR);
5116         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5117         I915_WRITE(G4X_AUD_CNTL_ST, i);
5118
5119         if (!eld[0])
5120                 return;
5121
5122         len = min_t(uint8_t, eld[2], len);
5123         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5124         for (i = 0; i < len; i++)
5125                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5126
5127         i = I915_READ(G4X_AUD_CNTL_ST);
5128         i |= eldv;
5129         I915_WRITE(G4X_AUD_CNTL_ST, i);
5130 }
5131
5132 static void haswell_write_eld(struct drm_connector *connector,
5133                                      struct drm_crtc *crtc)
5134 {
5135         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5136         uint8_t *eld = connector->eld;
5137         struct drm_device *dev = crtc->dev;
5138         uint32_t eldv;
5139         uint32_t i;
5140         int len;
5141         int pipe = to_intel_crtc(crtc)->pipe;
5142         int tmp;
5143
5144         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5145         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5146         int aud_config = HSW_AUD_CFG(pipe);
5147         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5148
5149
5150         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5151
5152         /* Audio output enable */
5153         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5154         tmp = I915_READ(aud_cntrl_st2);
5155         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5156         I915_WRITE(aud_cntrl_st2, tmp);
5157
5158         /* Wait for 1 vertical blank */
5159         intel_wait_for_vblank(dev, pipe);
5160
5161         /* Set ELD valid state */
5162         tmp = I915_READ(aud_cntrl_st2);
5163         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5164         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5165         I915_WRITE(aud_cntrl_st2, tmp);
5166         tmp = I915_READ(aud_cntrl_st2);
5167         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5168
5169         /* Enable HDMI mode */
5170         tmp = I915_READ(aud_config);
5171         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5172         /* clear N_programing_enable and N_value_index */
5173         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5174         I915_WRITE(aud_config, tmp);
5175
5176         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5177
5178         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5179
5180         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5181                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5182                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5183                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5184         } else
5185                 I915_WRITE(aud_config, 0);
5186
5187         if (intel_eld_uptodate(connector,
5188                                aud_cntrl_st2, eldv,
5189                                aud_cntl_st, IBX_ELD_ADDRESS,
5190                                hdmiw_hdmiedid))
5191                 return;
5192
5193         i = I915_READ(aud_cntrl_st2);
5194         i &= ~eldv;
5195         I915_WRITE(aud_cntrl_st2, i);
5196
5197         if (!eld[0])
5198                 return;
5199
5200         i = I915_READ(aud_cntl_st);
5201         i &= ~IBX_ELD_ADDRESS;
5202         I915_WRITE(aud_cntl_st, i);
5203         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5204         DRM_DEBUG_DRIVER("port num:%d\n", i);
5205
5206         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5207         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5208         for (i = 0; i < len; i++)
5209                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5210
5211         i = I915_READ(aud_cntrl_st2);
5212         i |= eldv;
5213         I915_WRITE(aud_cntrl_st2, i);
5214
5215 }
5216
5217 static void ironlake_write_eld(struct drm_connector *connector,
5218                                      struct drm_crtc *crtc)
5219 {
5220         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5221         uint8_t *eld = connector->eld;
5222         uint32_t eldv;
5223         uint32_t i;
5224         int len;
5225         int hdmiw_hdmiedid;
5226         int aud_config;
5227         int aud_cntl_st;
5228         int aud_cntrl_st2;
5229         int pipe = to_intel_crtc(crtc)->pipe;
5230
5231         if (HAS_PCH_IBX(connector->dev)) {
5232                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5233                 aud_config = IBX_AUD_CFG(pipe);
5234                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5235                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5236         } else {
5237                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5238                 aud_config = CPT_AUD_CFG(pipe);
5239                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5240                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5241         }
5242
5243         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5244
5245         i = I915_READ(aud_cntl_st);
5246         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5247         if (!i) {
5248                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5249                 /* operate blindly on all ports */
5250                 eldv = IBX_ELD_VALIDB;
5251                 eldv |= IBX_ELD_VALIDB << 4;
5252                 eldv |= IBX_ELD_VALIDB << 8;
5253         } else {
5254                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5255                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5256         }
5257
5258         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5259                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5260                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5261                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5262         } else
5263                 I915_WRITE(aud_config, 0);
5264
5265         if (intel_eld_uptodate(connector,
5266                                aud_cntrl_st2, eldv,
5267                                aud_cntl_st, IBX_ELD_ADDRESS,
5268                                hdmiw_hdmiedid))
5269                 return;
5270
5271         i = I915_READ(aud_cntrl_st2);
5272         i &= ~eldv;
5273         I915_WRITE(aud_cntrl_st2, i);
5274
5275         if (!eld[0])
5276                 return;
5277
5278         i = I915_READ(aud_cntl_st);
5279         i &= ~IBX_ELD_ADDRESS;
5280         I915_WRITE(aud_cntl_st, i);
5281
5282         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5283         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5284         for (i = 0; i < len; i++)
5285                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5286
5287         i = I915_READ(aud_cntrl_st2);
5288         i |= eldv;
5289         I915_WRITE(aud_cntrl_st2, i);
5290 }
5291
5292 void intel_write_eld(struct drm_encoder *encoder,
5293                      struct drm_display_mode *mode)
5294 {
5295         struct drm_crtc *crtc = encoder->crtc;
5296         struct drm_connector *connector;
5297         struct drm_device *dev = encoder->dev;
5298         struct drm_i915_private *dev_priv = dev->dev_private;
5299
5300         connector = drm_select_eld(encoder, mode);
5301         if (!connector)
5302                 return;
5303
5304         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5305                          connector->base.id,
5306                          drm_get_connector_name(connector),
5307                          connector->encoder->base.id,
5308                          drm_get_encoder_name(connector->encoder));
5309
5310         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5311
5312         if (dev_priv->display.write_eld)
5313                 dev_priv->display.write_eld(connector, crtc);
5314 }
5315
5316 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5317 void intel_crtc_load_lut(struct drm_crtc *crtc)
5318 {
5319         struct drm_device *dev = crtc->dev;
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5322         int palreg = PALETTE(intel_crtc->pipe);
5323         int i;
5324
5325         /* The clocks have to be on to load the palette. */
5326         if (!crtc->enabled || !intel_crtc->active)
5327                 return;
5328
5329         /* use legacy palette for Ironlake */
5330         if (HAS_PCH_SPLIT(dev))
5331                 palreg = LGC_PALETTE(intel_crtc->pipe);
5332
5333         for (i = 0; i < 256; i++) {
5334                 I915_WRITE(palreg + 4 * i,
5335                            (intel_crtc->lut_r[i] << 16) |
5336                            (intel_crtc->lut_g[i] << 8) |
5337                            intel_crtc->lut_b[i]);
5338         }
5339 }
5340
5341 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5346         bool visible = base != 0;
5347         u32 cntl;
5348
5349         if (intel_crtc->cursor_visible == visible)
5350                 return;
5351
5352         cntl = I915_READ(_CURACNTR);
5353         if (visible) {
5354                 /* On these chipsets we can only modify the base whilst
5355                  * the cursor is disabled.
5356                  */
5357                 I915_WRITE(_CURABASE, base);
5358
5359                 cntl &= ~(CURSOR_FORMAT_MASK);
5360                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5361                 cntl |= CURSOR_ENABLE |
5362                         CURSOR_GAMMA_ENABLE |
5363                         CURSOR_FORMAT_ARGB;
5364         } else
5365                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5366         I915_WRITE(_CURACNTR, cntl);
5367
5368         intel_crtc->cursor_visible = visible;
5369 }
5370
5371 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5372 {
5373         struct drm_device *dev = crtc->dev;
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376         int pipe = intel_crtc->pipe;
5377         bool visible = base != 0;
5378
5379         if (intel_crtc->cursor_visible != visible) {
5380                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5381                 if (base) {
5382                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5383                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5384                         cntl |= pipe << 28; /* Connect to correct pipe */
5385                 } else {
5386                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5387                         cntl |= CURSOR_MODE_DISABLE;
5388                 }
5389                 I915_WRITE(CURCNTR(pipe), cntl);
5390
5391                 intel_crtc->cursor_visible = visible;
5392         }
5393         /* and commit changes on next vblank */
5394         I915_WRITE(CURBASE(pipe), base);
5395 }
5396
5397 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5398 {
5399         struct drm_device *dev = crtc->dev;
5400         struct drm_i915_private *dev_priv = dev->dev_private;
5401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402         int pipe = intel_crtc->pipe;
5403         bool visible = base != 0;
5404
5405         if (intel_crtc->cursor_visible != visible) {
5406                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5407                 if (base) {
5408                         cntl &= ~CURSOR_MODE;
5409                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5410                 } else {
5411                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5412                         cntl |= CURSOR_MODE_DISABLE;
5413                 }
5414                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5415
5416                 intel_crtc->cursor_visible = visible;
5417         }
5418         /* and commit changes on next vblank */
5419         I915_WRITE(CURBASE_IVB(pipe), base);
5420 }
5421
5422 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5423 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5424                                      bool on)
5425 {
5426         struct drm_device *dev = crtc->dev;
5427         struct drm_i915_private *dev_priv = dev->dev_private;
5428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429         int pipe = intel_crtc->pipe;
5430         int x = intel_crtc->cursor_x;
5431         int y = intel_crtc->cursor_y;
5432         u32 base, pos;
5433         bool visible;
5434
5435         pos = 0;
5436
5437         if (on && crtc->enabled && crtc->fb) {
5438                 base = intel_crtc->cursor_addr;
5439                 if (x > (int) crtc->fb->width)
5440                         base = 0;
5441
5442                 if (y > (int) crtc->fb->height)
5443                         base = 0;
5444         } else
5445                 base = 0;
5446
5447         if (x < 0) {
5448                 if (x + intel_crtc->cursor_width < 0)
5449                         base = 0;
5450
5451                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5452                 x = -x;
5453         }
5454         pos |= x << CURSOR_X_SHIFT;
5455
5456         if (y < 0) {
5457                 if (y + intel_crtc->cursor_height < 0)
5458                         base = 0;
5459
5460                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5461                 y = -y;
5462         }
5463         pos |= y << CURSOR_Y_SHIFT;
5464
5465         visible = base != 0;
5466         if (!visible && !intel_crtc->cursor_visible)
5467                 return;
5468
5469         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5470                 I915_WRITE(CURPOS_IVB(pipe), pos);
5471                 ivb_update_cursor(crtc, base);
5472         } else {
5473                 I915_WRITE(CURPOS(pipe), pos);
5474                 if (IS_845G(dev) || IS_I865G(dev))
5475                         i845_update_cursor(crtc, base);
5476                 else
5477                         i9xx_update_cursor(crtc, base);
5478         }
5479 }
5480
5481 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5482                                  struct drm_file *file,
5483                                  uint32_t handle,
5484                                  uint32_t width, uint32_t height)
5485 {
5486         struct drm_device *dev = crtc->dev;
5487         struct drm_i915_private *dev_priv = dev->dev_private;
5488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489         struct drm_i915_gem_object *obj;
5490         uint32_t addr;
5491         int ret;
5492
5493         /* if we want to turn off the cursor ignore width and height */
5494         if (!handle) {
5495                 DRM_DEBUG_KMS("cursor off\n");
5496                 addr = 0;
5497                 obj = NULL;
5498                 mutex_lock(&dev->struct_mutex);
5499                 goto finish;
5500         }
5501
5502         /* Currently we only support 64x64 cursors */
5503         if (width != 64 || height != 64) {
5504                 DRM_ERROR("we currently only support 64x64 cursors\n");
5505                 return -EINVAL;
5506         }
5507
5508         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5509         if (&obj->base == NULL)
5510                 return -ENOENT;
5511
5512         if (obj->base.size < width * height * 4) {
5513                 DRM_ERROR("buffer is to small\n");
5514                 ret = -ENOMEM;
5515                 goto fail;
5516         }
5517
5518         /* we only need to pin inside GTT if cursor is non-phy */
5519         mutex_lock(&dev->struct_mutex);
5520         if (!dev_priv->info->cursor_needs_physical) {
5521                 if (obj->tiling_mode) {
5522                         DRM_ERROR("cursor cannot be tiled\n");
5523                         ret = -EINVAL;
5524                         goto fail_locked;
5525                 }
5526
5527                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5528                 if (ret) {
5529                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5530                         goto fail_locked;
5531                 }
5532
5533                 ret = i915_gem_object_put_fence(obj);
5534                 if (ret) {
5535                         DRM_ERROR("failed to release fence for cursor");
5536                         goto fail_unpin;
5537                 }
5538
5539                 addr = obj->gtt_offset;
5540         } else {
5541                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5542                 ret = i915_gem_attach_phys_object(dev, obj,
5543                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5544                                                   align);
5545                 if (ret) {
5546                         DRM_ERROR("failed to attach phys object\n");
5547                         goto fail_locked;
5548                 }
5549                 addr = obj->phys_obj->handle->busaddr;
5550         }
5551
5552         if (IS_GEN2(dev))
5553                 I915_WRITE(CURSIZE, (height << 12) | width);
5554
5555  finish:
5556         if (intel_crtc->cursor_bo) {
5557                 if (dev_priv->info->cursor_needs_physical) {
5558                         if (intel_crtc->cursor_bo != obj)
5559                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5560                 } else
5561                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5562                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5563         }
5564
5565         mutex_unlock(&dev->struct_mutex);
5566
5567         intel_crtc->cursor_addr = addr;
5568         intel_crtc->cursor_bo = obj;
5569         intel_crtc->cursor_width = width;
5570         intel_crtc->cursor_height = height;
5571
5572         intel_crtc_update_cursor(crtc, true);
5573
5574         return 0;
5575 fail_unpin:
5576         i915_gem_object_unpin(obj);
5577 fail_locked:
5578         mutex_unlock(&dev->struct_mutex);
5579 fail:
5580         drm_gem_object_unreference_unlocked(&obj->base);
5581         return ret;
5582 }
5583
5584 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5585 {
5586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5587
5588         intel_crtc->cursor_x = x;
5589         intel_crtc->cursor_y = y;
5590
5591         intel_crtc_update_cursor(crtc, true);
5592
5593         return 0;
5594 }
5595
5596 /** Sets the color ramps on behalf of RandR */
5597 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5598                                  u16 blue, int regno)
5599 {
5600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601
5602         intel_crtc->lut_r[regno] = red >> 8;
5603         intel_crtc->lut_g[regno] = green >> 8;
5604         intel_crtc->lut_b[regno] = blue >> 8;
5605 }
5606
5607 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5608                              u16 *blue, int regno)
5609 {
5610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611
5612         *red = intel_crtc->lut_r[regno] << 8;
5613         *green = intel_crtc->lut_g[regno] << 8;
5614         *blue = intel_crtc->lut_b[regno] << 8;
5615 }
5616
5617 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5618                                  u16 *blue, uint32_t start, uint32_t size)
5619 {
5620         int end = (start + size > 256) ? 256 : start + size, i;
5621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5622
5623         for (i = start; i < end; i++) {
5624                 intel_crtc->lut_r[i] = red[i] >> 8;
5625                 intel_crtc->lut_g[i] = green[i] >> 8;
5626                 intel_crtc->lut_b[i] = blue[i] >> 8;
5627         }
5628
5629         intel_crtc_load_lut(crtc);
5630 }
5631
5632 /**
5633  * Get a pipe with a simple mode set on it for doing load-based monitor
5634  * detection.
5635  *
5636  * It will be up to the load-detect code to adjust the pipe as appropriate for
5637  * its requirements.  The pipe will be connected to no other encoders.
5638  *
5639  * Currently this code will only succeed if there is a pipe with no encoders
5640  * configured for it.  In the future, it could choose to temporarily disable
5641  * some outputs to free up a pipe for its use.
5642  *
5643  * \return crtc, or NULL if no pipes are available.
5644  */
5645
5646 /* VESA 640x480x72Hz mode to set on the pipe */
5647 static struct drm_display_mode load_detect_mode = {
5648         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5649                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5650 };
5651
5652 static struct drm_framebuffer *
5653 intel_framebuffer_create(struct drm_device *dev,
5654                          struct drm_mode_fb_cmd2 *mode_cmd,
5655                          struct drm_i915_gem_object *obj)
5656 {
5657         struct intel_framebuffer *intel_fb;
5658         int ret;
5659
5660         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5661         if (!intel_fb) {
5662                 drm_gem_object_unreference_unlocked(&obj->base);
5663                 return ERR_PTR(-ENOMEM);
5664         }
5665
5666         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5667         if (ret) {
5668                 drm_gem_object_unreference_unlocked(&obj->base);
5669                 kfree(intel_fb);
5670                 return ERR_PTR(ret);
5671         }
5672
5673         return &intel_fb->base;
5674 }
5675
5676 static u32
5677 intel_framebuffer_pitch_for_width(int width, int bpp)
5678 {
5679         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5680         return ALIGN(pitch, 64);
5681 }
5682
5683 static u32
5684 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5685 {
5686         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5687         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5688 }
5689
5690 static struct drm_framebuffer *
5691 intel_framebuffer_create_for_mode(struct drm_device *dev,
5692                                   struct drm_display_mode *mode,
5693                                   int depth, int bpp)
5694 {
5695         struct drm_i915_gem_object *obj;
5696         struct drm_mode_fb_cmd2 mode_cmd;
5697
5698         obj = i915_gem_alloc_object(dev,
5699                                     intel_framebuffer_size_for_mode(mode, bpp));
5700         if (obj == NULL)
5701                 return ERR_PTR(-ENOMEM);
5702
5703         mode_cmd.width = mode->hdisplay;
5704         mode_cmd.height = mode->vdisplay;
5705         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5706                                                                 bpp);
5707         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5708
5709         return intel_framebuffer_create(dev, &mode_cmd, obj);
5710 }
5711
5712 static struct drm_framebuffer *
5713 mode_fits_in_fbdev(struct drm_device *dev,
5714                    struct drm_display_mode *mode)
5715 {
5716         struct drm_i915_private *dev_priv = dev->dev_private;
5717         struct drm_i915_gem_object *obj;
5718         struct drm_framebuffer *fb;
5719
5720         if (dev_priv->fbdev == NULL)
5721                 return NULL;
5722
5723         obj = dev_priv->fbdev->ifb.obj;
5724         if (obj == NULL)
5725                 return NULL;
5726
5727         fb = &dev_priv->fbdev->ifb.base;
5728         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5729                                                                fb->bits_per_pixel))
5730                 return NULL;
5731
5732         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5733                 return NULL;
5734
5735         return fb;
5736 }
5737
5738 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5739                                 struct drm_display_mode *mode,
5740                                 struct intel_load_detect_pipe *old)
5741 {
5742         struct intel_crtc *intel_crtc;
5743         struct intel_encoder *intel_encoder =
5744                 intel_attached_encoder(connector);
5745         struct drm_crtc *possible_crtc;
5746         struct drm_encoder *encoder = &intel_encoder->base;
5747         struct drm_crtc *crtc = NULL;
5748         struct drm_device *dev = encoder->dev;
5749         struct drm_framebuffer *fb;
5750         int i = -1;
5751
5752         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5753                       connector->base.id, drm_get_connector_name(connector),
5754                       encoder->base.id, drm_get_encoder_name(encoder));
5755
5756         /*
5757          * Algorithm gets a little messy:
5758          *
5759          *   - if the connector already has an assigned crtc, use it (but make
5760          *     sure it's on first)
5761          *
5762          *   - try to find the first unused crtc that can drive this connector,
5763          *     and use that if we find one
5764          */
5765
5766         /* See if we already have a CRTC for this connector */
5767         if (encoder->crtc) {
5768                 crtc = encoder->crtc;
5769
5770                 old->dpms_mode = connector->dpms;
5771                 old->load_detect_temp = false;
5772
5773                 /* Make sure the crtc and connector are running */
5774                 if (connector->dpms != DRM_MODE_DPMS_ON)
5775                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5776
5777                 return true;
5778         }
5779
5780         /* Find an unused one (if possible) */
5781         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5782                 i++;
5783                 if (!(encoder->possible_crtcs & (1 << i)))
5784                         continue;
5785                 if (!possible_crtc->enabled) {
5786                         crtc = possible_crtc;
5787                         break;
5788                 }
5789         }
5790
5791         /*
5792          * If we didn't find an unused CRTC, don't use any.
5793          */
5794         if (!crtc) {
5795                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5796                 return false;
5797         }
5798
5799         encoder->crtc = crtc;
5800         connector->encoder = encoder;
5801
5802         intel_crtc = to_intel_crtc(crtc);
5803         old->dpms_mode = connector->dpms;
5804         old->load_detect_temp = true;
5805         old->release_fb = NULL;
5806
5807         if (!mode)
5808                 mode = &load_detect_mode;
5809
5810         /* We need a framebuffer large enough to accommodate all accesses
5811          * that the plane may generate whilst we perform load detection.
5812          * We can not rely on the fbcon either being present (we get called
5813          * during its initialisation to detect all boot displays, or it may
5814          * not even exist) or that it is large enough to satisfy the
5815          * requested mode.
5816          */
5817         fb = mode_fits_in_fbdev(dev, mode);
5818         if (fb == NULL) {
5819                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5820                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5821                 old->release_fb = fb;
5822         } else
5823                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5824         if (IS_ERR(fb)) {
5825                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5826                 goto fail;
5827         }
5828
5829         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5830                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5831                 if (old->release_fb)
5832                         old->release_fb->funcs->destroy(old->release_fb);
5833                 goto fail;
5834         }
5835
5836         /* let the connector get through one full cycle before testing */
5837         intel_wait_for_vblank(dev, intel_crtc->pipe);
5838
5839         return true;
5840 fail:
5841         connector->encoder = NULL;
5842         encoder->crtc = NULL;
5843         return false;
5844 }
5845
5846 void intel_release_load_detect_pipe(struct drm_connector *connector,
5847                                     struct intel_load_detect_pipe *old)
5848 {
5849         struct intel_encoder *intel_encoder =
5850                 intel_attached_encoder(connector);
5851         struct drm_encoder *encoder = &intel_encoder->base;
5852         struct drm_device *dev = encoder->dev;
5853
5854         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5855                       connector->base.id, drm_get_connector_name(connector),
5856                       encoder->base.id, drm_get_encoder_name(encoder));
5857
5858         if (old->load_detect_temp) {
5859                 connector->encoder = NULL;
5860                 encoder->crtc = NULL;
5861                 drm_helper_disable_unused_functions(dev);
5862
5863                 if (old->release_fb)
5864                         old->release_fb->funcs->destroy(old->release_fb);
5865
5866                 return;
5867         }
5868
5869         /* Switch crtc and encoder back off if necessary */
5870         if (old->dpms_mode != DRM_MODE_DPMS_ON)
5871                 connector->funcs->dpms(connector, old->dpms_mode);
5872 }
5873
5874 /* Returns the clock of the currently programmed mode of the given pipe. */
5875 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5876 {
5877         struct drm_i915_private *dev_priv = dev->dev_private;
5878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5879         int pipe = intel_crtc->pipe;
5880         u32 dpll = I915_READ(DPLL(pipe));
5881         u32 fp;
5882         intel_clock_t clock;
5883
5884         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5885                 fp = I915_READ(FP0(pipe));
5886         else
5887                 fp = I915_READ(FP1(pipe));
5888
5889         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5890         if (IS_PINEVIEW(dev)) {
5891                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5892                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5893         } else {
5894                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5895                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5896         }
5897
5898         if (!IS_GEN2(dev)) {
5899                 if (IS_PINEVIEW(dev))
5900                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5901                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5902                 else
5903                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5904                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5905
5906                 switch (dpll & DPLL_MODE_MASK) {
5907                 case DPLLB_MODE_DAC_SERIAL:
5908                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5909                                 5 : 10;
5910                         break;
5911                 case DPLLB_MODE_LVDS:
5912                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5913                                 7 : 14;
5914                         break;
5915                 default:
5916                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5917                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5918                         return 0;
5919                 }
5920
5921                 /* XXX: Handle the 100Mhz refclk */
5922                 intel_clock(dev, 96000, &clock);
5923         } else {
5924                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5925
5926                 if (is_lvds) {
5927                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5928                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5929                         clock.p2 = 14;
5930
5931                         if ((dpll & PLL_REF_INPUT_MASK) ==
5932                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5933                                 /* XXX: might not be 66MHz */
5934                                 intel_clock(dev, 66000, &clock);
5935                         } else
5936                                 intel_clock(dev, 48000, &clock);
5937                 } else {
5938                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5939                                 clock.p1 = 2;
5940                         else {
5941                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5942                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5943                         }
5944                         if (dpll & PLL_P2_DIVIDE_BY_4)
5945                                 clock.p2 = 4;
5946                         else
5947                                 clock.p2 = 2;
5948
5949                         intel_clock(dev, 48000, &clock);
5950                 }
5951         }
5952
5953         /* XXX: It would be nice to validate the clocks, but we can't reuse
5954          * i830PllIsValid() because it relies on the xf86_config connector
5955          * configuration being accurate, which it isn't necessarily.
5956          */
5957
5958         return clock.dot;
5959 }
5960
5961 /** Returns the currently programmed mode of the given pipe. */
5962 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5963                                              struct drm_crtc *crtc)
5964 {
5965         struct drm_i915_private *dev_priv = dev->dev_private;
5966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967         int pipe = intel_crtc->pipe;
5968         struct drm_display_mode *mode;
5969         int htot = I915_READ(HTOTAL(pipe));
5970         int hsync = I915_READ(HSYNC(pipe));
5971         int vtot = I915_READ(VTOTAL(pipe));
5972         int vsync = I915_READ(VSYNC(pipe));
5973
5974         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5975         if (!mode)
5976                 return NULL;
5977
5978         mode->clock = intel_crtc_clock_get(dev, crtc);
5979         mode->hdisplay = (htot & 0xffff) + 1;
5980         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5981         mode->hsync_start = (hsync & 0xffff) + 1;
5982         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5983         mode->vdisplay = (vtot & 0xffff) + 1;
5984         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5985         mode->vsync_start = (vsync & 0xffff) + 1;
5986         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5987
5988         drm_mode_set_name(mode);
5989
5990         return mode;
5991 }
5992
5993 static void intel_increase_pllclock(struct drm_crtc *crtc)
5994 {
5995         struct drm_device *dev = crtc->dev;
5996         drm_i915_private_t *dev_priv = dev->dev_private;
5997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998         int pipe = intel_crtc->pipe;
5999         int dpll_reg = DPLL(pipe);
6000         int dpll;
6001
6002         if (HAS_PCH_SPLIT(dev))
6003                 return;
6004
6005         if (!dev_priv->lvds_downclock_avail)
6006                 return;
6007
6008         dpll = I915_READ(dpll_reg);
6009         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6010                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6011
6012                 assert_panel_unlocked(dev_priv, pipe);
6013
6014                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6015                 I915_WRITE(dpll_reg, dpll);
6016                 intel_wait_for_vblank(dev, pipe);
6017
6018                 dpll = I915_READ(dpll_reg);
6019                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6020                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6021         }
6022 }
6023
6024 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6025 {
6026         struct drm_device *dev = crtc->dev;
6027         drm_i915_private_t *dev_priv = dev->dev_private;
6028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6029
6030         if (HAS_PCH_SPLIT(dev))
6031                 return;
6032
6033         if (!dev_priv->lvds_downclock_avail)
6034                 return;
6035
6036         /*
6037          * Since this is called by a timer, we should never get here in
6038          * the manual case.
6039          */
6040         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6041                 int pipe = intel_crtc->pipe;
6042                 int dpll_reg = DPLL(pipe);
6043                 int dpll;
6044
6045                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6046
6047                 assert_panel_unlocked(dev_priv, pipe);
6048
6049                 dpll = I915_READ(dpll_reg);
6050                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6051                 I915_WRITE(dpll_reg, dpll);
6052                 intel_wait_for_vblank(dev, pipe);
6053                 dpll = I915_READ(dpll_reg);
6054                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6055                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6056         }
6057
6058 }
6059
6060 void intel_mark_busy(struct drm_device *dev)
6061 {
6062         i915_update_gfx_val(dev->dev_private);
6063 }
6064
6065 void intel_mark_idle(struct drm_device *dev)
6066 {
6067 }
6068
6069 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6070 {
6071         struct drm_device *dev = obj->base.dev;
6072         struct drm_crtc *crtc;
6073
6074         if (!i915_powersave)
6075                 return;
6076
6077         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6078                 if (!crtc->fb)
6079                         continue;
6080
6081                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6082                         intel_increase_pllclock(crtc);
6083         }
6084 }
6085
6086 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6087 {
6088         struct drm_device *dev = obj->base.dev;
6089         struct drm_crtc *crtc;
6090
6091         if (!i915_powersave)
6092                 return;
6093
6094         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6095                 if (!crtc->fb)
6096                         continue;
6097
6098                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6099                         intel_decrease_pllclock(crtc);
6100         }
6101 }
6102
6103 static void intel_crtc_destroy(struct drm_crtc *crtc)
6104 {
6105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6106         struct drm_device *dev = crtc->dev;
6107         struct intel_unpin_work *work;
6108         unsigned long flags;
6109
6110         spin_lock_irqsave(&dev->event_lock, flags);
6111         work = intel_crtc->unpin_work;
6112         intel_crtc->unpin_work = NULL;
6113         spin_unlock_irqrestore(&dev->event_lock, flags);
6114
6115         if (work) {
6116                 cancel_work_sync(&work->work);
6117                 kfree(work);
6118         }
6119
6120         drm_crtc_cleanup(crtc);
6121
6122         kfree(intel_crtc);
6123 }
6124
6125 static void intel_unpin_work_fn(struct work_struct *__work)
6126 {
6127         struct intel_unpin_work *work =
6128                 container_of(__work, struct intel_unpin_work, work);
6129
6130         mutex_lock(&work->dev->struct_mutex);
6131         intel_unpin_fb_obj(work->old_fb_obj);
6132         drm_gem_object_unreference(&work->pending_flip_obj->base);
6133         drm_gem_object_unreference(&work->old_fb_obj->base);
6134
6135         intel_update_fbc(work->dev);
6136         mutex_unlock(&work->dev->struct_mutex);
6137         kfree(work);
6138 }
6139
6140 static void do_intel_finish_page_flip(struct drm_device *dev,
6141                                       struct drm_crtc *crtc)
6142 {
6143         drm_i915_private_t *dev_priv = dev->dev_private;
6144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145         struct intel_unpin_work *work;
6146         struct drm_i915_gem_object *obj;
6147         struct drm_pending_vblank_event *e;
6148         struct timeval tnow, tvbl;
6149         unsigned long flags;
6150
6151         /* Ignore early vblank irqs */
6152         if (intel_crtc == NULL)
6153                 return;
6154
6155         do_gettimeofday(&tnow);
6156
6157         spin_lock_irqsave(&dev->event_lock, flags);
6158         work = intel_crtc->unpin_work;
6159         if (work == NULL || !work->pending) {
6160                 spin_unlock_irqrestore(&dev->event_lock, flags);
6161                 return;
6162         }
6163
6164         intel_crtc->unpin_work = NULL;
6165
6166         if (work->event) {
6167                 e = work->event;
6168                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6169
6170                 /* Called before vblank count and timestamps have
6171                  * been updated for the vblank interval of flip
6172                  * completion? Need to increment vblank count and
6173                  * add one videorefresh duration to returned timestamp
6174                  * to account for this. We assume this happened if we
6175                  * get called over 0.9 frame durations after the last
6176                  * timestamped vblank.
6177                  *
6178                  * This calculation can not be used with vrefresh rates
6179                  * below 5Hz (10Hz to be on the safe side) without
6180                  * promoting to 64 integers.
6181                  */
6182                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6183                     9 * crtc->framedur_ns) {
6184                         e->event.sequence++;
6185                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6186                                              crtc->framedur_ns);
6187                 }
6188
6189                 e->event.tv_sec = tvbl.tv_sec;
6190                 e->event.tv_usec = tvbl.tv_usec;
6191
6192                 list_add_tail(&e->base.link,
6193                               &e->base.file_priv->event_list);
6194                 wake_up_interruptible(&e->base.file_priv->event_wait);
6195         }
6196
6197         drm_vblank_put(dev, intel_crtc->pipe);
6198
6199         spin_unlock_irqrestore(&dev->event_lock, flags);
6200
6201         obj = work->old_fb_obj;
6202
6203         atomic_clear_mask(1 << intel_crtc->plane,
6204                           &obj->pending_flip.counter);
6205         if (atomic_read(&obj->pending_flip) == 0)
6206                 wake_up(&dev_priv->pending_flip_queue);
6207
6208         schedule_work(&work->work);
6209
6210         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6211 }
6212
6213 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6214 {
6215         drm_i915_private_t *dev_priv = dev->dev_private;
6216         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6217
6218         do_intel_finish_page_flip(dev, crtc);
6219 }
6220
6221 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6222 {
6223         drm_i915_private_t *dev_priv = dev->dev_private;
6224         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6225
6226         do_intel_finish_page_flip(dev, crtc);
6227 }
6228
6229 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6230 {
6231         drm_i915_private_t *dev_priv = dev->dev_private;
6232         struct intel_crtc *intel_crtc =
6233                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6234         unsigned long flags;
6235
6236         spin_lock_irqsave(&dev->event_lock, flags);
6237         if (intel_crtc->unpin_work) {
6238                 if ((++intel_crtc->unpin_work->pending) > 1)
6239                         DRM_ERROR("Prepared flip multiple times\n");
6240         } else {
6241                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6242         }
6243         spin_unlock_irqrestore(&dev->event_lock, flags);
6244 }
6245
6246 static int intel_gen2_queue_flip(struct drm_device *dev,
6247                                  struct drm_crtc *crtc,
6248                                  struct drm_framebuffer *fb,
6249                                  struct drm_i915_gem_object *obj)
6250 {
6251         struct drm_i915_private *dev_priv = dev->dev_private;
6252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6253         u32 flip_mask;
6254         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6255         int ret;
6256
6257         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6258         if (ret)
6259                 goto err;
6260
6261         ret = intel_ring_begin(ring, 6);
6262         if (ret)
6263                 goto err_unpin;
6264
6265         /* Can't queue multiple flips, so wait for the previous
6266          * one to finish before executing the next.
6267          */
6268         if (intel_crtc->plane)
6269                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6270         else
6271                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6272         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6273         intel_ring_emit(ring, MI_NOOP);
6274         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6275                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6276         intel_ring_emit(ring, fb->pitches[0]);
6277         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6278         intel_ring_emit(ring, 0); /* aux display base address, unused */
6279         intel_ring_advance(ring);
6280         return 0;
6281
6282 err_unpin:
6283         intel_unpin_fb_obj(obj);
6284 err:
6285         return ret;
6286 }
6287
6288 static int intel_gen3_queue_flip(struct drm_device *dev,
6289                                  struct drm_crtc *crtc,
6290                                  struct drm_framebuffer *fb,
6291                                  struct drm_i915_gem_object *obj)
6292 {
6293         struct drm_i915_private *dev_priv = dev->dev_private;
6294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295         u32 flip_mask;
6296         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6297         int ret;
6298
6299         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6300         if (ret)
6301                 goto err;
6302
6303         ret = intel_ring_begin(ring, 6);
6304         if (ret)
6305                 goto err_unpin;
6306
6307         if (intel_crtc->plane)
6308                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6309         else
6310                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6311         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6312         intel_ring_emit(ring, MI_NOOP);
6313         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6314                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6315         intel_ring_emit(ring, fb->pitches[0]);
6316         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6317         intel_ring_emit(ring, MI_NOOP);
6318
6319         intel_ring_advance(ring);
6320         return 0;
6321
6322 err_unpin:
6323         intel_unpin_fb_obj(obj);
6324 err:
6325         return ret;
6326 }
6327
6328 static int intel_gen4_queue_flip(struct drm_device *dev,
6329                                  struct drm_crtc *crtc,
6330                                  struct drm_framebuffer *fb,
6331                                  struct drm_i915_gem_object *obj)
6332 {
6333         struct drm_i915_private *dev_priv = dev->dev_private;
6334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335         uint32_t pf, pipesrc;
6336         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6337         int ret;
6338
6339         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6340         if (ret)
6341                 goto err;
6342
6343         ret = intel_ring_begin(ring, 4);
6344         if (ret)
6345                 goto err_unpin;
6346
6347         /* i965+ uses the linear or tiled offsets from the
6348          * Display Registers (which do not change across a page-flip)
6349          * so we need only reprogram the base address.
6350          */
6351         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6352                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6353         intel_ring_emit(ring, fb->pitches[0]);
6354         intel_ring_emit(ring,
6355                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6356                         obj->tiling_mode);
6357
6358         /* XXX Enabling the panel-fitter across page-flip is so far
6359          * untested on non-native modes, so ignore it for now.
6360          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6361          */
6362         pf = 0;
6363         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6364         intel_ring_emit(ring, pf | pipesrc);
6365         intel_ring_advance(ring);
6366         return 0;
6367
6368 err_unpin:
6369         intel_unpin_fb_obj(obj);
6370 err:
6371         return ret;
6372 }
6373
6374 static int intel_gen6_queue_flip(struct drm_device *dev,
6375                                  struct drm_crtc *crtc,
6376                                  struct drm_framebuffer *fb,
6377                                  struct drm_i915_gem_object *obj)
6378 {
6379         struct drm_i915_private *dev_priv = dev->dev_private;
6380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6382         uint32_t pf, pipesrc;
6383         int ret;
6384
6385         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6386         if (ret)
6387                 goto err;
6388
6389         ret = intel_ring_begin(ring, 4);
6390         if (ret)
6391                 goto err_unpin;
6392
6393         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6394                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6395         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6396         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6397
6398         /* Contrary to the suggestions in the documentation,
6399          * "Enable Panel Fitter" does not seem to be required when page
6400          * flipping with a non-native mode, and worse causes a normal
6401          * modeset to fail.
6402          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6403          */
6404         pf = 0;
6405         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6406         intel_ring_emit(ring, pf | pipesrc);
6407         intel_ring_advance(ring);
6408         return 0;
6409
6410 err_unpin:
6411         intel_unpin_fb_obj(obj);
6412 err:
6413         return ret;
6414 }
6415
6416 /*
6417  * On gen7 we currently use the blit ring because (in early silicon at least)
6418  * the render ring doesn't give us interrpts for page flip completion, which
6419  * means clients will hang after the first flip is queued.  Fortunately the
6420  * blit ring generates interrupts properly, so use it instead.
6421  */
6422 static int intel_gen7_queue_flip(struct drm_device *dev,
6423                                  struct drm_crtc *crtc,
6424                                  struct drm_framebuffer *fb,
6425                                  struct drm_i915_gem_object *obj)
6426 {
6427         struct drm_i915_private *dev_priv = dev->dev_private;
6428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6429         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6430         uint32_t plane_bit = 0;
6431         int ret;
6432
6433         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6434         if (ret)
6435                 goto err;
6436
6437         switch(intel_crtc->plane) {
6438         case PLANE_A:
6439                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6440                 break;
6441         case PLANE_B:
6442                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6443                 break;
6444         case PLANE_C:
6445                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6446                 break;
6447         default:
6448                 WARN_ONCE(1, "unknown plane in flip command\n");
6449                 ret = -ENODEV;
6450                 goto err_unpin;
6451         }
6452
6453         ret = intel_ring_begin(ring, 4);
6454         if (ret)
6455                 goto err_unpin;
6456
6457         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6458         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6459         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6460         intel_ring_emit(ring, (MI_NOOP));
6461         intel_ring_advance(ring);
6462         return 0;
6463
6464 err_unpin:
6465         intel_unpin_fb_obj(obj);
6466 err:
6467         return ret;
6468 }
6469
6470 static int intel_default_queue_flip(struct drm_device *dev,
6471                                     struct drm_crtc *crtc,
6472                                     struct drm_framebuffer *fb,
6473                                     struct drm_i915_gem_object *obj)
6474 {
6475         return -ENODEV;
6476 }
6477
6478 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6479                                 struct drm_framebuffer *fb,
6480                                 struct drm_pending_vblank_event *event)
6481 {
6482         struct drm_device *dev = crtc->dev;
6483         struct drm_i915_private *dev_priv = dev->dev_private;
6484         struct intel_framebuffer *intel_fb;
6485         struct drm_i915_gem_object *obj;
6486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6487         struct intel_unpin_work *work;
6488         unsigned long flags;
6489         int ret;
6490
6491         /* Can't change pixel format via MI display flips. */
6492         if (fb->pixel_format != crtc->fb->pixel_format)
6493                 return -EINVAL;
6494
6495         /*
6496          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6497          * Note that pitch changes could also affect these register.
6498          */
6499         if (INTEL_INFO(dev)->gen > 3 &&
6500             (fb->offsets[0] != crtc->fb->offsets[0] ||
6501              fb->pitches[0] != crtc->fb->pitches[0]))
6502                 return -EINVAL;
6503
6504         work = kzalloc(sizeof *work, GFP_KERNEL);
6505         if (work == NULL)
6506                 return -ENOMEM;
6507
6508         work->event = event;
6509         work->dev = crtc->dev;
6510         intel_fb = to_intel_framebuffer(crtc->fb);
6511         work->old_fb_obj = intel_fb->obj;
6512         INIT_WORK(&work->work, intel_unpin_work_fn);
6513
6514         ret = drm_vblank_get(dev, intel_crtc->pipe);
6515         if (ret)
6516                 goto free_work;
6517
6518         /* We borrow the event spin lock for protecting unpin_work */
6519         spin_lock_irqsave(&dev->event_lock, flags);
6520         if (intel_crtc->unpin_work) {
6521                 spin_unlock_irqrestore(&dev->event_lock, flags);
6522                 kfree(work);
6523                 drm_vblank_put(dev, intel_crtc->pipe);
6524
6525                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6526                 return -EBUSY;
6527         }
6528         intel_crtc->unpin_work = work;
6529         spin_unlock_irqrestore(&dev->event_lock, flags);
6530
6531         intel_fb = to_intel_framebuffer(fb);
6532         obj = intel_fb->obj;
6533
6534         ret = i915_mutex_lock_interruptible(dev);
6535         if (ret)
6536                 goto cleanup;
6537
6538         /* Reference the objects for the scheduled work. */
6539         drm_gem_object_reference(&work->old_fb_obj->base);
6540         drm_gem_object_reference(&obj->base);
6541
6542         crtc->fb = fb;
6543
6544         work->pending_flip_obj = obj;
6545
6546         work->enable_stall_check = true;
6547
6548         /* Block clients from rendering to the new back buffer until
6549          * the flip occurs and the object is no longer visible.
6550          */
6551         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6552
6553         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6554         if (ret)
6555                 goto cleanup_pending;
6556
6557         intel_disable_fbc(dev);
6558         intel_mark_fb_busy(obj);
6559         mutex_unlock(&dev->struct_mutex);
6560
6561         trace_i915_flip_request(intel_crtc->plane, obj);
6562
6563         return 0;
6564
6565 cleanup_pending:
6566         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6567         drm_gem_object_unreference(&work->old_fb_obj->base);
6568         drm_gem_object_unreference(&obj->base);
6569         mutex_unlock(&dev->struct_mutex);
6570
6571 cleanup:
6572         spin_lock_irqsave(&dev->event_lock, flags);
6573         intel_crtc->unpin_work = NULL;
6574         spin_unlock_irqrestore(&dev->event_lock, flags);
6575
6576         drm_vblank_put(dev, intel_crtc->pipe);
6577 free_work:
6578         kfree(work);
6579
6580         return ret;
6581 }
6582
6583 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6584         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6585         .load_lut = intel_crtc_load_lut,
6586         .disable = intel_crtc_noop,
6587 };
6588
6589 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6590 {
6591         struct intel_encoder *other_encoder;
6592         struct drm_crtc *crtc = &encoder->new_crtc->base;
6593
6594         if (WARN_ON(!crtc))
6595                 return false;
6596
6597         list_for_each_entry(other_encoder,
6598                             &crtc->dev->mode_config.encoder_list,
6599                             base.head) {
6600
6601                 if (&other_encoder->new_crtc->base != crtc ||
6602                     encoder == other_encoder)
6603                         continue;
6604                 else
6605                         return true;
6606         }
6607
6608         return false;
6609 }
6610
6611 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6612                                   struct drm_crtc *crtc)
6613 {
6614         struct drm_device *dev;
6615         struct drm_crtc *tmp;
6616         int crtc_mask = 1;
6617
6618         WARN(!crtc, "checking null crtc?\n");
6619
6620         dev = crtc->dev;
6621
6622         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6623                 if (tmp == crtc)
6624                         break;
6625                 crtc_mask <<= 1;
6626         }
6627
6628         if (encoder->possible_crtcs & crtc_mask)
6629                 return true;
6630         return false;
6631 }
6632
6633 static void
6634 intel_crtc_prepare_encoders(struct drm_device *dev)
6635 {
6636         struct intel_encoder *encoder;
6637
6638         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6639                 /* Disable unused encoders */
6640                 if (encoder->base.crtc == NULL)
6641                         encoder->disable(encoder);
6642         }
6643 }
6644
6645 /**
6646  * intel_modeset_update_staged_output_state
6647  *
6648  * Updates the staged output configuration state, e.g. after we've read out the
6649  * current hw state.
6650  */
6651 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6652 {
6653         struct intel_encoder *encoder;
6654         struct intel_connector *connector;
6655
6656         list_for_each_entry(connector, &dev->mode_config.connector_list,
6657                             base.head) {
6658                 connector->new_encoder =
6659                         to_intel_encoder(connector->base.encoder);
6660         }
6661
6662         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6663                             base.head) {
6664                 encoder->new_crtc =
6665                         to_intel_crtc(encoder->base.crtc);
6666         }
6667 }
6668
6669 /**
6670  * intel_modeset_commit_output_state
6671  *
6672  * This function copies the stage display pipe configuration to the real one.
6673  */
6674 static void intel_modeset_commit_output_state(struct drm_device *dev)
6675 {
6676         struct intel_encoder *encoder;
6677         struct intel_connector *connector;
6678
6679         list_for_each_entry(connector, &dev->mode_config.connector_list,
6680                             base.head) {
6681                 connector->base.encoder = &connector->new_encoder->base;
6682         }
6683
6684         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6685                             base.head) {
6686                 encoder->base.crtc = &encoder->new_crtc->base;
6687         }
6688 }
6689
6690 static struct drm_display_mode *
6691 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6692                             struct drm_display_mode *mode)
6693 {
6694         struct drm_device *dev = crtc->dev;
6695         struct drm_display_mode *adjusted_mode;
6696         struct drm_encoder_helper_funcs *encoder_funcs;
6697         struct intel_encoder *encoder;
6698
6699         adjusted_mode = drm_mode_duplicate(dev, mode);
6700         if (!adjusted_mode)
6701                 return ERR_PTR(-ENOMEM);
6702
6703         /* Pass our mode to the connectors and the CRTC to give them a chance to
6704          * adjust it according to limitations or connector properties, and also
6705          * a chance to reject the mode entirely.
6706          */
6707         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6708                             base.head) {
6709
6710                 if (&encoder->new_crtc->base != crtc)
6711                         continue;
6712                 encoder_funcs = encoder->base.helper_private;
6713                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6714                                                 adjusted_mode))) {
6715                         DRM_DEBUG_KMS("Encoder fixup failed\n");
6716                         goto fail;
6717                 }
6718         }
6719
6720         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6721                 DRM_DEBUG_KMS("CRTC fixup failed\n");
6722                 goto fail;
6723         }
6724         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6725
6726         return adjusted_mode;
6727 fail:
6728         drm_mode_destroy(dev, adjusted_mode);
6729         return ERR_PTR(-EINVAL);
6730 }
6731
6732 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6733  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6734 static void
6735 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6736                              unsigned *prepare_pipes, unsigned *disable_pipes)
6737 {
6738         struct intel_crtc *intel_crtc;
6739         struct drm_device *dev = crtc->dev;
6740         struct intel_encoder *encoder;
6741         struct intel_connector *connector;
6742         struct drm_crtc *tmp_crtc;
6743
6744         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6745
6746         /* Check which crtcs have changed outputs connected to them, these need
6747          * to be part of the prepare_pipes mask. We don't (yet) support global
6748          * modeset across multiple crtcs, so modeset_pipes will only have one
6749          * bit set at most. */
6750         list_for_each_entry(connector, &dev->mode_config.connector_list,
6751                             base.head) {
6752                 if (connector->base.encoder == &connector->new_encoder->base)
6753                         continue;
6754
6755                 if (connector->base.encoder) {
6756                         tmp_crtc = connector->base.encoder->crtc;
6757
6758                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6759                 }
6760
6761                 if (connector->new_encoder)
6762                         *prepare_pipes |=
6763                                 1 << connector->new_encoder->new_crtc->pipe;
6764         }
6765
6766         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6767                             base.head) {
6768                 if (encoder->base.crtc == &encoder->new_crtc->base)
6769                         continue;
6770
6771                 if (encoder->base.crtc) {
6772                         tmp_crtc = encoder->base.crtc;
6773
6774                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6775                 }
6776
6777                 if (encoder->new_crtc)
6778                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6779         }
6780
6781         /* Check for any pipes that will be fully disabled ... */
6782         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6783                             base.head) {
6784                 bool used = false;
6785
6786                 /* Don't try to disable disabled crtcs. */
6787                 if (!intel_crtc->base.enabled)
6788                         continue;
6789
6790                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6791                                     base.head) {
6792                         if (encoder->new_crtc == intel_crtc)
6793                                 used = true;
6794                 }
6795
6796                 if (!used)
6797                         *disable_pipes |= 1 << intel_crtc->pipe;
6798         }
6799
6800
6801         /* set_mode is also used to update properties on life display pipes. */
6802         intel_crtc = to_intel_crtc(crtc);
6803         if (crtc->enabled)
6804                 *prepare_pipes |= 1 << intel_crtc->pipe;
6805
6806         /* We only support modeset on one single crtc, hence we need to do that
6807          * only for the passed in crtc iff we change anything else than just
6808          * disable crtcs.
6809          *
6810          * This is actually not true, to be fully compatible with the old crtc
6811          * helper we automatically disable _any_ output (i.e. doesn't need to be
6812          * connected to the crtc we're modesetting on) if it's disconnected.
6813          * Which is a rather nutty api (since changed the output configuration
6814          * without userspace's explicit request can lead to confusion), but
6815          * alas. Hence we currently need to modeset on all pipes we prepare. */
6816         if (*prepare_pipes)
6817                 *modeset_pipes = *prepare_pipes;
6818
6819         /* ... and mask these out. */
6820         *modeset_pipes &= ~(*disable_pipes);
6821         *prepare_pipes &= ~(*disable_pipes);
6822 }
6823
6824 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6825         list_for_each_entry((intel_crtc), \
6826                             &(dev)->mode_config.crtc_list, \
6827                             base.head) \
6828                 if (mask & (1 <<(intel_crtc)->pipe)) \
6829
6830 bool intel_set_mode(struct drm_crtc *crtc,
6831                     struct drm_display_mode *mode,
6832                     int x, int y, struct drm_framebuffer *fb)
6833 {
6834         struct drm_device *dev = crtc->dev;
6835         drm_i915_private_t *dev_priv = dev->dev_private;
6836         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6837         struct drm_encoder_helper_funcs *encoder_funcs;
6838         struct drm_encoder *encoder;
6839         struct intel_crtc *intel_crtc;
6840         unsigned disable_pipes, prepare_pipes, modeset_pipes;
6841         bool ret = true;
6842
6843         intel_modeset_affected_pipes(crtc, &modeset_pipes,
6844                                      &prepare_pipes, &disable_pipes);
6845
6846         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
6847                       modeset_pipes, prepare_pipes, disable_pipes);
6848
6849         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
6850                 intel_crtc_disable(&intel_crtc->base);
6851
6852         intel_modeset_commit_output_state(dev);
6853
6854         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6855                             base.head)
6856                 intel_crtc->base.enabled = drm_helper_crtc_in_use(crtc);
6857
6858         saved_hwmode = crtc->hwmode;
6859         saved_mode = crtc->mode;
6860
6861         /* Hack: Because we don't (yet) support global modeset on multiple
6862          * crtcs, we don't keep track of the new mode for more than one crtc.
6863          * Hence simply check whether any bit is set in modeset_pipes in all the
6864          * pieces of code that are not yet converted to deal with mutliple crtcs
6865          * changing their mode at the same time. */
6866         adjusted_mode = NULL;
6867         if (modeset_pipes) {
6868                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
6869                 if (IS_ERR(adjusted_mode)) {
6870                         return false;
6871                 }
6872
6873                 intel_crtc_prepare_encoders(dev);
6874         }
6875
6876         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
6877                 dev_priv->display.crtc_disable(&intel_crtc->base);
6878
6879         if (modeset_pipes) {
6880                 crtc->mode = *mode;
6881                 crtc->x = x;
6882                 crtc->y = y;
6883         }
6884
6885         /* Set up the DPLL and any encoders state that needs to adjust or depend
6886          * on the DPLL.
6887          */
6888         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
6889                 ret = !intel_crtc_mode_set(&intel_crtc->base,
6890                                            mode, adjusted_mode,
6891                                            x, y, fb);
6892                 if (!ret)
6893                     goto done;
6894
6895                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6896
6897                         if (encoder->crtc != &intel_crtc->base)
6898                                 continue;
6899
6900                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6901                                 encoder->base.id, drm_get_encoder_name(encoder),
6902                                 mode->base.id, mode->name);
6903                         encoder_funcs = encoder->helper_private;
6904                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6905                 }
6906         }
6907
6908         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
6909         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
6910                 dev_priv->display.crtc_enable(&intel_crtc->base);
6911
6912         if (modeset_pipes) {
6913                 /* Store real post-adjustment hardware mode. */
6914                 crtc->hwmode = *adjusted_mode;
6915
6916                 /* Calculate and store various constants which
6917                  * are later needed by vblank and swap-completion
6918                  * timestamping. They are derived from true hwmode.
6919                  */
6920                 drm_calc_timestamping_constants(crtc);
6921         }
6922
6923         /* FIXME: add subpixel order */
6924 done:
6925         drm_mode_destroy(dev, adjusted_mode);
6926         if (!ret && crtc->enabled) {
6927                 crtc->hwmode = saved_hwmode;
6928                 crtc->mode = saved_mode;
6929         }
6930
6931         return ret;
6932 }
6933
6934 #undef for_each_intel_crtc_masked
6935
6936 static void intel_set_config_free(struct intel_set_config *config)
6937 {
6938         if (!config)
6939                 return;
6940
6941         kfree(config->save_connector_encoders);
6942         kfree(config->save_encoder_crtcs);
6943         kfree(config);
6944 }
6945
6946 static int intel_set_config_save_state(struct drm_device *dev,
6947                                        struct intel_set_config *config)
6948 {
6949         struct drm_encoder *encoder;
6950         struct drm_connector *connector;
6951         int count;
6952
6953         config->save_encoder_crtcs =
6954                 kcalloc(dev->mode_config.num_encoder,
6955                         sizeof(struct drm_crtc *), GFP_KERNEL);
6956         if (!config->save_encoder_crtcs)
6957                 return -ENOMEM;
6958
6959         config->save_connector_encoders =
6960                 kcalloc(dev->mode_config.num_connector,
6961                         sizeof(struct drm_encoder *), GFP_KERNEL);
6962         if (!config->save_connector_encoders)
6963                 return -ENOMEM;
6964
6965         /* Copy data. Note that driver private data is not affected.
6966          * Should anything bad happen only the expected state is
6967          * restored, not the drivers personal bookkeeping.
6968          */
6969         count = 0;
6970         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6971                 config->save_encoder_crtcs[count++] = encoder->crtc;
6972         }
6973
6974         count = 0;
6975         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6976                 config->save_connector_encoders[count++] = connector->encoder;
6977         }
6978
6979         return 0;
6980 }
6981
6982 static void intel_set_config_restore_state(struct drm_device *dev,
6983                                            struct intel_set_config *config)
6984 {
6985         struct intel_encoder *encoder;
6986         struct intel_connector *connector;
6987         int count;
6988
6989         count = 0;
6990         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6991                 encoder->new_crtc =
6992                         to_intel_crtc(config->save_encoder_crtcs[count++]);
6993         }
6994
6995         count = 0;
6996         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
6997                 connector->new_encoder =
6998                         to_intel_encoder(config->save_connector_encoders[count++]);
6999         }
7000 }
7001
7002 static void
7003 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7004                                       struct intel_set_config *config)
7005 {
7006
7007         /* We should be able to check here if the fb has the same properties
7008          * and then just flip_or_move it */
7009         if (set->crtc->fb != set->fb) {
7010                 /* If we have no fb then treat it as a full mode set */
7011                 if (set->crtc->fb == NULL) {
7012                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7013                         config->mode_changed = true;
7014                 } else if (set->fb == NULL) {
7015                         config->mode_changed = true;
7016                 } else if (set->fb->depth != set->crtc->fb->depth) {
7017                         config->mode_changed = true;
7018                 } else if (set->fb->bits_per_pixel !=
7019                            set->crtc->fb->bits_per_pixel) {
7020                         config->mode_changed = true;
7021                 } else
7022                         config->fb_changed = true;
7023         }
7024
7025         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7026                 config->fb_changed = true;
7027
7028         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7029                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7030                 drm_mode_debug_printmodeline(&set->crtc->mode);
7031                 drm_mode_debug_printmodeline(set->mode);
7032                 config->mode_changed = true;
7033         }
7034 }
7035
7036 static int
7037 intel_modeset_stage_output_state(struct drm_device *dev,
7038                                  struct drm_mode_set *set,
7039                                  struct intel_set_config *config)
7040 {
7041         struct drm_crtc *new_crtc;
7042         struct intel_connector *connector;
7043         struct intel_encoder *encoder;
7044         int count, ro;
7045
7046         /* The upper layers ensure that we either disabl a crtc or have a list
7047          * of connectors. For paranoia, double-check this. */
7048         WARN_ON(!set->fb && (set->num_connectors != 0));
7049         WARN_ON(set->fb && (set->num_connectors == 0));
7050
7051         count = 0;
7052         list_for_each_entry(connector, &dev->mode_config.connector_list,
7053                             base.head) {
7054                 /* Otherwise traverse passed in connector list and get encoders
7055                  * for them. */
7056                 for (ro = 0; ro < set->num_connectors; ro++) {
7057                         if (set->connectors[ro] == &connector->base) {
7058                                 connector->new_encoder = connector->encoder;
7059                                 break;
7060                         }
7061                 }
7062
7063                 /* If we disable the crtc, disable all its connectors. Also, if
7064                  * the connector is on the changing crtc but not on the new
7065                  * connector list, disable it. */
7066                 if ((!set->fb || ro == set->num_connectors) &&
7067                     connector->base.encoder &&
7068                     connector->base.encoder->crtc == set->crtc) {
7069                         connector->new_encoder = NULL;
7070
7071                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7072                                 connector->base.base.id,
7073                                 drm_get_connector_name(&connector->base));
7074                 }
7075
7076
7077                 if (&connector->new_encoder->base != connector->base.encoder) {
7078                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7079                         config->mode_changed = true;
7080                 }
7081
7082                 /* Disable all disconnected encoders. */
7083                 if (connector->base.status == connector_status_disconnected)
7084                         connector->new_encoder = NULL;
7085         }
7086         /* connector->new_encoder is now updated for all connectors. */
7087
7088         /* Update crtc of enabled connectors. */
7089         count = 0;
7090         list_for_each_entry(connector, &dev->mode_config.connector_list,
7091                             base.head) {
7092                 if (!connector->new_encoder)
7093                         continue;
7094
7095                 new_crtc = connector->new_encoder->base.crtc;
7096
7097                 for (ro = 0; ro < set->num_connectors; ro++) {
7098                         if (set->connectors[ro] == &connector->base)
7099                                 new_crtc = set->crtc;
7100                 }
7101
7102                 /* Make sure the new CRTC will work with the encoder */
7103                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7104                                            new_crtc)) {
7105                         return -EINVAL;
7106                 }
7107                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7108
7109                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7110                         connector->base.base.id,
7111                         drm_get_connector_name(&connector->base),
7112                         new_crtc->base.id);
7113         }
7114
7115         /* Check for any encoders that needs to be disabled. */
7116         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7117                             base.head) {
7118                 list_for_each_entry(connector,
7119                                     &dev->mode_config.connector_list,
7120                                     base.head) {
7121                         if (connector->new_encoder == encoder) {
7122                                 WARN_ON(!connector->new_encoder->new_crtc);
7123
7124                                 goto next_encoder;
7125                         }
7126                 }
7127                 encoder->new_crtc = NULL;
7128 next_encoder:
7129                 /* Only now check for crtc changes so we don't miss encoders
7130                  * that will be disabled. */
7131                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7132                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7133                         config->mode_changed = true;
7134                 }
7135         }
7136         /* Now we've also updated encoder->new_crtc for all encoders. */
7137
7138         return 0;
7139 }
7140
7141 static int intel_crtc_set_config(struct drm_mode_set *set)
7142 {
7143         struct drm_device *dev;
7144         struct drm_mode_set save_set;
7145         struct intel_set_config *config;
7146         int ret;
7147         int i;
7148
7149         BUG_ON(!set);
7150         BUG_ON(!set->crtc);
7151         BUG_ON(!set->crtc->helper_private);
7152
7153         if (!set->mode)
7154                 set->fb = NULL;
7155
7156         /* The fb helper likes to play gross jokes with ->mode_set_config.
7157          * Unfortunately the crtc helper doesn't do much at all for this case,
7158          * so we have to cope with this madness until the fb helper is fixed up. */
7159         if (set->fb && set->num_connectors == 0)
7160                 return 0;
7161
7162         if (set->fb) {
7163                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7164                                 set->crtc->base.id, set->fb->base.id,
7165                                 (int)set->num_connectors, set->x, set->y);
7166         } else {
7167                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7168         }
7169
7170         dev = set->crtc->dev;
7171
7172         ret = -ENOMEM;
7173         config = kzalloc(sizeof(*config), GFP_KERNEL);
7174         if (!config)
7175                 goto out_config;
7176
7177         ret = intel_set_config_save_state(dev, config);
7178         if (ret)
7179                 goto out_config;
7180
7181         save_set.crtc = set->crtc;
7182         save_set.mode = &set->crtc->mode;
7183         save_set.x = set->crtc->x;
7184         save_set.y = set->crtc->y;
7185         save_set.fb = set->crtc->fb;
7186
7187         /* Compute whether we need a full modeset, only an fb base update or no
7188          * change at all. In the future we might also check whether only the
7189          * mode changed, e.g. for LVDS where we only change the panel fitter in
7190          * such cases. */
7191         intel_set_config_compute_mode_changes(set, config);
7192
7193         ret = intel_modeset_stage_output_state(dev, set, config);
7194         if (ret)
7195                 goto fail;
7196
7197         if (config->mode_changed) {
7198                 if (set->mode) {
7199                         DRM_DEBUG_KMS("attempting to set mode from"
7200                                         " userspace\n");
7201                         drm_mode_debug_printmodeline(set->mode);
7202                 }
7203
7204                 if (!intel_set_mode(set->crtc, set->mode,
7205                                     set->x, set->y, set->fb)) {
7206                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7207                                   set->crtc->base.id);
7208                         ret = -EINVAL;
7209                         goto fail;
7210                 }
7211
7212                 if (set->crtc->enabled) {
7213                         DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7214                         for (i = 0; i < set->num_connectors; i++) {
7215                                 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7216                                               drm_get_connector_name(set->connectors[i]));
7217                                 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7218                         }
7219                 }
7220         } else if (config->fb_changed) {
7221                 ret = intel_pipe_set_base(set->crtc,
7222                                           set->x, set->y, set->fb);
7223         }
7224
7225         intel_set_config_free(config);
7226
7227         return 0;
7228
7229 fail:
7230         intel_set_config_restore_state(dev, config);
7231
7232         /* Try to restore the config */
7233         if (config->mode_changed &&
7234             !intel_set_mode(save_set.crtc, save_set.mode,
7235                             save_set.x, save_set.y, save_set.fb))
7236                 DRM_ERROR("failed to restore config after modeset failure\n");
7237
7238 out_config:
7239         intel_set_config_free(config);
7240         return ret;
7241 }
7242
7243 static const struct drm_crtc_funcs intel_crtc_funcs = {
7244         .cursor_set = intel_crtc_cursor_set,
7245         .cursor_move = intel_crtc_cursor_move,
7246         .gamma_set = intel_crtc_gamma_set,
7247         .set_config = intel_crtc_set_config,
7248         .destroy = intel_crtc_destroy,
7249         .page_flip = intel_crtc_page_flip,
7250 };
7251
7252 static void intel_pch_pll_init(struct drm_device *dev)
7253 {
7254         drm_i915_private_t *dev_priv = dev->dev_private;
7255         int i;
7256
7257         if (dev_priv->num_pch_pll == 0) {
7258                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7259                 return;
7260         }
7261
7262         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7263                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7264                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7265                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7266         }
7267 }
7268
7269 static void intel_crtc_init(struct drm_device *dev, int pipe)
7270 {
7271         drm_i915_private_t *dev_priv = dev->dev_private;
7272         struct intel_crtc *intel_crtc;
7273         int i;
7274
7275         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7276         if (intel_crtc == NULL)
7277                 return;
7278
7279         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7280
7281         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7282         for (i = 0; i < 256; i++) {
7283                 intel_crtc->lut_r[i] = i;
7284                 intel_crtc->lut_g[i] = i;
7285                 intel_crtc->lut_b[i] = i;
7286         }
7287
7288         /* Swap pipes & planes for FBC on pre-965 */
7289         intel_crtc->pipe = pipe;
7290         intel_crtc->plane = pipe;
7291         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7292                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7293                 intel_crtc->plane = !pipe;
7294         }
7295
7296         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7297                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7298         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7299         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7300
7301         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7302
7303         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7304 }
7305
7306 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7307                                 struct drm_file *file)
7308 {
7309         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7310         struct drm_mode_object *drmmode_obj;
7311         struct intel_crtc *crtc;
7312
7313         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7314                 return -ENODEV;
7315
7316         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7317                         DRM_MODE_OBJECT_CRTC);
7318
7319         if (!drmmode_obj) {
7320                 DRM_ERROR("no such CRTC id\n");
7321                 return -EINVAL;
7322         }
7323
7324         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7325         pipe_from_crtc_id->pipe = crtc->pipe;
7326
7327         return 0;
7328 }
7329
7330 static int intel_encoder_clones(struct intel_encoder *encoder)
7331 {
7332         struct drm_device *dev = encoder->base.dev;
7333         struct intel_encoder *source_encoder;
7334         int index_mask = 0;
7335         int entry = 0;
7336
7337         list_for_each_entry(source_encoder,
7338                             &dev->mode_config.encoder_list, base.head) {
7339
7340                 if (encoder == source_encoder)
7341                         index_mask |= (1 << entry);
7342
7343                 /* Intel hw has only one MUX where enocoders could be cloned. */
7344                 if (encoder->cloneable && source_encoder->cloneable)
7345                         index_mask |= (1 << entry);
7346
7347                 entry++;
7348         }
7349
7350         return index_mask;
7351 }
7352
7353 static bool has_edp_a(struct drm_device *dev)
7354 {
7355         struct drm_i915_private *dev_priv = dev->dev_private;
7356
7357         if (!IS_MOBILE(dev))
7358                 return false;
7359
7360         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7361                 return false;
7362
7363         if (IS_GEN5(dev) &&
7364             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7365                 return false;
7366
7367         return true;
7368 }
7369
7370 static void intel_setup_outputs(struct drm_device *dev)
7371 {
7372         struct drm_i915_private *dev_priv = dev->dev_private;
7373         struct intel_encoder *encoder;
7374         bool dpd_is_edp = false;
7375         bool has_lvds;
7376
7377         has_lvds = intel_lvds_init(dev);
7378         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7379                 /* disable the panel fitter on everything but LVDS */
7380                 I915_WRITE(PFIT_CONTROL, 0);
7381         }
7382
7383         if (HAS_PCH_SPLIT(dev)) {
7384                 dpd_is_edp = intel_dpd_is_edp(dev);
7385
7386                 if (has_edp_a(dev))
7387                         intel_dp_init(dev, DP_A, PORT_A);
7388
7389                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7390                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7391         }
7392
7393         intel_crt_init(dev);
7394
7395         if (IS_HASWELL(dev)) {
7396                 int found;
7397
7398                 /* Haswell uses DDI functions to detect digital outputs */
7399                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7400                 /* DDI A only supports eDP */
7401                 if (found)
7402                         intel_ddi_init(dev, PORT_A);
7403
7404                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7405                  * register */
7406                 found = I915_READ(SFUSE_STRAP);
7407
7408                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7409                         intel_ddi_init(dev, PORT_B);
7410                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7411                         intel_ddi_init(dev, PORT_C);
7412                 if (found & SFUSE_STRAP_DDID_DETECTED)
7413                         intel_ddi_init(dev, PORT_D);
7414         } else if (HAS_PCH_SPLIT(dev)) {
7415                 int found;
7416
7417                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7418                         /* PCH SDVOB multiplex with HDMIB */
7419                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7420                         if (!found)
7421                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7422                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7423                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7424                 }
7425
7426                 if (I915_READ(HDMIC) & PORT_DETECTED)
7427                         intel_hdmi_init(dev, HDMIC, PORT_C);
7428
7429                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7430                         intel_hdmi_init(dev, HDMID, PORT_D);
7431
7432                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7433                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7434
7435                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7436                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7437         } else if (IS_VALLEYVIEW(dev)) {
7438                 int found;
7439
7440                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7441                         /* SDVOB multiplex with HDMIB */
7442                         found = intel_sdvo_init(dev, SDVOB, true);
7443                         if (!found)
7444                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7445                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7446                                 intel_dp_init(dev, DP_B, PORT_B);
7447                 }
7448
7449                 if (I915_READ(SDVOC) & PORT_DETECTED)
7450                         intel_hdmi_init(dev, SDVOC, PORT_C);
7451
7452                 /* Shares lanes with HDMI on SDVOC */
7453                 if (I915_READ(DP_C) & DP_DETECTED)
7454                         intel_dp_init(dev, DP_C, PORT_C);
7455         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7456                 bool found = false;
7457
7458                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7459                         DRM_DEBUG_KMS("probing SDVOB\n");
7460                         found = intel_sdvo_init(dev, SDVOB, true);
7461                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7462                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7463                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7464                         }
7465
7466                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7467                                 DRM_DEBUG_KMS("probing DP_B\n");
7468                                 intel_dp_init(dev, DP_B, PORT_B);
7469                         }
7470                 }
7471
7472                 /* Before G4X SDVOC doesn't have its own detect register */
7473
7474                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7475                         DRM_DEBUG_KMS("probing SDVOC\n");
7476                         found = intel_sdvo_init(dev, SDVOC, false);
7477                 }
7478
7479                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7480
7481                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7482                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7483                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7484                         }
7485                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7486                                 DRM_DEBUG_KMS("probing DP_C\n");
7487                                 intel_dp_init(dev, DP_C, PORT_C);
7488                         }
7489                 }
7490
7491                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7492                     (I915_READ(DP_D) & DP_DETECTED)) {
7493                         DRM_DEBUG_KMS("probing DP_D\n");
7494                         intel_dp_init(dev, DP_D, PORT_D);
7495                 }
7496         } else if (IS_GEN2(dev))
7497                 intel_dvo_init(dev);
7498
7499         if (SUPPORTS_TV(dev))
7500                 intel_tv_init(dev);
7501
7502         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7503                 encoder->base.possible_crtcs = encoder->crtc_mask;
7504                 encoder->base.possible_clones =
7505                         intel_encoder_clones(encoder);
7506         }
7507
7508         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7509                 ironlake_init_pch_refclk(dev);
7510 }
7511
7512 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7513 {
7514         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7515
7516         drm_framebuffer_cleanup(fb);
7517         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7518
7519         kfree(intel_fb);
7520 }
7521
7522 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7523                                                 struct drm_file *file,
7524                                                 unsigned int *handle)
7525 {
7526         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7527         struct drm_i915_gem_object *obj = intel_fb->obj;
7528
7529         return drm_gem_handle_create(file, &obj->base, handle);
7530 }
7531
7532 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7533         .destroy = intel_user_framebuffer_destroy,
7534         .create_handle = intel_user_framebuffer_create_handle,
7535 };
7536
7537 int intel_framebuffer_init(struct drm_device *dev,
7538                            struct intel_framebuffer *intel_fb,
7539                            struct drm_mode_fb_cmd2 *mode_cmd,
7540                            struct drm_i915_gem_object *obj)
7541 {
7542         int ret;
7543
7544         if (obj->tiling_mode == I915_TILING_Y)
7545                 return -EINVAL;
7546
7547         if (mode_cmd->pitches[0] & 63)
7548                 return -EINVAL;
7549
7550         switch (mode_cmd->pixel_format) {
7551         case DRM_FORMAT_RGB332:
7552         case DRM_FORMAT_RGB565:
7553         case DRM_FORMAT_XRGB8888:
7554         case DRM_FORMAT_XBGR8888:
7555         case DRM_FORMAT_ARGB8888:
7556         case DRM_FORMAT_XRGB2101010:
7557         case DRM_FORMAT_ARGB2101010:
7558                 /* RGB formats are common across chipsets */
7559                 break;
7560         case DRM_FORMAT_YUYV:
7561         case DRM_FORMAT_UYVY:
7562         case DRM_FORMAT_YVYU:
7563         case DRM_FORMAT_VYUY:
7564                 break;
7565         default:
7566                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7567                                 mode_cmd->pixel_format);
7568                 return -EINVAL;
7569         }
7570
7571         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7572         if (ret) {
7573                 DRM_ERROR("framebuffer init failed %d\n", ret);
7574                 return ret;
7575         }
7576
7577         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7578         intel_fb->obj = obj;
7579         return 0;
7580 }
7581
7582 static struct drm_framebuffer *
7583 intel_user_framebuffer_create(struct drm_device *dev,
7584                               struct drm_file *filp,
7585                               struct drm_mode_fb_cmd2 *mode_cmd)
7586 {
7587         struct drm_i915_gem_object *obj;
7588
7589         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7590                                                 mode_cmd->handles[0]));
7591         if (&obj->base == NULL)
7592                 return ERR_PTR(-ENOENT);
7593
7594         return intel_framebuffer_create(dev, mode_cmd, obj);
7595 }
7596
7597 static const struct drm_mode_config_funcs intel_mode_funcs = {
7598         .fb_create = intel_user_framebuffer_create,
7599         .output_poll_changed = intel_fb_output_poll_changed,
7600 };
7601
7602 /* Set up chip specific display functions */
7603 static void intel_init_display(struct drm_device *dev)
7604 {
7605         struct drm_i915_private *dev_priv = dev->dev_private;
7606
7607         /* We always want a DPMS function */
7608         if (HAS_PCH_SPLIT(dev)) {
7609                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7610                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7611                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7612                 dev_priv->display.off = ironlake_crtc_off;
7613                 dev_priv->display.update_plane = ironlake_update_plane;
7614         } else {
7615                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7616                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7617                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7618                 dev_priv->display.off = i9xx_crtc_off;
7619                 dev_priv->display.update_plane = i9xx_update_plane;
7620         }
7621
7622         /* Returns the core display clock speed */
7623         if (IS_VALLEYVIEW(dev))
7624                 dev_priv->display.get_display_clock_speed =
7625                         valleyview_get_display_clock_speed;
7626         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7627                 dev_priv->display.get_display_clock_speed =
7628                         i945_get_display_clock_speed;
7629         else if (IS_I915G(dev))
7630                 dev_priv->display.get_display_clock_speed =
7631                         i915_get_display_clock_speed;
7632         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7633                 dev_priv->display.get_display_clock_speed =
7634                         i9xx_misc_get_display_clock_speed;
7635         else if (IS_I915GM(dev))
7636                 dev_priv->display.get_display_clock_speed =
7637                         i915gm_get_display_clock_speed;
7638         else if (IS_I865G(dev))
7639                 dev_priv->display.get_display_clock_speed =
7640                         i865_get_display_clock_speed;
7641         else if (IS_I85X(dev))
7642                 dev_priv->display.get_display_clock_speed =
7643                         i855_get_display_clock_speed;
7644         else /* 852, 830 */
7645                 dev_priv->display.get_display_clock_speed =
7646                         i830_get_display_clock_speed;
7647
7648         if (HAS_PCH_SPLIT(dev)) {
7649                 if (IS_GEN5(dev)) {
7650                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7651                         dev_priv->display.write_eld = ironlake_write_eld;
7652                 } else if (IS_GEN6(dev)) {
7653                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7654                         dev_priv->display.write_eld = ironlake_write_eld;
7655                 } else if (IS_IVYBRIDGE(dev)) {
7656                         /* FIXME: detect B0+ stepping and use auto training */
7657                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7658                         dev_priv->display.write_eld = ironlake_write_eld;
7659                 } else if (IS_HASWELL(dev)) {
7660                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7661                         dev_priv->display.write_eld = haswell_write_eld;
7662                 } else
7663                         dev_priv->display.update_wm = NULL;
7664         } else if (IS_G4X(dev)) {
7665                 dev_priv->display.write_eld = g4x_write_eld;
7666         }
7667
7668         /* Default just returns -ENODEV to indicate unsupported */
7669         dev_priv->display.queue_flip = intel_default_queue_flip;
7670
7671         switch (INTEL_INFO(dev)->gen) {
7672         case 2:
7673                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7674                 break;
7675
7676         case 3:
7677                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7678                 break;
7679
7680         case 4:
7681         case 5:
7682                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7683                 break;
7684
7685         case 6:
7686                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7687                 break;
7688         case 7:
7689                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7690                 break;
7691         }
7692 }
7693
7694 /*
7695  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7696  * resume, or other times.  This quirk makes sure that's the case for
7697  * affected systems.
7698  */
7699 static void quirk_pipea_force(struct drm_device *dev)
7700 {
7701         struct drm_i915_private *dev_priv = dev->dev_private;
7702
7703         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7704         DRM_INFO("applying pipe a force quirk\n");
7705 }
7706
7707 /*
7708  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7709  */
7710 static void quirk_ssc_force_disable(struct drm_device *dev)
7711 {
7712         struct drm_i915_private *dev_priv = dev->dev_private;
7713         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7714         DRM_INFO("applying lvds SSC disable quirk\n");
7715 }
7716
7717 /*
7718  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7719  * brightness value
7720  */
7721 static void quirk_invert_brightness(struct drm_device *dev)
7722 {
7723         struct drm_i915_private *dev_priv = dev->dev_private;
7724         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7725         DRM_INFO("applying inverted panel brightness quirk\n");
7726 }
7727
7728 struct intel_quirk {
7729         int device;
7730         int subsystem_vendor;
7731         int subsystem_device;
7732         void (*hook)(struct drm_device *dev);
7733 };
7734
7735 static struct intel_quirk intel_quirks[] = {
7736         /* HP Mini needs pipe A force quirk (LP: #322104) */
7737         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7738
7739         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7740         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7741
7742         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7743         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7744
7745         /* 855 & before need to leave pipe A & dpll A up */
7746         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7747         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7748         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7749
7750         /* Lenovo U160 cannot use SSC on LVDS */
7751         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7752
7753         /* Sony Vaio Y cannot use SSC on LVDS */
7754         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7755
7756         /* Acer Aspire 5734Z must invert backlight brightness */
7757         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7758 };
7759
7760 static void intel_init_quirks(struct drm_device *dev)
7761 {
7762         struct pci_dev *d = dev->pdev;
7763         int i;
7764
7765         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7766                 struct intel_quirk *q = &intel_quirks[i];
7767
7768                 if (d->device == q->device &&
7769                     (d->subsystem_vendor == q->subsystem_vendor ||
7770                      q->subsystem_vendor == PCI_ANY_ID) &&
7771                     (d->subsystem_device == q->subsystem_device ||
7772                      q->subsystem_device == PCI_ANY_ID))
7773                         q->hook(dev);
7774         }
7775 }
7776
7777 /* Disable the VGA plane that we never use */
7778 static void i915_disable_vga(struct drm_device *dev)
7779 {
7780         struct drm_i915_private *dev_priv = dev->dev_private;
7781         u8 sr1;
7782         u32 vga_reg;
7783
7784         if (HAS_PCH_SPLIT(dev))
7785                 vga_reg = CPU_VGACNTRL;
7786         else
7787                 vga_reg = VGACNTRL;
7788
7789         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7790         outb(SR01, VGA_SR_INDEX);
7791         sr1 = inb(VGA_SR_DATA);
7792         outb(sr1 | 1<<5, VGA_SR_DATA);
7793         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7794         udelay(300);
7795
7796         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7797         POSTING_READ(vga_reg);
7798 }
7799
7800 void intel_modeset_init_hw(struct drm_device *dev)
7801 {
7802         /* We attempt to init the necessary power wells early in the initialization
7803          * time, so the subsystems that expect power to be enabled can work.
7804          */
7805         intel_init_power_wells(dev);
7806
7807         intel_prepare_ddi(dev);
7808
7809         intel_init_clock_gating(dev);
7810
7811         mutex_lock(&dev->struct_mutex);
7812         intel_enable_gt_powersave(dev);
7813         mutex_unlock(&dev->struct_mutex);
7814 }
7815
7816 void intel_modeset_init(struct drm_device *dev)
7817 {
7818         struct drm_i915_private *dev_priv = dev->dev_private;
7819         int i, ret;
7820
7821         drm_mode_config_init(dev);
7822
7823         dev->mode_config.min_width = 0;
7824         dev->mode_config.min_height = 0;
7825
7826         dev->mode_config.preferred_depth = 24;
7827         dev->mode_config.prefer_shadow = 1;
7828
7829         dev->mode_config.funcs = &intel_mode_funcs;
7830
7831         intel_init_quirks(dev);
7832
7833         intel_init_pm(dev);
7834
7835         intel_init_display(dev);
7836
7837         if (IS_GEN2(dev)) {
7838                 dev->mode_config.max_width = 2048;
7839                 dev->mode_config.max_height = 2048;
7840         } else if (IS_GEN3(dev)) {
7841                 dev->mode_config.max_width = 4096;
7842                 dev->mode_config.max_height = 4096;
7843         } else {
7844                 dev->mode_config.max_width = 8192;
7845                 dev->mode_config.max_height = 8192;
7846         }
7847         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7848
7849         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7850                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7851
7852         for (i = 0; i < dev_priv->num_pipe; i++) {
7853                 intel_crtc_init(dev, i);
7854                 ret = intel_plane_init(dev, i);
7855                 if (ret)
7856                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7857         }
7858
7859         intel_pch_pll_init(dev);
7860
7861         /* Just disable it once at startup */
7862         i915_disable_vga(dev);
7863         intel_setup_outputs(dev);
7864 }
7865
7866 static void
7867 intel_connector_break_all_links(struct intel_connector *connector)
7868 {
7869         connector->base.dpms = DRM_MODE_DPMS_OFF;
7870         connector->base.encoder = NULL;
7871         connector->encoder->connectors_active = false;
7872         connector->encoder->base.crtc = NULL;
7873 }
7874
7875 static void intel_enable_pipe_a(struct drm_device *dev)
7876 {
7877         struct intel_connector *connector;
7878         struct drm_connector *crt = NULL;
7879         struct intel_load_detect_pipe load_detect_temp;
7880
7881         /* We can't just switch on the pipe A, we need to set things up with a
7882          * proper mode and output configuration. As a gross hack, enable pipe A
7883          * by enabling the load detect pipe once. */
7884         list_for_each_entry(connector,
7885                             &dev->mode_config.connector_list,
7886                             base.head) {
7887                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
7888                         crt = &connector->base;
7889                         break;
7890                 }
7891         }
7892
7893         if (!crt)
7894                 return;
7895
7896         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
7897                 intel_release_load_detect_pipe(crt, &load_detect_temp);
7898
7899
7900 }
7901
7902 static void intel_sanitize_crtc(struct intel_crtc *crtc)
7903 {
7904         struct drm_device *dev = crtc->base.dev;
7905         struct drm_i915_private *dev_priv = dev->dev_private;
7906         u32 reg, val;
7907
7908         /* Clear any frame start delays used for debugging left by the BIOS */
7909         reg = PIPECONF(crtc->pipe);
7910         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7911
7912         /* We need to sanitize the plane -> pipe mapping first because this will
7913          * disable the crtc (and hence change the state) if it is wrong. */
7914         if (!HAS_PCH_SPLIT(dev)) {
7915                 struct intel_connector *connector;
7916                 bool plane;
7917
7918                 reg = DSPCNTR(crtc->plane);
7919                 val = I915_READ(reg);
7920
7921                 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7922                     (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7923                         goto ok;
7924
7925                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7926                               crtc->base.base.id);
7927
7928                 /* Pipe has the wrong plane attached and the plane is active.
7929                  * Temporarily change the plane mapping and disable everything
7930                  * ...  */
7931                 plane = crtc->plane;
7932                 crtc->plane = !plane;
7933                 dev_priv->display.crtc_disable(&crtc->base);
7934                 crtc->plane = plane;
7935
7936                 /* ... and break all links. */
7937                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7938                                     base.head) {
7939                         if (connector->encoder->base.crtc != &crtc->base)
7940                                 continue;
7941
7942                         intel_connector_break_all_links(connector);
7943                 }
7944
7945                 WARN_ON(crtc->active);
7946                 crtc->base.enabled = false;
7947         }
7948 ok:
7949
7950         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
7951             crtc->pipe == PIPE_A && !crtc->active) {
7952                 /* BIOS forgot to enable pipe A, this mostly happens after
7953                  * resume. Force-enable the pipe to fix this, the update_dpms
7954                  * call below we restore the pipe to the right state, but leave
7955                  * the required bits on. */
7956                 intel_enable_pipe_a(dev);
7957         }
7958
7959         /* Adjust the state of the output pipe according to whether we
7960          * have active connectors/encoders. */
7961         intel_crtc_update_dpms(&crtc->base);
7962
7963         if (crtc->active != crtc->base.enabled) {
7964                 struct intel_encoder *encoder;
7965
7966                 /* This can happen either due to bugs in the get_hw_state
7967                  * functions or because the pipe is force-enabled due to the
7968                  * pipe A quirk. */
7969                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7970                               crtc->base.base.id,
7971                               crtc->base.enabled ? "enabled" : "disabled",
7972                               crtc->active ? "enabled" : "disabled");
7973
7974                 crtc->base.enabled = crtc->active;
7975
7976                 /* Because we only establish the connector -> encoder ->
7977                  * crtc links if something is active, this means the
7978                  * crtc is now deactivated. Break the links. connector
7979                  * -> encoder links are only establish when things are
7980                  *  actually up, hence no need to break them. */
7981                 WARN_ON(crtc->active);
7982
7983                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7984                         WARN_ON(encoder->connectors_active);
7985                         encoder->base.crtc = NULL;
7986                 }
7987         }
7988 }
7989
7990 static void intel_sanitize_encoder(struct intel_encoder *encoder)
7991 {
7992         struct intel_connector *connector;
7993         struct drm_device *dev = encoder->base.dev;
7994
7995         /* We need to check both for a crtc link (meaning that the
7996          * encoder is active and trying to read from a pipe) and the
7997          * pipe itself being active. */
7998         bool has_active_crtc = encoder->base.crtc &&
7999                 to_intel_crtc(encoder->base.crtc)->active;
8000
8001         if (encoder->connectors_active && !has_active_crtc) {
8002                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8003                               encoder->base.base.id,
8004                               drm_get_encoder_name(&encoder->base));
8005
8006                 /* Connector is active, but has no active pipe. This is
8007                  * fallout from our resume register restoring. Disable
8008                  * the encoder manually again. */
8009                 if (encoder->base.crtc) {
8010                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8011                                       encoder->base.base.id,
8012                                       drm_get_encoder_name(&encoder->base));
8013                         encoder->disable(encoder);
8014                 }
8015
8016                 /* Inconsistent output/port/pipe state happens presumably due to
8017                  * a bug in one of the get_hw_state functions. Or someplace else
8018                  * in our code, like the register restore mess on resume. Clamp
8019                  * things to off as a safer default. */
8020                 list_for_each_entry(connector,
8021                                     &dev->mode_config.connector_list,
8022                                     base.head) {
8023                         if (connector->encoder != encoder)
8024                                 continue;
8025
8026                         intel_connector_break_all_links(connector);
8027                 }
8028         }
8029         /* Enabled encoders without active connectors will be fixed in
8030          * the crtc fixup. */
8031 }
8032
8033 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8034  * and i915 state tracking structures. */
8035 void intel_modeset_setup_hw_state(struct drm_device *dev)
8036 {
8037         struct drm_i915_private *dev_priv = dev->dev_private;
8038         enum pipe pipe;
8039         u32 tmp;
8040         struct intel_crtc *crtc;
8041         struct intel_encoder *encoder;
8042         struct intel_connector *connector;
8043
8044         for_each_pipe(pipe) {
8045                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8046
8047                 tmp = I915_READ(PIPECONF(pipe));
8048                 if (tmp & PIPECONF_ENABLE)
8049                         crtc->active = true;
8050                 else
8051                         crtc->active = false;
8052
8053                 crtc->base.enabled = crtc->active;
8054
8055                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8056                               crtc->base.base.id,
8057                               crtc->active ? "enabled" : "disabled");
8058         }
8059
8060         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8061                             base.head) {
8062                 pipe = 0;
8063
8064                 if (encoder->get_hw_state(encoder, &pipe)) {
8065                         encoder->base.crtc =
8066                                 dev_priv->pipe_to_crtc_mapping[pipe];
8067                 } else {
8068                         encoder->base.crtc = NULL;
8069                 }
8070
8071                 encoder->connectors_active = false;
8072                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8073                               encoder->base.base.id,
8074                               drm_get_encoder_name(&encoder->base),
8075                               encoder->base.crtc ? "enabled" : "disabled",
8076                               pipe);
8077         }
8078
8079         list_for_each_entry(connector, &dev->mode_config.connector_list,
8080                             base.head) {
8081                 if (connector->get_hw_state(connector)) {
8082                         connector->base.dpms = DRM_MODE_DPMS_ON;
8083                         connector->encoder->connectors_active = true;
8084                         connector->base.encoder = &connector->encoder->base;
8085                 } else {
8086                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8087                         connector->base.encoder = NULL;
8088                 }
8089                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8090                               connector->base.base.id,
8091                               drm_get_connector_name(&connector->base),
8092                               connector->base.encoder ? "enabled" : "disabled");
8093         }
8094
8095         /* HW state is read out, now we need to sanitize this mess. */
8096         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8097                             base.head) {
8098                 intel_sanitize_encoder(encoder);
8099         }
8100
8101         for_each_pipe(pipe) {
8102                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8103                 intel_sanitize_crtc(crtc);
8104         }
8105
8106         intel_modeset_update_staged_output_state(dev);
8107 }
8108
8109 void intel_modeset_gem_init(struct drm_device *dev)
8110 {
8111         intel_modeset_init_hw(dev);
8112
8113         intel_setup_overlay(dev);
8114
8115         intel_modeset_setup_hw_state(dev);
8116 }
8117
8118 void intel_modeset_cleanup(struct drm_device *dev)
8119 {
8120         struct drm_i915_private *dev_priv = dev->dev_private;
8121         struct drm_crtc *crtc;
8122         struct intel_crtc *intel_crtc;
8123
8124         drm_kms_helper_poll_fini(dev);
8125         mutex_lock(&dev->struct_mutex);
8126
8127         intel_unregister_dsm_handler();
8128
8129
8130         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8131                 /* Skip inactive CRTCs */
8132                 if (!crtc->fb)
8133                         continue;
8134
8135                 intel_crtc = to_intel_crtc(crtc);
8136                 intel_increase_pllclock(crtc);
8137         }
8138
8139         intel_disable_fbc(dev);
8140
8141         intel_disable_gt_powersave(dev);
8142
8143         ironlake_teardown_rc6(dev);
8144
8145         if (IS_VALLEYVIEW(dev))
8146                 vlv_init_dpio(dev);
8147
8148         mutex_unlock(&dev->struct_mutex);
8149
8150         /* Disable the irq before mode object teardown, for the irq might
8151          * enqueue unpin/hotplug work. */
8152         drm_irq_uninstall(dev);
8153         cancel_work_sync(&dev_priv->hotplug_work);
8154         cancel_work_sync(&dev_priv->rps.work);
8155
8156         /* flush any delayed tasks or pending work */
8157         flush_scheduled_work();
8158
8159         drm_mode_config_cleanup(dev);
8160 }
8161
8162 /*
8163  * Return which encoder is currently attached for connector.
8164  */
8165 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8166 {
8167         return &intel_attached_encoder(connector)->base;
8168 }
8169
8170 void intel_connector_attach_encoder(struct intel_connector *connector,
8171                                     struct intel_encoder *encoder)
8172 {
8173         connector->encoder = encoder;
8174         drm_mode_connector_attach_encoder(&connector->base,
8175                                           &encoder->base);
8176 }
8177
8178 /*
8179  * set vga decode state - true == enable VGA decode
8180  */
8181 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8182 {
8183         struct drm_i915_private *dev_priv = dev->dev_private;
8184         u16 gmch_ctrl;
8185
8186         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8187         if (state)
8188                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8189         else
8190                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8191         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8192         return 0;
8193 }
8194
8195 #ifdef CONFIG_DEBUG_FS
8196 #include <linux/seq_file.h>
8197
8198 struct intel_display_error_state {
8199         struct intel_cursor_error_state {
8200                 u32 control;
8201                 u32 position;
8202                 u32 base;
8203                 u32 size;
8204         } cursor[I915_MAX_PIPES];
8205
8206         struct intel_pipe_error_state {
8207                 u32 conf;
8208                 u32 source;
8209
8210                 u32 htotal;
8211                 u32 hblank;
8212                 u32 hsync;
8213                 u32 vtotal;
8214                 u32 vblank;
8215                 u32 vsync;
8216         } pipe[I915_MAX_PIPES];
8217
8218         struct intel_plane_error_state {
8219                 u32 control;
8220                 u32 stride;
8221                 u32 size;
8222                 u32 pos;
8223                 u32 addr;
8224                 u32 surface;
8225                 u32 tile_offset;
8226         } plane[I915_MAX_PIPES];
8227 };
8228
8229 struct intel_display_error_state *
8230 intel_display_capture_error_state(struct drm_device *dev)
8231 {
8232         drm_i915_private_t *dev_priv = dev->dev_private;
8233         struct intel_display_error_state *error;
8234         int i;
8235
8236         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8237         if (error == NULL)
8238                 return NULL;
8239
8240         for_each_pipe(i) {
8241                 error->cursor[i].control = I915_READ(CURCNTR(i));
8242                 error->cursor[i].position = I915_READ(CURPOS(i));
8243                 error->cursor[i].base = I915_READ(CURBASE(i));
8244
8245                 error->plane[i].control = I915_READ(DSPCNTR(i));
8246                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8247                 error->plane[i].size = I915_READ(DSPSIZE(i));
8248                 error->plane[i].pos = I915_READ(DSPPOS(i));
8249                 error->plane[i].addr = I915_READ(DSPADDR(i));
8250                 if (INTEL_INFO(dev)->gen >= 4) {
8251                         error->plane[i].surface = I915_READ(DSPSURF(i));
8252                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8253                 }
8254
8255                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8256                 error->pipe[i].source = I915_READ(PIPESRC(i));
8257                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8258                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8259                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8260                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8261                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8262                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8263         }
8264
8265         return error;
8266 }
8267
8268 void
8269 intel_display_print_error_state(struct seq_file *m,
8270                                 struct drm_device *dev,
8271                                 struct intel_display_error_state *error)
8272 {
8273         drm_i915_private_t *dev_priv = dev->dev_private;
8274         int i;
8275
8276         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8277         for_each_pipe(i) {
8278                 seq_printf(m, "Pipe [%d]:\n", i);
8279                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8280                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8281                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8282                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8283                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8284                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8285                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8286                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8287
8288                 seq_printf(m, "Plane [%d]:\n", i);
8289                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8290                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8291                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8292                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8293                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8294                 if (INTEL_INFO(dev)->gen >= 4) {
8295                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8296                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8297                 }
8298
8299                 seq_printf(m, "Cursor [%d]:\n", i);
8300                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8301                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8302                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8303         }
8304 }
8305 #endif