drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static const intel_limit_t intel_limits_i8xx_dvo = {
 346         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 347         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 348         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 349         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 350         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 351         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 352         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 353         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 354         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 355                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 356         .find_pll = intel_find_best_PLL,
 357 };
 358
 359 static const intel_limit_t intel_limits_i8xx_lvds = {
 360         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 361         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 362         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 363         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 364         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 365         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 366         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 367         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 368         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 369                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 370         .find_pll = intel_find_best_PLL,
 371 };
 372
 373 static const intel_limit_t intel_limits_i9xx_sdvo = {
 374         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 375         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 376         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 377         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 378         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 379         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 380         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 381         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 382         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 384         .find_pll = intel_find_best_PLL,
 385 };
 386
 387 static const intel_limit_t intel_limits_i9xx_lvds = {
 388         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 389         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 390         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 391         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 392         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 393         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 394         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 395         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 396         /* The single-channel range is 25-112Mhz, and dual-channel
 397          * is 80-224Mhz.  Prefer single channel as much as possible.
 398          */
 399         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 400                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 401         .find_pll = intel_find_best_PLL,
 402 };
 403
 404     /* below parameter and function is for G4X Chipset Family*/
 405 static const intel_limit_t intel_limits_g4x_sdvo = {
 406         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 407         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 408         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 409         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 410         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 411         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 412         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 413         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 414         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 415                  .p2_slow = G4X_P2_SDVO_SLOW,
 416                  .p2_fast = G4X_P2_SDVO_FAST
 417         },
 418         .find_pll = intel_g4x_find_best_PLL,
 419 };
 420
 421 static const intel_limit_t intel_limits_g4x_hdmi = {
 422         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 423         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 424         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 425         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 426         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 427         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 428         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 429         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 430         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 431                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 432                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 433         },
 434         .find_pll = intel_g4x_find_best_PLL,
 435 };
 436
 437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 438         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 440         .vco = { .min = G4X_VCO_MIN,
 441                  .max = G4X_VCO_MAX },
 442         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 444         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 446         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 448         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 450         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 452         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 454         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 455                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 456                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 457         },
 458         .find_pll = intel_g4x_find_best_PLL,
 459 };
 460
 461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 462         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 464         .vco = { .min = G4X_VCO_MIN,
 465                  .max = G4X_VCO_MAX },
 466         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 468         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 470         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 472         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 474         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 476         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 478         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 479                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 480                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 481         },
 482         .find_pll = intel_g4x_find_best_PLL,
 483 };
 484
 485 static const intel_limit_t intel_limits_g4x_display_port = {
 486         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 487                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 488         .vco = { .min = G4X_VCO_MIN,
 489                  .max = G4X_VCO_MAX},
 490         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 491                  .max = G4X_N_DISPLAY_PORT_MAX },
 492         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 493                  .max = G4X_M_DISPLAY_PORT_MAX },
 494         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 495                  .max = G4X_M1_DISPLAY_PORT_MAX },
 496         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 497                  .max = G4X_M2_DISPLAY_PORT_MAX },
 498         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 499                  .max = G4X_P_DISPLAY_PORT_MAX },
 500         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 501                  .max = G4X_P1_DISPLAY_PORT_MAX},
 502         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 503                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 504                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 505         .find_pll = intel_find_pll_g4x_dp,
 506 };
 507
 508 static const intel_limit_t intel_limits_pineview_sdvo = {
 509         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 510         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 511         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 512         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 513         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 514         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 515         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 516         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 517         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 518                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 519         .find_pll = intel_find_best_PLL,
 520 };
 521
 522 static const intel_limit_t intel_limits_pineview_lvds = {
 523         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 524         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 525         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 526         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 527         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 528         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 529         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 530         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 531         /* Pineview only supports single-channel mode. */
 532         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 533                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 534         .find_pll = intel_find_best_PLL,
 535 };
 536
 537 static const intel_limit_t intel_limits_ironlake_dac = {
 538         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 539         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 540         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 541         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 542         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 543         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 544         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 545         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 546         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 547                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 548                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 549         .find_pll = intel_g4x_find_best_PLL,
 550 };
 551
 552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 553         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 554         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 555         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 556         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 557         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 558         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 559         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 560         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 561         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 562                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 563                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 564         .find_pll = intel_g4x_find_best_PLL,
 565 };
 566
 567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 568         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 569         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 570         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 571         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 572         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 573         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 574         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 575         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 576         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 577                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 578                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 579         .find_pll = intel_g4x_find_best_PLL,
 580 };
 581
 582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 583         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 584         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 585         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 586         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 587         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 588         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 589         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 590         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 591         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 592                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 593                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 594         .find_pll = intel_g4x_find_best_PLL,
 595 };
 596
 597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 598         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 599         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 600         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 601         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 602         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 603         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 604         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 605         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 606         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 607                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 608                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 609         .find_pll = intel_g4x_find_best_PLL,
 610 };
 611
 612 static const intel_limit_t intel_limits_ironlake_display_port = {
 613         .dot = { .min = IRONLAKE_DOT_MIN,
 614                  .max = IRONLAKE_DOT_MAX },
 615         .vco = { .min = IRONLAKE_VCO_MIN,
 616                  .max = IRONLAKE_VCO_MAX},
 617         .n   = { .min = IRONLAKE_DP_N_MIN,
 618                  .max = IRONLAKE_DP_N_MAX },
 619         .m   = { .min = IRONLAKE_DP_M_MIN,
 620                  .max = IRONLAKE_DP_M_MAX },
 621         .m1  = { .min = IRONLAKE_M1_MIN,
 622                  .max = IRONLAKE_M1_MAX },
 623         .m2  = { .min = IRONLAKE_M2_MIN,
 624                  .max = IRONLAKE_M2_MAX },
 625         .p   = { .min = IRONLAKE_DP_P_MIN,
 626                  .max = IRONLAKE_DP_P_MAX },
 627         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 628                  .max = IRONLAKE_DP_P1_MAX},
 629         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 630                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 631                  .p2_fast = IRONLAKE_DP_P2_FAST },
 632         .find_pll = intel_find_pll_ironlake_dp,
 633 };
 634
 635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         const intel_limit_t *limit;
 640         int refclk = 120;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 644                         refclk = 100;
 645
 646                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 647                     LVDS_CLKB_POWER_UP) {
 648                         /* LVDS dual channel */
 649                         if (refclk == 100)
 650                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 651                         else
 652                                 limit = &intel_limits_ironlake_dual_lvds;
 653                 } else {
 654                         if (refclk == 100)
 655                                 limit = &intel_limits_ironlake_single_lvds_100m;
 656                         else
 657                                 limit = &intel_limits_ironlake_single_lvds;
 658                 }
 659         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 660                         HAS_eDP)
 661                 limit = &intel_limits_ironlake_display_port;
 662         else
 663                 limit = &intel_limits_ironlake_dac;
 664
 665         return limit;
 666 }
 667
 668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         const intel_limit_t *limit;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 676                     LVDS_CLKB_POWER_UP)
 677                         /* LVDS with dual channel */
 678                         limit = &intel_limits_g4x_dual_channel_lvds;
 679                 else
 680                         /* LVDS with dual channel */
 681                         limit = &intel_limits_g4x_single_channel_lvds;
 682         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 683                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 684                 limit = &intel_limits_g4x_hdmi;
 685         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 686                 limit = &intel_limits_g4x_sdvo;
 687         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 688                 limit = &intel_limits_g4x_display_port;
 689         } else /* The option is for other outputs */
 690                 limit = &intel_limits_i9xx_sdvo;
 691
 692         return limit;
 693 }
 694
 695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 696 {
 697         struct drm_device *dev = crtc->dev;
 698         const intel_limit_t *limit;
 699
 700         if (HAS_PCH_SPLIT(dev))
 701                 limit = intel_ironlake_limit(crtc);
 702         else if (IS_G4X(dev)) {
 703                 limit = intel_g4x_limit(crtc);
 704         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 705                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 706                         limit = &intel_limits_i9xx_lvds;
 707                 else
 708                         limit = &intel_limits_i9xx_sdvo;
 709         } else if (IS_PINEVIEW(dev)) {
 710                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 711                         limit = &intel_limits_pineview_lvds;
 712                 else
 713                         limit = &intel_limits_pineview_sdvo;
 714         } else {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_i8xx_lvds;
 717                 else
 718                         limit = &intel_limits_i8xx_dvo;
 719         }
 720         return limit;
 721 }
 722
 723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 724 static void pineview_clock(int refclk, intel_clock_t *clock)
 725 {
 726         clock->m = clock->m2 + 2;
 727         clock->p = clock->p1 * clock->p2;
 728         clock->vco = refclk * clock->m / clock->n;
 729         clock->dot = clock->vco / clock->p;
 730 }
 731
 732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 733 {
 734         if (IS_PINEVIEW(dev)) {
 735                 pineview_clock(refclk, clock);
 736                 return;
 737         }
 738         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 739         clock->p = clock->p1 * clock->p2;
 740         clock->vco = refclk * clock->m / (clock->n + 2);
 741         clock->dot = clock->vco / clock->p;
 742 }
 743
 744 /**
 745  * Returns whether any output on the specified pipe is of the specified type
 746  */
 747 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 748 {
 749         struct drm_device *dev = crtc->dev;
 750         struct drm_mode_config *mode_config = &dev->mode_config;
 751         struct intel_encoder *encoder;
 752
 753         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 754                 if (encoder->base.crtc == crtc && encoder->type == type)
 755                         return true;
 756
 757         return false;
 758 }
 759
 760 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 761 /**
 762  * Returns whether the given set of divisors are valid for a given refclk with
 763  * the given connectors.
 764  */
 765
 766 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 767 {
 768         const intel_limit_t *limit = intel_limit (crtc);
 769         struct drm_device *dev = crtc->dev;
 770
 771         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 772                 INTELPllInvalid ("p1 out of range\n");
 773         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 774                 INTELPllInvalid ("p out of range\n");
 775         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 776                 INTELPllInvalid ("m2 out of range\n");
 777         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 778                 INTELPllInvalid ("m1 out of range\n");
 779         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 780                 INTELPllInvalid ("m1 <= m2\n");
 781         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 782                 INTELPllInvalid ("m out of range\n");
 783         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 784                 INTELPllInvalid ("n out of range\n");
 785         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 786                 INTELPllInvalid ("vco out of range\n");
 787         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 788          * connector, etc., rather than just a single range.
 789          */
 790         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 791                 INTELPllInvalid ("dot out of range\n");
 792
 793         return true;
 794 }
 795
 796 static bool
 797 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 798                     int target, int refclk, intel_clock_t *best_clock)
 799
 800 {
 801         struct drm_device *dev = crtc->dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         intel_clock_t clock;
 804         int err = target;
 805
 806         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 807             (I915_READ(LVDS)) != 0) {
 808                 /*
 809                  * For LVDS, if the panel is on, just rely on its current
 810                  * settings for dual-channel.  We haven't figured out how to
 811                  * reliably set up different single/dual channel state, if we
 812                  * even can.
 813                  */
 814                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 815                     LVDS_CLKB_POWER_UP)
 816                         clock.p2 = limit->p2.p2_fast;
 817                 else
 818                         clock.p2 = limit->p2.p2_slow;
 819         } else {
 820                 if (target < limit->p2.dot_limit)
 821                         clock.p2 = limit->p2.p2_slow;
 822                 else
 823                         clock.p2 = limit->p2.p2_fast;
 824         }
 825
 826         memset (best_clock, 0, sizeof (*best_clock));
 827
 828         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 829              clock.m1++) {
 830                 for (clock.m2 = limit->m2.min;
 831                      clock.m2 <= limit->m2.max; clock.m2++) {
 832                         /* m1 is always 0 in Pineview */
 833                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 834                                 break;
 835                         for (clock.n = limit->n.min;
 836                              clock.n <= limit->n.max; clock.n++) {
 837                                 for (clock.p1 = limit->p1.min;
 838                                         clock.p1 <= limit->p1.max; clock.p1++) {
 839                                         int this_err;
 840
 841                                         intel_clock(dev, refclk, &clock);
 842
 843                                         if (!intel_PLL_is_valid(crtc, &clock))
 844                                                 continue;
 845
 846                                         this_err = abs(clock.dot - target);
 847                                         if (this_err < err) {
 848                                                 *best_clock = clock;
 849                                                 err = this_err;
 850                                         }
 851                                 }
 852                         }
 853                 }
 854         }
 855
 856         return (err != target);
 857 }
 858
 859 static bool
 860 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870         found = false;
 871
 872         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 873                 int lvds_reg;
 874
 875                 if (HAS_PCH_SPLIT(dev))
 876                         lvds_reg = PCH_LVDS;
 877                 else
 878                         lvds_reg = LVDS;
 879                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 880                     LVDS_CLKB_POWER_UP)
 881                         clock.p2 = limit->p2.p2_fast;
 882                 else
 883                         clock.p2 = limit->p2.p2_slow;
 884         } else {
 885                 if (target < limit->p2.dot_limit)
 886                         clock.p2 = limit->p2.p2_slow;
 887                 else
 888                         clock.p2 = limit->p2.p2_fast;
 889         }
 890
 891         memset(best_clock, 0, sizeof(*best_clock));
 892         max_n = limit->n.max;
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 895                 /* based on hardware requirement, prefere larger m1,m2 */
 896                 for (clock.m1 = limit->m1.max;
 897                      clock.m1 >= limit->m1.min; clock.m1--) {
 898                         for (clock.m2 = limit->m2.max;
 899                              clock.m2 >= limit->m2.min; clock.m2--) {
 900                                 for (clock.p1 = limit->p1.max;
 901                                      clock.p1 >= limit->p1.min; clock.p1--) {
 902                                         int this_err;
 903
 904                                         intel_clock(dev, refclk, &clock);
 905                                         if (!intel_PLL_is_valid(crtc, &clock))
 906                                                 continue;
 907                                         this_err = abs(clock.dot - target) ;
 908                                         if (this_err < err_most) {
 909                                                 *best_clock = clock;
 910                                                 err_most = this_err;
 911                                                 max_n = clock.n;
 912                                                 found = true;
 913                                         }
 914                                 }
 915                         }
 916                 }
 917         }
 918         return found;
 919 }
 920
 921 static bool
 922 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 923                            int target, int refclk, intel_clock_t *best_clock)
 924 {
 925         struct drm_device *dev = crtc->dev;
 926         intel_clock_t clock;
 927
 928         /* return directly when it is eDP */
 929         if (HAS_eDP)
 930                 return true;
 931
 932         if (target < 200000) {
 933                 clock.n = 1;
 934                 clock.p1 = 2;
 935                 clock.p2 = 10;
 936                 clock.m1 = 12;
 937                 clock.m2 = 9;
 938         } else {
 939                 clock.n = 2;
 940                 clock.p1 = 1;
 941                 clock.p2 = 10;
 942                 clock.m1 = 14;
 943                 clock.m2 = 8;
 944         }
 945         intel_clock(dev, refclk, &clock);
 946         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 947         return true;
 948 }
 949
 950 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 951 static bool
 952 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 953                       int target, int refclk, intel_clock_t *best_clock)
 954 {
 955     intel_clock_t clock;
 956     if (target < 200000) {
 957         clock.p1 = 2;
 958         clock.p2 = 10;
 959         clock.n = 2;
 960         clock.m1 = 23;
 961         clock.m2 = 8;
 962     } else {
 963         clock.p1 = 1;
 964         clock.p2 = 10;
 965         clock.n = 1;
 966         clock.m1 = 14;
 967         clock.m2 = 2;
 968     }
 969     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 970     clock.p = (clock.p1 * clock.p2);
 971     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 972     clock.vco = 0;
 973     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 974     return true;
 975 }
 976
 977 /**
 978  * intel_wait_for_vblank - wait for vblank on a given pipe
 979  * @dev: drm device
 980  * @pipe: pipe to wait for
 981  *
 982  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 983  * mode setting code.
 984  */
 985 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 986 {
 987         struct drm_i915_private *dev_priv = dev->dev_private;
 988         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 989
 990         /* Clear existing vblank status. Note this will clear any other
 991          * sticky status fields as well.
 992          *
 993          * This races with i915_driver_irq_handler() with the result
 994          * that either function could miss a vblank event.  Here it is not
 995          * fatal, as we will either wait upon the next vblank interrupt or
 996          * timeout.  Generally speaking intel_wait_for_vblank() is only
 997          * called during modeset at which time the GPU should be idle and
 998          * should *not* be performing page flips and thus not waiting on
 999          * vblanks...
1000          * Currently, the result of us stealing a vblank from the irq
1001          * handler is that a single frame will be skipped during swapbuffers.
1002          */
1003         I915_WRITE(pipestat_reg,
1004                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1005
1006         /* Wait for vblank interrupt bit to set */
1007         if (wait_for(I915_READ(pipestat_reg) &
1008                      PIPE_VBLANK_INTERRUPT_STATUS,
1009                      50))
1010                 DRM_DEBUG_KMS("vblank wait timed out\n");
1011 }
1012
1013 /**
1014  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1015  * @dev: drm device
1016  * @pipe: pipe to wait for
1017  *
1018  * After disabling a pipe, we can't wait for vblank in the usual way,
1019  * spinning on the vblank interrupt status bit, since we won't actually
1020  * see an interrupt when the pipe is disabled.
1021  *
1022  * So this function waits for the display line value to settle (it
1023  * usually ends up stopping at the start of the next frame).
1024  */
1025 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1026 {
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1029         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1030         u32 last_line;
1031
1032         /* Wait for the display line to settle */
1033         do {
1034                 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1035                 mdelay(5);
1036         } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1037                  time_after(timeout, jiffies));
1038
1039         if (time_after(jiffies, timeout))
1040                 DRM_DEBUG_KMS("vblank wait timed out\n");
1041 }
1042
1043 /* Parameters have changed, update FBC info */
1044 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1045 {
1046         struct drm_device *dev = crtc->dev;
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048         struct drm_framebuffer *fb = crtc->fb;
1049         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1050         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1052         int plane, i;
1053         u32 fbc_ctl, fbc_ctl2;
1054
1055         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1056
1057         if (fb->pitch < dev_priv->cfb_pitch)
1058                 dev_priv->cfb_pitch = fb->pitch;
1059
1060         /* FBC_CTL wants 64B units */
1061         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1062         dev_priv->cfb_fence = obj_priv->fence_reg;
1063         dev_priv->cfb_plane = intel_crtc->plane;
1064         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1065
1066         /* Clear old tags */
1067         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1068                 I915_WRITE(FBC_TAG + (i * 4), 0);
1069
1070         /* Set it up... */
1071         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1072         if (obj_priv->tiling_mode != I915_TILING_NONE)
1073                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1074         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1075         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1076
1077         /* enable it... */
1078         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1079         if (IS_I945GM(dev))
1080                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1081         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1082         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1083         if (obj_priv->tiling_mode != I915_TILING_NONE)
1084                 fbc_ctl |= dev_priv->cfb_fence;
1085         I915_WRITE(FBC_CONTROL, fbc_ctl);
1086
1087         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1088                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1089 }
1090
1091 void i8xx_disable_fbc(struct drm_device *dev)
1092 {
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         u32 fbc_ctl;
1095
1096         if (!I915_HAS_FBC(dev))
1097                 return;
1098
1099         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1100                 return; /* Already off, just return */
1101
1102         /* Disable compression */
1103         fbc_ctl = I915_READ(FBC_CONTROL);
1104         fbc_ctl &= ~FBC_CTL_EN;
1105         I915_WRITE(FBC_CONTROL, fbc_ctl);
1106
1107         /* Wait for compressing bit to clear */
1108         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1109                 DRM_DEBUG_KMS("FBC idle timed out\n");
1110                 return;
1111         }
1112
1113         DRM_DEBUG_KMS("disabled FBC\n");
1114 }
1115
1116 static bool i8xx_fbc_enabled(struct drm_device *dev)
1117 {
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1121 }
1122
1123 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1124 {
1125         struct drm_device *dev = crtc->dev;
1126         struct drm_i915_private *dev_priv = dev->dev_private;
1127         struct drm_framebuffer *fb = crtc->fb;
1128         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1129         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1131         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1132                      DPFC_CTL_PLANEB);
1133         unsigned long stall_watermark = 200;
1134         u32 dpfc_ctl;
1135
1136         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1137         dev_priv->cfb_fence = obj_priv->fence_reg;
1138         dev_priv->cfb_plane = intel_crtc->plane;
1139
1140         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1141         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1142                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1143                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1144         } else {
1145                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1146         }
1147
1148         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1149         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1150                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1151                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1152         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1153
1154         /* enable it... */
1155         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1156
1157         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1158 }
1159
1160 void g4x_disable_fbc(struct drm_device *dev)
1161 {
1162         struct drm_i915_private *dev_priv = dev->dev_private;
1163         u32 dpfc_ctl;
1164
1165         /* Disable compression */
1166         dpfc_ctl = I915_READ(DPFC_CONTROL);
1167         dpfc_ctl &= ~DPFC_CTL_EN;
1168         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1169
1170         DRM_DEBUG_KMS("disabled FBC\n");
1171 }
1172
1173 static bool g4x_fbc_enabled(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176
1177         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1178 }
1179
1180 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1181 {
1182         struct drm_device *dev = crtc->dev;
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         struct drm_framebuffer *fb = crtc->fb;
1185         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1186         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1189                                                DPFC_CTL_PLANEB;
1190         unsigned long stall_watermark = 200;
1191         u32 dpfc_ctl;
1192
1193         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1194         dev_priv->cfb_fence = obj_priv->fence_reg;
1195         dev_priv->cfb_plane = intel_crtc->plane;
1196
1197         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1198         dpfc_ctl &= DPFC_RESERVED;
1199         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1200         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1201                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1202                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1203         } else {
1204                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1205         }
1206
1207         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1208         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1209                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1210                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1211         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1212         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1213         /* enable it... */
1214         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1215                    DPFC_CTL_EN);
1216
1217         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1218 }
1219
1220 void ironlake_disable_fbc(struct drm_device *dev)
1221 {
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         u32 dpfc_ctl;
1224
1225         /* Disable compression */
1226         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1227         dpfc_ctl &= ~DPFC_CTL_EN;
1228         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1229
1230         DRM_DEBUG_KMS("disabled FBC\n");
1231 }
1232
1233 static bool ironlake_fbc_enabled(struct drm_device *dev)
1234 {
1235         struct drm_i915_private *dev_priv = dev->dev_private;
1236
1237         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1238 }
1239
1240 bool intel_fbc_enabled(struct drm_device *dev)
1241 {
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243
1244         if (!dev_priv->display.fbc_enabled)
1245                 return false;
1246
1247         return dev_priv->display.fbc_enabled(dev);
1248 }
1249
1250 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1251 {
1252         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1253
1254         if (!dev_priv->display.enable_fbc)
1255                 return;
1256
1257         dev_priv->display.enable_fbc(crtc, interval);
1258 }
1259
1260 void intel_disable_fbc(struct drm_device *dev)
1261 {
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263
1264         if (!dev_priv->display.disable_fbc)
1265                 return;
1266
1267         dev_priv->display.disable_fbc(dev);
1268 }
1269
1270 /**
1271  * intel_update_fbc - enable/disable FBC as needed
1272  * @crtc: CRTC to point the compressor at
1273  * @mode: mode in use
1274  *
1275  * Set up the framebuffer compression hardware at mode set time.  We
1276  * enable it if possible:
1277  *   - plane A only (on pre-965)
1278  *   - no pixel mulitply/line duplication
1279  *   - no alpha buffer discard
1280  *   - no dual wide
1281  *   - framebuffer <= 2048 in width, 1536 in height
1282  *
1283  * We can't assume that any compression will take place (worst case),
1284  * so the compressed buffer has to be the same size as the uncompressed
1285  * one.  It also must reside (along with the line length buffer) in
1286  * stolen memory.
1287  *
1288  * We need to enable/disable FBC on a global basis.
1289  */
1290 static void intel_update_fbc(struct drm_crtc *crtc,
1291                              struct drm_display_mode *mode)
1292 {
1293         struct drm_device *dev = crtc->dev;
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295         struct drm_framebuffer *fb = crtc->fb;
1296         struct intel_framebuffer *intel_fb;
1297         struct drm_i915_gem_object *obj_priv;
1298         struct drm_crtc *tmp_crtc;
1299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1300         int plane = intel_crtc->plane;
1301         int crtcs_enabled = 0;
1302
1303         DRM_DEBUG_KMS("\n");
1304
1305         if (!i915_powersave)
1306                 return;
1307
1308         if (!I915_HAS_FBC(dev))
1309                 return;
1310
1311         if (!crtc->fb)
1312                 return;
1313
1314         intel_fb = to_intel_framebuffer(fb);
1315         obj_priv = to_intel_bo(intel_fb->obj);
1316
1317         /*
1318          * If FBC is already on, we just have to verify that we can
1319          * keep it that way...
1320          * Need to disable if:
1321          *   - more than one pipe is active
1322          *   - changing FBC params (stride, fence, mode)
1323          *   - new fb is too large to fit in compressed buffer
1324          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1325          */
1326         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1327                 if (tmp_crtc->enabled)
1328                         crtcs_enabled++;
1329         }
1330         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1331         if (crtcs_enabled > 1) {
1332                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1333                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1334                 goto out_disable;
1335         }
1336         if (intel_fb->obj->size > dev_priv->cfb_size) {
1337                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1338                                 "compression\n");
1339                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1340                 goto out_disable;
1341         }
1342         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1343             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1344                 DRM_DEBUG_KMS("mode incompatible with compression, "
1345                                 "disabling\n");
1346                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1347                 goto out_disable;
1348         }
1349         if ((mode->hdisplay > 2048) ||
1350             (mode->vdisplay > 1536)) {
1351                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1352                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1353                 goto out_disable;
1354         }
1355         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1356                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1357                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1358                 goto out_disable;
1359         }
1360         if (obj_priv->tiling_mode != I915_TILING_X) {
1361                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1362                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1363                 goto out_disable;
1364         }
1365
1366         /* If the kernel debugger is active, always disable compression */
1367         if (in_dbg_master())
1368                 goto out_disable;
1369
1370         if (intel_fbc_enabled(dev)) {
1371                 /* We can re-enable it in this case, but need to update pitch */
1372                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1373                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1374                     (plane != dev_priv->cfb_plane))
1375                         intel_disable_fbc(dev);
1376         }
1377
1378         /* Now try to turn it back on if possible */
1379         if (!intel_fbc_enabled(dev))
1380                 intel_enable_fbc(crtc, 500);
1381
1382         return;
1383
1384 out_disable:
1385         /* Multiple disables should be harmless */
1386         if (intel_fbc_enabled(dev)) {
1387                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1388                 intel_disable_fbc(dev);
1389         }
1390 }
1391
1392 int
1393 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1394 {
1395         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1396         u32 alignment;
1397         int ret;
1398
1399         switch (obj_priv->tiling_mode) {
1400         case I915_TILING_NONE:
1401                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1402                         alignment = 128 * 1024;
1403                 else if (IS_I965G(dev))
1404                         alignment = 4 * 1024;
1405                 else
1406                         alignment = 64 * 1024;
1407                 break;
1408         case I915_TILING_X:
1409                 /* pin() will align the object as required by fence */
1410                 alignment = 0;
1411                 break;
1412         case I915_TILING_Y:
1413                 /* FIXME: Is this true? */
1414                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1415                 return -EINVAL;
1416         default:
1417                 BUG();
1418         }
1419
1420         ret = i915_gem_object_pin(obj, alignment);
1421         if (ret != 0)
1422                 return ret;
1423
1424         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1425          * fence, whereas 965+ only requires a fence if using
1426          * framebuffer compression.  For simplicity, we always install
1427          * a fence as the cost is not that onerous.
1428          */
1429         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1430             obj_priv->tiling_mode != I915_TILING_NONE) {
1431                 ret = i915_gem_object_get_fence_reg(obj);
1432                 if (ret != 0) {
1433                         i915_gem_object_unpin(obj);
1434                         return ret;
1435                 }
1436         }
1437
1438         return 0;
1439 }
1440
1441 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1442 static int
1443 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1444                            int x, int y)
1445 {
1446         struct drm_device *dev = crtc->dev;
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1449         struct intel_framebuffer *intel_fb;
1450         struct drm_i915_gem_object *obj_priv;
1451         struct drm_gem_object *obj;
1452         int plane = intel_crtc->plane;
1453         unsigned long Start, Offset;
1454         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1455         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1456         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1457         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1458         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1459         u32 dspcntr;
1460
1461         switch (plane) {
1462         case 0:
1463         case 1:
1464                 break;
1465         default:
1466                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1467                 return -EINVAL;
1468         }
1469
1470         intel_fb = to_intel_framebuffer(fb);
1471         obj = intel_fb->obj;
1472         obj_priv = to_intel_bo(obj);
1473
1474         dspcntr = I915_READ(dspcntr_reg);
1475         /* Mask out pixel format bits in case we change it */
1476         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1477         switch (fb->bits_per_pixel) {
1478         case 8:
1479                 dspcntr |= DISPPLANE_8BPP;
1480                 break;
1481         case 16:
1482                 if (fb->depth == 15)
1483                         dspcntr |= DISPPLANE_15_16BPP;
1484                 else
1485                         dspcntr |= DISPPLANE_16BPP;
1486                 break;
1487         case 24:
1488         case 32:
1489                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1490                 break;
1491         default:
1492                 DRM_ERROR("Unknown color depth\n");
1493                 return -EINVAL;
1494         }
1495         if (IS_I965G(dev)) {
1496                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1497                         dspcntr |= DISPPLANE_TILED;
1498                 else
1499                         dspcntr &= ~DISPPLANE_TILED;
1500         }
1501
1502         if (HAS_PCH_SPLIT(dev))
1503                 /* must disable */
1504                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1505
1506         I915_WRITE(dspcntr_reg, dspcntr);
1507
1508         Start = obj_priv->gtt_offset;
1509         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1510
1511         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1512                       Start, Offset, x, y, fb->pitch);
1513         I915_WRITE(dspstride, fb->pitch);
1514         if (IS_I965G(dev)) {
1515                 I915_WRITE(dspsurf, Start);
1516                 I915_WRITE(dsptileoff, (y << 16) | x);
1517                 I915_WRITE(dspbase, Offset);
1518         } else {
1519                 I915_WRITE(dspbase, Start + Offset);
1520         }
1521         POSTING_READ(dspbase);
1522
1523         if (IS_I965G(dev) || plane == 0)
1524                 intel_update_fbc(crtc, &crtc->mode);
1525
1526         intel_wait_for_vblank(dev, intel_crtc->pipe);
1527         intel_increase_pllclock(crtc);
1528
1529         return 0;
1530 }
1531
1532 static int
1533 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1534                     struct drm_framebuffer *old_fb)
1535 {
1536         struct drm_device *dev = crtc->dev;
1537         struct drm_i915_master_private *master_priv;
1538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1539         struct intel_framebuffer *intel_fb;
1540         struct drm_i915_gem_object *obj_priv;
1541         struct drm_gem_object *obj;
1542         int pipe = intel_crtc->pipe;
1543         int plane = intel_crtc->plane;
1544         int ret;
1545
1546         /* no fb bound */
1547         if (!crtc->fb) {
1548                 DRM_DEBUG_KMS("No FB bound\n");
1549                 return 0;
1550         }
1551
1552         switch (plane) {
1553         case 0:
1554         case 1:
1555                 break;
1556         default:
1557                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1558                 return -EINVAL;
1559         }
1560
1561         intel_fb = to_intel_framebuffer(crtc->fb);
1562         obj = intel_fb->obj;
1563         obj_priv = to_intel_bo(obj);
1564
1565         mutex_lock(&dev->struct_mutex);
1566         ret = intel_pin_and_fence_fb_obj(dev, obj);
1567         if (ret != 0) {
1568                 mutex_unlock(&dev->struct_mutex);
1569                 return ret;
1570         }
1571
1572         ret = i915_gem_object_set_to_display_plane(obj);
1573         if (ret != 0) {
1574                 i915_gem_object_unpin(obj);
1575                 mutex_unlock(&dev->struct_mutex);
1576                 return ret;
1577         }
1578
1579         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1580         if (ret) {
1581                 i915_gem_object_unpin(obj);
1582                 mutex_unlock(&dev->struct_mutex);
1583                 return ret;
1584         }
1585
1586         if (old_fb) {
1587                 intel_fb = to_intel_framebuffer(old_fb);
1588                 obj_priv = to_intel_bo(intel_fb->obj);
1589                 i915_gem_object_unpin(intel_fb->obj);
1590         }
1591
1592         mutex_unlock(&dev->struct_mutex);
1593
1594         if (!dev->primary->master)
1595                 return 0;
1596
1597         master_priv = dev->primary->master->driver_priv;
1598         if (!master_priv->sarea_priv)
1599                 return 0;
1600
1601         if (pipe) {
1602                 master_priv->sarea_priv->pipeB_x = x;
1603                 master_priv->sarea_priv->pipeB_y = y;
1604         } else {
1605                 master_priv->sarea_priv->pipeA_x = x;
1606                 master_priv->sarea_priv->pipeA_y = y;
1607         }
1608
1609         return 0;
1610 }
1611
1612 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1613 {
1614         struct drm_device *dev = crtc->dev;
1615         struct drm_i915_private *dev_priv = dev->dev_private;
1616         u32 dpa_ctl;
1617
1618         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1619         dpa_ctl = I915_READ(DP_A);
1620         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1621
1622         if (clock < 200000) {
1623                 u32 temp;
1624                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1625                 /* workaround for 160Mhz:
1626                    1) program 0x4600c bits 15:0 = 0x8124
1627                    2) program 0x46010 bit 0 = 1
1628                    3) program 0x46034 bit 24 = 1
1629                    4) program 0x64000 bit 14 = 1
1630                    */
1631                 temp = I915_READ(0x4600c);
1632                 temp &= 0xffff0000;
1633                 I915_WRITE(0x4600c, temp | 0x8124);
1634
1635                 temp = I915_READ(0x46010);
1636                 I915_WRITE(0x46010, temp | 1);
1637
1638                 temp = I915_READ(0x46034);
1639                 I915_WRITE(0x46034, temp | (1 << 24));
1640         } else {
1641                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1642         }
1643         I915_WRITE(DP_A, dpa_ctl);
1644
1645         udelay(500);
1646 }
1647
1648 /* The FDI link training functions for ILK/Ibexpeak. */
1649 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1650 {
1651         struct drm_device *dev = crtc->dev;
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1654         int pipe = intel_crtc->pipe;
1655         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1656         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1657         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1658         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1659         u32 temp, tries = 0;
1660
1661         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1662            for train result */
1663         temp = I915_READ(fdi_rx_imr_reg);
1664         temp &= ~FDI_RX_SYMBOL_LOCK;
1665         temp &= ~FDI_RX_BIT_LOCK;
1666         I915_WRITE(fdi_rx_imr_reg, temp);
1667         I915_READ(fdi_rx_imr_reg);
1668         udelay(150);
1669
1670         /* enable CPU FDI TX and PCH FDI RX */
1671         temp = I915_READ(fdi_tx_reg);
1672         temp |= FDI_TX_ENABLE;
1673         temp &= ~(7 << 19);
1674         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1675         temp &= ~FDI_LINK_TRAIN_NONE;
1676         temp |= FDI_LINK_TRAIN_PATTERN_1;
1677         I915_WRITE(fdi_tx_reg, temp);
1678         I915_READ(fdi_tx_reg);
1679
1680         temp = I915_READ(fdi_rx_reg);
1681         temp &= ~FDI_LINK_TRAIN_NONE;
1682         temp |= FDI_LINK_TRAIN_PATTERN_1;
1683         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1684         I915_READ(fdi_rx_reg);
1685         udelay(150);
1686
1687         for (tries = 0; tries < 5; tries++) {
1688                 temp = I915_READ(fdi_rx_iir_reg);
1689                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1690
1691                 if ((temp & FDI_RX_BIT_LOCK)) {
1692                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1693                         I915_WRITE(fdi_rx_iir_reg,
1694                                    temp | FDI_RX_BIT_LOCK);
1695                         break;
1696                 }
1697         }
1698         if (tries == 5)
1699                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1700
1701         /* Train 2 */
1702         temp = I915_READ(fdi_tx_reg);
1703         temp &= ~FDI_LINK_TRAIN_NONE;
1704         temp |= FDI_LINK_TRAIN_PATTERN_2;
1705         I915_WRITE(fdi_tx_reg, temp);
1706
1707         temp = I915_READ(fdi_rx_reg);
1708         temp &= ~FDI_LINK_TRAIN_NONE;
1709         temp |= FDI_LINK_TRAIN_PATTERN_2;
1710         I915_WRITE(fdi_rx_reg, temp);
1711         udelay(150);
1712
1713         tries = 0;
1714
1715         for (tries = 0; tries < 5; tries++) {
1716                 temp = I915_READ(fdi_rx_iir_reg);
1717                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1718
1719                 if (temp & FDI_RX_SYMBOL_LOCK) {
1720                         I915_WRITE(fdi_rx_iir_reg,
1721                                    temp | FDI_RX_SYMBOL_LOCK);
1722                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1723                         break;
1724                 }
1725         }
1726         if (tries == 5)
1727                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1728
1729         DRM_DEBUG_KMS("FDI train done\n");
1730 }
1731
1732 static int snb_b_fdi_train_param [] = {
1733         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1734         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1735         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1736         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1737 };
1738
1739 /* The FDI link training functions for SNB/Cougarpoint. */
1740 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1741 {
1742         struct drm_device *dev = crtc->dev;
1743         struct drm_i915_private *dev_priv = dev->dev_private;
1744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1745         int pipe = intel_crtc->pipe;
1746         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1747         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1748         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1749         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1750         u32 temp, i;
1751
1752         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1753            for train result */
1754         temp = I915_READ(fdi_rx_imr_reg);
1755         temp &= ~FDI_RX_SYMBOL_LOCK;
1756         temp &= ~FDI_RX_BIT_LOCK;
1757         I915_WRITE(fdi_rx_imr_reg, temp);
1758         I915_READ(fdi_rx_imr_reg);
1759         udelay(150);
1760
1761         /* enable CPU FDI TX and PCH FDI RX */
1762         temp = I915_READ(fdi_tx_reg);
1763         temp |= FDI_TX_ENABLE;
1764         temp &= ~(7 << 19);
1765         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1766         temp &= ~FDI_LINK_TRAIN_NONE;
1767         temp |= FDI_LINK_TRAIN_PATTERN_1;
1768         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1769         /* SNB-B */
1770         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1771         I915_WRITE(fdi_tx_reg, temp);
1772         I915_READ(fdi_tx_reg);
1773
1774         temp = I915_READ(fdi_rx_reg);
1775         if (HAS_PCH_CPT(dev)) {
1776                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1777                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1778         } else {
1779                 temp &= ~FDI_LINK_TRAIN_NONE;
1780                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1781         }
1782         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1783         I915_READ(fdi_rx_reg);
1784         udelay(150);
1785
1786         for (i = 0; i < 4; i++ ) {
1787                 temp = I915_READ(fdi_tx_reg);
1788                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1789                 temp |= snb_b_fdi_train_param[i];
1790                 I915_WRITE(fdi_tx_reg, temp);
1791                 udelay(500);
1792
1793                 temp = I915_READ(fdi_rx_iir_reg);
1794                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1795
1796                 if (temp & FDI_RX_BIT_LOCK) {
1797                         I915_WRITE(fdi_rx_iir_reg,
1798                                    temp | FDI_RX_BIT_LOCK);
1799                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1800                         break;
1801                 }
1802         }
1803         if (i == 4)
1804                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1805
1806         /* Train 2 */
1807         temp = I915_READ(fdi_tx_reg);
1808         temp &= ~FDI_LINK_TRAIN_NONE;
1809         temp |= FDI_LINK_TRAIN_PATTERN_2;
1810         if (IS_GEN6(dev)) {
1811                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1812                 /* SNB-B */
1813                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1814         }
1815         I915_WRITE(fdi_tx_reg, temp);
1816
1817         temp = I915_READ(fdi_rx_reg);
1818         if (HAS_PCH_CPT(dev)) {
1819                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1820                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1821         } else {
1822                 temp &= ~FDI_LINK_TRAIN_NONE;
1823                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1824         }
1825         I915_WRITE(fdi_rx_reg, temp);
1826         udelay(150);
1827
1828         for (i = 0; i < 4; i++ ) {
1829                 temp = I915_READ(fdi_tx_reg);
1830                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1831                 temp |= snb_b_fdi_train_param[i];
1832                 I915_WRITE(fdi_tx_reg, temp);
1833                 udelay(500);
1834
1835                 temp = I915_READ(fdi_rx_iir_reg);
1836                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1837
1838                 if (temp & FDI_RX_SYMBOL_LOCK) {
1839                         I915_WRITE(fdi_rx_iir_reg,
1840                                    temp | FDI_RX_SYMBOL_LOCK);
1841                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1842                         break;
1843                 }
1844         }
1845         if (i == 4)
1846                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1847
1848         DRM_DEBUG_KMS("FDI train done.\n");
1849 }
1850
1851 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1852 {
1853         struct drm_device *dev = crtc->dev;
1854         struct drm_i915_private *dev_priv = dev->dev_private;
1855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1856         int pipe = intel_crtc->pipe;
1857         int plane = intel_crtc->plane;
1858         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1859         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1860         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1861         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1862         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1863         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1864         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1865         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1866         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1867         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1868         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1869         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1870         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1871         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1872         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1873         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1874         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1875         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1876         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1877         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1878         u32 temp;
1879         u32 pipe_bpc;
1880
1881         temp = I915_READ(pipeconf_reg);
1882         pipe_bpc = temp & PIPE_BPC_MASK;
1883
1884         /* XXX: When our outputs are all unaware of DPMS modes other than off
1885          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1886          */
1887         switch (mode) {
1888         case DRM_MODE_DPMS_ON:
1889         case DRM_MODE_DPMS_STANDBY:
1890         case DRM_MODE_DPMS_SUSPEND:
1891                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1892
1893                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1894                         temp = I915_READ(PCH_LVDS);
1895                         if ((temp & LVDS_PORT_EN) == 0) {
1896                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1897                                 POSTING_READ(PCH_LVDS);
1898                         }
1899                 }
1900
1901                 if (!HAS_eDP) {
1902
1903                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1904                         temp = I915_READ(fdi_rx_reg);
1905                         /*
1906                          * make the BPC in FDI Rx be consistent with that in
1907                          * pipeconf reg.
1908                          */
1909                         temp &= ~(0x7 << 16);
1910                         temp |= (pipe_bpc << 11);
1911                         temp &= ~(7 << 19);
1912                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1913                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1914                         I915_READ(fdi_rx_reg);
1915                         udelay(200);
1916
1917                         /* Switch from Rawclk to PCDclk */
1918                         temp = I915_READ(fdi_rx_reg);
1919                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1920                         I915_READ(fdi_rx_reg);
1921                         udelay(200);
1922
1923                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1924                         temp = I915_READ(fdi_tx_reg);
1925                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1926                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1927                                 I915_READ(fdi_tx_reg);
1928                                 udelay(100);
1929                         }
1930                 }
1931
1932                 /* Enable panel fitting for LVDS */
1933                 if (dev_priv->pch_pf_size &&
1934                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1935                     || HAS_eDP || intel_pch_has_edp(crtc))) {
1936                         /* Force use of hard-coded filter coefficients
1937                          * as some pre-programmed values are broken,
1938                          * e.g. x201.
1939                          */
1940                         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1941                                    PF_ENABLE | PF_FILTER_MED_3x3);
1942                         I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1943                                    dev_priv->pch_pf_pos);
1944                         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1945                                    dev_priv->pch_pf_size);
1946                 }
1947
1948                 /* Enable CPU pipe */
1949                 temp = I915_READ(pipeconf_reg);
1950                 if ((temp & PIPEACONF_ENABLE) == 0) {
1951                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1952                         I915_READ(pipeconf_reg);
1953                         udelay(100);
1954                 }
1955
1956                 /* configure and enable CPU plane */
1957                 temp = I915_READ(dspcntr_reg);
1958                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1959                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1960                         /* Flush the plane changes */
1961                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1962                 }
1963
1964                 if (!HAS_eDP) {
1965                         /* For PCH output, training FDI link */
1966                         if (IS_GEN6(dev))
1967                                 gen6_fdi_link_train(crtc);
1968                         else
1969                                 ironlake_fdi_link_train(crtc);
1970
1971                         /* enable PCH DPLL */
1972                         temp = I915_READ(pch_dpll_reg);
1973                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1974                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1975                                 I915_READ(pch_dpll_reg);
1976                         }
1977                         udelay(200);
1978
1979                         if (HAS_PCH_CPT(dev)) {
1980                                 /* Be sure PCH DPLL SEL is set */
1981                                 temp = I915_READ(PCH_DPLL_SEL);
1982                                 if (trans_dpll_sel == 0 &&
1983                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1984                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1985                                 else if (trans_dpll_sel == 1 &&
1986                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1987                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1988                                 I915_WRITE(PCH_DPLL_SEL, temp);
1989                                 I915_READ(PCH_DPLL_SEL);
1990                         }
1991
1992                         /* set transcoder timing */
1993                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1994                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1995                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1996
1997                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1998                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1999                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2000
2001                         /* enable normal train */
2002                         temp = I915_READ(fdi_tx_reg);
2003                         temp &= ~FDI_LINK_TRAIN_NONE;
2004                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2005                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2006                         I915_READ(fdi_tx_reg);
2007
2008                         temp = I915_READ(fdi_rx_reg);
2009                         if (HAS_PCH_CPT(dev)) {
2010                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2011                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2012                         } else {
2013                                 temp &= ~FDI_LINK_TRAIN_NONE;
2014                                 temp |= FDI_LINK_TRAIN_NONE;
2015                         }
2016                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2017                         I915_READ(fdi_rx_reg);
2018
2019                         /* wait one idle pattern time */
2020                         udelay(100);
2021
2022                         /* For PCH DP, enable TRANS_DP_CTL */
2023                         if (HAS_PCH_CPT(dev) &&
2024                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2025                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2026                                 int reg;
2027
2028                                 reg = I915_READ(trans_dp_ctl);
2029                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2030                                          TRANS_DP_SYNC_MASK);
2031                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2032                                         TRANS_DP_ENH_FRAMING);
2033
2034                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2035                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2036                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2037                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2038
2039                                 switch (intel_trans_dp_port_sel(crtc)) {
2040                                 case PCH_DP_B:
2041                                         reg |= TRANS_DP_PORT_SEL_B;
2042                                         break;
2043                                 case PCH_DP_C:
2044                                         reg |= TRANS_DP_PORT_SEL_C;
2045                                         break;
2046                                 case PCH_DP_D:
2047                                         reg |= TRANS_DP_PORT_SEL_D;
2048                                         break;
2049                                 default:
2050                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2051                                         reg |= TRANS_DP_PORT_SEL_B;
2052                                         break;
2053                                 }
2054
2055                                 I915_WRITE(trans_dp_ctl, reg);
2056                                 POSTING_READ(trans_dp_ctl);
2057                         }
2058
2059                         /* enable PCH transcoder */
2060                         temp = I915_READ(transconf_reg);
2061                         /*
2062                          * make the BPC in transcoder be consistent with
2063                          * that in pipeconf reg.
2064                          */
2065                         temp &= ~PIPE_BPC_MASK;
2066                         temp |= pipe_bpc;
2067                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2068                         I915_READ(transconf_reg);
2069
2070                         if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
2071                                 DRM_ERROR("failed to enable transcoder\n");
2072                 }
2073
2074                 intel_crtc_load_lut(crtc);
2075
2076                 intel_update_fbc(crtc, &crtc->mode);
2077                 break;
2078
2079         case DRM_MODE_DPMS_OFF:
2080                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2081
2082                 drm_vblank_off(dev, pipe);
2083                 /* Disable display plane */
2084                 temp = I915_READ(dspcntr_reg);
2085                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2086                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2087                         /* Flush the plane changes */
2088                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2089                         I915_READ(dspbase_reg);
2090                 }
2091
2092                 if (dev_priv->cfb_plane == plane &&
2093                     dev_priv->display.disable_fbc)
2094                         dev_priv->display.disable_fbc(dev);
2095
2096                 /* disable cpu pipe, disable after all planes disabled */
2097                 temp = I915_READ(pipeconf_reg);
2098                 if ((temp & PIPEACONF_ENABLE) != 0) {
2099                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2100
2101                         /* wait for cpu pipe off, pipe state */
2102                         if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2103                                 DRM_ERROR("failed to turn off cpu pipe\n");
2104                 } else
2105                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2106
2107                 udelay(100);
2108
2109                 /* Disable PF */
2110                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2111                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2112
2113                 /* disable CPU FDI tx and PCH FDI rx */
2114                 temp = I915_READ(fdi_tx_reg);
2115                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2116                 I915_READ(fdi_tx_reg);
2117
2118                 temp = I915_READ(fdi_rx_reg);
2119                 /* BPC in FDI rx is consistent with that in pipeconf */
2120                 temp &= ~(0x07 << 16);
2121                 temp |= (pipe_bpc << 11);
2122                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2123                 I915_READ(fdi_rx_reg);
2124
2125                 udelay(100);
2126
2127                 /* still set train pattern 1 */
2128                 temp = I915_READ(fdi_tx_reg);
2129                 temp &= ~FDI_LINK_TRAIN_NONE;
2130                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2131                 I915_WRITE(fdi_tx_reg, temp);
2132                 POSTING_READ(fdi_tx_reg);
2133
2134                 temp = I915_READ(fdi_rx_reg);
2135                 if (HAS_PCH_CPT(dev)) {
2136                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2137                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2138                 } else {
2139                         temp &= ~FDI_LINK_TRAIN_NONE;
2140                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2141                 }
2142                 I915_WRITE(fdi_rx_reg, temp);
2143                 POSTING_READ(fdi_rx_reg);
2144
2145                 udelay(100);
2146
2147                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2148                         temp = I915_READ(PCH_LVDS);
2149                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2150                         I915_READ(PCH_LVDS);
2151                         udelay(100);
2152                 }
2153
2154                 /* disable PCH transcoder */
2155                 temp = I915_READ(transconf_reg);
2156                 if ((temp & TRANS_ENABLE) != 0) {
2157                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2158
2159                         /* wait for PCH transcoder off, transcoder state */
2160                         if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50))
2161                                 DRM_ERROR("failed to disable transcoder\n");
2162                 }
2163
2164                 temp = I915_READ(transconf_reg);
2165                 /* BPC in transcoder is consistent with that in pipeconf */
2166                 temp &= ~PIPE_BPC_MASK;
2167                 temp |= pipe_bpc;
2168                 I915_WRITE(transconf_reg, temp);
2169                 I915_READ(transconf_reg);
2170                 udelay(100);
2171
2172                 if (HAS_PCH_CPT(dev)) {
2173                         /* disable TRANS_DP_CTL */
2174                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2175                         int reg;
2176
2177                         reg = I915_READ(trans_dp_ctl);
2178                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2179                         I915_WRITE(trans_dp_ctl, reg);
2180                         POSTING_READ(trans_dp_ctl);
2181
2182                         /* disable DPLL_SEL */
2183                         temp = I915_READ(PCH_DPLL_SEL);
2184                         if (trans_dpll_sel == 0)
2185                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2186                         else
2187                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2188                         I915_WRITE(PCH_DPLL_SEL, temp);
2189                         I915_READ(PCH_DPLL_SEL);
2190
2191                 }
2192
2193                 /* disable PCH DPLL */
2194                 temp = I915_READ(pch_dpll_reg);
2195                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2196                 I915_READ(pch_dpll_reg);
2197
2198                 /* Switch from PCDclk to Rawclk */
2199                 temp = I915_READ(fdi_rx_reg);
2200                 temp &= ~FDI_SEL_PCDCLK;
2201                 I915_WRITE(fdi_rx_reg, temp);
2202                 I915_READ(fdi_rx_reg);
2203
2204                 /* Disable CPU FDI TX PLL */
2205                 temp = I915_READ(fdi_tx_reg);
2206                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2207                 I915_READ(fdi_tx_reg);
2208                 udelay(100);
2209
2210                 temp = I915_READ(fdi_rx_reg);
2211                 temp &= ~FDI_RX_PLL_ENABLE;
2212                 I915_WRITE(fdi_rx_reg, temp);
2213                 I915_READ(fdi_rx_reg);
2214
2215                 /* Wait for the clocks to turn off. */
2216                 udelay(100);
2217                 break;
2218         }
2219 }
2220
2221 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2222 {
2223         if (!enable && intel_crtc->overlay) {
2224                 struct drm_device *dev = intel_crtc->base.dev;
2225
2226                 mutex_lock(&dev->struct_mutex);
2227                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2228                 mutex_unlock(&dev->struct_mutex);
2229         }
2230
2231         /* Let userspace switch the overlay on again. In most cases userspace
2232          * has to recompute where to put it anyway.
2233          */
2234 }
2235
2236 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2237 {
2238         struct drm_device *dev = crtc->dev;
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241         int pipe = intel_crtc->pipe;
2242         int plane = intel_crtc->plane;
2243         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2244         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2245         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2246         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2247         u32 temp;
2248
2249         /* XXX: When our outputs are all unaware of DPMS modes other than off
2250          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2251          */
2252         switch (mode) {
2253         case DRM_MODE_DPMS_ON:
2254         case DRM_MODE_DPMS_STANDBY:
2255         case DRM_MODE_DPMS_SUSPEND:
2256                 /* Enable the DPLL */
2257                 temp = I915_READ(dpll_reg);
2258                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2259                         I915_WRITE(dpll_reg, temp);
2260                         I915_READ(dpll_reg);
2261                         /* Wait for the clocks to stabilize. */
2262                         udelay(150);
2263                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2264                         I915_READ(dpll_reg);
2265                         /* Wait for the clocks to stabilize. */
2266                         udelay(150);
2267                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2268                         I915_READ(dpll_reg);
2269                         /* Wait for the clocks to stabilize. */
2270                         udelay(150);
2271                 }
2272
2273                 /* Enable the pipe */
2274                 temp = I915_READ(pipeconf_reg);
2275                 if ((temp & PIPEACONF_ENABLE) == 0)
2276                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2277
2278                 /* Enable the plane */
2279                 temp = I915_READ(dspcntr_reg);
2280                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2281                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2282                         /* Flush the plane changes */
2283                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2284                 }
2285
2286                 intel_crtc_load_lut(crtc);
2287
2288                 if ((IS_I965G(dev) || plane == 0))
2289                         intel_update_fbc(crtc, &crtc->mode);
2290
2291                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2292                 intel_crtc_dpms_overlay(intel_crtc, true);
2293         break;
2294         case DRM_MODE_DPMS_OFF:
2295                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2296                 intel_crtc_dpms_overlay(intel_crtc, false);
2297                 drm_vblank_off(dev, pipe);
2298
2299                 if (dev_priv->cfb_plane == plane &&
2300                     dev_priv->display.disable_fbc)
2301                         dev_priv->display.disable_fbc(dev);
2302
2303                 /* Disable display plane */
2304                 temp = I915_READ(dspcntr_reg);
2305                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2306                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2307                         /* Flush the plane changes */
2308                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2309                         I915_READ(dspbase_reg);
2310                 }
2311
2312                 if (!IS_I9XX(dev)) {
2313                         /* Wait for vblank for the disable to take effect */
2314                         intel_wait_for_vblank_off(dev, pipe);
2315                 }
2316
2317                 /* Don't disable pipe A or pipe A PLLs if needed */
2318                 if (pipeconf_reg == PIPEACONF &&
2319                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2320                         goto skip_pipe_off;
2321
2322                 /* Next, disable display pipes */
2323                 temp = I915_READ(pipeconf_reg);
2324                 if ((temp & PIPEACONF_ENABLE) != 0) {
2325                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2326                         I915_READ(pipeconf_reg);
2327                 }
2328
2329                 /* Wait for vblank for the disable to take effect. */
2330                 intel_wait_for_vblank_off(dev, pipe);
2331
2332                 temp = I915_READ(dpll_reg);
2333                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2334                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2335                         I915_READ(dpll_reg);
2336                 }
2337         skip_pipe_off:
2338                 /* Wait for the clocks to turn off. */
2339                 udelay(150);
2340                 break;
2341         }
2342 }
2343
2344 /*
2345  * When we disable a pipe, we need to clear any pending scanline wait events
2346  * to avoid hanging the ring, which we assume we are waiting on.
2347  */
2348 static void intel_clear_scanline_wait(struct drm_device *dev)
2349 {
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         u32 tmp;
2352
2353         if (IS_GEN2(dev))
2354                 /* Can't break the hang on i8xx */
2355                 return;
2356
2357         tmp = I915_READ(PRB0_CTL);
2358         if (tmp & RING_WAIT) {
2359                 I915_WRITE(PRB0_CTL, tmp);
2360                 POSTING_READ(PRB0_CTL);
2361         }
2362 }
2363
2364 /**
2365  * Sets the power management mode of the pipe and plane.
2366  */
2367 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2368 {
2369         struct drm_device *dev = crtc->dev;
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371         struct drm_i915_master_private *master_priv;
2372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2373         int pipe = intel_crtc->pipe;
2374         bool enabled;
2375
2376         if (intel_crtc->dpms_mode == mode)
2377                 return;
2378
2379         intel_crtc->dpms_mode = mode;
2380         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2381
2382         /* When switching on the display, ensure that SR is disabled
2383          * with multiple pipes prior to enabling to new pipe.
2384          *
2385          * When switching off the display, make sure the cursor is
2386          * properly hidden and there are no pending waits prior to
2387          * disabling the pipe.
2388          */
2389         if (mode == DRM_MODE_DPMS_ON)
2390                 intel_update_watermarks(dev);
2391         else
2392                 intel_crtc_update_cursor(crtc);
2393
2394         dev_priv->display.dpms(crtc, mode);
2395
2396         if (mode == DRM_MODE_DPMS_ON)
2397                 intel_crtc_update_cursor(crtc);
2398         else {
2399                 /* XXX Note that this is not a complete solution, but a hack
2400                  * to avoid the most frequently hit hang.
2401                  */
2402                 intel_clear_scanline_wait(dev);
2403
2404                 intel_update_watermarks(dev);
2405         }
2406
2407         if (!dev->primary->master)
2408                 return;
2409
2410         master_priv = dev->primary->master->driver_priv;
2411         if (!master_priv->sarea_priv)
2412                 return;
2413
2414         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2415
2416         switch (pipe) {
2417         case 0:
2418                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2419                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2420                 break;
2421         case 1:
2422                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2423                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2424                 break;
2425         default:
2426                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2427                 break;
2428         }
2429 }
2430
2431 static void intel_crtc_prepare (struct drm_crtc *crtc)
2432 {
2433         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2434         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2435 }
2436
2437 static void intel_crtc_commit (struct drm_crtc *crtc)
2438 {
2439         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2440         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2441 }
2442
2443 void intel_encoder_prepare (struct drm_encoder *encoder)
2444 {
2445         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2446         /* lvds has its own version of prepare see intel_lvds_prepare */
2447         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2448 }
2449
2450 void intel_encoder_commit (struct drm_encoder *encoder)
2451 {
2452         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2453         /* lvds has its own version of commit see intel_lvds_commit */
2454         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2455 }
2456
2457 void intel_encoder_destroy(struct drm_encoder *encoder)
2458 {
2459         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2460
2461         if (intel_encoder->ddc_bus)
2462                 intel_i2c_destroy(intel_encoder->ddc_bus);
2463
2464         if (intel_encoder->i2c_bus)
2465                 intel_i2c_destroy(intel_encoder->i2c_bus);
2466
2467         drm_encoder_cleanup(encoder);
2468         kfree(intel_encoder);
2469 }
2470
2471 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2472                                   struct drm_display_mode *mode,
2473                                   struct drm_display_mode *adjusted_mode)
2474 {
2475         struct drm_device *dev = crtc->dev;
2476         if (HAS_PCH_SPLIT(dev)) {
2477                 /* FDI link clock is fixed at 2.7G */
2478                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2479                         return false;
2480         }
2481         return true;
2482 }
2483
2484 static int i945_get_display_clock_speed(struct drm_device *dev)
2485 {
2486         return 400000;
2487 }
2488
2489 static int i915_get_display_clock_speed(struct drm_device *dev)
2490 {
2491         return 333000;
2492 }
2493
2494 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2495 {
2496         return 200000;
2497 }
2498
2499 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2500 {
2501         u16 gcfgc = 0;
2502
2503         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2504
2505         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2506                 return 133000;
2507         else {
2508                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2509                 case GC_DISPLAY_CLOCK_333_MHZ:
2510                         return 333000;
2511                 default:
2512                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2513                         return 190000;
2514                 }
2515         }
2516 }
2517
2518 static int i865_get_display_clock_speed(struct drm_device *dev)
2519 {
2520         return 266000;
2521 }
2522
2523 static int i855_get_display_clock_speed(struct drm_device *dev)
2524 {
2525         u16 hpllcc = 0;
2526         /* Assume that the hardware is in the high speed state.  This
2527          * should be the default.
2528          */
2529         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2530         case GC_CLOCK_133_200:
2531         case GC_CLOCK_100_200:
2532                 return 200000;
2533         case GC_CLOCK_166_250:
2534                 return 250000;
2535         case GC_CLOCK_100_133:
2536                 return 133000;
2537         }
2538
2539         /* Shouldn't happen */
2540         return 0;
2541 }
2542
2543 static int i830_get_display_clock_speed(struct drm_device *dev)
2544 {
2545         return 133000;
2546 }
2547
2548 /**
2549  * Return the pipe currently connected to the panel fitter,
2550  * or -1 if the panel fitter is not present or not in use
2551  */
2552 int intel_panel_fitter_pipe (struct drm_device *dev)
2553 {
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555         u32  pfit_control;
2556
2557         /* i830 doesn't have a panel fitter */
2558         if (IS_I830(dev))
2559                 return -1;
2560
2561         pfit_control = I915_READ(PFIT_CONTROL);
2562
2563         /* See if the panel fitter is in use */
2564         if ((pfit_control & PFIT_ENABLE) == 0)
2565                 return -1;
2566
2567         /* 965 can place panel fitter on either pipe */
2568         if (IS_I965G(dev))
2569                 return (pfit_control >> 29) & 0x3;
2570
2571         /* older chips can only use pipe 1 */
2572         return 1;
2573 }
2574
2575 struct fdi_m_n {
2576         u32        tu;
2577         u32        gmch_m;
2578         u32        gmch_n;
2579         u32        link_m;
2580         u32        link_n;
2581 };
2582
2583 static void
2584 fdi_reduce_ratio(u32 *num, u32 *den)
2585 {
2586         while (*num > 0xffffff || *den > 0xffffff) {
2587                 *num >>= 1;
2588                 *den >>= 1;
2589         }
2590 }
2591
2592 #define DATA_N 0x800000
2593 #define LINK_N 0x80000
2594
2595 static void
2596 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2597                      int link_clock, struct fdi_m_n *m_n)
2598 {
2599         u64 temp;
2600
2601         m_n->tu = 64; /* default size */
2602
2603         temp = (u64) DATA_N * pixel_clock;
2604         temp = div_u64(temp, link_clock);
2605         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2606         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2607         m_n->gmch_n = DATA_N;
2608         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2609
2610         temp = (u64) LINK_N * pixel_clock;
2611         m_n->link_m = div_u64(temp, link_clock);
2612         m_n->link_n = LINK_N;
2613         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2614 }
2615
2616
2617 struct intel_watermark_params {
2618         unsigned long fifo_size;
2619         unsigned long max_wm;
2620         unsigned long default_wm;
2621         unsigned long guard_size;
2622         unsigned long cacheline_size;
2623 };
2624
2625 /* Pineview has different values for various configs */
2626 static struct intel_watermark_params pineview_display_wm = {
2627         PINEVIEW_DISPLAY_FIFO,
2628         PINEVIEW_MAX_WM,
2629         PINEVIEW_DFT_WM,
2630         PINEVIEW_GUARD_WM,
2631         PINEVIEW_FIFO_LINE_SIZE
2632 };
2633 static struct intel_watermark_params pineview_display_hplloff_wm = {
2634         PINEVIEW_DISPLAY_FIFO,
2635         PINEVIEW_MAX_WM,
2636         PINEVIEW_DFT_HPLLOFF_WM,
2637         PINEVIEW_GUARD_WM,
2638         PINEVIEW_FIFO_LINE_SIZE
2639 };
2640 static struct intel_watermark_params pineview_cursor_wm = {
2641         PINEVIEW_CURSOR_FIFO,
2642         PINEVIEW_CURSOR_MAX_WM,
2643         PINEVIEW_CURSOR_DFT_WM,
2644         PINEVIEW_CURSOR_GUARD_WM,
2645         PINEVIEW_FIFO_LINE_SIZE,
2646 };
2647 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2648         PINEVIEW_CURSOR_FIFO,
2649         PINEVIEW_CURSOR_MAX_WM,
2650         PINEVIEW_CURSOR_DFT_WM,
2651         PINEVIEW_CURSOR_GUARD_WM,
2652         PINEVIEW_FIFO_LINE_SIZE
2653 };
2654 static struct intel_watermark_params g4x_wm_info = {
2655         G4X_FIFO_SIZE,
2656         G4X_MAX_WM,
2657         G4X_MAX_WM,
2658         2,
2659         G4X_FIFO_LINE_SIZE,
2660 };
2661 static struct intel_watermark_params g4x_cursor_wm_info = {
2662         I965_CURSOR_FIFO,
2663         I965_CURSOR_MAX_WM,
2664         I965_CURSOR_DFT_WM,
2665         2,
2666         G4X_FIFO_LINE_SIZE,
2667 };
2668 static struct intel_watermark_params i965_cursor_wm_info = {
2669         I965_CURSOR_FIFO,
2670         I965_CURSOR_MAX_WM,
2671         I965_CURSOR_DFT_WM,
2672         2,
2673         I915_FIFO_LINE_SIZE,
2674 };
2675 static struct intel_watermark_params i945_wm_info = {
2676         I945_FIFO_SIZE,
2677         I915_MAX_WM,
2678         1,
2679         2,
2680         I915_FIFO_LINE_SIZE
2681 };
2682 static struct intel_watermark_params i915_wm_info = {
2683         I915_FIFO_SIZE,
2684         I915_MAX_WM,
2685         1,
2686         2,
2687         I915_FIFO_LINE_SIZE
2688 };
2689 static struct intel_watermark_params i855_wm_info = {
2690         I855GM_FIFO_SIZE,
2691         I915_MAX_WM,
2692         1,
2693         2,
2694         I830_FIFO_LINE_SIZE
2695 };
2696 static struct intel_watermark_params i830_wm_info = {
2697         I830_FIFO_SIZE,
2698         I915_MAX_WM,
2699         1,
2700         2,
2701         I830_FIFO_LINE_SIZE
2702 };
2703
2704 static struct intel_watermark_params ironlake_display_wm_info = {
2705         ILK_DISPLAY_FIFO,
2706         ILK_DISPLAY_MAXWM,
2707         ILK_DISPLAY_DFTWM,
2708         2,
2709         ILK_FIFO_LINE_SIZE
2710 };
2711
2712 static struct intel_watermark_params ironlake_cursor_wm_info = {
2713         ILK_CURSOR_FIFO,
2714         ILK_CURSOR_MAXWM,
2715         ILK_CURSOR_DFTWM,
2716         2,
2717         ILK_FIFO_LINE_SIZE
2718 };
2719
2720 static struct intel_watermark_params ironlake_display_srwm_info = {
2721         ILK_DISPLAY_SR_FIFO,
2722         ILK_DISPLAY_MAX_SRWM,
2723         ILK_DISPLAY_DFT_SRWM,
2724         2,
2725         ILK_FIFO_LINE_SIZE
2726 };
2727
2728 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2729         ILK_CURSOR_SR_FIFO,
2730         ILK_CURSOR_MAX_SRWM,
2731         ILK_CURSOR_DFT_SRWM,
2732         2,
2733         ILK_FIFO_LINE_SIZE
2734 };
2735
2736 /**
2737  * intel_calculate_wm - calculate watermark level
2738  * @clock_in_khz: pixel clock
2739  * @wm: chip FIFO params
2740  * @pixel_size: display pixel size
2741  * @latency_ns: memory latency for the platform
2742  *
2743  * Calculate the watermark level (the level at which the display plane will
2744  * start fetching from memory again).  Each chip has a different display
2745  * FIFO size and allocation, so the caller needs to figure that out and pass
2746  * in the correct intel_watermark_params structure.
2747  *
2748  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2749  * on the pixel size.  When it reaches the watermark level, it'll start
2750  * fetching FIFO line sized based chunks from memory until the FIFO fills
2751  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2752  * will occur, and a display engine hang could result.
2753  */
2754 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2755                                         struct intel_watermark_params *wm,
2756                                         int pixel_size,
2757                                         unsigned long latency_ns)
2758 {
2759         long entries_required, wm_size;
2760
2761         /*
2762          * Note: we need to make sure we don't overflow for various clock &
2763          * latency values.
2764          * clocks go from a few thousand to several hundred thousand.
2765          * latency is usually a few thousand
2766          */
2767         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2768                 1000;
2769         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2770
2771         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2772
2773         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2774
2775         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2776
2777         /* Don't promote wm_size to unsigned... */
2778         if (wm_size > (long)wm->max_wm)
2779                 wm_size = wm->max_wm;
2780         if (wm_size <= 0)
2781                 wm_size = wm->default_wm;
2782         return wm_size;
2783 }
2784
2785 struct cxsr_latency {
2786         int is_desktop;
2787         int is_ddr3;
2788         unsigned long fsb_freq;
2789         unsigned long mem_freq;
2790         unsigned long display_sr;
2791         unsigned long display_hpll_disable;
2792         unsigned long cursor_sr;
2793         unsigned long cursor_hpll_disable;
2794 };
2795
2796 static const struct cxsr_latency cxsr_latency_table[] = {
2797         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2798         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2799         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2800         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2801         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2802
2803         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2804         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2805         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2806         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2807         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2808
2809         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2810         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2811         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2812         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2813         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2814
2815         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2816         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2817         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2818         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2819         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2820
2821         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2822         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2823         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2824         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2825         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2826
2827         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2828         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2829         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2830         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2831         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2832 };
2833
2834 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2835                                                          int is_ddr3,
2836                                                          int fsb,
2837                                                          int mem)
2838 {
2839         const struct cxsr_latency *latency;
2840         int i;
2841
2842         if (fsb == 0 || mem == 0)
2843                 return NULL;
2844
2845         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2846                 latency = &cxsr_latency_table[i];
2847                 if (is_desktop == latency->is_desktop &&
2848                     is_ddr3 == latency->is_ddr3 &&
2849                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2850                         return latency;
2851         }
2852
2853         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2854
2855         return NULL;
2856 }
2857
2858 static void pineview_disable_cxsr(struct drm_device *dev)
2859 {
2860         struct drm_i915_private *dev_priv = dev->dev_private;
2861
2862         /* deactivate cxsr */
2863         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2864 }
2865
2866 /*
2867  * Latency for FIFO fetches is dependent on several factors:
2868  *   - memory configuration (speed, channels)
2869  *   - chipset
2870  *   - current MCH state
2871  * It can be fairly high in some situations, so here we assume a fairly
2872  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2873  * set this value too high, the FIFO will fetch frequently to stay full)
2874  * and power consumption (set it too low to save power and we might see
2875  * FIFO underruns and display "flicker").
2876  *
2877  * A value of 5us seems to be a good balance; safe for very low end
2878  * platforms but not overly aggressive on lower latency configs.
2879  */
2880 static const int latency_ns = 5000;
2881
2882 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2883 {
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         uint32_t dsparb = I915_READ(DSPARB);
2886         int size;
2887
2888         size = dsparb & 0x7f;
2889         if (plane)
2890                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2891
2892         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2893                         plane ? "B" : "A", size);
2894
2895         return size;
2896 }
2897
2898 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2899 {
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901         uint32_t dsparb = I915_READ(DSPARB);
2902         int size;
2903
2904         size = dsparb & 0x1ff;
2905         if (plane)
2906                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2907         size >>= 1; /* Convert to cachelines */
2908
2909         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2910                         plane ? "B" : "A", size);
2911
2912         return size;
2913 }
2914
2915 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2916 {
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         uint32_t dsparb = I915_READ(DSPARB);
2919         int size;
2920
2921         size = dsparb & 0x7f;
2922         size >>= 2; /* Convert to cachelines */
2923
2924         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2925                         plane ? "B" : "A",
2926                   size);
2927
2928         return size;
2929 }
2930
2931 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2932 {
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         uint32_t dsparb = I915_READ(DSPARB);
2935         int size;
2936
2937         size = dsparb & 0x7f;
2938         size >>= 1; /* Convert to cachelines */
2939
2940         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2941                         plane ? "B" : "A", size);
2942
2943         return size;
2944 }
2945
2946 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2947                           int planeb_clock, int sr_hdisplay, int unused,
2948                           int pixel_size)
2949 {
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         const struct cxsr_latency *latency;
2952         u32 reg;
2953         unsigned long wm;
2954         int sr_clock;
2955
2956         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2957                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2958         if (!latency) {
2959                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2960                 pineview_disable_cxsr(dev);
2961                 return;
2962         }
2963
2964         if (!planea_clock || !planeb_clock) {
2965                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2966
2967                 /* Display SR */
2968                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2969                                         pixel_size, latency->display_sr);
2970                 reg = I915_READ(DSPFW1);
2971                 reg &= ~DSPFW_SR_MASK;
2972                 reg |= wm << DSPFW_SR_SHIFT;
2973                 I915_WRITE(DSPFW1, reg);
2974                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2975
2976                 /* cursor SR */
2977                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2978                                         pixel_size, latency->cursor_sr);
2979                 reg = I915_READ(DSPFW3);
2980                 reg &= ~DSPFW_CURSOR_SR_MASK;
2981                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2982                 I915_WRITE(DSPFW3, reg);
2983
2984                 /* Display HPLL off SR */
2985                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2986                                         pixel_size, latency->display_hpll_disable);
2987                 reg = I915_READ(DSPFW3);
2988                 reg &= ~DSPFW_HPLL_SR_MASK;
2989                 reg |= wm & DSPFW_HPLL_SR_MASK;
2990                 I915_WRITE(DSPFW3, reg);
2991
2992                 /* cursor HPLL off SR */
2993                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2994                                         pixel_size, latency->cursor_hpll_disable);
2995                 reg = I915_READ(DSPFW3);
2996                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2997                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2998                 I915_WRITE(DSPFW3, reg);
2999                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3000
3001                 /* activate cxsr */
3002                 I915_WRITE(DSPFW3,
3003                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3004                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3005         } else {
3006                 pineview_disable_cxsr(dev);
3007                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3008         }
3009 }
3010
3011 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3012                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3013                           int pixel_size)
3014 {
3015         struct drm_i915_private *dev_priv = dev->dev_private;
3016         int total_size, cacheline_size;
3017         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3018         struct intel_watermark_params planea_params, planeb_params;
3019         unsigned long line_time_us;
3020         int sr_clock, sr_entries = 0, entries_required;
3021
3022         /* Create copies of the base settings for each pipe */
3023         planea_params = planeb_params = g4x_wm_info;
3024
3025         /* Grab a couple of global values before we overwrite them */
3026         total_size = planea_params.fifo_size;
3027         cacheline_size = planea_params.cacheline_size;
3028
3029         /*
3030          * Note: we need to make sure we don't overflow for various clock &
3031          * latency values.
3032          * clocks go from a few thousand to several hundred thousand.
3033          * latency is usually a few thousand
3034          */
3035         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3036                 1000;
3037         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3038         planea_wm = entries_required + planea_params.guard_size;
3039
3040         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3041                 1000;
3042         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3043         planeb_wm = entries_required + planeb_params.guard_size;
3044
3045         cursora_wm = cursorb_wm = 16;
3046         cursor_sr = 32;
3047
3048         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3049
3050         /* Calc sr entries for one plane configs */
3051         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3052                 /* self-refresh has much higher latency */
3053                 static const int sr_latency_ns = 12000;
3054
3055                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3056                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3057
3058                 /* Use ns/us then divide to preserve precision */
3059                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3060                               pixel_size * sr_hdisplay;
3061                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3062
3063                 entries_required = (((sr_latency_ns / line_time_us) +
3064                                      1000) / 1000) * pixel_size * 64;
3065                 entries_required = DIV_ROUND_UP(entries_required,
3066                                            g4x_cursor_wm_info.cacheline_size);
3067                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3068
3069                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3070                         cursor_sr = g4x_cursor_wm_info.max_wm;
3071                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3072                               "cursor %d\n", sr_entries, cursor_sr);
3073
3074                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3075         } else {
3076                 /* Turn off self refresh if both pipes are enabled */
3077                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3078                                         & ~FW_BLC_SELF_EN);
3079         }
3080
3081         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3082                   planea_wm, planeb_wm, sr_entries);
3083
3084         planea_wm &= 0x3f;
3085         planeb_wm &= 0x3f;
3086
3087         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3088                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3089                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3090         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3091                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3092         /* HPLL off in SR has some issues on G4x... disable it */
3093         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3094                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3095 }
3096
3097 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3098                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3099                            int pixel_size)
3100 {
3101         struct drm_i915_private *dev_priv = dev->dev_private;
3102         unsigned long line_time_us;
3103         int sr_clock, sr_entries, srwm = 1;
3104         int cursor_sr = 16;
3105
3106         /* Calc sr entries for one plane configs */
3107         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3108                 /* self-refresh has much higher latency */
3109                 static const int sr_latency_ns = 12000;
3110
3111                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3112                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3113
3114                 /* Use ns/us then divide to preserve precision */
3115                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3116                               pixel_size * sr_hdisplay;
3117                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3118                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3119                 srwm = I965_FIFO_SIZE - sr_entries;
3120                 if (srwm < 0)
3121                         srwm = 1;
3122                 srwm &= 0x1ff;
3123
3124                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3125                              pixel_size * 64;
3126                 sr_entries = DIV_ROUND_UP(sr_entries,
3127                                           i965_cursor_wm_info.cacheline_size);
3128                 cursor_sr = i965_cursor_wm_info.fifo_size -
3129                             (sr_entries + i965_cursor_wm_info.guard_size);
3130
3131                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3132                         cursor_sr = i965_cursor_wm_info.max_wm;
3133
3134                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3135                               "cursor %d\n", srwm, cursor_sr);
3136
3137                 if (IS_I965GM(dev))
3138                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3139         } else {
3140                 /* Turn off self refresh if both pipes are enabled */
3141                 if (IS_I965GM(dev))
3142                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3143                                    & ~FW_BLC_SELF_EN);
3144         }
3145
3146         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3147                       srwm);
3148
3149         /* 965 has limitations... */
3150         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3151                    (8 << 0));
3152         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3153         /* update cursor SR watermark */
3154         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3155 }
3156
3157 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3158                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3159                            int pixel_size)
3160 {
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162         uint32_t fwater_lo;
3163         uint32_t fwater_hi;
3164         int total_size, cacheline_size, cwm, srwm = 1;
3165         int planea_wm, planeb_wm;
3166         struct intel_watermark_params planea_params, planeb_params;
3167         unsigned long line_time_us;
3168         int sr_clock, sr_entries = 0;
3169
3170         /* Create copies of the base settings for each pipe */
3171         if (IS_I965GM(dev) || IS_I945GM(dev))
3172                 planea_params = planeb_params = i945_wm_info;
3173         else if (IS_I9XX(dev))
3174                 planea_params = planeb_params = i915_wm_info;
3175         else
3176                 planea_params = planeb_params = i855_wm_info;
3177
3178         /* Grab a couple of global values before we overwrite them */
3179         total_size = planea_params.fifo_size;
3180         cacheline_size = planea_params.cacheline_size;
3181
3182         /* Update per-plane FIFO sizes */
3183         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3184         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3185
3186         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3187                                        pixel_size, latency_ns);
3188         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3189                                        pixel_size, latency_ns);
3190         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3191
3192         /*
3193          * Overlay gets an aggressive default since video jitter is bad.
3194          */
3195         cwm = 2;
3196
3197         /* Calc sr entries for one plane configs */
3198         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3199             (!planea_clock || !planeb_clock)) {
3200                 /* self-refresh has much higher latency */
3201                 static const int sr_latency_ns = 6000;
3202
3203                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3204                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3205
3206                 /* Use ns/us then divide to preserve precision */
3207                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3208                               pixel_size * sr_hdisplay;
3209                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3210                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3211                 srwm = total_size - sr_entries;
3212                 if (srwm < 0)
3213                         srwm = 1;
3214
3215                 if (IS_I945G(dev) || IS_I945GM(dev))
3216                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3217                 else if (IS_I915GM(dev)) {
3218                         /* 915M has a smaller SRWM field */
3219                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3220                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3221                 }
3222         } else {
3223                 /* Turn off self refresh if both pipes are enabled */
3224                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3225                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3226                                    & ~FW_BLC_SELF_EN);
3227                 } else if (IS_I915GM(dev)) {
3228                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3229                 }
3230         }
3231
3232         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3233                   planea_wm, planeb_wm, cwm, srwm);
3234
3235         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3236         fwater_hi = (cwm & 0x1f);
3237
3238         /* Set request length to 8 cachelines per fetch */
3239         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3240         fwater_hi = fwater_hi | (1 << 8);
3241
3242         I915_WRITE(FW_BLC, fwater_lo);
3243         I915_WRITE(FW_BLC2, fwater_hi);
3244 }
3245
3246 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3247                            int unused2, int unused3, int pixel_size)
3248 {
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3251         int planea_wm;
3252
3253         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3254
3255         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3256                                        pixel_size, latency_ns);
3257         fwater_lo |= (3<<8) | planea_wm;
3258
3259         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3260
3261         I915_WRITE(FW_BLC, fwater_lo);
3262 }
3263
3264 #define ILK_LP0_PLANE_LATENCY           700
3265 #define ILK_LP0_CURSOR_LATENCY          1300
3266
3267 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3268                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3269                        int pixel_size)
3270 {
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3273         int sr_wm, cursor_wm;
3274         unsigned long line_time_us;
3275         int sr_clock, entries_required;
3276         u32 reg_value;
3277         int line_count;
3278         int planea_htotal = 0, planeb_htotal = 0;
3279         struct drm_crtc *crtc;
3280
3281         /* Need htotal for all active display plane */
3282         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3283                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3285                         if (intel_crtc->plane == 0)
3286                                 planea_htotal = crtc->mode.htotal;
3287                         else
3288                                 planeb_htotal = crtc->mode.htotal;
3289                 }
3290         }
3291
3292         /* Calculate and update the watermark for plane A */
3293         if (planea_clock) {
3294                 entries_required = ((planea_clock / 1000) * pixel_size *
3295                                      ILK_LP0_PLANE_LATENCY) / 1000;
3296                 entries_required = DIV_ROUND_UP(entries_required,
3297                                                 ironlake_display_wm_info.cacheline_size);
3298                 planea_wm = entries_required +
3299                             ironlake_display_wm_info.guard_size;
3300
3301                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3302                         planea_wm = ironlake_display_wm_info.max_wm;
3303
3304                 /* Use the large buffer method to calculate cursor watermark */
3305                 line_time_us = (planea_htotal * 1000) / planea_clock;
3306
3307                 /* Use ns/us then divide to preserve precision */
3308                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3309
3310                 /* calculate the cursor watermark for cursor A */
3311                 entries_required = line_count * 64 * pixel_size;
3312                 entries_required = DIV_ROUND_UP(entries_required,
3313                                                 ironlake_cursor_wm_info.cacheline_size);
3314                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3315                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3316                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3317
3318                 reg_value = I915_READ(WM0_PIPEA_ILK);
3319                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3320                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3321                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3322                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3323                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3324                                 "cursor: %d\n", planea_wm, cursora_wm);
3325         }
3326         /* Calculate and update the watermark for plane B */
3327         if (planeb_clock) {
3328                 entries_required = ((planeb_clock / 1000) * pixel_size *
3329                                      ILK_LP0_PLANE_LATENCY) / 1000;
3330                 entries_required = DIV_ROUND_UP(entries_required,
3331                                                 ironlake_display_wm_info.cacheline_size);
3332                 planeb_wm = entries_required +
3333                             ironlake_display_wm_info.guard_size;
3334
3335                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3336                         planeb_wm = ironlake_display_wm_info.max_wm;
3337
3338                 /* Use the large buffer method to calculate cursor watermark */
3339                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3340
3341                 /* Use ns/us then divide to preserve precision */
3342                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3343
3344                 /* calculate the cursor watermark for cursor B */
3345                 entries_required = line_count * 64 * pixel_size;
3346                 entries_required = DIV_ROUND_UP(entries_required,
3347                                                 ironlake_cursor_wm_info.cacheline_size);
3348                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3349                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3350                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3351
3352                 reg_value = I915_READ(WM0_PIPEB_ILK);
3353                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3354                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3355                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3356                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3357                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3358                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3359         }
3360
3361         /*
3362          * Calculate and update the self-refresh watermark only when one
3363          * display plane is used.
3364          */
3365         if (!planea_clock || !planeb_clock) {
3366
3367                 /* Read the self-refresh latency. The unit is 0.5us */
3368                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3369
3370                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3371                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3372
3373                 /* Use ns/us then divide to preserve precision */
3374                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3375                                / 1000;
3376
3377                 /* calculate the self-refresh watermark for display plane */
3378                 entries_required = line_count * sr_hdisplay * pixel_size;
3379                 entries_required = DIV_ROUND_UP(entries_required,
3380                                                 ironlake_display_srwm_info.cacheline_size);
3381                 sr_wm = entries_required +
3382                         ironlake_display_srwm_info.guard_size;
3383
3384                 /* calculate the self-refresh watermark for display cursor */
3385                 entries_required = line_count * pixel_size * 64;
3386                 entries_required = DIV_ROUND_UP(entries_required,
3387                                                 ironlake_cursor_srwm_info.cacheline_size);
3388                 cursor_wm = entries_required +
3389                             ironlake_cursor_srwm_info.guard_size;
3390
3391                 /* configure watermark and enable self-refresh */
3392                 reg_value = I915_READ(WM1_LP_ILK);
3393                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3394                                WM1_LP_CURSOR_MASK);
3395                 reg_value |= WM1_LP_SR_EN |
3396                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3397                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3398
3399                 I915_WRITE(WM1_LP_ILK, reg_value);
3400                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3401                                 "cursor %d\n", sr_wm, cursor_wm);
3402
3403         } else {
3404                 /* Turn off self refresh if both pipes are enabled */
3405                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3406         }
3407 }
3408 /**
3409  * intel_update_watermarks - update FIFO watermark values based on current modes
3410  *
3411  * Calculate watermark values for the various WM regs based on current mode
3412  * and plane configuration.
3413  *
3414  * There are several cases to deal with here:
3415  *   - normal (i.e. non-self-refresh)
3416  *   - self-refresh (SR) mode
3417  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3418  *   - lines are small relative to FIFO size (buffer can hold more than 2
3419  *     lines), so need to account for TLB latency
3420  *
3421  *   The normal calculation is:
3422  *     watermark = dotclock * bytes per pixel * latency
3423  *   where latency is platform & configuration dependent (we assume pessimal
3424  *   values here).
3425  *
3426  *   The SR calculation is:
3427  *     watermark = (trunc(latency/line time)+1) * surface width *
3428  *       bytes per pixel
3429  *   where
3430  *     line time = htotal / dotclock
3431  *     surface width = hdisplay for normal plane and 64 for cursor
3432  *   and latency is assumed to be high, as above.
3433  *
3434  * The final value programmed to the register should always be rounded up,
3435  * and include an extra 2 entries to account for clock crossings.
3436  *
3437  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3438  * to set the non-SR watermarks to 8.
3439   */
3440 static void intel_update_watermarks(struct drm_device *dev)
3441 {
3442         struct drm_i915_private *dev_priv = dev->dev_private;
3443         struct drm_crtc *crtc;
3444         int sr_hdisplay = 0;
3445         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3446         int enabled = 0, pixel_size = 0;
3447         int sr_htotal = 0;
3448
3449         if (!dev_priv->display.update_wm)
3450                 return;
3451
3452         /* Get the clock config from both planes */
3453         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3454                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3456                         enabled++;
3457                         if (intel_crtc->plane == 0) {
3458                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3459                                           intel_crtc->pipe, crtc->mode.clock);
3460                                 planea_clock = crtc->mode.clock;
3461                         } else {
3462                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3463                                           intel_crtc->pipe, crtc->mode.clock);
3464                                 planeb_clock = crtc->mode.clock;
3465                         }
3466                         sr_hdisplay = crtc->mode.hdisplay;
3467                         sr_clock = crtc->mode.clock;
3468                         sr_htotal = crtc->mode.htotal;
3469                         if (crtc->fb)
3470                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3471                         else
3472                                 pixel_size = 4; /* by default */
3473                 }
3474         }
3475
3476         if (enabled <= 0)
3477                 return;
3478
3479         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3480                                     sr_hdisplay, sr_htotal, pixel_size);
3481 }
3482
3483 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3484                                struct drm_display_mode *mode,
3485                                struct drm_display_mode *adjusted_mode,
3486                                int x, int y,
3487                                struct drm_framebuffer *old_fb)
3488 {
3489         struct drm_device *dev = crtc->dev;
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492         int pipe = intel_crtc->pipe;
3493         int plane = intel_crtc->plane;
3494         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3495         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3496         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3497         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3498         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3499         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3500         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3501         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3502         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3503         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3504         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3505         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3506         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3507         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3508         int refclk, num_connectors = 0;
3509         intel_clock_t clock, reduced_clock;
3510         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3511         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3512         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3513         struct intel_encoder *has_edp_encoder = NULL;
3514         struct drm_mode_config *mode_config = &dev->mode_config;
3515         struct drm_encoder *encoder;
3516         const intel_limit_t *limit;
3517         int ret;
3518         struct fdi_m_n m_n = {0};
3519         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3520         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3521         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3522         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3523         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3524         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3525         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3526         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3527         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3528         int lvds_reg = LVDS;
3529         u32 temp;
3530         int target_clock;
3531
3532         drm_vblank_pre_modeset(dev, pipe);
3533
3534         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3535                 struct intel_encoder *intel_encoder;
3536
3537                 if (encoder->crtc != crtc)
3538                         continue;
3539
3540                 intel_encoder = to_intel_encoder(encoder);
3541                 switch (intel_encoder->type) {
3542                 case INTEL_OUTPUT_LVDS:
3543                         is_lvds = true;
3544                         break;
3545                 case INTEL_OUTPUT_SDVO:
3546                 case INTEL_OUTPUT_HDMI:
3547                         is_sdvo = true;
3548                         if (intel_encoder->needs_tv_clock)
3549                                 is_tv = true;
3550                         break;
3551                 case INTEL_OUTPUT_DVO:
3552                         is_dvo = true;
3553                         break;
3554                 case INTEL_OUTPUT_TVOUT:
3555                         is_tv = true;
3556                         break;
3557                 case INTEL_OUTPUT_ANALOG:
3558                         is_crt = true;
3559                         break;
3560                 case INTEL_OUTPUT_DISPLAYPORT:
3561                         is_dp = true;
3562                         break;
3563                 case INTEL_OUTPUT_EDP:
3564                         has_edp_encoder = intel_encoder;
3565                         break;
3566                 }
3567
3568                 num_connectors++;
3569         }
3570
3571         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3572                 refclk = dev_priv->lvds_ssc_freq * 1000;
3573                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3574                                         refclk / 1000);
3575         } else if (IS_I9XX(dev)) {
3576                 refclk = 96000;
3577                 if (HAS_PCH_SPLIT(dev))
3578                         refclk = 120000; /* 120Mhz refclk */
3579         } else {
3580                 refclk = 48000;
3581         }
3582
3583
3584         /*
3585          * Returns a set of divisors for the desired target clock with the given
3586          * refclk, or FALSE.  The returned values represent the clock equation:
3587          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3588          */
3589         limit = intel_limit(crtc);
3590         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3591         if (!ok) {
3592                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3593                 drm_vblank_post_modeset(dev, pipe);
3594                 return -EINVAL;
3595         }
3596
3597         /* Ensure that the cursor is valid for the new mode before changing... */
3598         intel_crtc_update_cursor(crtc);
3599
3600         if (is_lvds && dev_priv->lvds_downclock_avail) {
3601                 has_reduced_clock = limit->find_pll(limit, crtc,
3602                                                             dev_priv->lvds_downclock,
3603                                                             refclk,
3604                                                             &reduced_clock);
3605                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3606                         /*
3607                          * If the different P is found, it means that we can't
3608                          * switch the display clock by using the FP0/FP1.
3609                          * In such case we will disable the LVDS downclock
3610                          * feature.
3611                          */
3612                         DRM_DEBUG_KMS("Different P is found for "
3613                                                 "LVDS clock/downclock\n");
3614                         has_reduced_clock = 0;
3615                 }
3616         }
3617         /* SDVO TV has fixed PLL values depend on its clock range,
3618            this mirrors vbios setting. */
3619         if (is_sdvo && is_tv) {
3620                 if (adjusted_mode->clock >= 100000
3621                                 && adjusted_mode->clock < 140500) {
3622                         clock.p1 = 2;
3623                         clock.p2 = 10;
3624                         clock.n = 3;
3625                         clock.m1 = 16;
3626                         clock.m2 = 8;
3627                 } else if (adjusted_mode->clock >= 140500
3628                                 && adjusted_mode->clock <= 200000) {
3629                         clock.p1 = 1;
3630                         clock.p2 = 10;
3631                         clock.n = 6;
3632                         clock.m1 = 12;
3633                         clock.m2 = 8;
3634                 }
3635         }
3636
3637         /* FDI link */
3638         if (HAS_PCH_SPLIT(dev)) {
3639                 int lane = 0, link_bw, bpp;
3640                 /* eDP doesn't require FDI link, so just set DP M/N
3641                    according to current link config */
3642                 if (has_edp_encoder) {
3643                         target_clock = mode->clock;
3644                         intel_edp_link_config(has_edp_encoder,
3645                                               &lane, &link_bw);
3646                 } else {
3647                         /* DP over FDI requires target mode clock
3648                            instead of link clock */
3649                         if (is_dp)
3650                                 target_clock = mode->clock;
3651                         else
3652                                 target_clock = adjusted_mode->clock;
3653                         link_bw = 270000;
3654                 }
3655
3656                 /* determine panel color depth */
3657                 temp = I915_READ(pipeconf_reg);
3658                 temp &= ~PIPE_BPC_MASK;
3659                 if (is_lvds) {
3660                         int lvds_reg = I915_READ(PCH_LVDS);
3661                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3662                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3663                                 temp |= PIPE_8BPC;
3664                         else
3665                                 temp |= PIPE_6BPC;
3666                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3667                         switch (dev_priv->edp_bpp/3) {
3668                         case 8:
3669                                 temp |= PIPE_8BPC;
3670                                 break;
3671                         case 10:
3672                                 temp |= PIPE_10BPC;
3673                                 break;
3674                         case 6:
3675                                 temp |= PIPE_6BPC;
3676                                 break;
3677                         case 12:
3678                                 temp |= PIPE_12BPC;
3679                                 break;
3680                         }
3681                 } else
3682                         temp |= PIPE_8BPC;
3683                 I915_WRITE(pipeconf_reg, temp);
3684                 I915_READ(pipeconf_reg);
3685
3686                 switch (temp & PIPE_BPC_MASK) {
3687                 case PIPE_8BPC:
3688                         bpp = 24;
3689                         break;
3690                 case PIPE_10BPC:
3691                         bpp = 30;
3692                         break;
3693                 case PIPE_6BPC:
3694                         bpp = 18;
3695                         break;
3696                 case PIPE_12BPC:
3697                         bpp = 36;
3698                         break;
3699                 default:
3700                         DRM_ERROR("unknown pipe bpc value\n");
3701                         bpp = 24;
3702                 }
3703
3704                 if (!lane) {
3705                         /*
3706                          * Account for spread spectrum to avoid
3707                          * oversubscribing the link. Max center spread
3708                          * is 2.5%; use 5% for safety's sake.
3709                          */
3710                         u32 bps = target_clock * bpp * 21 / 20;
3711                         lane = bps / (link_bw * 8) + 1;
3712                 }
3713
3714                 intel_crtc->fdi_lanes = lane;
3715
3716                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3717         }
3718
3719         /* Ironlake: try to setup display ref clock before DPLL
3720          * enabling. This is only under driver's control after
3721          * PCH B stepping, previous chipset stepping should be
3722          * ignoring this setting.
3723          */
3724         if (HAS_PCH_SPLIT(dev)) {
3725                 temp = I915_READ(PCH_DREF_CONTROL);
3726                 /* Always enable nonspread source */
3727                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3728                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3729                 I915_WRITE(PCH_DREF_CONTROL, temp);
3730                 POSTING_READ(PCH_DREF_CONTROL);
3731
3732                 temp &= ~DREF_SSC_SOURCE_MASK;
3733                 temp |= DREF_SSC_SOURCE_ENABLE;
3734                 I915_WRITE(PCH_DREF_CONTROL, temp);
3735                 POSTING_READ(PCH_DREF_CONTROL);
3736
3737                 udelay(200);
3738
3739                 if (has_edp_encoder) {
3740                         if (dev_priv->lvds_use_ssc) {
3741                                 temp |= DREF_SSC1_ENABLE;
3742                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3743                                 POSTING_READ(PCH_DREF_CONTROL);
3744
3745                                 udelay(200);
3746
3747                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3748                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3749                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3750                                 POSTING_READ(PCH_DREF_CONTROL);
3751                         } else {
3752                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3753                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3754                                 POSTING_READ(PCH_DREF_CONTROL);
3755                         }
3756                 }
3757         }
3758
3759         if (IS_PINEVIEW(dev)) {
3760                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3761                 if (has_reduced_clock)
3762                         fp2 = (1 << reduced_clock.n) << 16 |
3763                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3764         } else {
3765                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3766                 if (has_reduced_clock)
3767                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3768                                 reduced_clock.m2;
3769         }
3770
3771         if (!HAS_PCH_SPLIT(dev))
3772                 dpll = DPLL_VGA_MODE_DIS;
3773
3774         if (IS_I9XX(dev)) {
3775                 if (is_lvds)
3776                         dpll |= DPLLB_MODE_LVDS;
3777                 else
3778                         dpll |= DPLLB_MODE_DAC_SERIAL;
3779                 if (is_sdvo) {
3780                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3781                         if (pixel_multiplier > 1) {
3782                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3783                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3784                                 else if (HAS_PCH_SPLIT(dev))
3785                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3786                         }
3787                         dpll |= DPLL_DVO_HIGH_SPEED;
3788                 }
3789                 if (is_dp)
3790                         dpll |= DPLL_DVO_HIGH_SPEED;
3791
3792                 /* compute bitmask from p1 value */
3793                 if (IS_PINEVIEW(dev))
3794                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3795                 else {
3796                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3797                         /* also FPA1 */
3798                         if (HAS_PCH_SPLIT(dev))
3799                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3800                         if (IS_G4X(dev) && has_reduced_clock)
3801                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3802                 }
3803                 switch (clock.p2) {
3804                 case 5:
3805                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3806                         break;
3807                 case 7:
3808                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3809                         break;
3810                 case 10:
3811                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3812                         break;
3813                 case 14:
3814                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3815                         break;
3816                 }
3817                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3818                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3819         } else {
3820                 if (is_lvds) {
3821                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3822                 } else {
3823                         if (clock.p1 == 2)
3824                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3825                         else
3826                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3827                         if (clock.p2 == 4)
3828                                 dpll |= PLL_P2_DIVIDE_BY_4;
3829                 }
3830         }
3831
3832         if (is_sdvo && is_tv)
3833                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3834         else if (is_tv)
3835                 /* XXX: just matching BIOS for now */
3836                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3837                 dpll |= 3;
3838         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3839                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3840         else
3841                 dpll |= PLL_REF_INPUT_DREFCLK;
3842
3843         /* setup pipeconf */
3844         pipeconf = I915_READ(pipeconf_reg);
3845
3846         /* Set up the display plane register */
3847         dspcntr = DISPPLANE_GAMMA_ENABLE;
3848
3849         /* Ironlake's plane is forced to pipe, bit 24 is to
3850            enable color space conversion */
3851         if (!HAS_PCH_SPLIT(dev)) {
3852                 if (pipe == 0)
3853                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3854                 else
3855                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3856         }
3857
3858         if (pipe == 0 && !IS_I965G(dev)) {
3859                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3860                  * core speed.
3861                  *
3862                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3863                  * pipe == 0 check?
3864                  */
3865                 if (mode->clock >
3866                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3867                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3868                 else
3869                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3870         }
3871
3872         dspcntr |= DISPLAY_PLANE_ENABLE;
3873         pipeconf |= PIPEACONF_ENABLE;
3874         dpll |= DPLL_VCO_ENABLE;
3875
3876
3877         /* Disable the panel fitter if it was on our pipe */
3878         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3879                 I915_WRITE(PFIT_CONTROL, 0);
3880
3881         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3882         drm_mode_debug_printmodeline(mode);
3883
3884         /* assign to Ironlake registers */
3885         if (HAS_PCH_SPLIT(dev)) {
3886                 fp_reg = pch_fp_reg;
3887                 dpll_reg = pch_dpll_reg;
3888         }
3889
3890         if (!has_edp_encoder) {
3891                 I915_WRITE(fp_reg, fp);
3892                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3893                 I915_READ(dpll_reg);
3894                 udelay(150);
3895         }
3896
3897         /* enable transcoder DPLL */
3898         if (HAS_PCH_CPT(dev)) {
3899                 temp = I915_READ(PCH_DPLL_SEL);
3900                 if (trans_dpll_sel == 0)
3901                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3902                 else
3903                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3904                 I915_WRITE(PCH_DPLL_SEL, temp);
3905                 I915_READ(PCH_DPLL_SEL);
3906                 udelay(150);
3907         }
3908
3909         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3910          * This is an exception to the general rule that mode_set doesn't turn
3911          * things on.
3912          */
3913         if (is_lvds) {
3914                 u32 lvds;
3915
3916                 if (HAS_PCH_SPLIT(dev))
3917                         lvds_reg = PCH_LVDS;
3918
3919                 lvds = I915_READ(lvds_reg);
3920                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3921                 if (pipe == 1) {
3922                         if (HAS_PCH_CPT(dev))
3923                                 lvds |= PORT_TRANS_B_SEL_CPT;
3924                         else
3925                                 lvds |= LVDS_PIPEB_SELECT;
3926                 } else {
3927                         if (HAS_PCH_CPT(dev))
3928                                 lvds &= ~PORT_TRANS_SEL_MASK;
3929                         else
3930                                 lvds &= ~LVDS_PIPEB_SELECT;
3931                 }
3932                 /* set the corresponsding LVDS_BORDER bit */
3933                 lvds |= dev_priv->lvds_border_bits;
3934                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3935                  * set the DPLLs for dual-channel mode or not.
3936                  */
3937                 if (clock.p2 == 7)
3938                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3939                 else
3940                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3941
3942                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3943                  * appropriately here, but we need to look more thoroughly into how
3944                  * panels behave in the two modes.
3945                  */
3946                 /* set the dithering flag on non-PCH LVDS as needed */
3947                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3948                         if (dev_priv->lvds_dither)
3949                                 lvds |= LVDS_ENABLE_DITHER;
3950                         else
3951                                 lvds &= ~LVDS_ENABLE_DITHER;
3952                 }
3953                 I915_WRITE(lvds_reg, lvds);
3954                 I915_READ(lvds_reg);
3955         }
3956
3957         /* set the dithering flag and clear for anything other than a panel. */
3958         if (HAS_PCH_SPLIT(dev)) {
3959                 pipeconf &= ~PIPECONF_DITHER_EN;
3960                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3961                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3962                         pipeconf |= PIPECONF_DITHER_EN;
3963                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3964                 }
3965         }
3966
3967         if (is_dp)
3968                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3969         else if (HAS_PCH_SPLIT(dev)) {
3970                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3971                 if (pipe == 0) {
3972                         I915_WRITE(TRANSA_DATA_M1, 0);
3973                         I915_WRITE(TRANSA_DATA_N1, 0);
3974                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3975                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3976                 } else {
3977                         I915_WRITE(TRANSB_DATA_M1, 0);
3978                         I915_WRITE(TRANSB_DATA_N1, 0);
3979                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3980                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3981                 }
3982         }
3983
3984         if (!has_edp_encoder) {
3985                 I915_WRITE(fp_reg, fp);
3986                 I915_WRITE(dpll_reg, dpll);
3987                 I915_READ(dpll_reg);
3988                 /* Wait for the clocks to stabilize. */
3989                 udelay(150);
3990
3991                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3992                         if (is_sdvo) {
3993                                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3994                                 if (pixel_multiplier > 1)
3995                                         pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3996                                 else
3997                                         pixel_multiplier = 0;
3998
3999                                 I915_WRITE(dpll_md_reg,
4000                                            (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4001                                            pixel_multiplier);
4002                         } else
4003                                 I915_WRITE(dpll_md_reg, 0);
4004                 } else {
4005                         /* write it again -- the BIOS does, after all */
4006                         I915_WRITE(dpll_reg, dpll);
4007                 }
4008                 I915_READ(dpll_reg);
4009                 /* Wait for the clocks to stabilize. */
4010                 udelay(150);
4011         }
4012
4013         if (is_lvds && has_reduced_clock && i915_powersave) {
4014                 I915_WRITE(fp_reg + 4, fp2);
4015                 intel_crtc->lowfreq_avail = true;
4016                 if (HAS_PIPE_CXSR(dev)) {
4017                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4018                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4019                 }
4020         } else {
4021                 I915_WRITE(fp_reg + 4, fp);
4022                 intel_crtc->lowfreq_avail = false;
4023                 if (HAS_PIPE_CXSR(dev)) {
4024                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4025                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4026                 }
4027         }
4028
4029         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4030                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4031                 /* the chip adds 2 halflines automatically */
4032                 adjusted_mode->crtc_vdisplay -= 1;
4033                 adjusted_mode->crtc_vtotal -= 1;
4034                 adjusted_mode->crtc_vblank_start -= 1;
4035                 adjusted_mode->crtc_vblank_end -= 1;
4036                 adjusted_mode->crtc_vsync_end -= 1;
4037                 adjusted_mode->crtc_vsync_start -= 1;
4038         } else
4039                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4040
4041         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4042                    ((adjusted_mode->crtc_htotal - 1) << 16));
4043         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4044                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4045         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4046                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4047         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4048                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4049         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4050                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4051         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4052                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4053         /* pipesrc and dspsize control the size that is scaled from, which should
4054          * always be the user's requested size.
4055          */
4056         if (!HAS_PCH_SPLIT(dev)) {
4057                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4058                                 (mode->hdisplay - 1));
4059                 I915_WRITE(dsppos_reg, 0);
4060         }
4061         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4062
4063         if (HAS_PCH_SPLIT(dev)) {
4064                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4065                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4066                 I915_WRITE(link_m1_reg, m_n.link_m);
4067                 I915_WRITE(link_n1_reg, m_n.link_n);
4068
4069                 if (has_edp_encoder) {
4070                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4071                 } else {
4072                         /* enable FDI RX PLL too */
4073                         temp = I915_READ(fdi_rx_reg);
4074                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4075                         I915_READ(fdi_rx_reg);
4076                         udelay(200);
4077
4078                         /* enable FDI TX PLL too */
4079                         temp = I915_READ(fdi_tx_reg);
4080                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4081                         I915_READ(fdi_tx_reg);
4082
4083                         /* enable FDI RX PCDCLK */
4084                         temp = I915_READ(fdi_rx_reg);
4085                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4086                         I915_READ(fdi_rx_reg);
4087                         udelay(200);
4088                 }
4089         }
4090
4091         I915_WRITE(pipeconf_reg, pipeconf);
4092         I915_READ(pipeconf_reg);
4093
4094         intel_wait_for_vblank(dev, pipe);
4095
4096         if (IS_IRONLAKE(dev)) {
4097                 /* enable address swizzle for tiling buffer */
4098                 temp = I915_READ(DISP_ARB_CTL);
4099                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4100         }
4101
4102         I915_WRITE(dspcntr_reg, dspcntr);
4103
4104         /* Flush the plane changes */
4105         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4106
4107         intel_update_watermarks(dev);
4108
4109         drm_vblank_post_modeset(dev, pipe);
4110
4111         return ret;
4112 }
4113
4114 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4115 void intel_crtc_load_lut(struct drm_crtc *crtc)
4116 {
4117         struct drm_device *dev = crtc->dev;
4118         struct drm_i915_private *dev_priv = dev->dev_private;
4119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4120         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4121         int i;
4122
4123         /* The clocks have to be on to load the palette. */
4124         if (!crtc->enabled)
4125                 return;
4126
4127         /* use legacy palette for Ironlake */
4128         if (HAS_PCH_SPLIT(dev))
4129                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4130                                                    LGC_PALETTE_B;
4131
4132         for (i = 0; i < 256; i++) {
4133                 I915_WRITE(palreg + 4 * i,
4134                            (intel_crtc->lut_r[i] << 16) |
4135                            (intel_crtc->lut_g[i] << 8) |
4136                            intel_crtc->lut_b[i]);
4137         }
4138 }
4139
4140 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         bool visible = base != 0;
4146         u32 cntl;
4147
4148         if (intel_crtc->cursor_visible == visible)
4149                 return;
4150
4151         cntl = I915_READ(CURACNTR);
4152         if (visible) {
4153                 /* On these chipsets we can only modify the base whilst
4154                  * the cursor is disabled.
4155                  */
4156                 I915_WRITE(CURABASE, base);
4157
4158                 cntl &= ~(CURSOR_FORMAT_MASK);
4159                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4160                 cntl |= CURSOR_ENABLE |
4161                         CURSOR_GAMMA_ENABLE |
4162                         CURSOR_FORMAT_ARGB;
4163         } else
4164                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4165         I915_WRITE(CURACNTR, cntl);
4166
4167         intel_crtc->cursor_visible = visible;
4168 }
4169
4170 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4171 {
4172         struct drm_device *dev = crtc->dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175         int pipe = intel_crtc->pipe;
4176         bool visible = base != 0;
4177
4178         if (intel_crtc->cursor_visible != visible) {
4179                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4180                 if (base) {
4181                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4182                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4183                         cntl |= pipe << 28; /* Connect to correct pipe */
4184                 } else {
4185                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4186                         cntl |= CURSOR_MODE_DISABLE;
4187                 }
4188                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4189
4190                 intel_crtc->cursor_visible = visible;
4191         }
4192         /* and commit changes on next vblank */
4193         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4194 }
4195
4196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4197 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4198 {
4199         struct drm_device *dev = crtc->dev;
4200         struct drm_i915_private *dev_priv = dev->dev_private;
4201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4202         int pipe = intel_crtc->pipe;
4203         int x = intel_crtc->cursor_x;
4204         int y = intel_crtc->cursor_y;
4205         u32 base, pos;
4206         bool visible;
4207
4208         pos = 0;
4209
4210         if (intel_crtc->cursor_on && crtc->fb) {
4211                 base = intel_crtc->cursor_addr;
4212                 if (x > (int) crtc->fb->width)
4213                         base = 0;
4214
4215                 if (y > (int) crtc->fb->height)
4216                         base = 0;
4217         } else
4218                 base = 0;
4219
4220         if (x < 0) {
4221                 if (x + intel_crtc->cursor_width < 0)
4222                         base = 0;
4223
4224                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4225                 x = -x;
4226         }
4227         pos |= x << CURSOR_X_SHIFT;
4228
4229         if (y < 0) {
4230                 if (y + intel_crtc->cursor_height < 0)
4231                         base = 0;
4232
4233                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4234                 y = -y;
4235         }
4236         pos |= y << CURSOR_Y_SHIFT;
4237
4238         visible = base != 0;
4239         if (!visible && !intel_crtc->cursor_visible)
4240                 return;
4241
4242         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4243         if (IS_845G(dev) || IS_I865G(dev))
4244                 i845_update_cursor(crtc, base);
4245         else
4246                 i9xx_update_cursor(crtc, base);
4247
4248         if (visible)
4249                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4250 }
4251
4252 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4253                                  struct drm_file *file_priv,
4254                                  uint32_t handle,
4255                                  uint32_t width, uint32_t height)
4256 {
4257         struct drm_device *dev = crtc->dev;
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260         struct drm_gem_object *bo;
4261         struct drm_i915_gem_object *obj_priv;
4262         uint32_t addr;
4263         int ret;
4264
4265         DRM_DEBUG_KMS("\n");
4266
4267         /* if we want to turn off the cursor ignore width and height */
4268         if (!handle) {
4269                 DRM_DEBUG_KMS("cursor off\n");
4270                 addr = 0;
4271                 bo = NULL;
4272                 mutex_lock(&dev->struct_mutex);
4273                 goto finish;
4274         }
4275
4276         /* Currently we only support 64x64 cursors */
4277         if (width != 64 || height != 64) {
4278                 DRM_ERROR("we currently only support 64x64 cursors\n");
4279                 return -EINVAL;
4280         }
4281
4282         bo = drm_gem_object_lookup(dev, file_priv, handle);
4283         if (!bo)
4284                 return -ENOENT;
4285
4286         obj_priv = to_intel_bo(bo);
4287
4288         if (bo->size < width * height * 4) {
4289                 DRM_ERROR("buffer is to small\n");
4290                 ret = -ENOMEM;
4291                 goto fail;
4292         }
4293
4294         /* we only need to pin inside GTT if cursor is non-phy */
4295         mutex_lock(&dev->struct_mutex);
4296         if (!dev_priv->info->cursor_needs_physical) {
4297                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4298                 if (ret) {
4299                         DRM_ERROR("failed to pin cursor bo\n");
4300                         goto fail_locked;
4301                 }
4302
4303                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4304                 if (ret) {
4305                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4306                         goto fail_unpin;
4307                 }
4308
4309                 addr = obj_priv->gtt_offset;
4310         } else {
4311                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4312                 ret = i915_gem_attach_phys_object(dev, bo,
4313                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4314                                                   align);
4315                 if (ret) {
4316                         DRM_ERROR("failed to attach phys object\n");
4317                         goto fail_locked;
4318                 }
4319                 addr = obj_priv->phys_obj->handle->busaddr;
4320         }
4321
4322         if (!IS_I9XX(dev))
4323                 I915_WRITE(CURSIZE, (height << 12) | width);
4324
4325  finish:
4326         if (intel_crtc->cursor_bo) {
4327                 if (dev_priv->info->cursor_needs_physical) {
4328                         if (intel_crtc->cursor_bo != bo)
4329                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4330                 } else
4331                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4332                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4333         }
4334
4335         mutex_unlock(&dev->struct_mutex);
4336
4337         intel_crtc->cursor_addr = addr;
4338         intel_crtc->cursor_bo = bo;
4339         intel_crtc->cursor_width = width;
4340         intel_crtc->cursor_height = height;
4341
4342         intel_crtc_update_cursor(crtc);
4343
4344         return 0;
4345 fail_unpin:
4346         i915_gem_object_unpin(bo);
4347 fail_locked:
4348         mutex_unlock(&dev->struct_mutex);
4349 fail:
4350         drm_gem_object_unreference_unlocked(bo);
4351         return ret;
4352 }
4353
4354 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4355 {
4356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357
4358         intel_crtc->cursor_x = x;
4359         intel_crtc->cursor_y = y;
4360
4361         intel_crtc_update_cursor(crtc);
4362
4363         return 0;
4364 }
4365
4366 /** Sets the color ramps on behalf of RandR */
4367 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4368                                  u16 blue, int regno)
4369 {
4370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4371
4372         intel_crtc->lut_r[regno] = red >> 8;
4373         intel_crtc->lut_g[regno] = green >> 8;
4374         intel_crtc->lut_b[regno] = blue >> 8;
4375 }
4376
4377 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4378                              u16 *blue, int regno)
4379 {
4380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4381
4382         *red = intel_crtc->lut_r[regno] << 8;
4383         *green = intel_crtc->lut_g[regno] << 8;
4384         *blue = intel_crtc->lut_b[regno] << 8;
4385 }
4386
4387 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4388                                  u16 *blue, uint32_t start, uint32_t size)
4389 {
4390         int end = (start + size > 256) ? 256 : start + size, i;
4391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392
4393         for (i = start; i < end; i++) {
4394                 intel_crtc->lut_r[i] = red[i] >> 8;
4395                 intel_crtc->lut_g[i] = green[i] >> 8;
4396                 intel_crtc->lut_b[i] = blue[i] >> 8;
4397         }
4398
4399         intel_crtc_load_lut(crtc);
4400 }
4401
4402 /**
4403  * Get a pipe with a simple mode set on it for doing load-based monitor
4404  * detection.
4405  *
4406  * It will be up to the load-detect code to adjust the pipe as appropriate for
4407  * its requirements.  The pipe will be connected to no other encoders.
4408  *
4409  * Currently this code will only succeed if there is a pipe with no encoders
4410  * configured for it.  In the future, it could choose to temporarily disable
4411  * some outputs to free up a pipe for its use.
4412  *
4413  * \return crtc, or NULL if no pipes are available.
4414  */
4415
4416 /* VESA 640x480x72Hz mode to set on the pipe */
4417 static struct drm_display_mode load_detect_mode = {
4418         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4419                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4420 };
4421
4422 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4423                                             struct drm_connector *connector,
4424                                             struct drm_display_mode *mode,
4425                                             int *dpms_mode)
4426 {
4427         struct intel_crtc *intel_crtc;
4428         struct drm_crtc *possible_crtc;
4429         struct drm_crtc *supported_crtc =NULL;
4430         struct drm_encoder *encoder = &intel_encoder->base;
4431         struct drm_crtc *crtc = NULL;
4432         struct drm_device *dev = encoder->dev;
4433         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4434         struct drm_crtc_helper_funcs *crtc_funcs;
4435         int i = -1;
4436
4437         /*
4438          * Algorithm gets a little messy:
4439          *   - if the connector already has an assigned crtc, use it (but make
4440          *     sure it's on first)
4441          *   - try to find the first unused crtc that can drive this connector,
4442          *     and use that if we find one
4443          *   - if there are no unused crtcs available, try to use the first
4444          *     one we found that supports the connector
4445          */
4446
4447         /* See if we already have a CRTC for this connector */
4448         if (encoder->crtc) {
4449                 crtc = encoder->crtc;
4450                 /* Make sure the crtc and connector are running */
4451                 intel_crtc = to_intel_crtc(crtc);
4452                 *dpms_mode = intel_crtc->dpms_mode;
4453                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4454                         crtc_funcs = crtc->helper_private;
4455                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4456                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4457                 }
4458                 return crtc;
4459         }
4460
4461         /* Find an unused one (if possible) */
4462         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4463                 i++;
4464                 if (!(encoder->possible_crtcs & (1 << i)))
4465                         continue;
4466                 if (!possible_crtc->enabled) {
4467                         crtc = possible_crtc;
4468                         break;
4469                 }
4470                 if (!supported_crtc)
4471                         supported_crtc = possible_crtc;
4472         }
4473
4474         /*
4475          * If we didn't find an unused CRTC, don't use any.
4476          */
4477         if (!crtc) {
4478                 return NULL;
4479         }
4480
4481         encoder->crtc = crtc;
4482         connector->encoder = encoder;
4483         intel_encoder->load_detect_temp = true;
4484
4485         intel_crtc = to_intel_crtc(crtc);
4486         *dpms_mode = intel_crtc->dpms_mode;
4487
4488         if (!crtc->enabled) {
4489                 if (!mode)
4490                         mode = &load_detect_mode;
4491                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4492         } else {
4493                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4494                         crtc_funcs = crtc->helper_private;
4495                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4496                 }
4497
4498                 /* Add this connector to the crtc */
4499                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4500                 encoder_funcs->commit(encoder);
4501         }
4502         /* let the connector get through one full cycle before testing */
4503         intel_wait_for_vblank(dev, intel_crtc->pipe);
4504
4505         return crtc;
4506 }
4507
4508 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4509                                     struct drm_connector *connector, int dpms_mode)
4510 {
4511         struct drm_encoder *encoder = &intel_encoder->base;
4512         struct drm_device *dev = encoder->dev;
4513         struct drm_crtc *crtc = encoder->crtc;
4514         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4515         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4516
4517         if (intel_encoder->load_detect_temp) {
4518                 encoder->crtc = NULL;
4519                 connector->encoder = NULL;
4520                 intel_encoder->load_detect_temp = false;
4521                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4522                 drm_helper_disable_unused_functions(dev);
4523         }
4524
4525         /* Switch crtc and encoder back off if necessary */
4526         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4527                 if (encoder->crtc == crtc)
4528                         encoder_funcs->dpms(encoder, dpms_mode);
4529                 crtc_funcs->dpms(crtc, dpms_mode);
4530         }
4531 }
4532
4533 /* Returns the clock of the currently programmed mode of the given pipe. */
4534 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4535 {
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538         int pipe = intel_crtc->pipe;
4539         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4540         u32 fp;
4541         intel_clock_t clock;
4542
4543         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4544                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4545         else
4546                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4547
4548         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4549         if (IS_PINEVIEW(dev)) {
4550                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4551                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4552         } else {
4553                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4554                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4555         }
4556
4557         if (IS_I9XX(dev)) {
4558                 if (IS_PINEVIEW(dev))
4559                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4560                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4561                 else
4562                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4563                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4564
4565                 switch (dpll & DPLL_MODE_MASK) {
4566                 case DPLLB_MODE_DAC_SERIAL:
4567                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4568                                 5 : 10;
4569                         break;
4570                 case DPLLB_MODE_LVDS:
4571                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4572                                 7 : 14;
4573                         break;
4574                 default:
4575                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4576                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4577                         return 0;
4578                 }
4579
4580                 /* XXX: Handle the 100Mhz refclk */
4581                 intel_clock(dev, 96000, &clock);
4582         } else {
4583                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4584
4585                 if (is_lvds) {
4586                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4587                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4588                         clock.p2 = 14;
4589
4590                         if ((dpll & PLL_REF_INPUT_MASK) ==
4591                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4592                                 /* XXX: might not be 66MHz */
4593                                 intel_clock(dev, 66000, &clock);
4594                         } else
4595                                 intel_clock(dev, 48000, &clock);
4596                 } else {
4597                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4598                                 clock.p1 = 2;
4599                         else {
4600                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4601                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4602                         }
4603                         if (dpll & PLL_P2_DIVIDE_BY_4)
4604                                 clock.p2 = 4;
4605                         else
4606                                 clock.p2 = 2;
4607
4608                         intel_clock(dev, 48000, &clock);
4609                 }
4610         }
4611
4612         /* XXX: It would be nice to validate the clocks, but we can't reuse
4613          * i830PllIsValid() because it relies on the xf86_config connector
4614          * configuration being accurate, which it isn't necessarily.
4615          */
4616
4617         return clock.dot;
4618 }
4619
4620 /** Returns the currently programmed mode of the given pipe. */
4621 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4622                                              struct drm_crtc *crtc)
4623 {
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         int pipe = intel_crtc->pipe;
4627         struct drm_display_mode *mode;
4628         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4629         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4630         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4631         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4632
4633         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4634         if (!mode)
4635                 return NULL;
4636
4637         mode->clock = intel_crtc_clock_get(dev, crtc);
4638         mode->hdisplay = (htot & 0xffff) + 1;
4639         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4640         mode->hsync_start = (hsync & 0xffff) + 1;
4641         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4642         mode->vdisplay = (vtot & 0xffff) + 1;
4643         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4644         mode->vsync_start = (vsync & 0xffff) + 1;
4645         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4646
4647         drm_mode_set_name(mode);
4648         drm_mode_set_crtcinfo(mode, 0);
4649
4650         return mode;
4651 }
4652
4653 #define GPU_IDLE_TIMEOUT 500 /* ms */
4654
4655 /* When this timer fires, we've been idle for awhile */
4656 static void intel_gpu_idle_timer(unsigned long arg)
4657 {
4658         struct drm_device *dev = (struct drm_device *)arg;
4659         drm_i915_private_t *dev_priv = dev->dev_private;
4660
4661         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4662
4663         dev_priv->busy = false;
4664
4665         queue_work(dev_priv->wq, &dev_priv->idle_work);
4666 }
4667
4668 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4669
4670 static void intel_crtc_idle_timer(unsigned long arg)
4671 {
4672         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4673         struct drm_crtc *crtc = &intel_crtc->base;
4674         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4675
4676         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4677
4678         intel_crtc->busy = false;
4679
4680         queue_work(dev_priv->wq, &dev_priv->idle_work);
4681 }
4682
4683 static void intel_increase_pllclock(struct drm_crtc *crtc)
4684 {
4685         struct drm_device *dev = crtc->dev;
4686         drm_i915_private_t *dev_priv = dev->dev_private;
4687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4688         int pipe = intel_crtc->pipe;
4689         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4690         int dpll = I915_READ(dpll_reg);
4691
4692         if (HAS_PCH_SPLIT(dev))
4693                 return;
4694
4695         if (!dev_priv->lvds_downclock_avail)
4696                 return;
4697
4698         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4699                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4700
4701                 /* Unlock panel regs */
4702                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4703                            PANEL_UNLOCK_REGS);
4704
4705                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4706                 I915_WRITE(dpll_reg, dpll);
4707                 dpll = I915_READ(dpll_reg);
4708                 intel_wait_for_vblank(dev, pipe);
4709                 dpll = I915_READ(dpll_reg);
4710                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4711                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4712
4713                 /* ...and lock them again */
4714                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4715         }
4716
4717         /* Schedule downclock */
4718         mod_timer(&intel_crtc->idle_timer, jiffies +
4719                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4720 }
4721
4722 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4723 {
4724         struct drm_device *dev = crtc->dev;
4725         drm_i915_private_t *dev_priv = dev->dev_private;
4726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4727         int pipe = intel_crtc->pipe;
4728         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4729         int dpll = I915_READ(dpll_reg);
4730
4731         if (HAS_PCH_SPLIT(dev))
4732                 return;
4733
4734         if (!dev_priv->lvds_downclock_avail)
4735                 return;
4736
4737         /*
4738          * Since this is called by a timer, we should never get here in
4739          * the manual case.
4740          */
4741         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4742                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4743
4744                 /* Unlock panel regs */
4745                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4746                            PANEL_UNLOCK_REGS);
4747
4748                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4749                 I915_WRITE(dpll_reg, dpll);
4750                 dpll = I915_READ(dpll_reg);
4751                 intel_wait_for_vblank(dev, pipe);
4752                 dpll = I915_READ(dpll_reg);
4753                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4754                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4755
4756                 /* ...and lock them again */
4757                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4758         }
4759
4760 }
4761
4762 /**
4763  * intel_idle_update - adjust clocks for idleness
4764  * @work: work struct
4765  *
4766  * Either the GPU or display (or both) went idle.  Check the busy status
4767  * here and adjust the CRTC and GPU clocks as necessary.
4768  */
4769 static void intel_idle_update(struct work_struct *work)
4770 {
4771         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4772                                                     idle_work);
4773         struct drm_device *dev = dev_priv->dev;
4774         struct drm_crtc *crtc;
4775         struct intel_crtc *intel_crtc;
4776         int enabled = 0;
4777
4778         if (!i915_powersave)
4779                 return;
4780
4781         mutex_lock(&dev->struct_mutex);
4782
4783         i915_update_gfx_val(dev_priv);
4784
4785         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4786                 /* Skip inactive CRTCs */
4787                 if (!crtc->fb)
4788                         continue;
4789
4790                 enabled++;
4791                 intel_crtc = to_intel_crtc(crtc);
4792                 if (!intel_crtc->busy)
4793                         intel_decrease_pllclock(crtc);
4794         }
4795
4796         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4797                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4798                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4799         }
4800
4801         mutex_unlock(&dev->struct_mutex);
4802 }
4803
4804 /**
4805  * intel_mark_busy - mark the GPU and possibly the display busy
4806  * @dev: drm device
4807  * @obj: object we're operating on
4808  *
4809  * Callers can use this function to indicate that the GPU is busy processing
4810  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4811  * buffer), we'll also mark the display as busy, so we know to increase its
4812  * clock frequency.
4813  */
4814 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4815 {
4816         drm_i915_private_t *dev_priv = dev->dev_private;
4817         struct drm_crtc *crtc = NULL;
4818         struct intel_framebuffer *intel_fb;
4819         struct intel_crtc *intel_crtc;
4820
4821         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4822                 return;
4823
4824         if (!dev_priv->busy) {
4825                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4826                         u32 fw_blc_self;
4827
4828                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4829                         fw_blc_self = I915_READ(FW_BLC_SELF);
4830                         fw_blc_self &= ~FW_BLC_SELF_EN;
4831                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4832                 }
4833                 dev_priv->busy = true;
4834         } else
4835                 mod_timer(&dev_priv->idle_timer, jiffies +
4836                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4837
4838         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4839                 if (!crtc->fb)
4840                         continue;
4841
4842                 intel_crtc = to_intel_crtc(crtc);
4843                 intel_fb = to_intel_framebuffer(crtc->fb);
4844                 if (intel_fb->obj == obj) {
4845                         if (!intel_crtc->busy) {
4846                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4847                                         u32 fw_blc_self;
4848
4849                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4850                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4851                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4852                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4853                                 }
4854                                 /* Non-busy -> busy, upclock */
4855                                 intel_increase_pllclock(crtc);
4856                                 intel_crtc->busy = true;
4857                         } else {
4858                                 /* Busy -> busy, put off timer */
4859                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4860                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4861                         }
4862                 }
4863         }
4864 }
4865
4866 static void intel_crtc_destroy(struct drm_crtc *crtc)
4867 {
4868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4869         struct drm_device *dev = crtc->dev;
4870         struct intel_unpin_work *work;
4871         unsigned long flags;
4872
4873         spin_lock_irqsave(&dev->event_lock, flags);
4874         work = intel_crtc->unpin_work;
4875         intel_crtc->unpin_work = NULL;
4876         spin_unlock_irqrestore(&dev->event_lock, flags);
4877
4878         if (work) {
4879                 cancel_work_sync(&work->work);
4880                 kfree(work);
4881         }
4882
4883         drm_crtc_cleanup(crtc);
4884
4885         kfree(intel_crtc);
4886 }
4887
4888 static void intel_unpin_work_fn(struct work_struct *__work)
4889 {
4890         struct intel_unpin_work *work =
4891                 container_of(__work, struct intel_unpin_work, work);
4892
4893         mutex_lock(&work->dev->struct_mutex);
4894         i915_gem_object_unpin(work->old_fb_obj);
4895         drm_gem_object_unreference(work->pending_flip_obj);
4896         drm_gem_object_unreference(work->old_fb_obj);
4897         mutex_unlock(&work->dev->struct_mutex);
4898         kfree(work);
4899 }
4900
4901 static void do_intel_finish_page_flip(struct drm_device *dev,
4902                                       struct drm_crtc *crtc)
4903 {
4904         drm_i915_private_t *dev_priv = dev->dev_private;
4905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4906         struct intel_unpin_work *work;
4907         struct drm_i915_gem_object *obj_priv;
4908         struct drm_pending_vblank_event *e;
4909         struct timeval now;
4910         unsigned long flags;
4911
4912         /* Ignore early vblank irqs */
4913         if (intel_crtc == NULL)
4914                 return;
4915
4916         spin_lock_irqsave(&dev->event_lock, flags);
4917         work = intel_crtc->unpin_work;
4918         if (work == NULL || !work->pending) {
4919                 spin_unlock_irqrestore(&dev->event_lock, flags);
4920                 return;
4921         }
4922
4923         intel_crtc->unpin_work = NULL;
4924         drm_vblank_put(dev, intel_crtc->pipe);
4925
4926         if (work->event) {
4927                 e = work->event;
4928                 do_gettimeofday(&now);
4929                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4930                 e->event.tv_sec = now.tv_sec;
4931                 e->event.tv_usec = now.tv_usec;
4932                 list_add_tail(&e->base.link,
4933                               &e->base.file_priv->event_list);
4934                 wake_up_interruptible(&e->base.file_priv->event_wait);
4935         }
4936
4937         spin_unlock_irqrestore(&dev->event_lock, flags);
4938
4939         obj_priv = to_intel_bo(work->pending_flip_obj);
4940
4941         /* Initial scanout buffer will have a 0 pending flip count */
4942         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4943             atomic_dec_and_test(&obj_priv->pending_flip))
4944                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4945         schedule_work(&work->work);
4946
4947         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4948 }
4949
4950 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4951 {
4952         drm_i915_private_t *dev_priv = dev->dev_private;
4953         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4954
4955         do_intel_finish_page_flip(dev, crtc);
4956 }
4957
4958 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4959 {
4960         drm_i915_private_t *dev_priv = dev->dev_private;
4961         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4962
4963         do_intel_finish_page_flip(dev, crtc);
4964 }
4965
4966 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4967 {
4968         drm_i915_private_t *dev_priv = dev->dev_private;
4969         struct intel_crtc *intel_crtc =
4970                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4971         unsigned long flags;
4972
4973         spin_lock_irqsave(&dev->event_lock, flags);
4974         if (intel_crtc->unpin_work) {
4975                 if ((++intel_crtc->unpin_work->pending) > 1)
4976                         DRM_ERROR("Prepared flip multiple times\n");
4977         } else {
4978                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4979         }
4980         spin_unlock_irqrestore(&dev->event_lock, flags);
4981 }
4982
4983 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4984                                 struct drm_framebuffer *fb,
4985                                 struct drm_pending_vblank_event *event)
4986 {
4987         struct drm_device *dev = crtc->dev;
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989         struct intel_framebuffer *intel_fb;
4990         struct drm_i915_gem_object *obj_priv;
4991         struct drm_gem_object *obj;
4992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993         struct intel_unpin_work *work;
4994         unsigned long flags, offset;
4995         int pipe = intel_crtc->pipe;
4996         u32 pf, pipesrc;
4997         int ret;
4998
4999         work = kzalloc(sizeof *work, GFP_KERNEL);
5000         if (work == NULL)
5001                 return -ENOMEM;
5002
5003         work->event = event;
5004         work->dev = crtc->dev;
5005         intel_fb = to_intel_framebuffer(crtc->fb);
5006         work->old_fb_obj = intel_fb->obj;
5007         INIT_WORK(&work->work, intel_unpin_work_fn);
5008
5009         /* We borrow the event spin lock for protecting unpin_work */
5010         spin_lock_irqsave(&dev->event_lock, flags);
5011         if (intel_crtc->unpin_work) {
5012                 spin_unlock_irqrestore(&dev->event_lock, flags);
5013                 kfree(work);
5014
5015                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5016                 return -EBUSY;
5017         }
5018         intel_crtc->unpin_work = work;
5019         spin_unlock_irqrestore(&dev->event_lock, flags);
5020
5021         intel_fb = to_intel_framebuffer(fb);
5022         obj = intel_fb->obj;
5023
5024         mutex_lock(&dev->struct_mutex);
5025         ret = intel_pin_and_fence_fb_obj(dev, obj);
5026         if (ret)
5027                 goto cleanup_work;
5028
5029         /* Reference the objects for the scheduled work. */
5030         drm_gem_object_reference(work->old_fb_obj);
5031         drm_gem_object_reference(obj);
5032
5033         crtc->fb = fb;
5034         ret = i915_gem_object_flush_write_domain(obj);
5035         if (ret)
5036                 goto cleanup_objs;
5037
5038         ret = drm_vblank_get(dev, intel_crtc->pipe);
5039         if (ret)
5040                 goto cleanup_objs;
5041
5042         obj_priv = to_intel_bo(obj);
5043         atomic_inc(&obj_priv->pending_flip);
5044         work->pending_flip_obj = obj;
5045
5046         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5047                 u32 flip_mask;
5048
5049                 if (intel_crtc->plane)
5050                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5051                 else
5052                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5053
5054                 BEGIN_LP_RING(2);
5055                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5056                 OUT_RING(0);
5057                 ADVANCE_LP_RING();
5058         }
5059
5060         work->enable_stall_check = true;
5061
5062         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5063         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5064
5065         BEGIN_LP_RING(4);
5066         switch(INTEL_INFO(dev)->gen) {
5067         case 2:
5068                 OUT_RING(MI_DISPLAY_FLIP |
5069                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5070                 OUT_RING(fb->pitch);
5071                 OUT_RING(obj_priv->gtt_offset + offset);
5072                 OUT_RING(MI_NOOP);
5073                 break;
5074
5075         case 3:
5076                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5077                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5078                 OUT_RING(fb->pitch);
5079                 OUT_RING(obj_priv->gtt_offset + offset);
5080                 OUT_RING(MI_NOOP);
5081                 break;
5082
5083         case 4:
5084         case 5:
5085                 /* i965+ uses the linear or tiled offsets from the
5086                  * Display Registers (which do not change across a page-flip)
5087                  * so we need only reprogram the base address.
5088                  */
5089                 OUT_RING(MI_DISPLAY_FLIP |
5090                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5091                 OUT_RING(fb->pitch);
5092                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5093
5094                 /* XXX Enabling the panel-fitter across page-flip is so far
5095                  * untested on non-native modes, so ignore it for now.
5096                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5097                  */
5098                 pf = 0;
5099                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5100                 OUT_RING(pf | pipesrc);
5101                 break;
5102
5103         case 6:
5104                 OUT_RING(MI_DISPLAY_FLIP |
5105                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5106                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5107                 OUT_RING(obj_priv->gtt_offset);
5108
5109                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5110                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5111                 OUT_RING(pf | pipesrc);
5112                 break;
5113         }
5114         ADVANCE_LP_RING();
5115
5116         mutex_unlock(&dev->struct_mutex);
5117
5118         trace_i915_flip_request(intel_crtc->plane, obj);
5119
5120         return 0;
5121
5122 cleanup_objs:
5123         drm_gem_object_unreference(work->old_fb_obj);
5124         drm_gem_object_unreference(obj);
5125 cleanup_work:
5126         mutex_unlock(&dev->struct_mutex);
5127
5128         spin_lock_irqsave(&dev->event_lock, flags);
5129         intel_crtc->unpin_work = NULL;
5130         spin_unlock_irqrestore(&dev->event_lock, flags);
5131
5132         kfree(work);
5133
5134         return ret;
5135 }
5136
5137 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5138         .dpms = intel_crtc_dpms,
5139         .mode_fixup = intel_crtc_mode_fixup,
5140         .mode_set = intel_crtc_mode_set,
5141         .mode_set_base = intel_pipe_set_base,
5142         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5143         .prepare = intel_crtc_prepare,
5144         .commit = intel_crtc_commit,
5145         .load_lut = intel_crtc_load_lut,
5146 };
5147
5148 static const struct drm_crtc_funcs intel_crtc_funcs = {
5149         .cursor_set = intel_crtc_cursor_set,
5150         .cursor_move = intel_crtc_cursor_move,
5151         .gamma_set = intel_crtc_gamma_set,
5152         .set_config = drm_crtc_helper_set_config,
5153         .destroy = intel_crtc_destroy,
5154         .page_flip = intel_crtc_page_flip,
5155 };
5156
5157
5158 static void intel_crtc_init(struct drm_device *dev, int pipe)
5159 {
5160         drm_i915_private_t *dev_priv = dev->dev_private;
5161         struct intel_crtc *intel_crtc;
5162         int i;
5163
5164         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5165         if (intel_crtc == NULL)
5166                 return;
5167
5168         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5169
5170         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5171         intel_crtc->pipe = pipe;
5172         intel_crtc->plane = pipe;
5173         for (i = 0; i < 256; i++) {
5174                 intel_crtc->lut_r[i] = i;
5175                 intel_crtc->lut_g[i] = i;
5176                 intel_crtc->lut_b[i] = i;
5177         }
5178
5179         /* Swap pipes & planes for FBC on pre-965 */
5180         intel_crtc->pipe = pipe;
5181         intel_crtc->plane = pipe;
5182         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5183                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5184                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5185         }
5186
5187         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5188                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5189         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5190         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5191
5192         intel_crtc->cursor_addr = 0;
5193         intel_crtc->dpms_mode = -1;
5194         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5195
5196         intel_crtc->busy = false;
5197
5198         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5199                     (unsigned long)intel_crtc);
5200 }
5201
5202 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5203                                 struct drm_file *file_priv)
5204 {
5205         drm_i915_private_t *dev_priv = dev->dev_private;
5206         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5207         struct drm_mode_object *drmmode_obj;
5208         struct intel_crtc *crtc;
5209
5210         if (!dev_priv) {
5211                 DRM_ERROR("called with no initialization\n");
5212                 return -EINVAL;
5213         }
5214
5215         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5216                         DRM_MODE_OBJECT_CRTC);
5217
5218         if (!drmmode_obj) {
5219                 DRM_ERROR("no such CRTC id\n");
5220                 return -EINVAL;
5221         }
5222
5223         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5224         pipe_from_crtc_id->pipe = crtc->pipe;
5225
5226         return 0;
5227 }
5228
5229 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5230 {
5231         struct intel_encoder *encoder;
5232         int index_mask = 0;
5233         int entry = 0;
5234
5235         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5236                 if (type_mask & encoder->clone_mask)
5237                         index_mask |= (1 << entry);
5238                 entry++;
5239         }
5240
5241         return index_mask;
5242 }
5243
5244 static void intel_setup_outputs(struct drm_device *dev)
5245 {
5246         struct drm_i915_private *dev_priv = dev->dev_private;
5247         struct intel_encoder *encoder;
5248         bool dpd_is_edp = false;
5249
5250         if (IS_MOBILE(dev) && !IS_I830(dev))
5251                 intel_lvds_init(dev);
5252
5253         if (HAS_PCH_SPLIT(dev)) {
5254                 dpd_is_edp = intel_dpd_is_edp(dev);
5255
5256                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5257                         intel_dp_init(dev, DP_A);
5258
5259                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5260                         intel_dp_init(dev, PCH_DP_D);
5261         }
5262
5263         intel_crt_init(dev);
5264
5265         if (HAS_PCH_SPLIT(dev)) {
5266                 int found;
5267
5268                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5269                         /* PCH SDVOB multiplex with HDMIB */
5270                         found = intel_sdvo_init(dev, PCH_SDVOB);
5271                         if (!found)
5272                                 intel_hdmi_init(dev, HDMIB);
5273                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5274                                 intel_dp_init(dev, PCH_DP_B);
5275                 }
5276
5277                 if (I915_READ(HDMIC) & PORT_DETECTED)
5278                         intel_hdmi_init(dev, HDMIC);
5279
5280                 if (I915_READ(HDMID) & PORT_DETECTED)
5281                         intel_hdmi_init(dev, HDMID);
5282
5283                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5284                         intel_dp_init(dev, PCH_DP_C);
5285
5286                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5287                         intel_dp_init(dev, PCH_DP_D);
5288
5289         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5290                 bool found = false;
5291
5292                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5293                         DRM_DEBUG_KMS("probing SDVOB\n");
5294                         found = intel_sdvo_init(dev, SDVOB);
5295                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5296                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5297                                 intel_hdmi_init(dev, SDVOB);
5298                         }
5299
5300                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5301                                 DRM_DEBUG_KMS("probing DP_B\n");
5302                                 intel_dp_init(dev, DP_B);
5303                         }
5304                 }
5305
5306                 /* Before G4X SDVOC doesn't have its own detect register */
5307
5308                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5309                         DRM_DEBUG_KMS("probing SDVOC\n");
5310                         found = intel_sdvo_init(dev, SDVOC);
5311                 }
5312
5313                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5314
5315                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5316                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5317                                 intel_hdmi_init(dev, SDVOC);
5318                         }
5319                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5320                                 DRM_DEBUG_KMS("probing DP_C\n");
5321                                 intel_dp_init(dev, DP_C);
5322                         }
5323                 }
5324
5325                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5326                     (I915_READ(DP_D) & DP_DETECTED)) {
5327                         DRM_DEBUG_KMS("probing DP_D\n");
5328                         intel_dp_init(dev, DP_D);
5329                 }
5330         } else if (IS_GEN2(dev))
5331                 intel_dvo_init(dev);
5332
5333         if (SUPPORTS_TV(dev))
5334                 intel_tv_init(dev);
5335
5336         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5337                 encoder->base.possible_crtcs = encoder->crtc_mask;
5338                 encoder->base.possible_clones =
5339                         intel_encoder_clones(dev, encoder->clone_mask);
5340         }
5341 }
5342
5343 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5344 {
5345         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5346
5347         drm_framebuffer_cleanup(fb);
5348         drm_gem_object_unreference_unlocked(intel_fb->obj);
5349
5350         kfree(intel_fb);
5351 }
5352
5353 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5354                                                 struct drm_file *file_priv,
5355                                                 unsigned int *handle)
5356 {
5357         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5358         struct drm_gem_object *object = intel_fb->obj;
5359
5360         return drm_gem_handle_create(file_priv, object, handle);
5361 }
5362
5363 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5364         .destroy = intel_user_framebuffer_destroy,
5365         .create_handle = intel_user_framebuffer_create_handle,
5366 };
5367
5368 int intel_framebuffer_init(struct drm_device *dev,
5369                            struct intel_framebuffer *intel_fb,
5370                            struct drm_mode_fb_cmd *mode_cmd,
5371                            struct drm_gem_object *obj)
5372 {
5373         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5374         int ret;
5375
5376         if (obj_priv->tiling_mode == I915_TILING_Y)
5377                 return -EINVAL;
5378
5379         if (mode_cmd->pitch & 63)
5380                 return -EINVAL;
5381
5382         switch (mode_cmd->bpp) {
5383         case 8:
5384         case 16:
5385         case 24:
5386         case 32:
5387                 break;
5388         default:
5389                 return -EINVAL;
5390         }
5391
5392         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5393         if (ret) {
5394                 DRM_ERROR("framebuffer init failed %d\n", ret);
5395                 return ret;
5396         }
5397
5398         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5399         intel_fb->obj = obj;
5400         return 0;
5401 }
5402
5403 static struct drm_framebuffer *
5404 intel_user_framebuffer_create(struct drm_device *dev,
5405                               struct drm_file *filp,
5406                               struct drm_mode_fb_cmd *mode_cmd)
5407 {
5408         struct drm_gem_object *obj;
5409         struct intel_framebuffer *intel_fb;
5410         int ret;
5411
5412         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5413         if (!obj)
5414                 return ERR_PTR(-ENOENT);
5415
5416         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5417         if (!intel_fb)
5418                 return ERR_PTR(-ENOMEM);
5419
5420         ret = intel_framebuffer_init(dev, intel_fb,
5421                                      mode_cmd, obj);
5422         if (ret) {
5423                 drm_gem_object_unreference_unlocked(obj);
5424                 kfree(intel_fb);
5425                 return ERR_PTR(ret);
5426         }
5427
5428         return &intel_fb->base;
5429 }
5430
5431 static const struct drm_mode_config_funcs intel_mode_funcs = {
5432         .fb_create = intel_user_framebuffer_create,
5433         .output_poll_changed = intel_fb_output_poll_changed,
5434 };
5435
5436 static struct drm_gem_object *
5437 intel_alloc_context_page(struct drm_device *dev)
5438 {
5439         struct drm_gem_object *ctx;
5440         int ret;
5441
5442         ctx = i915_gem_alloc_object(dev, 4096);
5443         if (!ctx) {
5444                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5445                 return NULL;
5446         }
5447
5448         mutex_lock(&dev->struct_mutex);
5449         ret = i915_gem_object_pin(ctx, 4096);
5450         if (ret) {
5451                 DRM_ERROR("failed to pin power context: %d\n", ret);
5452                 goto err_unref;
5453         }
5454
5455         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5456         if (ret) {
5457                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5458                 goto err_unpin;
5459         }
5460         mutex_unlock(&dev->struct_mutex);
5461
5462         return ctx;
5463
5464 err_unpin:
5465         i915_gem_object_unpin(ctx);
5466 err_unref:
5467         drm_gem_object_unreference(ctx);
5468         mutex_unlock(&dev->struct_mutex);
5469         return NULL;
5470 }
5471
5472 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5473 {
5474         struct drm_i915_private *dev_priv = dev->dev_private;
5475         u16 rgvswctl;
5476
5477         rgvswctl = I915_READ16(MEMSWCTL);
5478         if (rgvswctl & MEMCTL_CMD_STS) {
5479                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5480                 return false; /* still busy with another command */
5481         }
5482
5483         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5484                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5485         I915_WRITE16(MEMSWCTL, rgvswctl);
5486         POSTING_READ16(MEMSWCTL);
5487
5488         rgvswctl |= MEMCTL_CMD_STS;
5489         I915_WRITE16(MEMSWCTL, rgvswctl);
5490
5491         return true;
5492 }
5493
5494 void ironlake_enable_drps(struct drm_device *dev)
5495 {
5496         struct drm_i915_private *dev_priv = dev->dev_private;
5497         u32 rgvmodectl = I915_READ(MEMMODECTL);
5498         u8 fmax, fmin, fstart, vstart;
5499
5500         /* 100ms RC evaluation intervals */
5501         I915_WRITE(RCUPEI, 100000);
5502         I915_WRITE(RCDNEI, 100000);
5503
5504         /* Set max/min thresholds to 90ms and 80ms respectively */
5505         I915_WRITE(RCBMAXAVG, 90000);
5506         I915_WRITE(RCBMINAVG, 80000);
5507
5508         I915_WRITE(MEMIHYST, 1);
5509
5510         /* Set up min, max, and cur for interrupt handling */
5511         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5512         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5513         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5514                 MEMMODE_FSTART_SHIFT;
5515         fstart = fmax;
5516
5517         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5518                 PXVFREQ_PX_SHIFT;
5519
5520         dev_priv->fmax = fstart; /* IPS callback will increase this */
5521         dev_priv->fstart = fstart;
5522
5523         dev_priv->max_delay = fmax;
5524         dev_priv->min_delay = fmin;
5525         dev_priv->cur_delay = fstart;
5526
5527         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5528                          fstart);
5529
5530         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5531
5532         /*
5533          * Interrupts will be enabled in ironlake_irq_postinstall
5534          */
5535
5536         I915_WRITE(VIDSTART, vstart);
5537         POSTING_READ(VIDSTART);
5538
5539         rgvmodectl |= MEMMODE_SWMODE_EN;
5540         I915_WRITE(MEMMODECTL, rgvmodectl);
5541
5542         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5543                 DRM_ERROR("stuck trying to change perf mode\n");
5544         msleep(1);
5545
5546         ironlake_set_drps(dev, fstart);
5547
5548         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5549                 I915_READ(0x112e0);
5550         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5551         dev_priv->last_count2 = I915_READ(0x112f4);
5552         getrawmonotonic(&dev_priv->last_time2);
5553 }
5554
5555 void ironlake_disable_drps(struct drm_device *dev)
5556 {
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         u16 rgvswctl = I915_READ16(MEMSWCTL);
5559
5560         /* Ack interrupts, disable EFC interrupt */
5561         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5562         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5563         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5564         I915_WRITE(DEIIR, DE_PCU_EVENT);
5565         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5566
5567         /* Go back to the starting frequency */
5568         ironlake_set_drps(dev, dev_priv->fstart);
5569         msleep(1);
5570         rgvswctl |= MEMCTL_CMD_STS;
5571         I915_WRITE(MEMSWCTL, rgvswctl);
5572         msleep(1);
5573
5574 }
5575
5576 static unsigned long intel_pxfreq(u32 vidfreq)
5577 {
5578         unsigned long freq;
5579         int div = (vidfreq & 0x3f0000) >> 16;
5580         int post = (vidfreq & 0x3000) >> 12;
5581         int pre = (vidfreq & 0x7);
5582
5583         if (!pre)
5584                 return 0;
5585
5586         freq = ((div * 133333) / ((1<<post) * pre));
5587
5588         return freq;
5589 }
5590
5591 void intel_init_emon(struct drm_device *dev)
5592 {
5593         struct drm_i915_private *dev_priv = dev->dev_private;
5594         u32 lcfuse;
5595         u8 pxw[16];
5596         int i;
5597
5598         /* Disable to program */
5599         I915_WRITE(ECR, 0);
5600         POSTING_READ(ECR);
5601
5602         /* Program energy weights for various events */
5603         I915_WRITE(SDEW, 0x15040d00);
5604         I915_WRITE(CSIEW0, 0x007f0000);
5605         I915_WRITE(CSIEW1, 0x1e220004);
5606         I915_WRITE(CSIEW2, 0x04000004);
5607
5608         for (i = 0; i < 5; i++)
5609                 I915_WRITE(PEW + (i * 4), 0);
5610         for (i = 0; i < 3; i++)
5611                 I915_WRITE(DEW + (i * 4), 0);
5612
5613         /* Program P-state weights to account for frequency power adjustment */
5614         for (i = 0; i < 16; i++) {
5615                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5616                 unsigned long freq = intel_pxfreq(pxvidfreq);
5617                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5618                         PXVFREQ_PX_SHIFT;
5619                 unsigned long val;
5620
5621                 val = vid * vid;
5622                 val *= (freq / 1000);
5623                 val *= 255;
5624                 val /= (127*127*900);
5625                 if (val > 0xff)
5626                         DRM_ERROR("bad pxval: %ld\n", val);
5627                 pxw[i] = val;
5628         }
5629         /* Render standby states get 0 weight */
5630         pxw[14] = 0;
5631         pxw[15] = 0;
5632
5633         for (i = 0; i < 4; i++) {
5634                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5635                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5636                 I915_WRITE(PXW + (i * 4), val);
5637         }
5638
5639         /* Adjust magic regs to magic values (more experimental results) */
5640         I915_WRITE(OGW0, 0);
5641         I915_WRITE(OGW1, 0);
5642         I915_WRITE(EG0, 0x00007f00);
5643         I915_WRITE(EG1, 0x0000000e);
5644         I915_WRITE(EG2, 0x000e0000);
5645         I915_WRITE(EG3, 0x68000300);
5646         I915_WRITE(EG4, 0x42000000);
5647         I915_WRITE(EG5, 0x00140031);
5648         I915_WRITE(EG6, 0);
5649         I915_WRITE(EG7, 0);
5650
5651         for (i = 0; i < 8; i++)
5652                 I915_WRITE(PXWL + (i * 4), 0);
5653
5654         /* Enable PMON + select events */
5655         I915_WRITE(ECR, 0x80000019);
5656
5657         lcfuse = I915_READ(LCFUSE02);
5658
5659         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5660 }
5661
5662 void intel_init_clock_gating(struct drm_device *dev)
5663 {
5664         struct drm_i915_private *dev_priv = dev->dev_private;
5665
5666         /*
5667          * Disable clock gating reported to work incorrectly according to the
5668          * specs, but enable as much else as we can.
5669          */
5670         if (HAS_PCH_SPLIT(dev)) {
5671                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5672
5673                 if (IS_IRONLAKE(dev)) {
5674                         /* Required for FBC */
5675                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5676                         /* Required for CxSR */
5677                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5678
5679                         I915_WRITE(PCH_3DCGDIS0,
5680                                    MARIUNIT_CLOCK_GATE_DISABLE |
5681                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5682                 }
5683
5684                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5685
5686                 /*
5687                  * According to the spec the following bits should be set in
5688                  * order to enable memory self-refresh
5689                  * The bit 22/21 of 0x42004
5690                  * The bit 5 of 0x42020
5691                  * The bit 15 of 0x45000
5692                  */
5693                 if (IS_IRONLAKE(dev)) {
5694                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5695                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5696                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5697                         I915_WRITE(ILK_DSPCLK_GATE,
5698                                         (I915_READ(ILK_DSPCLK_GATE) |
5699                                                 ILK_DPARB_CLK_GATE));
5700                         I915_WRITE(DISP_ARB_CTL,
5701                                         (I915_READ(DISP_ARB_CTL) |
5702                                                 DISP_FBC_WM_DIS));
5703                 }
5704                 /*
5705                  * Based on the document from hardware guys the following bits
5706                  * should be set unconditionally in order to enable FBC.
5707                  * The bit 22 of 0x42000
5708                  * The bit 22 of 0x42004
5709                  * The bit 7,8,9 of 0x42020.
5710                  */
5711                 if (IS_IRONLAKE_M(dev)) {
5712                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5713                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5714                                    ILK_FBCQ_DIS);
5715                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5716                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5717                                    ILK_DPARB_GATE);
5718                         I915_WRITE(ILK_DSPCLK_GATE,
5719                                    I915_READ(ILK_DSPCLK_GATE) |
5720                                    ILK_DPFC_DIS1 |
5721                                    ILK_DPFC_DIS2 |
5722                                    ILK_CLK_FBC);
5723                 }
5724                 return;
5725         } else if (IS_G4X(dev)) {
5726                 uint32_t dspclk_gate;
5727                 I915_WRITE(RENCLK_GATE_D1, 0);
5728                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5729                        GS_UNIT_CLOCK_GATE_DISABLE |
5730                        CL_UNIT_CLOCK_GATE_DISABLE);
5731                 I915_WRITE(RAMCLK_GATE_D, 0);
5732                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5733                         OVRUNIT_CLOCK_GATE_DISABLE |
5734                         OVCUNIT_CLOCK_GATE_DISABLE;
5735                 if (IS_GM45(dev))
5736                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5737                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5738         } else if (IS_I965GM(dev)) {
5739                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5740                 I915_WRITE(RENCLK_GATE_D2, 0);
5741                 I915_WRITE(DSPCLK_GATE_D, 0);
5742                 I915_WRITE(RAMCLK_GATE_D, 0);
5743                 I915_WRITE16(DEUC, 0);
5744         } else if (IS_I965G(dev)) {
5745                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5746                        I965_RCC_CLOCK_GATE_DISABLE |
5747                        I965_RCPB_CLOCK_GATE_DISABLE |
5748                        I965_ISC_CLOCK_GATE_DISABLE |
5749                        I965_FBC_CLOCK_GATE_DISABLE);
5750                 I915_WRITE(RENCLK_GATE_D2, 0);
5751         } else if (IS_I9XX(dev)) {
5752                 u32 dstate = I915_READ(D_STATE);
5753
5754                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5755                         DSTATE_DOT_CLOCK_GATING;
5756                 I915_WRITE(D_STATE, dstate);
5757         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5758                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5759         } else if (IS_I830(dev)) {
5760                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5761         }
5762
5763         /*
5764          * GPU can automatically power down the render unit if given a page
5765          * to save state.
5766          */
5767         if (IS_IRONLAKE_M(dev)) {
5768                 if (dev_priv->renderctx == NULL)
5769                         dev_priv->renderctx = intel_alloc_context_page(dev);
5770                 if (dev_priv->renderctx) {
5771                         struct drm_i915_gem_object *obj_priv;
5772                         obj_priv = to_intel_bo(dev_priv->renderctx);
5773                         if (obj_priv) {
5774                                 BEGIN_LP_RING(4);
5775                                 OUT_RING(MI_SET_CONTEXT);
5776                                 OUT_RING(obj_priv->gtt_offset |
5777                                                 MI_MM_SPACE_GTT |
5778                                                 MI_SAVE_EXT_STATE_EN |
5779                                                 MI_RESTORE_EXT_STATE_EN |
5780                                                 MI_RESTORE_INHIBIT);
5781                                 OUT_RING(MI_NOOP);
5782                                 OUT_RING(MI_FLUSH);
5783                                 ADVANCE_LP_RING();
5784                         }
5785                 } else
5786                         DRM_DEBUG_KMS("Failed to allocate render context."
5787                                        "Disable RC6\n");
5788         }
5789
5790         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5791                 struct drm_i915_gem_object *obj_priv = NULL;
5792
5793                 if (dev_priv->pwrctx) {
5794                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5795                 } else {
5796                         struct drm_gem_object *pwrctx;
5797
5798                         pwrctx = intel_alloc_context_page(dev);
5799                         if (pwrctx) {
5800                                 dev_priv->pwrctx = pwrctx;
5801                                 obj_priv = to_intel_bo(pwrctx);
5802                         }
5803                 }
5804
5805                 if (obj_priv) {
5806                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5807                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5808                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5809                 }
5810         }
5811 }
5812
5813 /* Set up chip specific display functions */
5814 static void intel_init_display(struct drm_device *dev)
5815 {
5816         struct drm_i915_private *dev_priv = dev->dev_private;
5817
5818         /* We always want a DPMS function */
5819         if (HAS_PCH_SPLIT(dev))
5820                 dev_priv->display.dpms = ironlake_crtc_dpms;
5821         else
5822                 dev_priv->display.dpms = i9xx_crtc_dpms;
5823
5824         if (I915_HAS_FBC(dev)) {
5825                 if (IS_IRONLAKE_M(dev)) {
5826                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5827                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5828                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5829                 } else if (IS_GM45(dev)) {
5830                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5831                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5832                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5833                 } else if (IS_I965GM(dev)) {
5834                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5835                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5836                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5837                 }
5838                 /* 855GM needs testing */
5839         }
5840
5841         /* Returns the core display clock speed */
5842         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5843                 dev_priv->display.get_display_clock_speed =
5844                         i945_get_display_clock_speed;
5845         else if (IS_I915G(dev))
5846                 dev_priv->display.get_display_clock_speed =
5847                         i915_get_display_clock_speed;
5848         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5849                 dev_priv->display.get_display_clock_speed =
5850                         i9xx_misc_get_display_clock_speed;
5851         else if (IS_I915GM(dev))
5852                 dev_priv->display.get_display_clock_speed =
5853                         i915gm_get_display_clock_speed;
5854         else if (IS_I865G(dev))
5855                 dev_priv->display.get_display_clock_speed =
5856                         i865_get_display_clock_speed;
5857         else if (IS_I85X(dev))
5858                 dev_priv->display.get_display_clock_speed =
5859                         i855_get_display_clock_speed;
5860         else /* 852, 830 */
5861                 dev_priv->display.get_display_clock_speed =
5862                         i830_get_display_clock_speed;
5863
5864         /* For FIFO watermark updates */
5865         if (HAS_PCH_SPLIT(dev)) {
5866                 if (IS_IRONLAKE(dev)) {
5867                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5868                                 dev_priv->display.update_wm = ironlake_update_wm;
5869                         else {
5870                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5871                                               "Disable CxSR\n");
5872                                 dev_priv->display.update_wm = NULL;
5873                         }
5874                 } else
5875                         dev_priv->display.update_wm = NULL;
5876         } else if (IS_PINEVIEW(dev)) {
5877                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5878                                             dev_priv->is_ddr3,
5879                                             dev_priv->fsb_freq,
5880                                             dev_priv->mem_freq)) {
5881                         DRM_INFO("failed to find known CxSR latency "
5882                                  "(found ddr%s fsb freq %d, mem freq %d), "
5883                                  "disabling CxSR\n",
5884                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5885                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5886                         /* Disable CxSR and never update its watermark again */
5887                         pineview_disable_cxsr(dev);
5888                         dev_priv->display.update_wm = NULL;
5889                 } else
5890                         dev_priv->display.update_wm = pineview_update_wm;
5891         } else if (IS_G4X(dev))
5892                 dev_priv->display.update_wm = g4x_update_wm;
5893         else if (IS_I965G(dev))
5894                 dev_priv->display.update_wm = i965_update_wm;
5895         else if (IS_I9XX(dev)) {
5896                 dev_priv->display.update_wm = i9xx_update_wm;
5897                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5898         } else if (IS_I85X(dev)) {
5899                 dev_priv->display.update_wm = i9xx_update_wm;
5900                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5901         } else {
5902                 dev_priv->display.update_wm = i830_update_wm;
5903                 if (IS_845G(dev))
5904                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5905                 else
5906                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5907         }
5908 }
5909
5910 /*
5911  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5912  * resume, or other times.  This quirk makes sure that's the case for
5913  * affected systems.
5914  */
5915 static void quirk_pipea_force (struct drm_device *dev)
5916 {
5917         struct drm_i915_private *dev_priv = dev->dev_private;
5918
5919         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5920         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5921 }
5922
5923 struct intel_quirk {
5924         int device;
5925         int subsystem_vendor;
5926         int subsystem_device;
5927         void (*hook)(struct drm_device *dev);
5928 };
5929
5930 struct intel_quirk intel_quirks[] = {
5931         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5932         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5933         /* HP Mini needs pipe A force quirk (LP: #322104) */
5934         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5935
5936         /* Thinkpad R31 needs pipe A force quirk */
5937         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5938         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5939         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5940
5941         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5942         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5943         /* ThinkPad X40 needs pipe A force quirk */
5944
5945         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5946         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5947
5948         /* 855 & before need to leave pipe A & dpll A up */
5949         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5950         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5951 };
5952
5953 static void intel_init_quirks(struct drm_device *dev)
5954 {
5955         struct pci_dev *d = dev->pdev;
5956         int i;
5957
5958         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5959                 struct intel_quirk *q = &intel_quirks[i];
5960
5961                 if (d->device == q->device &&
5962                     (d->subsystem_vendor == q->subsystem_vendor ||
5963                      q->subsystem_vendor == PCI_ANY_ID) &&
5964                     (d->subsystem_device == q->subsystem_device ||
5965                      q->subsystem_device == PCI_ANY_ID))
5966                         q->hook(dev);
5967         }
5968 }
5969
5970 /* Disable the VGA plane that we never use */
5971 static void i915_disable_vga(struct drm_device *dev)
5972 {
5973         struct drm_i915_private *dev_priv = dev->dev_private;
5974         u8 sr1;
5975         u32 vga_reg;
5976
5977         if (HAS_PCH_SPLIT(dev))
5978                 vga_reg = CPU_VGACNTRL;
5979         else
5980                 vga_reg = VGACNTRL;
5981
5982         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5983         outb(1, VGA_SR_INDEX);
5984         sr1 = inb(VGA_SR_DATA);
5985         outb(sr1 | 1<<5, VGA_SR_DATA);
5986         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5987         udelay(300);
5988
5989         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5990         POSTING_READ(vga_reg);
5991 }
5992
5993 void intel_modeset_init(struct drm_device *dev)
5994 {
5995         struct drm_i915_private *dev_priv = dev->dev_private;
5996         int i;
5997
5998         drm_mode_config_init(dev);
5999
6000         dev->mode_config.min_width = 0;
6001         dev->mode_config.min_height = 0;
6002
6003         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6004
6005         intel_init_quirks(dev);
6006
6007         intel_init_display(dev);
6008
6009         if (IS_I965G(dev)) {
6010                 dev->mode_config.max_width = 8192;
6011                 dev->mode_config.max_height = 8192;
6012         } else if (IS_I9XX(dev)) {
6013                 dev->mode_config.max_width = 4096;
6014                 dev->mode_config.max_height = 4096;
6015         } else {
6016                 dev->mode_config.max_width = 2048;
6017                 dev->mode_config.max_height = 2048;
6018         }
6019
6020         /* set memory base */
6021         if (IS_I9XX(dev))
6022                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6023         else
6024                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6025
6026         if (IS_MOBILE(dev) || IS_I9XX(dev))
6027                 dev_priv->num_pipe = 2;
6028         else
6029                 dev_priv->num_pipe = 1;
6030         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6031                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6032
6033         for (i = 0; i < dev_priv->num_pipe; i++) {
6034                 intel_crtc_init(dev, i);
6035         }
6036
6037         intel_setup_outputs(dev);
6038
6039         intel_init_clock_gating(dev);
6040
6041         /* Just disable it once at startup */
6042         i915_disable_vga(dev);
6043
6044         if (IS_IRONLAKE_M(dev)) {
6045                 ironlake_enable_drps(dev);
6046                 intel_init_emon(dev);
6047         }
6048
6049         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6050         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6051                     (unsigned long)dev);
6052
6053         intel_setup_overlay(dev);
6054 }
6055
6056 void intel_modeset_cleanup(struct drm_device *dev)
6057 {
6058         struct drm_i915_private *dev_priv = dev->dev_private;
6059         struct drm_crtc *crtc;
6060         struct intel_crtc *intel_crtc;
6061
6062         mutex_lock(&dev->struct_mutex);
6063
6064         drm_kms_helper_poll_fini(dev);
6065         intel_fbdev_fini(dev);
6066
6067         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6068                 /* Skip inactive CRTCs */
6069                 if (!crtc->fb)
6070                         continue;
6071
6072                 intel_crtc = to_intel_crtc(crtc);
6073                 intel_increase_pllclock(crtc);
6074         }
6075
6076         if (dev_priv->display.disable_fbc)
6077                 dev_priv->display.disable_fbc(dev);
6078
6079         if (dev_priv->renderctx) {
6080                 struct drm_i915_gem_object *obj_priv;
6081
6082                 obj_priv = to_intel_bo(dev_priv->renderctx);
6083                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6084                 I915_READ(CCID);
6085                 i915_gem_object_unpin(dev_priv->renderctx);
6086                 drm_gem_object_unreference(dev_priv->renderctx);
6087         }
6088
6089         if (dev_priv->pwrctx) {
6090                 struct drm_i915_gem_object *obj_priv;
6091
6092                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6093                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6094                 I915_READ(PWRCTXA);
6095                 i915_gem_object_unpin(dev_priv->pwrctx);
6096                 drm_gem_object_unreference(dev_priv->pwrctx);
6097         }
6098
6099         if (IS_IRONLAKE_M(dev))
6100                 ironlake_disable_drps(dev);
6101
6102         mutex_unlock(&dev->struct_mutex);
6103
6104         /* Disable the irq before mode object teardown, for the irq might
6105          * enqueue unpin/hotplug work. */
6106         drm_irq_uninstall(dev);
6107         cancel_work_sync(&dev_priv->hotplug_work);
6108
6109         /* Shut off idle work before the crtcs get freed. */
6110         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6111                 intel_crtc = to_intel_crtc(crtc);
6112                 del_timer_sync(&intel_crtc->idle_timer);
6113         }
6114         del_timer_sync(&dev_priv->idle_timer);
6115         cancel_work_sync(&dev_priv->idle_work);
6116
6117         drm_mode_config_cleanup(dev);
6118 }
6119
6120 /*
6121  * Return which encoder is currently attached for connector.
6122  */
6123 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6124 {
6125         return &intel_attached_encoder(connector)->base;
6126 }
6127
6128 void intel_connector_attach_encoder(struct intel_connector *connector,
6129                                     struct intel_encoder *encoder)
6130 {
6131         connector->encoder = encoder;
6132         drm_mode_connector_attach_encoder(&connector->base,
6133                                           &encoder->base);
6134 }
6135
6136 /*
6137  * set vga decode state - true == enable VGA decode
6138  */
6139 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6140 {
6141         struct drm_i915_private *dev_priv = dev->dev_private;
6142         u16 gmch_ctrl;
6143
6144         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6145         if (state)
6146                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6147         else
6148                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6149         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6150         return 0;
6151 }