drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include "drmP.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "drm_dp_helper.h"
  40
  41 #include "drm_crtc_helper.h"
  42
  43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  44
  45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  46 static void intel_update_watermarks(struct drm_device *dev);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51     /* given values */
  52     int n;
  53     int m1, m2;
  54     int p1, p2;
  55     /* derived values */
  56     int dot;
  57     int vco;
  58     int m;
  59     int p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63     int min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67     int dot_limit;
  68     int p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75     intel_p2_t      p2;
  76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                       int, int, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *best_clock);
  86 static bool
  87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  88                         int target, int refclk, intel_clock_t *best_clock);
  89
  90 static bool
  91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  92                       int target, int refclk, intel_clock_t *best_clock);
  93 static bool
  94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                            int target, int refclk, intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2,.max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2,.max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 359                                                 int refclk)
 360 {
 361         struct drm_device *dev = crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363         const intel_limit_t *limit;
 364
 365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 367                     LVDS_CLKB_POWER_UP) {
 368                         /* LVDS dual channel */
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_dual_lvds;
 373                 } else {
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_single_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_single_lvds;
 378                 }
 379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 380                         HAS_eDP)
 381                 limit = &intel_limits_ironlake_display_port;
 382         else
 383                 limit = &intel_limits_ironlake_dac;
 384
 385         return limit;
 386 }
 387
 388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 389 {
 390         struct drm_device *dev = crtc->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         const intel_limit_t *limit;
 393
 394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 396                     LVDS_CLKB_POWER_UP)
 397                         /* LVDS with dual channel */
 398                         limit = &intel_limits_g4x_dual_channel_lvds;
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits_g4x_single_channel_lvds;
 402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 404                 limit = &intel_limits_g4x_hdmi;
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 406                 limit = &intel_limits_g4x_sdvo;
 407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 408                 limit = &intel_limits_g4x_display_port;
 409         } else /* The option is for other outputs */
 410                 limit = &intel_limits_i9xx_sdvo;
 411
 412         return limit;
 413 }
 414
 415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         const intel_limit_t *limit;
 419
 420         if (HAS_PCH_SPLIT(dev))
 421                 limit = intel_ironlake_limit(crtc, refclk);
 422         else if (IS_G4X(dev)) {
 423                 limit = intel_g4x_limit(crtc);
 424         } else if (IS_PINEVIEW(dev)) {
 425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 426                         limit = &intel_limits_pineview_lvds;
 427                 else
 428                         limit = &intel_limits_pineview_sdvo;
 429         } else if (!IS_GEN2(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_i9xx_lvds;
 432                 else
 433                         limit = &intel_limits_i9xx_sdvo;
 434         } else {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i8xx_lvds;
 437                 else
 438                         limit = &intel_limits_i8xx_dvo;
 439         }
 440         return limit;
 441 }
 442
 443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 444 static void pineview_clock(int refclk, intel_clock_t *clock)
 445 {
 446         clock->m = clock->m2 + 2;
 447         clock->p = clock->p1 * clock->p2;
 448         clock->vco = refclk * clock->m / clock->n;
 449         clock->dot = clock->vco / clock->p;
 450 }
 451
 452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 453 {
 454         if (IS_PINEVIEW(dev)) {
 455                 pineview_clock(refclk, clock);
 456                 return;
 457         }
 458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 459         clock->p = clock->p1 * clock->p2;
 460         clock->vco = refclk * clock->m / (clock->n + 2);
 461         clock->dot = clock->vco / clock->p;
 462 }
 463
 464 /**
 465  * Returns whether any output on the specified pipe is of the specified type
 466  */
 467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_mode_config *mode_config = &dev->mode_config;
 471         struct intel_encoder *encoder;
 472
 473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 474                 if (encoder->base.crtc == crtc && encoder->type == type)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 481 /**
 482  * Returns whether the given set of divisors are valid for a given refclk with
 483  * the given connectors.
 484  */
 485
 486 static bool intel_PLL_is_valid(struct drm_device *dev,
 487                                const intel_limit_t *limit,
 488                                const intel_clock_t *clock)
 489 {
 490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 491                 INTELPllInvalid ("p1 out of range\n");
 492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 493                 INTELPllInvalid ("p out of range\n");
 494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 495                 INTELPllInvalid ("m2 out of range\n");
 496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 497                 INTELPllInvalid ("m1 out of range\n");
 498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 499                 INTELPllInvalid ("m1 <= m2\n");
 500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 501                 INTELPllInvalid ("m out of range\n");
 502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 503                 INTELPllInvalid ("n out of range\n");
 504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 505                 INTELPllInvalid ("vco out of range\n");
 506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 507          * connector, etc., rather than just a single range.
 508          */
 509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 510                 INTELPllInvalid ("dot out of range\n");
 511
 512         return true;
 513 }
 514
 515 static bool
 516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                     int target, int refclk, intel_clock_t *best_clock)
 518
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         intel_clock_t clock;
 523         int err = target;
 524
 525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 526             (I915_READ(LVDS)) != 0) {
 527                 /*
 528                  * For LVDS, if the panel is on, just rely on its current
 529                  * settings for dual-channel.  We haven't figured out how to
 530                  * reliably set up different single/dual channel state, if we
 531                  * even can.
 532                  */
 533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 534                     LVDS_CLKB_POWER_UP)
 535                         clock.p2 = limit->p2.p2_fast;
 536                 else
 537                         clock.p2 = limit->p2.p2_slow;
 538         } else {
 539                 if (target < limit->p2.dot_limit)
 540                         clock.p2 = limit->p2.p2_slow;
 541                 else
 542                         clock.p2 = limit->p2.p2_fast;
 543         }
 544
 545         memset (best_clock, 0, sizeof (*best_clock));
 546
 547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 548              clock.m1++) {
 549                 for (clock.m2 = limit->m2.min;
 550                      clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in Pineview */
 552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min;
 555                              clock.n <= limit->n.max; clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                         clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561                                         if (!intel_PLL_is_valid(dev, limit,
 562                                                                 &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00585 */
 588         int err_most = (target >> 8) + (target >> 9);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 int lvds_reg;
 593
 594                 if (HAS_PCH_SPLIT(dev))
 595                         lvds_reg = PCH_LVDS;
 596                 else
 597                         lvds_reg = LVDS;
 598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 599                     LVDS_CLKB_POWER_UP)
 600                         clock.p2 = limit->p2.p2_fast;
 601                 else
 602                         clock.p2 = limit->p2.p2_slow;
 603         } else {
 604                 if (target < limit->p2.dot_limit)
 605                         clock.p2 = limit->p2.p2_slow;
 606                 else
 607                         clock.p2 = limit->p2.p2_fast;
 608         }
 609
 610         memset(best_clock, 0, sizeof(*best_clock));
 611         max_n = limit->n.max;
 612         /* based on hardware requirement, prefer smaller n to precision */
 613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 614                 /* based on hardware requirement, prefere larger m1,m2 */
 615                 for (clock.m1 = limit->m1.max;
 616                      clock.m1 >= limit->m1.min; clock.m1--) {
 617                         for (clock.m2 = limit->m2.max;
 618                              clock.m2 >= limit->m2.min; clock.m2--) {
 619                                 for (clock.p1 = limit->p1.max;
 620                                      clock.p1 >= limit->p1.min; clock.p1--) {
 621                                         int this_err;
 622
 623                                         intel_clock(dev, refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err_most) {
 630                                                 *best_clock = clock;
 631                                                 err_most = this_err;
 632                                                 max_n = clock.n;
 633                                                 found = true;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639         return found;
 640 }
 641
 642 static bool
 643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 644                            int target, int refclk, intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648
 649         if (target < 200000) {
 650                 clock.n = 1;
 651                 clock.p1 = 2;
 652                 clock.p2 = 10;
 653                 clock.m1 = 12;
 654                 clock.m2 = 9;
 655         } else {
 656                 clock.n = 2;
 657                 clock.p1 = 1;
 658                 clock.p2 = 10;
 659                 clock.m1 = 14;
 660                 clock.m2 = 8;
 661         }
 662         intel_clock(dev, refclk, &clock);
 663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 664         return true;
 665 }
 666
 667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 668 static bool
 669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                       int target, int refclk, intel_clock_t *best_clock)
 671 {
 672         intel_clock_t clock;
 673         if (target < 200000) {
 674                 clock.p1 = 2;
 675                 clock.p2 = 10;
 676                 clock.n = 2;
 677                 clock.m1 = 23;
 678                 clock.m2 = 8;
 679         } else {
 680                 clock.p1 = 1;
 681                 clock.p2 = 10;
 682                 clock.n = 1;
 683                 clock.m1 = 14;
 684                 clock.m2 = 2;
 685         }
 686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 687         clock.p = (clock.p1 * clock.p2);
 688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 689         clock.vco = 0;
 690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 691         return true;
 692 }
 693
 694 /**
 695  * intel_wait_for_vblank - wait for vblank on a given pipe
 696  * @dev: drm device
 697  * @pipe: pipe to wait for
 698  *
 699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 700  * mode setting code.
 701  */
 702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         int pipestat_reg = PIPESTAT(pipe);
 706
 707         /* Clear existing vblank status. Note this will clear any other
 708          * sticky status fields as well.
 709          *
 710          * This races with i915_driver_irq_handler() with the result
 711          * that either function could miss a vblank event.  Here it is not
 712          * fatal, as we will either wait upon the next vblank interrupt or
 713          * timeout.  Generally speaking intel_wait_for_vblank() is only
 714          * called during modeset at which time the GPU should be idle and
 715          * should *not* be performing page flips and thus not waiting on
 716          * vblanks...
 717          * Currently, the result of us stealing a vblank from the irq
 718          * handler is that a single frame will be skipped during swapbuffers.
 719          */
 720         I915_WRITE(pipestat_reg,
 721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 722
 723         /* Wait for vblank interrupt bit to set */
 724         if (wait_for(I915_READ(pipestat_reg) &
 725                      PIPE_VBLANK_INTERRUPT_STATUS,
 726                      50))
 727                 DRM_DEBUG_KMS("vblank wait timed out\n");
 728 }
 729
 730 /*
 731  * intel_wait_for_pipe_off - wait for pipe to turn off
 732  * @dev: drm device
 733  * @pipe: pipe to wait for
 734  *
 735  * After disabling a pipe, we can't wait for vblank in the usual way,
 736  * spinning on the vblank interrupt status bit, since we won't actually
 737  * see an interrupt when the pipe is disabled.
 738  *
 739  * On Gen4 and above:
 740  *   wait for the pipe register state bit to turn off
 741  *
 742  * Otherwise:
 743  *   wait for the display line value to settle (it usually
 744  *   ends up stopping at the start of the next frame).
 745  *
 746  */
 747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750
 751         if (INTEL_INFO(dev)->gen >= 4) {
 752                 int reg = PIPECONF(pipe);
 753
 754                 /* Wait for the Pipe State to go off */
 755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 756                              100))
 757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 758         } else {
 759                 u32 last_line;
 760                 int reg = PIPEDSL(pipe);
 761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 762
 763                 /* Wait for the display line to settle */
 764                 do {
 765                         last_line = I915_READ(reg) & DSL_LINEMASK;
 766                         mdelay(5);
 767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 768                          time_after(timeout, jiffies));
 769                 if (time_after(jiffies, timeout))
 770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 771         }
 772 }
 773
 774 static const char *state_string(bool enabled)
 775 {
 776         return enabled ? "on" : "off";
 777 }
 778
 779 /* Only for pre-ILK configs */
 780 static void assert_pll(struct drm_i915_private *dev_priv,
 781                        enum pipe pipe, bool state)
 782 {
 783         int reg;
 784         u32 val;
 785         bool cur_state;
 786
 787         reg = DPLL(pipe);
 788         val = I915_READ(reg);
 789         cur_state = !!(val & DPLL_VCO_ENABLE);
 790         WARN(cur_state != state,
 791              "PLL state assertion failure (expected %s, current %s)\n",
 792              state_string(state), state_string(cur_state));
 793 }
 794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 796
 797 /* For ILK+ */
 798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 799                            enum pipe pipe, bool state)
 800 {
 801         int reg;
 802         u32 val;
 803         bool cur_state;
 804
 805         reg = PCH_DPLL(pipe);
 806         val = I915_READ(reg);
 807         cur_state = !!(val & DPLL_VCO_ENABLE);
 808         WARN(cur_state != state,
 809              "PCH PLL state assertion failure (expected %s, current %s)\n",
 810              state_string(state), state_string(cur_state));
 811 }
 812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 814
 815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 816                           enum pipe pipe, bool state)
 817 {
 818         int reg;
 819         u32 val;
 820         bool cur_state;
 821
 822         reg = FDI_TX_CTL(pipe);
 823         val = I915_READ(reg);
 824         cur_state = !!(val & FDI_TX_ENABLE);
 825         WARN(cur_state != state,
 826              "FDI TX state assertion failure (expected %s, current %s)\n",
 827              state_string(state), state_string(cur_state));
 828 }
 829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 831
 832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 833                           enum pipe pipe, bool state)
 834 {
 835         int reg;
 836         u32 val;
 837         bool cur_state;
 838
 839         reg = FDI_RX_CTL(pipe);
 840         val = I915_READ(reg);
 841         cur_state = !!(val & FDI_RX_ENABLE);
 842         WARN(cur_state != state,
 843              "FDI RX state assertion failure (expected %s, current %s)\n",
 844              state_string(state), state_string(cur_state));
 845 }
 846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 848
 849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 850                                       enum pipe pipe)
 851 {
 852         int reg;
 853         u32 val;
 854
 855         /* ILK FDI PLL is always enabled */
 856         if (dev_priv->info->gen == 5)
 857                 return;
 858
 859         reg = FDI_TX_CTL(pipe);
 860         val = I915_READ(reg);
 861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 862 }
 863
 864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 865                                       enum pipe pipe)
 866 {
 867         int reg;
 868         u32 val;
 869
 870         reg = FDI_RX_CTL(pipe);
 871         val = I915_READ(reg);
 872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 873 }
 874
 875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 876                                   enum pipe pipe)
 877 {
 878         int pp_reg, lvds_reg;
 879         u32 val;
 880         enum pipe panel_pipe = PIPE_A;
 881         bool locked = locked;
 882
 883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 884                 pp_reg = PCH_PP_CONTROL;
 885                 lvds_reg = PCH_LVDS;
 886         } else {
 887                 pp_reg = PP_CONTROL;
 888                 lvds_reg = LVDS;
 889         }
 890
 891         val = I915_READ(pp_reg);
 892         if (!(val & PANEL_POWER_ON) ||
 893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 894                 locked = false;
 895
 896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 897                 panel_pipe = PIPE_B;
 898
 899         WARN(panel_pipe == pipe && locked,
 900              "panel assertion failure, pipe %c regs locked\n",
 901              pipe_name(pipe));
 902 }
 903
 904 static void assert_pipe(struct drm_i915_private *dev_priv,
 905                         enum pipe pipe, bool state)
 906 {
 907         int reg;
 908         u32 val;
 909         bool cur_state;
 910
 911         reg = PIPECONF(pipe);
 912         val = I915_READ(reg);
 913         cur_state = !!(val & PIPECONF_ENABLE);
 914         WARN(cur_state != state,
 915              "pipe %c assertion failure (expected %s, current %s)\n",
 916              pipe_name(pipe), state_string(state), state_string(cur_state));
 917 }
 918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 920
 921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 922                                  enum plane plane)
 923 {
 924         int reg;
 925         u32 val;
 926
 927         reg = DSPCNTR(plane);
 928         val = I915_READ(reg);
 929         WARN(!(val & DISPLAY_PLANE_ENABLE),
 930              "plane %c assertion failure, should be active but is disabled\n",
 931              plane_name(plane));
 932 }
 933
 934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 935                                    enum pipe pipe)
 936 {
 937         int reg, i;
 938         u32 val;
 939         int cur_pipe;
 940
 941         /* Planes are fixed to pipes on ILK+ */
 942         if (HAS_PCH_SPLIT(dev_priv->dev))
 943                 return;
 944
 945         /* Need to check both planes against the pipe */
 946         for (i = 0; i < 2; i++) {
 947                 reg = DSPCNTR(i);
 948                 val = I915_READ(reg);
 949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 950                         DISPPLANE_SEL_PIPE_SHIFT;
 951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 953                      plane_name(i), pipe_name(pipe));
 954         }
 955 }
 956
 957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 958 {
 959         u32 val;
 960         bool enabled;
 961
 962         val = I915_READ(PCH_DREF_CONTROL);
 963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 964                             DREF_SUPERSPREAD_SOURCE_MASK));
 965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 966 }
 967
 968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 969                                        enum pipe pipe)
 970 {
 971         int reg;
 972         u32 val;
 973         bool enabled;
 974
 975         reg = TRANSCONF(pipe);
 976         val = I915_READ(reg);
 977         enabled = !!(val & TRANS_ENABLE);
 978         WARN(enabled,
 979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 980              pipe_name(pipe));
 981 }
 982
 983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 984                                    enum pipe pipe, int reg)
 985 {
 986         u32 val = I915_READ(reg);
 987         WARN(DP_PIPE_ENABLED(val, pipe),
 988              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 989              reg, pipe_name(pipe));
 990 }
 991
 992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 993                                      enum pipe pipe, int reg)
 994 {
 995         u32 val = I915_READ(reg);
 996         WARN(HDMI_PIPE_ENABLED(val, pipe),
 997              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 998              reg, pipe_name(pipe));
 999 }
1000
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011         reg = PCH_ADPA;
1012         val = I915_READ(reg);
1013         WARN(ADPA_PIPE_ENABLED(val, pipe),
1014              "PCH VGA enabled on transcoder %c, should be disabled\n",
1015              pipe_name(pipe));
1016
1017         reg = PCH_LVDS;
1018         val = I915_READ(reg);
1019         WARN(LVDS_PIPE_ENABLED(val, pipe),
1020              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1021              pipe_name(pipe));
1022
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026 }
1027
1028 /**
1029  * intel_enable_pll - enable a PLL
1030  * @dev_priv: i915 private structure
1031  * @pipe: pipe PLL to enable
1032  *
1033  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1034  * make sure the PLL reg is writable first though, since the panel write
1035  * protect mechanism may be enabled.
1036  *
1037  * Note!  This is for pre-ILK only.
1038  */
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041         int reg;
1042         u32 val;
1043
1044         /* No really, not for ILK+ */
1045         BUG_ON(dev_priv->info->gen >= 5);
1046
1047         /* PLL is protected by panel, make sure we can write it */
1048         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049                 assert_panel_unlocked(dev_priv, pipe);
1050
1051         reg = DPLL(pipe);
1052         val = I915_READ(reg);
1053         val |= DPLL_VCO_ENABLE;
1054
1055         /* We do this three times for luck */
1056         I915_WRITE(reg, val);
1057         POSTING_READ(reg);
1058         udelay(150); /* wait for warmup */
1059         I915_WRITE(reg, val);
1060         POSTING_READ(reg);
1061         udelay(150); /* wait for warmup */
1062         I915_WRITE(reg, val);
1063         POSTING_READ(reg);
1064         udelay(150); /* wait for warmup */
1065 }
1066
1067 /**
1068  * intel_disable_pll - disable a PLL
1069  * @dev_priv: i915 private structure
1070  * @pipe: pipe PLL to disable
1071  *
1072  * Disable the PLL for @pipe, making sure the pipe is off first.
1073  *
1074  * Note!  This is for pre-ILK only.
1075  */
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077 {
1078         int reg;
1079         u32 val;
1080
1081         /* Don't disable pipe A or pipe A PLLs if needed */
1082         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083                 return;
1084
1085         /* Make sure the pipe isn't still relying on us */
1086         assert_pipe_disabled(dev_priv, pipe);
1087
1088         reg = DPLL(pipe);
1089         val = I915_READ(reg);
1090         val &= ~DPLL_VCO_ENABLE;
1091         I915_WRITE(reg, val);
1092         POSTING_READ(reg);
1093 }
1094
1095 /**
1096  * intel_enable_pch_pll - enable PCH PLL
1097  * @dev_priv: i915 private structure
1098  * @pipe: pipe PLL to enable
1099  *
1100  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101  * drives the transcoder clock.
1102  */
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104                                  enum pipe pipe)
1105 {
1106         int reg;
1107         u32 val;
1108
1109         /* PCH only available on ILK+ */
1110         BUG_ON(dev_priv->info->gen < 5);
1111
1112         /* PCH refclock must be enabled first */
1113         assert_pch_refclk_enabled(dev_priv);
1114
1115         reg = PCH_DPLL(pipe);
1116         val = I915_READ(reg);
1117         val |= DPLL_VCO_ENABLE;
1118         I915_WRITE(reg, val);
1119         POSTING_READ(reg);
1120         udelay(200);
1121 }
1122
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124                                   enum pipe pipe)
1125 {
1126         int reg;
1127         u32 val;
1128
1129         /* PCH only available on ILK+ */
1130         BUG_ON(dev_priv->info->gen < 5);
1131
1132         /* Make sure transcoder isn't still depending on us */
1133         assert_transcoder_disabled(dev_priv, pipe);
1134
1135         reg = PCH_DPLL(pipe);
1136         val = I915_READ(reg);
1137         val &= ~DPLL_VCO_ENABLE;
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(200);
1141 }
1142
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144                                     enum pipe pipe)
1145 {
1146         int reg;
1147         u32 val;
1148
1149         /* PCH only available on ILK+ */
1150         BUG_ON(dev_priv->info->gen < 5);
1151
1152         /* Make sure PCH DPLL is enabled */
1153         assert_pch_pll_enabled(dev_priv, pipe);
1154
1155         /* FDI must be feeding us bits for PCH ports */
1156         assert_fdi_tx_enabled(dev_priv, pipe);
1157         assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159         reg = TRANSCONF(pipe);
1160         val = I915_READ(reg);
1161
1162         if (HAS_PCH_IBX(dev_priv->dev)) {
1163                 /*
1164                  * make the BPC in transcoder be consistent with
1165                  * that in pipeconf reg.
1166                  */
1167                 val &= ~PIPE_BPC_MASK;
1168                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169         }
1170         I915_WRITE(reg, val | TRANS_ENABLE);
1171         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173 }
1174
1175 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176                                      enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         /* FDI relies on the transcoder */
1182         assert_fdi_tx_disabled(dev_priv, pipe);
1183         assert_fdi_rx_disabled(dev_priv, pipe);
1184
1185         /* Ports must be off as well */
1186         assert_pch_ports_disabled(dev_priv, pipe);
1187
1188         reg = TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         val &= ~TRANS_ENABLE;
1191         I915_WRITE(reg, val);
1192         /* wait for PCH transcoder off, transcoder state */
1193         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194                 DRM_ERROR("failed to disable transcoder\n");
1195 }
1196
1197 /**
1198  * intel_enable_pipe - enable a pipe, asserting requirements
1199  * @dev_priv: i915 private structure
1200  * @pipe: pipe to enable
1201  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1202  *
1203  * Enable @pipe, making sure that various hardware specific requirements
1204  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205  *
1206  * @pipe should be %PIPE_A or %PIPE_B.
1207  *
1208  * Will wait until the pipe is actually running (i.e. first vblank) before
1209  * returning.
1210  */
1211 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212                               bool pch_port)
1213 {
1214         int reg;
1215         u32 val;
1216
1217         /*
1218          * A pipe without a PLL won't actually be able to drive bits from
1219          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1220          * need the check.
1221          */
1222         if (!HAS_PCH_SPLIT(dev_priv->dev))
1223                 assert_pll_enabled(dev_priv, pipe);
1224         else {
1225                 if (pch_port) {
1226                         /* if driving the PCH, we need FDI enabled */
1227                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229                 }
1230                 /* FIXME: assert CPU port conditions for SNB+ */
1231         }
1232
1233         reg = PIPECONF(pipe);
1234         val = I915_READ(reg);
1235         if (val & PIPECONF_ENABLE)
1236                 return;
1237
1238         I915_WRITE(reg, val | PIPECONF_ENABLE);
1239         intel_wait_for_vblank(dev_priv->dev, pipe);
1240 }
1241
1242 /**
1243  * intel_disable_pipe - disable a pipe, asserting requirements
1244  * @dev_priv: i915 private structure
1245  * @pipe: pipe to disable
1246  *
1247  * Disable @pipe, making sure that various hardware specific requirements
1248  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249  *
1250  * @pipe should be %PIPE_A or %PIPE_B.
1251  *
1252  * Will wait until the pipe has shut down before returning.
1253  */
1254 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255                                enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val;
1259
1260         /*
1261          * Make sure planes won't keep trying to pump pixels to us,
1262          * or we might hang the display.
1263          */
1264         assert_planes_disabled(dev_priv, pipe);
1265
1266         /* Don't disable pipe A or pipe A PLLs if needed */
1267         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268                 return;
1269
1270         reg = PIPECONF(pipe);
1271         val = I915_READ(reg);
1272         if ((val & PIPECONF_ENABLE) == 0)
1273                 return;
1274
1275         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1276         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277 }
1278
1279 /**
1280  * intel_enable_plane - enable a display plane on a given pipe
1281  * @dev_priv: i915 private structure
1282  * @plane: plane to enable
1283  * @pipe: pipe being fed
1284  *
1285  * Enable @plane on @pipe, making sure that @pipe is running first.
1286  */
1287 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288                                enum plane plane, enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294         assert_pipe_enabled(dev_priv, pipe);
1295
1296         reg = DSPCNTR(plane);
1297         val = I915_READ(reg);
1298         if (val & DISPLAY_PLANE_ENABLE)
1299                 return;
1300
1301         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302         intel_wait_for_vblank(dev_priv->dev, pipe);
1303 }
1304
1305 /*
1306  * Plane regs are double buffered, going from enabled->disabled needs a
1307  * trigger in order to latch.  The display address reg provides this.
1308  */
1309 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310                                       enum plane plane)
1311 {
1312         u32 reg = DSPADDR(plane);
1313         I915_WRITE(reg, I915_READ(reg));
1314 }
1315
1316 /**
1317  * intel_disable_plane - disable a display plane
1318  * @dev_priv: i915 private structure
1319  * @plane: plane to disable
1320  * @pipe: pipe consuming the data
1321  *
1322  * Disable @plane; should be an independent operation.
1323  */
1324 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325                                 enum plane plane, enum pipe pipe)
1326 {
1327         int reg;
1328         u32 val;
1329
1330         reg = DSPCNTR(plane);
1331         val = I915_READ(reg);
1332         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333                 return;
1334
1335         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1336         intel_flush_display_plane(dev_priv, plane);
1337         intel_wait_for_vblank(dev_priv->dev, pipe);
1338 }
1339
1340 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341                            enum pipe pipe, int reg)
1342 {
1343         u32 val = I915_READ(reg);
1344         if (DP_PIPE_ENABLED(val, pipe))
1345                 I915_WRITE(reg, val & ~DP_PORT_EN);
1346 }
1347
1348 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349                              enum pipe pipe, int reg)
1350 {
1351         u32 val = I915_READ(reg);
1352         if (HDMI_PIPE_ENABLED(val, pipe))
1353                 I915_WRITE(reg, val & ~PORT_ENABLE);
1354 }
1355
1356 /* Disable any ports connected to this transcoder */
1357 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358                                     enum pipe pipe)
1359 {
1360         u32 reg, val;
1361
1362         val = I915_READ(PCH_PP_CONTROL);
1363         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369         reg = PCH_ADPA;
1370         val = I915_READ(reg);
1371         if (ADPA_PIPE_ENABLED(val, pipe))
1372                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         if (LVDS_PIPE_ENABLED(val, pipe)) {
1377                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378                 POSTING_READ(reg);
1379                 udelay(100);
1380         }
1381
1382         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384         disable_pch_hdmi(dev_priv, pipe, HDMID);
1385 }
1386
1387 static void i8xx_disable_fbc(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390         u32 fbc_ctl;
1391
1392         /* Disable compression */
1393         fbc_ctl = I915_READ(FBC_CONTROL);
1394         if ((fbc_ctl & FBC_CTL_EN) == 0)
1395                 return;
1396
1397         fbc_ctl &= ~FBC_CTL_EN;
1398         I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400         /* Wait for compressing bit to clear */
1401         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402                 DRM_DEBUG_KMS("FBC idle timed out\n");
1403                 return;
1404         }
1405
1406         DRM_DEBUG_KMS("disabled FBC\n");
1407 }
1408
1409 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_framebuffer *fb = crtc->fb;
1414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1415         struct drm_i915_gem_object *obj = intel_fb->obj;
1416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417         int plane, i;
1418         u32 fbc_ctl, fbc_ctl2;
1419
1420         if (fb->pitch == dev_priv->cfb_pitch &&
1421             obj->fence_reg == dev_priv->cfb_fence &&
1422             intel_crtc->plane == dev_priv->cfb_plane &&
1423             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1424                 return;
1425
1426         i8xx_disable_fbc(dev);
1427
1428         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1429
1430         if (fb->pitch < dev_priv->cfb_pitch)
1431                 dev_priv->cfb_pitch = fb->pitch;
1432
1433         /* FBC_CTL wants 64B units */
1434         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1435         dev_priv->cfb_fence = obj->fence_reg;
1436         dev_priv->cfb_plane = intel_crtc->plane;
1437         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1438
1439         /* Clear old tags */
1440         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1441                 I915_WRITE(FBC_TAG + (i * 4), 0);
1442
1443         /* Set it up... */
1444         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1445         fbc_ctl2 |= plane;
1446         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1447         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1448
1449         /* enable it... */
1450         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1451         if (IS_I945GM(dev))
1452                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1453         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1454         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1455         fbc_ctl |= dev_priv->cfb_fence;
1456         I915_WRITE(FBC_CONTROL, fbc_ctl);
1457
1458         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1459                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1460 }
1461
1462 static bool i8xx_fbc_enabled(struct drm_device *dev)
1463 {
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465
1466         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1467 }
1468
1469 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1470 {
1471         struct drm_device *dev = crtc->dev;
1472         struct drm_i915_private *dev_priv = dev->dev_private;
1473         struct drm_framebuffer *fb = crtc->fb;
1474         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1475         struct drm_i915_gem_object *obj = intel_fb->obj;
1476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1477         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1478         unsigned long stall_watermark = 200;
1479         u32 dpfc_ctl;
1480
1481         dpfc_ctl = I915_READ(DPFC_CONTROL);
1482         if (dpfc_ctl & DPFC_CTL_EN) {
1483                 if (dev_priv->cfb_fence == obj->fence_reg &&
1484                     dev_priv->cfb_plane == intel_crtc->plane &&
1485                     dev_priv->cfb_y == crtc->y)
1486                         return;
1487
1488                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1489                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1490         }
1491
1492         dev_priv->cfb_fence = obj->fence_reg;
1493         dev_priv->cfb_plane = intel_crtc->plane;
1494         dev_priv->cfb_y = crtc->y;
1495
1496         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1497         dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1498         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1499
1500         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1501                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1502                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1503         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1504
1505         /* enable it... */
1506         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1507
1508         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1509 }
1510
1511 static void g4x_disable_fbc(struct drm_device *dev)
1512 {
1513         struct drm_i915_private *dev_priv = dev->dev_private;
1514         u32 dpfc_ctl;
1515
1516         /* Disable compression */
1517         dpfc_ctl = I915_READ(DPFC_CONTROL);
1518         if (dpfc_ctl & DPFC_CTL_EN) {
1519                 dpfc_ctl &= ~DPFC_CTL_EN;
1520                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1521
1522                 DRM_DEBUG_KMS("disabled FBC\n");
1523         }
1524 }
1525
1526 static bool g4x_fbc_enabled(struct drm_device *dev)
1527 {
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1531 }
1532
1533 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1534 {
1535         struct drm_i915_private *dev_priv = dev->dev_private;
1536         u32 blt_ecoskpd;
1537
1538         /* Make sure blitter notifies FBC of writes */
1539         gen6_gt_force_wake_get(dev_priv);
1540         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1541         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1542                 GEN6_BLITTER_LOCK_SHIFT;
1543         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1544         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1545         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1546         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1547                          GEN6_BLITTER_LOCK_SHIFT);
1548         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1549         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1550         gen6_gt_force_wake_put(dev_priv);
1551 }
1552
1553 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1554 {
1555         struct drm_device *dev = crtc->dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct drm_framebuffer *fb = crtc->fb;
1558         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1559         struct drm_i915_gem_object *obj = intel_fb->obj;
1560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1561         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1562         unsigned long stall_watermark = 200;
1563         u32 dpfc_ctl;
1564
1565         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1566         if (dpfc_ctl & DPFC_CTL_EN) {
1567                 if (dev_priv->cfb_fence == obj->fence_reg &&
1568                     dev_priv->cfb_plane == intel_crtc->plane &&
1569                     dev_priv->cfb_offset == obj->gtt_offset &&
1570                     dev_priv->cfb_y == crtc->y)
1571                         return;
1572
1573                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1574                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1575         }
1576
1577         dev_priv->cfb_fence = obj->fence_reg;
1578         dev_priv->cfb_plane = intel_crtc->plane;
1579         dev_priv->cfb_offset = obj->gtt_offset;
1580         dev_priv->cfb_y = crtc->y;
1581
1582         dpfc_ctl &= DPFC_RESERVED;
1583         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1584         /* Set persistent mode for front-buffer rendering, ala X. */
1585         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1586         dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1587         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1588
1589         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1590                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1591                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1592         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1593         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1594         /* enable it... */
1595         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1596
1597         if (IS_GEN6(dev)) {
1598                 I915_WRITE(SNB_DPFC_CTL_SA,
1599                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1600                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1601                 sandybridge_blit_fbc_update(dev);
1602         }
1603
1604         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1605 }
1606
1607 static void ironlake_disable_fbc(struct drm_device *dev)
1608 {
1609         struct drm_i915_private *dev_priv = dev->dev_private;
1610         u32 dpfc_ctl;
1611
1612         /* Disable compression */
1613         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1614         if (dpfc_ctl & DPFC_CTL_EN) {
1615                 dpfc_ctl &= ~DPFC_CTL_EN;
1616                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1617
1618                 DRM_DEBUG_KMS("disabled FBC\n");
1619         }
1620 }
1621
1622 static bool ironlake_fbc_enabled(struct drm_device *dev)
1623 {
1624         struct drm_i915_private *dev_priv = dev->dev_private;
1625
1626         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1627 }
1628
1629 bool intel_fbc_enabled(struct drm_device *dev)
1630 {
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632
1633         if (!dev_priv->display.fbc_enabled)
1634                 return false;
1635
1636         return dev_priv->display.fbc_enabled(dev);
1637 }
1638
1639 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1640 {
1641         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1642
1643         if (!dev_priv->display.enable_fbc)
1644                 return;
1645
1646         dev_priv->display.enable_fbc(crtc, interval);
1647 }
1648
1649 void intel_disable_fbc(struct drm_device *dev)
1650 {
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652
1653         if (!dev_priv->display.disable_fbc)
1654                 return;
1655
1656         dev_priv->display.disable_fbc(dev);
1657 }
1658
1659 /**
1660  * intel_update_fbc - enable/disable FBC as needed
1661  * @dev: the drm_device
1662  *
1663  * Set up the framebuffer compression hardware at mode set time.  We
1664  * enable it if possible:
1665  *   - plane A only (on pre-965)
1666  *   - no pixel mulitply/line duplication
1667  *   - no alpha buffer discard
1668  *   - no dual wide
1669  *   - framebuffer <= 2048 in width, 1536 in height
1670  *
1671  * We can't assume that any compression will take place (worst case),
1672  * so the compressed buffer has to be the same size as the uncompressed
1673  * one.  It also must reside (along with the line length buffer) in
1674  * stolen memory.
1675  *
1676  * We need to enable/disable FBC on a global basis.
1677  */
1678 static void intel_update_fbc(struct drm_device *dev)
1679 {
1680         struct drm_i915_private *dev_priv = dev->dev_private;
1681         struct drm_crtc *crtc = NULL, *tmp_crtc;
1682         struct intel_crtc *intel_crtc;
1683         struct drm_framebuffer *fb;
1684         struct intel_framebuffer *intel_fb;
1685         struct drm_i915_gem_object *obj;
1686
1687         DRM_DEBUG_KMS("\n");
1688
1689         if (!i915_powersave)
1690                 return;
1691
1692         if (!I915_HAS_FBC(dev))
1693                 return;
1694
1695         /*
1696          * If FBC is already on, we just have to verify that we can
1697          * keep it that way...
1698          * Need to disable if:
1699          *   - more than one pipe is active
1700          *   - changing FBC params (stride, fence, mode)
1701          *   - new fb is too large to fit in compressed buffer
1702          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1703          */
1704         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1705                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1706                         if (crtc) {
1707                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1708                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1709                                 goto out_disable;
1710                         }
1711                         crtc = tmp_crtc;
1712                 }
1713         }
1714
1715         if (!crtc || crtc->fb == NULL) {
1716                 DRM_DEBUG_KMS("no output, disabling\n");
1717                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1718                 goto out_disable;
1719         }
1720
1721         intel_crtc = to_intel_crtc(crtc);
1722         fb = crtc->fb;
1723         intel_fb = to_intel_framebuffer(fb);
1724         obj = intel_fb->obj;
1725
1726         if (!i915_enable_fbc) {
1727                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1728                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1729                 goto out_disable;
1730         }
1731         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1732                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1733                               "compression\n");
1734                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1735                 goto out_disable;
1736         }
1737         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1738             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1739                 DRM_DEBUG_KMS("mode incompatible with compression, "
1740                               "disabling\n");
1741                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1742                 goto out_disable;
1743         }
1744         if ((crtc->mode.hdisplay > 2048) ||
1745             (crtc->mode.vdisplay > 1536)) {
1746                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1747                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1748                 goto out_disable;
1749         }
1750         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1751                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1752                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1753                 goto out_disable;
1754         }
1755
1756         /* The use of a CPU fence is mandatory in order to detect writes
1757          * by the CPU to the scanout and trigger updates to the FBC.
1758          */
1759         if (obj->tiling_mode != I915_TILING_X ||
1760             obj->fence_reg == I915_FENCE_REG_NONE) {
1761                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1762                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1763                 goto out_disable;
1764         }
1765
1766         /* If the kernel debugger is active, always disable compression */
1767         if (in_dbg_master())
1768                 goto out_disable;
1769
1770         intel_enable_fbc(crtc, 500);
1771         return;
1772
1773 out_disable:
1774         /* Multiple disables should be harmless */
1775         if (intel_fbc_enabled(dev)) {
1776                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1777                 intel_disable_fbc(dev);
1778         }
1779 }
1780
1781 int
1782 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1783                            struct drm_i915_gem_object *obj,
1784                            struct intel_ring_buffer *pipelined)
1785 {
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         u32 alignment;
1788         int ret;
1789
1790         switch (obj->tiling_mode) {
1791         case I915_TILING_NONE:
1792                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1793                         alignment = 128 * 1024;
1794                 else if (INTEL_INFO(dev)->gen >= 4)
1795                         alignment = 4 * 1024;
1796                 else
1797                         alignment = 64 * 1024;
1798                 break;
1799         case I915_TILING_X:
1800                 /* pin() will align the object as required by fence */
1801                 alignment = 0;
1802                 break;
1803         case I915_TILING_Y:
1804                 /* FIXME: Is this true? */
1805                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1806                 return -EINVAL;
1807         default:
1808                 BUG();
1809         }
1810
1811         dev_priv->mm.interruptible = false;
1812         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1813         if (ret)
1814                 goto err_interruptible;
1815
1816         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1817          * fence, whereas 965+ only requires a fence if using
1818          * framebuffer compression.  For simplicity, we always install
1819          * a fence as the cost is not that onerous.
1820          */
1821         if (obj->tiling_mode != I915_TILING_NONE) {
1822                 ret = i915_gem_object_get_fence(obj, pipelined);
1823                 if (ret)
1824                         goto err_unpin;
1825         }
1826
1827         dev_priv->mm.interruptible = true;
1828         return 0;
1829
1830 err_unpin:
1831         i915_gem_object_unpin(obj);
1832 err_interruptible:
1833         dev_priv->mm.interruptible = true;
1834         return ret;
1835 }
1836
1837 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1838                              int x, int y)
1839 {
1840         struct drm_device *dev = crtc->dev;
1841         struct drm_i915_private *dev_priv = dev->dev_private;
1842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1843         struct intel_framebuffer *intel_fb;
1844         struct drm_i915_gem_object *obj;
1845         int plane = intel_crtc->plane;
1846         unsigned long Start, Offset;
1847         u32 dspcntr;
1848         u32 reg;
1849
1850         switch (plane) {
1851         case 0:
1852         case 1:
1853                 break;
1854         default:
1855                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1856                 return -EINVAL;
1857         }
1858
1859         intel_fb = to_intel_framebuffer(fb);
1860         obj = intel_fb->obj;
1861
1862         reg = DSPCNTR(plane);
1863         dspcntr = I915_READ(reg);
1864         /* Mask out pixel format bits in case we change it */
1865         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1866         switch (fb->bits_per_pixel) {
1867         case 8:
1868                 dspcntr |= DISPPLANE_8BPP;
1869                 break;
1870         case 16:
1871                 if (fb->depth == 15)
1872                         dspcntr |= DISPPLANE_15_16BPP;
1873                 else
1874                         dspcntr |= DISPPLANE_16BPP;
1875                 break;
1876         case 24:
1877         case 32:
1878                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1879                 break;
1880         default:
1881                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1882                 return -EINVAL;
1883         }
1884         if (INTEL_INFO(dev)->gen >= 4) {
1885                 if (obj->tiling_mode != I915_TILING_NONE)
1886                         dspcntr |= DISPPLANE_TILED;
1887                 else
1888                         dspcntr &= ~DISPPLANE_TILED;
1889         }
1890
1891         I915_WRITE(reg, dspcntr);
1892
1893         Start = obj->gtt_offset;
1894         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1895
1896         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1897                       Start, Offset, x, y, fb->pitch);
1898         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1899         if (INTEL_INFO(dev)->gen >= 4) {
1900                 I915_WRITE(DSPSURF(plane), Start);
1901                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1902                 I915_WRITE(DSPADDR(plane), Offset);
1903         } else
1904                 I915_WRITE(DSPADDR(plane), Start + Offset);
1905         POSTING_READ(reg);
1906
1907         return 0;
1908 }
1909
1910 static int ironlake_update_plane(struct drm_crtc *crtc,
1911                                  struct drm_framebuffer *fb, int x, int y)
1912 {
1913         struct drm_device *dev = crtc->dev;
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1916         struct intel_framebuffer *intel_fb;
1917         struct drm_i915_gem_object *obj;
1918         int plane = intel_crtc->plane;
1919         unsigned long Start, Offset;
1920         u32 dspcntr;
1921         u32 reg;
1922
1923         switch (plane) {
1924         case 0:
1925         case 1:
1926                 break;
1927         default:
1928                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1929                 return -EINVAL;
1930         }
1931
1932         intel_fb = to_intel_framebuffer(fb);
1933         obj = intel_fb->obj;
1934
1935         reg = DSPCNTR(plane);
1936         dspcntr = I915_READ(reg);
1937         /* Mask out pixel format bits in case we change it */
1938         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1939         switch (fb->bits_per_pixel) {
1940         case 8:
1941                 dspcntr |= DISPPLANE_8BPP;
1942                 break;
1943         case 16:
1944                 if (fb->depth != 16)
1945                         return -EINVAL;
1946
1947                 dspcntr |= DISPPLANE_16BPP;
1948                 break;
1949         case 24:
1950         case 32:
1951                 if (fb->depth == 24)
1952                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1953                 else if (fb->depth == 30)
1954                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1955                 else
1956                         return -EINVAL;
1957                 break;
1958         default:
1959                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1960                 return -EINVAL;
1961         }
1962
1963         if (obj->tiling_mode != I915_TILING_NONE)
1964                 dspcntr |= DISPPLANE_TILED;
1965         else
1966                 dspcntr &= ~DISPPLANE_TILED;
1967
1968         /* must disable */
1969         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1970
1971         I915_WRITE(reg, dspcntr);
1972
1973         Start = obj->gtt_offset;
1974         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1975
1976         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1977                       Start, Offset, x, y, fb->pitch);
1978         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1979         I915_WRITE(DSPSURF(plane), Start);
1980         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1981         I915_WRITE(DSPADDR(plane), Offset);
1982         POSTING_READ(reg);
1983
1984         return 0;
1985 }
1986
1987 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1988 static int
1989 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1990                            int x, int y, enum mode_set_atomic state)
1991 {
1992         struct drm_device *dev = crtc->dev;
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         int ret;
1995
1996         ret = dev_priv->display.update_plane(crtc, fb, x, y);
1997         if (ret)
1998                 return ret;
1999
2000         intel_update_fbc(dev);
2001         intel_increase_pllclock(crtc);
2002
2003         return 0;
2004 }
2005
2006 static int
2007 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2008                     struct drm_framebuffer *old_fb)
2009 {
2010         struct drm_device *dev = crtc->dev;
2011         struct drm_i915_master_private *master_priv;
2012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2013         int ret;
2014
2015         /* no fb bound */
2016         if (!crtc->fb) {
2017                 DRM_DEBUG_KMS("No FB bound\n");
2018                 return 0;
2019         }
2020
2021         switch (intel_crtc->plane) {
2022         case 0:
2023         case 1:
2024                 break;
2025         default:
2026                 return -EINVAL;
2027         }
2028
2029         mutex_lock(&dev->struct_mutex);
2030         ret = intel_pin_and_fence_fb_obj(dev,
2031                                          to_intel_framebuffer(crtc->fb)->obj,
2032                                          NULL);
2033         if (ret != 0) {
2034                 mutex_unlock(&dev->struct_mutex);
2035                 return ret;
2036         }
2037
2038         if (old_fb) {
2039                 struct drm_i915_private *dev_priv = dev->dev_private;
2040                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2041
2042                 wait_event(dev_priv->pending_flip_queue,
2043                            atomic_read(&dev_priv->mm.wedged) ||
2044                            atomic_read(&obj->pending_flip) == 0);
2045
2046                 /* Big Hammer, we also need to ensure that any pending
2047                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2048                  * current scanout is retired before unpinning the old
2049                  * framebuffer.
2050                  *
2051                  * This should only fail upon a hung GPU, in which case we
2052                  * can safely continue.
2053                  */
2054                 ret = i915_gem_object_finish_gpu(obj);
2055                 (void) ret;
2056         }
2057
2058         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2059                                          LEAVE_ATOMIC_MODE_SET);
2060         if (ret) {
2061                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2062                 mutex_unlock(&dev->struct_mutex);
2063                 return ret;
2064         }
2065
2066         if (old_fb) {
2067                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2068                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2069         }
2070
2071         mutex_unlock(&dev->struct_mutex);
2072
2073         if (!dev->primary->master)
2074                 return 0;
2075
2076         master_priv = dev->primary->master->driver_priv;
2077         if (!master_priv->sarea_priv)
2078                 return 0;
2079
2080         if (intel_crtc->pipe) {
2081                 master_priv->sarea_priv->pipeB_x = x;
2082                 master_priv->sarea_priv->pipeB_y = y;
2083         } else {
2084                 master_priv->sarea_priv->pipeA_x = x;
2085                 master_priv->sarea_priv->pipeA_y = y;
2086         }
2087
2088         return 0;
2089 }
2090
2091 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2092 {
2093         struct drm_device *dev = crtc->dev;
2094         struct drm_i915_private *dev_priv = dev->dev_private;
2095         u32 dpa_ctl;
2096
2097         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2098         dpa_ctl = I915_READ(DP_A);
2099         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2100
2101         if (clock < 200000) {
2102                 u32 temp;
2103                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2104                 /* workaround for 160Mhz:
2105                    1) program 0x4600c bits 15:0 = 0x8124
2106                    2) program 0x46010 bit 0 = 1
2107                    3) program 0x46034 bit 24 = 1
2108                    4) program 0x64000 bit 14 = 1
2109                    */
2110                 temp = I915_READ(0x4600c);
2111                 temp &= 0xffff0000;
2112                 I915_WRITE(0x4600c, temp | 0x8124);
2113
2114                 temp = I915_READ(0x46010);
2115                 I915_WRITE(0x46010, temp | 1);
2116
2117                 temp = I915_READ(0x46034);
2118                 I915_WRITE(0x46034, temp | (1 << 24));
2119         } else {
2120                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2121         }
2122         I915_WRITE(DP_A, dpa_ctl);
2123
2124         POSTING_READ(DP_A);
2125         udelay(500);
2126 }
2127
2128 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = crtc->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133         int pipe = intel_crtc->pipe;
2134         u32 reg, temp;
2135
2136         /* enable normal train */
2137         reg = FDI_TX_CTL(pipe);
2138         temp = I915_READ(reg);
2139         if (IS_IVYBRIDGE(dev)) {
2140                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2141                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2142         } else {
2143                 temp &= ~FDI_LINK_TRAIN_NONE;
2144                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2145         }
2146         I915_WRITE(reg, temp);
2147
2148         reg = FDI_RX_CTL(pipe);
2149         temp = I915_READ(reg);
2150         if (HAS_PCH_CPT(dev)) {
2151                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2152                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2153         } else {
2154                 temp &= ~FDI_LINK_TRAIN_NONE;
2155                 temp |= FDI_LINK_TRAIN_NONE;
2156         }
2157         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2158
2159         /* wait one idle pattern time */
2160         POSTING_READ(reg);
2161         udelay(1000);
2162
2163         /* IVB wants error correction enabled */
2164         if (IS_IVYBRIDGE(dev))
2165                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2166                            FDI_FE_ERRC_ENABLE);
2167 }
2168
2169 /* The FDI link training functions for ILK/Ibexpeak. */
2170 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2171 {
2172         struct drm_device *dev = crtc->dev;
2173         struct drm_i915_private *dev_priv = dev->dev_private;
2174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175         int pipe = intel_crtc->pipe;
2176         int plane = intel_crtc->plane;
2177         u32 reg, temp, tries;
2178
2179         /* FDI needs bits from pipe & plane first */
2180         assert_pipe_enabled(dev_priv, pipe);
2181         assert_plane_enabled(dev_priv, plane);
2182
2183         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2184            for train result */
2185         reg = FDI_RX_IMR(pipe);
2186         temp = I915_READ(reg);
2187         temp &= ~FDI_RX_SYMBOL_LOCK;
2188         temp &= ~FDI_RX_BIT_LOCK;
2189         I915_WRITE(reg, temp);
2190         I915_READ(reg);
2191         udelay(150);
2192
2193         /* enable CPU FDI TX and PCH FDI RX */
2194         reg = FDI_TX_CTL(pipe);
2195         temp = I915_READ(reg);
2196         temp &= ~(7 << 19);
2197         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2198         temp &= ~FDI_LINK_TRAIN_NONE;
2199         temp |= FDI_LINK_TRAIN_PATTERN_1;
2200         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2201
2202         reg = FDI_RX_CTL(pipe);
2203         temp = I915_READ(reg);
2204         temp &= ~FDI_LINK_TRAIN_NONE;
2205         temp |= FDI_LINK_TRAIN_PATTERN_1;
2206         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2207
2208         POSTING_READ(reg);
2209         udelay(150);
2210
2211         /* Ironlake workaround, enable clock pointer after FDI enable*/
2212         if (HAS_PCH_IBX(dev)) {
2213                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2214                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2215                            FDI_RX_PHASE_SYNC_POINTER_EN);
2216         }
2217
2218         reg = FDI_RX_IIR(pipe);
2219         for (tries = 0; tries < 5; tries++) {
2220                 temp = I915_READ(reg);
2221                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2222
2223                 if ((temp & FDI_RX_BIT_LOCK)) {
2224                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2225                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2226                         break;
2227                 }
2228         }
2229         if (tries == 5)
2230                 DRM_ERROR("FDI train 1 fail!\n");
2231
2232         /* Train 2 */
2233         reg = FDI_TX_CTL(pipe);
2234         temp = I915_READ(reg);
2235         temp &= ~FDI_LINK_TRAIN_NONE;
2236         temp |= FDI_LINK_TRAIN_PATTERN_2;
2237         I915_WRITE(reg, temp);
2238
2239         reg = FDI_RX_CTL(pipe);
2240         temp = I915_READ(reg);
2241         temp &= ~FDI_LINK_TRAIN_NONE;
2242         temp |= FDI_LINK_TRAIN_PATTERN_2;
2243         I915_WRITE(reg, temp);
2244
2245         POSTING_READ(reg);
2246         udelay(150);
2247
2248         reg = FDI_RX_IIR(pipe);
2249         for (tries = 0; tries < 5; tries++) {
2250                 temp = I915_READ(reg);
2251                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252
2253                 if (temp & FDI_RX_SYMBOL_LOCK) {
2254                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2255                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2256                         break;
2257                 }
2258         }
2259         if (tries == 5)
2260                 DRM_ERROR("FDI train 2 fail!\n");
2261
2262         DRM_DEBUG_KMS("FDI train done\n");
2263
2264 }
2265
2266 static const int snb_b_fdi_train_param [] = {
2267         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2268         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2269         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2270         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2271 };
2272
2273 /* The FDI link training functions for SNB/Cougarpoint. */
2274 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         int pipe = intel_crtc->pipe;
2280         u32 reg, temp, i;
2281
2282         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2283            for train result */
2284         reg = FDI_RX_IMR(pipe);
2285         temp = I915_READ(reg);
2286         temp &= ~FDI_RX_SYMBOL_LOCK;
2287         temp &= ~FDI_RX_BIT_LOCK;
2288         I915_WRITE(reg, temp);
2289
2290         POSTING_READ(reg);
2291         udelay(150);
2292
2293         /* enable CPU FDI TX and PCH FDI RX */
2294         reg = FDI_TX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         temp &= ~(7 << 19);
2297         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2298         temp &= ~FDI_LINK_TRAIN_NONE;
2299         temp |= FDI_LINK_TRAIN_PATTERN_1;
2300         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2301         /* SNB-B */
2302         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2303         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2304
2305         reg = FDI_RX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         if (HAS_PCH_CPT(dev)) {
2308                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2310         } else {
2311                 temp &= ~FDI_LINK_TRAIN_NONE;
2312                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2313         }
2314         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2315
2316         POSTING_READ(reg);
2317         udelay(150);
2318
2319         for (i = 0; i < 4; i++ ) {
2320                 reg = FDI_TX_CTL(pipe);
2321                 temp = I915_READ(reg);
2322                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2323                 temp |= snb_b_fdi_train_param[i];
2324                 I915_WRITE(reg, temp);
2325
2326                 POSTING_READ(reg);
2327                 udelay(500);
2328
2329                 reg = FDI_RX_IIR(pipe);
2330                 temp = I915_READ(reg);
2331                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2332
2333                 if (temp & FDI_RX_BIT_LOCK) {
2334                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2335                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2336                         break;
2337                 }
2338         }
2339         if (i == 4)
2340                 DRM_ERROR("FDI train 1 fail!\n");
2341
2342         /* Train 2 */
2343         reg = FDI_TX_CTL(pipe);
2344         temp = I915_READ(reg);
2345         temp &= ~FDI_LINK_TRAIN_NONE;
2346         temp |= FDI_LINK_TRAIN_PATTERN_2;
2347         if (IS_GEN6(dev)) {
2348                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2349                 /* SNB-B */
2350                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2351         }
2352         I915_WRITE(reg, temp);
2353
2354         reg = FDI_RX_CTL(pipe);
2355         temp = I915_READ(reg);
2356         if (HAS_PCH_CPT(dev)) {
2357                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2358                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2359         } else {
2360                 temp &= ~FDI_LINK_TRAIN_NONE;
2361                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2362         }
2363         I915_WRITE(reg, temp);
2364
2365         POSTING_READ(reg);
2366         udelay(150);
2367
2368         for (i = 0; i < 4; i++ ) {
2369                 reg = FDI_TX_CTL(pipe);
2370                 temp = I915_READ(reg);
2371                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2372                 temp |= snb_b_fdi_train_param[i];
2373                 I915_WRITE(reg, temp);
2374
2375                 POSTING_READ(reg);
2376                 udelay(500);
2377
2378                 reg = FDI_RX_IIR(pipe);
2379                 temp = I915_READ(reg);
2380                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2381
2382                 if (temp & FDI_RX_SYMBOL_LOCK) {
2383                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2384                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2385                         break;
2386                 }
2387         }
2388         if (i == 4)
2389                 DRM_ERROR("FDI train 2 fail!\n");
2390
2391         DRM_DEBUG_KMS("FDI train done.\n");
2392 }
2393
2394 /* Manual link training for Ivy Bridge A0 parts */
2395 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2396 {
2397         struct drm_device *dev = crtc->dev;
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400         int pipe = intel_crtc->pipe;
2401         u32 reg, temp, i;
2402
2403         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2404            for train result */
2405         reg = FDI_RX_IMR(pipe);
2406         temp = I915_READ(reg);
2407         temp &= ~FDI_RX_SYMBOL_LOCK;
2408         temp &= ~FDI_RX_BIT_LOCK;
2409         I915_WRITE(reg, temp);
2410
2411         POSTING_READ(reg);
2412         udelay(150);
2413
2414         /* enable CPU FDI TX and PCH FDI RX */
2415         reg = FDI_TX_CTL(pipe);
2416         temp = I915_READ(reg);
2417         temp &= ~(7 << 19);
2418         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2419         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2420         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2421         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2422         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2423         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2424
2425         reg = FDI_RX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_AUTO;
2428         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2429         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2430         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2431
2432         POSTING_READ(reg);
2433         udelay(150);
2434
2435         for (i = 0; i < 4; i++ ) {
2436                 reg = FDI_TX_CTL(pipe);
2437                 temp = I915_READ(reg);
2438                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2439                 temp |= snb_b_fdi_train_param[i];
2440                 I915_WRITE(reg, temp);
2441
2442                 POSTING_READ(reg);
2443                 udelay(500);
2444
2445                 reg = FDI_RX_IIR(pipe);
2446                 temp = I915_READ(reg);
2447                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449                 if (temp & FDI_RX_BIT_LOCK ||
2450                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2451                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2453                         break;
2454                 }
2455         }
2456         if (i == 4)
2457                 DRM_ERROR("FDI train 1 fail!\n");
2458
2459         /* Train 2 */
2460         reg = FDI_TX_CTL(pipe);
2461         temp = I915_READ(reg);
2462         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2463         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2464         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2465         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2466         I915_WRITE(reg, temp);
2467
2468         reg = FDI_RX_CTL(pipe);
2469         temp = I915_READ(reg);
2470         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2471         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2472         I915_WRITE(reg, temp);
2473
2474         POSTING_READ(reg);
2475         udelay(150);
2476
2477         for (i = 0; i < 4; i++ ) {
2478                 reg = FDI_TX_CTL(pipe);
2479                 temp = I915_READ(reg);
2480                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2481                 temp |= snb_b_fdi_train_param[i];
2482                 I915_WRITE(reg, temp);
2483
2484                 POSTING_READ(reg);
2485                 udelay(500);
2486
2487                 reg = FDI_RX_IIR(pipe);
2488                 temp = I915_READ(reg);
2489                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2490
2491                 if (temp & FDI_RX_SYMBOL_LOCK) {
2492                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2493                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2494                         break;
2495                 }
2496         }
2497         if (i == 4)
2498                 DRM_ERROR("FDI train 2 fail!\n");
2499
2500         DRM_DEBUG_KMS("FDI train done.\n");
2501 }
2502
2503 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2504 {
2505         struct drm_device *dev = crtc->dev;
2506         struct drm_i915_private *dev_priv = dev->dev_private;
2507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2508         int pipe = intel_crtc->pipe;
2509         u32 reg, temp;
2510
2511         /* Write the TU size bits so error detection works */
2512         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2513                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2514
2515         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2516         reg = FDI_RX_CTL(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~((0x7 << 19) | (0x7 << 16));
2519         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2520         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2521         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2522
2523         POSTING_READ(reg);
2524         udelay(200);
2525
2526         /* Switch from Rawclk to PCDclk */
2527         temp = I915_READ(reg);
2528         I915_WRITE(reg, temp | FDI_PCDCLK);
2529
2530         POSTING_READ(reg);
2531         udelay(200);
2532
2533         /* Enable CPU FDI TX PLL, always on for Ironlake */
2534         reg = FDI_TX_CTL(pipe);
2535         temp = I915_READ(reg);
2536         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2537                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2538
2539                 POSTING_READ(reg);
2540                 udelay(100);
2541         }
2542 }
2543
2544 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2545 {
2546         struct drm_device *dev = crtc->dev;
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549         int pipe = intel_crtc->pipe;
2550         u32 reg, temp;
2551
2552         /* disable CPU FDI tx and PCH FDI rx */
2553         reg = FDI_TX_CTL(pipe);
2554         temp = I915_READ(reg);
2555         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2556         POSTING_READ(reg);
2557
2558         reg = FDI_RX_CTL(pipe);
2559         temp = I915_READ(reg);
2560         temp &= ~(0x7 << 16);
2561         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2562         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2563
2564         POSTING_READ(reg);
2565         udelay(100);
2566
2567         /* Ironlake workaround, disable clock pointer after downing FDI */
2568         if (HAS_PCH_IBX(dev)) {
2569                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2570                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2571                            I915_READ(FDI_RX_CHICKEN(pipe) &
2572                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2573         }
2574
2575         /* still set train pattern 1 */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_LINK_TRAIN_NONE;
2579         temp |= FDI_LINK_TRAIN_PATTERN_1;
2580         I915_WRITE(reg, temp);
2581
2582         reg = FDI_RX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         if (HAS_PCH_CPT(dev)) {
2585                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2586                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2587         } else {
2588                 temp &= ~FDI_LINK_TRAIN_NONE;
2589                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2590         }
2591         /* BPC in FDI rx is consistent with that in PIPECONF */
2592         temp &= ~(0x07 << 16);
2593         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2594         I915_WRITE(reg, temp);
2595
2596         POSTING_READ(reg);
2597         udelay(100);
2598 }
2599
2600 /*
2601  * When we disable a pipe, we need to clear any pending scanline wait events
2602  * to avoid hanging the ring, which we assume we are waiting on.
2603  */
2604 static void intel_clear_scanline_wait(struct drm_device *dev)
2605 {
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_ring_buffer *ring;
2608         u32 tmp;
2609
2610         if (IS_GEN2(dev))
2611                 /* Can't break the hang on i8xx */
2612                 return;
2613
2614         ring = LP_RING(dev_priv);
2615         tmp = I915_READ_CTL(ring);
2616         if (tmp & RING_WAIT)
2617                 I915_WRITE_CTL(ring, tmp);
2618 }
2619
2620 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2621 {
2622         struct drm_i915_gem_object *obj;
2623         struct drm_i915_private *dev_priv;
2624
2625         if (crtc->fb == NULL)
2626                 return;
2627
2628         obj = to_intel_framebuffer(crtc->fb)->obj;
2629         dev_priv = crtc->dev->dev_private;
2630         wait_event(dev_priv->pending_flip_queue,
2631                    atomic_read(&obj->pending_flip) == 0);
2632 }
2633
2634 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2635 {
2636         struct drm_device *dev = crtc->dev;
2637         struct drm_mode_config *mode_config = &dev->mode_config;
2638         struct intel_encoder *encoder;
2639
2640         /*
2641          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2642          * must be driven by its own crtc; no sharing is possible.
2643          */
2644         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2645                 if (encoder->base.crtc != crtc)
2646                         continue;
2647
2648                 switch (encoder->type) {
2649                 case INTEL_OUTPUT_EDP:
2650                         if (!intel_encoder_is_pch_edp(&encoder->base))
2651                                 return false;
2652                         continue;
2653                 }
2654         }
2655
2656         return true;
2657 }
2658
2659 /*
2660  * Enable PCH resources required for PCH ports:
2661  *   - PCH PLLs
2662  *   - FDI training & RX/TX
2663  *   - update transcoder timings
2664  *   - DP transcoding bits
2665  *   - transcoder
2666  */
2667 static void ironlake_pch_enable(struct drm_crtc *crtc)
2668 {
2669         struct drm_device *dev = crtc->dev;
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2672         int pipe = intel_crtc->pipe;
2673         u32 reg, temp;
2674
2675         /* For PCH output, training FDI link */
2676         dev_priv->display.fdi_link_train(crtc);
2677
2678         intel_enable_pch_pll(dev_priv, pipe);
2679
2680         if (HAS_PCH_CPT(dev)) {
2681                 /* Be sure PCH DPLL SEL is set */
2682                 temp = I915_READ(PCH_DPLL_SEL);
2683                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2684                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2685                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2686                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2687                 I915_WRITE(PCH_DPLL_SEL, temp);
2688         }
2689
2690         /* set transcoder timing, panel must allow it */
2691         assert_panel_unlocked(dev_priv, pipe);
2692         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2693         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2694         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2695
2696         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2697         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2698         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2699
2700         intel_fdi_normal_train(crtc);
2701
2702         /* For PCH DP, enable TRANS_DP_CTL */
2703         if (HAS_PCH_CPT(dev) &&
2704             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2705                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2706                 reg = TRANS_DP_CTL(pipe);
2707                 temp = I915_READ(reg);
2708                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2709                           TRANS_DP_SYNC_MASK |
2710                           TRANS_DP_BPC_MASK);
2711                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2712                          TRANS_DP_ENH_FRAMING);
2713                 temp |= bpc << 9; /* same format but at 11:9 */
2714
2715                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2716                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2717                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2718                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2719
2720                 switch (intel_trans_dp_port_sel(crtc)) {
2721                 case PCH_DP_B:
2722                         temp |= TRANS_DP_PORT_SEL_B;
2723                         break;
2724                 case PCH_DP_C:
2725                         temp |= TRANS_DP_PORT_SEL_C;
2726                         break;
2727                 case PCH_DP_D:
2728                         temp |= TRANS_DP_PORT_SEL_D;
2729                         break;
2730                 default:
2731                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2732                         temp |= TRANS_DP_PORT_SEL_B;
2733                         break;
2734                 }
2735
2736                 I915_WRITE(reg, temp);
2737         }
2738
2739         intel_enable_transcoder(dev_priv, pipe);
2740 }
2741
2742 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2743 {
2744         struct drm_device *dev = crtc->dev;
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2747         int pipe = intel_crtc->pipe;
2748         int plane = intel_crtc->plane;
2749         u32 temp;
2750         bool is_pch_port;
2751
2752         if (intel_crtc->active)
2753                 return;
2754
2755         intel_crtc->active = true;
2756         intel_update_watermarks(dev);
2757
2758         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2759                 temp = I915_READ(PCH_LVDS);
2760                 if ((temp & LVDS_PORT_EN) == 0)
2761                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2762         }
2763
2764         is_pch_port = intel_crtc_driving_pch(crtc);
2765
2766         if (is_pch_port)
2767                 ironlake_fdi_pll_enable(crtc);
2768         else
2769                 ironlake_fdi_disable(crtc);
2770
2771         /* Enable panel fitting for LVDS */
2772         if (dev_priv->pch_pf_size &&
2773             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2774                 /* Force use of hard-coded filter coefficients
2775                  * as some pre-programmed values are broken,
2776                  * e.g. x201.
2777                  */
2778                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2779                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2780                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2781         }
2782
2783         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2784         intel_enable_plane(dev_priv, plane, pipe);
2785
2786         if (is_pch_port)
2787                 ironlake_pch_enable(crtc);
2788
2789         intel_crtc_load_lut(crtc);
2790
2791         mutex_lock(&dev->struct_mutex);
2792         intel_update_fbc(dev);
2793         mutex_unlock(&dev->struct_mutex);
2794
2795         intel_crtc_update_cursor(crtc, true);
2796 }
2797
2798 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2799 {
2800         struct drm_device *dev = crtc->dev;
2801         struct drm_i915_private *dev_priv = dev->dev_private;
2802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2803         int pipe = intel_crtc->pipe;
2804         int plane = intel_crtc->plane;
2805         u32 reg, temp;
2806
2807         if (!intel_crtc->active)
2808                 return;
2809
2810         intel_crtc_wait_for_pending_flips(crtc);
2811         drm_vblank_off(dev, pipe);
2812         intel_crtc_update_cursor(crtc, false);
2813
2814         intel_disable_plane(dev_priv, plane, pipe);
2815
2816         if (dev_priv->cfb_plane == plane)
2817                 intel_disable_fbc(dev);
2818
2819         intel_disable_pipe(dev_priv, pipe);
2820
2821         /* Disable PF */
2822         I915_WRITE(PF_CTL(pipe), 0);
2823         I915_WRITE(PF_WIN_SZ(pipe), 0);
2824
2825         ironlake_fdi_disable(crtc);
2826
2827         /* This is a horrible layering violation; we should be doing this in
2828          * the connector/encoder ->prepare instead, but we don't always have
2829          * enough information there about the config to know whether it will
2830          * actually be necessary or just cause undesired flicker.
2831          */
2832         intel_disable_pch_ports(dev_priv, pipe);
2833
2834         intel_disable_transcoder(dev_priv, pipe);
2835
2836         if (HAS_PCH_CPT(dev)) {
2837                 /* disable TRANS_DP_CTL */
2838                 reg = TRANS_DP_CTL(pipe);
2839                 temp = I915_READ(reg);
2840                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2841                 temp |= TRANS_DP_PORT_SEL_NONE;
2842                 I915_WRITE(reg, temp);
2843
2844                 /* disable DPLL_SEL */
2845                 temp = I915_READ(PCH_DPLL_SEL);
2846                 switch (pipe) {
2847                 case 0:
2848                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2849                         break;
2850                 case 1:
2851                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2852                         break;
2853                 case 2:
2854                         /* FIXME: manage transcoder PLLs? */
2855                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2856                         break;
2857                 default:
2858                         BUG(); /* wtf */
2859                 }
2860                 I915_WRITE(PCH_DPLL_SEL, temp);
2861         }
2862
2863         /* disable PCH DPLL */
2864         intel_disable_pch_pll(dev_priv, pipe);
2865
2866         /* Switch from PCDclk to Rawclk */
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2870
2871         /* Disable CPU FDI TX PLL */
2872         reg = FDI_TX_CTL(pipe);
2873         temp = I915_READ(reg);
2874         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2875
2876         POSTING_READ(reg);
2877         udelay(100);
2878
2879         reg = FDI_RX_CTL(pipe);
2880         temp = I915_READ(reg);
2881         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2882
2883         /* Wait for the clocks to turn off. */
2884         POSTING_READ(reg);
2885         udelay(100);
2886
2887         intel_crtc->active = false;
2888         intel_update_watermarks(dev);
2889
2890         mutex_lock(&dev->struct_mutex);
2891         intel_update_fbc(dev);
2892         intel_clear_scanline_wait(dev);
2893         mutex_unlock(&dev->struct_mutex);
2894 }
2895
2896 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2897 {
2898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2899         int pipe = intel_crtc->pipe;
2900         int plane = intel_crtc->plane;
2901
2902         /* XXX: When our outputs are all unaware of DPMS modes other than off
2903          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2904          */
2905         switch (mode) {
2906         case DRM_MODE_DPMS_ON:
2907         case DRM_MODE_DPMS_STANDBY:
2908         case DRM_MODE_DPMS_SUSPEND:
2909                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2910                 ironlake_crtc_enable(crtc);
2911                 break;
2912
2913         case DRM_MODE_DPMS_OFF:
2914                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2915                 ironlake_crtc_disable(crtc);
2916                 break;
2917         }
2918 }
2919
2920 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2921 {
2922         if (!enable && intel_crtc->overlay) {
2923                 struct drm_device *dev = intel_crtc->base.dev;
2924                 struct drm_i915_private *dev_priv = dev->dev_private;
2925
2926                 mutex_lock(&dev->struct_mutex);
2927                 dev_priv->mm.interruptible = false;
2928                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2929                 dev_priv->mm.interruptible = true;
2930                 mutex_unlock(&dev->struct_mutex);
2931         }
2932
2933         /* Let userspace switch the overlay on again. In most cases userspace
2934          * has to recompute where to put it anyway.
2935          */
2936 }
2937
2938 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2939 {
2940         struct drm_device *dev = crtc->dev;
2941         struct drm_i915_private *dev_priv = dev->dev_private;
2942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2943         int pipe = intel_crtc->pipe;
2944         int plane = intel_crtc->plane;
2945
2946         if (intel_crtc->active)
2947                 return;
2948
2949         intel_crtc->active = true;
2950         intel_update_watermarks(dev);
2951
2952         intel_enable_pll(dev_priv, pipe);
2953         intel_enable_pipe(dev_priv, pipe, false);
2954         intel_enable_plane(dev_priv, plane, pipe);
2955
2956         intel_crtc_load_lut(crtc);
2957         intel_update_fbc(dev);
2958
2959         /* Give the overlay scaler a chance to enable if it's on this pipe */
2960         intel_crtc_dpms_overlay(intel_crtc, true);
2961         intel_crtc_update_cursor(crtc, true);
2962 }
2963
2964 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2965 {
2966         struct drm_device *dev = crtc->dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969         int pipe = intel_crtc->pipe;
2970         int plane = intel_crtc->plane;
2971
2972         if (!intel_crtc->active)
2973                 return;
2974
2975         /* Give the overlay scaler a chance to disable if it's on this pipe */
2976         intel_crtc_wait_for_pending_flips(crtc);
2977         drm_vblank_off(dev, pipe);
2978         intel_crtc_dpms_overlay(intel_crtc, false);
2979         intel_crtc_update_cursor(crtc, false);
2980
2981         if (dev_priv->cfb_plane == plane)
2982                 intel_disable_fbc(dev);
2983
2984         intel_disable_plane(dev_priv, plane, pipe);
2985         intel_disable_pipe(dev_priv, pipe);
2986         intel_disable_pll(dev_priv, pipe);
2987
2988         intel_crtc->active = false;
2989         intel_update_fbc(dev);
2990         intel_update_watermarks(dev);
2991         intel_clear_scanline_wait(dev);
2992 }
2993
2994 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2995 {
2996         /* XXX: When our outputs are all unaware of DPMS modes other than off
2997          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2998          */
2999         switch (mode) {
3000         case DRM_MODE_DPMS_ON:
3001         case DRM_MODE_DPMS_STANDBY:
3002         case DRM_MODE_DPMS_SUSPEND:
3003                 i9xx_crtc_enable(crtc);
3004                 break;
3005         case DRM_MODE_DPMS_OFF:
3006                 i9xx_crtc_disable(crtc);
3007                 break;
3008         }
3009 }
3010
3011 /**
3012  * Sets the power management mode of the pipe and plane.
3013  */
3014 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3015 {
3016         struct drm_device *dev = crtc->dev;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         struct drm_i915_master_private *master_priv;
3019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020         int pipe = intel_crtc->pipe;
3021         bool enabled;
3022
3023         if (intel_crtc->dpms_mode == mode)
3024                 return;
3025
3026         intel_crtc->dpms_mode = mode;
3027
3028         dev_priv->display.dpms(crtc, mode);
3029
3030         if (!dev->primary->master)
3031                 return;
3032
3033         master_priv = dev->primary->master->driver_priv;
3034         if (!master_priv->sarea_priv)
3035                 return;
3036
3037         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3038
3039         switch (pipe) {
3040         case 0:
3041                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3042                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3043                 break;
3044         case 1:
3045                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3046                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3047                 break;
3048         default:
3049                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3050                 break;
3051         }
3052 }
3053
3054 static void intel_crtc_disable(struct drm_crtc *crtc)
3055 {
3056         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3057         struct drm_device *dev = crtc->dev;
3058
3059         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3060
3061         if (crtc->fb) {
3062                 mutex_lock(&dev->struct_mutex);
3063                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3064                 mutex_unlock(&dev->struct_mutex);
3065         }
3066 }
3067
3068 /* Prepare for a mode set.
3069  *
3070  * Note we could be a lot smarter here.  We need to figure out which outputs
3071  * will be enabled, which disabled (in short, how the config will changes)
3072  * and perform the minimum necessary steps to accomplish that, e.g. updating
3073  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3074  * panel fitting is in the proper state, etc.
3075  */
3076 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3077 {
3078         i9xx_crtc_disable(crtc);
3079 }
3080
3081 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3082 {
3083         i9xx_crtc_enable(crtc);
3084 }
3085
3086 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3087 {
3088         ironlake_crtc_disable(crtc);
3089 }
3090
3091 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3092 {
3093         ironlake_crtc_enable(crtc);
3094 }
3095
3096 void intel_encoder_prepare (struct drm_encoder *encoder)
3097 {
3098         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3099         /* lvds has its own version of prepare see intel_lvds_prepare */
3100         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3101 }
3102
3103 void intel_encoder_commit (struct drm_encoder *encoder)
3104 {
3105         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3106         /* lvds has its own version of commit see intel_lvds_commit */
3107         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3108 }
3109
3110 void intel_encoder_destroy(struct drm_encoder *encoder)
3111 {
3112         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3113
3114         drm_encoder_cleanup(encoder);
3115         kfree(intel_encoder);
3116 }
3117
3118 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3119                                   struct drm_display_mode *mode,
3120                                   struct drm_display_mode *adjusted_mode)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123
3124         if (HAS_PCH_SPLIT(dev)) {
3125                 /* FDI link clock is fixed at 2.7G */
3126                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3127                         return false;
3128         }
3129
3130         /* XXX some encoders set the crtcinfo, others don't.
3131          * Obviously we need some form of conflict resolution here...
3132          */
3133         if (adjusted_mode->crtc_htotal == 0)
3134                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3135
3136         return true;
3137 }
3138
3139 static int i945_get_display_clock_speed(struct drm_device *dev)
3140 {
3141         return 400000;
3142 }
3143
3144 static int i915_get_display_clock_speed(struct drm_device *dev)
3145 {
3146         return 333000;
3147 }
3148
3149 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3150 {
3151         return 200000;
3152 }
3153
3154 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3155 {
3156         u16 gcfgc = 0;
3157
3158         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3159
3160         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3161                 return 133000;
3162         else {
3163                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3164                 case GC_DISPLAY_CLOCK_333_MHZ:
3165                         return 333000;
3166                 default:
3167                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3168                         return 190000;
3169                 }
3170         }
3171 }
3172
3173 static int i865_get_display_clock_speed(struct drm_device *dev)
3174 {
3175         return 266000;
3176 }
3177
3178 static int i855_get_display_clock_speed(struct drm_device *dev)
3179 {
3180         u16 hpllcc = 0;
3181         /* Assume that the hardware is in the high speed state.  This
3182          * should be the default.
3183          */
3184         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3185         case GC_CLOCK_133_200:
3186         case GC_CLOCK_100_200:
3187                 return 200000;
3188         case GC_CLOCK_166_250:
3189                 return 250000;
3190         case GC_CLOCK_100_133:
3191                 return 133000;
3192         }
3193
3194         /* Shouldn't happen */
3195         return 0;
3196 }
3197
3198 static int i830_get_display_clock_speed(struct drm_device *dev)
3199 {
3200         return 133000;
3201 }
3202
3203 struct fdi_m_n {
3204         u32        tu;
3205         u32        gmch_m;
3206         u32        gmch_n;
3207         u32        link_m;
3208         u32        link_n;
3209 };
3210
3211 static void
3212 fdi_reduce_ratio(u32 *num, u32 *den)
3213 {
3214         while (*num > 0xffffff || *den > 0xffffff) {
3215                 *num >>= 1;
3216                 *den >>= 1;
3217         }
3218 }
3219
3220 static void
3221 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3222                      int link_clock, struct fdi_m_n *m_n)
3223 {
3224         m_n->tu = 64; /* default size */
3225
3226         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3227         m_n->gmch_m = bits_per_pixel * pixel_clock;
3228         m_n->gmch_n = link_clock * nlanes * 8;
3229         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3230
3231         m_n->link_m = pixel_clock;
3232         m_n->link_n = link_clock;
3233         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3234 }
3235
3236
3237 struct intel_watermark_params {
3238         unsigned long fifo_size;
3239         unsigned long max_wm;
3240         unsigned long default_wm;
3241         unsigned long guard_size;
3242         unsigned long cacheline_size;
3243 };
3244
3245 /* Pineview has different values for various configs */
3246 static const struct intel_watermark_params pineview_display_wm = {
3247         PINEVIEW_DISPLAY_FIFO,
3248         PINEVIEW_MAX_WM,
3249         PINEVIEW_DFT_WM,
3250         PINEVIEW_GUARD_WM,
3251         PINEVIEW_FIFO_LINE_SIZE
3252 };
3253 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3254         PINEVIEW_DISPLAY_FIFO,
3255         PINEVIEW_MAX_WM,
3256         PINEVIEW_DFT_HPLLOFF_WM,
3257         PINEVIEW_GUARD_WM,
3258         PINEVIEW_FIFO_LINE_SIZE
3259 };
3260 static const struct intel_watermark_params pineview_cursor_wm = {
3261         PINEVIEW_CURSOR_FIFO,
3262         PINEVIEW_CURSOR_MAX_WM,
3263         PINEVIEW_CURSOR_DFT_WM,
3264         PINEVIEW_CURSOR_GUARD_WM,
3265         PINEVIEW_FIFO_LINE_SIZE,
3266 };
3267 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3268         PINEVIEW_CURSOR_FIFO,
3269         PINEVIEW_CURSOR_MAX_WM,
3270         PINEVIEW_CURSOR_DFT_WM,
3271         PINEVIEW_CURSOR_GUARD_WM,
3272         PINEVIEW_FIFO_LINE_SIZE
3273 };
3274 static const struct intel_watermark_params g4x_wm_info = {
3275         G4X_FIFO_SIZE,
3276         G4X_MAX_WM,
3277         G4X_MAX_WM,
3278         2,
3279         G4X_FIFO_LINE_SIZE,
3280 };
3281 static const struct intel_watermark_params g4x_cursor_wm_info = {
3282         I965_CURSOR_FIFO,
3283         I965_CURSOR_MAX_WM,
3284         I965_CURSOR_DFT_WM,
3285         2,
3286         G4X_FIFO_LINE_SIZE,
3287 };
3288 static const struct intel_watermark_params i965_cursor_wm_info = {
3289         I965_CURSOR_FIFO,
3290         I965_CURSOR_MAX_WM,
3291         I965_CURSOR_DFT_WM,
3292         2,
3293         I915_FIFO_LINE_SIZE,
3294 };
3295 static const struct intel_watermark_params i945_wm_info = {
3296         I945_FIFO_SIZE,
3297         I915_MAX_WM,
3298         1,
3299         2,
3300         I915_FIFO_LINE_SIZE
3301 };
3302 static const struct intel_watermark_params i915_wm_info = {
3303         I915_FIFO_SIZE,
3304         I915_MAX_WM,
3305         1,
3306         2,
3307         I915_FIFO_LINE_SIZE
3308 };
3309 static const struct intel_watermark_params i855_wm_info = {
3310         I855GM_FIFO_SIZE,
3311         I915_MAX_WM,
3312         1,
3313         2,
3314         I830_FIFO_LINE_SIZE
3315 };
3316 static const struct intel_watermark_params i830_wm_info = {
3317         I830_FIFO_SIZE,
3318         I915_MAX_WM,
3319         1,
3320         2,
3321         I830_FIFO_LINE_SIZE
3322 };
3323
3324 static const struct intel_watermark_params ironlake_display_wm_info = {
3325         ILK_DISPLAY_FIFO,
3326         ILK_DISPLAY_MAXWM,
3327         ILK_DISPLAY_DFTWM,
3328         2,
3329         ILK_FIFO_LINE_SIZE
3330 };
3331 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3332         ILK_CURSOR_FIFO,
3333         ILK_CURSOR_MAXWM,
3334         ILK_CURSOR_DFTWM,
3335         2,
3336         ILK_FIFO_LINE_SIZE
3337 };
3338 static const struct intel_watermark_params ironlake_display_srwm_info = {
3339         ILK_DISPLAY_SR_FIFO,
3340         ILK_DISPLAY_MAX_SRWM,
3341         ILK_DISPLAY_DFT_SRWM,
3342         2,
3343         ILK_FIFO_LINE_SIZE
3344 };
3345 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3346         ILK_CURSOR_SR_FIFO,
3347         ILK_CURSOR_MAX_SRWM,
3348         ILK_CURSOR_DFT_SRWM,
3349         2,
3350         ILK_FIFO_LINE_SIZE
3351 };
3352
3353 static const struct intel_watermark_params sandybridge_display_wm_info = {
3354         SNB_DISPLAY_FIFO,
3355         SNB_DISPLAY_MAXWM,
3356         SNB_DISPLAY_DFTWM,
3357         2,
3358         SNB_FIFO_LINE_SIZE
3359 };
3360 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3361         SNB_CURSOR_FIFO,
3362         SNB_CURSOR_MAXWM,
3363         SNB_CURSOR_DFTWM,
3364         2,
3365         SNB_FIFO_LINE_SIZE
3366 };
3367 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3368         SNB_DISPLAY_SR_FIFO,
3369         SNB_DISPLAY_MAX_SRWM,
3370         SNB_DISPLAY_DFT_SRWM,
3371         2,
3372         SNB_FIFO_LINE_SIZE
3373 };
3374 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3375         SNB_CURSOR_SR_FIFO,
3376         SNB_CURSOR_MAX_SRWM,
3377         SNB_CURSOR_DFT_SRWM,
3378         2,
3379         SNB_FIFO_LINE_SIZE
3380 };
3381
3382
3383 /**
3384  * intel_calculate_wm - calculate watermark level
3385  * @clock_in_khz: pixel clock
3386  * @wm: chip FIFO params
3387  * @pixel_size: display pixel size
3388  * @latency_ns: memory latency for the platform
3389  *
3390  * Calculate the watermark level (the level at which the display plane will
3391  * start fetching from memory again).  Each chip has a different display
3392  * FIFO size and allocation, so the caller needs to figure that out and pass
3393  * in the correct intel_watermark_params structure.
3394  *
3395  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3396  * on the pixel size.  When it reaches the watermark level, it'll start
3397  * fetching FIFO line sized based chunks from memory until the FIFO fills
3398  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3399  * will occur, and a display engine hang could result.
3400  */
3401 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3402                                         const struct intel_watermark_params *wm,
3403                                         int fifo_size,
3404                                         int pixel_size,
3405                                         unsigned long latency_ns)
3406 {
3407         long entries_required, wm_size;
3408
3409         /*
3410          * Note: we need to make sure we don't overflow for various clock &
3411          * latency values.
3412          * clocks go from a few thousand to several hundred thousand.
3413          * latency is usually a few thousand
3414          */
3415         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3416                 1000;
3417         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3418
3419         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3420
3421         wm_size = fifo_size - (entries_required + wm->guard_size);
3422
3423         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3424
3425         /* Don't promote wm_size to unsigned... */
3426         if (wm_size > (long)wm->max_wm)
3427                 wm_size = wm->max_wm;
3428         if (wm_size <= 0)
3429                 wm_size = wm->default_wm;
3430         return wm_size;
3431 }
3432
3433 struct cxsr_latency {
3434         int is_desktop;
3435         int is_ddr3;
3436         unsigned long fsb_freq;
3437         unsigned long mem_freq;
3438         unsigned long display_sr;
3439         unsigned long display_hpll_disable;
3440         unsigned long cursor_sr;
3441         unsigned long cursor_hpll_disable;
3442 };
3443
3444 static const struct cxsr_latency cxsr_latency_table[] = {
3445         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3446         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3447         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3448         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3449         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3450
3451         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3452         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3453         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3454         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3455         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3456
3457         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3458         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3459         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3460         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3461         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3462
3463         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3464         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3465         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3466         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3467         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3468
3469         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3470         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3471         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3472         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3473         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3474
3475         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3476         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3477         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3478         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3479         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3480 };
3481
3482 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3483                                                          int is_ddr3,
3484                                                          int fsb,
3485                                                          int mem)
3486 {
3487         const struct cxsr_latency *latency;
3488         int i;
3489
3490         if (fsb == 0 || mem == 0)
3491                 return NULL;
3492
3493         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3494                 latency = &cxsr_latency_table[i];
3495                 if (is_desktop == latency->is_desktop &&
3496                     is_ddr3 == latency->is_ddr3 &&
3497                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3498                         return latency;
3499         }
3500
3501         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3502
3503         return NULL;
3504 }
3505
3506 static void pineview_disable_cxsr(struct drm_device *dev)
3507 {
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509
3510         /* deactivate cxsr */
3511         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3512 }
3513
3514 /*
3515  * Latency for FIFO fetches is dependent on several factors:
3516  *   - memory configuration (speed, channels)
3517  *   - chipset
3518  *   - current MCH state
3519  * It can be fairly high in some situations, so here we assume a fairly
3520  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3521  * set this value too high, the FIFO will fetch frequently to stay full)
3522  * and power consumption (set it too low to save power and we might see
3523  * FIFO underruns and display "flicker").
3524  *
3525  * A value of 5us seems to be a good balance; safe for very low end
3526  * platforms but not overly aggressive on lower latency configs.
3527  */
3528 static const int latency_ns = 5000;
3529
3530 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3531 {
3532         struct drm_i915_private *dev_priv = dev->dev_private;
3533         uint32_t dsparb = I915_READ(DSPARB);
3534         int size;
3535
3536         size = dsparb & 0x7f;
3537         if (plane)
3538                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3539
3540         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3541                       plane ? "B" : "A", size);
3542
3543         return size;
3544 }
3545
3546 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3547 {
3548         struct drm_i915_private *dev_priv = dev->dev_private;
3549         uint32_t dsparb = I915_READ(DSPARB);
3550         int size;
3551
3552         size = dsparb & 0x1ff;
3553         if (plane)
3554                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3555         size >>= 1; /* Convert to cachelines */
3556
3557         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3558                       plane ? "B" : "A", size);
3559
3560         return size;
3561 }
3562
3563 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3564 {
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566         uint32_t dsparb = I915_READ(DSPARB);
3567         int size;
3568
3569         size = dsparb & 0x7f;
3570         size >>= 2; /* Convert to cachelines */
3571
3572         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3573                       plane ? "B" : "A",
3574                       size);
3575
3576         return size;
3577 }
3578
3579 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3580 {
3581         struct drm_i915_private *dev_priv = dev->dev_private;
3582         uint32_t dsparb = I915_READ(DSPARB);
3583         int size;
3584
3585         size = dsparb & 0x7f;
3586         size >>= 1; /* Convert to cachelines */
3587
3588         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3589                       plane ? "B" : "A", size);
3590
3591         return size;
3592 }
3593
3594 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3595 {
3596         struct drm_crtc *crtc, *enabled = NULL;
3597
3598         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3599                 if (crtc->enabled && crtc->fb) {
3600                         if (enabled)
3601                                 return NULL;
3602                         enabled = crtc;
3603                 }
3604         }
3605
3606         return enabled;
3607 }
3608
3609 static void pineview_update_wm(struct drm_device *dev)
3610 {
3611         struct drm_i915_private *dev_priv = dev->dev_private;
3612         struct drm_crtc *crtc;
3613         const struct cxsr_latency *latency;
3614         u32 reg;
3615         unsigned long wm;
3616
3617         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3618                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3619         if (!latency) {
3620                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3621                 pineview_disable_cxsr(dev);
3622                 return;
3623         }
3624
3625         crtc = single_enabled_crtc(dev);
3626         if (crtc) {
3627                 int clock = crtc->mode.clock;
3628                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3629
3630                 /* Display SR */
3631                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3632                                         pineview_display_wm.fifo_size,
3633                                         pixel_size, latency->display_sr);
3634                 reg = I915_READ(DSPFW1);
3635                 reg &= ~DSPFW_SR_MASK;
3636                 reg |= wm << DSPFW_SR_SHIFT;
3637                 I915_WRITE(DSPFW1, reg);
3638                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3639
3640                 /* cursor SR */
3641                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3642                                         pineview_display_wm.fifo_size,
3643                                         pixel_size, latency->cursor_sr);
3644                 reg = I915_READ(DSPFW3);
3645                 reg &= ~DSPFW_CURSOR_SR_MASK;
3646                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3647                 I915_WRITE(DSPFW3, reg);
3648
3649                 /* Display HPLL off SR */
3650                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3651                                         pineview_display_hplloff_wm.fifo_size,
3652                                         pixel_size, latency->display_hpll_disable);
3653                 reg = I915_READ(DSPFW3);
3654                 reg &= ~DSPFW_HPLL_SR_MASK;
3655                 reg |= wm & DSPFW_HPLL_SR_MASK;
3656                 I915_WRITE(DSPFW3, reg);
3657
3658                 /* cursor HPLL off SR */
3659                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3660                                         pineview_display_hplloff_wm.fifo_size,
3661                                         pixel_size, latency->cursor_hpll_disable);
3662                 reg = I915_READ(DSPFW3);
3663                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3664                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3665                 I915_WRITE(DSPFW3, reg);
3666                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3667
3668                 /* activate cxsr */
3669                 I915_WRITE(DSPFW3,
3670                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3671                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3672         } else {
3673                 pineview_disable_cxsr(dev);
3674                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3675         }
3676 }
3677
3678 static bool g4x_compute_wm0(struct drm_device *dev,
3679                             int plane,
3680                             const struct intel_watermark_params *display,
3681                             int display_latency_ns,
3682                             const struct intel_watermark_params *cursor,
3683                             int cursor_latency_ns,
3684                             int *plane_wm,
3685                             int *cursor_wm)
3686 {
3687         struct drm_crtc *crtc;
3688         int htotal, hdisplay, clock, pixel_size;
3689         int line_time_us, line_count;
3690         int entries, tlb_miss;
3691
3692         crtc = intel_get_crtc_for_plane(dev, plane);
3693         if (crtc->fb == NULL || !crtc->enabled) {
3694                 *cursor_wm = cursor->guard_size;
3695                 *plane_wm = display->guard_size;
3696                 return false;
3697         }
3698
3699         htotal = crtc->mode.htotal;
3700         hdisplay = crtc->mode.hdisplay;
3701         clock = crtc->mode.clock;
3702         pixel_size = crtc->fb->bits_per_pixel / 8;
3703
3704         /* Use the small buffer method to calculate plane watermark */
3705         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3706         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3707         if (tlb_miss > 0)
3708                 entries += tlb_miss;
3709         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3710         *plane_wm = entries + display->guard_size;
3711         if (*plane_wm > (int)display->max_wm)
3712                 *plane_wm = display->max_wm;
3713
3714         /* Use the large buffer method to calculate cursor watermark */
3715         line_time_us = ((htotal * 1000) / clock);
3716         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3717         entries = line_count * 64 * pixel_size;
3718         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3719         if (tlb_miss > 0)
3720                 entries += tlb_miss;
3721         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3722         *cursor_wm = entries + cursor->guard_size;
3723         if (*cursor_wm > (int)cursor->max_wm)
3724                 *cursor_wm = (int)cursor->max_wm;
3725
3726         return true;
3727 }
3728
3729 /*
3730  * Check the wm result.
3731  *
3732  * If any calculated watermark values is larger than the maximum value that
3733  * can be programmed into the associated watermark register, that watermark
3734  * must be disabled.
3735  */
3736 static bool g4x_check_srwm(struct drm_device *dev,
3737                            int display_wm, int cursor_wm,
3738                            const struct intel_watermark_params *display,
3739                            const struct intel_watermark_params *cursor)
3740 {
3741         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3742                       display_wm, cursor_wm);
3743
3744         if (display_wm > display->max_wm) {
3745                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3746                               display_wm, display->max_wm);
3747                 return false;
3748         }
3749
3750         if (cursor_wm > cursor->max_wm) {
3751                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3752                               cursor_wm, cursor->max_wm);
3753                 return false;
3754         }
3755
3756         if (!(display_wm || cursor_wm)) {
3757                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3758                 return false;
3759         }
3760
3761         return true;
3762 }
3763
3764 static bool g4x_compute_srwm(struct drm_device *dev,
3765                              int plane,
3766                              int latency_ns,
3767                              const struct intel_watermark_params *display,
3768                              const struct intel_watermark_params *cursor,
3769                              int *display_wm, int *cursor_wm)
3770 {
3771         struct drm_crtc *crtc;
3772         int hdisplay, htotal, pixel_size, clock;
3773         unsigned long line_time_us;
3774         int line_count, line_size;
3775         int small, large;
3776         int entries;
3777
3778         if (!latency_ns) {
3779                 *display_wm = *cursor_wm = 0;
3780                 return false;
3781         }
3782
3783         crtc = intel_get_crtc_for_plane(dev, plane);
3784         hdisplay = crtc->mode.hdisplay;
3785         htotal = crtc->mode.htotal;
3786         clock = crtc->mode.clock;
3787         pixel_size = crtc->fb->bits_per_pixel / 8;
3788
3789         line_time_us = (htotal * 1000) / clock;
3790         line_count = (latency_ns / line_time_us + 1000) / 1000;
3791         line_size = hdisplay * pixel_size;
3792
3793         /* Use the minimum of the small and large buffer method for primary */
3794         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3795         large = line_count * line_size;
3796
3797         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3798         *display_wm = entries + display->guard_size;
3799
3800         /* calculate the self-refresh watermark for display cursor */
3801         entries = line_count * pixel_size * 64;
3802         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3803         *cursor_wm = entries + cursor->guard_size;
3804
3805         return g4x_check_srwm(dev,
3806                               *display_wm, *cursor_wm,
3807                               display, cursor);
3808 }
3809
3810 #define single_plane_enabled(mask) is_power_of_2(mask)
3811
3812 static void g4x_update_wm(struct drm_device *dev)
3813 {
3814         static const int sr_latency_ns = 12000;
3815         struct drm_i915_private *dev_priv = dev->dev_private;
3816         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3817         int plane_sr, cursor_sr;
3818         unsigned int enabled = 0;
3819
3820         if (g4x_compute_wm0(dev, 0,
3821                             &g4x_wm_info, latency_ns,
3822                             &g4x_cursor_wm_info, latency_ns,
3823                             &planea_wm, &cursora_wm))
3824                 enabled |= 1;
3825
3826         if (g4x_compute_wm0(dev, 1,
3827                             &g4x_wm_info, latency_ns,
3828                             &g4x_cursor_wm_info, latency_ns,
3829                             &planeb_wm, &cursorb_wm))
3830                 enabled |= 2;
3831
3832         plane_sr = cursor_sr = 0;
3833         if (single_plane_enabled(enabled) &&
3834             g4x_compute_srwm(dev, ffs(enabled) - 1,
3835                              sr_latency_ns,
3836                              &g4x_wm_info,
3837                              &g4x_cursor_wm_info,
3838                              &plane_sr, &cursor_sr))
3839                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3840         else
3841                 I915_WRITE(FW_BLC_SELF,
3842                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3843
3844         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3845                       planea_wm, cursora_wm,
3846                       planeb_wm, cursorb_wm,
3847                       plane_sr, cursor_sr);
3848
3849         I915_WRITE(DSPFW1,
3850                    (plane_sr << DSPFW_SR_SHIFT) |
3851                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3852                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3853                    planea_wm);
3854         I915_WRITE(DSPFW2,
3855                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3856                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3857         /* HPLL off in SR has some issues on G4x... disable it */
3858         I915_WRITE(DSPFW3,
3859                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3860                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3861 }
3862
3863 static void i965_update_wm(struct drm_device *dev)
3864 {
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         struct drm_crtc *crtc;
3867         int srwm = 1;
3868         int cursor_sr = 16;
3869
3870         /* Calc sr entries for one plane configs */
3871         crtc = single_enabled_crtc(dev);
3872         if (crtc) {
3873                 /* self-refresh has much higher latency */
3874                 static const int sr_latency_ns = 12000;
3875                 int clock = crtc->mode.clock;
3876                 int htotal = crtc->mode.htotal;
3877                 int hdisplay = crtc->mode.hdisplay;
3878                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3879                 unsigned long line_time_us;
3880                 int entries;
3881
3882                 line_time_us = ((htotal * 1000) / clock);
3883
3884                 /* Use ns/us then divide to preserve precision */
3885                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3886                         pixel_size * hdisplay;
3887                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3888                 srwm = I965_FIFO_SIZE - entries;
3889                 if (srwm < 0)
3890                         srwm = 1;
3891                 srwm &= 0x1ff;
3892                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3893                               entries, srwm);
3894
3895                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3896                         pixel_size * 64;
3897                 entries = DIV_ROUND_UP(entries,
3898                                           i965_cursor_wm_info.cacheline_size);
3899                 cursor_sr = i965_cursor_wm_info.fifo_size -
3900                         (entries + i965_cursor_wm_info.guard_size);
3901
3902                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3903                         cursor_sr = i965_cursor_wm_info.max_wm;
3904
3905                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3906                               "cursor %d\n", srwm, cursor_sr);
3907
3908                 if (IS_CRESTLINE(dev))
3909                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3910         } else {
3911                 /* Turn off self refresh if both pipes are enabled */
3912                 if (IS_CRESTLINE(dev))
3913                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3914                                    & ~FW_BLC_SELF_EN);
3915         }
3916
3917         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3918                       srwm);
3919
3920         /* 965 has limitations... */
3921         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3922                    (8 << 16) | (8 << 8) | (8 << 0));
3923         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3924         /* update cursor SR watermark */
3925         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3926 }
3927
3928 static void i9xx_update_wm(struct drm_device *dev)
3929 {
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         const struct intel_watermark_params *wm_info;
3932         uint32_t fwater_lo;
3933         uint32_t fwater_hi;
3934         int cwm, srwm = 1;
3935         int fifo_size;
3936         int planea_wm, planeb_wm;
3937         struct drm_crtc *crtc, *enabled = NULL;
3938
3939         if (IS_I945GM(dev))
3940                 wm_info = &i945_wm_info;
3941         else if (!IS_GEN2(dev))
3942                 wm_info = &i915_wm_info;
3943         else
3944                 wm_info = &i855_wm_info;
3945
3946         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3947         crtc = intel_get_crtc_for_plane(dev, 0);
3948         if (crtc->enabled && crtc->fb) {
3949                 planea_wm = intel_calculate_wm(crtc->mode.clock,
3950                                                wm_info, fifo_size,
3951                                                crtc->fb->bits_per_pixel / 8,
3952                                                latency_ns);
3953                 enabled = crtc;
3954         } else
3955                 planea_wm = fifo_size - wm_info->guard_size;
3956
3957         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3958         crtc = intel_get_crtc_for_plane(dev, 1);
3959         if (crtc->enabled && crtc->fb) {
3960                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3961                                                wm_info, fifo_size,
3962                                                crtc->fb->bits_per_pixel / 8,
3963                                                latency_ns);
3964                 if (enabled == NULL)
3965                         enabled = crtc;
3966                 else
3967                         enabled = NULL;
3968         } else
3969                 planeb_wm = fifo_size - wm_info->guard_size;
3970
3971         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3972
3973         /*
3974          * Overlay gets an aggressive default since video jitter is bad.
3975          */
3976         cwm = 2;
3977
3978         /* Play safe and disable self-refresh before adjusting watermarks. */
3979         if (IS_I945G(dev) || IS_I945GM(dev))
3980                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3981         else if (IS_I915GM(dev))
3982                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3983
3984         /* Calc sr entries for one plane configs */
3985         if (HAS_FW_BLC(dev) && enabled) {
3986                 /* self-refresh has much higher latency */
3987                 static const int sr_latency_ns = 6000;
3988                 int clock = enabled->mode.clock;
3989                 int htotal = enabled->mode.htotal;
3990                 int hdisplay = enabled->mode.hdisplay;
3991                 int pixel_size = enabled->fb->bits_per_pixel / 8;
3992                 unsigned long line_time_us;
3993                 int entries;
3994
3995                 line_time_us = (htotal * 1000) / clock;
3996
3997                 /* Use ns/us then divide to preserve precision */
3998                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3999                         pixel_size * hdisplay;
4000                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4001                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4002                 srwm = wm_info->fifo_size - entries;
4003                 if (srwm < 0)
4004                         srwm = 1;
4005
4006                 if (IS_I945G(dev) || IS_I945GM(dev))
4007                         I915_WRITE(FW_BLC_SELF,
4008                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4009                 else if (IS_I915GM(dev))
4010                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4011         }
4012
4013         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4014                       planea_wm, planeb_wm, cwm, srwm);
4015
4016         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4017         fwater_hi = (cwm & 0x1f);
4018
4019         /* Set request length to 8 cachelines per fetch */
4020         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4021         fwater_hi = fwater_hi | (1 << 8);
4022
4023         I915_WRITE(FW_BLC, fwater_lo);
4024         I915_WRITE(FW_BLC2, fwater_hi);
4025
4026         if (HAS_FW_BLC(dev)) {
4027                 if (enabled) {
4028                         if (IS_I945G(dev) || IS_I945GM(dev))
4029                                 I915_WRITE(FW_BLC_SELF,
4030                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4031                         else if (IS_I915GM(dev))
4032                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4033                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4034                 } else
4035                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4036         }
4037 }
4038
4039 static void i830_update_wm(struct drm_device *dev)
4040 {
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042         struct drm_crtc *crtc;
4043         uint32_t fwater_lo;
4044         int planea_wm;
4045
4046         crtc = single_enabled_crtc(dev);
4047         if (crtc == NULL)
4048                 return;
4049
4050         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4051                                        dev_priv->display.get_fifo_size(dev, 0),
4052                                        crtc->fb->bits_per_pixel / 8,
4053                                        latency_ns);
4054         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4055         fwater_lo |= (3<<8) | planea_wm;
4056
4057         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4058
4059         I915_WRITE(FW_BLC, fwater_lo);
4060 }
4061
4062 #define ILK_LP0_PLANE_LATENCY           700
4063 #define ILK_LP0_CURSOR_LATENCY          1300
4064
4065 /*
4066  * Check the wm result.
4067  *
4068  * If any calculated watermark values is larger than the maximum value that
4069  * can be programmed into the associated watermark register, that watermark
4070  * must be disabled.
4071  */
4072 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4073                                 int fbc_wm, int display_wm, int cursor_wm,
4074                                 const struct intel_watermark_params *display,
4075                                 const struct intel_watermark_params *cursor)
4076 {
4077         struct drm_i915_private *dev_priv = dev->dev_private;
4078
4079         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4080                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4081
4082         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4083                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4084                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4085
4086                 /* fbc has it's own way to disable FBC WM */
4087                 I915_WRITE(DISP_ARB_CTL,
4088                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4089                 return false;
4090         }
4091
4092         if (display_wm > display->max_wm) {
4093                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4094                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4095                 return false;
4096         }
4097
4098         if (cursor_wm > cursor->max_wm) {
4099                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4100                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4101                 return false;
4102         }
4103
4104         if (!(fbc_wm || display_wm || cursor_wm)) {
4105                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4106                 return false;
4107         }
4108
4109         return true;
4110 }
4111
4112 /*
4113  * Compute watermark values of WM[1-3],
4114  */
4115 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4116                                   int latency_ns,
4117                                   const struct intel_watermark_params *display,
4118                                   const struct intel_watermark_params *cursor,
4119                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4120 {
4121         struct drm_crtc *crtc;
4122         unsigned long line_time_us;
4123         int hdisplay, htotal, pixel_size, clock;
4124         int line_count, line_size;
4125         int small, large;
4126         int entries;
4127
4128         if (!latency_ns) {
4129                 *fbc_wm = *display_wm = *cursor_wm = 0;
4130                 return false;
4131         }
4132
4133         crtc = intel_get_crtc_for_plane(dev, plane);
4134         hdisplay = crtc->mode.hdisplay;
4135         htotal = crtc->mode.htotal;
4136         clock = crtc->mode.clock;
4137         pixel_size = crtc->fb->bits_per_pixel / 8;
4138
4139         line_time_us = (htotal * 1000) / clock;
4140         line_count = (latency_ns / line_time_us + 1000) / 1000;
4141         line_size = hdisplay * pixel_size;
4142
4143         /* Use the minimum of the small and large buffer method for primary */
4144         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4145         large = line_count * line_size;
4146
4147         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4148         *display_wm = entries + display->guard_size;
4149
4150         /*
4151          * Spec says:
4152          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4153          */
4154         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4155
4156         /* calculate the self-refresh watermark for display cursor */
4157         entries = line_count * pixel_size * 64;
4158         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4159         *cursor_wm = entries + cursor->guard_size;
4160
4161         return ironlake_check_srwm(dev, level,
4162                                    *fbc_wm, *display_wm, *cursor_wm,
4163                                    display, cursor);
4164 }
4165
4166 static void ironlake_update_wm(struct drm_device *dev)
4167 {
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         int fbc_wm, plane_wm, cursor_wm;
4170         unsigned int enabled;
4171
4172         enabled = 0;
4173         if (g4x_compute_wm0(dev, 0,
4174                             &ironlake_display_wm_info,
4175                             ILK_LP0_PLANE_LATENCY,
4176                             &ironlake_cursor_wm_info,
4177                             ILK_LP0_CURSOR_LATENCY,
4178                             &plane_wm, &cursor_wm)) {
4179                 I915_WRITE(WM0_PIPEA_ILK,
4180                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4181                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4182                               " plane %d, " "cursor: %d\n",
4183                               plane_wm, cursor_wm);
4184                 enabled |= 1;
4185         }
4186
4187         if (g4x_compute_wm0(dev, 1,
4188                             &ironlake_display_wm_info,
4189                             ILK_LP0_PLANE_LATENCY,
4190                             &ironlake_cursor_wm_info,
4191                             ILK_LP0_CURSOR_LATENCY,
4192                             &plane_wm, &cursor_wm)) {
4193                 I915_WRITE(WM0_PIPEB_ILK,
4194                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4195                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4196                               " plane %d, cursor: %d\n",
4197                               plane_wm, cursor_wm);
4198                 enabled |= 2;
4199         }
4200
4201         /*
4202          * Calculate and update the self-refresh watermark only when one
4203          * display plane is used.
4204          */
4205         I915_WRITE(WM3_LP_ILK, 0);
4206         I915_WRITE(WM2_LP_ILK, 0);
4207         I915_WRITE(WM1_LP_ILK, 0);
4208
4209         if (!single_plane_enabled(enabled))
4210                 return;
4211         enabled = ffs(enabled) - 1;
4212
4213         /* WM1 */
4214         if (!ironlake_compute_srwm(dev, 1, enabled,
4215                                    ILK_READ_WM1_LATENCY() * 500,
4216                                    &ironlake_display_srwm_info,
4217                                    &ironlake_cursor_srwm_info,
4218                                    &fbc_wm, &plane_wm, &cursor_wm))
4219                 return;
4220
4221         I915_WRITE(WM1_LP_ILK,
4222                    WM1_LP_SR_EN |
4223                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4224                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4225                    (plane_wm << WM1_LP_SR_SHIFT) |
4226                    cursor_wm);
4227
4228         /* WM2 */
4229         if (!ironlake_compute_srwm(dev, 2, enabled,
4230                                    ILK_READ_WM2_LATENCY() * 500,
4231                                    &ironlake_display_srwm_info,
4232                                    &ironlake_cursor_srwm_info,
4233                                    &fbc_wm, &plane_wm, &cursor_wm))
4234                 return;
4235
4236         I915_WRITE(WM2_LP_ILK,
4237                    WM2_LP_EN |
4238                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4239                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4240                    (plane_wm << WM1_LP_SR_SHIFT) |
4241                    cursor_wm);
4242
4243         /*
4244          * WM3 is unsupported on ILK, probably because we don't have latency
4245          * data for that power state
4246          */
4247 }
4248
4249 static void sandybridge_update_wm(struct drm_device *dev)
4250 {
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4253         int fbc_wm, plane_wm, cursor_wm;
4254         unsigned int enabled;
4255
4256         enabled = 0;
4257         if (g4x_compute_wm0(dev, 0,
4258                             &sandybridge_display_wm_info, latency,
4259                             &sandybridge_cursor_wm_info, latency,
4260                             &plane_wm, &cursor_wm)) {
4261                 I915_WRITE(WM0_PIPEA_ILK,
4262                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4263                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4264                               " plane %d, " "cursor: %d\n",
4265                               plane_wm, cursor_wm);
4266                 enabled |= 1;
4267         }
4268
4269         if (g4x_compute_wm0(dev, 1,
4270                             &sandybridge_display_wm_info, latency,
4271                             &sandybridge_cursor_wm_info, latency,
4272                             &plane_wm, &cursor_wm)) {
4273                 I915_WRITE(WM0_PIPEB_ILK,
4274                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4275                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4276                               " plane %d, cursor: %d\n",
4277                               plane_wm, cursor_wm);
4278                 enabled |= 2;
4279         }
4280
4281         /*
4282          * Calculate and update the self-refresh watermark only when one
4283          * display plane is used.
4284          *
4285          * SNB support 3 levels of watermark.
4286          *
4287          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4288          * and disabled in the descending order
4289          *
4290          */
4291         I915_WRITE(WM3_LP_ILK, 0);
4292         I915_WRITE(WM2_LP_ILK, 0);
4293         I915_WRITE(WM1_LP_ILK, 0);
4294
4295         if (!single_plane_enabled(enabled))
4296                 return;
4297         enabled = ffs(enabled) - 1;
4298
4299         /* WM1 */
4300         if (!ironlake_compute_srwm(dev, 1, enabled,
4301                                    SNB_READ_WM1_LATENCY() * 500,
4302                                    &sandybridge_display_srwm_info,
4303                                    &sandybridge_cursor_srwm_info,
4304                                    &fbc_wm, &plane_wm, &cursor_wm))
4305                 return;
4306
4307         I915_WRITE(WM1_LP_ILK,
4308                    WM1_LP_SR_EN |
4309                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4310                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4311                    (plane_wm << WM1_LP_SR_SHIFT) |
4312                    cursor_wm);
4313
4314         /* WM2 */
4315         if (!ironlake_compute_srwm(dev, 2, enabled,
4316                                    SNB_READ_WM2_LATENCY() * 500,
4317                                    &sandybridge_display_srwm_info,
4318                                    &sandybridge_cursor_srwm_info,
4319                                    &fbc_wm, &plane_wm, &cursor_wm))
4320                 return;
4321
4322         I915_WRITE(WM2_LP_ILK,
4323                    WM2_LP_EN |
4324                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4325                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4326                    (plane_wm << WM1_LP_SR_SHIFT) |
4327                    cursor_wm);
4328
4329         /* WM3 */
4330         if (!ironlake_compute_srwm(dev, 3, enabled,
4331                                    SNB_READ_WM3_LATENCY() * 500,
4332                                    &sandybridge_display_srwm_info,
4333                                    &sandybridge_cursor_srwm_info,
4334                                    &fbc_wm, &plane_wm, &cursor_wm))
4335                 return;
4336
4337         I915_WRITE(WM3_LP_ILK,
4338                    WM3_LP_EN |
4339                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4340                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4341                    (plane_wm << WM1_LP_SR_SHIFT) |
4342                    cursor_wm);
4343 }
4344
4345 /**
4346  * intel_update_watermarks - update FIFO watermark values based on current modes
4347  *
4348  * Calculate watermark values for the various WM regs based on current mode
4349  * and plane configuration.
4350  *
4351  * There are several cases to deal with here:
4352  *   - normal (i.e. non-self-refresh)
4353  *   - self-refresh (SR) mode
4354  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4355  *   - lines are small relative to FIFO size (buffer can hold more than 2
4356  *     lines), so need to account for TLB latency
4357  *
4358  *   The normal calculation is:
4359  *     watermark = dotclock * bytes per pixel * latency
4360  *   where latency is platform & configuration dependent (we assume pessimal
4361  *   values here).
4362  *
4363  *   The SR calculation is:
4364  *     watermark = (trunc(latency/line time)+1) * surface width *
4365  *       bytes per pixel
4366  *   where
4367  *     line time = htotal / dotclock
4368  *     surface width = hdisplay for normal plane and 64 for cursor
4369  *   and latency is assumed to be high, as above.
4370  *
4371  * The final value programmed to the register should always be rounded up,
4372  * and include an extra 2 entries to account for clock crossings.
4373  *
4374  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4375  * to set the non-SR watermarks to 8.
4376  */
4377 static void intel_update_watermarks(struct drm_device *dev)
4378 {
4379         struct drm_i915_private *dev_priv = dev->dev_private;
4380
4381         if (dev_priv->display.update_wm)
4382                 dev_priv->display.update_wm(dev);
4383 }
4384
4385 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4386 {
4387         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4388 }
4389
4390 /**
4391  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4392  * @crtc: CRTC structure
4393  *
4394  * A pipe may be connected to one or more outputs.  Based on the depth of the
4395  * attached framebuffer, choose a good color depth to use on the pipe.
4396  *
4397  * If possible, match the pipe depth to the fb depth.  In some cases, this
4398  * isn't ideal, because the connected output supports a lesser or restricted
4399  * set of depths.  Resolve that here:
4400  *    LVDS typically supports only 6bpc, so clamp down in that case
4401  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4402  *    Displays may support a restricted set as well, check EDID and clamp as
4403  *      appropriate.
4404  *
4405  * RETURNS:
4406  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4407  * true if they don't match).
4408  */
4409 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4410                                          unsigned int *pipe_bpp)
4411 {
4412         struct drm_device *dev = crtc->dev;
4413         struct drm_i915_private *dev_priv = dev->dev_private;
4414         struct drm_encoder *encoder;
4415         struct drm_connector *connector;
4416         unsigned int display_bpc = UINT_MAX, bpc;
4417
4418         /* Walk the encoders & connectors on this crtc, get min bpc */
4419         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4420                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4421
4422                 if (encoder->crtc != crtc)
4423                         continue;
4424
4425                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4426                         unsigned int lvds_bpc;
4427
4428                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4429                             LVDS_A3_POWER_UP)
4430                                 lvds_bpc = 8;
4431                         else
4432                                 lvds_bpc = 6;
4433
4434                         if (lvds_bpc < display_bpc) {
4435                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4436                                 display_bpc = lvds_bpc;
4437                         }
4438                         continue;
4439                 }
4440
4441                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4442                         /* Use VBT settings if we have an eDP panel */
4443                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4444
4445                         if (edp_bpc < display_bpc) {
4446                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4447                                 display_bpc = edp_bpc;
4448                         }
4449                         continue;
4450                 }
4451
4452                 /* Not one of the known troublemakers, check the EDID */
4453                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4454                                     head) {
4455                         if (connector->encoder != encoder)
4456                                 continue;
4457
4458                         if (connector->display_info.bpc < display_bpc) {
4459                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4460                                 display_bpc = connector->display_info.bpc;
4461                         }
4462                 }
4463
4464                 /*
4465                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4466                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4467                  */
4468                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4469                         if (display_bpc > 8 && display_bpc < 12) {
4470                                 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4471                                 display_bpc = 12;
4472                         } else {
4473                                 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4474                                 display_bpc = 8;
4475                         }
4476                 }
4477         }
4478
4479         /*
4480          * We could just drive the pipe at the highest bpc all the time and
4481          * enable dithering as needed, but that costs bandwidth.  So choose
4482          * the minimum value that expresses the full color range of the fb but
4483          * also stays within the max display bpc discovered above.
4484          */
4485
4486         switch (crtc->fb->depth) {
4487         case 8:
4488                 bpc = 8; /* since we go through a colormap */
4489                 break;
4490         case 15:
4491         case 16:
4492                 bpc = 6; /* min is 18bpp */
4493                 break;
4494         case 24:
4495                 bpc = min((unsigned int)8, display_bpc);
4496                 break;
4497         case 30:
4498                 bpc = min((unsigned int)10, display_bpc);
4499                 break;
4500         case 48:
4501                 bpc = min((unsigned int)12, display_bpc);
4502                 break;
4503         default:
4504                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4505                 bpc = min((unsigned int)8, display_bpc);
4506                 break;
4507         }
4508
4509         DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4510                          bpc, display_bpc);
4511
4512         *pipe_bpp = bpc * 3;
4513
4514         return display_bpc != bpc;
4515 }
4516
4517 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4518                               struct drm_display_mode *mode,
4519                               struct drm_display_mode *adjusted_mode,
4520                               int x, int y,
4521                               struct drm_framebuffer *old_fb)
4522 {
4523         struct drm_device *dev = crtc->dev;
4524         struct drm_i915_private *dev_priv = dev->dev_private;
4525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4526         int pipe = intel_crtc->pipe;
4527         int plane = intel_crtc->plane;
4528         int refclk, num_connectors = 0;
4529         intel_clock_t clock, reduced_clock;
4530         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4531         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4532         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4533         struct drm_mode_config *mode_config = &dev->mode_config;
4534         struct intel_encoder *encoder;
4535         const intel_limit_t *limit;
4536         int ret;
4537         u32 temp;
4538         u32 lvds_sync = 0;
4539
4540         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4541                 if (encoder->base.crtc != crtc)
4542                         continue;
4543
4544                 switch (encoder->type) {
4545                 case INTEL_OUTPUT_LVDS:
4546                         is_lvds = true;
4547                         break;
4548                 case INTEL_OUTPUT_SDVO:
4549                 case INTEL_OUTPUT_HDMI:
4550                         is_sdvo = true;
4551                         if (encoder->needs_tv_clock)
4552                                 is_tv = true;
4553                         break;
4554                 case INTEL_OUTPUT_DVO:
4555                         is_dvo = true;
4556                         break;
4557                 case INTEL_OUTPUT_TVOUT:
4558                         is_tv = true;
4559                         break;
4560                 case INTEL_OUTPUT_ANALOG:
4561                         is_crt = true;
4562                         break;
4563                 case INTEL_OUTPUT_DISPLAYPORT:
4564                         is_dp = true;
4565                         break;
4566                 }
4567
4568                 num_connectors++;
4569         }
4570
4571         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4572                 refclk = dev_priv->lvds_ssc_freq * 1000;
4573                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4574                               refclk / 1000);
4575         } else if (!IS_GEN2(dev)) {
4576                 refclk = 96000;
4577         } else {
4578                 refclk = 48000;
4579         }
4580
4581         /*
4582          * Returns a set of divisors for the desired target clock with the given
4583          * refclk, or FALSE.  The returned values represent the clock equation:
4584          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4585          */
4586         limit = intel_limit(crtc, refclk);
4587         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4588         if (!ok) {
4589                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4590                 return -EINVAL;
4591         }
4592
4593         /* Ensure that the cursor is valid for the new mode before changing... */
4594         intel_crtc_update_cursor(crtc, true);
4595
4596         if (is_lvds && dev_priv->lvds_downclock_avail) {
4597                 has_reduced_clock = limit->find_pll(limit, crtc,
4598                                                     dev_priv->lvds_downclock,
4599                                                     refclk,
4600                                                     &reduced_clock);
4601                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4602                         /*
4603                          * If the different P is found, it means that we can't
4604                          * switch the display clock by using the FP0/FP1.
4605                          * In such case we will disable the LVDS downclock
4606                          * feature.
4607                          */
4608                         DRM_DEBUG_KMS("Different P is found for "
4609                                       "LVDS clock/downclock\n");
4610                         has_reduced_clock = 0;
4611                 }
4612         }
4613         /* SDVO TV has fixed PLL values depend on its clock range,
4614            this mirrors vbios setting. */
4615         if (is_sdvo && is_tv) {
4616                 if (adjusted_mode->clock >= 100000
4617                     && adjusted_mode->clock < 140500) {
4618                         clock.p1 = 2;
4619                         clock.p2 = 10;
4620                         clock.n = 3;
4621                         clock.m1 = 16;
4622                         clock.m2 = 8;
4623                 } else if (adjusted_mode->clock >= 140500
4624                            && adjusted_mode->clock <= 200000) {
4625                         clock.p1 = 1;
4626                         clock.p2 = 10;
4627                         clock.n = 6;
4628                         clock.m1 = 12;
4629                         clock.m2 = 8;
4630                 }
4631         }
4632
4633         if (IS_PINEVIEW(dev)) {
4634                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4635                 if (has_reduced_clock)
4636                         fp2 = (1 << reduced_clock.n) << 16 |
4637                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4638         } else {
4639                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4640                 if (has_reduced_clock)
4641                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4642                                 reduced_clock.m2;
4643         }
4644
4645         dpll = DPLL_VGA_MODE_DIS;
4646
4647         if (!IS_GEN2(dev)) {
4648                 if (is_lvds)
4649                         dpll |= DPLLB_MODE_LVDS;
4650                 else
4651                         dpll |= DPLLB_MODE_DAC_SERIAL;
4652                 if (is_sdvo) {
4653                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4654                         if (pixel_multiplier > 1) {
4655                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4656                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4657                         }
4658                         dpll |= DPLL_DVO_HIGH_SPEED;
4659                 }
4660                 if (is_dp)
4661                         dpll |= DPLL_DVO_HIGH_SPEED;
4662
4663                 /* compute bitmask from p1 value */
4664                 if (IS_PINEVIEW(dev))
4665                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4666                 else {
4667                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4668                         if (IS_G4X(dev) && has_reduced_clock)
4669                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4670                 }
4671                 switch (clock.p2) {
4672                 case 5:
4673                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4674                         break;
4675                 case 7:
4676                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4677                         break;
4678                 case 10:
4679                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4680                         break;
4681                 case 14:
4682                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4683                         break;
4684                 }
4685                 if (INTEL_INFO(dev)->gen >= 4)
4686                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4687         } else {
4688                 if (is_lvds) {
4689                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4690                 } else {
4691                         if (clock.p1 == 2)
4692                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4693                         else
4694                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4695                         if (clock.p2 == 4)
4696                                 dpll |= PLL_P2_DIVIDE_BY_4;
4697                 }
4698         }
4699
4700         if (is_sdvo && is_tv)
4701                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4702         else if (is_tv)
4703                 /* XXX: just matching BIOS for now */
4704                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4705                 dpll |= 3;
4706         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4707                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4708         else
4709                 dpll |= PLL_REF_INPUT_DREFCLK;
4710
4711         /* setup pipeconf */
4712         pipeconf = I915_READ(PIPECONF(pipe));
4713
4714         /* Set up the display plane register */
4715         dspcntr = DISPPLANE_GAMMA_ENABLE;
4716
4717         /* Ironlake's plane is forced to pipe, bit 24 is to
4718            enable color space conversion */
4719         if (pipe == 0)
4720                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4721         else
4722                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4723
4724         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4725                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4726                  * core speed.
4727                  *
4728                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4729                  * pipe == 0 check?
4730                  */
4731                 if (mode->clock >
4732                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4733                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4734                 else
4735                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4736         }
4737
4738         dpll |= DPLL_VCO_ENABLE;
4739
4740         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4741         drm_mode_debug_printmodeline(mode);
4742
4743         I915_WRITE(FP0(pipe), fp);
4744         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4745
4746         POSTING_READ(DPLL(pipe));
4747         udelay(150);
4748
4749         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4750          * This is an exception to the general rule that mode_set doesn't turn
4751          * things on.
4752          */
4753         if (is_lvds) {
4754                 temp = I915_READ(LVDS);
4755                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4756                 if (pipe == 1) {
4757                         temp |= LVDS_PIPEB_SELECT;
4758                 } else {
4759                         temp &= ~LVDS_PIPEB_SELECT;
4760                 }
4761                 /* set the corresponsding LVDS_BORDER bit */
4762                 temp |= dev_priv->lvds_border_bits;
4763                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4764                  * set the DPLLs for dual-channel mode or not.
4765                  */
4766                 if (clock.p2 == 7)
4767                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4768                 else
4769                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4770
4771                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4772                  * appropriately here, but we need to look more thoroughly into how
4773                  * panels behave in the two modes.
4774                  */
4775                 /* set the dithering flag on LVDS as needed */
4776                 if (INTEL_INFO(dev)->gen >= 4) {
4777                         if (dev_priv->lvds_dither)
4778                                 temp |= LVDS_ENABLE_DITHER;
4779                         else
4780                                 temp &= ~LVDS_ENABLE_DITHER;
4781                 }
4782                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4783                         lvds_sync |= LVDS_HSYNC_POLARITY;
4784                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4785                         lvds_sync |= LVDS_VSYNC_POLARITY;
4786                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4787                     != lvds_sync) {
4788                         char flags[2] = "-+";
4789                         DRM_INFO("Changing LVDS panel from "
4790                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4791                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4792                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4793                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4794                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4795                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4796                         temp |= lvds_sync;
4797                 }
4798                 I915_WRITE(LVDS, temp);
4799         }
4800
4801         if (is_dp) {
4802                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4803         }
4804
4805         I915_WRITE(DPLL(pipe), dpll);
4806
4807         /* Wait for the clocks to stabilize. */
4808         POSTING_READ(DPLL(pipe));
4809         udelay(150);
4810
4811         if (INTEL_INFO(dev)->gen >= 4) {
4812                 temp = 0;
4813                 if (is_sdvo) {
4814                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4815                         if (temp > 1)
4816                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4817                         else
4818                                 temp = 0;
4819                 }
4820                 I915_WRITE(DPLL_MD(pipe), temp);
4821         } else {
4822                 /* The pixel multiplier can only be updated once the
4823                  * DPLL is enabled and the clocks are stable.
4824                  *
4825                  * So write it again.
4826                  */
4827                 I915_WRITE(DPLL(pipe), dpll);
4828         }
4829
4830         intel_crtc->lowfreq_avail = false;
4831         if (is_lvds && has_reduced_clock && i915_powersave) {
4832                 I915_WRITE(FP1(pipe), fp2);
4833                 intel_crtc->lowfreq_avail = true;
4834                 if (HAS_PIPE_CXSR(dev)) {
4835                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4836                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4837                 }
4838         } else {
4839                 I915_WRITE(FP1(pipe), fp);
4840                 if (HAS_PIPE_CXSR(dev)) {
4841                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4842                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4843                 }
4844         }
4845
4846         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4847                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4848                 /* the chip adds 2 halflines automatically */
4849                 adjusted_mode->crtc_vdisplay -= 1;
4850                 adjusted_mode->crtc_vtotal -= 1;
4851                 adjusted_mode->crtc_vblank_start -= 1;
4852                 adjusted_mode->crtc_vblank_end -= 1;
4853                 adjusted_mode->crtc_vsync_end -= 1;
4854                 adjusted_mode->crtc_vsync_start -= 1;
4855         } else
4856                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4857
4858         I915_WRITE(HTOTAL(pipe),
4859                    (adjusted_mode->crtc_hdisplay - 1) |
4860                    ((adjusted_mode->crtc_htotal - 1) << 16));
4861         I915_WRITE(HBLANK(pipe),
4862                    (adjusted_mode->crtc_hblank_start - 1) |
4863                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4864         I915_WRITE(HSYNC(pipe),
4865                    (adjusted_mode->crtc_hsync_start - 1) |
4866                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4867
4868         I915_WRITE(VTOTAL(pipe),
4869                    (adjusted_mode->crtc_vdisplay - 1) |
4870                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4871         I915_WRITE(VBLANK(pipe),
4872                    (adjusted_mode->crtc_vblank_start - 1) |
4873                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4874         I915_WRITE(VSYNC(pipe),
4875                    (adjusted_mode->crtc_vsync_start - 1) |
4876                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4877
4878         /* pipesrc and dspsize control the size that is scaled from,
4879          * which should always be the user's requested size.
4880          */
4881         I915_WRITE(DSPSIZE(plane),
4882                    ((mode->vdisplay - 1) << 16) |
4883                    (mode->hdisplay - 1));
4884         I915_WRITE(DSPPOS(plane), 0);
4885         I915_WRITE(PIPESRC(pipe),
4886                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4887
4888         I915_WRITE(PIPECONF(pipe), pipeconf);
4889         POSTING_READ(PIPECONF(pipe));
4890         intel_enable_pipe(dev_priv, pipe, false);
4891
4892         intel_wait_for_vblank(dev, pipe);
4893
4894         I915_WRITE(DSPCNTR(plane), dspcntr);
4895         POSTING_READ(DSPCNTR(plane));
4896         intel_enable_plane(dev_priv, plane, pipe);
4897
4898         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4899
4900         intel_update_watermarks(dev);
4901
4902         return ret;
4903 }
4904
4905 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4906                                   struct drm_display_mode *mode,
4907                                   struct drm_display_mode *adjusted_mode,
4908                                   int x, int y,
4909                                   struct drm_framebuffer *old_fb)
4910 {
4911         struct drm_device *dev = crtc->dev;
4912         struct drm_i915_private *dev_priv = dev->dev_private;
4913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4914         int pipe = intel_crtc->pipe;
4915         int plane = intel_crtc->plane;
4916         int refclk, num_connectors = 0;
4917         intel_clock_t clock, reduced_clock;
4918         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4919         bool ok, has_reduced_clock = false, is_sdvo = false;
4920         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4921         struct intel_encoder *has_edp_encoder = NULL;
4922         struct drm_mode_config *mode_config = &dev->mode_config;
4923         struct intel_encoder *encoder;
4924         const intel_limit_t *limit;
4925         int ret;
4926         struct fdi_m_n m_n = {0};
4927         u32 temp;
4928         u32 lvds_sync = 0;
4929         int target_clock, pixel_multiplier, lane, link_bw, factor;
4930         unsigned int pipe_bpp;
4931         bool dither;
4932
4933         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4934                 if (encoder->base.crtc != crtc)
4935                         continue;
4936
4937                 switch (encoder->type) {
4938                 case INTEL_OUTPUT_LVDS:
4939                         is_lvds = true;
4940                         break;
4941                 case INTEL_OUTPUT_SDVO:
4942                 case INTEL_OUTPUT_HDMI:
4943                         is_sdvo = true;
4944                         if (encoder->needs_tv_clock)
4945                                 is_tv = true;
4946                         break;
4947                 case INTEL_OUTPUT_TVOUT:
4948                         is_tv = true;
4949                         break;
4950                 case INTEL_OUTPUT_ANALOG:
4951                         is_crt = true;
4952                         break;
4953                 case INTEL_OUTPUT_DISPLAYPORT:
4954                         is_dp = true;
4955                         break;
4956                 case INTEL_OUTPUT_EDP:
4957                         has_edp_encoder = encoder;
4958                         break;
4959                 }
4960
4961                 num_connectors++;
4962         }
4963
4964         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4965                 refclk = dev_priv->lvds_ssc_freq * 1000;
4966                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4967                               refclk / 1000);
4968         } else {
4969                 refclk = 96000;
4970                 if (!has_edp_encoder ||
4971                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
4972                         refclk = 120000; /* 120Mhz refclk */
4973         }
4974
4975         /*
4976          * Returns a set of divisors for the desired target clock with the given
4977          * refclk, or FALSE.  The returned values represent the clock equation:
4978          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4979          */
4980         limit = intel_limit(crtc, refclk);
4981         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4982         if (!ok) {
4983                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4984                 return -EINVAL;
4985         }
4986
4987         /* Ensure that the cursor is valid for the new mode before changing... */
4988         intel_crtc_update_cursor(crtc, true);
4989
4990         if (is_lvds && dev_priv->lvds_downclock_avail) {
4991                 has_reduced_clock = limit->find_pll(limit, crtc,
4992                                                     dev_priv->lvds_downclock,
4993                                                     refclk,
4994                                                     &reduced_clock);
4995                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4996                         /*
4997                          * If the different P is found, it means that we can't
4998                          * switch the display clock by using the FP0/FP1.
4999                          * In such case we will disable the LVDS downclock
5000                          * feature.
5001                          */
5002                         DRM_DEBUG_KMS("Different P is found for "
5003                                       "LVDS clock/downclock\n");
5004                         has_reduced_clock = 0;
5005                 }
5006         }
5007         /* SDVO TV has fixed PLL values depend on its clock range,
5008            this mirrors vbios setting. */
5009         if (is_sdvo && is_tv) {
5010                 if (adjusted_mode->clock >= 100000
5011                     && adjusted_mode->clock < 140500) {
5012                         clock.p1 = 2;
5013                         clock.p2 = 10;
5014                         clock.n = 3;
5015                         clock.m1 = 16;
5016                         clock.m2 = 8;
5017                 } else if (adjusted_mode->clock >= 140500
5018                            && adjusted_mode->clock <= 200000) {
5019                         clock.p1 = 1;
5020                         clock.p2 = 10;
5021                         clock.n = 6;
5022                         clock.m1 = 12;
5023                         clock.m2 = 8;
5024                 }
5025         }
5026
5027         /* FDI link */
5028         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5029         lane = 0;
5030         /* CPU eDP doesn't require FDI link, so just set DP M/N
5031            according to current link config */
5032         if (has_edp_encoder &&
5033             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5034                 target_clock = mode->clock;
5035                 intel_edp_link_config(has_edp_encoder,
5036                                       &lane, &link_bw);
5037         } else {
5038                 /* [e]DP over FDI requires target mode clock
5039                    instead of link clock */
5040                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5041                         target_clock = mode->clock;
5042                 else
5043                         target_clock = adjusted_mode->clock;
5044
5045                 /* FDI is a binary signal running at ~2.7GHz, encoding
5046                  * each output octet as 10 bits. The actual frequency
5047                  * is stored as a divider into a 100MHz clock, and the
5048                  * mode pixel clock is stored in units of 1KHz.
5049                  * Hence the bw of each lane in terms of the mode signal
5050                  * is:
5051                  */
5052                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5053         }
5054
5055         /* determine panel color depth */
5056         temp = I915_READ(PIPECONF(pipe));
5057         temp &= ~PIPE_BPC_MASK;
5058         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5059         switch (pipe_bpp) {
5060         case 18:
5061                 temp |= PIPE_6BPC;
5062                 break;
5063         case 24:
5064                 temp |= PIPE_8BPC;
5065                 break;
5066         case 30:
5067                 temp |= PIPE_10BPC;
5068                 break;
5069         case 36:
5070                 temp |= PIPE_12BPC;
5071                 break;
5072         default:
5073                 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5074                 temp |= PIPE_8BPC;
5075                 pipe_bpp = 24;
5076                 break;
5077         }
5078
5079         intel_crtc->bpp = pipe_bpp;
5080         I915_WRITE(PIPECONF(pipe), temp);
5081
5082         if (!lane) {
5083                 /*
5084                  * Account for spread spectrum to avoid
5085                  * oversubscribing the link. Max center spread
5086                  * is 2.5%; use 5% for safety's sake.
5087                  */
5088                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5089                 lane = bps / (link_bw * 8) + 1;
5090         }
5091
5092         intel_crtc->fdi_lanes = lane;
5093
5094         if (pixel_multiplier > 1)
5095                 link_bw *= pixel_multiplier;
5096         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5097                              &m_n);
5098
5099         /* Ironlake: try to setup display ref clock before DPLL
5100          * enabling. This is only under driver's control after
5101          * PCH B stepping, previous chipset stepping should be
5102          * ignoring this setting.
5103          */
5104         temp = I915_READ(PCH_DREF_CONTROL);
5105         /* Always enable nonspread source */
5106         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5107         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5108         temp &= ~DREF_SSC_SOURCE_MASK;
5109         temp |= DREF_SSC_SOURCE_ENABLE;
5110         I915_WRITE(PCH_DREF_CONTROL, temp);
5111
5112         POSTING_READ(PCH_DREF_CONTROL);
5113         udelay(200);
5114
5115         if (has_edp_encoder) {
5116                 if (intel_panel_use_ssc(dev_priv)) {
5117                         temp |= DREF_SSC1_ENABLE;
5118                         I915_WRITE(PCH_DREF_CONTROL, temp);
5119
5120                         POSTING_READ(PCH_DREF_CONTROL);
5121                         udelay(200);
5122                 }
5123                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5124
5125                 /* Enable CPU source on CPU attached eDP */
5126                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5127                         if (intel_panel_use_ssc(dev_priv))
5128                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5129                         else
5130                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5131                 } else {
5132                         /* Enable SSC on PCH eDP if needed */
5133                         if (intel_panel_use_ssc(dev_priv)) {
5134                                 DRM_ERROR("enabling SSC on PCH\n");
5135                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5136                         }
5137                 }
5138                 I915_WRITE(PCH_DREF_CONTROL, temp);
5139                 POSTING_READ(PCH_DREF_CONTROL);
5140                 udelay(200);
5141         }
5142
5143         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5144         if (has_reduced_clock)
5145                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5146                         reduced_clock.m2;
5147
5148         /* Enable autotuning of the PLL clock (if permissible) */
5149         factor = 21;
5150         if (is_lvds) {
5151                 if ((intel_panel_use_ssc(dev_priv) &&
5152                      dev_priv->lvds_ssc_freq == 100) ||
5153                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5154                         factor = 25;
5155         } else if (is_sdvo && is_tv)
5156                 factor = 20;
5157
5158         if (clock.m1 < factor * clock.n)
5159                 fp |= FP_CB_TUNE;
5160
5161         dpll = 0;
5162
5163         if (is_lvds)
5164                 dpll |= DPLLB_MODE_LVDS;
5165         else
5166                 dpll |= DPLLB_MODE_DAC_SERIAL;
5167         if (is_sdvo) {
5168                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5169                 if (pixel_multiplier > 1) {
5170                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5171                 }
5172                 dpll |= DPLL_DVO_HIGH_SPEED;
5173         }
5174         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5175                 dpll |= DPLL_DVO_HIGH_SPEED;
5176
5177         /* compute bitmask from p1 value */
5178         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5179         /* also FPA1 */
5180         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5181
5182         switch (clock.p2) {
5183         case 5:
5184                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5185                 break;
5186         case 7:
5187                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5188                 break;
5189         case 10:
5190                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5191                 break;
5192         case 14:
5193                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5194                 break;
5195         }
5196
5197         if (is_sdvo && is_tv)
5198                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5199         else if (is_tv)
5200                 /* XXX: just matching BIOS for now */
5201                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5202                 dpll |= 3;
5203         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5204                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5205         else
5206                 dpll |= PLL_REF_INPUT_DREFCLK;
5207
5208         /* setup pipeconf */
5209         pipeconf = I915_READ(PIPECONF(pipe));
5210
5211         /* Set up the display plane register */
5212         dspcntr = DISPPLANE_GAMMA_ENABLE;
5213
5214         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5215         drm_mode_debug_printmodeline(mode);
5216
5217         /* PCH eDP needs FDI, but CPU eDP does not */
5218         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5219                 I915_WRITE(PCH_FP0(pipe), fp);
5220                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5221
5222                 POSTING_READ(PCH_DPLL(pipe));
5223                 udelay(150);
5224         }
5225
5226         /* enable transcoder DPLL */
5227         if (HAS_PCH_CPT(dev)) {
5228                 temp = I915_READ(PCH_DPLL_SEL);
5229                 switch (pipe) {
5230                 case 0:
5231                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5232                         break;
5233                 case 1:
5234                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5235                         break;
5236                 case 2:
5237                         /* FIXME: manage transcoder PLLs? */
5238                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5239                         break;
5240                 default:
5241                         BUG();
5242                 }
5243                 I915_WRITE(PCH_DPLL_SEL, temp);
5244
5245                 POSTING_READ(PCH_DPLL_SEL);
5246                 udelay(150);
5247         }
5248
5249         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5250          * This is an exception to the general rule that mode_set doesn't turn
5251          * things on.
5252          */
5253         if (is_lvds) {
5254                 temp = I915_READ(PCH_LVDS);
5255                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5256                 if (pipe == 1) {
5257                         if (HAS_PCH_CPT(dev))
5258                                 temp |= PORT_TRANS_B_SEL_CPT;
5259                         else
5260                                 temp |= LVDS_PIPEB_SELECT;
5261                 } else {
5262                         if (HAS_PCH_CPT(dev))
5263                                 temp &= ~PORT_TRANS_SEL_MASK;
5264                         else
5265                                 temp &= ~LVDS_PIPEB_SELECT;
5266                 }
5267                 /* set the corresponsding LVDS_BORDER bit */
5268                 temp |= dev_priv->lvds_border_bits;
5269                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5270                  * set the DPLLs for dual-channel mode or not.
5271                  */
5272                 if (clock.p2 == 7)
5273                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5274                 else
5275                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5276
5277                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5278                  * appropriately here, but we need to look more thoroughly into how
5279                  * panels behave in the two modes.
5280                  */
5281                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5282                         lvds_sync |= LVDS_HSYNC_POLARITY;
5283                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5284                         lvds_sync |= LVDS_VSYNC_POLARITY;
5285                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5286                     != lvds_sync) {
5287                         char flags[2] = "-+";
5288                         DRM_INFO("Changing LVDS panel from "
5289                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5290                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5291                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5292                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5293                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5294                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5295                         temp |= lvds_sync;
5296                 }
5297                 I915_WRITE(PCH_LVDS, temp);
5298         }
5299
5300         pipeconf &= ~PIPECONF_DITHER_EN;
5301         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5302         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5303                 pipeconf |= PIPECONF_DITHER_EN;
5304                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5305         }
5306         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5307                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5308         } else {
5309                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5310                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5311                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5312                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5313                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5314         }
5315
5316         if (!has_edp_encoder ||
5317             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5318                 I915_WRITE(PCH_DPLL(pipe), dpll);
5319
5320                 /* Wait for the clocks to stabilize. */
5321                 POSTING_READ(PCH_DPLL(pipe));
5322                 udelay(150);
5323
5324                 /* The pixel multiplier can only be updated once the
5325                  * DPLL is enabled and the clocks are stable.
5326                  *
5327                  * So write it again.
5328                  */
5329                 I915_WRITE(PCH_DPLL(pipe), dpll);
5330         }
5331
5332         intel_crtc->lowfreq_avail = false;
5333         if (is_lvds && has_reduced_clock && i915_powersave) {
5334                 I915_WRITE(PCH_FP1(pipe), fp2);
5335                 intel_crtc->lowfreq_avail = true;
5336                 if (HAS_PIPE_CXSR(dev)) {
5337                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5338                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5339                 }
5340         } else {
5341                 I915_WRITE(PCH_FP1(pipe), fp);
5342                 if (HAS_PIPE_CXSR(dev)) {
5343                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5344                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5345                 }
5346         }
5347
5348         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5349                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5350                 /* the chip adds 2 halflines automatically */
5351                 adjusted_mode->crtc_vdisplay -= 1;
5352                 adjusted_mode->crtc_vtotal -= 1;
5353                 adjusted_mode->crtc_vblank_start -= 1;
5354                 adjusted_mode->crtc_vblank_end -= 1;
5355                 adjusted_mode->crtc_vsync_end -= 1;
5356                 adjusted_mode->crtc_vsync_start -= 1;
5357         } else
5358                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5359
5360         I915_WRITE(HTOTAL(pipe),
5361                    (adjusted_mode->crtc_hdisplay - 1) |
5362                    ((adjusted_mode->crtc_htotal - 1) << 16));
5363         I915_WRITE(HBLANK(pipe),
5364                    (adjusted_mode->crtc_hblank_start - 1) |
5365                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5366         I915_WRITE(HSYNC(pipe),
5367                    (adjusted_mode->crtc_hsync_start - 1) |
5368                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5369
5370         I915_WRITE(VTOTAL(pipe),
5371                    (adjusted_mode->crtc_vdisplay - 1) |
5372                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5373         I915_WRITE(VBLANK(pipe),
5374                    (adjusted_mode->crtc_vblank_start - 1) |
5375                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5376         I915_WRITE(VSYNC(pipe),
5377                    (adjusted_mode->crtc_vsync_start - 1) |
5378                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5379
5380         /* pipesrc controls the size that is scaled from, which should
5381          * always be the user's requested size.
5382          */
5383         I915_WRITE(PIPESRC(pipe),
5384                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5385
5386         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5387         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5388         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5389         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5390
5391         if (has_edp_encoder &&
5392             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5393                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5394         }
5395
5396         I915_WRITE(PIPECONF(pipe), pipeconf);
5397         POSTING_READ(PIPECONF(pipe));
5398
5399         intel_wait_for_vblank(dev, pipe);
5400
5401         if (IS_GEN5(dev)) {
5402                 /* enable address swizzle for tiling buffer */
5403                 temp = I915_READ(DISP_ARB_CTL);
5404                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5405         }
5406
5407         I915_WRITE(DSPCNTR(plane), dspcntr);
5408         POSTING_READ(DSPCNTR(plane));
5409
5410         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5411
5412         intel_update_watermarks(dev);
5413
5414         return ret;
5415 }
5416
5417 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5418                                struct drm_display_mode *mode,
5419                                struct drm_display_mode *adjusted_mode,
5420                                int x, int y,
5421                                struct drm_framebuffer *old_fb)
5422 {
5423         struct drm_device *dev = crtc->dev;
5424         struct drm_i915_private *dev_priv = dev->dev_private;
5425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5426         int pipe = intel_crtc->pipe;
5427         int ret;
5428
5429         drm_vblank_pre_modeset(dev, pipe);
5430
5431         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5432                                               x, y, old_fb);
5433
5434         drm_vblank_post_modeset(dev, pipe);
5435
5436         return ret;
5437 }
5438
5439 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5440 void intel_crtc_load_lut(struct drm_crtc *crtc)
5441 {
5442         struct drm_device *dev = crtc->dev;
5443         struct drm_i915_private *dev_priv = dev->dev_private;
5444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5445         int palreg = PALETTE(intel_crtc->pipe);
5446         int i;
5447
5448         /* The clocks have to be on to load the palette. */
5449         if (!crtc->enabled)
5450                 return;
5451
5452         /* use legacy palette for Ironlake */
5453         if (HAS_PCH_SPLIT(dev))
5454                 palreg = LGC_PALETTE(intel_crtc->pipe);
5455
5456         for (i = 0; i < 256; i++) {
5457                 I915_WRITE(palreg + 4 * i,
5458                            (intel_crtc->lut_r[i] << 16) |
5459                            (intel_crtc->lut_g[i] << 8) |
5460                            intel_crtc->lut_b[i]);
5461         }
5462 }
5463
5464 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5465 {
5466         struct drm_device *dev = crtc->dev;
5467         struct drm_i915_private *dev_priv = dev->dev_private;
5468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5469         bool visible = base != 0;
5470         u32 cntl;
5471
5472         if (intel_crtc->cursor_visible == visible)
5473                 return;
5474
5475         cntl = I915_READ(_CURACNTR);
5476         if (visible) {
5477                 /* On these chipsets we can only modify the base whilst
5478                  * the cursor is disabled.
5479                  */
5480                 I915_WRITE(_CURABASE, base);
5481
5482                 cntl &= ~(CURSOR_FORMAT_MASK);
5483                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5484                 cntl |= CURSOR_ENABLE |
5485                         CURSOR_GAMMA_ENABLE |
5486                         CURSOR_FORMAT_ARGB;
5487         } else
5488                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5489         I915_WRITE(_CURACNTR, cntl);
5490
5491         intel_crtc->cursor_visible = visible;
5492 }
5493
5494 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5495 {
5496         struct drm_device *dev = crtc->dev;
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5499         int pipe = intel_crtc->pipe;
5500         bool visible = base != 0;
5501
5502         if (intel_crtc->cursor_visible != visible) {
5503                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5504                 if (base) {
5505                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5506                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5507                         cntl |= pipe << 28; /* Connect to correct pipe */
5508                 } else {
5509                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5510                         cntl |= CURSOR_MODE_DISABLE;
5511                 }
5512                 I915_WRITE(CURCNTR(pipe), cntl);
5513
5514                 intel_crtc->cursor_visible = visible;
5515         }
5516         /* and commit changes on next vblank */
5517         I915_WRITE(CURBASE(pipe), base);
5518 }
5519
5520 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5521 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5522                                      bool on)
5523 {
5524         struct drm_device *dev = crtc->dev;
5525         struct drm_i915_private *dev_priv = dev->dev_private;
5526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5527         int pipe = intel_crtc->pipe;
5528         int x = intel_crtc->cursor_x;
5529         int y = intel_crtc->cursor_y;
5530         u32 base, pos;
5531         bool visible;
5532
5533         pos = 0;
5534
5535         if (on && crtc->enabled && crtc->fb) {
5536                 base = intel_crtc->cursor_addr;
5537                 if (x > (int) crtc->fb->width)
5538                         base = 0;
5539
5540                 if (y > (int) crtc->fb->height)
5541                         base = 0;
5542         } else
5543                 base = 0;
5544
5545         if (x < 0) {
5546                 if (x + intel_crtc->cursor_width < 0)
5547                         base = 0;
5548
5549                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5550                 x = -x;
5551         }
5552         pos |= x << CURSOR_X_SHIFT;
5553
5554         if (y < 0) {
5555                 if (y + intel_crtc->cursor_height < 0)
5556                         base = 0;
5557
5558                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5559                 y = -y;
5560         }
5561         pos |= y << CURSOR_Y_SHIFT;
5562
5563         visible = base != 0;
5564         if (!visible && !intel_crtc->cursor_visible)
5565                 return;
5566
5567         I915_WRITE(CURPOS(pipe), pos);
5568         if (IS_845G(dev) || IS_I865G(dev))
5569                 i845_update_cursor(crtc, base);
5570         else
5571                 i9xx_update_cursor(crtc, base);
5572
5573         if (visible)
5574                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5575 }
5576
5577 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5578                                  struct drm_file *file,
5579                                  uint32_t handle,
5580                                  uint32_t width, uint32_t height)
5581 {
5582         struct drm_device *dev = crtc->dev;
5583         struct drm_i915_private *dev_priv = dev->dev_private;
5584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5585         struct drm_i915_gem_object *obj;
5586         uint32_t addr;
5587         int ret;
5588
5589         DRM_DEBUG_KMS("\n");
5590
5591         /* if we want to turn off the cursor ignore width and height */
5592         if (!handle) {
5593                 DRM_DEBUG_KMS("cursor off\n");
5594                 addr = 0;
5595                 obj = NULL;
5596                 mutex_lock(&dev->struct_mutex);
5597                 goto finish;
5598         }
5599
5600         /* Currently we only support 64x64 cursors */
5601         if (width != 64 || height != 64) {
5602                 DRM_ERROR("we currently only support 64x64 cursors\n");
5603                 return -EINVAL;
5604         }
5605
5606         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5607         if (&obj->base == NULL)
5608                 return -ENOENT;
5609
5610         if (obj->base.size < width * height * 4) {
5611                 DRM_ERROR("buffer is to small\n");
5612                 ret = -ENOMEM;
5613                 goto fail;
5614         }
5615
5616         /* we only need to pin inside GTT if cursor is non-phy */
5617         mutex_lock(&dev->struct_mutex);
5618         if (!dev_priv->info->cursor_needs_physical) {
5619                 if (obj->tiling_mode) {
5620                         DRM_ERROR("cursor cannot be tiled\n");
5621                         ret = -EINVAL;
5622                         goto fail_locked;
5623                 }
5624
5625                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5626                 if (ret) {
5627                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5628                         goto fail_locked;
5629                 }
5630
5631                 ret = i915_gem_object_put_fence(obj);
5632                 if (ret) {
5633                         DRM_ERROR("failed to release fence for cursor");
5634                         goto fail_unpin;
5635                 }
5636
5637                 addr = obj->gtt_offset;
5638         } else {
5639                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5640                 ret = i915_gem_attach_phys_object(dev, obj,
5641                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5642                                                   align);
5643                 if (ret) {
5644                         DRM_ERROR("failed to attach phys object\n");
5645                         goto fail_locked;
5646                 }
5647                 addr = obj->phys_obj->handle->busaddr;
5648         }
5649
5650         if (IS_GEN2(dev))
5651                 I915_WRITE(CURSIZE, (height << 12) | width);
5652
5653  finish:
5654         if (intel_crtc->cursor_bo) {
5655                 if (dev_priv->info->cursor_needs_physical) {
5656                         if (intel_crtc->cursor_bo != obj)
5657                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5658                 } else
5659                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5660                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5661         }
5662
5663         mutex_unlock(&dev->struct_mutex);
5664
5665         intel_crtc->cursor_addr = addr;
5666         intel_crtc->cursor_bo = obj;
5667         intel_crtc->cursor_width = width;
5668         intel_crtc->cursor_height = height;
5669
5670         intel_crtc_update_cursor(crtc, true);
5671
5672         return 0;
5673 fail_unpin:
5674         i915_gem_object_unpin(obj);
5675 fail_locked:
5676         mutex_unlock(&dev->struct_mutex);
5677 fail:
5678         drm_gem_object_unreference_unlocked(&obj->base);
5679         return ret;
5680 }
5681
5682 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5683 {
5684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5685
5686         intel_crtc->cursor_x = x;
5687         intel_crtc->cursor_y = y;
5688
5689         intel_crtc_update_cursor(crtc, true);
5690
5691         return 0;
5692 }
5693
5694 /** Sets the color ramps on behalf of RandR */
5695 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5696                                  u16 blue, int regno)
5697 {
5698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5699
5700         intel_crtc->lut_r[regno] = red >> 8;
5701         intel_crtc->lut_g[regno] = green >> 8;
5702         intel_crtc->lut_b[regno] = blue >> 8;
5703 }
5704
5705 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5706                              u16 *blue, int regno)
5707 {
5708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5709
5710         *red = intel_crtc->lut_r[regno] << 8;
5711         *green = intel_crtc->lut_g[regno] << 8;
5712         *blue = intel_crtc->lut_b[regno] << 8;
5713 }
5714
5715 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5716                                  u16 *blue, uint32_t start, uint32_t size)
5717 {
5718         int end = (start + size > 256) ? 256 : start + size, i;
5719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5720
5721         for (i = start; i < end; i++) {
5722                 intel_crtc->lut_r[i] = red[i] >> 8;
5723                 intel_crtc->lut_g[i] = green[i] >> 8;
5724                 intel_crtc->lut_b[i] = blue[i] >> 8;
5725         }
5726
5727         intel_crtc_load_lut(crtc);
5728 }
5729
5730 /**
5731  * Get a pipe with a simple mode set on it for doing load-based monitor
5732  * detection.
5733  *
5734  * It will be up to the load-detect code to adjust the pipe as appropriate for
5735  * its requirements.  The pipe will be connected to no other encoders.
5736  *
5737  * Currently this code will only succeed if there is a pipe with no encoders
5738  * configured for it.  In the future, it could choose to temporarily disable
5739  * some outputs to free up a pipe for its use.
5740  *
5741  * \return crtc, or NULL if no pipes are available.
5742  */
5743
5744 /* VESA 640x480x72Hz mode to set on the pipe */
5745 static struct drm_display_mode load_detect_mode = {
5746         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5747                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5748 };
5749
5750 static struct drm_framebuffer *
5751 intel_framebuffer_create(struct drm_device *dev,
5752                          struct drm_mode_fb_cmd *mode_cmd,
5753                          struct drm_i915_gem_object *obj)
5754 {
5755         struct intel_framebuffer *intel_fb;
5756         int ret;
5757
5758         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5759         if (!intel_fb) {
5760                 drm_gem_object_unreference_unlocked(&obj->base);
5761                 return ERR_PTR(-ENOMEM);
5762         }
5763
5764         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5765         if (ret) {
5766                 drm_gem_object_unreference_unlocked(&obj->base);
5767                 kfree(intel_fb);
5768                 return ERR_PTR(ret);
5769         }
5770
5771         return &intel_fb->base;
5772 }
5773
5774 static u32
5775 intel_framebuffer_pitch_for_width(int width, int bpp)
5776 {
5777         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5778         return ALIGN(pitch, 64);
5779 }
5780
5781 static u32
5782 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5783 {
5784         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5785         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5786 }
5787
5788 static struct drm_framebuffer *
5789 intel_framebuffer_create_for_mode(struct drm_device *dev,
5790                                   struct drm_display_mode *mode,
5791                                   int depth, int bpp)
5792 {
5793         struct drm_i915_gem_object *obj;
5794         struct drm_mode_fb_cmd mode_cmd;
5795
5796         obj = i915_gem_alloc_object(dev,
5797                                     intel_framebuffer_size_for_mode(mode, bpp));
5798         if (obj == NULL)
5799                 return ERR_PTR(-ENOMEM);
5800
5801         mode_cmd.width = mode->hdisplay;
5802         mode_cmd.height = mode->vdisplay;
5803         mode_cmd.depth = depth;
5804         mode_cmd.bpp = bpp;
5805         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5806
5807         return intel_framebuffer_create(dev, &mode_cmd, obj);
5808 }
5809
5810 static struct drm_framebuffer *
5811 mode_fits_in_fbdev(struct drm_device *dev,
5812                    struct drm_display_mode *mode)
5813 {
5814         struct drm_i915_private *dev_priv = dev->dev_private;
5815         struct drm_i915_gem_object *obj;
5816         struct drm_framebuffer *fb;
5817
5818         if (dev_priv->fbdev == NULL)
5819                 return NULL;
5820
5821         obj = dev_priv->fbdev->ifb.obj;
5822         if (obj == NULL)
5823                 return NULL;
5824
5825         fb = &dev_priv->fbdev->ifb.base;
5826         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5827                                                           fb->bits_per_pixel))
5828                 return NULL;
5829
5830         if (obj->base.size < mode->vdisplay * fb->pitch)
5831                 return NULL;
5832
5833         return fb;
5834 }
5835
5836 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5837                                 struct drm_connector *connector,
5838                                 struct drm_display_mode *mode,
5839                                 struct intel_load_detect_pipe *old)
5840 {
5841         struct intel_crtc *intel_crtc;
5842         struct drm_crtc *possible_crtc;
5843         struct drm_encoder *encoder = &intel_encoder->base;
5844         struct drm_crtc *crtc = NULL;
5845         struct drm_device *dev = encoder->dev;
5846         struct drm_framebuffer *old_fb;
5847         int i = -1;
5848
5849         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5850                       connector->base.id, drm_get_connector_name(connector),
5851                       encoder->base.id, drm_get_encoder_name(encoder));
5852
5853         /*
5854          * Algorithm gets a little messy:
5855          *
5856          *   - if the connector already has an assigned crtc, use it (but make
5857          *     sure it's on first)
5858          *
5859          *   - try to find the first unused crtc that can drive this connector,
5860          *     and use that if we find one
5861          */
5862
5863         /* See if we already have a CRTC for this connector */
5864         if (encoder->crtc) {
5865                 crtc = encoder->crtc;
5866
5867                 intel_crtc = to_intel_crtc(crtc);
5868                 old->dpms_mode = intel_crtc->dpms_mode;
5869                 old->load_detect_temp = false;
5870
5871                 /* Make sure the crtc and connector are running */
5872                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5873                         struct drm_encoder_helper_funcs *encoder_funcs;
5874                         struct drm_crtc_helper_funcs *crtc_funcs;
5875
5876                         crtc_funcs = crtc->helper_private;
5877                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5878
5879                         encoder_funcs = encoder->helper_private;
5880                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5881                 }
5882
5883                 return true;
5884         }
5885
5886         /* Find an unused one (if possible) */
5887         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5888                 i++;
5889                 if (!(encoder->possible_crtcs & (1 << i)))
5890                         continue;
5891                 if (!possible_crtc->enabled) {
5892                         crtc = possible_crtc;
5893                         break;
5894                 }
5895         }
5896
5897         /*
5898          * If we didn't find an unused CRTC, don't use any.
5899          */
5900         if (!crtc) {
5901                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5902                 return false;
5903         }
5904
5905         encoder->crtc = crtc;
5906         connector->encoder = encoder;
5907
5908         intel_crtc = to_intel_crtc(crtc);
5909         old->dpms_mode = intel_crtc->dpms_mode;
5910         old->load_detect_temp = true;
5911         old->release_fb = NULL;
5912
5913         if (!mode)
5914                 mode = &load_detect_mode;
5915
5916         old_fb = crtc->fb;
5917
5918         /* We need a framebuffer large enough to accommodate all accesses
5919          * that the plane may generate whilst we perform load detection.
5920          * We can not rely on the fbcon either being present (we get called
5921          * during its initialisation to detect all boot displays, or it may
5922          * not even exist) or that it is large enough to satisfy the
5923          * requested mode.
5924          */
5925         crtc->fb = mode_fits_in_fbdev(dev, mode);
5926         if (crtc->fb == NULL) {
5927                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5928                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5929                 old->release_fb = crtc->fb;
5930         } else
5931                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5932         if (IS_ERR(crtc->fb)) {
5933                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5934                 crtc->fb = old_fb;
5935                 return false;
5936         }
5937
5938         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5939                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5940                 if (old->release_fb)
5941                         old->release_fb->funcs->destroy(old->release_fb);
5942                 crtc->fb = old_fb;
5943                 return false;
5944         }
5945
5946         /* let the connector get through one full cycle before testing */
5947         intel_wait_for_vblank(dev, intel_crtc->pipe);
5948
5949         return true;
5950 }
5951
5952 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5953                                     struct drm_connector *connector,
5954                                     struct intel_load_detect_pipe *old)
5955 {
5956         struct drm_encoder *encoder = &intel_encoder->base;
5957         struct drm_device *dev = encoder->dev;
5958         struct drm_crtc *crtc = encoder->crtc;
5959         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5960         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5961
5962         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5963                       connector->base.id, drm_get_connector_name(connector),
5964                       encoder->base.id, drm_get_encoder_name(encoder));
5965
5966         if (old->load_detect_temp) {
5967                 connector->encoder = NULL;
5968                 drm_helper_disable_unused_functions(dev);
5969
5970                 if (old->release_fb)
5971                         old->release_fb->funcs->destroy(old->release_fb);
5972
5973                 return;
5974         }
5975
5976         /* Switch crtc and encoder back off if necessary */
5977         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5978                 encoder_funcs->dpms(encoder, old->dpms_mode);
5979                 crtc_funcs->dpms(crtc, old->dpms_mode);
5980         }
5981 }
5982
5983 /* Returns the clock of the currently programmed mode of the given pipe. */
5984 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5985 {
5986         struct drm_i915_private *dev_priv = dev->dev_private;
5987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988         int pipe = intel_crtc->pipe;
5989         u32 dpll = I915_READ(DPLL(pipe));
5990         u32 fp;
5991         intel_clock_t clock;
5992
5993         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5994                 fp = I915_READ(FP0(pipe));
5995         else
5996                 fp = I915_READ(FP1(pipe));
5997
5998         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5999         if (IS_PINEVIEW(dev)) {
6000                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6001                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6002         } else {
6003                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6004                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6005         }
6006
6007         if (!IS_GEN2(dev)) {
6008                 if (IS_PINEVIEW(dev))
6009                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6010                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6011                 else
6012                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6013                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6014
6015                 switch (dpll & DPLL_MODE_MASK) {
6016                 case DPLLB_MODE_DAC_SERIAL:
6017                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6018                                 5 : 10;
6019                         break;
6020                 case DPLLB_MODE_LVDS:
6021                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6022                                 7 : 14;
6023                         break;
6024                 default:
6025                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6026                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6027                         return 0;
6028                 }
6029
6030                 /* XXX: Handle the 100Mhz refclk */
6031                 intel_clock(dev, 96000, &clock);
6032         } else {
6033                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6034
6035                 if (is_lvds) {
6036                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6037                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6038                         clock.p2 = 14;
6039
6040                         if ((dpll & PLL_REF_INPUT_MASK) ==
6041                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6042                                 /* XXX: might not be 66MHz */
6043                                 intel_clock(dev, 66000, &clock);
6044                         } else
6045                                 intel_clock(dev, 48000, &clock);
6046                 } else {
6047                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6048                                 clock.p1 = 2;
6049                         else {
6050                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6051                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6052                         }
6053                         if (dpll & PLL_P2_DIVIDE_BY_4)
6054                                 clock.p2 = 4;
6055                         else
6056                                 clock.p2 = 2;
6057
6058                         intel_clock(dev, 48000, &clock);
6059                 }
6060         }
6061
6062         /* XXX: It would be nice to validate the clocks, but we can't reuse
6063          * i830PllIsValid() because it relies on the xf86_config connector
6064          * configuration being accurate, which it isn't necessarily.
6065          */
6066
6067         return clock.dot;
6068 }
6069
6070 /** Returns the currently programmed mode of the given pipe. */
6071 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6072                                              struct drm_crtc *crtc)
6073 {
6074         struct drm_i915_private *dev_priv = dev->dev_private;
6075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076         int pipe = intel_crtc->pipe;
6077         struct drm_display_mode *mode;
6078         int htot = I915_READ(HTOTAL(pipe));
6079         int hsync = I915_READ(HSYNC(pipe));
6080         int vtot = I915_READ(VTOTAL(pipe));
6081         int vsync = I915_READ(VSYNC(pipe));
6082
6083         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6084         if (!mode)
6085                 return NULL;
6086
6087         mode->clock = intel_crtc_clock_get(dev, crtc);
6088         mode->hdisplay = (htot & 0xffff) + 1;
6089         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6090         mode->hsync_start = (hsync & 0xffff) + 1;
6091         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6092         mode->vdisplay = (vtot & 0xffff) + 1;
6093         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6094         mode->vsync_start = (vsync & 0xffff) + 1;
6095         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6096
6097         drm_mode_set_name(mode);
6098         drm_mode_set_crtcinfo(mode, 0);
6099
6100         return mode;
6101 }
6102
6103 #define GPU_IDLE_TIMEOUT 500 /* ms */
6104
6105 /* When this timer fires, we've been idle for awhile */
6106 static void intel_gpu_idle_timer(unsigned long arg)
6107 {
6108         struct drm_device *dev = (struct drm_device *)arg;
6109         drm_i915_private_t *dev_priv = dev->dev_private;
6110
6111         if (!list_empty(&dev_priv->mm.active_list)) {
6112                 /* Still processing requests, so just re-arm the timer. */
6113                 mod_timer(&dev_priv->idle_timer, jiffies +
6114                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6115                 return;
6116         }
6117
6118         dev_priv->busy = false;
6119         queue_work(dev_priv->wq, &dev_priv->idle_work);
6120 }
6121
6122 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6123
6124 static void intel_crtc_idle_timer(unsigned long arg)
6125 {
6126         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6127         struct drm_crtc *crtc = &intel_crtc->base;
6128         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6129         struct intel_framebuffer *intel_fb;
6130
6131         intel_fb = to_intel_framebuffer(crtc->fb);
6132         if (intel_fb && intel_fb->obj->active) {
6133                 /* The framebuffer is still being accessed by the GPU. */
6134                 mod_timer(&intel_crtc->idle_timer, jiffies +
6135                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6136                 return;
6137         }
6138
6139         intel_crtc->busy = false;
6140         queue_work(dev_priv->wq, &dev_priv->idle_work);
6141 }
6142
6143 static void intel_increase_pllclock(struct drm_crtc *crtc)
6144 {
6145         struct drm_device *dev = crtc->dev;
6146         drm_i915_private_t *dev_priv = dev->dev_private;
6147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148         int pipe = intel_crtc->pipe;
6149         int dpll_reg = DPLL(pipe);
6150         int dpll;
6151
6152         if (HAS_PCH_SPLIT(dev))
6153                 return;
6154
6155         if (!dev_priv->lvds_downclock_avail)
6156                 return;
6157
6158         dpll = I915_READ(dpll_reg);
6159         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6160                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6161
6162                 /* Unlock panel regs */
6163                 I915_WRITE(PP_CONTROL,
6164                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6165
6166                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6167                 I915_WRITE(dpll_reg, dpll);
6168                 intel_wait_for_vblank(dev, pipe);
6169
6170                 dpll = I915_READ(dpll_reg);
6171                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6172                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6173
6174                 /* ...and lock them again */
6175                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6176         }
6177
6178         /* Schedule downclock */
6179         mod_timer(&intel_crtc->idle_timer, jiffies +
6180                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6181 }
6182
6183 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6184 {
6185         struct drm_device *dev = crtc->dev;
6186         drm_i915_private_t *dev_priv = dev->dev_private;
6187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6188         int pipe = intel_crtc->pipe;
6189         int dpll_reg = DPLL(pipe);
6190         int dpll = I915_READ(dpll_reg);
6191
6192         if (HAS_PCH_SPLIT(dev))
6193                 return;
6194
6195         if (!dev_priv->lvds_downclock_avail)
6196                 return;
6197
6198         /*
6199          * Since this is called by a timer, we should never get here in
6200          * the manual case.
6201          */
6202         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6203                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6204
6205                 /* Unlock panel regs */
6206                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6207                            PANEL_UNLOCK_REGS);
6208
6209                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6210                 I915_WRITE(dpll_reg, dpll);
6211                 intel_wait_for_vblank(dev, pipe);
6212                 dpll = I915_READ(dpll_reg);
6213                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6214                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6215
6216                 /* ...and lock them again */
6217                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6218         }
6219
6220 }
6221
6222 /**
6223  * intel_idle_update - adjust clocks for idleness
6224  * @work: work struct
6225  *
6226  * Either the GPU or display (or both) went idle.  Check the busy status
6227  * here and adjust the CRTC and GPU clocks as necessary.
6228  */
6229 static void intel_idle_update(struct work_struct *work)
6230 {
6231         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6232                                                     idle_work);
6233         struct drm_device *dev = dev_priv->dev;
6234         struct drm_crtc *crtc;
6235         struct intel_crtc *intel_crtc;
6236
6237         if (!i915_powersave)
6238                 return;
6239
6240         mutex_lock(&dev->struct_mutex);
6241
6242         i915_update_gfx_val(dev_priv);
6243
6244         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6245                 /* Skip inactive CRTCs */
6246                 if (!crtc->fb)
6247                         continue;
6248
6249                 intel_crtc = to_intel_crtc(crtc);
6250                 if (!intel_crtc->busy)
6251                         intel_decrease_pllclock(crtc);
6252         }
6253
6254
6255         mutex_unlock(&dev->struct_mutex);
6256 }
6257
6258 /**
6259  * intel_mark_busy - mark the GPU and possibly the display busy
6260  * @dev: drm device
6261  * @obj: object we're operating on
6262  *
6263  * Callers can use this function to indicate that the GPU is busy processing
6264  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6265  * buffer), we'll also mark the display as busy, so we know to increase its
6266  * clock frequency.
6267  */
6268 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6269 {
6270         drm_i915_private_t *dev_priv = dev->dev_private;
6271         struct drm_crtc *crtc = NULL;
6272         struct intel_framebuffer *intel_fb;
6273         struct intel_crtc *intel_crtc;
6274
6275         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6276                 return;
6277
6278         if (!dev_priv->busy)
6279                 dev_priv->busy = true;
6280         else
6281                 mod_timer(&dev_priv->idle_timer, jiffies +
6282                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6283
6284         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6285                 if (!crtc->fb)
6286                         continue;
6287
6288                 intel_crtc = to_intel_crtc(crtc);
6289                 intel_fb = to_intel_framebuffer(crtc->fb);
6290                 if (intel_fb->obj == obj) {
6291                         if (!intel_crtc->busy) {
6292                                 /* Non-busy -> busy, upclock */
6293                                 intel_increase_pllclock(crtc);
6294                                 intel_crtc->busy = true;
6295                         } else {
6296                                 /* Busy -> busy, put off timer */
6297                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6298                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6299                         }
6300                 }
6301         }
6302 }
6303
6304 static void intel_crtc_destroy(struct drm_crtc *crtc)
6305 {
6306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307         struct drm_device *dev = crtc->dev;
6308         struct intel_unpin_work *work;
6309         unsigned long flags;
6310
6311         spin_lock_irqsave(&dev->event_lock, flags);
6312         work = intel_crtc->unpin_work;
6313         intel_crtc->unpin_work = NULL;
6314         spin_unlock_irqrestore(&dev->event_lock, flags);
6315
6316         if (work) {
6317                 cancel_work_sync(&work->work);
6318                 kfree(work);
6319         }
6320
6321         drm_crtc_cleanup(crtc);
6322
6323         kfree(intel_crtc);
6324 }
6325
6326 static void intel_unpin_work_fn(struct work_struct *__work)
6327 {
6328         struct intel_unpin_work *work =
6329                 container_of(__work, struct intel_unpin_work, work);
6330
6331         mutex_lock(&work->dev->struct_mutex);
6332         i915_gem_object_unpin(work->old_fb_obj);
6333         drm_gem_object_unreference(&work->pending_flip_obj->base);
6334         drm_gem_object_unreference(&work->old_fb_obj->base);
6335
6336         mutex_unlock(&work->dev->struct_mutex);
6337         kfree(work);
6338 }
6339
6340 static void do_intel_finish_page_flip(struct drm_device *dev,
6341                                       struct drm_crtc *crtc)
6342 {
6343         drm_i915_private_t *dev_priv = dev->dev_private;
6344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345         struct intel_unpin_work *work;
6346         struct drm_i915_gem_object *obj;
6347         struct drm_pending_vblank_event *e;
6348         struct timeval tnow, tvbl;
6349         unsigned long flags;
6350
6351         /* Ignore early vblank irqs */
6352         if (intel_crtc == NULL)
6353                 return;
6354
6355         do_gettimeofday(&tnow);
6356
6357         spin_lock_irqsave(&dev->event_lock, flags);
6358         work = intel_crtc->unpin_work;
6359         if (work == NULL || !work->pending) {
6360                 spin_unlock_irqrestore(&dev->event_lock, flags);
6361                 return;
6362         }
6363
6364         intel_crtc->unpin_work = NULL;
6365
6366         if (work->event) {
6367                 e = work->event;
6368                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6369
6370                 /* Called before vblank count and timestamps have
6371                  * been updated for the vblank interval of flip
6372                  * completion? Need to increment vblank count and
6373                  * add one videorefresh duration to returned timestamp
6374                  * to account for this. We assume this happened if we
6375                  * get called over 0.9 frame durations after the last
6376                  * timestamped vblank.
6377                  *
6378                  * This calculation can not be used with vrefresh rates
6379                  * below 5Hz (10Hz to be on the safe side) without
6380                  * promoting to 64 integers.
6381                  */
6382                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6383                     9 * crtc->framedur_ns) {
6384                         e->event.sequence++;
6385                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6386                                              crtc->framedur_ns);
6387                 }
6388
6389                 e->event.tv_sec = tvbl.tv_sec;
6390                 e->event.tv_usec = tvbl.tv_usec;
6391
6392                 list_add_tail(&e->base.link,
6393                               &e->base.file_priv->event_list);
6394                 wake_up_interruptible(&e->base.file_priv->event_wait);
6395         }
6396
6397         drm_vblank_put(dev, intel_crtc->pipe);
6398
6399         spin_unlock_irqrestore(&dev->event_lock, flags);
6400
6401         obj = work->old_fb_obj;
6402
6403         atomic_clear_mask(1 << intel_crtc->plane,
6404                           &obj->pending_flip.counter);
6405         if (atomic_read(&obj->pending_flip) == 0)
6406                 wake_up(&dev_priv->pending_flip_queue);
6407
6408         schedule_work(&work->work);
6409
6410         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6411 }
6412
6413 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6414 {
6415         drm_i915_private_t *dev_priv = dev->dev_private;
6416         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6417
6418         do_intel_finish_page_flip(dev, crtc);
6419 }
6420
6421 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6422 {
6423         drm_i915_private_t *dev_priv = dev->dev_private;
6424         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6425
6426         do_intel_finish_page_flip(dev, crtc);
6427 }
6428
6429 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6430 {
6431         drm_i915_private_t *dev_priv = dev->dev_private;
6432         struct intel_crtc *intel_crtc =
6433                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6434         unsigned long flags;
6435
6436         spin_lock_irqsave(&dev->event_lock, flags);
6437         if (intel_crtc->unpin_work) {
6438                 if ((++intel_crtc->unpin_work->pending) > 1)
6439                         DRM_ERROR("Prepared flip multiple times\n");
6440         } else {
6441                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6442         }
6443         spin_unlock_irqrestore(&dev->event_lock, flags);
6444 }
6445
6446 static int intel_gen2_queue_flip(struct drm_device *dev,
6447                                  struct drm_crtc *crtc,
6448                                  struct drm_framebuffer *fb,
6449                                  struct drm_i915_gem_object *obj)
6450 {
6451         struct drm_i915_private *dev_priv = dev->dev_private;
6452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6453         unsigned long offset;
6454         u32 flip_mask;
6455         int ret;
6456
6457         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6458         if (ret)
6459                 goto out;
6460
6461         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6462         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6463
6464         ret = BEGIN_LP_RING(6);
6465         if (ret)
6466                 goto out;
6467
6468         /* Can't queue multiple flips, so wait for the previous
6469          * one to finish before executing the next.
6470          */
6471         if (intel_crtc->plane)
6472                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6473         else
6474                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6475         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6476         OUT_RING(MI_NOOP);
6477         OUT_RING(MI_DISPLAY_FLIP |
6478                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6479         OUT_RING(fb->pitch);
6480         OUT_RING(obj->gtt_offset + offset);
6481         OUT_RING(MI_NOOP);
6482         ADVANCE_LP_RING();
6483 out:
6484         return ret;
6485 }
6486
6487 static int intel_gen3_queue_flip(struct drm_device *dev,
6488                                  struct drm_crtc *crtc,
6489                                  struct drm_framebuffer *fb,
6490                                  struct drm_i915_gem_object *obj)
6491 {
6492         struct drm_i915_private *dev_priv = dev->dev_private;
6493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6494         unsigned long offset;
6495         u32 flip_mask;
6496         int ret;
6497
6498         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6499         if (ret)
6500                 goto out;
6501
6502         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6503         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6504
6505         ret = BEGIN_LP_RING(6);
6506         if (ret)
6507                 goto out;
6508
6509         if (intel_crtc->plane)
6510                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6511         else
6512                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6513         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6514         OUT_RING(MI_NOOP);
6515         OUT_RING(MI_DISPLAY_FLIP_I915 |
6516                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6517         OUT_RING(fb->pitch);
6518         OUT_RING(obj->gtt_offset + offset);
6519         OUT_RING(MI_NOOP);
6520
6521         ADVANCE_LP_RING();
6522 out:
6523         return ret;
6524 }
6525
6526 static int intel_gen4_queue_flip(struct drm_device *dev,
6527                                  struct drm_crtc *crtc,
6528                                  struct drm_framebuffer *fb,
6529                                  struct drm_i915_gem_object *obj)
6530 {
6531         struct drm_i915_private *dev_priv = dev->dev_private;
6532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6533         uint32_t pf, pipesrc;
6534         int ret;
6535
6536         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6537         if (ret)
6538                 goto out;
6539
6540         ret = BEGIN_LP_RING(4);
6541         if (ret)
6542                 goto out;
6543
6544         /* i965+ uses the linear or tiled offsets from the
6545          * Display Registers (which do not change across a page-flip)
6546          * so we need only reprogram the base address.
6547          */
6548         OUT_RING(MI_DISPLAY_FLIP |
6549                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6550         OUT_RING(fb->pitch);
6551         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6552
6553         /* XXX Enabling the panel-fitter across page-flip is so far
6554          * untested on non-native modes, so ignore it for now.
6555          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6556          */
6557         pf = 0;
6558         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6559         OUT_RING(pf | pipesrc);
6560         ADVANCE_LP_RING();
6561 out:
6562         return ret;
6563 }
6564
6565 static int intel_gen6_queue_flip(struct drm_device *dev,
6566                                  struct drm_crtc *crtc,
6567                                  struct drm_framebuffer *fb,
6568                                  struct drm_i915_gem_object *obj)
6569 {
6570         struct drm_i915_private *dev_priv = dev->dev_private;
6571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6572         uint32_t pf, pipesrc;
6573         int ret;
6574
6575         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6576         if (ret)
6577                 goto out;
6578
6579         ret = BEGIN_LP_RING(4);
6580         if (ret)
6581                 goto out;
6582
6583         OUT_RING(MI_DISPLAY_FLIP |
6584                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6585         OUT_RING(fb->pitch | obj->tiling_mode);
6586         OUT_RING(obj->gtt_offset);
6587
6588         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6589         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6590         OUT_RING(pf | pipesrc);
6591         ADVANCE_LP_RING();
6592 out:
6593         return ret;
6594 }
6595
6596 /*
6597  * On gen7 we currently use the blit ring because (in early silicon at least)
6598  * the render ring doesn't give us interrpts for page flip completion, which
6599  * means clients will hang after the first flip is queued.  Fortunately the
6600  * blit ring generates interrupts properly, so use it instead.
6601  */
6602 static int intel_gen7_queue_flip(struct drm_device *dev,
6603                                  struct drm_crtc *crtc,
6604                                  struct drm_framebuffer *fb,
6605                                  struct drm_i915_gem_object *obj)
6606 {
6607         struct drm_i915_private *dev_priv = dev->dev_private;
6608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6609         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6610         int ret;
6611
6612         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6613         if (ret)
6614                 goto out;
6615
6616         ret = intel_ring_begin(ring, 4);
6617         if (ret)
6618                 goto out;
6619
6620         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6621         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6622         intel_ring_emit(ring, (obj->gtt_offset));
6623         intel_ring_emit(ring, (MI_NOOP));
6624         intel_ring_advance(ring);
6625 out:
6626         return ret;
6627 }
6628
6629 static int intel_default_queue_flip(struct drm_device *dev,
6630                                     struct drm_crtc *crtc,
6631                                     struct drm_framebuffer *fb,
6632                                     struct drm_i915_gem_object *obj)
6633 {
6634         return -ENODEV;
6635 }
6636
6637 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6638                                 struct drm_framebuffer *fb,
6639                                 struct drm_pending_vblank_event *event)
6640 {
6641         struct drm_device *dev = crtc->dev;
6642         struct drm_i915_private *dev_priv = dev->dev_private;
6643         struct intel_framebuffer *intel_fb;
6644         struct drm_i915_gem_object *obj;
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         struct intel_unpin_work *work;
6647         unsigned long flags;
6648         int ret;
6649
6650         work = kzalloc(sizeof *work, GFP_KERNEL);
6651         if (work == NULL)
6652                 return -ENOMEM;
6653
6654         work->event = event;
6655         work->dev = crtc->dev;
6656         intel_fb = to_intel_framebuffer(crtc->fb);
6657         work->old_fb_obj = intel_fb->obj;
6658         INIT_WORK(&work->work, intel_unpin_work_fn);
6659
6660         /* We borrow the event spin lock for protecting unpin_work */
6661         spin_lock_irqsave(&dev->event_lock, flags);
6662         if (intel_crtc->unpin_work) {
6663                 spin_unlock_irqrestore(&dev->event_lock, flags);
6664                 kfree(work);
6665
6666                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6667                 return -EBUSY;
6668         }
6669         intel_crtc->unpin_work = work;
6670         spin_unlock_irqrestore(&dev->event_lock, flags);
6671
6672         intel_fb = to_intel_framebuffer(fb);
6673         obj = intel_fb->obj;
6674
6675         mutex_lock(&dev->struct_mutex);
6676
6677         /* Reference the objects for the scheduled work. */
6678         drm_gem_object_reference(&work->old_fb_obj->base);
6679         drm_gem_object_reference(&obj->base);
6680
6681         crtc->fb = fb;
6682
6683         ret = drm_vblank_get(dev, intel_crtc->pipe);
6684         if (ret)
6685                 goto cleanup_objs;
6686
6687         work->pending_flip_obj = obj;
6688
6689         work->enable_stall_check = true;
6690
6691         /* Block clients from rendering to the new back buffer until
6692          * the flip occurs and the object is no longer visible.
6693          */
6694         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6695
6696         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6697         if (ret)
6698                 goto cleanup_pending;
6699
6700         mutex_unlock(&dev->struct_mutex);
6701
6702         trace_i915_flip_request(intel_crtc->plane, obj);
6703
6704         return 0;
6705
6706 cleanup_pending:
6707         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6708 cleanup_objs:
6709         drm_gem_object_unreference(&work->old_fb_obj->base);
6710         drm_gem_object_unreference(&obj->base);
6711         mutex_unlock(&dev->struct_mutex);
6712
6713         spin_lock_irqsave(&dev->event_lock, flags);
6714         intel_crtc->unpin_work = NULL;
6715         spin_unlock_irqrestore(&dev->event_lock, flags);
6716
6717         kfree(work);
6718
6719         return ret;
6720 }
6721
6722 static void intel_sanitize_modesetting(struct drm_device *dev,
6723                                        int pipe, int plane)
6724 {
6725         struct drm_i915_private *dev_priv = dev->dev_private;
6726         u32 reg, val;
6727
6728         if (HAS_PCH_SPLIT(dev))
6729                 return;
6730
6731         /* Who knows what state these registers were left in by the BIOS or
6732          * grub?
6733          *
6734          * If we leave the registers in a conflicting state (e.g. with the
6735          * display plane reading from the other pipe than the one we intend
6736          * to use) then when we attempt to teardown the active mode, we will
6737          * not disable the pipes and planes in the correct order -- leaving
6738          * a plane reading from a disabled pipe and possibly leading to
6739          * undefined behaviour.
6740          */
6741
6742         reg = DSPCNTR(plane);
6743         val = I915_READ(reg);
6744
6745         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6746                 return;
6747         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6748                 return;
6749
6750         /* This display plane is active and attached to the other CPU pipe. */
6751         pipe = !pipe;
6752
6753         /* Disable the plane and wait for it to stop reading from the pipe. */
6754         intel_disable_plane(dev_priv, plane, pipe);
6755         intel_disable_pipe(dev_priv, pipe);
6756 }
6757
6758 static void intel_crtc_reset(struct drm_crtc *crtc)
6759 {
6760         struct drm_device *dev = crtc->dev;
6761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6762
6763         /* Reset flags back to the 'unknown' status so that they
6764          * will be correctly set on the initial modeset.
6765          */
6766         intel_crtc->dpms_mode = -1;
6767
6768         /* We need to fix up any BIOS configuration that conflicts with
6769          * our expectations.
6770          */
6771         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6772 }
6773
6774 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6775         .dpms = intel_crtc_dpms,
6776         .mode_fixup = intel_crtc_mode_fixup,
6777         .mode_set = intel_crtc_mode_set,
6778         .mode_set_base = intel_pipe_set_base,
6779         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6780         .load_lut = intel_crtc_load_lut,
6781         .disable = intel_crtc_disable,
6782 };
6783
6784 static const struct drm_crtc_funcs intel_crtc_funcs = {
6785         .reset = intel_crtc_reset,
6786         .cursor_set = intel_crtc_cursor_set,
6787         .cursor_move = intel_crtc_cursor_move,
6788         .gamma_set = intel_crtc_gamma_set,
6789         .set_config = drm_crtc_helper_set_config,
6790         .destroy = intel_crtc_destroy,
6791         .page_flip = intel_crtc_page_flip,
6792 };
6793
6794 static void intel_crtc_init(struct drm_device *dev, int pipe)
6795 {
6796         drm_i915_private_t *dev_priv = dev->dev_private;
6797         struct intel_crtc *intel_crtc;
6798         int i;
6799
6800         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6801         if (intel_crtc == NULL)
6802                 return;
6803
6804         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6805
6806         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6807         for (i = 0; i < 256; i++) {
6808                 intel_crtc->lut_r[i] = i;
6809                 intel_crtc->lut_g[i] = i;
6810                 intel_crtc->lut_b[i] = i;
6811         }
6812
6813         /* Swap pipes & planes for FBC on pre-965 */
6814         intel_crtc->pipe = pipe;
6815         intel_crtc->plane = pipe;
6816         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6817                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6818                 intel_crtc->plane = !pipe;
6819         }
6820
6821         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6822                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6823         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6824         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6825
6826         intel_crtc_reset(&intel_crtc->base);
6827         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6828         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6829
6830         if (HAS_PCH_SPLIT(dev)) {
6831                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6832                 intel_helper_funcs.commit = ironlake_crtc_commit;
6833         } else {
6834                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6835                 intel_helper_funcs.commit = i9xx_crtc_commit;
6836         }
6837
6838         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6839
6840         intel_crtc->busy = false;
6841
6842         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6843                     (unsigned long)intel_crtc);
6844 }
6845
6846 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6847                                 struct drm_file *file)
6848 {
6849         drm_i915_private_t *dev_priv = dev->dev_private;
6850         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6851         struct drm_mode_object *drmmode_obj;
6852         struct intel_crtc *crtc;
6853
6854         if (!dev_priv) {
6855                 DRM_ERROR("called with no initialization\n");
6856                 return -EINVAL;
6857         }
6858
6859         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6860                         DRM_MODE_OBJECT_CRTC);
6861
6862         if (!drmmode_obj) {
6863                 DRM_ERROR("no such CRTC id\n");
6864                 return -EINVAL;
6865         }
6866
6867         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6868         pipe_from_crtc_id->pipe = crtc->pipe;
6869
6870         return 0;
6871 }
6872
6873 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6874 {
6875         struct intel_encoder *encoder;
6876         int index_mask = 0;
6877         int entry = 0;
6878
6879         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6880                 if (type_mask & encoder->clone_mask)
6881                         index_mask |= (1 << entry);
6882                 entry++;
6883         }
6884
6885         return index_mask;
6886 }
6887
6888 static bool has_edp_a(struct drm_device *dev)
6889 {
6890         struct drm_i915_private *dev_priv = dev->dev_private;
6891
6892         if (!IS_MOBILE(dev))
6893                 return false;
6894
6895         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6896                 return false;
6897
6898         if (IS_GEN5(dev) &&
6899             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6900                 return false;
6901
6902         return true;
6903 }
6904
6905 static void intel_setup_outputs(struct drm_device *dev)
6906 {
6907         struct drm_i915_private *dev_priv = dev->dev_private;
6908         struct intel_encoder *encoder;
6909         bool dpd_is_edp = false;
6910         bool has_lvds = false;
6911
6912         if (IS_MOBILE(dev) && !IS_I830(dev))
6913                 has_lvds = intel_lvds_init(dev);
6914         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6915                 /* disable the panel fitter on everything but LVDS */
6916                 I915_WRITE(PFIT_CONTROL, 0);
6917         }
6918
6919         if (HAS_PCH_SPLIT(dev)) {
6920                 dpd_is_edp = intel_dpd_is_edp(dev);
6921
6922                 if (has_edp_a(dev))
6923                         intel_dp_init(dev, DP_A);
6924
6925                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6926                         intel_dp_init(dev, PCH_DP_D);
6927         }
6928
6929         intel_crt_init(dev);
6930
6931         if (HAS_PCH_SPLIT(dev)) {
6932                 int found;
6933
6934                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6935                         /* PCH SDVOB multiplex with HDMIB */
6936                         found = intel_sdvo_init(dev, PCH_SDVOB);
6937                         if (!found)
6938                                 intel_hdmi_init(dev, HDMIB);
6939                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6940                                 intel_dp_init(dev, PCH_DP_B);
6941                 }
6942
6943                 if (I915_READ(HDMIC) & PORT_DETECTED)
6944                         intel_hdmi_init(dev, HDMIC);
6945
6946                 if (I915_READ(HDMID) & PORT_DETECTED)
6947                         intel_hdmi_init(dev, HDMID);
6948
6949                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6950                         intel_dp_init(dev, PCH_DP_C);
6951
6952                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6953                         intel_dp_init(dev, PCH_DP_D);
6954
6955         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6956                 bool found = false;
6957
6958                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6959                         DRM_DEBUG_KMS("probing SDVOB\n");
6960                         found = intel_sdvo_init(dev, SDVOB);
6961                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6962                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6963                                 intel_hdmi_init(dev, SDVOB);
6964                         }
6965
6966                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6967                                 DRM_DEBUG_KMS("probing DP_B\n");
6968                                 intel_dp_init(dev, DP_B);
6969                         }
6970                 }
6971
6972                 /* Before G4X SDVOC doesn't have its own detect register */
6973
6974                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6975                         DRM_DEBUG_KMS("probing SDVOC\n");
6976                         found = intel_sdvo_init(dev, SDVOC);
6977                 }
6978
6979                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6980
6981                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6982                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6983                                 intel_hdmi_init(dev, SDVOC);
6984                         }
6985                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6986                                 DRM_DEBUG_KMS("probing DP_C\n");
6987                                 intel_dp_init(dev, DP_C);
6988                         }
6989                 }
6990
6991                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6992                     (I915_READ(DP_D) & DP_DETECTED)) {
6993                         DRM_DEBUG_KMS("probing DP_D\n");
6994                         intel_dp_init(dev, DP_D);
6995                 }
6996         } else if (IS_GEN2(dev))
6997                 intel_dvo_init(dev);
6998
6999         if (SUPPORTS_TV(dev))
7000                 intel_tv_init(dev);
7001
7002         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7003                 encoder->base.possible_crtcs = encoder->crtc_mask;
7004                 encoder->base.possible_clones =
7005                         intel_encoder_clones(dev, encoder->clone_mask);
7006         }
7007
7008         intel_panel_setup_backlight(dev);
7009
7010         /* disable all the possible outputs/crtcs before entering KMS mode */
7011         drm_helper_disable_unused_functions(dev);
7012 }
7013
7014 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7015 {
7016         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7017
7018         drm_framebuffer_cleanup(fb);
7019         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7020
7021         kfree(intel_fb);
7022 }
7023
7024 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7025                                                 struct drm_file *file,
7026                                                 unsigned int *handle)
7027 {
7028         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7029         struct drm_i915_gem_object *obj = intel_fb->obj;
7030
7031         return drm_gem_handle_create(file, &obj->base, handle);
7032 }
7033
7034 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7035         .destroy = intel_user_framebuffer_destroy,
7036         .create_handle = intel_user_framebuffer_create_handle,
7037 };
7038
7039 int intel_framebuffer_init(struct drm_device *dev,
7040                            struct intel_framebuffer *intel_fb,
7041                            struct drm_mode_fb_cmd *mode_cmd,
7042                            struct drm_i915_gem_object *obj)
7043 {
7044         int ret;
7045
7046         if (obj->tiling_mode == I915_TILING_Y)
7047                 return -EINVAL;
7048
7049         if (mode_cmd->pitch & 63)
7050                 return -EINVAL;
7051
7052         switch (mode_cmd->bpp) {
7053         case 8:
7054         case 16:
7055                 /* Only pre-ILK can handle 5:5:5 */
7056                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7057                         return -EINVAL;
7058                 break;
7059
7060         case 24:
7061         case 32:
7062                 break;
7063         default:
7064                 return -EINVAL;
7065         }
7066
7067         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7068         if (ret) {
7069                 DRM_ERROR("framebuffer init failed %d\n", ret);
7070                 return ret;
7071         }
7072
7073         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7074         intel_fb->obj = obj;
7075         return 0;
7076 }
7077
7078 static struct drm_framebuffer *
7079 intel_user_framebuffer_create(struct drm_device *dev,
7080                               struct drm_file *filp,
7081                               struct drm_mode_fb_cmd *mode_cmd)
7082 {
7083         struct drm_i915_gem_object *obj;
7084
7085         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7086         if (&obj->base == NULL)
7087                 return ERR_PTR(-ENOENT);
7088
7089         return intel_framebuffer_create(dev, mode_cmd, obj);
7090 }
7091
7092 static const struct drm_mode_config_funcs intel_mode_funcs = {
7093         .fb_create = intel_user_framebuffer_create,
7094         .output_poll_changed = intel_fb_output_poll_changed,
7095 };
7096
7097 static struct drm_i915_gem_object *
7098 intel_alloc_context_page(struct drm_device *dev)
7099 {
7100         struct drm_i915_gem_object *ctx;
7101         int ret;
7102
7103         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7104
7105         ctx = i915_gem_alloc_object(dev, 4096);
7106         if (!ctx) {
7107                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7108                 return NULL;
7109         }
7110
7111         ret = i915_gem_object_pin(ctx, 4096, true);
7112         if (ret) {
7113                 DRM_ERROR("failed to pin power context: %d\n", ret);
7114                 goto err_unref;
7115         }
7116
7117         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7118         if (ret) {
7119                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7120                 goto err_unpin;
7121         }
7122
7123         return ctx;
7124
7125 err_unpin:
7126         i915_gem_object_unpin(ctx);
7127 err_unref:
7128         drm_gem_object_unreference(&ctx->base);
7129         mutex_unlock(&dev->struct_mutex);
7130         return NULL;
7131 }
7132
7133 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7134 {
7135         struct drm_i915_private *dev_priv = dev->dev_private;
7136         u16 rgvswctl;
7137
7138         rgvswctl = I915_READ16(MEMSWCTL);
7139         if (rgvswctl & MEMCTL_CMD_STS) {
7140                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7141                 return false; /* still busy with another command */
7142         }
7143
7144         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7145                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7146         I915_WRITE16(MEMSWCTL, rgvswctl);
7147         POSTING_READ16(MEMSWCTL);
7148
7149         rgvswctl |= MEMCTL_CMD_STS;
7150         I915_WRITE16(MEMSWCTL, rgvswctl);
7151
7152         return true;
7153 }
7154
7155 void ironlake_enable_drps(struct drm_device *dev)
7156 {
7157         struct drm_i915_private *dev_priv = dev->dev_private;
7158         u32 rgvmodectl = I915_READ(MEMMODECTL);
7159         u8 fmax, fmin, fstart, vstart;
7160
7161         /* Enable temp reporting */
7162         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7163         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7164
7165         /* 100ms RC evaluation intervals */
7166         I915_WRITE(RCUPEI, 100000);
7167         I915_WRITE(RCDNEI, 100000);
7168
7169         /* Set max/min thresholds to 90ms and 80ms respectively */
7170         I915_WRITE(RCBMAXAVG, 90000);
7171         I915_WRITE(RCBMINAVG, 80000);
7172
7173         I915_WRITE(MEMIHYST, 1);
7174
7175         /* Set up min, max, and cur for interrupt handling */
7176         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7177         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7178         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7179                 MEMMODE_FSTART_SHIFT;
7180
7181         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7182                 PXVFREQ_PX_SHIFT;
7183
7184         dev_priv->fmax = fmax; /* IPS callback will increase this */
7185         dev_priv->fstart = fstart;
7186
7187         dev_priv->max_delay = fstart;
7188         dev_priv->min_delay = fmin;
7189         dev_priv->cur_delay = fstart;
7190
7191         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7192                          fmax, fmin, fstart);
7193
7194         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7195
7196         /*
7197          * Interrupts will be enabled in ironlake_irq_postinstall
7198          */
7199
7200         I915_WRITE(VIDSTART, vstart);
7201         POSTING_READ(VIDSTART);
7202
7203         rgvmodectl |= MEMMODE_SWMODE_EN;
7204         I915_WRITE(MEMMODECTL, rgvmodectl);
7205
7206         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7207                 DRM_ERROR("stuck trying to change perf mode\n");
7208         msleep(1);
7209
7210         ironlake_set_drps(dev, fstart);
7211
7212         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7213                 I915_READ(0x112e0);
7214         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7215         dev_priv->last_count2 = I915_READ(0x112f4);
7216         getrawmonotonic(&dev_priv->last_time2);
7217 }
7218
7219 void ironlake_disable_drps(struct drm_device *dev)
7220 {
7221         struct drm_i915_private *dev_priv = dev->dev_private;
7222         u16 rgvswctl = I915_READ16(MEMSWCTL);
7223
7224         /* Ack interrupts, disable EFC interrupt */
7225         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7226         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7227         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7228         I915_WRITE(DEIIR, DE_PCU_EVENT);
7229         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7230
7231         /* Go back to the starting frequency */
7232         ironlake_set_drps(dev, dev_priv->fstart);
7233         msleep(1);
7234         rgvswctl |= MEMCTL_CMD_STS;
7235         I915_WRITE(MEMSWCTL, rgvswctl);
7236         msleep(1);
7237
7238 }
7239
7240 void gen6_set_rps(struct drm_device *dev, u8 val)
7241 {
7242         struct drm_i915_private *dev_priv = dev->dev_private;
7243         u32 swreq;
7244
7245         swreq = (val & 0x3ff) << 25;
7246         I915_WRITE(GEN6_RPNSWREQ, swreq);
7247 }
7248
7249 void gen6_disable_rps(struct drm_device *dev)
7250 {
7251         struct drm_i915_private *dev_priv = dev->dev_private;
7252
7253         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7254         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7255         I915_WRITE(GEN6_PMIER, 0);
7256
7257         spin_lock_irq(&dev_priv->rps_lock);
7258         dev_priv->pm_iir = 0;
7259         spin_unlock_irq(&dev_priv->rps_lock);
7260
7261         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7262 }
7263
7264 static unsigned long intel_pxfreq(u32 vidfreq)
7265 {
7266         unsigned long freq;
7267         int div = (vidfreq & 0x3f0000) >> 16;
7268         int post = (vidfreq & 0x3000) >> 12;
7269         int pre = (vidfreq & 0x7);
7270
7271         if (!pre)
7272                 return 0;
7273
7274         freq = ((div * 133333) / ((1<<post) * pre));
7275
7276         return freq;
7277 }
7278
7279 void intel_init_emon(struct drm_device *dev)
7280 {
7281         struct drm_i915_private *dev_priv = dev->dev_private;
7282         u32 lcfuse;
7283         u8 pxw[16];
7284         int i;
7285
7286         /* Disable to program */
7287         I915_WRITE(ECR, 0);
7288         POSTING_READ(ECR);
7289
7290         /* Program energy weights for various events */
7291         I915_WRITE(SDEW, 0x15040d00);
7292         I915_WRITE(CSIEW0, 0x007f0000);
7293         I915_WRITE(CSIEW1, 0x1e220004);
7294         I915_WRITE(CSIEW2, 0x04000004);
7295
7296         for (i = 0; i < 5; i++)
7297                 I915_WRITE(PEW + (i * 4), 0);
7298         for (i = 0; i < 3; i++)
7299                 I915_WRITE(DEW + (i * 4), 0);
7300
7301         /* Program P-state weights to account for frequency power adjustment */
7302         for (i = 0; i < 16; i++) {
7303                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7304                 unsigned long freq = intel_pxfreq(pxvidfreq);
7305                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7306                         PXVFREQ_PX_SHIFT;
7307                 unsigned long val;
7308
7309                 val = vid * vid;
7310                 val *= (freq / 1000);
7311                 val *= 255;
7312                 val /= (127*127*900);
7313                 if (val > 0xff)
7314                         DRM_ERROR("bad pxval: %ld\n", val);
7315                 pxw[i] = val;
7316         }
7317         /* Render standby states get 0 weight */
7318         pxw[14] = 0;
7319         pxw[15] = 0;
7320
7321         for (i = 0; i < 4; i++) {
7322                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7323                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7324                 I915_WRITE(PXW + (i * 4), val);
7325         }
7326
7327         /* Adjust magic regs to magic values (more experimental results) */
7328         I915_WRITE(OGW0, 0);
7329         I915_WRITE(OGW1, 0);
7330         I915_WRITE(EG0, 0x00007f00);
7331         I915_WRITE(EG1, 0x0000000e);
7332         I915_WRITE(EG2, 0x000e0000);
7333         I915_WRITE(EG3, 0x68000300);
7334         I915_WRITE(EG4, 0x42000000);
7335         I915_WRITE(EG5, 0x00140031);
7336         I915_WRITE(EG6, 0);
7337         I915_WRITE(EG7, 0);
7338
7339         for (i = 0; i < 8; i++)
7340                 I915_WRITE(PXWL + (i * 4), 0);
7341
7342         /* Enable PMON + select events */
7343         I915_WRITE(ECR, 0x80000019);
7344
7345         lcfuse = I915_READ(LCFUSE02);
7346
7347         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7348 }
7349
7350 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7351 {
7352         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7353         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7354         u32 pcu_mbox, rc6_mask = 0;
7355         int cur_freq, min_freq, max_freq;
7356         int i;
7357
7358         /* Here begins a magic sequence of register writes to enable
7359          * auto-downclocking.
7360          *
7361          * Perhaps there might be some value in exposing these to
7362          * userspace...
7363          */
7364         I915_WRITE(GEN6_RC_STATE, 0);
7365         mutex_lock(&dev_priv->dev->struct_mutex);
7366         gen6_gt_force_wake_get(dev_priv);
7367
7368         /* disable the counters and set deterministic thresholds */
7369         I915_WRITE(GEN6_RC_CONTROL, 0);
7370
7371         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7372         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7373         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7374         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7375         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7376
7377         for (i = 0; i < I915_NUM_RINGS; i++)
7378                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7379
7380         I915_WRITE(GEN6_RC_SLEEP, 0);
7381         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7382         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7383         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7384         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7385
7386         if (i915_enable_rc6)
7387                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7388                         GEN6_RC_CTL_RC6_ENABLE;
7389
7390         I915_WRITE(GEN6_RC_CONTROL,
7391                    rc6_mask |
7392                    GEN6_RC_CTL_EI_MODE(1) |
7393                    GEN6_RC_CTL_HW_ENABLE);
7394
7395         I915_WRITE(GEN6_RPNSWREQ,
7396                    GEN6_FREQUENCY(10) |
7397                    GEN6_OFFSET(0) |
7398                    GEN6_AGGRESSIVE_TURBO);
7399         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7400                    GEN6_FREQUENCY(12));
7401
7402         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7403         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7404                    18 << 24 |
7405                    6 << 16);
7406         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7407         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7408         I915_WRITE(GEN6_RP_UP_EI, 100000);
7409         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7410         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7411         I915_WRITE(GEN6_RP_CONTROL,
7412                    GEN6_RP_MEDIA_TURBO |
7413                    GEN6_RP_USE_NORMAL_FREQ |
7414                    GEN6_RP_MEDIA_IS_GFX |
7415                    GEN6_RP_ENABLE |
7416                    GEN6_RP_UP_BUSY_AVG |
7417                    GEN6_RP_DOWN_IDLE_CONT);
7418
7419         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7420                      500))
7421                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7422
7423         I915_WRITE(GEN6_PCODE_DATA, 0);
7424         I915_WRITE(GEN6_PCODE_MAILBOX,
7425                    GEN6_PCODE_READY |
7426                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7427         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7428                      500))
7429                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7430
7431         min_freq = (rp_state_cap & 0xff0000) >> 16;
7432         max_freq = rp_state_cap & 0xff;
7433         cur_freq = (gt_perf_status & 0xff00) >> 8;
7434
7435         /* Check for overclock support */
7436         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7437                      500))
7438                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7439         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7440         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7441         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7442                      500))
7443                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7444         if (pcu_mbox & (1<<31)) { /* OC supported */
7445                 max_freq = pcu_mbox & 0xff;
7446                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7447         }
7448
7449         /* In units of 100MHz */
7450         dev_priv->max_delay = max_freq;
7451         dev_priv->min_delay = min_freq;
7452         dev_priv->cur_delay = cur_freq;
7453
7454         /* requires MSI enabled */
7455         I915_WRITE(GEN6_PMIER,
7456                    GEN6_PM_MBOX_EVENT |
7457                    GEN6_PM_THERMAL_EVENT |
7458                    GEN6_PM_RP_DOWN_TIMEOUT |
7459                    GEN6_PM_RP_UP_THRESHOLD |
7460                    GEN6_PM_RP_DOWN_THRESHOLD |
7461                    GEN6_PM_RP_UP_EI_EXPIRED |
7462                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7463         spin_lock_irq(&dev_priv->rps_lock);
7464         WARN_ON(dev_priv->pm_iir != 0);
7465         I915_WRITE(GEN6_PMIMR, 0);
7466         spin_unlock_irq(&dev_priv->rps_lock);
7467         /* enable all PM interrupts */
7468         I915_WRITE(GEN6_PMINTRMSK, 0);
7469
7470         gen6_gt_force_wake_put(dev_priv);
7471         mutex_unlock(&dev_priv->dev->struct_mutex);
7472 }
7473
7474 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7475 {
7476         int min_freq = 15;
7477         int gpu_freq, ia_freq, max_ia_freq;
7478         int scaling_factor = 180;
7479
7480         max_ia_freq = cpufreq_quick_get_max(0);
7481         /*
7482          * Default to measured freq if none found, PCU will ensure we don't go
7483          * over
7484          */
7485         if (!max_ia_freq)
7486                 max_ia_freq = tsc_khz;
7487
7488         /* Convert from kHz to MHz */
7489         max_ia_freq /= 1000;
7490
7491         mutex_lock(&dev_priv->dev->struct_mutex);
7492
7493         /*
7494          * For each potential GPU frequency, load a ring frequency we'd like
7495          * to use for memory access.  We do this by specifying the IA frequency
7496          * the PCU should use as a reference to determine the ring frequency.
7497          */
7498         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7499              gpu_freq--) {
7500                 int diff = dev_priv->max_delay - gpu_freq;
7501
7502                 /*
7503                  * For GPU frequencies less than 750MHz, just use the lowest
7504                  * ring freq.
7505                  */
7506                 if (gpu_freq < min_freq)
7507                         ia_freq = 800;
7508                 else
7509                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7510                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7511
7512                 I915_WRITE(GEN6_PCODE_DATA,
7513                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7514                            gpu_freq);
7515                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7516                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7517                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7518                               GEN6_PCODE_READY) == 0, 10)) {
7519                         DRM_ERROR("pcode write of freq table timed out\n");
7520                         continue;
7521                 }
7522         }
7523
7524         mutex_unlock(&dev_priv->dev->struct_mutex);
7525 }
7526
7527 static void ironlake_init_clock_gating(struct drm_device *dev)
7528 {
7529         struct drm_i915_private *dev_priv = dev->dev_private;
7530         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7531
7532         /* Required for FBC */
7533         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7534                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7535                 DPFDUNIT_CLOCK_GATE_DISABLE;
7536         /* Required for CxSR */
7537         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7538
7539         I915_WRITE(PCH_3DCGDIS0,
7540                    MARIUNIT_CLOCK_GATE_DISABLE |
7541                    SVSMUNIT_CLOCK_GATE_DISABLE);
7542         I915_WRITE(PCH_3DCGDIS1,
7543                    VFMUNIT_CLOCK_GATE_DISABLE);
7544
7545         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7546
7547         /*
7548          * According to the spec the following bits should be set in
7549          * order to enable memory self-refresh
7550          * The bit 22/21 of 0x42004
7551          * The bit 5 of 0x42020
7552          * The bit 15 of 0x45000
7553          */
7554         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7555                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7556                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7557         I915_WRITE(ILK_DSPCLK_GATE,
7558                    (I915_READ(ILK_DSPCLK_GATE) |
7559                     ILK_DPARB_CLK_GATE));
7560         I915_WRITE(DISP_ARB_CTL,
7561                    (I915_READ(DISP_ARB_CTL) |
7562                     DISP_FBC_WM_DIS));
7563         I915_WRITE(WM3_LP_ILK, 0);
7564         I915_WRITE(WM2_LP_ILK, 0);
7565         I915_WRITE(WM1_LP_ILK, 0);
7566
7567         /*
7568          * Based on the document from hardware guys the following bits
7569          * should be set unconditionally in order to enable FBC.
7570          * The bit 22 of 0x42000
7571          * The bit 22 of 0x42004
7572          * The bit 7,8,9 of 0x42020.
7573          */
7574         if (IS_IRONLAKE_M(dev)) {
7575                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7576                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7577                            ILK_FBCQ_DIS);
7578                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7579                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7580                            ILK_DPARB_GATE);
7581                 I915_WRITE(ILK_DSPCLK_GATE,
7582                            I915_READ(ILK_DSPCLK_GATE) |
7583                            ILK_DPFC_DIS1 |
7584                            ILK_DPFC_DIS2 |
7585                            ILK_CLK_FBC);
7586         }
7587
7588         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7589                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7590                    ILK_ELPIN_409_SELECT);
7591         I915_WRITE(_3D_CHICKEN2,
7592                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7593                    _3D_CHICKEN2_WM_READ_PIPELINED);
7594 }
7595
7596 static void gen6_init_clock_gating(struct drm_device *dev)
7597 {
7598         struct drm_i915_private *dev_priv = dev->dev_private;
7599         int pipe;
7600         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7601
7602         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7603
7604         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7605                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7606                    ILK_ELPIN_409_SELECT);
7607
7608         I915_WRITE(WM3_LP_ILK, 0);
7609         I915_WRITE(WM2_LP_ILK, 0);
7610         I915_WRITE(WM1_LP_ILK, 0);
7611
7612         /*
7613          * According to the spec the following bits should be
7614          * set in order to enable memory self-refresh and fbc:
7615          * The bit21 and bit22 of 0x42000
7616          * The bit21 and bit22 of 0x42004
7617          * The bit5 and bit7 of 0x42020
7618          * The bit14 of 0x70180
7619          * The bit14 of 0x71180
7620          */
7621         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7622                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7623                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7624         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7625                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7626                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7627         I915_WRITE(ILK_DSPCLK_GATE,
7628                    I915_READ(ILK_DSPCLK_GATE) |
7629                    ILK_DPARB_CLK_GATE  |
7630                    ILK_DPFD_CLK_GATE);
7631
7632         for_each_pipe(pipe)
7633                 I915_WRITE(DSPCNTR(pipe),
7634                            I915_READ(DSPCNTR(pipe)) |
7635                            DISPPLANE_TRICKLE_FEED_DISABLE);
7636 }
7637
7638 static void ivybridge_init_clock_gating(struct drm_device *dev)
7639 {
7640         struct drm_i915_private *dev_priv = dev->dev_private;
7641         int pipe;
7642         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7643
7644         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7645
7646         I915_WRITE(WM3_LP_ILK, 0);
7647         I915_WRITE(WM2_LP_ILK, 0);
7648         I915_WRITE(WM1_LP_ILK, 0);
7649
7650         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7651
7652         for_each_pipe(pipe)
7653                 I915_WRITE(DSPCNTR(pipe),
7654                            I915_READ(DSPCNTR(pipe)) |
7655                            DISPPLANE_TRICKLE_FEED_DISABLE);
7656 }
7657
7658 static void g4x_init_clock_gating(struct drm_device *dev)
7659 {
7660         struct drm_i915_private *dev_priv = dev->dev_private;
7661         uint32_t dspclk_gate;
7662
7663         I915_WRITE(RENCLK_GATE_D1, 0);
7664         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7665                    GS_UNIT_CLOCK_GATE_DISABLE |
7666                    CL_UNIT_CLOCK_GATE_DISABLE);
7667         I915_WRITE(RAMCLK_GATE_D, 0);
7668         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7669                 OVRUNIT_CLOCK_GATE_DISABLE |
7670                 OVCUNIT_CLOCK_GATE_DISABLE;
7671         if (IS_GM45(dev))
7672                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7673         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7674 }
7675
7676 static void crestline_init_clock_gating(struct drm_device *dev)
7677 {
7678         struct drm_i915_private *dev_priv = dev->dev_private;
7679
7680         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7681         I915_WRITE(RENCLK_GATE_D2, 0);
7682         I915_WRITE(DSPCLK_GATE_D, 0);
7683         I915_WRITE(RAMCLK_GATE_D, 0);
7684         I915_WRITE16(DEUC, 0);
7685 }
7686
7687 static void broadwater_init_clock_gating(struct drm_device *dev)
7688 {
7689         struct drm_i915_private *dev_priv = dev->dev_private;
7690
7691         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7692                    I965_RCC_CLOCK_GATE_DISABLE |
7693                    I965_RCPB_CLOCK_GATE_DISABLE |
7694                    I965_ISC_CLOCK_GATE_DISABLE |
7695                    I965_FBC_CLOCK_GATE_DISABLE);
7696         I915_WRITE(RENCLK_GATE_D2, 0);
7697 }
7698
7699 static void gen3_init_clock_gating(struct drm_device *dev)
7700 {
7701         struct drm_i915_private *dev_priv = dev->dev_private;
7702         u32 dstate = I915_READ(D_STATE);
7703
7704         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7705                 DSTATE_DOT_CLOCK_GATING;
7706         I915_WRITE(D_STATE, dstate);
7707 }
7708
7709 static void i85x_init_clock_gating(struct drm_device *dev)
7710 {
7711         struct drm_i915_private *dev_priv = dev->dev_private;
7712
7713         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7714 }
7715
7716 static void i830_init_clock_gating(struct drm_device *dev)
7717 {
7718         struct drm_i915_private *dev_priv = dev->dev_private;
7719
7720         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7721 }
7722
7723 static void ibx_init_clock_gating(struct drm_device *dev)
7724 {
7725         struct drm_i915_private *dev_priv = dev->dev_private;
7726
7727         /*
7728          * On Ibex Peak and Cougar Point, we need to disable clock
7729          * gating for the panel power sequencer or it will fail to
7730          * start up when no ports are active.
7731          */
7732         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7733 }
7734
7735 static void cpt_init_clock_gating(struct drm_device *dev)
7736 {
7737         struct drm_i915_private *dev_priv = dev->dev_private;
7738
7739         /*
7740          * On Ibex Peak and Cougar Point, we need to disable clock
7741          * gating for the panel power sequencer or it will fail to
7742          * start up when no ports are active.
7743          */
7744         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7745         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7746                    DPLS_EDP_PPS_FIX_DIS);
7747 }
7748
7749 static void ironlake_teardown_rc6(struct drm_device *dev)
7750 {
7751         struct drm_i915_private *dev_priv = dev->dev_private;
7752
7753         if (dev_priv->renderctx) {
7754                 i915_gem_object_unpin(dev_priv->renderctx);
7755                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7756                 dev_priv->renderctx = NULL;
7757         }
7758
7759         if (dev_priv->pwrctx) {
7760                 i915_gem_object_unpin(dev_priv->pwrctx);
7761                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7762                 dev_priv->pwrctx = NULL;
7763         }
7764 }
7765
7766 static void ironlake_disable_rc6(struct drm_device *dev)
7767 {
7768         struct drm_i915_private *dev_priv = dev->dev_private;
7769
7770         if (I915_READ(PWRCTXA)) {
7771                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7772                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7773                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7774                          50);
7775
7776                 I915_WRITE(PWRCTXA, 0);
7777                 POSTING_READ(PWRCTXA);
7778
7779                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7780                 POSTING_READ(RSTDBYCTL);
7781         }
7782
7783         ironlake_teardown_rc6(dev);
7784 }
7785
7786 static int ironlake_setup_rc6(struct drm_device *dev)
7787 {
7788         struct drm_i915_private *dev_priv = dev->dev_private;
7789
7790         if (dev_priv->renderctx == NULL)
7791                 dev_priv->renderctx = intel_alloc_context_page(dev);
7792         if (!dev_priv->renderctx)
7793                 return -ENOMEM;
7794
7795         if (dev_priv->pwrctx == NULL)
7796                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7797         if (!dev_priv->pwrctx) {
7798                 ironlake_teardown_rc6(dev);
7799                 return -ENOMEM;
7800         }
7801
7802         return 0;
7803 }
7804
7805 void ironlake_enable_rc6(struct drm_device *dev)
7806 {
7807         struct drm_i915_private *dev_priv = dev->dev_private;
7808         int ret;
7809
7810         /* rc6 disabled by default due to repeated reports of hanging during
7811          * boot and resume.
7812          */
7813         if (!i915_enable_rc6)
7814                 return;
7815
7816         mutex_lock(&dev->struct_mutex);
7817         ret = ironlake_setup_rc6(dev);
7818         if (ret) {
7819                 mutex_unlock(&dev->struct_mutex);
7820                 return;
7821         }
7822
7823         /*
7824          * GPU can automatically power down the render unit if given a page
7825          * to save state.
7826          */
7827         ret = BEGIN_LP_RING(6);
7828         if (ret) {
7829                 ironlake_teardown_rc6(dev);
7830                 mutex_unlock(&dev->struct_mutex);
7831                 return;
7832         }
7833
7834         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7835         OUT_RING(MI_SET_CONTEXT);
7836         OUT_RING(dev_priv->renderctx->gtt_offset |
7837                  MI_MM_SPACE_GTT |
7838                  MI_SAVE_EXT_STATE_EN |
7839                  MI_RESTORE_EXT_STATE_EN |
7840                  MI_RESTORE_INHIBIT);
7841         OUT_RING(MI_SUSPEND_FLUSH);
7842         OUT_RING(MI_NOOP);
7843         OUT_RING(MI_FLUSH);
7844         ADVANCE_LP_RING();
7845
7846         /*
7847          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7848          * does an implicit flush, combined with MI_FLUSH above, it should be
7849          * safe to assume that renderctx is valid
7850          */
7851         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7852         if (ret) {
7853                 DRM_ERROR("failed to enable ironlake power power savings\n");
7854                 ironlake_teardown_rc6(dev);
7855                 mutex_unlock(&dev->struct_mutex);
7856                 return;
7857         }
7858
7859         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7860         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7861         mutex_unlock(&dev->struct_mutex);
7862 }
7863
7864 void intel_init_clock_gating(struct drm_device *dev)
7865 {
7866         struct drm_i915_private *dev_priv = dev->dev_private;
7867
7868         dev_priv->display.init_clock_gating(dev);
7869
7870         if (dev_priv->display.init_pch_clock_gating)
7871                 dev_priv->display.init_pch_clock_gating(dev);
7872 }
7873
7874 /* Set up chip specific display functions */
7875 static void intel_init_display(struct drm_device *dev)
7876 {
7877         struct drm_i915_private *dev_priv = dev->dev_private;
7878
7879         /* We always want a DPMS function */
7880         if (HAS_PCH_SPLIT(dev)) {
7881                 dev_priv->display.dpms = ironlake_crtc_dpms;
7882                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7883                 dev_priv->display.update_plane = ironlake_update_plane;
7884         } else {
7885                 dev_priv->display.dpms = i9xx_crtc_dpms;
7886                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7887                 dev_priv->display.update_plane = i9xx_update_plane;
7888         }
7889
7890         if (I915_HAS_FBC(dev)) {
7891                 if (HAS_PCH_SPLIT(dev)) {
7892                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7893                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7894                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7895                 } else if (IS_GM45(dev)) {
7896                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7897                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7898                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7899                 } else if (IS_CRESTLINE(dev)) {
7900                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7901                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7902                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7903                 }
7904                 /* 855GM needs testing */
7905         }
7906
7907         /* Returns the core display clock speed */
7908         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7909                 dev_priv->display.get_display_clock_speed =
7910                         i945_get_display_clock_speed;
7911         else if (IS_I915G(dev))
7912                 dev_priv->display.get_display_clock_speed =
7913                         i915_get_display_clock_speed;
7914         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7915                 dev_priv->display.get_display_clock_speed =
7916                         i9xx_misc_get_display_clock_speed;
7917         else if (IS_I915GM(dev))
7918                 dev_priv->display.get_display_clock_speed =
7919                         i915gm_get_display_clock_speed;
7920         else if (IS_I865G(dev))
7921                 dev_priv->display.get_display_clock_speed =
7922                         i865_get_display_clock_speed;
7923         else if (IS_I85X(dev))
7924                 dev_priv->display.get_display_clock_speed =
7925                         i855_get_display_clock_speed;
7926         else /* 852, 830 */
7927                 dev_priv->display.get_display_clock_speed =
7928                         i830_get_display_clock_speed;
7929
7930         /* For FIFO watermark updates */
7931         if (HAS_PCH_SPLIT(dev)) {
7932                 if (HAS_PCH_IBX(dev))
7933                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7934                 else if (HAS_PCH_CPT(dev))
7935                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7936
7937                 if (IS_GEN5(dev)) {
7938                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7939                                 dev_priv->display.update_wm = ironlake_update_wm;
7940                         else {
7941                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7942                                               "Disable CxSR\n");
7943                                 dev_priv->display.update_wm = NULL;
7944                         }
7945                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7946                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7947                 } else if (IS_GEN6(dev)) {
7948                         if (SNB_READ_WM0_LATENCY()) {
7949                                 dev_priv->display.update_wm = sandybridge_update_wm;
7950                         } else {
7951                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7952                                               "Disable CxSR\n");
7953                                 dev_priv->display.update_wm = NULL;
7954                         }
7955                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7956                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7957                 } else if (IS_IVYBRIDGE(dev)) {
7958                         /* FIXME: detect B0+ stepping and use auto training */
7959                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7960                         if (SNB_READ_WM0_LATENCY()) {
7961                                 dev_priv->display.update_wm = sandybridge_update_wm;
7962                         } else {
7963                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7964                                               "Disable CxSR\n");
7965                                 dev_priv->display.update_wm = NULL;
7966                         }
7967                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7968
7969                 } else
7970                         dev_priv->display.update_wm = NULL;
7971         } else if (IS_PINEVIEW(dev)) {
7972                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7973                                             dev_priv->is_ddr3,
7974                                             dev_priv->fsb_freq,
7975                                             dev_priv->mem_freq)) {
7976                         DRM_INFO("failed to find known CxSR latency "
7977                                  "(found ddr%s fsb freq %d, mem freq %d), "
7978                                  "disabling CxSR\n",
7979                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7980                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7981                         /* Disable CxSR and never update its watermark again */
7982                         pineview_disable_cxsr(dev);
7983                         dev_priv->display.update_wm = NULL;
7984                 } else
7985                         dev_priv->display.update_wm = pineview_update_wm;
7986                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7987         } else if (IS_G4X(dev)) {
7988                 dev_priv->display.update_wm = g4x_update_wm;
7989                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7990         } else if (IS_GEN4(dev)) {
7991                 dev_priv->display.update_wm = i965_update_wm;
7992                 if (IS_CRESTLINE(dev))
7993                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7994                 else if (IS_BROADWATER(dev))
7995                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7996         } else if (IS_GEN3(dev)) {
7997                 dev_priv->display.update_wm = i9xx_update_wm;
7998                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7999                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8000         } else if (IS_I865G(dev)) {
8001                 dev_priv->display.update_wm = i830_update_wm;
8002                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8003                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8004         } else if (IS_I85X(dev)) {
8005                 dev_priv->display.update_wm = i9xx_update_wm;
8006                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8007                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8008         } else {
8009                 dev_priv->display.update_wm = i830_update_wm;
8010                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8011                 if (IS_845G(dev))
8012                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8013                 else
8014                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8015         }
8016
8017         /* Default just returns -ENODEV to indicate unsupported */
8018         dev_priv->display.queue_flip = intel_default_queue_flip;
8019
8020         switch (INTEL_INFO(dev)->gen) {
8021         case 2:
8022                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8023                 break;
8024
8025         case 3:
8026                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8027                 break;
8028
8029         case 4:
8030         case 5:
8031                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8032                 break;
8033
8034         case 6:
8035                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8036                 break;
8037         case 7:
8038                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8039                 break;
8040         }
8041 }
8042
8043 /*
8044  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8045  * resume, or other times.  This quirk makes sure that's the case for
8046  * affected systems.
8047  */
8048 static void quirk_pipea_force (struct drm_device *dev)
8049 {
8050         struct drm_i915_private *dev_priv = dev->dev_private;
8051
8052         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8053         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8054 }
8055
8056 struct intel_quirk {
8057         int device;
8058         int subsystem_vendor;
8059         int subsystem_device;
8060         void (*hook)(struct drm_device *dev);
8061 };
8062
8063 struct intel_quirk intel_quirks[] = {
8064         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8065         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8066         /* HP Mini needs pipe A force quirk (LP: #322104) */
8067         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8068
8069         /* Thinkpad R31 needs pipe A force quirk */
8070         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8071         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8072         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8073
8074         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8075         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8076         /* ThinkPad X40 needs pipe A force quirk */
8077
8078         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8079         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8080
8081         /* 855 & before need to leave pipe A & dpll A up */
8082         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8083         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8084 };
8085
8086 static void intel_init_quirks(struct drm_device *dev)
8087 {
8088         struct pci_dev *d = dev->pdev;
8089         int i;
8090
8091         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8092                 struct intel_quirk *q = &intel_quirks[i];
8093
8094                 if (d->device == q->device &&
8095                     (d->subsystem_vendor == q->subsystem_vendor ||
8096                      q->subsystem_vendor == PCI_ANY_ID) &&
8097                     (d->subsystem_device == q->subsystem_device ||
8098                      q->subsystem_device == PCI_ANY_ID))
8099                         q->hook(dev);
8100         }
8101 }
8102
8103 /* Disable the VGA plane that we never use */
8104 static void i915_disable_vga(struct drm_device *dev)
8105 {
8106         struct drm_i915_private *dev_priv = dev->dev_private;
8107         u8 sr1;
8108         u32 vga_reg;
8109
8110         if (HAS_PCH_SPLIT(dev))
8111                 vga_reg = CPU_VGACNTRL;
8112         else
8113                 vga_reg = VGACNTRL;
8114
8115         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8116         outb(1, VGA_SR_INDEX);
8117         sr1 = inb(VGA_SR_DATA);
8118         outb(sr1 | 1<<5, VGA_SR_DATA);
8119         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8120         udelay(300);
8121
8122         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8123         POSTING_READ(vga_reg);
8124 }
8125
8126 void intel_modeset_init(struct drm_device *dev)
8127 {
8128         struct drm_i915_private *dev_priv = dev->dev_private;
8129         int i;
8130
8131         drm_mode_config_init(dev);
8132
8133         dev->mode_config.min_width = 0;
8134         dev->mode_config.min_height = 0;
8135
8136         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8137
8138         intel_init_quirks(dev);
8139
8140         intel_init_display(dev);
8141
8142         if (IS_GEN2(dev)) {
8143                 dev->mode_config.max_width = 2048;
8144                 dev->mode_config.max_height = 2048;
8145         } else if (IS_GEN3(dev)) {
8146                 dev->mode_config.max_width = 4096;
8147                 dev->mode_config.max_height = 4096;
8148         } else {
8149                 dev->mode_config.max_width = 8192;
8150                 dev->mode_config.max_height = 8192;
8151         }
8152         dev->mode_config.fb_base = dev->agp->base;
8153
8154         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8155                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8156
8157         for (i = 0; i < dev_priv->num_pipe; i++) {
8158                 intel_crtc_init(dev, i);
8159         }
8160
8161         /* Just disable it once at startup */
8162         i915_disable_vga(dev);
8163         intel_setup_outputs(dev);
8164
8165         intel_init_clock_gating(dev);
8166
8167         if (IS_IRONLAKE_M(dev)) {
8168                 ironlake_enable_drps(dev);
8169                 intel_init_emon(dev);
8170         }
8171
8172         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8173                 gen6_enable_rps(dev_priv);
8174                 gen6_update_ring_freq(dev_priv);
8175         }
8176
8177         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8178         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8179                     (unsigned long)dev);
8180 }
8181
8182 void intel_modeset_gem_init(struct drm_device *dev)
8183 {
8184         if (IS_IRONLAKE_M(dev))
8185                 ironlake_enable_rc6(dev);
8186
8187         intel_setup_overlay(dev);
8188 }
8189
8190 void intel_modeset_cleanup(struct drm_device *dev)
8191 {
8192         struct drm_i915_private *dev_priv = dev->dev_private;
8193         struct drm_crtc *crtc;
8194         struct intel_crtc *intel_crtc;
8195
8196         drm_kms_helper_poll_fini(dev);
8197         mutex_lock(&dev->struct_mutex);
8198
8199         intel_unregister_dsm_handler();
8200
8201
8202         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8203                 /* Skip inactive CRTCs */
8204                 if (!crtc->fb)
8205                         continue;
8206
8207                 intel_crtc = to_intel_crtc(crtc);
8208                 intel_increase_pllclock(crtc);
8209         }
8210
8211         intel_disable_fbc(dev);
8212
8213         if (IS_IRONLAKE_M(dev))
8214                 ironlake_disable_drps(dev);
8215         if (IS_GEN6(dev) || IS_GEN7(dev))
8216                 gen6_disable_rps(dev);
8217
8218         if (IS_IRONLAKE_M(dev))
8219                 ironlake_disable_rc6(dev);
8220
8221         mutex_unlock(&dev->struct_mutex);
8222
8223         /* Disable the irq before mode object teardown, for the irq might
8224          * enqueue unpin/hotplug work. */
8225         drm_irq_uninstall(dev);
8226         cancel_work_sync(&dev_priv->hotplug_work);
8227
8228         /* Shut off idle work before the crtcs get freed. */
8229         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8230                 intel_crtc = to_intel_crtc(crtc);
8231                 del_timer_sync(&intel_crtc->idle_timer);
8232         }
8233         del_timer_sync(&dev_priv->idle_timer);
8234         cancel_work_sync(&dev_priv->idle_work);
8235
8236         drm_mode_config_cleanup(dev);
8237 }
8238
8239 /*
8240  * Return which encoder is currently attached for connector.
8241  */
8242 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8243 {
8244         return &intel_attached_encoder(connector)->base;
8245 }
8246
8247 void intel_connector_attach_encoder(struct intel_connector *connector,
8248                                     struct intel_encoder *encoder)
8249 {
8250         connector->encoder = encoder;
8251         drm_mode_connector_attach_encoder(&connector->base,
8252                                           &encoder->base);
8253 }
8254
8255 /*
8256  * set vga decode state - true == enable VGA decode
8257  */
8258 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8259 {
8260         struct drm_i915_private *dev_priv = dev->dev_private;
8261         u16 gmch_ctrl;
8262
8263         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8264         if (state)
8265                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8266         else
8267                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8268         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8269         return 0;
8270 }
8271
8272 #ifdef CONFIG_DEBUG_FS
8273 #include <linux/seq_file.h>
8274
8275 struct intel_display_error_state {
8276         struct intel_cursor_error_state {
8277                 u32 control;
8278                 u32 position;
8279                 u32 base;
8280                 u32 size;
8281         } cursor[2];
8282
8283         struct intel_pipe_error_state {
8284                 u32 conf;
8285                 u32 source;
8286
8287                 u32 htotal;
8288                 u32 hblank;
8289                 u32 hsync;
8290                 u32 vtotal;
8291                 u32 vblank;
8292                 u32 vsync;
8293         } pipe[2];
8294
8295         struct intel_plane_error_state {
8296                 u32 control;
8297                 u32 stride;
8298                 u32 size;
8299                 u32 pos;
8300                 u32 addr;
8301                 u32 surface;
8302                 u32 tile_offset;
8303         } plane[2];
8304 };
8305
8306 struct intel_display_error_state *
8307 intel_display_capture_error_state(struct drm_device *dev)
8308 {
8309         drm_i915_private_t *dev_priv = dev->dev_private;
8310         struct intel_display_error_state *error;
8311         int i;
8312
8313         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8314         if (error == NULL)
8315                 return NULL;
8316
8317         for (i = 0; i < 2; i++) {
8318                 error->cursor[i].control = I915_READ(CURCNTR(i));
8319                 error->cursor[i].position = I915_READ(CURPOS(i));
8320                 error->cursor[i].base = I915_READ(CURBASE(i));
8321
8322                 error->plane[i].control = I915_READ(DSPCNTR(i));
8323                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8324                 error->plane[i].size = I915_READ(DSPSIZE(i));
8325                 error->plane[i].pos= I915_READ(DSPPOS(i));
8326                 error->plane[i].addr = I915_READ(DSPADDR(i));
8327                 if (INTEL_INFO(dev)->gen >= 4) {
8328                         error->plane[i].surface = I915_READ(DSPSURF(i));
8329                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8330                 }
8331
8332                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8333                 error->pipe[i].source = I915_READ(PIPESRC(i));
8334                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8335                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8336                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8337                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8338                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8339                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8340         }
8341
8342         return error;
8343 }
8344
8345 void
8346 intel_display_print_error_state(struct seq_file *m,
8347                                 struct drm_device *dev,
8348                                 struct intel_display_error_state *error)
8349 {
8350         int i;
8351
8352         for (i = 0; i < 2; i++) {
8353                 seq_printf(m, "Pipe [%d]:\n", i);
8354                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8355                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8356                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8357                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8358                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8359                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8360                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8361                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8362
8363                 seq_printf(m, "Plane [%d]:\n", i);
8364                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8365                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8366                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8367                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8368                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8369                 if (INTEL_INFO(dev)->gen >= 4) {
8370                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8371                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8372                 }
8373
8374                 seq_printf(m, "Cursor [%d]:\n", i);
8375                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8376                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8377                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8378         }
8379 }
8380 #endif