drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include "drmP.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "drm_dp_helper.h"
  40
  41 #include "drm_crtc_helper.h"
  42
  43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  44
  45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  46 static void intel_update_watermarks(struct drm_device *dev);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51     /* given values */
  52     int n;
  53     int m1, m2;
  54     int p1, p2;
  55     /* derived values */
  56     int dot;
  57     int vco;
  58     int m;
  59     int p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63     int min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67     int dot_limit;
  68     int p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75     intel_p2_t      p2;
  76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                       int, int, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *best_clock);
  86 static bool
  87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  88                         int target, int refclk, intel_clock_t *best_clock);
  89
  90 static bool
  91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  92                       int target, int refclk, intel_clock_t *best_clock);
  93 static bool
  94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95                            int target, int refclk, intel_clock_t *best_clock);
  96
  97 static inline u32 /* units of 100MHz */
  98 intel_fdi_link_freq(struct drm_device *dev)
  99 {
 100         if (IS_GEN5(dev)) {
 101                 struct drm_i915_private *dev_priv = dev->dev_private;
 102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 103         } else
 104                 return 27;
 105 }
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 930000, .max = 1400000 },
 110         .n = { .min = 3, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 2 },
 118         .find_pll = intel_find_best_PLL,
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132         .find_pll = intel_find_best_PLL,
 133 };
 134
 135 static const intel_limit_t intel_limits_i9xx_sdvo = {
 136         .dot = { .min = 20000, .max = 400000 },
 137         .vco = { .min = 1400000, .max = 2800000 },
 138         .n = { .min = 1, .max = 6 },
 139         .m = { .min = 70, .max = 120 },
 140         .m1 = { .min = 10, .max = 22 },
 141         .m2 = { .min = 5, .max = 9 },
 142         .p = { .min = 5, .max = 80 },
 143         .p1 = { .min = 1, .max = 8 },
 144         .p2 = { .dot_limit = 200000,
 145                 .p2_slow = 10, .p2_fast = 5 },
 146         .find_pll = intel_find_best_PLL,
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 10, .max = 22 },
 155         .m2 = { .min = 5, .max = 9 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160         .find_pll = intel_find_best_PLL,
 161 };
 162
 163
 164 static const intel_limit_t intel_limits_g4x_sdvo = {
 165         .dot = { .min = 25000, .max = 270000 },
 166         .vco = { .min = 1750000, .max = 3500000},
 167         .n = { .min = 1, .max = 4 },
 168         .m = { .min = 104, .max = 138 },
 169         .m1 = { .min = 17, .max = 23 },
 170         .m2 = { .min = 5, .max = 11 },
 171         .p = { .min = 10, .max = 30 },
 172         .p1 = { .min = 1, .max = 3},
 173         .p2 = { .dot_limit = 270000,
 174                 .p2_slow = 10,
 175                 .p2_fast = 10
 176         },
 177         .find_pll = intel_g4x_find_best_PLL,
 178 };
 179
 180 static const intel_limit_t intel_limits_g4x_hdmi = {
 181         .dot = { .min = 22000, .max = 400000 },
 182         .vco = { .min = 1750000, .max = 3500000},
 183         .n = { .min = 1, .max = 4 },
 184         .m = { .min = 104, .max = 138 },
 185         .m1 = { .min = 16, .max = 23 },
 186         .m2 = { .min = 5, .max = 11 },
 187         .p = { .min = 5, .max = 80 },
 188         .p1 = { .min = 1, .max = 8},
 189         .p2 = { .dot_limit = 165000,
 190                 .p2_slow = 10, .p2_fast = 5 },
 191         .find_pll = intel_g4x_find_best_PLL,
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206         .find_pll = intel_g4x_find_best_PLL,
 207 };
 208
 209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 210         .dot = { .min = 80000, .max = 224000 },
 211         .vco = { .min = 1750000, .max = 3500000 },
 212         .n = { .min = 1, .max = 3 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 14, .max = 42 },
 217         .p1 = { .min = 2, .max = 6 },
 218         .p2 = { .dot_limit = 0,
 219                 .p2_slow = 7, .p2_fast = 7
 220         },
 221         .find_pll = intel_g4x_find_best_PLL,
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_display_port = {
 225         .dot = { .min = 161670, .max = 227000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 2 },
 228         .m = { .min = 97, .max = 108 },
 229         .m1 = { .min = 0x10, .max = 0x12 },
 230         .m2 = { .min = 0x05, .max = 0x06 },
 231         .p = { .min = 10, .max = 20 },
 232         .p1 = { .min = 1, .max = 2},
 233         .p2 = { .dot_limit = 0,
 234                 .p2_slow = 10, .p2_fast = 10 },
 235         .find_pll = intel_find_pll_g4x_dp,
 236 };
 237
 238 static const intel_limit_t intel_limits_pineview_sdvo = {
 239         .dot = { .min = 20000, .max = 400000},
 240         .vco = { .min = 1700000, .max = 3500000 },
 241         /* Pineview's Ncounter is a ring counter */
 242         .n = { .min = 3, .max = 6 },
 243         .m = { .min = 2, .max = 256 },
 244         /* Pineview only has one combined m divider, which we treat as m2. */
 245         .m1 = { .min = 0, .max = 0 },
 246         .m2 = { .min = 0, .max = 254 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8 },
 249         .p2 = { .dot_limit = 200000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251         .find_pll = intel_find_best_PLL,
 252 };
 253
 254 static const intel_limit_t intel_limits_pineview_lvds = {
 255         .dot = { .min = 20000, .max = 400000 },
 256         .vco = { .min = 1700000, .max = 3500000 },
 257         .n = { .min = 3, .max = 6 },
 258         .m = { .min = 2, .max = 256 },
 259         .m1 = { .min = 0, .max = 0 },
 260         .m2 = { .min = 0, .max = 254 },
 261         .p = { .min = 7, .max = 112 },
 262         .p1 = { .min = 1, .max = 8 },
 263         .p2 = { .dot_limit = 112000,
 264                 .p2_slow = 14, .p2_fast = 14 },
 265         .find_pll = intel_find_best_PLL,
 266 };
 267
 268 /* Ironlake / Sandybridge
 269  *
 270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 271  * the range value for them is (actual_value - 2).
 272  */
 273 static const intel_limit_t intel_limits_ironlake_dac = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 5 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_g4x_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 118 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_g4x_find_best_PLL,
 299 };
 300
 301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 3 },
 305         .m = { .min = 79, .max = 127 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 14, .max = 56 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 7, .p2_fast = 7 },
 312         .find_pll = intel_g4x_find_best_PLL,
 313 };
 314
 315 /* LVDS 100mhz refclk limits. */
 316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 2 },
 320         .m = { .min = 79, .max = 126 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2,.max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327         .find_pll = intel_g4x_find_best_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 126 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 42 },
 338         .p1 = { .min = 2,.max = 6 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341         .find_pll = intel_g4x_find_best_PLL,
 342 };
 343
 344 static const intel_limit_t intel_limits_ironlake_display_port = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000},
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 81, .max = 90 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 10, .max = 20 },
 352         .p1 = { .min = 1, .max = 2},
 353         .p2 = { .dot_limit = 0,
 354                 .p2_slow = 10, .p2_fast = 10 },
 355         .find_pll = intel_find_pll_ironlake_dp,
 356 };
 357
 358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 359                                                 int refclk)
 360 {
 361         struct drm_device *dev = crtc->dev;
 362         struct drm_i915_private *dev_priv = dev->dev_private;
 363         const intel_limit_t *limit;
 364
 365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 367                     LVDS_CLKB_POWER_UP) {
 368                         /* LVDS dual channel */
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_dual_lvds;
 373                 } else {
 374                         if (refclk == 100000)
 375                                 limit = &intel_limits_ironlake_single_lvds_100m;
 376                         else
 377                                 limit = &intel_limits_ironlake_single_lvds;
 378                 }
 379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 380                         HAS_eDP)
 381                 limit = &intel_limits_ironlake_display_port;
 382         else
 383                 limit = &intel_limits_ironlake_dac;
 384
 385         return limit;
 386 }
 387
 388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 389 {
 390         struct drm_device *dev = crtc->dev;
 391         struct drm_i915_private *dev_priv = dev->dev_private;
 392         const intel_limit_t *limit;
 393
 394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 396                     LVDS_CLKB_POWER_UP)
 397                         /* LVDS with dual channel */
 398                         limit = &intel_limits_g4x_dual_channel_lvds;
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits_g4x_single_channel_lvds;
 402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 404                 limit = &intel_limits_g4x_hdmi;
 405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 406                 limit = &intel_limits_g4x_sdvo;
 407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 408                 limit = &intel_limits_g4x_display_port;
 409         } else /* The option is for other outputs */
 410                 limit = &intel_limits_i9xx_sdvo;
 411
 412         return limit;
 413 }
 414
 415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 416 {
 417         struct drm_device *dev = crtc->dev;
 418         const intel_limit_t *limit;
 419
 420         if (HAS_PCH_SPLIT(dev))
 421                 limit = intel_ironlake_limit(crtc, refclk);
 422         else if (IS_G4X(dev)) {
 423                 limit = intel_g4x_limit(crtc);
 424         } else if (IS_PINEVIEW(dev)) {
 425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 426                         limit = &intel_limits_pineview_lvds;
 427                 else
 428                         limit = &intel_limits_pineview_sdvo;
 429         } else if (!IS_GEN2(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_i9xx_lvds;
 432                 else
 433                         limit = &intel_limits_i9xx_sdvo;
 434         } else {
 435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 436                         limit = &intel_limits_i8xx_lvds;
 437                 else
 438                         limit = &intel_limits_i8xx_dvo;
 439         }
 440         return limit;
 441 }
 442
 443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 444 static void pineview_clock(int refclk, intel_clock_t *clock)
 445 {
 446         clock->m = clock->m2 + 2;
 447         clock->p = clock->p1 * clock->p2;
 448         clock->vco = refclk * clock->m / clock->n;
 449         clock->dot = clock->vco / clock->p;
 450 }
 451
 452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 453 {
 454         if (IS_PINEVIEW(dev)) {
 455                 pineview_clock(refclk, clock);
 456                 return;
 457         }
 458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 459         clock->p = clock->p1 * clock->p2;
 460         clock->vco = refclk * clock->m / (clock->n + 2);
 461         clock->dot = clock->vco / clock->p;
 462 }
 463
 464 /**
 465  * Returns whether any output on the specified pipe is of the specified type
 466  */
 467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         struct drm_mode_config *mode_config = &dev->mode_config;
 471         struct intel_encoder *encoder;
 472
 473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 474                 if (encoder->base.crtc == crtc && encoder->type == type)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 481 /**
 482  * Returns whether the given set of divisors are valid for a given refclk with
 483  * the given connectors.
 484  */
 485
 486 static bool intel_PLL_is_valid(struct drm_device *dev,
 487                                const intel_limit_t *limit,
 488                                const intel_clock_t *clock)
 489 {
 490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 491                 INTELPllInvalid ("p1 out of range\n");
 492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 493                 INTELPllInvalid ("p out of range\n");
 494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 495                 INTELPllInvalid ("m2 out of range\n");
 496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 497                 INTELPllInvalid ("m1 out of range\n");
 498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 499                 INTELPllInvalid ("m1 <= m2\n");
 500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 501                 INTELPllInvalid ("m out of range\n");
 502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 503                 INTELPllInvalid ("n out of range\n");
 504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 505                 INTELPllInvalid ("vco out of range\n");
 506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 507          * connector, etc., rather than just a single range.
 508          */
 509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 510                 INTELPllInvalid ("dot out of range\n");
 511
 512         return true;
 513 }
 514
 515 static bool
 516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 517                     int target, int refclk, intel_clock_t *best_clock)
 518
 519 {
 520         struct drm_device *dev = crtc->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         intel_clock_t clock;
 523         int err = target;
 524
 525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 526             (I915_READ(LVDS)) != 0) {
 527                 /*
 528                  * For LVDS, if the panel is on, just rely on its current
 529                  * settings for dual-channel.  We haven't figured out how to
 530                  * reliably set up different single/dual channel state, if we
 531                  * even can.
 532                  */
 533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 534                     LVDS_CLKB_POWER_UP)
 535                         clock.p2 = limit->p2.p2_fast;
 536                 else
 537                         clock.p2 = limit->p2.p2_slow;
 538         } else {
 539                 if (target < limit->p2.dot_limit)
 540                         clock.p2 = limit->p2.p2_slow;
 541                 else
 542                         clock.p2 = limit->p2.p2_fast;
 543         }
 544
 545         memset (best_clock, 0, sizeof (*best_clock));
 546
 547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 548              clock.m1++) {
 549                 for (clock.m2 = limit->m2.min;
 550                      clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in Pineview */
 552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min;
 555                              clock.n <= limit->n.max; clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                         clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561                                         if (!intel_PLL_is_valid(dev, limit,
 562                                                                 &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00585 */
 588         int err_most = (target >> 8) + (target >> 9);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 int lvds_reg;
 593
 594                 if (HAS_PCH_SPLIT(dev))
 595                         lvds_reg = PCH_LVDS;
 596                 else
 597                         lvds_reg = LVDS;
 598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 599                     LVDS_CLKB_POWER_UP)
 600                         clock.p2 = limit->p2.p2_fast;
 601                 else
 602                         clock.p2 = limit->p2.p2_slow;
 603         } else {
 604                 if (target < limit->p2.dot_limit)
 605                         clock.p2 = limit->p2.p2_slow;
 606                 else
 607                         clock.p2 = limit->p2.p2_fast;
 608         }
 609
 610         memset(best_clock, 0, sizeof(*best_clock));
 611         max_n = limit->n.max;
 612         /* based on hardware requirement, prefer smaller n to precision */
 613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 614                 /* based on hardware requirement, prefere larger m1,m2 */
 615                 for (clock.m1 = limit->m1.max;
 616                      clock.m1 >= limit->m1.min; clock.m1--) {
 617                         for (clock.m2 = limit->m2.max;
 618                              clock.m2 >= limit->m2.min; clock.m2--) {
 619                                 for (clock.p1 = limit->p1.max;
 620                                      clock.p1 >= limit->p1.min; clock.p1--) {
 621                                         int this_err;
 622
 623                                         intel_clock(dev, refclk, &clock);
 624                                         if (!intel_PLL_is_valid(dev, limit,
 625                                                                 &clock))
 626                                                 continue;
 627
 628                                         this_err = abs(clock.dot - target);
 629                                         if (this_err < err_most) {
 630                                                 *best_clock = clock;
 631                                                 err_most = this_err;
 632                                                 max_n = clock.n;
 633                                                 found = true;
 634                                         }
 635                                 }
 636                         }
 637                 }
 638         }
 639         return found;
 640 }
 641
 642 static bool
 643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 644                            int target, int refclk, intel_clock_t *best_clock)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         intel_clock_t clock;
 648
 649         if (target < 200000) {
 650                 clock.n = 1;
 651                 clock.p1 = 2;
 652                 clock.p2 = 10;
 653                 clock.m1 = 12;
 654                 clock.m2 = 9;
 655         } else {
 656                 clock.n = 2;
 657                 clock.p1 = 1;
 658                 clock.p2 = 10;
 659                 clock.m1 = 14;
 660                 clock.m2 = 8;
 661         }
 662         intel_clock(dev, refclk, &clock);
 663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 664         return true;
 665 }
 666
 667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 668 static bool
 669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                       int target, int refclk, intel_clock_t *best_clock)
 671 {
 672         intel_clock_t clock;
 673         if (target < 200000) {
 674                 clock.p1 = 2;
 675                 clock.p2 = 10;
 676                 clock.n = 2;
 677                 clock.m1 = 23;
 678                 clock.m2 = 8;
 679         } else {
 680                 clock.p1 = 1;
 681                 clock.p2 = 10;
 682                 clock.n = 1;
 683                 clock.m1 = 14;
 684                 clock.m2 = 2;
 685         }
 686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 687         clock.p = (clock.p1 * clock.p2);
 688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 689         clock.vco = 0;
 690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 691         return true;
 692 }
 693
 694 /**
 695  * intel_wait_for_vblank - wait for vblank on a given pipe
 696  * @dev: drm device
 697  * @pipe: pipe to wait for
 698  *
 699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 700  * mode setting code.
 701  */
 702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 703 {
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         int pipestat_reg = PIPESTAT(pipe);
 706
 707         /* Clear existing vblank status. Note this will clear any other
 708          * sticky status fields as well.
 709          *
 710          * This races with i915_driver_irq_handler() with the result
 711          * that either function could miss a vblank event.  Here it is not
 712          * fatal, as we will either wait upon the next vblank interrupt or
 713          * timeout.  Generally speaking intel_wait_for_vblank() is only
 714          * called during modeset at which time the GPU should be idle and
 715          * should *not* be performing page flips and thus not waiting on
 716          * vblanks...
 717          * Currently, the result of us stealing a vblank from the irq
 718          * handler is that a single frame will be skipped during swapbuffers.
 719          */
 720         I915_WRITE(pipestat_reg,
 721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 722
 723         /* Wait for vblank interrupt bit to set */
 724         if (wait_for(I915_READ(pipestat_reg) &
 725                      PIPE_VBLANK_INTERRUPT_STATUS,
 726                      50))
 727                 DRM_DEBUG_KMS("vblank wait timed out\n");
 728 }
 729
 730 /*
 731  * intel_wait_for_pipe_off - wait for pipe to turn off
 732  * @dev: drm device
 733  * @pipe: pipe to wait for
 734  *
 735  * After disabling a pipe, we can't wait for vblank in the usual way,
 736  * spinning on the vblank interrupt status bit, since we won't actually
 737  * see an interrupt when the pipe is disabled.
 738  *
 739  * On Gen4 and above:
 740  *   wait for the pipe register state bit to turn off
 741  *
 742  * Otherwise:
 743  *   wait for the display line value to settle (it usually
 744  *   ends up stopping at the start of the next frame).
 745  *
 746  */
 747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750
 751         if (INTEL_INFO(dev)->gen >= 4) {
 752                 int reg = PIPECONF(pipe);
 753
 754                 /* Wait for the Pipe State to go off */
 755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 756                              100))
 757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 758         } else {
 759                 u32 last_line;
 760                 int reg = PIPEDSL(pipe);
 761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 762
 763                 /* Wait for the display line to settle */
 764                 do {
 765                         last_line = I915_READ(reg) & DSL_LINEMASK;
 766                         mdelay(5);
 767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 768                          time_after(timeout, jiffies));
 769                 if (time_after(jiffies, timeout))
 770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 771         }
 772 }
 773
 774 static const char *state_string(bool enabled)
 775 {
 776         return enabled ? "on" : "off";
 777 }
 778
 779 /* Only for pre-ILK configs */
 780 static void assert_pll(struct drm_i915_private *dev_priv,
 781                        enum pipe pipe, bool state)
 782 {
 783         int reg;
 784         u32 val;
 785         bool cur_state;
 786
 787         reg = DPLL(pipe);
 788         val = I915_READ(reg);
 789         cur_state = !!(val & DPLL_VCO_ENABLE);
 790         WARN(cur_state != state,
 791              "PLL state assertion failure (expected %s, current %s)\n",
 792              state_string(state), state_string(cur_state));
 793 }
 794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 796
 797 /* For ILK+ */
 798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 799                            enum pipe pipe, bool state)
 800 {
 801         int reg;
 802         u32 val;
 803         bool cur_state;
 804
 805         reg = PCH_DPLL(pipe);
 806         val = I915_READ(reg);
 807         cur_state = !!(val & DPLL_VCO_ENABLE);
 808         WARN(cur_state != state,
 809              "PCH PLL state assertion failure (expected %s, current %s)\n",
 810              state_string(state), state_string(cur_state));
 811 }
 812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 814
 815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 816                           enum pipe pipe, bool state)
 817 {
 818         int reg;
 819         u32 val;
 820         bool cur_state;
 821
 822         reg = FDI_TX_CTL(pipe);
 823         val = I915_READ(reg);
 824         cur_state = !!(val & FDI_TX_ENABLE);
 825         WARN(cur_state != state,
 826              "FDI TX state assertion failure (expected %s, current %s)\n",
 827              state_string(state), state_string(cur_state));
 828 }
 829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 831
 832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 833                           enum pipe pipe, bool state)
 834 {
 835         int reg;
 836         u32 val;
 837         bool cur_state;
 838
 839         reg = FDI_RX_CTL(pipe);
 840         val = I915_READ(reg);
 841         cur_state = !!(val & FDI_RX_ENABLE);
 842         WARN(cur_state != state,
 843              "FDI RX state assertion failure (expected %s, current %s)\n",
 844              state_string(state), state_string(cur_state));
 845 }
 846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 848
 849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 850                                       enum pipe pipe)
 851 {
 852         int reg;
 853         u32 val;
 854
 855         /* ILK FDI PLL is always enabled */
 856         if (dev_priv->info->gen == 5)
 857                 return;
 858
 859         reg = FDI_TX_CTL(pipe);
 860         val = I915_READ(reg);
 861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 862 }
 863
 864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 865                                       enum pipe pipe)
 866 {
 867         int reg;
 868         u32 val;
 869
 870         reg = FDI_RX_CTL(pipe);
 871         val = I915_READ(reg);
 872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 873 }
 874
 875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 876                                   enum pipe pipe)
 877 {
 878         int pp_reg, lvds_reg;
 879         u32 val;
 880         enum pipe panel_pipe = PIPE_A;
 881         bool locked = locked;
 882
 883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 884                 pp_reg = PCH_PP_CONTROL;
 885                 lvds_reg = PCH_LVDS;
 886         } else {
 887                 pp_reg = PP_CONTROL;
 888                 lvds_reg = LVDS;
 889         }
 890
 891         val = I915_READ(pp_reg);
 892         if (!(val & PANEL_POWER_ON) ||
 893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 894                 locked = false;
 895
 896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 897                 panel_pipe = PIPE_B;
 898
 899         WARN(panel_pipe == pipe && locked,
 900              "panel assertion failure, pipe %c regs locked\n",
 901              pipe_name(pipe));
 902 }
 903
 904 static void assert_pipe(struct drm_i915_private *dev_priv,
 905                         enum pipe pipe, bool state)
 906 {
 907         int reg;
 908         u32 val;
 909         bool cur_state;
 910
 911         reg = PIPECONF(pipe);
 912         val = I915_READ(reg);
 913         cur_state = !!(val & PIPECONF_ENABLE);
 914         WARN(cur_state != state,
 915              "pipe %c assertion failure (expected %s, current %s)\n",
 916              pipe_name(pipe), state_string(state), state_string(cur_state));
 917 }
 918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 920
 921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 922                                  enum plane plane)
 923 {
 924         int reg;
 925         u32 val;
 926
 927         reg = DSPCNTR(plane);
 928         val = I915_READ(reg);
 929         WARN(!(val & DISPLAY_PLANE_ENABLE),
 930              "plane %c assertion failure, should be active but is disabled\n",
 931              plane_name(plane));
 932 }
 933
 934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 935                                    enum pipe pipe)
 936 {
 937         int reg, i;
 938         u32 val;
 939         int cur_pipe;
 940
 941         /* Planes are fixed to pipes on ILK+ */
 942         if (HAS_PCH_SPLIT(dev_priv->dev))
 943                 return;
 944
 945         /* Need to check both planes against the pipe */
 946         for (i = 0; i < 2; i++) {
 947                 reg = DSPCNTR(i);
 948                 val = I915_READ(reg);
 949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 950                         DISPPLANE_SEL_PIPE_SHIFT;
 951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 953                      plane_name(i), pipe_name(pipe));
 954         }
 955 }
 956
 957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 958 {
 959         u32 val;
 960         bool enabled;
 961
 962         val = I915_READ(PCH_DREF_CONTROL);
 963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 964                             DREF_SUPERSPREAD_SOURCE_MASK));
 965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 966 }
 967
 968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 969                                        enum pipe pipe)
 970 {
 971         int reg;
 972         u32 val;
 973         bool enabled;
 974
 975         reg = TRANSCONF(pipe);
 976         val = I915_READ(reg);
 977         enabled = !!(val & TRANS_ENABLE);
 978         WARN(enabled,
 979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 980              pipe_name(pipe));
 981 }
 982
 983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 984                                    enum pipe pipe, int reg)
 985 {
 986         u32 val = I915_READ(reg);
 987         WARN(DP_PIPE_ENABLED(val, pipe),
 988              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 989              reg, pipe_name(pipe));
 990 }
 991
 992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 993                                      enum pipe pipe, int reg)
 994 {
 995         u32 val = I915_READ(reg);
 996         WARN(HDMI_PIPE_ENABLED(val, pipe),
 997              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 998              reg, pipe_name(pipe));
 999 }
1000
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011         reg = PCH_ADPA;
1012         val = I915_READ(reg);
1013         WARN(ADPA_PIPE_ENABLED(val, pipe),
1014              "PCH VGA enabled on transcoder %c, should be disabled\n",
1015              pipe_name(pipe));
1016
1017         reg = PCH_LVDS;
1018         val = I915_READ(reg);
1019         WARN(LVDS_PIPE_ENABLED(val, pipe),
1020              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1021              pipe_name(pipe));
1022
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026 }
1027
1028 /**
1029  * intel_enable_pll - enable a PLL
1030  * @dev_priv: i915 private structure
1031  * @pipe: pipe PLL to enable
1032  *
1033  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1034  * make sure the PLL reg is writable first though, since the panel write
1035  * protect mechanism may be enabled.
1036  *
1037  * Note!  This is for pre-ILK only.
1038  */
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041         int reg;
1042         u32 val;
1043
1044         /* No really, not for ILK+ */
1045         BUG_ON(dev_priv->info->gen >= 5);
1046
1047         /* PLL is protected by panel, make sure we can write it */
1048         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049                 assert_panel_unlocked(dev_priv, pipe);
1050
1051         reg = DPLL(pipe);
1052         val = I915_READ(reg);
1053         val |= DPLL_VCO_ENABLE;
1054
1055         /* We do this three times for luck */
1056         I915_WRITE(reg, val);
1057         POSTING_READ(reg);
1058         udelay(150); /* wait for warmup */
1059         I915_WRITE(reg, val);
1060         POSTING_READ(reg);
1061         udelay(150); /* wait for warmup */
1062         I915_WRITE(reg, val);
1063         POSTING_READ(reg);
1064         udelay(150); /* wait for warmup */
1065 }
1066
1067 /**
1068  * intel_disable_pll - disable a PLL
1069  * @dev_priv: i915 private structure
1070  * @pipe: pipe PLL to disable
1071  *
1072  * Disable the PLL for @pipe, making sure the pipe is off first.
1073  *
1074  * Note!  This is for pre-ILK only.
1075  */
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077 {
1078         int reg;
1079         u32 val;
1080
1081         /* Don't disable pipe A or pipe A PLLs if needed */
1082         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083                 return;
1084
1085         /* Make sure the pipe isn't still relying on us */
1086         assert_pipe_disabled(dev_priv, pipe);
1087
1088         reg = DPLL(pipe);
1089         val = I915_READ(reg);
1090         val &= ~DPLL_VCO_ENABLE;
1091         I915_WRITE(reg, val);
1092         POSTING_READ(reg);
1093 }
1094
1095 /**
1096  * intel_enable_pch_pll - enable PCH PLL
1097  * @dev_priv: i915 private structure
1098  * @pipe: pipe PLL to enable
1099  *
1100  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101  * drives the transcoder clock.
1102  */
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104                                  enum pipe pipe)
1105 {
1106         int reg;
1107         u32 val;
1108
1109         /* PCH only available on ILK+ */
1110         BUG_ON(dev_priv->info->gen < 5);
1111
1112         /* PCH refclock must be enabled first */
1113         assert_pch_refclk_enabled(dev_priv);
1114
1115         reg = PCH_DPLL(pipe);
1116         val = I915_READ(reg);
1117         val |= DPLL_VCO_ENABLE;
1118         I915_WRITE(reg, val);
1119         POSTING_READ(reg);
1120         udelay(200);
1121 }
1122
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124                                   enum pipe pipe)
1125 {
1126         int reg;
1127         u32 val;
1128
1129         /* PCH only available on ILK+ */
1130         BUG_ON(dev_priv->info->gen < 5);
1131
1132         /* Make sure transcoder isn't still depending on us */
1133         assert_transcoder_disabled(dev_priv, pipe);
1134
1135         reg = PCH_DPLL(pipe);
1136         val = I915_READ(reg);
1137         val &= ~DPLL_VCO_ENABLE;
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(200);
1141 }
1142
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144                                     enum pipe pipe)
1145 {
1146         int reg;
1147         u32 val;
1148
1149         /* PCH only available on ILK+ */
1150         BUG_ON(dev_priv->info->gen < 5);
1151
1152         /* Make sure PCH DPLL is enabled */
1153         assert_pch_pll_enabled(dev_priv, pipe);
1154
1155         /* FDI must be feeding us bits for PCH ports */
1156         assert_fdi_tx_enabled(dev_priv, pipe);
1157         assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159         reg = TRANSCONF(pipe);
1160         val = I915_READ(reg);
1161
1162         if (HAS_PCH_IBX(dev_priv->dev)) {
1163                 /*
1164                  * make the BPC in transcoder be consistent with
1165                  * that in pipeconf reg.
1166                  */
1167                 val &= ~PIPE_BPC_MASK;
1168                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169         }
1170         I915_WRITE(reg, val | TRANS_ENABLE);
1171         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173 }
1174
1175 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176                                      enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         /* FDI relies on the transcoder */
1182         assert_fdi_tx_disabled(dev_priv, pipe);
1183         assert_fdi_rx_disabled(dev_priv, pipe);
1184
1185         /* Ports must be off as well */
1186         assert_pch_ports_disabled(dev_priv, pipe);
1187
1188         reg = TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         val &= ~TRANS_ENABLE;
1191         I915_WRITE(reg, val);
1192         /* wait for PCH transcoder off, transcoder state */
1193         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194                 DRM_ERROR("failed to disable transcoder\n");
1195 }
1196
1197 /**
1198  * intel_enable_pipe - enable a pipe, asserting requirements
1199  * @dev_priv: i915 private structure
1200  * @pipe: pipe to enable
1201  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1202  *
1203  * Enable @pipe, making sure that various hardware specific requirements
1204  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205  *
1206  * @pipe should be %PIPE_A or %PIPE_B.
1207  *
1208  * Will wait until the pipe is actually running (i.e. first vblank) before
1209  * returning.
1210  */
1211 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212                               bool pch_port)
1213 {
1214         int reg;
1215         u32 val;
1216
1217         /*
1218          * A pipe without a PLL won't actually be able to drive bits from
1219          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1220          * need the check.
1221          */
1222         if (!HAS_PCH_SPLIT(dev_priv->dev))
1223                 assert_pll_enabled(dev_priv, pipe);
1224         else {
1225                 if (pch_port) {
1226                         /* if driving the PCH, we need FDI enabled */
1227                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229                 }
1230                 /* FIXME: assert CPU port conditions for SNB+ */
1231         }
1232
1233         reg = PIPECONF(pipe);
1234         val = I915_READ(reg);
1235         if (val & PIPECONF_ENABLE)
1236                 return;
1237
1238         I915_WRITE(reg, val | PIPECONF_ENABLE);
1239         intel_wait_for_vblank(dev_priv->dev, pipe);
1240 }
1241
1242 /**
1243  * intel_disable_pipe - disable a pipe, asserting requirements
1244  * @dev_priv: i915 private structure
1245  * @pipe: pipe to disable
1246  *
1247  * Disable @pipe, making sure that various hardware specific requirements
1248  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249  *
1250  * @pipe should be %PIPE_A or %PIPE_B.
1251  *
1252  * Will wait until the pipe has shut down before returning.
1253  */
1254 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255                                enum pipe pipe)
1256 {
1257         int reg;
1258         u32 val;
1259
1260         /*
1261          * Make sure planes won't keep trying to pump pixels to us,
1262          * or we might hang the display.
1263          */
1264         assert_planes_disabled(dev_priv, pipe);
1265
1266         /* Don't disable pipe A or pipe A PLLs if needed */
1267         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268                 return;
1269
1270         reg = PIPECONF(pipe);
1271         val = I915_READ(reg);
1272         if ((val & PIPECONF_ENABLE) == 0)
1273                 return;
1274
1275         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1276         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277 }
1278
1279 /**
1280  * intel_enable_plane - enable a display plane on a given pipe
1281  * @dev_priv: i915 private structure
1282  * @plane: plane to enable
1283  * @pipe: pipe being fed
1284  *
1285  * Enable @plane on @pipe, making sure that @pipe is running first.
1286  */
1287 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288                                enum plane plane, enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294         assert_pipe_enabled(dev_priv, pipe);
1295
1296         reg = DSPCNTR(plane);
1297         val = I915_READ(reg);
1298         if (val & DISPLAY_PLANE_ENABLE)
1299                 return;
1300
1301         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302         intel_wait_for_vblank(dev_priv->dev, pipe);
1303 }
1304
1305 /*
1306  * Plane regs are double buffered, going from enabled->disabled needs a
1307  * trigger in order to latch.  The display address reg provides this.
1308  */
1309 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310                                       enum plane plane)
1311 {
1312         u32 reg = DSPADDR(plane);
1313         I915_WRITE(reg, I915_READ(reg));
1314 }
1315
1316 /**
1317  * intel_disable_plane - disable a display plane
1318  * @dev_priv: i915 private structure
1319  * @plane: plane to disable
1320  * @pipe: pipe consuming the data
1321  *
1322  * Disable @plane; should be an independent operation.
1323  */
1324 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325                                 enum plane plane, enum pipe pipe)
1326 {
1327         int reg;
1328         u32 val;
1329
1330         reg = DSPCNTR(plane);
1331         val = I915_READ(reg);
1332         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333                 return;
1334
1335         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1336         intel_flush_display_plane(dev_priv, plane);
1337         intel_wait_for_vblank(dev_priv->dev, pipe);
1338 }
1339
1340 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341                            enum pipe pipe, int reg)
1342 {
1343         u32 val = I915_READ(reg);
1344         if (DP_PIPE_ENABLED(val, pipe))
1345                 I915_WRITE(reg, val & ~DP_PORT_EN);
1346 }
1347
1348 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349                              enum pipe pipe, int reg)
1350 {
1351         u32 val = I915_READ(reg);
1352         if (HDMI_PIPE_ENABLED(val, pipe))
1353                 I915_WRITE(reg, val & ~PORT_ENABLE);
1354 }
1355
1356 /* Disable any ports connected to this transcoder */
1357 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358                                     enum pipe pipe)
1359 {
1360         u32 reg, val;
1361
1362         val = I915_READ(PCH_PP_CONTROL);
1363         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369         reg = PCH_ADPA;
1370         val = I915_READ(reg);
1371         if (ADPA_PIPE_ENABLED(val, pipe))
1372                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         if (LVDS_PIPE_ENABLED(val, pipe)) {
1377                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378                 POSTING_READ(reg);
1379                 udelay(100);
1380         }
1381
1382         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384         disable_pch_hdmi(dev_priv, pipe, HDMID);
1385 }
1386
1387 static void i8xx_disable_fbc(struct drm_device *dev)
1388 {
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390         u32 fbc_ctl;
1391
1392         /* Disable compression */
1393         fbc_ctl = I915_READ(FBC_CONTROL);
1394         if ((fbc_ctl & FBC_CTL_EN) == 0)
1395                 return;
1396
1397         fbc_ctl &= ~FBC_CTL_EN;
1398         I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400         /* Wait for compressing bit to clear */
1401         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402                 DRM_DEBUG_KMS("FBC idle timed out\n");
1403                 return;
1404         }
1405
1406         DRM_DEBUG_KMS("disabled FBC\n");
1407 }
1408
1409 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_framebuffer *fb = crtc->fb;
1414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1415         struct drm_i915_gem_object *obj = intel_fb->obj;
1416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417         int cfb_pitch;
1418         int plane, i;
1419         u32 fbc_ctl, fbc_ctl2;
1420
1421         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1422         if (fb->pitch < cfb_pitch)
1423                 cfb_pitch = fb->pitch;
1424
1425         /* FBC_CTL wants 64B units */
1426         cfb_pitch = (cfb_pitch / 64) - 1;
1427         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1428
1429         /* Clear old tags */
1430         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1431                 I915_WRITE(FBC_TAG + (i * 4), 0);
1432
1433         /* Set it up... */
1434         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1435         fbc_ctl2 |= plane;
1436         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1437         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1438
1439         /* enable it... */
1440         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1441         if (IS_I945GM(dev))
1442                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1443         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1444         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1445         fbc_ctl |= obj->fence_reg;
1446         I915_WRITE(FBC_CONTROL, fbc_ctl);
1447
1448         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1449                       cfb_pitch, crtc->y, intel_crtc->plane);
1450 }
1451
1452 static bool i8xx_fbc_enabled(struct drm_device *dev)
1453 {
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455
1456         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1457 }
1458
1459 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1460 {
1461         struct drm_device *dev = crtc->dev;
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463         struct drm_framebuffer *fb = crtc->fb;
1464         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1465         struct drm_i915_gem_object *obj = intel_fb->obj;
1466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1467         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1468         unsigned long stall_watermark = 200;
1469         u32 dpfc_ctl;
1470
1471         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1472         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1473         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1474
1475         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1476                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1477                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1478         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1479
1480         /* enable it... */
1481         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1482
1483         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1484 }
1485
1486 static void g4x_disable_fbc(struct drm_device *dev)
1487 {
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         u32 dpfc_ctl;
1490
1491         /* Disable compression */
1492         dpfc_ctl = I915_READ(DPFC_CONTROL);
1493         if (dpfc_ctl & DPFC_CTL_EN) {
1494                 dpfc_ctl &= ~DPFC_CTL_EN;
1495                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1496
1497                 DRM_DEBUG_KMS("disabled FBC\n");
1498         }
1499 }
1500
1501 static bool g4x_fbc_enabled(struct drm_device *dev)
1502 {
1503         struct drm_i915_private *dev_priv = dev->dev_private;
1504
1505         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1506 }
1507
1508 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1509 {
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         u32 blt_ecoskpd;
1512
1513         /* Make sure blitter notifies FBC of writes */
1514         gen6_gt_force_wake_get(dev_priv);
1515         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1516         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1517                 GEN6_BLITTER_LOCK_SHIFT;
1518         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1519         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1520         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1521         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1522                          GEN6_BLITTER_LOCK_SHIFT);
1523         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1524         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1525         gen6_gt_force_wake_put(dev_priv);
1526 }
1527
1528 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1529 {
1530         struct drm_device *dev = crtc->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct drm_framebuffer *fb = crtc->fb;
1533         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1534         struct drm_i915_gem_object *obj = intel_fb->obj;
1535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1536         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1537         unsigned long stall_watermark = 200;
1538         u32 dpfc_ctl;
1539
1540         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1541         dpfc_ctl &= DPFC_RESERVED;
1542         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1543         /* Set persistent mode for front-buffer rendering, ala X. */
1544         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1545         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1546         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1547
1548         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1549                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1550                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1551         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1552         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1553         /* enable it... */
1554         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1555
1556         if (IS_GEN6(dev)) {
1557                 I915_WRITE(SNB_DPFC_CTL_SA,
1558                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1559                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1560                 sandybridge_blit_fbc_update(dev);
1561         }
1562
1563         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1564 }
1565
1566 static void ironlake_disable_fbc(struct drm_device *dev)
1567 {
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         u32 dpfc_ctl;
1570
1571         /* Disable compression */
1572         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1573         if (dpfc_ctl & DPFC_CTL_EN) {
1574                 dpfc_ctl &= ~DPFC_CTL_EN;
1575                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1576
1577                 DRM_DEBUG_KMS("disabled FBC\n");
1578         }
1579 }
1580
1581 static bool ironlake_fbc_enabled(struct drm_device *dev)
1582 {
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1586 }
1587
1588 bool intel_fbc_enabled(struct drm_device *dev)
1589 {
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592         if (!dev_priv->display.fbc_enabled)
1593                 return false;
1594
1595         return dev_priv->display.fbc_enabled(dev);
1596 }
1597
1598 static void intel_fbc_work_fn(struct work_struct *__work)
1599 {
1600         struct intel_fbc_work *work =
1601                 container_of(to_delayed_work(__work),
1602                              struct intel_fbc_work, work);
1603         struct drm_device *dev = work->crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605
1606         mutex_lock(&dev->struct_mutex);
1607         if (work == dev_priv->fbc_work) {
1608                 /* Double check that we haven't switched fb without cancelling
1609                  * the prior work.
1610                  */
1611                 if (work->crtc->fb == work->fb) {
1612                         dev_priv->display.enable_fbc(work->crtc,
1613                                                      work->interval);
1614
1615                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1616                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1617                         dev_priv->cfb_y = work->crtc->y;
1618                 }
1619
1620                 dev_priv->fbc_work = NULL;
1621         }
1622         mutex_unlock(&dev->struct_mutex);
1623
1624         kfree(work);
1625 }
1626
1627 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1628 {
1629         if (dev_priv->fbc_work == NULL)
1630                 return;
1631
1632         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1633
1634         /* Synchronisation is provided by struct_mutex and checking of
1635          * dev_priv->fbc_work, so we can perform the cancellation
1636          * entirely asynchronously.
1637          */
1638         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1639                 /* tasklet was killed before being run, clean up */
1640                 kfree(dev_priv->fbc_work);
1641
1642         /* Mark the work as no longer wanted so that if it does
1643          * wake-up (because the work was already running and waiting
1644          * for our mutex), it will discover that is no longer
1645          * necessary to run.
1646          */
1647         dev_priv->fbc_work = NULL;
1648 }
1649
1650 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1651 {
1652         struct intel_fbc_work *work;
1653         struct drm_device *dev = crtc->dev;
1654         struct drm_i915_private *dev_priv = dev->dev_private;
1655
1656         if (!dev_priv->display.enable_fbc)
1657                 return;
1658
1659         intel_cancel_fbc_work(dev_priv);
1660
1661         work = kzalloc(sizeof *work, GFP_KERNEL);
1662         if (work == NULL) {
1663                 dev_priv->display.enable_fbc(crtc, interval);
1664                 return;
1665         }
1666
1667         work->crtc = crtc;
1668         work->fb = crtc->fb;
1669         work->interval = interval;
1670         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1671
1672         dev_priv->fbc_work = work;
1673
1674         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1675
1676         /* Delay the actual enabling to let pageflipping cease and the
1677          * display to settle before starting the compression. Note that
1678          * this delay also serves a second purpose: it allows for a
1679          * vblank to pass after disabling the FBC before we attempt
1680          * to modify the control registers.
1681          *
1682          * A more complicated solution would involve tracking vblanks
1683          * following the termination of the page-flipping sequence
1684          * and indeed performing the enable as a co-routine and not
1685          * waiting synchronously upon the vblank.
1686          */
1687         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1688 }
1689
1690 void intel_disable_fbc(struct drm_device *dev)
1691 {
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693
1694         intel_cancel_fbc_work(dev_priv);
1695
1696         if (!dev_priv->display.disable_fbc)
1697                 return;
1698
1699         dev_priv->display.disable_fbc(dev);
1700         dev_priv->cfb_plane = -1;
1701 }
1702
1703 /**
1704  * intel_update_fbc - enable/disable FBC as needed
1705  * @dev: the drm_device
1706  *
1707  * Set up the framebuffer compression hardware at mode set time.  We
1708  * enable it if possible:
1709  *   - plane A only (on pre-965)
1710  *   - no pixel mulitply/line duplication
1711  *   - no alpha buffer discard
1712  *   - no dual wide
1713  *   - framebuffer <= 2048 in width, 1536 in height
1714  *
1715  * We can't assume that any compression will take place (worst case),
1716  * so the compressed buffer has to be the same size as the uncompressed
1717  * one.  It also must reside (along with the line length buffer) in
1718  * stolen memory.
1719  *
1720  * We need to enable/disable FBC on a global basis.
1721  */
1722 static void intel_update_fbc(struct drm_device *dev)
1723 {
1724         struct drm_i915_private *dev_priv = dev->dev_private;
1725         struct drm_crtc *crtc = NULL, *tmp_crtc;
1726         struct intel_crtc *intel_crtc;
1727         struct drm_framebuffer *fb;
1728         struct intel_framebuffer *intel_fb;
1729         struct drm_i915_gem_object *obj;
1730
1731         DRM_DEBUG_KMS("\n");
1732
1733         if (!i915_powersave)
1734                 return;
1735
1736         if (!I915_HAS_FBC(dev))
1737                 return;
1738
1739         /*
1740          * If FBC is already on, we just have to verify that we can
1741          * keep it that way...
1742          * Need to disable if:
1743          *   - more than one pipe is active
1744          *   - changing FBC params (stride, fence, mode)
1745          *   - new fb is too large to fit in compressed buffer
1746          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1747          */
1748         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1749                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1750                         if (crtc) {
1751                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1752                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1753                                 goto out_disable;
1754                         }
1755                         crtc = tmp_crtc;
1756                 }
1757         }
1758
1759         if (!crtc || crtc->fb == NULL) {
1760                 DRM_DEBUG_KMS("no output, disabling\n");
1761                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1762                 goto out_disable;
1763         }
1764
1765         intel_crtc = to_intel_crtc(crtc);
1766         fb = crtc->fb;
1767         intel_fb = to_intel_framebuffer(fb);
1768         obj = intel_fb->obj;
1769
1770         if (!i915_enable_fbc) {
1771                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1772                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1773                 goto out_disable;
1774         }
1775         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1776                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1777                               "compression\n");
1778                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1779                 goto out_disable;
1780         }
1781         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1782             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1783                 DRM_DEBUG_KMS("mode incompatible with compression, "
1784                               "disabling\n");
1785                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1786                 goto out_disable;
1787         }
1788         if ((crtc->mode.hdisplay > 2048) ||
1789             (crtc->mode.vdisplay > 1536)) {
1790                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1791                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1792                 goto out_disable;
1793         }
1794         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1795                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1796                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1797                 goto out_disable;
1798         }
1799
1800         /* The use of a CPU fence is mandatory in order to detect writes
1801          * by the CPU to the scanout and trigger updates to the FBC.
1802          */
1803         if (obj->tiling_mode != I915_TILING_X ||
1804             obj->fence_reg == I915_FENCE_REG_NONE) {
1805                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1806                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1807                 goto out_disable;
1808         }
1809
1810         /* If the kernel debugger is active, always disable compression */
1811         if (in_dbg_master())
1812                 goto out_disable;
1813
1814         /* If the scanout has not changed, don't modify the FBC settings.
1815          * Note that we make the fundamental assumption that the fb->obj
1816          * cannot be unpinned (and have its GTT offset and fence revoked)
1817          * without first being decoupled from the scanout and FBC disabled.
1818          */
1819         if (dev_priv->cfb_plane == intel_crtc->plane &&
1820             dev_priv->cfb_fb == fb->base.id &&
1821             dev_priv->cfb_y == crtc->y)
1822                 return;
1823
1824         if (intel_fbc_enabled(dev)) {
1825                 /* We update FBC along two paths, after changing fb/crtc
1826                  * configuration (modeswitching) and after page-flipping
1827                  * finishes. For the latter, we know that not only did
1828                  * we disable the FBC at the start of the page-flip
1829                  * sequence, but also more than one vblank has passed.
1830                  *
1831                  * For the former case of modeswitching, it is possible
1832                  * to switch between two FBC valid configurations
1833                  * instantaneously so we do need to disable the FBC
1834                  * before we can modify its control registers. We also
1835                  * have to wait for the next vblank for that to take
1836                  * effect. However, since we delay enabling FBC we can
1837                  * assume that a vblank has passed since disabling and
1838                  * that we can safely alter the registers in the deferred
1839                  * callback.
1840                  *
1841                  * In the scenario that we go from a valid to invalid
1842                  * and then back to valid FBC configuration we have
1843                  * no strict enforcement that a vblank occurred since
1844                  * disabling the FBC. However, along all current pipe
1845                  * disabling paths we do need to wait for a vblank at
1846                  * some point. And we wait before enabling FBC anyway.
1847                  */
1848                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1849                 intel_disable_fbc(dev);
1850         }
1851
1852         intel_enable_fbc(crtc, 500);
1853         return;
1854
1855 out_disable:
1856         /* Multiple disables should be harmless */
1857         if (intel_fbc_enabled(dev)) {
1858                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1859                 intel_disable_fbc(dev);
1860         }
1861 }
1862
1863 int
1864 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1865                            struct drm_i915_gem_object *obj,
1866                            struct intel_ring_buffer *pipelined)
1867 {
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         u32 alignment;
1870         int ret;
1871
1872         switch (obj->tiling_mode) {
1873         case I915_TILING_NONE:
1874                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1875                         alignment = 128 * 1024;
1876                 else if (INTEL_INFO(dev)->gen >= 4)
1877                         alignment = 4 * 1024;
1878                 else
1879                         alignment = 64 * 1024;
1880                 break;
1881         case I915_TILING_X:
1882                 /* pin() will align the object as required by fence */
1883                 alignment = 0;
1884                 break;
1885         case I915_TILING_Y:
1886                 /* FIXME: Is this true? */
1887                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1888                 return -EINVAL;
1889         default:
1890                 BUG();
1891         }
1892
1893         dev_priv->mm.interruptible = false;
1894         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1895         if (ret)
1896                 goto err_interruptible;
1897
1898         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899          * fence, whereas 965+ only requires a fence if using
1900          * framebuffer compression.  For simplicity, we always install
1901          * a fence as the cost is not that onerous.
1902          */
1903         if (obj->tiling_mode != I915_TILING_NONE) {
1904                 ret = i915_gem_object_get_fence(obj, pipelined);
1905                 if (ret)
1906                         goto err_unpin;
1907         }
1908
1909         dev_priv->mm.interruptible = true;
1910         return 0;
1911
1912 err_unpin:
1913         i915_gem_object_unpin(obj);
1914 err_interruptible:
1915         dev_priv->mm.interruptible = true;
1916         return ret;
1917 }
1918
1919 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1920                              int x, int y)
1921 {
1922         struct drm_device *dev = crtc->dev;
1923         struct drm_i915_private *dev_priv = dev->dev_private;
1924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1925         struct intel_framebuffer *intel_fb;
1926         struct drm_i915_gem_object *obj;
1927         int plane = intel_crtc->plane;
1928         unsigned long Start, Offset;
1929         u32 dspcntr;
1930         u32 reg;
1931
1932         switch (plane) {
1933         case 0:
1934         case 1:
1935                 break;
1936         default:
1937                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1938                 return -EINVAL;
1939         }
1940
1941         intel_fb = to_intel_framebuffer(fb);
1942         obj = intel_fb->obj;
1943
1944         reg = DSPCNTR(plane);
1945         dspcntr = I915_READ(reg);
1946         /* Mask out pixel format bits in case we change it */
1947         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1948         switch (fb->bits_per_pixel) {
1949         case 8:
1950                 dspcntr |= DISPPLANE_8BPP;
1951                 break;
1952         case 16:
1953                 if (fb->depth == 15)
1954                         dspcntr |= DISPPLANE_15_16BPP;
1955                 else
1956                         dspcntr |= DISPPLANE_16BPP;
1957                 break;
1958         case 24:
1959         case 32:
1960                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1961                 break;
1962         default:
1963                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1964                 return -EINVAL;
1965         }
1966         if (INTEL_INFO(dev)->gen >= 4) {
1967                 if (obj->tiling_mode != I915_TILING_NONE)
1968                         dspcntr |= DISPPLANE_TILED;
1969                 else
1970                         dspcntr &= ~DISPPLANE_TILED;
1971         }
1972
1973         I915_WRITE(reg, dspcntr);
1974
1975         Start = obj->gtt_offset;
1976         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1977
1978         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1979                       Start, Offset, x, y, fb->pitch);
1980         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1981         if (INTEL_INFO(dev)->gen >= 4) {
1982                 I915_WRITE(DSPSURF(plane), Start);
1983                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1984                 I915_WRITE(DSPADDR(plane), Offset);
1985         } else
1986                 I915_WRITE(DSPADDR(plane), Start + Offset);
1987         POSTING_READ(reg);
1988
1989         return 0;
1990 }
1991
1992 static int ironlake_update_plane(struct drm_crtc *crtc,
1993                                  struct drm_framebuffer *fb, int x, int y)
1994 {
1995         struct drm_device *dev = crtc->dev;
1996         struct drm_i915_private *dev_priv = dev->dev_private;
1997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998         struct intel_framebuffer *intel_fb;
1999         struct drm_i915_gem_object *obj;
2000         int plane = intel_crtc->plane;
2001         unsigned long Start, Offset;
2002         u32 dspcntr;
2003         u32 reg;
2004
2005         switch (plane) {
2006         case 0:
2007         case 1:
2008                 break;
2009         default:
2010                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011                 return -EINVAL;
2012         }
2013
2014         intel_fb = to_intel_framebuffer(fb);
2015         obj = intel_fb->obj;
2016
2017         reg = DSPCNTR(plane);
2018         dspcntr = I915_READ(reg);
2019         /* Mask out pixel format bits in case we change it */
2020         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021         switch (fb->bits_per_pixel) {
2022         case 8:
2023                 dspcntr |= DISPPLANE_8BPP;
2024                 break;
2025         case 16:
2026                 if (fb->depth != 16)
2027                         return -EINVAL;
2028
2029                 dspcntr |= DISPPLANE_16BPP;
2030                 break;
2031         case 24:
2032         case 32:
2033                 if (fb->depth == 24)
2034                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2035                 else if (fb->depth == 30)
2036                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2037                 else
2038                         return -EINVAL;
2039                 break;
2040         default:
2041                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2042                 return -EINVAL;
2043         }
2044
2045         if (obj->tiling_mode != I915_TILING_NONE)
2046                 dspcntr |= DISPPLANE_TILED;
2047         else
2048                 dspcntr &= ~DISPPLANE_TILED;
2049
2050         /* must disable */
2051         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2052
2053         I915_WRITE(reg, dspcntr);
2054
2055         Start = obj->gtt_offset;
2056         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2057
2058         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059                       Start, Offset, x, y, fb->pitch);
2060         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2061         I915_WRITE(DSPSURF(plane), Start);
2062         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063         I915_WRITE(DSPADDR(plane), Offset);
2064         POSTING_READ(reg);
2065
2066         return 0;
2067 }
2068
2069 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2070 static int
2071 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2072                            int x, int y, enum mode_set_atomic state)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         int ret;
2077
2078         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2079         if (ret)
2080                 return ret;
2081
2082         intel_update_fbc(dev);
2083         intel_increase_pllclock(crtc);
2084
2085         return 0;
2086 }
2087
2088 static int
2089 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2090                     struct drm_framebuffer *old_fb)
2091 {
2092         struct drm_device *dev = crtc->dev;
2093         struct drm_i915_master_private *master_priv;
2094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095         int ret;
2096
2097         /* no fb bound */
2098         if (!crtc->fb) {
2099                 DRM_ERROR("No FB bound\n");
2100                 return 0;
2101         }
2102
2103         switch (intel_crtc->plane) {
2104         case 0:
2105         case 1:
2106                 break;
2107         default:
2108                 DRM_ERROR("no plane for crtc\n");
2109                 return -EINVAL;
2110         }
2111
2112         mutex_lock(&dev->struct_mutex);
2113         ret = intel_pin_and_fence_fb_obj(dev,
2114                                          to_intel_framebuffer(crtc->fb)->obj,
2115                                          NULL);
2116         if (ret != 0) {
2117                 mutex_unlock(&dev->struct_mutex);
2118                 DRM_ERROR("pin & fence failed\n");
2119                 return ret;
2120         }
2121
2122         if (old_fb) {
2123                 struct drm_i915_private *dev_priv = dev->dev_private;
2124                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125
2126                 wait_event(dev_priv->pending_flip_queue,
2127                            atomic_read(&dev_priv->mm.wedged) ||
2128                            atomic_read(&obj->pending_flip) == 0);
2129
2130                 /* Big Hammer, we also need to ensure that any pending
2131                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2132                  * current scanout is retired before unpinning the old
2133                  * framebuffer.
2134                  *
2135                  * This should only fail upon a hung GPU, in which case we
2136                  * can safely continue.
2137                  */
2138                 ret = i915_gem_object_finish_gpu(obj);
2139                 (void) ret;
2140         }
2141
2142         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2143                                          LEAVE_ATOMIC_MODE_SET);
2144         if (ret) {
2145                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2146                 mutex_unlock(&dev->struct_mutex);
2147                 DRM_ERROR("failed to update base address\n");
2148                 return ret;
2149         }
2150
2151         if (old_fb) {
2152                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2153                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2154         }
2155
2156         mutex_unlock(&dev->struct_mutex);
2157
2158         if (!dev->primary->master)
2159                 return 0;
2160
2161         master_priv = dev->primary->master->driver_priv;
2162         if (!master_priv->sarea_priv)
2163                 return 0;
2164
2165         if (intel_crtc->pipe) {
2166                 master_priv->sarea_priv->pipeB_x = x;
2167                 master_priv->sarea_priv->pipeB_y = y;
2168         } else {
2169                 master_priv->sarea_priv->pipeA_x = x;
2170                 master_priv->sarea_priv->pipeA_y = y;
2171         }
2172
2173         return 0;
2174 }
2175
2176 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2177 {
2178         struct drm_device *dev = crtc->dev;
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         u32 dpa_ctl;
2181
2182         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2183         dpa_ctl = I915_READ(DP_A);
2184         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2185
2186         if (clock < 200000) {
2187                 u32 temp;
2188                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2189                 /* workaround for 160Mhz:
2190                    1) program 0x4600c bits 15:0 = 0x8124
2191                    2) program 0x46010 bit 0 = 1
2192                    3) program 0x46034 bit 24 = 1
2193                    4) program 0x64000 bit 14 = 1
2194                    */
2195                 temp = I915_READ(0x4600c);
2196                 temp &= 0xffff0000;
2197                 I915_WRITE(0x4600c, temp | 0x8124);
2198
2199                 temp = I915_READ(0x46010);
2200                 I915_WRITE(0x46010, temp | 1);
2201
2202                 temp = I915_READ(0x46034);
2203                 I915_WRITE(0x46034, temp | (1 << 24));
2204         } else {
2205                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2206         }
2207         I915_WRITE(DP_A, dpa_ctl);
2208
2209         POSTING_READ(DP_A);
2210         udelay(500);
2211 }
2212
2213 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214 {
2215         struct drm_device *dev = crtc->dev;
2216         struct drm_i915_private *dev_priv = dev->dev_private;
2217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218         int pipe = intel_crtc->pipe;
2219         u32 reg, temp;
2220
2221         /* enable normal train */
2222         reg = FDI_TX_CTL(pipe);
2223         temp = I915_READ(reg);
2224         if (IS_IVYBRIDGE(dev)) {
2225                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2227         } else {
2228                 temp &= ~FDI_LINK_TRAIN_NONE;
2229                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2230         }
2231         I915_WRITE(reg, temp);
2232
2233         reg = FDI_RX_CTL(pipe);
2234         temp = I915_READ(reg);
2235         if (HAS_PCH_CPT(dev)) {
2236                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238         } else {
2239                 temp &= ~FDI_LINK_TRAIN_NONE;
2240                 temp |= FDI_LINK_TRAIN_NONE;
2241         }
2242         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244         /* wait one idle pattern time */
2245         POSTING_READ(reg);
2246         udelay(1000);
2247
2248         /* IVB wants error correction enabled */
2249         if (IS_IVYBRIDGE(dev))
2250                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251                            FDI_FE_ERRC_ENABLE);
2252 }
2253
2254 /* The FDI link training functions for ILK/Ibexpeak. */
2255 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2256 {
2257         struct drm_device *dev = crtc->dev;
2258         struct drm_i915_private *dev_priv = dev->dev_private;
2259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260         int pipe = intel_crtc->pipe;
2261         int plane = intel_crtc->plane;
2262         u32 reg, temp, tries;
2263
2264         /* FDI needs bits from pipe & plane first */
2265         assert_pipe_enabled(dev_priv, pipe);
2266         assert_plane_enabled(dev_priv, plane);
2267
2268         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2269            for train result */
2270         reg = FDI_RX_IMR(pipe);
2271         temp = I915_READ(reg);
2272         temp &= ~FDI_RX_SYMBOL_LOCK;
2273         temp &= ~FDI_RX_BIT_LOCK;
2274         I915_WRITE(reg, temp);
2275         I915_READ(reg);
2276         udelay(150);
2277
2278         /* enable CPU FDI TX and PCH FDI RX */
2279         reg = FDI_TX_CTL(pipe);
2280         temp = I915_READ(reg);
2281         temp &= ~(7 << 19);
2282         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2283         temp &= ~FDI_LINK_TRAIN_NONE;
2284         temp |= FDI_LINK_TRAIN_PATTERN_1;
2285         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2286
2287         reg = FDI_RX_CTL(pipe);
2288         temp = I915_READ(reg);
2289         temp &= ~FDI_LINK_TRAIN_NONE;
2290         temp |= FDI_LINK_TRAIN_PATTERN_1;
2291         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2292
2293         POSTING_READ(reg);
2294         udelay(150);
2295
2296         /* Ironlake workaround, enable clock pointer after FDI enable*/
2297         if (HAS_PCH_IBX(dev)) {
2298                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2299                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2300                            FDI_RX_PHASE_SYNC_POINTER_EN);
2301         }
2302
2303         reg = FDI_RX_IIR(pipe);
2304         for (tries = 0; tries < 5; tries++) {
2305                 temp = I915_READ(reg);
2306                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2307
2308                 if ((temp & FDI_RX_BIT_LOCK)) {
2309                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2310                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2311                         break;
2312                 }
2313         }
2314         if (tries == 5)
2315                 DRM_ERROR("FDI train 1 fail!\n");
2316
2317         /* Train 2 */
2318         reg = FDI_TX_CTL(pipe);
2319         temp = I915_READ(reg);
2320         temp &= ~FDI_LINK_TRAIN_NONE;
2321         temp |= FDI_LINK_TRAIN_PATTERN_2;
2322         I915_WRITE(reg, temp);
2323
2324         reg = FDI_RX_CTL(pipe);
2325         temp = I915_READ(reg);
2326         temp &= ~FDI_LINK_TRAIN_NONE;
2327         temp |= FDI_LINK_TRAIN_PATTERN_2;
2328         I915_WRITE(reg, temp);
2329
2330         POSTING_READ(reg);
2331         udelay(150);
2332
2333         reg = FDI_RX_IIR(pipe);
2334         for (tries = 0; tries < 5; tries++) {
2335                 temp = I915_READ(reg);
2336                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2337
2338                 if (temp & FDI_RX_SYMBOL_LOCK) {
2339                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2340                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2341                         break;
2342                 }
2343         }
2344         if (tries == 5)
2345                 DRM_ERROR("FDI train 2 fail!\n");
2346
2347         DRM_DEBUG_KMS("FDI train done\n");
2348
2349 }
2350
2351 static const int snb_b_fdi_train_param [] = {
2352         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2353         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2354         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2355         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2356 };
2357
2358 /* The FDI link training functions for SNB/Cougarpoint. */
2359 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2360 {
2361         struct drm_device *dev = crtc->dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364         int pipe = intel_crtc->pipe;
2365         u32 reg, temp, i;
2366
2367         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2368            for train result */
2369         reg = FDI_RX_IMR(pipe);
2370         temp = I915_READ(reg);
2371         temp &= ~FDI_RX_SYMBOL_LOCK;
2372         temp &= ~FDI_RX_BIT_LOCK;
2373         I915_WRITE(reg, temp);
2374
2375         POSTING_READ(reg);
2376         udelay(150);
2377
2378         /* enable CPU FDI TX and PCH FDI RX */
2379         reg = FDI_TX_CTL(pipe);
2380         temp = I915_READ(reg);
2381         temp &= ~(7 << 19);
2382         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2383         temp &= ~FDI_LINK_TRAIN_NONE;
2384         temp |= FDI_LINK_TRAIN_PATTERN_1;
2385         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2386         /* SNB-B */
2387         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2388         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2389
2390         reg = FDI_RX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         if (HAS_PCH_CPT(dev)) {
2393                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2394                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2395         } else {
2396                 temp &= ~FDI_LINK_TRAIN_NONE;
2397                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2398         }
2399         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401         POSTING_READ(reg);
2402         udelay(150);
2403
2404         for (i = 0; i < 4; i++ ) {
2405                 reg = FDI_TX_CTL(pipe);
2406                 temp = I915_READ(reg);
2407                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2408                 temp |= snb_b_fdi_train_param[i];
2409                 I915_WRITE(reg, temp);
2410
2411                 POSTING_READ(reg);
2412                 udelay(500);
2413
2414                 reg = FDI_RX_IIR(pipe);
2415                 temp = I915_READ(reg);
2416                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2417
2418                 if (temp & FDI_RX_BIT_LOCK) {
2419                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2420                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2421                         break;
2422                 }
2423         }
2424         if (i == 4)
2425                 DRM_ERROR("FDI train 1 fail!\n");
2426
2427         /* Train 2 */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_LINK_TRAIN_NONE;
2431         temp |= FDI_LINK_TRAIN_PATTERN_2;
2432         if (IS_GEN6(dev)) {
2433                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2434                 /* SNB-B */
2435                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2436         }
2437         I915_WRITE(reg, temp);
2438
2439         reg = FDI_RX_CTL(pipe);
2440         temp = I915_READ(reg);
2441         if (HAS_PCH_CPT(dev)) {
2442                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2444         } else {
2445                 temp &= ~FDI_LINK_TRAIN_NONE;
2446                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2447         }
2448         I915_WRITE(reg, temp);
2449
2450         POSTING_READ(reg);
2451         udelay(150);
2452
2453         for (i = 0; i < 4; i++ ) {
2454                 reg = FDI_TX_CTL(pipe);
2455                 temp = I915_READ(reg);
2456                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2457                 temp |= snb_b_fdi_train_param[i];
2458                 I915_WRITE(reg, temp);
2459
2460                 POSTING_READ(reg);
2461                 udelay(500);
2462
2463                 reg = FDI_RX_IIR(pipe);
2464                 temp = I915_READ(reg);
2465                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2466
2467                 if (temp & FDI_RX_SYMBOL_LOCK) {
2468                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2469                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2470                         break;
2471                 }
2472         }
2473         if (i == 4)
2474                 DRM_ERROR("FDI train 2 fail!\n");
2475
2476         DRM_DEBUG_KMS("FDI train done.\n");
2477 }
2478
2479 /* Manual link training for Ivy Bridge A0 parts */
2480 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2481 {
2482         struct drm_device *dev = crtc->dev;
2483         struct drm_i915_private *dev_priv = dev->dev_private;
2484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2485         int pipe = intel_crtc->pipe;
2486         u32 reg, temp, i;
2487
2488         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2489            for train result */
2490         reg = FDI_RX_IMR(pipe);
2491         temp = I915_READ(reg);
2492         temp &= ~FDI_RX_SYMBOL_LOCK;
2493         temp &= ~FDI_RX_BIT_LOCK;
2494         I915_WRITE(reg, temp);
2495
2496         POSTING_READ(reg);
2497         udelay(150);
2498
2499         /* enable CPU FDI TX and PCH FDI RX */
2500         reg = FDI_TX_CTL(pipe);
2501         temp = I915_READ(reg);
2502         temp &= ~(7 << 19);
2503         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2504         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2505         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2506         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2507         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2508         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2509
2510         reg = FDI_RX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_LINK_TRAIN_AUTO;
2513         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2514         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2515         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2516
2517         POSTING_READ(reg);
2518         udelay(150);
2519
2520         for (i = 0; i < 4; i++ ) {
2521                 reg = FDI_TX_CTL(pipe);
2522                 temp = I915_READ(reg);
2523                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2524                 temp |= snb_b_fdi_train_param[i];
2525                 I915_WRITE(reg, temp);
2526
2527                 POSTING_READ(reg);
2528                 udelay(500);
2529
2530                 reg = FDI_RX_IIR(pipe);
2531                 temp = I915_READ(reg);
2532                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533
2534                 if (temp & FDI_RX_BIT_LOCK ||
2535                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2536                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2537                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2538                         break;
2539                 }
2540         }
2541         if (i == 4)
2542                 DRM_ERROR("FDI train 1 fail!\n");
2543
2544         /* Train 2 */
2545         reg = FDI_TX_CTL(pipe);
2546         temp = I915_READ(reg);
2547         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2548         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2549         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551         I915_WRITE(reg, temp);
2552
2553         reg = FDI_RX_CTL(pipe);
2554         temp = I915_READ(reg);
2555         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2557         I915_WRITE(reg, temp);
2558
2559         POSTING_READ(reg);
2560         udelay(150);
2561
2562         for (i = 0; i < 4; i++ ) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 reg = FDI_RX_IIR(pipe);
2573                 temp = I915_READ(reg);
2574                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576                 if (temp & FDI_RX_SYMBOL_LOCK) {
2577                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2578                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2579                         break;
2580                 }
2581         }
2582         if (i == 4)
2583                 DRM_ERROR("FDI train 2 fail!\n");
2584
2585         DRM_DEBUG_KMS("FDI train done.\n");
2586 }
2587
2588 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2589 {
2590         struct drm_device *dev = crtc->dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2593         int pipe = intel_crtc->pipe;
2594         u32 reg, temp;
2595
2596         /* Write the TU size bits so error detection works */
2597         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2598                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2599
2600         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~((0x7 << 19) | (0x7 << 16));
2604         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2605         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2606         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2607
2608         POSTING_READ(reg);
2609         udelay(200);
2610
2611         /* Switch from Rawclk to PCDclk */
2612         temp = I915_READ(reg);
2613         I915_WRITE(reg, temp | FDI_PCDCLK);
2614
2615         POSTING_READ(reg);
2616         udelay(200);
2617
2618         /* Enable CPU FDI TX PLL, always on for Ironlake */
2619         reg = FDI_TX_CTL(pipe);
2620         temp = I915_READ(reg);
2621         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2622                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2623
2624                 POSTING_READ(reg);
2625                 udelay(100);
2626         }
2627 }
2628
2629 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2630 {
2631         struct drm_device *dev = crtc->dev;
2632         struct drm_i915_private *dev_priv = dev->dev_private;
2633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2634         int pipe = intel_crtc->pipe;
2635         u32 reg, temp;
2636
2637         /* disable CPU FDI tx and PCH FDI rx */
2638         reg = FDI_TX_CTL(pipe);
2639         temp = I915_READ(reg);
2640         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2641         POSTING_READ(reg);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~(0x7 << 16);
2646         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2647         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2648
2649         POSTING_READ(reg);
2650         udelay(100);
2651
2652         /* Ironlake workaround, disable clock pointer after downing FDI */
2653         if (HAS_PCH_IBX(dev)) {
2654                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2655                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2656                            I915_READ(FDI_RX_CHICKEN(pipe) &
2657                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2658         }
2659
2660         /* still set train pattern 1 */
2661         reg = FDI_TX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         temp &= ~FDI_LINK_TRAIN_NONE;
2664         temp |= FDI_LINK_TRAIN_PATTERN_1;
2665         I915_WRITE(reg, temp);
2666
2667         reg = FDI_RX_CTL(pipe);
2668         temp = I915_READ(reg);
2669         if (HAS_PCH_CPT(dev)) {
2670                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672         } else {
2673                 temp &= ~FDI_LINK_TRAIN_NONE;
2674                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2675         }
2676         /* BPC in FDI rx is consistent with that in PIPECONF */
2677         temp &= ~(0x07 << 16);
2678         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2679         I915_WRITE(reg, temp);
2680
2681         POSTING_READ(reg);
2682         udelay(100);
2683 }
2684
2685 /*
2686  * When we disable a pipe, we need to clear any pending scanline wait events
2687  * to avoid hanging the ring, which we assume we are waiting on.
2688  */
2689 static void intel_clear_scanline_wait(struct drm_device *dev)
2690 {
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_ring_buffer *ring;
2693         u32 tmp;
2694
2695         if (IS_GEN2(dev))
2696                 /* Can't break the hang on i8xx */
2697                 return;
2698
2699         ring = LP_RING(dev_priv);
2700         tmp = I915_READ_CTL(ring);
2701         if (tmp & RING_WAIT)
2702                 I915_WRITE_CTL(ring, tmp);
2703 }
2704
2705 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2706 {
2707         struct drm_i915_gem_object *obj;
2708         struct drm_i915_private *dev_priv;
2709
2710         if (crtc->fb == NULL)
2711                 return;
2712
2713         obj = to_intel_framebuffer(crtc->fb)->obj;
2714         dev_priv = crtc->dev->dev_private;
2715         wait_event(dev_priv->pending_flip_queue,
2716                    atomic_read(&obj->pending_flip) == 0);
2717 }
2718
2719 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2720 {
2721         struct drm_device *dev = crtc->dev;
2722         struct drm_mode_config *mode_config = &dev->mode_config;
2723         struct intel_encoder *encoder;
2724
2725         /*
2726          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2727          * must be driven by its own crtc; no sharing is possible.
2728          */
2729         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2730                 if (encoder->base.crtc != crtc)
2731                         continue;
2732
2733                 switch (encoder->type) {
2734                 case INTEL_OUTPUT_EDP:
2735                         if (!intel_encoder_is_pch_edp(&encoder->base))
2736                                 return false;
2737                         continue;
2738                 }
2739         }
2740
2741         return true;
2742 }
2743
2744 /*
2745  * Enable PCH resources required for PCH ports:
2746  *   - PCH PLLs
2747  *   - FDI training & RX/TX
2748  *   - update transcoder timings
2749  *   - DP transcoding bits
2750  *   - transcoder
2751  */
2752 static void ironlake_pch_enable(struct drm_crtc *crtc)
2753 {
2754         struct drm_device *dev = crtc->dev;
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2757         int pipe = intel_crtc->pipe;
2758         u32 reg, temp;
2759
2760         /* For PCH output, training FDI link */
2761         dev_priv->display.fdi_link_train(crtc);
2762
2763         intel_enable_pch_pll(dev_priv, pipe);
2764
2765         if (HAS_PCH_CPT(dev)) {
2766                 /* Be sure PCH DPLL SEL is set */
2767                 temp = I915_READ(PCH_DPLL_SEL);
2768                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2769                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2770                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2771                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2772                 I915_WRITE(PCH_DPLL_SEL, temp);
2773         }
2774
2775         /* set transcoder timing, panel must allow it */
2776         assert_panel_unlocked(dev_priv, pipe);
2777         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2778         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2779         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2780
2781         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2782         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2783         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2784
2785         intel_fdi_normal_train(crtc);
2786
2787         /* For PCH DP, enable TRANS_DP_CTL */
2788         if (HAS_PCH_CPT(dev) &&
2789             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2790                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2791                 reg = TRANS_DP_CTL(pipe);
2792                 temp = I915_READ(reg);
2793                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2794                           TRANS_DP_SYNC_MASK |
2795                           TRANS_DP_BPC_MASK);
2796                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2797                          TRANS_DP_ENH_FRAMING);
2798                 temp |= bpc << 9; /* same format but at 11:9 */
2799
2800                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2801                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2802                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2803                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2804
2805                 switch (intel_trans_dp_port_sel(crtc)) {
2806                 case PCH_DP_B:
2807                         temp |= TRANS_DP_PORT_SEL_B;
2808                         break;
2809                 case PCH_DP_C:
2810                         temp |= TRANS_DP_PORT_SEL_C;
2811                         break;
2812                 case PCH_DP_D:
2813                         temp |= TRANS_DP_PORT_SEL_D;
2814                         break;
2815                 default:
2816                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2817                         temp |= TRANS_DP_PORT_SEL_B;
2818                         break;
2819                 }
2820
2821                 I915_WRITE(reg, temp);
2822         }
2823
2824         intel_enable_transcoder(dev_priv, pipe);
2825 }
2826
2827 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2828 {
2829         struct drm_device *dev = crtc->dev;
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2832         int pipe = intel_crtc->pipe;
2833         int plane = intel_crtc->plane;
2834         u32 temp;
2835         bool is_pch_port;
2836
2837         if (intel_crtc->active)
2838                 return;
2839
2840         intel_crtc->active = true;
2841         intel_update_watermarks(dev);
2842
2843         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2844                 temp = I915_READ(PCH_LVDS);
2845                 if ((temp & LVDS_PORT_EN) == 0)
2846                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2847         }
2848
2849         is_pch_port = intel_crtc_driving_pch(crtc);
2850
2851         if (is_pch_port)
2852                 ironlake_fdi_pll_enable(crtc);
2853         else
2854                 ironlake_fdi_disable(crtc);
2855
2856         /* Enable panel fitting for LVDS */
2857         if (dev_priv->pch_pf_size &&
2858             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2859                 /* Force use of hard-coded filter coefficients
2860                  * as some pre-programmed values are broken,
2861                  * e.g. x201.
2862                  */
2863                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2864                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2865                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2866         }
2867
2868         /*
2869          * On ILK+ LUT must be loaded before the pipe is running but with
2870          * clocks enabled
2871          */
2872         intel_crtc_load_lut(crtc);
2873
2874         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2875         intel_enable_plane(dev_priv, plane, pipe);
2876
2877         if (is_pch_port)
2878                 ironlake_pch_enable(crtc);
2879
2880         mutex_lock(&dev->struct_mutex);
2881         intel_update_fbc(dev);
2882         mutex_unlock(&dev->struct_mutex);
2883
2884         intel_crtc_update_cursor(crtc, true);
2885 }
2886
2887 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2888 {
2889         struct drm_device *dev = crtc->dev;
2890         struct drm_i915_private *dev_priv = dev->dev_private;
2891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2892         int pipe = intel_crtc->pipe;
2893         int plane = intel_crtc->plane;
2894         u32 reg, temp;
2895
2896         if (!intel_crtc->active)
2897                 return;
2898
2899         intel_crtc_wait_for_pending_flips(crtc);
2900         drm_vblank_off(dev, pipe);
2901         intel_crtc_update_cursor(crtc, false);
2902
2903         intel_disable_plane(dev_priv, plane, pipe);
2904
2905         if (dev_priv->cfb_plane == plane)
2906                 intel_disable_fbc(dev);
2907
2908         intel_disable_pipe(dev_priv, pipe);
2909
2910         /* Disable PF */
2911         I915_WRITE(PF_CTL(pipe), 0);
2912         I915_WRITE(PF_WIN_SZ(pipe), 0);
2913
2914         ironlake_fdi_disable(crtc);
2915
2916         /* This is a horrible layering violation; we should be doing this in
2917          * the connector/encoder ->prepare instead, but we don't always have
2918          * enough information there about the config to know whether it will
2919          * actually be necessary or just cause undesired flicker.
2920          */
2921         intel_disable_pch_ports(dev_priv, pipe);
2922
2923         intel_disable_transcoder(dev_priv, pipe);
2924
2925         if (HAS_PCH_CPT(dev)) {
2926                 /* disable TRANS_DP_CTL */
2927                 reg = TRANS_DP_CTL(pipe);
2928                 temp = I915_READ(reg);
2929                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2930                 temp |= TRANS_DP_PORT_SEL_NONE;
2931                 I915_WRITE(reg, temp);
2932
2933                 /* disable DPLL_SEL */
2934                 temp = I915_READ(PCH_DPLL_SEL);
2935                 switch (pipe) {
2936                 case 0:
2937                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2938                         break;
2939                 case 1:
2940                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2941                         break;
2942                 case 2:
2943                         /* FIXME: manage transcoder PLLs? */
2944                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2945                         break;
2946                 default:
2947                         BUG(); /* wtf */
2948                 }
2949                 I915_WRITE(PCH_DPLL_SEL, temp);
2950         }
2951
2952         /* disable PCH DPLL */
2953         intel_disable_pch_pll(dev_priv, pipe);
2954
2955         /* Switch from PCDclk to Rawclk */
2956         reg = FDI_RX_CTL(pipe);
2957         temp = I915_READ(reg);
2958         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2959
2960         /* Disable CPU FDI TX PLL */
2961         reg = FDI_TX_CTL(pipe);
2962         temp = I915_READ(reg);
2963         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2964
2965         POSTING_READ(reg);
2966         udelay(100);
2967
2968         reg = FDI_RX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2971
2972         /* Wait for the clocks to turn off. */
2973         POSTING_READ(reg);
2974         udelay(100);
2975
2976         intel_crtc->active = false;
2977         intel_update_watermarks(dev);
2978
2979         mutex_lock(&dev->struct_mutex);
2980         intel_update_fbc(dev);
2981         intel_clear_scanline_wait(dev);
2982         mutex_unlock(&dev->struct_mutex);
2983 }
2984
2985 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2986 {
2987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988         int pipe = intel_crtc->pipe;
2989         int plane = intel_crtc->plane;
2990
2991         /* XXX: When our outputs are all unaware of DPMS modes other than off
2992          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2993          */
2994         switch (mode) {
2995         case DRM_MODE_DPMS_ON:
2996         case DRM_MODE_DPMS_STANDBY:
2997         case DRM_MODE_DPMS_SUSPEND:
2998                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2999                 ironlake_crtc_enable(crtc);
3000                 break;
3001
3002         case DRM_MODE_DPMS_OFF:
3003                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3004                 ironlake_crtc_disable(crtc);
3005                 break;
3006         }
3007 }
3008
3009 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3010 {
3011         if (!enable && intel_crtc->overlay) {
3012                 struct drm_device *dev = intel_crtc->base.dev;
3013                 struct drm_i915_private *dev_priv = dev->dev_private;
3014
3015                 mutex_lock(&dev->struct_mutex);
3016                 dev_priv->mm.interruptible = false;
3017                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3018                 dev_priv->mm.interruptible = true;
3019                 mutex_unlock(&dev->struct_mutex);
3020         }
3021
3022         /* Let userspace switch the overlay on again. In most cases userspace
3023          * has to recompute where to put it anyway.
3024          */
3025 }
3026
3027 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3028 {
3029         struct drm_device *dev = crtc->dev;
3030         struct drm_i915_private *dev_priv = dev->dev_private;
3031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032         int pipe = intel_crtc->pipe;
3033         int plane = intel_crtc->plane;
3034
3035         if (intel_crtc->active)
3036                 return;
3037
3038         intel_crtc->active = true;
3039         intel_update_watermarks(dev);
3040
3041         intel_enable_pll(dev_priv, pipe);
3042         intel_enable_pipe(dev_priv, pipe, false);
3043         intel_enable_plane(dev_priv, plane, pipe);
3044
3045         intel_crtc_load_lut(crtc);
3046         intel_update_fbc(dev);
3047
3048         /* Give the overlay scaler a chance to enable if it's on this pipe */
3049         intel_crtc_dpms_overlay(intel_crtc, true);
3050         intel_crtc_update_cursor(crtc, true);
3051 }
3052
3053 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3054 {
3055         struct drm_device *dev = crtc->dev;
3056         struct drm_i915_private *dev_priv = dev->dev_private;
3057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058         int pipe = intel_crtc->pipe;
3059         int plane = intel_crtc->plane;
3060
3061         if (!intel_crtc->active)
3062                 return;
3063
3064         /* Give the overlay scaler a chance to disable if it's on this pipe */
3065         intel_crtc_wait_for_pending_flips(crtc);
3066         drm_vblank_off(dev, pipe);
3067         intel_crtc_dpms_overlay(intel_crtc, false);
3068         intel_crtc_update_cursor(crtc, false);
3069
3070         if (dev_priv->cfb_plane == plane)
3071                 intel_disable_fbc(dev);
3072
3073         intel_disable_plane(dev_priv, plane, pipe);
3074         intel_disable_pipe(dev_priv, pipe);
3075         intel_disable_pll(dev_priv, pipe);
3076
3077         intel_crtc->active = false;
3078         intel_update_fbc(dev);
3079         intel_update_watermarks(dev);
3080         intel_clear_scanline_wait(dev);
3081 }
3082
3083 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3084 {
3085         /* XXX: When our outputs are all unaware of DPMS modes other than off
3086          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3087          */
3088         switch (mode) {
3089         case DRM_MODE_DPMS_ON:
3090         case DRM_MODE_DPMS_STANDBY:
3091         case DRM_MODE_DPMS_SUSPEND:
3092                 i9xx_crtc_enable(crtc);
3093                 break;
3094         case DRM_MODE_DPMS_OFF:
3095                 i9xx_crtc_disable(crtc);
3096                 break;
3097         }
3098 }
3099
3100 /**
3101  * Sets the power management mode of the pipe and plane.
3102  */
3103 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         struct drm_i915_master_private *master_priv;
3108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3109         int pipe = intel_crtc->pipe;
3110         bool enabled;
3111
3112         if (intel_crtc->dpms_mode == mode)
3113                 return;
3114
3115         intel_crtc->dpms_mode = mode;
3116
3117         dev_priv->display.dpms(crtc, mode);
3118
3119         if (!dev->primary->master)
3120                 return;
3121
3122         master_priv = dev->primary->master->driver_priv;
3123         if (!master_priv->sarea_priv)
3124                 return;
3125
3126         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3127
3128         switch (pipe) {
3129         case 0:
3130                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3131                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3132                 break;
3133         case 1:
3134                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3135                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3136                 break;
3137         default:
3138                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3139                 break;
3140         }
3141 }
3142
3143 static void intel_crtc_disable(struct drm_crtc *crtc)
3144 {
3145         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3146         struct drm_device *dev = crtc->dev;
3147
3148         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3149
3150         if (crtc->fb) {
3151                 mutex_lock(&dev->struct_mutex);
3152                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3153                 mutex_unlock(&dev->struct_mutex);
3154         }
3155 }
3156
3157 /* Prepare for a mode set.
3158  *
3159  * Note we could be a lot smarter here.  We need to figure out which outputs
3160  * will be enabled, which disabled (in short, how the config will changes)
3161  * and perform the minimum necessary steps to accomplish that, e.g. updating
3162  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3163  * panel fitting is in the proper state, etc.
3164  */
3165 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3166 {
3167         i9xx_crtc_disable(crtc);
3168 }
3169
3170 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3171 {
3172         i9xx_crtc_enable(crtc);
3173 }
3174
3175 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3176 {
3177         ironlake_crtc_disable(crtc);
3178 }
3179
3180 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3181 {
3182         ironlake_crtc_enable(crtc);
3183 }
3184
3185 void intel_encoder_prepare (struct drm_encoder *encoder)
3186 {
3187         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3188         /* lvds has its own version of prepare see intel_lvds_prepare */
3189         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3190 }
3191
3192 void intel_encoder_commit (struct drm_encoder *encoder)
3193 {
3194         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3195         /* lvds has its own version of commit see intel_lvds_commit */
3196         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3197 }
3198
3199 void intel_encoder_destroy(struct drm_encoder *encoder)
3200 {
3201         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3202
3203         drm_encoder_cleanup(encoder);
3204         kfree(intel_encoder);
3205 }
3206
3207 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3208                                   struct drm_display_mode *mode,
3209                                   struct drm_display_mode *adjusted_mode)
3210 {
3211         struct drm_device *dev = crtc->dev;
3212
3213         if (HAS_PCH_SPLIT(dev)) {
3214                 /* FDI link clock is fixed at 2.7G */
3215                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3216                         return false;
3217         }
3218
3219         /* XXX some encoders set the crtcinfo, others don't.
3220          * Obviously we need some form of conflict resolution here...
3221          */
3222         if (adjusted_mode->crtc_htotal == 0)
3223                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3224
3225         return true;
3226 }
3227
3228 static int i945_get_display_clock_speed(struct drm_device *dev)
3229 {
3230         return 400000;
3231 }
3232
3233 static int i915_get_display_clock_speed(struct drm_device *dev)
3234 {
3235         return 333000;
3236 }
3237
3238 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3239 {
3240         return 200000;
3241 }
3242
3243 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3244 {
3245         u16 gcfgc = 0;
3246
3247         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3248
3249         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3250                 return 133000;
3251         else {
3252                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3253                 case GC_DISPLAY_CLOCK_333_MHZ:
3254                         return 333000;
3255                 default:
3256                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3257                         return 190000;
3258                 }
3259         }
3260 }
3261
3262 static int i865_get_display_clock_speed(struct drm_device *dev)
3263 {
3264         return 266000;
3265 }
3266
3267 static int i855_get_display_clock_speed(struct drm_device *dev)
3268 {
3269         u16 hpllcc = 0;
3270         /* Assume that the hardware is in the high speed state.  This
3271          * should be the default.
3272          */
3273         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3274         case GC_CLOCK_133_200:
3275         case GC_CLOCK_100_200:
3276                 return 200000;
3277         case GC_CLOCK_166_250:
3278                 return 250000;
3279         case GC_CLOCK_100_133:
3280                 return 133000;
3281         }
3282
3283         /* Shouldn't happen */
3284         return 0;
3285 }
3286
3287 static int i830_get_display_clock_speed(struct drm_device *dev)
3288 {
3289         return 133000;
3290 }
3291
3292 struct fdi_m_n {
3293         u32        tu;
3294         u32        gmch_m;
3295         u32        gmch_n;
3296         u32        link_m;
3297         u32        link_n;
3298 };
3299
3300 static void
3301 fdi_reduce_ratio(u32 *num, u32 *den)
3302 {
3303         while (*num > 0xffffff || *den > 0xffffff) {
3304                 *num >>= 1;
3305                 *den >>= 1;
3306         }
3307 }
3308
3309 static void
3310 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3311                      int link_clock, struct fdi_m_n *m_n)
3312 {
3313         m_n->tu = 64; /* default size */
3314
3315         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3316         m_n->gmch_m = bits_per_pixel * pixel_clock;
3317         m_n->gmch_n = link_clock * nlanes * 8;
3318         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3319
3320         m_n->link_m = pixel_clock;
3321         m_n->link_n = link_clock;
3322         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3323 }
3324
3325
3326 struct intel_watermark_params {
3327         unsigned long fifo_size;
3328         unsigned long max_wm;
3329         unsigned long default_wm;
3330         unsigned long guard_size;
3331         unsigned long cacheline_size;
3332 };
3333
3334 /* Pineview has different values for various configs */
3335 static const struct intel_watermark_params pineview_display_wm = {
3336         PINEVIEW_DISPLAY_FIFO,
3337         PINEVIEW_MAX_WM,
3338         PINEVIEW_DFT_WM,
3339         PINEVIEW_GUARD_WM,
3340         PINEVIEW_FIFO_LINE_SIZE
3341 };
3342 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3343         PINEVIEW_DISPLAY_FIFO,
3344         PINEVIEW_MAX_WM,
3345         PINEVIEW_DFT_HPLLOFF_WM,
3346         PINEVIEW_GUARD_WM,
3347         PINEVIEW_FIFO_LINE_SIZE
3348 };
3349 static const struct intel_watermark_params pineview_cursor_wm = {
3350         PINEVIEW_CURSOR_FIFO,
3351         PINEVIEW_CURSOR_MAX_WM,
3352         PINEVIEW_CURSOR_DFT_WM,
3353         PINEVIEW_CURSOR_GUARD_WM,
3354         PINEVIEW_FIFO_LINE_SIZE,
3355 };
3356 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3357         PINEVIEW_CURSOR_FIFO,
3358         PINEVIEW_CURSOR_MAX_WM,
3359         PINEVIEW_CURSOR_DFT_WM,
3360         PINEVIEW_CURSOR_GUARD_WM,
3361         PINEVIEW_FIFO_LINE_SIZE
3362 };
3363 static const struct intel_watermark_params g4x_wm_info = {
3364         G4X_FIFO_SIZE,
3365         G4X_MAX_WM,
3366         G4X_MAX_WM,
3367         2,
3368         G4X_FIFO_LINE_SIZE,
3369 };
3370 static const struct intel_watermark_params g4x_cursor_wm_info = {
3371         I965_CURSOR_FIFO,
3372         I965_CURSOR_MAX_WM,
3373         I965_CURSOR_DFT_WM,
3374         2,
3375         G4X_FIFO_LINE_SIZE,
3376 };
3377 static const struct intel_watermark_params i965_cursor_wm_info = {
3378         I965_CURSOR_FIFO,
3379         I965_CURSOR_MAX_WM,
3380         I965_CURSOR_DFT_WM,
3381         2,
3382         I915_FIFO_LINE_SIZE,
3383 };
3384 static const struct intel_watermark_params i945_wm_info = {
3385         I945_FIFO_SIZE,
3386         I915_MAX_WM,
3387         1,
3388         2,
3389         I915_FIFO_LINE_SIZE
3390 };
3391 static const struct intel_watermark_params i915_wm_info = {
3392         I915_FIFO_SIZE,
3393         I915_MAX_WM,
3394         1,
3395         2,
3396         I915_FIFO_LINE_SIZE
3397 };
3398 static const struct intel_watermark_params i855_wm_info = {
3399         I855GM_FIFO_SIZE,
3400         I915_MAX_WM,
3401         1,
3402         2,
3403         I830_FIFO_LINE_SIZE
3404 };
3405 static const struct intel_watermark_params i830_wm_info = {
3406         I830_FIFO_SIZE,
3407         I915_MAX_WM,
3408         1,
3409         2,
3410         I830_FIFO_LINE_SIZE
3411 };
3412
3413 static const struct intel_watermark_params ironlake_display_wm_info = {
3414         ILK_DISPLAY_FIFO,
3415         ILK_DISPLAY_MAXWM,
3416         ILK_DISPLAY_DFTWM,
3417         2,
3418         ILK_FIFO_LINE_SIZE
3419 };
3420 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3421         ILK_CURSOR_FIFO,
3422         ILK_CURSOR_MAXWM,
3423         ILK_CURSOR_DFTWM,
3424         2,
3425         ILK_FIFO_LINE_SIZE
3426 };
3427 static const struct intel_watermark_params ironlake_display_srwm_info = {
3428         ILK_DISPLAY_SR_FIFO,
3429         ILK_DISPLAY_MAX_SRWM,
3430         ILK_DISPLAY_DFT_SRWM,
3431         2,
3432         ILK_FIFO_LINE_SIZE
3433 };
3434 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3435         ILK_CURSOR_SR_FIFO,
3436         ILK_CURSOR_MAX_SRWM,
3437         ILK_CURSOR_DFT_SRWM,
3438         2,
3439         ILK_FIFO_LINE_SIZE
3440 };
3441
3442 static const struct intel_watermark_params sandybridge_display_wm_info = {
3443         SNB_DISPLAY_FIFO,
3444         SNB_DISPLAY_MAXWM,
3445         SNB_DISPLAY_DFTWM,
3446         2,
3447         SNB_FIFO_LINE_SIZE
3448 };
3449 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3450         SNB_CURSOR_FIFO,
3451         SNB_CURSOR_MAXWM,
3452         SNB_CURSOR_DFTWM,
3453         2,
3454         SNB_FIFO_LINE_SIZE
3455 };
3456 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3457         SNB_DISPLAY_SR_FIFO,
3458         SNB_DISPLAY_MAX_SRWM,
3459         SNB_DISPLAY_DFT_SRWM,
3460         2,
3461         SNB_FIFO_LINE_SIZE
3462 };
3463 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3464         SNB_CURSOR_SR_FIFO,
3465         SNB_CURSOR_MAX_SRWM,
3466         SNB_CURSOR_DFT_SRWM,
3467         2,
3468         SNB_FIFO_LINE_SIZE
3469 };
3470
3471
3472 /**
3473  * intel_calculate_wm - calculate watermark level
3474  * @clock_in_khz: pixel clock
3475  * @wm: chip FIFO params
3476  * @pixel_size: display pixel size
3477  * @latency_ns: memory latency for the platform
3478  *
3479  * Calculate the watermark level (the level at which the display plane will
3480  * start fetching from memory again).  Each chip has a different display
3481  * FIFO size and allocation, so the caller needs to figure that out and pass
3482  * in the correct intel_watermark_params structure.
3483  *
3484  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3485  * on the pixel size.  When it reaches the watermark level, it'll start
3486  * fetching FIFO line sized based chunks from memory until the FIFO fills
3487  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3488  * will occur, and a display engine hang could result.
3489  */
3490 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3491                                         const struct intel_watermark_params *wm,
3492                                         int fifo_size,
3493                                         int pixel_size,
3494                                         unsigned long latency_ns)
3495 {
3496         long entries_required, wm_size;
3497
3498         /*
3499          * Note: we need to make sure we don't overflow for various clock &
3500          * latency values.
3501          * clocks go from a few thousand to several hundred thousand.
3502          * latency is usually a few thousand
3503          */
3504         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3505                 1000;
3506         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3507
3508         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3509
3510         wm_size = fifo_size - (entries_required + wm->guard_size);
3511
3512         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3513
3514         /* Don't promote wm_size to unsigned... */
3515         if (wm_size > (long)wm->max_wm)
3516                 wm_size = wm->max_wm;
3517         if (wm_size <= 0)
3518                 wm_size = wm->default_wm;
3519         return wm_size;
3520 }
3521
3522 struct cxsr_latency {
3523         int is_desktop;
3524         int is_ddr3;
3525         unsigned long fsb_freq;
3526         unsigned long mem_freq;
3527         unsigned long display_sr;
3528         unsigned long display_hpll_disable;
3529         unsigned long cursor_sr;
3530         unsigned long cursor_hpll_disable;
3531 };
3532
3533 static const struct cxsr_latency cxsr_latency_table[] = {
3534         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3535         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3536         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3537         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3538         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3539
3540         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3541         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3542         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3543         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3544         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3545
3546         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3547         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3548         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3549         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3550         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3551
3552         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3553         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3554         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3555         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3556         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3557
3558         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3559         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3560         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3561         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3562         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3563
3564         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3565         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3566         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3567         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3568         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3569 };
3570
3571 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3572                                                          int is_ddr3,
3573                                                          int fsb,
3574                                                          int mem)
3575 {
3576         const struct cxsr_latency *latency;
3577         int i;
3578
3579         if (fsb == 0 || mem == 0)
3580                 return NULL;
3581
3582         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3583                 latency = &cxsr_latency_table[i];
3584                 if (is_desktop == latency->is_desktop &&
3585                     is_ddr3 == latency->is_ddr3 &&
3586                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3587                         return latency;
3588         }
3589
3590         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3591
3592         return NULL;
3593 }
3594
3595 static void pineview_disable_cxsr(struct drm_device *dev)
3596 {
3597         struct drm_i915_private *dev_priv = dev->dev_private;
3598
3599         /* deactivate cxsr */
3600         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3601 }
3602
3603 /*
3604  * Latency for FIFO fetches is dependent on several factors:
3605  *   - memory configuration (speed, channels)
3606  *   - chipset
3607  *   - current MCH state
3608  * It can be fairly high in some situations, so here we assume a fairly
3609  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3610  * set this value too high, the FIFO will fetch frequently to stay full)
3611  * and power consumption (set it too low to save power and we might see
3612  * FIFO underruns and display "flicker").
3613  *
3614  * A value of 5us seems to be a good balance; safe for very low end
3615  * platforms but not overly aggressive on lower latency configs.
3616  */
3617 static const int latency_ns = 5000;
3618
3619 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3620 {
3621         struct drm_i915_private *dev_priv = dev->dev_private;
3622         uint32_t dsparb = I915_READ(DSPARB);
3623         int size;
3624
3625         size = dsparb & 0x7f;
3626         if (plane)
3627                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3628
3629         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3630                       plane ? "B" : "A", size);
3631
3632         return size;
3633 }
3634
3635 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3636 {
3637         struct drm_i915_private *dev_priv = dev->dev_private;
3638         uint32_t dsparb = I915_READ(DSPARB);
3639         int size;
3640
3641         size = dsparb & 0x1ff;
3642         if (plane)
3643                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3644         size >>= 1; /* Convert to cachelines */
3645
3646         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3647                       plane ? "B" : "A", size);
3648
3649         return size;
3650 }
3651
3652 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3653 {
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         uint32_t dsparb = I915_READ(DSPARB);
3656         int size;
3657
3658         size = dsparb & 0x7f;
3659         size >>= 2; /* Convert to cachelines */
3660
3661         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3662                       plane ? "B" : "A",
3663                       size);
3664
3665         return size;
3666 }
3667
3668 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3669 {
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671         uint32_t dsparb = I915_READ(DSPARB);
3672         int size;
3673
3674         size = dsparb & 0x7f;
3675         size >>= 1; /* Convert to cachelines */
3676
3677         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3678                       plane ? "B" : "A", size);
3679
3680         return size;
3681 }
3682
3683 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3684 {
3685         struct drm_crtc *crtc, *enabled = NULL;
3686
3687         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3688                 if (crtc->enabled && crtc->fb) {
3689                         if (enabled)
3690                                 return NULL;
3691                         enabled = crtc;
3692                 }
3693         }
3694
3695         return enabled;
3696 }
3697
3698 static void pineview_update_wm(struct drm_device *dev)
3699 {
3700         struct drm_i915_private *dev_priv = dev->dev_private;
3701         struct drm_crtc *crtc;
3702         const struct cxsr_latency *latency;
3703         u32 reg;
3704         unsigned long wm;
3705
3706         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3707                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3708         if (!latency) {
3709                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3710                 pineview_disable_cxsr(dev);
3711                 return;
3712         }
3713
3714         crtc = single_enabled_crtc(dev);
3715         if (crtc) {
3716                 int clock = crtc->mode.clock;
3717                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3718
3719                 /* Display SR */
3720                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3721                                         pineview_display_wm.fifo_size,
3722                                         pixel_size, latency->display_sr);
3723                 reg = I915_READ(DSPFW1);
3724                 reg &= ~DSPFW_SR_MASK;
3725                 reg |= wm << DSPFW_SR_SHIFT;
3726                 I915_WRITE(DSPFW1, reg);
3727                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3728
3729                 /* cursor SR */
3730                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3731                                         pineview_display_wm.fifo_size,
3732                                         pixel_size, latency->cursor_sr);
3733                 reg = I915_READ(DSPFW3);
3734                 reg &= ~DSPFW_CURSOR_SR_MASK;
3735                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3736                 I915_WRITE(DSPFW3, reg);
3737
3738                 /* Display HPLL off SR */
3739                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3740                                         pineview_display_hplloff_wm.fifo_size,
3741                                         pixel_size, latency->display_hpll_disable);
3742                 reg = I915_READ(DSPFW3);
3743                 reg &= ~DSPFW_HPLL_SR_MASK;
3744                 reg |= wm & DSPFW_HPLL_SR_MASK;
3745                 I915_WRITE(DSPFW3, reg);
3746
3747                 /* cursor HPLL off SR */
3748                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3749                                         pineview_display_hplloff_wm.fifo_size,
3750                                         pixel_size, latency->cursor_hpll_disable);
3751                 reg = I915_READ(DSPFW3);
3752                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3753                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3754                 I915_WRITE(DSPFW3, reg);
3755                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3756
3757                 /* activate cxsr */
3758                 I915_WRITE(DSPFW3,
3759                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3760                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3761         } else {
3762                 pineview_disable_cxsr(dev);
3763                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3764         }
3765 }
3766
3767 static bool g4x_compute_wm0(struct drm_device *dev,
3768                             int plane,
3769                             const struct intel_watermark_params *display,
3770                             int display_latency_ns,
3771                             const struct intel_watermark_params *cursor,
3772                             int cursor_latency_ns,
3773                             int *plane_wm,
3774                             int *cursor_wm)
3775 {
3776         struct drm_crtc *crtc;
3777         int htotal, hdisplay, clock, pixel_size;
3778         int line_time_us, line_count;
3779         int entries, tlb_miss;
3780
3781         crtc = intel_get_crtc_for_plane(dev, plane);
3782         if (crtc->fb == NULL || !crtc->enabled) {
3783                 *cursor_wm = cursor->guard_size;
3784                 *plane_wm = display->guard_size;
3785                 return false;
3786         }
3787
3788         htotal = crtc->mode.htotal;
3789         hdisplay = crtc->mode.hdisplay;
3790         clock = crtc->mode.clock;
3791         pixel_size = crtc->fb->bits_per_pixel / 8;
3792
3793         /* Use the small buffer method to calculate plane watermark */
3794         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3795         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3796         if (tlb_miss > 0)
3797                 entries += tlb_miss;
3798         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3799         *plane_wm = entries + display->guard_size;
3800         if (*plane_wm > (int)display->max_wm)
3801                 *plane_wm = display->max_wm;
3802
3803         /* Use the large buffer method to calculate cursor watermark */
3804         line_time_us = ((htotal * 1000) / clock);
3805         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3806         entries = line_count * 64 * pixel_size;
3807         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3808         if (tlb_miss > 0)
3809                 entries += tlb_miss;
3810         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3811         *cursor_wm = entries + cursor->guard_size;
3812         if (*cursor_wm > (int)cursor->max_wm)
3813                 *cursor_wm = (int)cursor->max_wm;
3814
3815         return true;
3816 }
3817
3818 /*
3819  * Check the wm result.
3820  *
3821  * If any calculated watermark values is larger than the maximum value that
3822  * can be programmed into the associated watermark register, that watermark
3823  * must be disabled.
3824  */
3825 static bool g4x_check_srwm(struct drm_device *dev,
3826                            int display_wm, int cursor_wm,
3827                            const struct intel_watermark_params *display,
3828                            const struct intel_watermark_params *cursor)
3829 {
3830         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3831                       display_wm, cursor_wm);
3832
3833         if (display_wm > display->max_wm) {
3834                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3835                               display_wm, display->max_wm);
3836                 return false;
3837         }
3838
3839         if (cursor_wm > cursor->max_wm) {
3840                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3841                               cursor_wm, cursor->max_wm);
3842                 return false;
3843         }
3844
3845         if (!(display_wm || cursor_wm)) {
3846                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3847                 return false;
3848         }
3849
3850         return true;
3851 }
3852
3853 static bool g4x_compute_srwm(struct drm_device *dev,
3854                              int plane,
3855                              int latency_ns,
3856                              const struct intel_watermark_params *display,
3857                              const struct intel_watermark_params *cursor,
3858                              int *display_wm, int *cursor_wm)
3859 {
3860         struct drm_crtc *crtc;
3861         int hdisplay, htotal, pixel_size, clock;
3862         unsigned long line_time_us;
3863         int line_count, line_size;
3864         int small, large;
3865         int entries;
3866
3867         if (!latency_ns) {
3868                 *display_wm = *cursor_wm = 0;
3869                 return false;
3870         }
3871
3872         crtc = intel_get_crtc_for_plane(dev, plane);
3873         hdisplay = crtc->mode.hdisplay;
3874         htotal = crtc->mode.htotal;
3875         clock = crtc->mode.clock;
3876         pixel_size = crtc->fb->bits_per_pixel / 8;
3877
3878         line_time_us = (htotal * 1000) / clock;
3879         line_count = (latency_ns / line_time_us + 1000) / 1000;
3880         line_size = hdisplay * pixel_size;
3881
3882         /* Use the minimum of the small and large buffer method for primary */
3883         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3884         large = line_count * line_size;
3885
3886         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3887         *display_wm = entries + display->guard_size;
3888
3889         /* calculate the self-refresh watermark for display cursor */
3890         entries = line_count * pixel_size * 64;
3891         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3892         *cursor_wm = entries + cursor->guard_size;
3893
3894         return g4x_check_srwm(dev,
3895                               *display_wm, *cursor_wm,
3896                               display, cursor);
3897 }
3898
3899 #define single_plane_enabled(mask) is_power_of_2(mask)
3900
3901 static void g4x_update_wm(struct drm_device *dev)
3902 {
3903         static const int sr_latency_ns = 12000;
3904         struct drm_i915_private *dev_priv = dev->dev_private;
3905         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3906         int plane_sr, cursor_sr;
3907         unsigned int enabled = 0;
3908
3909         if (g4x_compute_wm0(dev, 0,
3910                             &g4x_wm_info, latency_ns,
3911                             &g4x_cursor_wm_info, latency_ns,
3912                             &planea_wm, &cursora_wm))
3913                 enabled |= 1;
3914
3915         if (g4x_compute_wm0(dev, 1,
3916                             &g4x_wm_info, latency_ns,
3917                             &g4x_cursor_wm_info, latency_ns,
3918                             &planeb_wm, &cursorb_wm))
3919                 enabled |= 2;
3920
3921         plane_sr = cursor_sr = 0;
3922         if (single_plane_enabled(enabled) &&
3923             g4x_compute_srwm(dev, ffs(enabled) - 1,
3924                              sr_latency_ns,
3925                              &g4x_wm_info,
3926                              &g4x_cursor_wm_info,
3927                              &plane_sr, &cursor_sr))
3928                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3929         else
3930                 I915_WRITE(FW_BLC_SELF,
3931                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3932
3933         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3934                       planea_wm, cursora_wm,
3935                       planeb_wm, cursorb_wm,
3936                       plane_sr, cursor_sr);
3937
3938         I915_WRITE(DSPFW1,
3939                    (plane_sr << DSPFW_SR_SHIFT) |
3940                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3941                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3942                    planea_wm);
3943         I915_WRITE(DSPFW2,
3944                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3945                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3946         /* HPLL off in SR has some issues on G4x... disable it */
3947         I915_WRITE(DSPFW3,
3948                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3949                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3950 }
3951
3952 static void i965_update_wm(struct drm_device *dev)
3953 {
3954         struct drm_i915_private *dev_priv = dev->dev_private;
3955         struct drm_crtc *crtc;
3956         int srwm = 1;
3957         int cursor_sr = 16;
3958
3959         /* Calc sr entries for one plane configs */
3960         crtc = single_enabled_crtc(dev);
3961         if (crtc) {
3962                 /* self-refresh has much higher latency */
3963                 static const int sr_latency_ns = 12000;
3964                 int clock = crtc->mode.clock;
3965                 int htotal = crtc->mode.htotal;
3966                 int hdisplay = crtc->mode.hdisplay;
3967                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3968                 unsigned long line_time_us;
3969                 int entries;
3970
3971                 line_time_us = ((htotal * 1000) / clock);
3972
3973                 /* Use ns/us then divide to preserve precision */
3974                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3975                         pixel_size * hdisplay;
3976                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3977                 srwm = I965_FIFO_SIZE - entries;
3978                 if (srwm < 0)
3979                         srwm = 1;
3980                 srwm &= 0x1ff;
3981                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3982                               entries, srwm);
3983
3984                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3985                         pixel_size * 64;
3986                 entries = DIV_ROUND_UP(entries,
3987                                           i965_cursor_wm_info.cacheline_size);
3988                 cursor_sr = i965_cursor_wm_info.fifo_size -
3989                         (entries + i965_cursor_wm_info.guard_size);
3990
3991                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3992                         cursor_sr = i965_cursor_wm_info.max_wm;
3993
3994                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3995                               "cursor %d\n", srwm, cursor_sr);
3996
3997                 if (IS_CRESTLINE(dev))
3998                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3999         } else {
4000                 /* Turn off self refresh if both pipes are enabled */
4001                 if (IS_CRESTLINE(dev))
4002                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4003                                    & ~FW_BLC_SELF_EN);
4004         }
4005
4006         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4007                       srwm);
4008
4009         /* 965 has limitations... */
4010         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4011                    (8 << 16) | (8 << 8) | (8 << 0));
4012         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4013         /* update cursor SR watermark */
4014         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4015 }
4016
4017 static void i9xx_update_wm(struct drm_device *dev)
4018 {
4019         struct drm_i915_private *dev_priv = dev->dev_private;
4020         const struct intel_watermark_params *wm_info;
4021         uint32_t fwater_lo;
4022         uint32_t fwater_hi;
4023         int cwm, srwm = 1;
4024         int fifo_size;
4025         int planea_wm, planeb_wm;
4026         struct drm_crtc *crtc, *enabled = NULL;
4027
4028         if (IS_I945GM(dev))
4029                 wm_info = &i945_wm_info;
4030         else if (!IS_GEN2(dev))
4031                 wm_info = &i915_wm_info;
4032         else
4033                 wm_info = &i855_wm_info;
4034
4035         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4036         crtc = intel_get_crtc_for_plane(dev, 0);
4037         if (crtc->enabled && crtc->fb) {
4038                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4039                                                wm_info, fifo_size,
4040                                                crtc->fb->bits_per_pixel / 8,
4041                                                latency_ns);
4042                 enabled = crtc;
4043         } else
4044                 planea_wm = fifo_size - wm_info->guard_size;
4045
4046         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4047         crtc = intel_get_crtc_for_plane(dev, 1);
4048         if (crtc->enabled && crtc->fb) {
4049                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4050                                                wm_info, fifo_size,
4051                                                crtc->fb->bits_per_pixel / 8,
4052                                                latency_ns);
4053                 if (enabled == NULL)
4054                         enabled = crtc;
4055                 else
4056                         enabled = NULL;
4057         } else
4058                 planeb_wm = fifo_size - wm_info->guard_size;
4059
4060         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4061
4062         /*
4063          * Overlay gets an aggressive default since video jitter is bad.
4064          */
4065         cwm = 2;
4066
4067         /* Play safe and disable self-refresh before adjusting watermarks. */
4068         if (IS_I945G(dev) || IS_I945GM(dev))
4069                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4070         else if (IS_I915GM(dev))
4071                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4072
4073         /* Calc sr entries for one plane configs */
4074         if (HAS_FW_BLC(dev) && enabled) {
4075                 /* self-refresh has much higher latency */
4076                 static const int sr_latency_ns = 6000;
4077                 int clock = enabled->mode.clock;
4078                 int htotal = enabled->mode.htotal;
4079                 int hdisplay = enabled->mode.hdisplay;
4080                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4081                 unsigned long line_time_us;
4082                 int entries;
4083
4084                 line_time_us = (htotal * 1000) / clock;
4085
4086                 /* Use ns/us then divide to preserve precision */
4087                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4088                         pixel_size * hdisplay;
4089                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4090                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4091                 srwm = wm_info->fifo_size - entries;
4092                 if (srwm < 0)
4093                         srwm = 1;
4094
4095                 if (IS_I945G(dev) || IS_I945GM(dev))
4096                         I915_WRITE(FW_BLC_SELF,
4097                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4098                 else if (IS_I915GM(dev))
4099                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4100         }
4101
4102         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4103                       planea_wm, planeb_wm, cwm, srwm);
4104
4105         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4106         fwater_hi = (cwm & 0x1f);
4107
4108         /* Set request length to 8 cachelines per fetch */
4109         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4110         fwater_hi = fwater_hi | (1 << 8);
4111
4112         I915_WRITE(FW_BLC, fwater_lo);
4113         I915_WRITE(FW_BLC2, fwater_hi);
4114
4115         if (HAS_FW_BLC(dev)) {
4116                 if (enabled) {
4117                         if (IS_I945G(dev) || IS_I945GM(dev))
4118                                 I915_WRITE(FW_BLC_SELF,
4119                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4120                         else if (IS_I915GM(dev))
4121                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4122                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4123                 } else
4124                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4125         }
4126 }
4127
4128 static void i830_update_wm(struct drm_device *dev)
4129 {
4130         struct drm_i915_private *dev_priv = dev->dev_private;
4131         struct drm_crtc *crtc;
4132         uint32_t fwater_lo;
4133         int planea_wm;
4134
4135         crtc = single_enabled_crtc(dev);
4136         if (crtc == NULL)
4137                 return;
4138
4139         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4140                                        dev_priv->display.get_fifo_size(dev, 0),
4141                                        crtc->fb->bits_per_pixel / 8,
4142                                        latency_ns);
4143         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4144         fwater_lo |= (3<<8) | planea_wm;
4145
4146         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4147
4148         I915_WRITE(FW_BLC, fwater_lo);
4149 }
4150
4151 #define ILK_LP0_PLANE_LATENCY           700
4152 #define ILK_LP0_CURSOR_LATENCY          1300
4153
4154 /*
4155  * Check the wm result.
4156  *
4157  * If any calculated watermark values is larger than the maximum value that
4158  * can be programmed into the associated watermark register, that watermark
4159  * must be disabled.
4160  */
4161 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4162                                 int fbc_wm, int display_wm, int cursor_wm,
4163                                 const struct intel_watermark_params *display,
4164                                 const struct intel_watermark_params *cursor)
4165 {
4166         struct drm_i915_private *dev_priv = dev->dev_private;
4167
4168         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4169                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4170
4171         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4172                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4173                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4174
4175                 /* fbc has it's own way to disable FBC WM */
4176                 I915_WRITE(DISP_ARB_CTL,
4177                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4178                 return false;
4179         }
4180
4181         if (display_wm > display->max_wm) {
4182                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4183                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4184                 return false;
4185         }
4186
4187         if (cursor_wm > cursor->max_wm) {
4188                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4189                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4190                 return false;
4191         }
4192
4193         if (!(fbc_wm || display_wm || cursor_wm)) {
4194                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4195                 return false;
4196         }
4197
4198         return true;
4199 }
4200
4201 /*
4202  * Compute watermark values of WM[1-3],
4203  */
4204 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4205                                   int latency_ns,
4206                                   const struct intel_watermark_params *display,
4207                                   const struct intel_watermark_params *cursor,
4208                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4209 {
4210         struct drm_crtc *crtc;
4211         unsigned long line_time_us;
4212         int hdisplay, htotal, pixel_size, clock;
4213         int line_count, line_size;
4214         int small, large;
4215         int entries;
4216
4217         if (!latency_ns) {
4218                 *fbc_wm = *display_wm = *cursor_wm = 0;
4219                 return false;
4220         }
4221
4222         crtc = intel_get_crtc_for_plane(dev, plane);
4223         hdisplay = crtc->mode.hdisplay;
4224         htotal = crtc->mode.htotal;
4225         clock = crtc->mode.clock;
4226         pixel_size = crtc->fb->bits_per_pixel / 8;
4227
4228         line_time_us = (htotal * 1000) / clock;
4229         line_count = (latency_ns / line_time_us + 1000) / 1000;
4230         line_size = hdisplay * pixel_size;
4231
4232         /* Use the minimum of the small and large buffer method for primary */
4233         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4234         large = line_count * line_size;
4235
4236         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4237         *display_wm = entries + display->guard_size;
4238
4239         /*
4240          * Spec says:
4241          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4242          */
4243         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4244
4245         /* calculate the self-refresh watermark for display cursor */
4246         entries = line_count * pixel_size * 64;
4247         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4248         *cursor_wm = entries + cursor->guard_size;
4249
4250         return ironlake_check_srwm(dev, level,
4251                                    *fbc_wm, *display_wm, *cursor_wm,
4252                                    display, cursor);
4253 }
4254
4255 static void ironlake_update_wm(struct drm_device *dev)
4256 {
4257         struct drm_i915_private *dev_priv = dev->dev_private;
4258         int fbc_wm, plane_wm, cursor_wm;
4259         unsigned int enabled;
4260
4261         enabled = 0;
4262         if (g4x_compute_wm0(dev, 0,
4263                             &ironlake_display_wm_info,
4264                             ILK_LP0_PLANE_LATENCY,
4265                             &ironlake_cursor_wm_info,
4266                             ILK_LP0_CURSOR_LATENCY,
4267                             &plane_wm, &cursor_wm)) {
4268                 I915_WRITE(WM0_PIPEA_ILK,
4269                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4270                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4271                               " plane %d, " "cursor: %d\n",
4272                               plane_wm, cursor_wm);
4273                 enabled |= 1;
4274         }
4275
4276         if (g4x_compute_wm0(dev, 1,
4277                             &ironlake_display_wm_info,
4278                             ILK_LP0_PLANE_LATENCY,
4279                             &ironlake_cursor_wm_info,
4280                             ILK_LP0_CURSOR_LATENCY,
4281                             &plane_wm, &cursor_wm)) {
4282                 I915_WRITE(WM0_PIPEB_ILK,
4283                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4284                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4285                               " plane %d, cursor: %d\n",
4286                               plane_wm, cursor_wm);
4287                 enabled |= 2;
4288         }
4289
4290         /*
4291          * Calculate and update the self-refresh watermark only when one
4292          * display plane is used.
4293          */
4294         I915_WRITE(WM3_LP_ILK, 0);
4295         I915_WRITE(WM2_LP_ILK, 0);
4296         I915_WRITE(WM1_LP_ILK, 0);
4297
4298         if (!single_plane_enabled(enabled))
4299                 return;
4300         enabled = ffs(enabled) - 1;
4301
4302         /* WM1 */
4303         if (!ironlake_compute_srwm(dev, 1, enabled,
4304                                    ILK_READ_WM1_LATENCY() * 500,
4305                                    &ironlake_display_srwm_info,
4306                                    &ironlake_cursor_srwm_info,
4307                                    &fbc_wm, &plane_wm, &cursor_wm))
4308                 return;
4309
4310         I915_WRITE(WM1_LP_ILK,
4311                    WM1_LP_SR_EN |
4312                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4313                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4314                    (plane_wm << WM1_LP_SR_SHIFT) |
4315                    cursor_wm);
4316
4317         /* WM2 */
4318         if (!ironlake_compute_srwm(dev, 2, enabled,
4319                                    ILK_READ_WM2_LATENCY() * 500,
4320                                    &ironlake_display_srwm_info,
4321                                    &ironlake_cursor_srwm_info,
4322                                    &fbc_wm, &plane_wm, &cursor_wm))
4323                 return;
4324
4325         I915_WRITE(WM2_LP_ILK,
4326                    WM2_LP_EN |
4327                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4328                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4329                    (plane_wm << WM1_LP_SR_SHIFT) |
4330                    cursor_wm);
4331
4332         /*
4333          * WM3 is unsupported on ILK, probably because we don't have latency
4334          * data for that power state
4335          */
4336 }
4337
4338 static void sandybridge_update_wm(struct drm_device *dev)
4339 {
4340         struct drm_i915_private *dev_priv = dev->dev_private;
4341         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4342         int fbc_wm, plane_wm, cursor_wm;
4343         unsigned int enabled;
4344
4345         enabled = 0;
4346         if (g4x_compute_wm0(dev, 0,
4347                             &sandybridge_display_wm_info, latency,
4348                             &sandybridge_cursor_wm_info, latency,
4349                             &plane_wm, &cursor_wm)) {
4350                 I915_WRITE(WM0_PIPEA_ILK,
4351                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4352                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4353                               " plane %d, " "cursor: %d\n",
4354                               plane_wm, cursor_wm);
4355                 enabled |= 1;
4356         }
4357
4358         if (g4x_compute_wm0(dev, 1,
4359                             &sandybridge_display_wm_info, latency,
4360                             &sandybridge_cursor_wm_info, latency,
4361                             &plane_wm, &cursor_wm)) {
4362                 I915_WRITE(WM0_PIPEB_ILK,
4363                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4364                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4365                               " plane %d, cursor: %d\n",
4366                               plane_wm, cursor_wm);
4367                 enabled |= 2;
4368         }
4369
4370         /*
4371          * Calculate and update the self-refresh watermark only when one
4372          * display plane is used.
4373          *
4374          * SNB support 3 levels of watermark.
4375          *
4376          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4377          * and disabled in the descending order
4378          *
4379          */
4380         I915_WRITE(WM3_LP_ILK, 0);
4381         I915_WRITE(WM2_LP_ILK, 0);
4382         I915_WRITE(WM1_LP_ILK, 0);
4383
4384         if (!single_plane_enabled(enabled))
4385                 return;
4386         enabled = ffs(enabled) - 1;
4387
4388         /* WM1 */
4389         if (!ironlake_compute_srwm(dev, 1, enabled,
4390                                    SNB_READ_WM1_LATENCY() * 500,
4391                                    &sandybridge_display_srwm_info,
4392                                    &sandybridge_cursor_srwm_info,
4393                                    &fbc_wm, &plane_wm, &cursor_wm))
4394                 return;
4395
4396         I915_WRITE(WM1_LP_ILK,
4397                    WM1_LP_SR_EN |
4398                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4399                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4400                    (plane_wm << WM1_LP_SR_SHIFT) |
4401                    cursor_wm);
4402
4403         /* WM2 */
4404         if (!ironlake_compute_srwm(dev, 2, enabled,
4405                                    SNB_READ_WM2_LATENCY() * 500,
4406                                    &sandybridge_display_srwm_info,
4407                                    &sandybridge_cursor_srwm_info,
4408                                    &fbc_wm, &plane_wm, &cursor_wm))
4409                 return;
4410
4411         I915_WRITE(WM2_LP_ILK,
4412                    WM2_LP_EN |
4413                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4414                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4415                    (plane_wm << WM1_LP_SR_SHIFT) |
4416                    cursor_wm);
4417
4418         /* WM3 */
4419         if (!ironlake_compute_srwm(dev, 3, enabled,
4420                                    SNB_READ_WM3_LATENCY() * 500,
4421                                    &sandybridge_display_srwm_info,
4422                                    &sandybridge_cursor_srwm_info,
4423                                    &fbc_wm, &plane_wm, &cursor_wm))
4424                 return;
4425
4426         I915_WRITE(WM3_LP_ILK,
4427                    WM3_LP_EN |
4428                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4429                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4430                    (plane_wm << WM1_LP_SR_SHIFT) |
4431                    cursor_wm);
4432 }
4433
4434 /**
4435  * intel_update_watermarks - update FIFO watermark values based on current modes
4436  *
4437  * Calculate watermark values for the various WM regs based on current mode
4438  * and plane configuration.
4439  *
4440  * There are several cases to deal with here:
4441  *   - normal (i.e. non-self-refresh)
4442  *   - self-refresh (SR) mode
4443  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4444  *   - lines are small relative to FIFO size (buffer can hold more than 2
4445  *     lines), so need to account for TLB latency
4446  *
4447  *   The normal calculation is:
4448  *     watermark = dotclock * bytes per pixel * latency
4449  *   where latency is platform & configuration dependent (we assume pessimal
4450  *   values here).
4451  *
4452  *   The SR calculation is:
4453  *     watermark = (trunc(latency/line time)+1) * surface width *
4454  *       bytes per pixel
4455  *   where
4456  *     line time = htotal / dotclock
4457  *     surface width = hdisplay for normal plane and 64 for cursor
4458  *   and latency is assumed to be high, as above.
4459  *
4460  * The final value programmed to the register should always be rounded up,
4461  * and include an extra 2 entries to account for clock crossings.
4462  *
4463  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4464  * to set the non-SR watermarks to 8.
4465  */
4466 static void intel_update_watermarks(struct drm_device *dev)
4467 {
4468         struct drm_i915_private *dev_priv = dev->dev_private;
4469
4470         if (dev_priv->display.update_wm)
4471                 dev_priv->display.update_wm(dev);
4472 }
4473
4474 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4475 {
4476         return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4477                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4478 }
4479
4480 /**
4481  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4482  * @crtc: CRTC structure
4483  *
4484  * A pipe may be connected to one or more outputs.  Based on the depth of the
4485  * attached framebuffer, choose a good color depth to use on the pipe.
4486  *
4487  * If possible, match the pipe depth to the fb depth.  In some cases, this
4488  * isn't ideal, because the connected output supports a lesser or restricted
4489  * set of depths.  Resolve that here:
4490  *    LVDS typically supports only 6bpc, so clamp down in that case
4491  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4492  *    Displays may support a restricted set as well, check EDID and clamp as
4493  *      appropriate.
4494  *
4495  * RETURNS:
4496  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4497  * true if they don't match).
4498  */
4499 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4500                                          unsigned int *pipe_bpp)
4501 {
4502         struct drm_device *dev = crtc->dev;
4503         struct drm_i915_private *dev_priv = dev->dev_private;
4504         struct drm_encoder *encoder;
4505         struct drm_connector *connector;
4506         unsigned int display_bpc = UINT_MAX, bpc;
4507
4508         /* Walk the encoders & connectors on this crtc, get min bpc */
4509         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4510                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4511
4512                 if (encoder->crtc != crtc)
4513                         continue;
4514
4515                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4516                         unsigned int lvds_bpc;
4517
4518                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4519                             LVDS_A3_POWER_UP)
4520                                 lvds_bpc = 8;
4521                         else
4522                                 lvds_bpc = 6;
4523
4524                         if (lvds_bpc < display_bpc) {
4525                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4526                                 display_bpc = lvds_bpc;
4527                         }
4528                         continue;
4529                 }
4530
4531                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4532                         /* Use VBT settings if we have an eDP panel */
4533                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4534
4535                         if (edp_bpc < display_bpc) {
4536                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4537                                 display_bpc = edp_bpc;
4538                         }
4539                         continue;
4540                 }
4541
4542                 /* Not one of the known troublemakers, check the EDID */
4543                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4544                                     head) {
4545                         if (connector->encoder != encoder)
4546                                 continue;
4547
4548                         if (connector->display_info.bpc < display_bpc) {
4549                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4550                                 display_bpc = connector->display_info.bpc;
4551                         }
4552                 }
4553
4554                 /*
4555                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4556                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4557                  */
4558                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4559                         if (display_bpc > 8 && display_bpc < 12) {
4560                                 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4561                                 display_bpc = 12;
4562                         } else {
4563                                 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4564                                 display_bpc = 8;
4565                         }
4566                 }
4567         }
4568
4569         /*
4570          * We could just drive the pipe at the highest bpc all the time and
4571          * enable dithering as needed, but that costs bandwidth.  So choose
4572          * the minimum value that expresses the full color range of the fb but
4573          * also stays within the max display bpc discovered above.
4574          */
4575
4576         switch (crtc->fb->depth) {
4577         case 8:
4578                 bpc = 8; /* since we go through a colormap */
4579                 break;
4580         case 15:
4581         case 16:
4582                 bpc = 6; /* min is 18bpp */
4583                 break;
4584         case 24:
4585                 bpc = min((unsigned int)8, display_bpc);
4586                 break;
4587         case 30:
4588                 bpc = min((unsigned int)10, display_bpc);
4589                 break;
4590         case 48:
4591                 bpc = min((unsigned int)12, display_bpc);
4592                 break;
4593         default:
4594                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4595                 bpc = min((unsigned int)8, display_bpc);
4596                 break;
4597         }
4598
4599         DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4600                          bpc, display_bpc);
4601
4602         *pipe_bpp = bpc * 3;
4603
4604         return display_bpc != bpc;
4605 }
4606
4607 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4608                               struct drm_display_mode *mode,
4609                               struct drm_display_mode *adjusted_mode,
4610                               int x, int y,
4611                               struct drm_framebuffer *old_fb)
4612 {
4613         struct drm_device *dev = crtc->dev;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4616         int pipe = intel_crtc->pipe;
4617         int plane = intel_crtc->plane;
4618         int refclk, num_connectors = 0;
4619         intel_clock_t clock, reduced_clock;
4620         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4621         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4622         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4623         struct drm_mode_config *mode_config = &dev->mode_config;
4624         struct intel_encoder *encoder;
4625         const intel_limit_t *limit;
4626         int ret;
4627         u32 temp;
4628         u32 lvds_sync = 0;
4629
4630         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4631                 if (encoder->base.crtc != crtc)
4632                         continue;
4633
4634                 switch (encoder->type) {
4635                 case INTEL_OUTPUT_LVDS:
4636                         is_lvds = true;
4637                         break;
4638                 case INTEL_OUTPUT_SDVO:
4639                 case INTEL_OUTPUT_HDMI:
4640                         is_sdvo = true;
4641                         if (encoder->needs_tv_clock)
4642                                 is_tv = true;
4643                         break;
4644                 case INTEL_OUTPUT_DVO:
4645                         is_dvo = true;
4646                         break;
4647                 case INTEL_OUTPUT_TVOUT:
4648                         is_tv = true;
4649                         break;
4650                 case INTEL_OUTPUT_ANALOG:
4651                         is_crt = true;
4652                         break;
4653                 case INTEL_OUTPUT_DISPLAYPORT:
4654                         is_dp = true;
4655                         break;
4656                 }
4657
4658                 num_connectors++;
4659         }
4660
4661         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4662                 refclk = dev_priv->lvds_ssc_freq * 1000;
4663                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4664                               refclk / 1000);
4665         } else if (!IS_GEN2(dev)) {
4666                 refclk = 96000;
4667         } else {
4668                 refclk = 48000;
4669         }
4670
4671         /*
4672          * Returns a set of divisors for the desired target clock with the given
4673          * refclk, or FALSE.  The returned values represent the clock equation:
4674          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4675          */
4676         limit = intel_limit(crtc, refclk);
4677         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4678         if (!ok) {
4679                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4680                 return -EINVAL;
4681         }
4682
4683         /* Ensure that the cursor is valid for the new mode before changing... */
4684         intel_crtc_update_cursor(crtc, true);
4685
4686         if (is_lvds && dev_priv->lvds_downclock_avail) {
4687                 has_reduced_clock = limit->find_pll(limit, crtc,
4688                                                     dev_priv->lvds_downclock,
4689                                                     refclk,
4690                                                     &reduced_clock);
4691                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4692                         /*
4693                          * If the different P is found, it means that we can't
4694                          * switch the display clock by using the FP0/FP1.
4695                          * In such case we will disable the LVDS downclock
4696                          * feature.
4697                          */
4698                         DRM_DEBUG_KMS("Different P is found for "
4699                                       "LVDS clock/downclock\n");
4700                         has_reduced_clock = 0;
4701                 }
4702         }
4703         /* SDVO TV has fixed PLL values depend on its clock range,
4704            this mirrors vbios setting. */
4705         if (is_sdvo && is_tv) {
4706                 if (adjusted_mode->clock >= 100000
4707                     && adjusted_mode->clock < 140500) {
4708                         clock.p1 = 2;
4709                         clock.p2 = 10;
4710                         clock.n = 3;
4711                         clock.m1 = 16;
4712                         clock.m2 = 8;
4713                 } else if (adjusted_mode->clock >= 140500
4714                            && adjusted_mode->clock <= 200000) {
4715                         clock.p1 = 1;
4716                         clock.p2 = 10;
4717                         clock.n = 6;
4718                         clock.m1 = 12;
4719                         clock.m2 = 8;
4720                 }
4721         }
4722
4723         if (IS_PINEVIEW(dev)) {
4724                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4725                 if (has_reduced_clock)
4726                         fp2 = (1 << reduced_clock.n) << 16 |
4727                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4728         } else {
4729                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4730                 if (has_reduced_clock)
4731                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4732                                 reduced_clock.m2;
4733         }
4734
4735         dpll = DPLL_VGA_MODE_DIS;
4736
4737         if (!IS_GEN2(dev)) {
4738                 if (is_lvds)
4739                         dpll |= DPLLB_MODE_LVDS;
4740                 else
4741                         dpll |= DPLLB_MODE_DAC_SERIAL;
4742                 if (is_sdvo) {
4743                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4744                         if (pixel_multiplier > 1) {
4745                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4746                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4747                         }
4748                         dpll |= DPLL_DVO_HIGH_SPEED;
4749                 }
4750                 if (is_dp)
4751                         dpll |= DPLL_DVO_HIGH_SPEED;
4752
4753                 /* compute bitmask from p1 value */
4754                 if (IS_PINEVIEW(dev))
4755                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4756                 else {
4757                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4758                         if (IS_G4X(dev) && has_reduced_clock)
4759                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4760                 }
4761                 switch (clock.p2) {
4762                 case 5:
4763                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4764                         break;
4765                 case 7:
4766                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4767                         break;
4768                 case 10:
4769                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4770                         break;
4771                 case 14:
4772                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4773                         break;
4774                 }
4775                 if (INTEL_INFO(dev)->gen >= 4)
4776                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4777         } else {
4778                 if (is_lvds) {
4779                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4780                 } else {
4781                         if (clock.p1 == 2)
4782                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4783                         else
4784                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4785                         if (clock.p2 == 4)
4786                                 dpll |= PLL_P2_DIVIDE_BY_4;
4787                 }
4788         }
4789
4790         if (is_sdvo && is_tv)
4791                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4792         else if (is_tv)
4793                 /* XXX: just matching BIOS for now */
4794                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4795                 dpll |= 3;
4796         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4797                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4798         else
4799                 dpll |= PLL_REF_INPUT_DREFCLK;
4800
4801         /* setup pipeconf */
4802         pipeconf = I915_READ(PIPECONF(pipe));
4803
4804         /* Set up the display plane register */
4805         dspcntr = DISPPLANE_GAMMA_ENABLE;
4806
4807         /* Ironlake's plane is forced to pipe, bit 24 is to
4808            enable color space conversion */
4809         if (pipe == 0)
4810                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4811         else
4812                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4813
4814         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4815                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4816                  * core speed.
4817                  *
4818                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4819                  * pipe == 0 check?
4820                  */
4821                 if (mode->clock >
4822                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4823                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4824                 else
4825                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4826         }
4827
4828         dpll |= DPLL_VCO_ENABLE;
4829
4830         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4831         drm_mode_debug_printmodeline(mode);
4832
4833         I915_WRITE(FP0(pipe), fp);
4834         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4835
4836         POSTING_READ(DPLL(pipe));
4837         udelay(150);
4838
4839         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4840          * This is an exception to the general rule that mode_set doesn't turn
4841          * things on.
4842          */
4843         if (is_lvds) {
4844                 temp = I915_READ(LVDS);
4845                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4846                 if (pipe == 1) {
4847                         temp |= LVDS_PIPEB_SELECT;
4848                 } else {
4849                         temp &= ~LVDS_PIPEB_SELECT;
4850                 }
4851                 /* set the corresponsding LVDS_BORDER bit */
4852                 temp |= dev_priv->lvds_border_bits;
4853                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4854                  * set the DPLLs for dual-channel mode or not.
4855                  */
4856                 if (clock.p2 == 7)
4857                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4858                 else
4859                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4860
4861                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4862                  * appropriately here, but we need to look more thoroughly into how
4863                  * panels behave in the two modes.
4864                  */
4865                 /* set the dithering flag on LVDS as needed */
4866                 if (INTEL_INFO(dev)->gen >= 4) {
4867                         if (dev_priv->lvds_dither)
4868                                 temp |= LVDS_ENABLE_DITHER;
4869                         else
4870                                 temp &= ~LVDS_ENABLE_DITHER;
4871                 }
4872                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4873                         lvds_sync |= LVDS_HSYNC_POLARITY;
4874                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4875                         lvds_sync |= LVDS_VSYNC_POLARITY;
4876                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4877                     != lvds_sync) {
4878                         char flags[2] = "-+";
4879                         DRM_INFO("Changing LVDS panel from "
4880                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4881                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4882                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4883                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4884                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4885                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4886                         temp |= lvds_sync;
4887                 }
4888                 I915_WRITE(LVDS, temp);
4889         }
4890
4891         if (is_dp) {
4892                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4893         }
4894
4895         I915_WRITE(DPLL(pipe), dpll);
4896
4897         /* Wait for the clocks to stabilize. */
4898         POSTING_READ(DPLL(pipe));
4899         udelay(150);
4900
4901         if (INTEL_INFO(dev)->gen >= 4) {
4902                 temp = 0;
4903                 if (is_sdvo) {
4904                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4905                         if (temp > 1)
4906                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4907                         else
4908                                 temp = 0;
4909                 }
4910                 I915_WRITE(DPLL_MD(pipe), temp);
4911         } else {
4912                 /* The pixel multiplier can only be updated once the
4913                  * DPLL is enabled and the clocks are stable.
4914                  *
4915                  * So write it again.
4916                  */
4917                 I915_WRITE(DPLL(pipe), dpll);
4918         }
4919
4920         intel_crtc->lowfreq_avail = false;
4921         if (is_lvds && has_reduced_clock && i915_powersave) {
4922                 I915_WRITE(FP1(pipe), fp2);
4923                 intel_crtc->lowfreq_avail = true;
4924                 if (HAS_PIPE_CXSR(dev)) {
4925                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4926                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4927                 }
4928         } else {
4929                 I915_WRITE(FP1(pipe), fp);
4930                 if (HAS_PIPE_CXSR(dev)) {
4931                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4932                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4933                 }
4934         }
4935
4936         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4937                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4938                 /* the chip adds 2 halflines automatically */
4939                 adjusted_mode->crtc_vdisplay -= 1;
4940                 adjusted_mode->crtc_vtotal -= 1;
4941                 adjusted_mode->crtc_vblank_start -= 1;
4942                 adjusted_mode->crtc_vblank_end -= 1;
4943                 adjusted_mode->crtc_vsync_end -= 1;
4944                 adjusted_mode->crtc_vsync_start -= 1;
4945         } else
4946                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4947
4948         I915_WRITE(HTOTAL(pipe),
4949                    (adjusted_mode->crtc_hdisplay - 1) |
4950                    ((adjusted_mode->crtc_htotal - 1) << 16));
4951         I915_WRITE(HBLANK(pipe),
4952                    (adjusted_mode->crtc_hblank_start - 1) |
4953                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4954         I915_WRITE(HSYNC(pipe),
4955                    (adjusted_mode->crtc_hsync_start - 1) |
4956                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4957
4958         I915_WRITE(VTOTAL(pipe),
4959                    (adjusted_mode->crtc_vdisplay - 1) |
4960                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4961         I915_WRITE(VBLANK(pipe),
4962                    (adjusted_mode->crtc_vblank_start - 1) |
4963                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4964         I915_WRITE(VSYNC(pipe),
4965                    (adjusted_mode->crtc_vsync_start - 1) |
4966                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4967
4968         /* pipesrc and dspsize control the size that is scaled from,
4969          * which should always be the user's requested size.
4970          */
4971         I915_WRITE(DSPSIZE(plane),
4972                    ((mode->vdisplay - 1) << 16) |
4973                    (mode->hdisplay - 1));
4974         I915_WRITE(DSPPOS(plane), 0);
4975         I915_WRITE(PIPESRC(pipe),
4976                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4977
4978         I915_WRITE(PIPECONF(pipe), pipeconf);
4979         POSTING_READ(PIPECONF(pipe));
4980         intel_enable_pipe(dev_priv, pipe, false);
4981
4982         intel_wait_for_vblank(dev, pipe);
4983
4984         I915_WRITE(DSPCNTR(plane), dspcntr);
4985         POSTING_READ(DSPCNTR(plane));
4986         intel_enable_plane(dev_priv, plane, pipe);
4987
4988         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4989
4990         intel_update_watermarks(dev);
4991
4992         return ret;
4993 }
4994
4995 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4996                                   struct drm_display_mode *mode,
4997                                   struct drm_display_mode *adjusted_mode,
4998                                   int x, int y,
4999                                   struct drm_framebuffer *old_fb)
5000 {
5001         struct drm_device *dev = crtc->dev;
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004         int pipe = intel_crtc->pipe;
5005         int plane = intel_crtc->plane;
5006         int refclk, num_connectors = 0;
5007         intel_clock_t clock, reduced_clock;
5008         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5009         bool ok, has_reduced_clock = false, is_sdvo = false;
5010         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5011         struct intel_encoder *has_edp_encoder = NULL;
5012         struct drm_mode_config *mode_config = &dev->mode_config;
5013         struct intel_encoder *encoder;
5014         const intel_limit_t *limit;
5015         int ret;
5016         struct fdi_m_n m_n = {0};
5017         u32 temp;
5018         u32 lvds_sync = 0;
5019         int target_clock, pixel_multiplier, lane, link_bw, factor;
5020         unsigned int pipe_bpp;
5021         bool dither;
5022
5023         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5024                 if (encoder->base.crtc != crtc)
5025                         continue;
5026
5027                 switch (encoder->type) {
5028                 case INTEL_OUTPUT_LVDS:
5029                         is_lvds = true;
5030                         break;
5031                 case INTEL_OUTPUT_SDVO:
5032                 case INTEL_OUTPUT_HDMI:
5033                         is_sdvo = true;
5034                         if (encoder->needs_tv_clock)
5035                                 is_tv = true;
5036                         break;
5037                 case INTEL_OUTPUT_TVOUT:
5038                         is_tv = true;
5039                         break;
5040                 case INTEL_OUTPUT_ANALOG:
5041                         is_crt = true;
5042                         break;
5043                 case INTEL_OUTPUT_DISPLAYPORT:
5044                         is_dp = true;
5045                         break;
5046                 case INTEL_OUTPUT_EDP:
5047                         has_edp_encoder = encoder;
5048                         break;
5049                 }
5050
5051                 num_connectors++;
5052         }
5053
5054         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5055                 refclk = dev_priv->lvds_ssc_freq * 1000;
5056                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5057                               refclk / 1000);
5058         } else {
5059                 refclk = 96000;
5060                 if (!has_edp_encoder ||
5061                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
5062                         refclk = 120000; /* 120Mhz refclk */
5063         }
5064
5065         /*
5066          * Returns a set of divisors for the desired target clock with the given
5067          * refclk, or FALSE.  The returned values represent the clock equation:
5068          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5069          */
5070         limit = intel_limit(crtc, refclk);
5071         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5072         if (!ok) {
5073                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5074                 return -EINVAL;
5075         }
5076
5077         /* Ensure that the cursor is valid for the new mode before changing... */
5078         intel_crtc_update_cursor(crtc, true);
5079
5080         if (is_lvds && dev_priv->lvds_downclock_avail) {
5081                 has_reduced_clock = limit->find_pll(limit, crtc,
5082                                                     dev_priv->lvds_downclock,
5083                                                     refclk,
5084                                                     &reduced_clock);
5085                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5086                         /*
5087                          * If the different P is found, it means that we can't
5088                          * switch the display clock by using the FP0/FP1.
5089                          * In such case we will disable the LVDS downclock
5090                          * feature.
5091                          */
5092                         DRM_DEBUG_KMS("Different P is found for "
5093                                       "LVDS clock/downclock\n");
5094                         has_reduced_clock = 0;
5095                 }
5096         }
5097         /* SDVO TV has fixed PLL values depend on its clock range,
5098            this mirrors vbios setting. */
5099         if (is_sdvo && is_tv) {
5100                 if (adjusted_mode->clock >= 100000
5101                     && adjusted_mode->clock < 140500) {
5102                         clock.p1 = 2;
5103                         clock.p2 = 10;
5104                         clock.n = 3;
5105                         clock.m1 = 16;
5106                         clock.m2 = 8;
5107                 } else if (adjusted_mode->clock >= 140500
5108                            && adjusted_mode->clock <= 200000) {
5109                         clock.p1 = 1;
5110                         clock.p2 = 10;
5111                         clock.n = 6;
5112                         clock.m1 = 12;
5113                         clock.m2 = 8;
5114                 }
5115         }
5116
5117         /* FDI link */
5118         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5119         lane = 0;
5120         /* CPU eDP doesn't require FDI link, so just set DP M/N
5121            according to current link config */
5122         if (has_edp_encoder &&
5123             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5124                 target_clock = mode->clock;
5125                 intel_edp_link_config(has_edp_encoder,
5126                                       &lane, &link_bw);
5127         } else {
5128                 /* [e]DP over FDI requires target mode clock
5129                    instead of link clock */
5130                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5131                         target_clock = mode->clock;
5132                 else
5133                         target_clock = adjusted_mode->clock;
5134
5135                 /* FDI is a binary signal running at ~2.7GHz, encoding
5136                  * each output octet as 10 bits. The actual frequency
5137                  * is stored as a divider into a 100MHz clock, and the
5138                  * mode pixel clock is stored in units of 1KHz.
5139                  * Hence the bw of each lane in terms of the mode signal
5140                  * is:
5141                  */
5142                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5143         }
5144
5145         /* determine panel color depth */
5146         temp = I915_READ(PIPECONF(pipe));
5147         temp &= ~PIPE_BPC_MASK;
5148         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5149         switch (pipe_bpp) {
5150         case 18:
5151                 temp |= PIPE_6BPC;
5152                 break;
5153         case 24:
5154                 temp |= PIPE_8BPC;
5155                 break;
5156         case 30:
5157                 temp |= PIPE_10BPC;
5158                 break;
5159         case 36:
5160                 temp |= PIPE_12BPC;
5161                 break;
5162         default:
5163                 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5164                 temp |= PIPE_8BPC;
5165                 pipe_bpp = 24;
5166                 break;
5167         }
5168
5169         intel_crtc->bpp = pipe_bpp;
5170         I915_WRITE(PIPECONF(pipe), temp);
5171
5172         if (!lane) {
5173                 /*
5174                  * Account for spread spectrum to avoid
5175                  * oversubscribing the link. Max center spread
5176                  * is 2.5%; use 5% for safety's sake.
5177                  */
5178                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5179                 lane = bps / (link_bw * 8) + 1;
5180         }
5181
5182         intel_crtc->fdi_lanes = lane;
5183
5184         if (pixel_multiplier > 1)
5185                 link_bw *= pixel_multiplier;
5186         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5187                              &m_n);
5188
5189         /* Ironlake: try to setup display ref clock before DPLL
5190          * enabling. This is only under driver's control after
5191          * PCH B stepping, previous chipset stepping should be
5192          * ignoring this setting.
5193          */
5194         temp = I915_READ(PCH_DREF_CONTROL);
5195         /* Always enable nonspread source */
5196         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5197         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5198         temp &= ~DREF_SSC_SOURCE_MASK;
5199         temp |= DREF_SSC_SOURCE_ENABLE;
5200         I915_WRITE(PCH_DREF_CONTROL, temp);
5201
5202         POSTING_READ(PCH_DREF_CONTROL);
5203         udelay(200);
5204
5205         if (has_edp_encoder) {
5206                 if (intel_panel_use_ssc(dev_priv)) {
5207                         temp |= DREF_SSC1_ENABLE;
5208                         I915_WRITE(PCH_DREF_CONTROL, temp);
5209
5210                         POSTING_READ(PCH_DREF_CONTROL);
5211                         udelay(200);
5212                 }
5213                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5214
5215                 /* Enable CPU source on CPU attached eDP */
5216                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5217                         if (intel_panel_use_ssc(dev_priv))
5218                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5219                         else
5220                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5221                 } else {
5222                         /* Enable SSC on PCH eDP if needed */
5223                         if (intel_panel_use_ssc(dev_priv)) {
5224                                 DRM_ERROR("enabling SSC on PCH\n");
5225                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5226                         }
5227                 }
5228                 I915_WRITE(PCH_DREF_CONTROL, temp);
5229                 POSTING_READ(PCH_DREF_CONTROL);
5230                 udelay(200);
5231         }
5232
5233         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5234         if (has_reduced_clock)
5235                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5236                         reduced_clock.m2;
5237
5238         /* Enable autotuning of the PLL clock (if permissible) */
5239         factor = 21;
5240         if (is_lvds) {
5241                 if ((intel_panel_use_ssc(dev_priv) &&
5242                      dev_priv->lvds_ssc_freq == 100) ||
5243                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5244                         factor = 25;
5245         } else if (is_sdvo && is_tv)
5246                 factor = 20;
5247
5248         if (clock.m1 < factor * clock.n)
5249                 fp |= FP_CB_TUNE;
5250
5251         dpll = 0;
5252
5253         if (is_lvds)
5254                 dpll |= DPLLB_MODE_LVDS;
5255         else
5256                 dpll |= DPLLB_MODE_DAC_SERIAL;
5257         if (is_sdvo) {
5258                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5259                 if (pixel_multiplier > 1) {
5260                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5261                 }
5262                 dpll |= DPLL_DVO_HIGH_SPEED;
5263         }
5264         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5265                 dpll |= DPLL_DVO_HIGH_SPEED;
5266
5267         /* compute bitmask from p1 value */
5268         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5269         /* also FPA1 */
5270         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5271
5272         switch (clock.p2) {
5273         case 5:
5274                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5275                 break;
5276         case 7:
5277                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5278                 break;
5279         case 10:
5280                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5281                 break;
5282         case 14:
5283                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5284                 break;
5285         }
5286
5287         if (is_sdvo && is_tv)
5288                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5289         else if (is_tv)
5290                 /* XXX: just matching BIOS for now */
5291                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5292                 dpll |= 3;
5293         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5294                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5295         else
5296                 dpll |= PLL_REF_INPUT_DREFCLK;
5297
5298         /* setup pipeconf */
5299         pipeconf = I915_READ(PIPECONF(pipe));
5300
5301         /* Set up the display plane register */
5302         dspcntr = DISPPLANE_GAMMA_ENABLE;
5303
5304         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5305         drm_mode_debug_printmodeline(mode);
5306
5307         /* PCH eDP needs FDI, but CPU eDP does not */
5308         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5309                 I915_WRITE(PCH_FP0(pipe), fp);
5310                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5311
5312                 POSTING_READ(PCH_DPLL(pipe));
5313                 udelay(150);
5314         }
5315
5316         /* enable transcoder DPLL */
5317         if (HAS_PCH_CPT(dev)) {
5318                 temp = I915_READ(PCH_DPLL_SEL);
5319                 switch (pipe) {
5320                 case 0:
5321                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5322                         break;
5323                 case 1:
5324                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5325                         break;
5326                 case 2:
5327                         /* FIXME: manage transcoder PLLs? */
5328                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5329                         break;
5330                 default:
5331                         BUG();
5332                 }
5333                 I915_WRITE(PCH_DPLL_SEL, temp);
5334
5335                 POSTING_READ(PCH_DPLL_SEL);
5336                 udelay(150);
5337         }
5338
5339         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5340          * This is an exception to the general rule that mode_set doesn't turn
5341          * things on.
5342          */
5343         if (is_lvds) {
5344                 temp = I915_READ(PCH_LVDS);
5345                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5346                 if (pipe == 1) {
5347                         if (HAS_PCH_CPT(dev))
5348                                 temp |= PORT_TRANS_B_SEL_CPT;
5349                         else
5350                                 temp |= LVDS_PIPEB_SELECT;
5351                 } else {
5352                         if (HAS_PCH_CPT(dev))
5353                                 temp &= ~PORT_TRANS_SEL_MASK;
5354                         else
5355                                 temp &= ~LVDS_PIPEB_SELECT;
5356                 }
5357                 /* set the corresponsding LVDS_BORDER bit */
5358                 temp |= dev_priv->lvds_border_bits;
5359                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5360                  * set the DPLLs for dual-channel mode or not.
5361                  */
5362                 if (clock.p2 == 7)
5363                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5364                 else
5365                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5366
5367                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5368                  * appropriately here, but we need to look more thoroughly into how
5369                  * panels behave in the two modes.
5370                  */
5371                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5372                         lvds_sync |= LVDS_HSYNC_POLARITY;
5373                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5374                         lvds_sync |= LVDS_VSYNC_POLARITY;
5375                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5376                     != lvds_sync) {
5377                         char flags[2] = "-+";
5378                         DRM_INFO("Changing LVDS panel from "
5379                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5380                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5381                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5382                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5383                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5384                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5385                         temp |= lvds_sync;
5386                 }
5387                 I915_WRITE(PCH_LVDS, temp);
5388         }
5389
5390         pipeconf &= ~PIPECONF_DITHER_EN;
5391         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5392         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5393                 pipeconf |= PIPECONF_DITHER_EN;
5394                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5395         }
5396         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5397                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5398         } else {
5399                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5400                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5401                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5402                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5403                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5404         }
5405
5406         if (!has_edp_encoder ||
5407             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5408                 I915_WRITE(PCH_DPLL(pipe), dpll);
5409
5410                 /* Wait for the clocks to stabilize. */
5411                 POSTING_READ(PCH_DPLL(pipe));
5412                 udelay(150);
5413
5414                 /* The pixel multiplier can only be updated once the
5415                  * DPLL is enabled and the clocks are stable.
5416                  *
5417                  * So write it again.
5418                  */
5419                 I915_WRITE(PCH_DPLL(pipe), dpll);
5420         }
5421
5422         intel_crtc->lowfreq_avail = false;
5423         if (is_lvds && has_reduced_clock && i915_powersave) {
5424                 I915_WRITE(PCH_FP1(pipe), fp2);
5425                 intel_crtc->lowfreq_avail = true;
5426                 if (HAS_PIPE_CXSR(dev)) {
5427                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5428                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5429                 }
5430         } else {
5431                 I915_WRITE(PCH_FP1(pipe), fp);
5432                 if (HAS_PIPE_CXSR(dev)) {
5433                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5434                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5435                 }
5436         }
5437
5438         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5439                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5440                 /* the chip adds 2 halflines automatically */
5441                 adjusted_mode->crtc_vdisplay -= 1;
5442                 adjusted_mode->crtc_vtotal -= 1;
5443                 adjusted_mode->crtc_vblank_start -= 1;
5444                 adjusted_mode->crtc_vblank_end -= 1;
5445                 adjusted_mode->crtc_vsync_end -= 1;
5446                 adjusted_mode->crtc_vsync_start -= 1;
5447         } else
5448                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5449
5450         I915_WRITE(HTOTAL(pipe),
5451                    (adjusted_mode->crtc_hdisplay - 1) |
5452                    ((adjusted_mode->crtc_htotal - 1) << 16));
5453         I915_WRITE(HBLANK(pipe),
5454                    (adjusted_mode->crtc_hblank_start - 1) |
5455                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5456         I915_WRITE(HSYNC(pipe),
5457                    (adjusted_mode->crtc_hsync_start - 1) |
5458                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5459
5460         I915_WRITE(VTOTAL(pipe),
5461                    (adjusted_mode->crtc_vdisplay - 1) |
5462                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5463         I915_WRITE(VBLANK(pipe),
5464                    (adjusted_mode->crtc_vblank_start - 1) |
5465                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5466         I915_WRITE(VSYNC(pipe),
5467                    (adjusted_mode->crtc_vsync_start - 1) |
5468                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5469
5470         /* pipesrc controls the size that is scaled from, which should
5471          * always be the user's requested size.
5472          */
5473         I915_WRITE(PIPESRC(pipe),
5474                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5475
5476         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5477         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5478         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5479         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5480
5481         if (has_edp_encoder &&
5482             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5483                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5484         }
5485
5486         I915_WRITE(PIPECONF(pipe), pipeconf);
5487         POSTING_READ(PIPECONF(pipe));
5488
5489         intel_wait_for_vblank(dev, pipe);
5490
5491         if (IS_GEN5(dev)) {
5492                 /* enable address swizzle for tiling buffer */
5493                 temp = I915_READ(DISP_ARB_CTL);
5494                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5495         }
5496
5497         I915_WRITE(DSPCNTR(plane), dspcntr);
5498         POSTING_READ(DSPCNTR(plane));
5499
5500         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5501
5502         intel_update_watermarks(dev);
5503
5504         return ret;
5505 }
5506
5507 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5508                                struct drm_display_mode *mode,
5509                                struct drm_display_mode *adjusted_mode,
5510                                int x, int y,
5511                                struct drm_framebuffer *old_fb)
5512 {
5513         struct drm_device *dev = crtc->dev;
5514         struct drm_i915_private *dev_priv = dev->dev_private;
5515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5516         int pipe = intel_crtc->pipe;
5517         int ret;
5518
5519         drm_vblank_pre_modeset(dev, pipe);
5520
5521         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5522                                               x, y, old_fb);
5523
5524         drm_vblank_post_modeset(dev, pipe);
5525
5526         return ret;
5527 }
5528
5529 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5530 void intel_crtc_load_lut(struct drm_crtc *crtc)
5531 {
5532         struct drm_device *dev = crtc->dev;
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5535         int palreg = PALETTE(intel_crtc->pipe);
5536         int i;
5537
5538         /* The clocks have to be on to load the palette. */
5539         if (!crtc->enabled)
5540                 return;
5541
5542         /* use legacy palette for Ironlake */
5543         if (HAS_PCH_SPLIT(dev))
5544                 palreg = LGC_PALETTE(intel_crtc->pipe);
5545
5546         for (i = 0; i < 256; i++) {
5547                 I915_WRITE(palreg + 4 * i,
5548                            (intel_crtc->lut_r[i] << 16) |
5549                            (intel_crtc->lut_g[i] << 8) |
5550                            intel_crtc->lut_b[i]);
5551         }
5552 }
5553
5554 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5555 {
5556         struct drm_device *dev = crtc->dev;
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5559         bool visible = base != 0;
5560         u32 cntl;
5561
5562         if (intel_crtc->cursor_visible == visible)
5563                 return;
5564
5565         cntl = I915_READ(_CURACNTR);
5566         if (visible) {
5567                 /* On these chipsets we can only modify the base whilst
5568                  * the cursor is disabled.
5569                  */
5570                 I915_WRITE(_CURABASE, base);
5571
5572                 cntl &= ~(CURSOR_FORMAT_MASK);
5573                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5574                 cntl |= CURSOR_ENABLE |
5575                         CURSOR_GAMMA_ENABLE |
5576                         CURSOR_FORMAT_ARGB;
5577         } else
5578                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5579         I915_WRITE(_CURACNTR, cntl);
5580
5581         intel_crtc->cursor_visible = visible;
5582 }
5583
5584 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5585 {
5586         struct drm_device *dev = crtc->dev;
5587         struct drm_i915_private *dev_priv = dev->dev_private;
5588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5589         int pipe = intel_crtc->pipe;
5590         bool visible = base != 0;
5591
5592         if (intel_crtc->cursor_visible != visible) {
5593                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5594                 if (base) {
5595                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5596                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5597                         cntl |= pipe << 28; /* Connect to correct pipe */
5598                 } else {
5599                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5600                         cntl |= CURSOR_MODE_DISABLE;
5601                 }
5602                 I915_WRITE(CURCNTR(pipe), cntl);
5603
5604                 intel_crtc->cursor_visible = visible;
5605         }
5606         /* and commit changes on next vblank */
5607         I915_WRITE(CURBASE(pipe), base);
5608 }
5609
5610 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5611 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5612                                      bool on)
5613 {
5614         struct drm_device *dev = crtc->dev;
5615         struct drm_i915_private *dev_priv = dev->dev_private;
5616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5617         int pipe = intel_crtc->pipe;
5618         int x = intel_crtc->cursor_x;
5619         int y = intel_crtc->cursor_y;
5620         u32 base, pos;
5621         bool visible;
5622
5623         pos = 0;
5624
5625         if (on && crtc->enabled && crtc->fb) {
5626                 base = intel_crtc->cursor_addr;
5627                 if (x > (int) crtc->fb->width)
5628                         base = 0;
5629
5630                 if (y > (int) crtc->fb->height)
5631                         base = 0;
5632         } else
5633                 base = 0;
5634
5635         if (x < 0) {
5636                 if (x + intel_crtc->cursor_width < 0)
5637                         base = 0;
5638
5639                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5640                 x = -x;
5641         }
5642         pos |= x << CURSOR_X_SHIFT;
5643
5644         if (y < 0) {
5645                 if (y + intel_crtc->cursor_height < 0)
5646                         base = 0;
5647
5648                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5649                 y = -y;
5650         }
5651         pos |= y << CURSOR_Y_SHIFT;
5652
5653         visible = base != 0;
5654         if (!visible && !intel_crtc->cursor_visible)
5655                 return;
5656
5657         I915_WRITE(CURPOS(pipe), pos);
5658         if (IS_845G(dev) || IS_I865G(dev))
5659                 i845_update_cursor(crtc, base);
5660         else
5661                 i9xx_update_cursor(crtc, base);
5662
5663         if (visible)
5664                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5665 }
5666
5667 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5668                                  struct drm_file *file,
5669                                  uint32_t handle,
5670                                  uint32_t width, uint32_t height)
5671 {
5672         struct drm_device *dev = crtc->dev;
5673         struct drm_i915_private *dev_priv = dev->dev_private;
5674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5675         struct drm_i915_gem_object *obj;
5676         uint32_t addr;
5677         int ret;
5678
5679         DRM_DEBUG_KMS("\n");
5680
5681         /* if we want to turn off the cursor ignore width and height */
5682         if (!handle) {
5683                 DRM_DEBUG_KMS("cursor off\n");
5684                 addr = 0;
5685                 obj = NULL;
5686                 mutex_lock(&dev->struct_mutex);
5687                 goto finish;
5688         }
5689
5690         /* Currently we only support 64x64 cursors */
5691         if (width != 64 || height != 64) {
5692                 DRM_ERROR("we currently only support 64x64 cursors\n");
5693                 return -EINVAL;
5694         }
5695
5696         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5697         if (&obj->base == NULL)
5698                 return -ENOENT;
5699
5700         if (obj->base.size < width * height * 4) {
5701                 DRM_ERROR("buffer is to small\n");
5702                 ret = -ENOMEM;
5703                 goto fail;
5704         }
5705
5706         /* we only need to pin inside GTT if cursor is non-phy */
5707         mutex_lock(&dev->struct_mutex);
5708         if (!dev_priv->info->cursor_needs_physical) {
5709                 if (obj->tiling_mode) {
5710                         DRM_ERROR("cursor cannot be tiled\n");
5711                         ret = -EINVAL;
5712                         goto fail_locked;
5713                 }
5714
5715                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5716                 if (ret) {
5717                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5718                         goto fail_locked;
5719                 }
5720
5721                 ret = i915_gem_object_put_fence(obj);
5722                 if (ret) {
5723                         DRM_ERROR("failed to release fence for cursor");
5724                         goto fail_unpin;
5725                 }
5726
5727                 addr = obj->gtt_offset;
5728         } else {
5729                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5730                 ret = i915_gem_attach_phys_object(dev, obj,
5731                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5732                                                   align);
5733                 if (ret) {
5734                         DRM_ERROR("failed to attach phys object\n");
5735                         goto fail_locked;
5736                 }
5737                 addr = obj->phys_obj->handle->busaddr;
5738         }
5739
5740         if (IS_GEN2(dev))
5741                 I915_WRITE(CURSIZE, (height << 12) | width);
5742
5743  finish:
5744         if (intel_crtc->cursor_bo) {
5745                 if (dev_priv->info->cursor_needs_physical) {
5746                         if (intel_crtc->cursor_bo != obj)
5747                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5748                 } else
5749                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5750                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5751         }
5752
5753         mutex_unlock(&dev->struct_mutex);
5754
5755         intel_crtc->cursor_addr = addr;
5756         intel_crtc->cursor_bo = obj;
5757         intel_crtc->cursor_width = width;
5758         intel_crtc->cursor_height = height;
5759
5760         intel_crtc_update_cursor(crtc, true);
5761
5762         return 0;
5763 fail_unpin:
5764         i915_gem_object_unpin(obj);
5765 fail_locked:
5766         mutex_unlock(&dev->struct_mutex);
5767 fail:
5768         drm_gem_object_unreference_unlocked(&obj->base);
5769         return ret;
5770 }
5771
5772 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5773 {
5774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5775
5776         intel_crtc->cursor_x = x;
5777         intel_crtc->cursor_y = y;
5778
5779         intel_crtc_update_cursor(crtc, true);
5780
5781         return 0;
5782 }
5783
5784 /** Sets the color ramps on behalf of RandR */
5785 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5786                                  u16 blue, int regno)
5787 {
5788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5789
5790         intel_crtc->lut_r[regno] = red >> 8;
5791         intel_crtc->lut_g[regno] = green >> 8;
5792         intel_crtc->lut_b[regno] = blue >> 8;
5793 }
5794
5795 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5796                              u16 *blue, int regno)
5797 {
5798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799
5800         *red = intel_crtc->lut_r[regno] << 8;
5801         *green = intel_crtc->lut_g[regno] << 8;
5802         *blue = intel_crtc->lut_b[regno] << 8;
5803 }
5804
5805 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5806                                  u16 *blue, uint32_t start, uint32_t size)
5807 {
5808         int end = (start + size > 256) ? 256 : start + size, i;
5809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5810
5811         for (i = start; i < end; i++) {
5812                 intel_crtc->lut_r[i] = red[i] >> 8;
5813                 intel_crtc->lut_g[i] = green[i] >> 8;
5814                 intel_crtc->lut_b[i] = blue[i] >> 8;
5815         }
5816
5817         intel_crtc_load_lut(crtc);
5818 }
5819
5820 /**
5821  * Get a pipe with a simple mode set on it for doing load-based monitor
5822  * detection.
5823  *
5824  * It will be up to the load-detect code to adjust the pipe as appropriate for
5825  * its requirements.  The pipe will be connected to no other encoders.
5826  *
5827  * Currently this code will only succeed if there is a pipe with no encoders
5828  * configured for it.  In the future, it could choose to temporarily disable
5829  * some outputs to free up a pipe for its use.
5830  *
5831  * \return crtc, or NULL if no pipes are available.
5832  */
5833
5834 /* VESA 640x480x72Hz mode to set on the pipe */
5835 static struct drm_display_mode load_detect_mode = {
5836         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5837                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5838 };
5839
5840 static struct drm_framebuffer *
5841 intel_framebuffer_create(struct drm_device *dev,
5842                          struct drm_mode_fb_cmd *mode_cmd,
5843                          struct drm_i915_gem_object *obj)
5844 {
5845         struct intel_framebuffer *intel_fb;
5846         int ret;
5847
5848         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5849         if (!intel_fb) {
5850                 drm_gem_object_unreference_unlocked(&obj->base);
5851                 return ERR_PTR(-ENOMEM);
5852         }
5853
5854         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5855         if (ret) {
5856                 drm_gem_object_unreference_unlocked(&obj->base);
5857                 kfree(intel_fb);
5858                 return ERR_PTR(ret);
5859         }
5860
5861         return &intel_fb->base;
5862 }
5863
5864 static u32
5865 intel_framebuffer_pitch_for_width(int width, int bpp)
5866 {
5867         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5868         return ALIGN(pitch, 64);
5869 }
5870
5871 static u32
5872 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5873 {
5874         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5875         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5876 }
5877
5878 static struct drm_framebuffer *
5879 intel_framebuffer_create_for_mode(struct drm_device *dev,
5880                                   struct drm_display_mode *mode,
5881                                   int depth, int bpp)
5882 {
5883         struct drm_i915_gem_object *obj;
5884         struct drm_mode_fb_cmd mode_cmd;
5885
5886         obj = i915_gem_alloc_object(dev,
5887                                     intel_framebuffer_size_for_mode(mode, bpp));
5888         if (obj == NULL)
5889                 return ERR_PTR(-ENOMEM);
5890
5891         mode_cmd.width = mode->hdisplay;
5892         mode_cmd.height = mode->vdisplay;
5893         mode_cmd.depth = depth;
5894         mode_cmd.bpp = bpp;
5895         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5896
5897         return intel_framebuffer_create(dev, &mode_cmd, obj);
5898 }
5899
5900 static struct drm_framebuffer *
5901 mode_fits_in_fbdev(struct drm_device *dev,
5902                    struct drm_display_mode *mode)
5903 {
5904         struct drm_i915_private *dev_priv = dev->dev_private;
5905         struct drm_i915_gem_object *obj;
5906         struct drm_framebuffer *fb;
5907
5908         if (dev_priv->fbdev == NULL)
5909                 return NULL;
5910
5911         obj = dev_priv->fbdev->ifb.obj;
5912         if (obj == NULL)
5913                 return NULL;
5914
5915         fb = &dev_priv->fbdev->ifb.base;
5916         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5917                                                           fb->bits_per_pixel))
5918                 return NULL;
5919
5920         if (obj->base.size < mode->vdisplay * fb->pitch)
5921                 return NULL;
5922
5923         return fb;
5924 }
5925
5926 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5927                                 struct drm_connector *connector,
5928                                 struct drm_display_mode *mode,
5929                                 struct intel_load_detect_pipe *old)
5930 {
5931         struct intel_crtc *intel_crtc;
5932         struct drm_crtc *possible_crtc;
5933         struct drm_encoder *encoder = &intel_encoder->base;
5934         struct drm_crtc *crtc = NULL;
5935         struct drm_device *dev = encoder->dev;
5936         struct drm_framebuffer *old_fb;
5937         int i = -1;
5938
5939         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5940                       connector->base.id, drm_get_connector_name(connector),
5941                       encoder->base.id, drm_get_encoder_name(encoder));
5942
5943         /*
5944          * Algorithm gets a little messy:
5945          *
5946          *   - if the connector already has an assigned crtc, use it (but make
5947          *     sure it's on first)
5948          *
5949          *   - try to find the first unused crtc that can drive this connector,
5950          *     and use that if we find one
5951          */
5952
5953         /* See if we already have a CRTC for this connector */
5954         if (encoder->crtc) {
5955                 crtc = encoder->crtc;
5956
5957                 intel_crtc = to_intel_crtc(crtc);
5958                 old->dpms_mode = intel_crtc->dpms_mode;
5959                 old->load_detect_temp = false;
5960
5961                 /* Make sure the crtc and connector are running */
5962                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5963                         struct drm_encoder_helper_funcs *encoder_funcs;
5964                         struct drm_crtc_helper_funcs *crtc_funcs;
5965
5966                         crtc_funcs = crtc->helper_private;
5967                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5968
5969                         encoder_funcs = encoder->helper_private;
5970                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5971                 }
5972
5973                 return true;
5974         }
5975
5976         /* Find an unused one (if possible) */
5977         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5978                 i++;
5979                 if (!(encoder->possible_crtcs & (1 << i)))
5980                         continue;
5981                 if (!possible_crtc->enabled) {
5982                         crtc = possible_crtc;
5983                         break;
5984                 }
5985         }
5986
5987         /*
5988          * If we didn't find an unused CRTC, don't use any.
5989          */
5990         if (!crtc) {
5991                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5992                 return false;
5993         }
5994
5995         encoder->crtc = crtc;
5996         connector->encoder = encoder;
5997
5998         intel_crtc = to_intel_crtc(crtc);
5999         old->dpms_mode = intel_crtc->dpms_mode;
6000         old->load_detect_temp = true;
6001         old->release_fb = NULL;
6002
6003         if (!mode)
6004                 mode = &load_detect_mode;
6005
6006         old_fb = crtc->fb;
6007
6008         /* We need a framebuffer large enough to accommodate all accesses
6009          * that the plane may generate whilst we perform load detection.
6010          * We can not rely on the fbcon either being present (we get called
6011          * during its initialisation to detect all boot displays, or it may
6012          * not even exist) or that it is large enough to satisfy the
6013          * requested mode.
6014          */
6015         crtc->fb = mode_fits_in_fbdev(dev, mode);
6016         if (crtc->fb == NULL) {
6017                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6018                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6019                 old->release_fb = crtc->fb;
6020         } else
6021                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6022         if (IS_ERR(crtc->fb)) {
6023                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6024                 crtc->fb = old_fb;
6025                 return false;
6026         }
6027
6028         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6029                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6030                 if (old->release_fb)
6031                         old->release_fb->funcs->destroy(old->release_fb);
6032                 crtc->fb = old_fb;
6033                 return false;
6034         }
6035
6036         /* let the connector get through one full cycle before testing */
6037         intel_wait_for_vblank(dev, intel_crtc->pipe);
6038
6039         return true;
6040 }
6041
6042 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6043                                     struct drm_connector *connector,
6044                                     struct intel_load_detect_pipe *old)
6045 {
6046         struct drm_encoder *encoder = &intel_encoder->base;
6047         struct drm_device *dev = encoder->dev;
6048         struct drm_crtc *crtc = encoder->crtc;
6049         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6050         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6051
6052         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6053                       connector->base.id, drm_get_connector_name(connector),
6054                       encoder->base.id, drm_get_encoder_name(encoder));
6055
6056         if (old->load_detect_temp) {
6057                 connector->encoder = NULL;
6058                 drm_helper_disable_unused_functions(dev);
6059
6060                 if (old->release_fb)
6061                         old->release_fb->funcs->destroy(old->release_fb);
6062
6063                 return;
6064         }
6065
6066         /* Switch crtc and encoder back off if necessary */
6067         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6068                 encoder_funcs->dpms(encoder, old->dpms_mode);
6069                 crtc_funcs->dpms(crtc, old->dpms_mode);
6070         }
6071 }
6072
6073 /* Returns the clock of the currently programmed mode of the given pipe. */
6074 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6075 {
6076         struct drm_i915_private *dev_priv = dev->dev_private;
6077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6078         int pipe = intel_crtc->pipe;
6079         u32 dpll = I915_READ(DPLL(pipe));
6080         u32 fp;
6081         intel_clock_t clock;
6082
6083         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6084                 fp = I915_READ(FP0(pipe));
6085         else
6086                 fp = I915_READ(FP1(pipe));
6087
6088         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6089         if (IS_PINEVIEW(dev)) {
6090                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6091                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6092         } else {
6093                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6094                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6095         }
6096
6097         if (!IS_GEN2(dev)) {
6098                 if (IS_PINEVIEW(dev))
6099                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6100                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6101                 else
6102                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6103                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6104
6105                 switch (dpll & DPLL_MODE_MASK) {
6106                 case DPLLB_MODE_DAC_SERIAL:
6107                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6108                                 5 : 10;
6109                         break;
6110                 case DPLLB_MODE_LVDS:
6111                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6112                                 7 : 14;
6113                         break;
6114                 default:
6115                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6116                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6117                         return 0;
6118                 }
6119
6120                 /* XXX: Handle the 100Mhz refclk */
6121                 intel_clock(dev, 96000, &clock);
6122         } else {
6123                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6124
6125                 if (is_lvds) {
6126                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6127                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6128                         clock.p2 = 14;
6129
6130                         if ((dpll & PLL_REF_INPUT_MASK) ==
6131                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6132                                 /* XXX: might not be 66MHz */
6133                                 intel_clock(dev, 66000, &clock);
6134                         } else
6135                                 intel_clock(dev, 48000, &clock);
6136                 } else {
6137                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6138                                 clock.p1 = 2;
6139                         else {
6140                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6141                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6142                         }
6143                         if (dpll & PLL_P2_DIVIDE_BY_4)
6144                                 clock.p2 = 4;
6145                         else
6146                                 clock.p2 = 2;
6147
6148                         intel_clock(dev, 48000, &clock);
6149                 }
6150         }
6151
6152         /* XXX: It would be nice to validate the clocks, but we can't reuse
6153          * i830PllIsValid() because it relies on the xf86_config connector
6154          * configuration being accurate, which it isn't necessarily.
6155          */
6156
6157         return clock.dot;
6158 }
6159
6160 /** Returns the currently programmed mode of the given pipe. */
6161 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6162                                              struct drm_crtc *crtc)
6163 {
6164         struct drm_i915_private *dev_priv = dev->dev_private;
6165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6166         int pipe = intel_crtc->pipe;
6167         struct drm_display_mode *mode;
6168         int htot = I915_READ(HTOTAL(pipe));
6169         int hsync = I915_READ(HSYNC(pipe));
6170         int vtot = I915_READ(VTOTAL(pipe));
6171         int vsync = I915_READ(VSYNC(pipe));
6172
6173         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6174         if (!mode)
6175                 return NULL;
6176
6177         mode->clock = intel_crtc_clock_get(dev, crtc);
6178         mode->hdisplay = (htot & 0xffff) + 1;
6179         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6180         mode->hsync_start = (hsync & 0xffff) + 1;
6181         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6182         mode->vdisplay = (vtot & 0xffff) + 1;
6183         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6184         mode->vsync_start = (vsync & 0xffff) + 1;
6185         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6186
6187         drm_mode_set_name(mode);
6188         drm_mode_set_crtcinfo(mode, 0);
6189
6190         return mode;
6191 }
6192
6193 #define GPU_IDLE_TIMEOUT 500 /* ms */
6194
6195 /* When this timer fires, we've been idle for awhile */
6196 static void intel_gpu_idle_timer(unsigned long arg)
6197 {
6198         struct drm_device *dev = (struct drm_device *)arg;
6199         drm_i915_private_t *dev_priv = dev->dev_private;
6200
6201         if (!list_empty(&dev_priv->mm.active_list)) {
6202                 /* Still processing requests, so just re-arm the timer. */
6203                 mod_timer(&dev_priv->idle_timer, jiffies +
6204                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6205                 return;
6206         }
6207
6208         dev_priv->busy = false;
6209         queue_work(dev_priv->wq, &dev_priv->idle_work);
6210 }
6211
6212 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6213
6214 static void intel_crtc_idle_timer(unsigned long arg)
6215 {
6216         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6217         struct drm_crtc *crtc = &intel_crtc->base;
6218         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6219         struct intel_framebuffer *intel_fb;
6220
6221         intel_fb = to_intel_framebuffer(crtc->fb);
6222         if (intel_fb && intel_fb->obj->active) {
6223                 /* The framebuffer is still being accessed by the GPU. */
6224                 mod_timer(&intel_crtc->idle_timer, jiffies +
6225                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6226                 return;
6227         }
6228
6229         intel_crtc->busy = false;
6230         queue_work(dev_priv->wq, &dev_priv->idle_work);
6231 }
6232
6233 static void intel_increase_pllclock(struct drm_crtc *crtc)
6234 {
6235         struct drm_device *dev = crtc->dev;
6236         drm_i915_private_t *dev_priv = dev->dev_private;
6237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6238         int pipe = intel_crtc->pipe;
6239         int dpll_reg = DPLL(pipe);
6240         int dpll;
6241
6242         if (HAS_PCH_SPLIT(dev))
6243                 return;
6244
6245         if (!dev_priv->lvds_downclock_avail)
6246                 return;
6247
6248         dpll = I915_READ(dpll_reg);
6249         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6250                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6251
6252                 /* Unlock panel regs */
6253                 I915_WRITE(PP_CONTROL,
6254                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6255
6256                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6257                 I915_WRITE(dpll_reg, dpll);
6258                 intel_wait_for_vblank(dev, pipe);
6259
6260                 dpll = I915_READ(dpll_reg);
6261                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6262                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6263
6264                 /* ...and lock them again */
6265                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6266         }
6267
6268         /* Schedule downclock */
6269         mod_timer(&intel_crtc->idle_timer, jiffies +
6270                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6271 }
6272
6273 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6274 {
6275         struct drm_device *dev = crtc->dev;
6276         drm_i915_private_t *dev_priv = dev->dev_private;
6277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6278         int pipe = intel_crtc->pipe;
6279         int dpll_reg = DPLL(pipe);
6280         int dpll = I915_READ(dpll_reg);
6281
6282         if (HAS_PCH_SPLIT(dev))
6283                 return;
6284
6285         if (!dev_priv->lvds_downclock_avail)
6286                 return;
6287
6288         /*
6289          * Since this is called by a timer, we should never get here in
6290          * the manual case.
6291          */
6292         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6293                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6294
6295                 /* Unlock panel regs */
6296                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6297                            PANEL_UNLOCK_REGS);
6298
6299                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6300                 I915_WRITE(dpll_reg, dpll);
6301                 intel_wait_for_vblank(dev, pipe);
6302                 dpll = I915_READ(dpll_reg);
6303                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6304                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6305
6306                 /* ...and lock them again */
6307                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6308         }
6309
6310 }
6311
6312 /**
6313  * intel_idle_update - adjust clocks for idleness
6314  * @work: work struct
6315  *
6316  * Either the GPU or display (or both) went idle.  Check the busy status
6317  * here and adjust the CRTC and GPU clocks as necessary.
6318  */
6319 static void intel_idle_update(struct work_struct *work)
6320 {
6321         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6322                                                     idle_work);
6323         struct drm_device *dev = dev_priv->dev;
6324         struct drm_crtc *crtc;
6325         struct intel_crtc *intel_crtc;
6326
6327         if (!i915_powersave)
6328                 return;
6329
6330         mutex_lock(&dev->struct_mutex);
6331
6332         i915_update_gfx_val(dev_priv);
6333
6334         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6335                 /* Skip inactive CRTCs */
6336                 if (!crtc->fb)
6337                         continue;
6338
6339                 intel_crtc = to_intel_crtc(crtc);
6340                 if (!intel_crtc->busy)
6341                         intel_decrease_pllclock(crtc);
6342         }
6343
6344
6345         mutex_unlock(&dev->struct_mutex);
6346 }
6347
6348 /**
6349  * intel_mark_busy - mark the GPU and possibly the display busy
6350  * @dev: drm device
6351  * @obj: object we're operating on
6352  *
6353  * Callers can use this function to indicate that the GPU is busy processing
6354  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6355  * buffer), we'll also mark the display as busy, so we know to increase its
6356  * clock frequency.
6357  */
6358 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6359 {
6360         drm_i915_private_t *dev_priv = dev->dev_private;
6361         struct drm_crtc *crtc = NULL;
6362         struct intel_framebuffer *intel_fb;
6363         struct intel_crtc *intel_crtc;
6364
6365         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6366                 return;
6367
6368         if (!dev_priv->busy)
6369                 dev_priv->busy = true;
6370         else
6371                 mod_timer(&dev_priv->idle_timer, jiffies +
6372                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6373
6374         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6375                 if (!crtc->fb)
6376                         continue;
6377
6378                 intel_crtc = to_intel_crtc(crtc);
6379                 intel_fb = to_intel_framebuffer(crtc->fb);
6380                 if (intel_fb->obj == obj) {
6381                         if (!intel_crtc->busy) {
6382                                 /* Non-busy -> busy, upclock */
6383                                 intel_increase_pllclock(crtc);
6384                                 intel_crtc->busy = true;
6385                         } else {
6386                                 /* Busy -> busy, put off timer */
6387                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6388                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6389                         }
6390                 }
6391         }
6392 }
6393
6394 static void intel_crtc_destroy(struct drm_crtc *crtc)
6395 {
6396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397         struct drm_device *dev = crtc->dev;
6398         struct intel_unpin_work *work;
6399         unsigned long flags;
6400
6401         spin_lock_irqsave(&dev->event_lock, flags);
6402         work = intel_crtc->unpin_work;
6403         intel_crtc->unpin_work = NULL;
6404         spin_unlock_irqrestore(&dev->event_lock, flags);
6405
6406         if (work) {
6407                 cancel_work_sync(&work->work);
6408                 kfree(work);
6409         }
6410
6411         drm_crtc_cleanup(crtc);
6412
6413         kfree(intel_crtc);
6414 }
6415
6416 static void intel_unpin_work_fn(struct work_struct *__work)
6417 {
6418         struct intel_unpin_work *work =
6419                 container_of(__work, struct intel_unpin_work, work);
6420
6421         mutex_lock(&work->dev->struct_mutex);
6422         i915_gem_object_unpin(work->old_fb_obj);
6423         drm_gem_object_unreference(&work->pending_flip_obj->base);
6424         drm_gem_object_unreference(&work->old_fb_obj->base);
6425
6426         intel_update_fbc(work->dev);
6427         mutex_unlock(&work->dev->struct_mutex);
6428         kfree(work);
6429 }
6430
6431 static void do_intel_finish_page_flip(struct drm_device *dev,
6432                                       struct drm_crtc *crtc)
6433 {
6434         drm_i915_private_t *dev_priv = dev->dev_private;
6435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6436         struct intel_unpin_work *work;
6437         struct drm_i915_gem_object *obj;
6438         struct drm_pending_vblank_event *e;
6439         struct timeval tnow, tvbl;
6440         unsigned long flags;
6441
6442         /* Ignore early vblank irqs */
6443         if (intel_crtc == NULL)
6444                 return;
6445
6446         do_gettimeofday(&tnow);
6447
6448         spin_lock_irqsave(&dev->event_lock, flags);
6449         work = intel_crtc->unpin_work;
6450         if (work == NULL || !work->pending) {
6451                 spin_unlock_irqrestore(&dev->event_lock, flags);
6452                 return;
6453         }
6454
6455         intel_crtc->unpin_work = NULL;
6456
6457         if (work->event) {
6458                 e = work->event;
6459                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6460
6461                 /* Called before vblank count and timestamps have
6462                  * been updated for the vblank interval of flip
6463                  * completion? Need to increment vblank count and
6464                  * add one videorefresh duration to returned timestamp
6465                  * to account for this. We assume this happened if we
6466                  * get called over 0.9 frame durations after the last
6467                  * timestamped vblank.
6468                  *
6469                  * This calculation can not be used with vrefresh rates
6470                  * below 5Hz (10Hz to be on the safe side) without
6471                  * promoting to 64 integers.
6472                  */
6473                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6474                     9 * crtc->framedur_ns) {
6475                         e->event.sequence++;
6476                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6477                                              crtc->framedur_ns);
6478                 }
6479
6480                 e->event.tv_sec = tvbl.tv_sec;
6481                 e->event.tv_usec = tvbl.tv_usec;
6482
6483                 list_add_tail(&e->base.link,
6484                               &e->base.file_priv->event_list);
6485                 wake_up_interruptible(&e->base.file_priv->event_wait);
6486         }
6487
6488         drm_vblank_put(dev, intel_crtc->pipe);
6489
6490         spin_unlock_irqrestore(&dev->event_lock, flags);
6491
6492         obj = work->old_fb_obj;
6493
6494         atomic_clear_mask(1 << intel_crtc->plane,
6495                           &obj->pending_flip.counter);
6496         if (atomic_read(&obj->pending_flip) == 0)
6497                 wake_up(&dev_priv->pending_flip_queue);
6498
6499         schedule_work(&work->work);
6500
6501         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6502 }
6503
6504 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6505 {
6506         drm_i915_private_t *dev_priv = dev->dev_private;
6507         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6508
6509         do_intel_finish_page_flip(dev, crtc);
6510 }
6511
6512 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6513 {
6514         drm_i915_private_t *dev_priv = dev->dev_private;
6515         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6516
6517         do_intel_finish_page_flip(dev, crtc);
6518 }
6519
6520 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6521 {
6522         drm_i915_private_t *dev_priv = dev->dev_private;
6523         struct intel_crtc *intel_crtc =
6524                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6525         unsigned long flags;
6526
6527         spin_lock_irqsave(&dev->event_lock, flags);
6528         if (intel_crtc->unpin_work) {
6529                 if ((++intel_crtc->unpin_work->pending) > 1)
6530                         DRM_ERROR("Prepared flip multiple times\n");
6531         } else {
6532                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6533         }
6534         spin_unlock_irqrestore(&dev->event_lock, flags);
6535 }
6536
6537 static int intel_gen2_queue_flip(struct drm_device *dev,
6538                                  struct drm_crtc *crtc,
6539                                  struct drm_framebuffer *fb,
6540                                  struct drm_i915_gem_object *obj)
6541 {
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544         unsigned long offset;
6545         u32 flip_mask;
6546         int ret;
6547
6548         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6549         if (ret)
6550                 goto out;
6551
6552         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6553         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6554
6555         ret = BEGIN_LP_RING(6);
6556         if (ret)
6557                 goto out;
6558
6559         /* Can't queue multiple flips, so wait for the previous
6560          * one to finish before executing the next.
6561          */
6562         if (intel_crtc->plane)
6563                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6564         else
6565                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6566         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6567         OUT_RING(MI_NOOP);
6568         OUT_RING(MI_DISPLAY_FLIP |
6569                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6570         OUT_RING(fb->pitch);
6571         OUT_RING(obj->gtt_offset + offset);
6572         OUT_RING(MI_NOOP);
6573         ADVANCE_LP_RING();
6574 out:
6575         return ret;
6576 }
6577
6578 static int intel_gen3_queue_flip(struct drm_device *dev,
6579                                  struct drm_crtc *crtc,
6580                                  struct drm_framebuffer *fb,
6581                                  struct drm_i915_gem_object *obj)
6582 {
6583         struct drm_i915_private *dev_priv = dev->dev_private;
6584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6585         unsigned long offset;
6586         u32 flip_mask;
6587         int ret;
6588
6589         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6590         if (ret)
6591                 goto out;
6592
6593         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6594         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6595
6596         ret = BEGIN_LP_RING(6);
6597         if (ret)
6598                 goto out;
6599
6600         if (intel_crtc->plane)
6601                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6602         else
6603                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6604         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6605         OUT_RING(MI_NOOP);
6606         OUT_RING(MI_DISPLAY_FLIP_I915 |
6607                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6608         OUT_RING(fb->pitch);
6609         OUT_RING(obj->gtt_offset + offset);
6610         OUT_RING(MI_NOOP);
6611
6612         ADVANCE_LP_RING();
6613 out:
6614         return ret;
6615 }
6616
6617 static int intel_gen4_queue_flip(struct drm_device *dev,
6618                                  struct drm_crtc *crtc,
6619                                  struct drm_framebuffer *fb,
6620                                  struct drm_i915_gem_object *obj)
6621 {
6622         struct drm_i915_private *dev_priv = dev->dev_private;
6623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6624         uint32_t pf, pipesrc;
6625         int ret;
6626
6627         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6628         if (ret)
6629                 goto out;
6630
6631         ret = BEGIN_LP_RING(4);
6632         if (ret)
6633                 goto out;
6634
6635         /* i965+ uses the linear or tiled offsets from the
6636          * Display Registers (which do not change across a page-flip)
6637          * so we need only reprogram the base address.
6638          */
6639         OUT_RING(MI_DISPLAY_FLIP |
6640                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6641         OUT_RING(fb->pitch);
6642         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6643
6644         /* XXX Enabling the panel-fitter across page-flip is so far
6645          * untested on non-native modes, so ignore it for now.
6646          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6647          */
6648         pf = 0;
6649         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6650         OUT_RING(pf | pipesrc);
6651         ADVANCE_LP_RING();
6652 out:
6653         return ret;
6654 }
6655
6656 static int intel_gen6_queue_flip(struct drm_device *dev,
6657                                  struct drm_crtc *crtc,
6658                                  struct drm_framebuffer *fb,
6659                                  struct drm_i915_gem_object *obj)
6660 {
6661         struct drm_i915_private *dev_priv = dev->dev_private;
6662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663         uint32_t pf, pipesrc;
6664         int ret;
6665
6666         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6667         if (ret)
6668                 goto out;
6669
6670         ret = BEGIN_LP_RING(4);
6671         if (ret)
6672                 goto out;
6673
6674         OUT_RING(MI_DISPLAY_FLIP |
6675                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6676         OUT_RING(fb->pitch | obj->tiling_mode);
6677         OUT_RING(obj->gtt_offset);
6678
6679         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6680         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6681         OUT_RING(pf | pipesrc);
6682         ADVANCE_LP_RING();
6683 out:
6684         return ret;
6685 }
6686
6687 /*
6688  * On gen7 we currently use the blit ring because (in early silicon at least)
6689  * the render ring doesn't give us interrpts for page flip completion, which
6690  * means clients will hang after the first flip is queued.  Fortunately the
6691  * blit ring generates interrupts properly, so use it instead.
6692  */
6693 static int intel_gen7_queue_flip(struct drm_device *dev,
6694                                  struct drm_crtc *crtc,
6695                                  struct drm_framebuffer *fb,
6696                                  struct drm_i915_gem_object *obj)
6697 {
6698         struct drm_i915_private *dev_priv = dev->dev_private;
6699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6700         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6701         int ret;
6702
6703         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6704         if (ret)
6705                 goto out;
6706
6707         ret = intel_ring_begin(ring, 4);
6708         if (ret)
6709                 goto out;
6710
6711         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6712         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6713         intel_ring_emit(ring, (obj->gtt_offset));
6714         intel_ring_emit(ring, (MI_NOOP));
6715         intel_ring_advance(ring);
6716 out:
6717         return ret;
6718 }
6719
6720 static int intel_default_queue_flip(struct drm_device *dev,
6721                                     struct drm_crtc *crtc,
6722                                     struct drm_framebuffer *fb,
6723                                     struct drm_i915_gem_object *obj)
6724 {
6725         return -ENODEV;
6726 }
6727
6728 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6729                                 struct drm_framebuffer *fb,
6730                                 struct drm_pending_vblank_event *event)
6731 {
6732         struct drm_device *dev = crtc->dev;
6733         struct drm_i915_private *dev_priv = dev->dev_private;
6734         struct intel_framebuffer *intel_fb;
6735         struct drm_i915_gem_object *obj;
6736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737         struct intel_unpin_work *work;
6738         unsigned long flags;
6739         int ret;
6740
6741         work = kzalloc(sizeof *work, GFP_KERNEL);
6742         if (work == NULL)
6743                 return -ENOMEM;
6744
6745         work->event = event;
6746         work->dev = crtc->dev;
6747         intel_fb = to_intel_framebuffer(crtc->fb);
6748         work->old_fb_obj = intel_fb->obj;
6749         INIT_WORK(&work->work, intel_unpin_work_fn);
6750
6751         /* We borrow the event spin lock for protecting unpin_work */
6752         spin_lock_irqsave(&dev->event_lock, flags);
6753         if (intel_crtc->unpin_work) {
6754                 spin_unlock_irqrestore(&dev->event_lock, flags);
6755                 kfree(work);
6756
6757                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6758                 return -EBUSY;
6759         }
6760         intel_crtc->unpin_work = work;
6761         spin_unlock_irqrestore(&dev->event_lock, flags);
6762
6763         intel_fb = to_intel_framebuffer(fb);
6764         obj = intel_fb->obj;
6765
6766         mutex_lock(&dev->struct_mutex);
6767
6768         /* Reference the objects for the scheduled work. */
6769         drm_gem_object_reference(&work->old_fb_obj->base);
6770         drm_gem_object_reference(&obj->base);
6771
6772         crtc->fb = fb;
6773
6774         ret = drm_vblank_get(dev, intel_crtc->pipe);
6775         if (ret)
6776                 goto cleanup_objs;
6777
6778         work->pending_flip_obj = obj;
6779
6780         work->enable_stall_check = true;
6781
6782         /* Block clients from rendering to the new back buffer until
6783          * the flip occurs and the object is no longer visible.
6784          */
6785         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6786
6787         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6788         if (ret)
6789                 goto cleanup_pending;
6790
6791         intel_disable_fbc(dev);
6792         mutex_unlock(&dev->struct_mutex);
6793
6794         trace_i915_flip_request(intel_crtc->plane, obj);
6795
6796         return 0;
6797
6798 cleanup_pending:
6799         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6800 cleanup_objs:
6801         drm_gem_object_unreference(&work->old_fb_obj->base);
6802         drm_gem_object_unreference(&obj->base);
6803         mutex_unlock(&dev->struct_mutex);
6804
6805         spin_lock_irqsave(&dev->event_lock, flags);
6806         intel_crtc->unpin_work = NULL;
6807         spin_unlock_irqrestore(&dev->event_lock, flags);
6808
6809         kfree(work);
6810
6811         return ret;
6812 }
6813
6814 static void intel_sanitize_modesetting(struct drm_device *dev,
6815                                        int pipe, int plane)
6816 {
6817         struct drm_i915_private *dev_priv = dev->dev_private;
6818         u32 reg, val;
6819
6820         if (HAS_PCH_SPLIT(dev))
6821                 return;
6822
6823         /* Who knows what state these registers were left in by the BIOS or
6824          * grub?
6825          *
6826          * If we leave the registers in a conflicting state (e.g. with the
6827          * display plane reading from the other pipe than the one we intend
6828          * to use) then when we attempt to teardown the active mode, we will
6829          * not disable the pipes and planes in the correct order -- leaving
6830          * a plane reading from a disabled pipe and possibly leading to
6831          * undefined behaviour.
6832          */
6833
6834         reg = DSPCNTR(plane);
6835         val = I915_READ(reg);
6836
6837         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6838                 return;
6839         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6840                 return;
6841
6842         /* This display plane is active and attached to the other CPU pipe. */
6843         pipe = !pipe;
6844
6845         /* Disable the plane and wait for it to stop reading from the pipe. */
6846         intel_disable_plane(dev_priv, plane, pipe);
6847         intel_disable_pipe(dev_priv, pipe);
6848 }
6849
6850 static void intel_crtc_reset(struct drm_crtc *crtc)
6851 {
6852         struct drm_device *dev = crtc->dev;
6853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6854
6855         /* Reset flags back to the 'unknown' status so that they
6856          * will be correctly set on the initial modeset.
6857          */
6858         intel_crtc->dpms_mode = -1;
6859
6860         /* We need to fix up any BIOS configuration that conflicts with
6861          * our expectations.
6862          */
6863         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6864 }
6865
6866 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6867         .dpms = intel_crtc_dpms,
6868         .mode_fixup = intel_crtc_mode_fixup,
6869         .mode_set = intel_crtc_mode_set,
6870         .mode_set_base = intel_pipe_set_base,
6871         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6872         .load_lut = intel_crtc_load_lut,
6873         .disable = intel_crtc_disable,
6874 };
6875
6876 static const struct drm_crtc_funcs intel_crtc_funcs = {
6877         .reset = intel_crtc_reset,
6878         .cursor_set = intel_crtc_cursor_set,
6879         .cursor_move = intel_crtc_cursor_move,
6880         .gamma_set = intel_crtc_gamma_set,
6881         .set_config = drm_crtc_helper_set_config,
6882         .destroy = intel_crtc_destroy,
6883         .page_flip = intel_crtc_page_flip,
6884 };
6885
6886 static void intel_crtc_init(struct drm_device *dev, int pipe)
6887 {
6888         drm_i915_private_t *dev_priv = dev->dev_private;
6889         struct intel_crtc *intel_crtc;
6890         int i;
6891
6892         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6893         if (intel_crtc == NULL)
6894                 return;
6895
6896         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6897
6898         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6899         for (i = 0; i < 256; i++) {
6900                 intel_crtc->lut_r[i] = i;
6901                 intel_crtc->lut_g[i] = i;
6902                 intel_crtc->lut_b[i] = i;
6903         }
6904
6905         /* Swap pipes & planes for FBC on pre-965 */
6906         intel_crtc->pipe = pipe;
6907         intel_crtc->plane = pipe;
6908         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6909                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6910                 intel_crtc->plane = !pipe;
6911         }
6912
6913         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6914                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6915         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6916         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6917
6918         intel_crtc_reset(&intel_crtc->base);
6919         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6920         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6921
6922         if (HAS_PCH_SPLIT(dev)) {
6923                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6924                 intel_helper_funcs.commit = ironlake_crtc_commit;
6925         } else {
6926                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6927                 intel_helper_funcs.commit = i9xx_crtc_commit;
6928         }
6929
6930         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6931
6932         intel_crtc->busy = false;
6933
6934         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6935                     (unsigned long)intel_crtc);
6936 }
6937
6938 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6939                                 struct drm_file *file)
6940 {
6941         drm_i915_private_t *dev_priv = dev->dev_private;
6942         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6943         struct drm_mode_object *drmmode_obj;
6944         struct intel_crtc *crtc;
6945
6946         if (!dev_priv) {
6947                 DRM_ERROR("called with no initialization\n");
6948                 return -EINVAL;
6949         }
6950
6951         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6952                         DRM_MODE_OBJECT_CRTC);
6953
6954         if (!drmmode_obj) {
6955                 DRM_ERROR("no such CRTC id\n");
6956                 return -EINVAL;
6957         }
6958
6959         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6960         pipe_from_crtc_id->pipe = crtc->pipe;
6961
6962         return 0;
6963 }
6964
6965 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6966 {
6967         struct intel_encoder *encoder;
6968         int index_mask = 0;
6969         int entry = 0;
6970
6971         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6972                 if (type_mask & encoder->clone_mask)
6973                         index_mask |= (1 << entry);
6974                 entry++;
6975         }
6976
6977         return index_mask;
6978 }
6979
6980 static bool has_edp_a(struct drm_device *dev)
6981 {
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983
6984         if (!IS_MOBILE(dev))
6985                 return false;
6986
6987         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6988                 return false;
6989
6990         if (IS_GEN5(dev) &&
6991             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6992                 return false;
6993
6994         return true;
6995 }
6996
6997 static void intel_setup_outputs(struct drm_device *dev)
6998 {
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000         struct intel_encoder *encoder;
7001         bool dpd_is_edp = false;
7002         bool has_lvds = false;
7003
7004         if (IS_MOBILE(dev) && !IS_I830(dev))
7005                 has_lvds = intel_lvds_init(dev);
7006         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7007                 /* disable the panel fitter on everything but LVDS */
7008                 I915_WRITE(PFIT_CONTROL, 0);
7009         }
7010
7011         if (HAS_PCH_SPLIT(dev)) {
7012                 dpd_is_edp = intel_dpd_is_edp(dev);
7013
7014                 if (has_edp_a(dev))
7015                         intel_dp_init(dev, DP_A);
7016
7017                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7018                         intel_dp_init(dev, PCH_DP_D);
7019         }
7020
7021         intel_crt_init(dev);
7022
7023         if (HAS_PCH_SPLIT(dev)) {
7024                 int found;
7025
7026                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7027                         /* PCH SDVOB multiplex with HDMIB */
7028                         found = intel_sdvo_init(dev, PCH_SDVOB);
7029                         if (!found)
7030                                 intel_hdmi_init(dev, HDMIB);
7031                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7032                                 intel_dp_init(dev, PCH_DP_B);
7033                 }
7034
7035                 if (I915_READ(HDMIC) & PORT_DETECTED)
7036                         intel_hdmi_init(dev, HDMIC);
7037
7038                 if (I915_READ(HDMID) & PORT_DETECTED)
7039                         intel_hdmi_init(dev, HDMID);
7040
7041                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7042                         intel_dp_init(dev, PCH_DP_C);
7043
7044                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7045                         intel_dp_init(dev, PCH_DP_D);
7046
7047         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7048                 bool found = false;
7049
7050                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7051                         DRM_DEBUG_KMS("probing SDVOB\n");
7052                         found = intel_sdvo_init(dev, SDVOB);
7053                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7054                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7055                                 intel_hdmi_init(dev, SDVOB);
7056                         }
7057
7058                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7059                                 DRM_DEBUG_KMS("probing DP_B\n");
7060                                 intel_dp_init(dev, DP_B);
7061                         }
7062                 }
7063
7064                 /* Before G4X SDVOC doesn't have its own detect register */
7065
7066                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7067                         DRM_DEBUG_KMS("probing SDVOC\n");
7068                         found = intel_sdvo_init(dev, SDVOC);
7069                 }
7070
7071                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7072
7073                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7074                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7075                                 intel_hdmi_init(dev, SDVOC);
7076                         }
7077                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7078                                 DRM_DEBUG_KMS("probing DP_C\n");
7079                                 intel_dp_init(dev, DP_C);
7080                         }
7081                 }
7082
7083                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7084                     (I915_READ(DP_D) & DP_DETECTED)) {
7085                         DRM_DEBUG_KMS("probing DP_D\n");
7086                         intel_dp_init(dev, DP_D);
7087                 }
7088         } else if (IS_GEN2(dev))
7089                 intel_dvo_init(dev);
7090
7091         if (SUPPORTS_TV(dev))
7092                 intel_tv_init(dev);
7093
7094         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7095                 encoder->base.possible_crtcs = encoder->crtc_mask;
7096                 encoder->base.possible_clones =
7097                         intel_encoder_clones(dev, encoder->clone_mask);
7098         }
7099
7100         intel_panel_setup_backlight(dev);
7101
7102         /* disable all the possible outputs/crtcs before entering KMS mode */
7103         drm_helper_disable_unused_functions(dev);
7104 }
7105
7106 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7107 {
7108         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7109
7110         drm_framebuffer_cleanup(fb);
7111         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7112
7113         kfree(intel_fb);
7114 }
7115
7116 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7117                                                 struct drm_file *file,
7118                                                 unsigned int *handle)
7119 {
7120         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7121         struct drm_i915_gem_object *obj = intel_fb->obj;
7122
7123         return drm_gem_handle_create(file, &obj->base, handle);
7124 }
7125
7126 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7127         .destroy = intel_user_framebuffer_destroy,
7128         .create_handle = intel_user_framebuffer_create_handle,
7129 };
7130
7131 int intel_framebuffer_init(struct drm_device *dev,
7132                            struct intel_framebuffer *intel_fb,
7133                            struct drm_mode_fb_cmd *mode_cmd,
7134                            struct drm_i915_gem_object *obj)
7135 {
7136         int ret;
7137
7138         if (obj->tiling_mode == I915_TILING_Y)
7139                 return -EINVAL;
7140
7141         if (mode_cmd->pitch & 63)
7142                 return -EINVAL;
7143
7144         switch (mode_cmd->bpp) {
7145         case 8:
7146         case 16:
7147                 /* Only pre-ILK can handle 5:5:5 */
7148                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7149                         return -EINVAL;
7150                 break;
7151
7152         case 24:
7153         case 32:
7154                 break;
7155         default:
7156                 return -EINVAL;
7157         }
7158
7159         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7160         if (ret) {
7161                 DRM_ERROR("framebuffer init failed %d\n", ret);
7162                 return ret;
7163         }
7164
7165         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7166         intel_fb->obj = obj;
7167         return 0;
7168 }
7169
7170 static struct drm_framebuffer *
7171 intel_user_framebuffer_create(struct drm_device *dev,
7172                               struct drm_file *filp,
7173                               struct drm_mode_fb_cmd *mode_cmd)
7174 {
7175         struct drm_i915_gem_object *obj;
7176
7177         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7178         if (&obj->base == NULL)
7179                 return ERR_PTR(-ENOENT);
7180
7181         return intel_framebuffer_create(dev, mode_cmd, obj);
7182 }
7183
7184 static const struct drm_mode_config_funcs intel_mode_funcs = {
7185         .fb_create = intel_user_framebuffer_create,
7186         .output_poll_changed = intel_fb_output_poll_changed,
7187 };
7188
7189 static struct drm_i915_gem_object *
7190 intel_alloc_context_page(struct drm_device *dev)
7191 {
7192         struct drm_i915_gem_object *ctx;
7193         int ret;
7194
7195         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7196
7197         ctx = i915_gem_alloc_object(dev, 4096);
7198         if (!ctx) {
7199                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7200                 return NULL;
7201         }
7202
7203         ret = i915_gem_object_pin(ctx, 4096, true);
7204         if (ret) {
7205                 DRM_ERROR("failed to pin power context: %d\n", ret);
7206                 goto err_unref;
7207         }
7208
7209         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7210         if (ret) {
7211                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7212                 goto err_unpin;
7213         }
7214
7215         return ctx;
7216
7217 err_unpin:
7218         i915_gem_object_unpin(ctx);
7219 err_unref:
7220         drm_gem_object_unreference(&ctx->base);
7221         mutex_unlock(&dev->struct_mutex);
7222         return NULL;
7223 }
7224
7225 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7226 {
7227         struct drm_i915_private *dev_priv = dev->dev_private;
7228         u16 rgvswctl;
7229
7230         rgvswctl = I915_READ16(MEMSWCTL);
7231         if (rgvswctl & MEMCTL_CMD_STS) {
7232                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7233                 return false; /* still busy with another command */
7234         }
7235
7236         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7237                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7238         I915_WRITE16(MEMSWCTL, rgvswctl);
7239         POSTING_READ16(MEMSWCTL);
7240
7241         rgvswctl |= MEMCTL_CMD_STS;
7242         I915_WRITE16(MEMSWCTL, rgvswctl);
7243
7244         return true;
7245 }
7246
7247 void ironlake_enable_drps(struct drm_device *dev)
7248 {
7249         struct drm_i915_private *dev_priv = dev->dev_private;
7250         u32 rgvmodectl = I915_READ(MEMMODECTL);
7251         u8 fmax, fmin, fstart, vstart;
7252
7253         /* Enable temp reporting */
7254         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7255         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7256
7257         /* 100ms RC evaluation intervals */
7258         I915_WRITE(RCUPEI, 100000);
7259         I915_WRITE(RCDNEI, 100000);
7260
7261         /* Set max/min thresholds to 90ms and 80ms respectively */
7262         I915_WRITE(RCBMAXAVG, 90000);
7263         I915_WRITE(RCBMINAVG, 80000);
7264
7265         I915_WRITE(MEMIHYST, 1);
7266
7267         /* Set up min, max, and cur for interrupt handling */
7268         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7269         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7270         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7271                 MEMMODE_FSTART_SHIFT;
7272
7273         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7274                 PXVFREQ_PX_SHIFT;
7275
7276         dev_priv->fmax = fmax; /* IPS callback will increase this */
7277         dev_priv->fstart = fstart;
7278
7279         dev_priv->max_delay = fstart;
7280         dev_priv->min_delay = fmin;
7281         dev_priv->cur_delay = fstart;
7282
7283         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7284                          fmax, fmin, fstart);
7285
7286         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7287
7288         /*
7289          * Interrupts will be enabled in ironlake_irq_postinstall
7290          */
7291
7292         I915_WRITE(VIDSTART, vstart);
7293         POSTING_READ(VIDSTART);
7294
7295         rgvmodectl |= MEMMODE_SWMODE_EN;
7296         I915_WRITE(MEMMODECTL, rgvmodectl);
7297
7298         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7299                 DRM_ERROR("stuck trying to change perf mode\n");
7300         msleep(1);
7301
7302         ironlake_set_drps(dev, fstart);
7303
7304         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7305                 I915_READ(0x112e0);
7306         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7307         dev_priv->last_count2 = I915_READ(0x112f4);
7308         getrawmonotonic(&dev_priv->last_time2);
7309 }
7310
7311 void ironlake_disable_drps(struct drm_device *dev)
7312 {
7313         struct drm_i915_private *dev_priv = dev->dev_private;
7314         u16 rgvswctl = I915_READ16(MEMSWCTL);
7315
7316         /* Ack interrupts, disable EFC interrupt */
7317         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7318         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7319         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7320         I915_WRITE(DEIIR, DE_PCU_EVENT);
7321         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7322
7323         /* Go back to the starting frequency */
7324         ironlake_set_drps(dev, dev_priv->fstart);
7325         msleep(1);
7326         rgvswctl |= MEMCTL_CMD_STS;
7327         I915_WRITE(MEMSWCTL, rgvswctl);
7328         msleep(1);
7329
7330 }
7331
7332 void gen6_set_rps(struct drm_device *dev, u8 val)
7333 {
7334         struct drm_i915_private *dev_priv = dev->dev_private;
7335         u32 swreq;
7336
7337         swreq = (val & 0x3ff) << 25;
7338         I915_WRITE(GEN6_RPNSWREQ, swreq);
7339 }
7340
7341 void gen6_disable_rps(struct drm_device *dev)
7342 {
7343         struct drm_i915_private *dev_priv = dev->dev_private;
7344
7345         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7346         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7347         I915_WRITE(GEN6_PMIER, 0);
7348
7349         spin_lock_irq(&dev_priv->rps_lock);
7350         dev_priv->pm_iir = 0;
7351         spin_unlock_irq(&dev_priv->rps_lock);
7352
7353         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7354 }
7355
7356 static unsigned long intel_pxfreq(u32 vidfreq)
7357 {
7358         unsigned long freq;
7359         int div = (vidfreq & 0x3f0000) >> 16;
7360         int post = (vidfreq & 0x3000) >> 12;
7361         int pre = (vidfreq & 0x7);
7362
7363         if (!pre)
7364                 return 0;
7365
7366         freq = ((div * 133333) / ((1<<post) * pre));
7367
7368         return freq;
7369 }
7370
7371 void intel_init_emon(struct drm_device *dev)
7372 {
7373         struct drm_i915_private *dev_priv = dev->dev_private;
7374         u32 lcfuse;
7375         u8 pxw[16];
7376         int i;
7377
7378         /* Disable to program */
7379         I915_WRITE(ECR, 0);
7380         POSTING_READ(ECR);
7381
7382         /* Program energy weights for various events */
7383         I915_WRITE(SDEW, 0x15040d00);
7384         I915_WRITE(CSIEW0, 0x007f0000);
7385         I915_WRITE(CSIEW1, 0x1e220004);
7386         I915_WRITE(CSIEW2, 0x04000004);
7387
7388         for (i = 0; i < 5; i++)
7389                 I915_WRITE(PEW + (i * 4), 0);
7390         for (i = 0; i < 3; i++)
7391                 I915_WRITE(DEW + (i * 4), 0);
7392
7393         /* Program P-state weights to account for frequency power adjustment */
7394         for (i = 0; i < 16; i++) {
7395                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7396                 unsigned long freq = intel_pxfreq(pxvidfreq);
7397                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7398                         PXVFREQ_PX_SHIFT;
7399                 unsigned long val;
7400
7401                 val = vid * vid;
7402                 val *= (freq / 1000);
7403                 val *= 255;
7404                 val /= (127*127*900);
7405                 if (val > 0xff)
7406                         DRM_ERROR("bad pxval: %ld\n", val);
7407                 pxw[i] = val;
7408         }
7409         /* Render standby states get 0 weight */
7410         pxw[14] = 0;
7411         pxw[15] = 0;
7412
7413         for (i = 0; i < 4; i++) {
7414                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7415                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7416                 I915_WRITE(PXW + (i * 4), val);
7417         }
7418
7419         /* Adjust magic regs to magic values (more experimental results) */
7420         I915_WRITE(OGW0, 0);
7421         I915_WRITE(OGW1, 0);
7422         I915_WRITE(EG0, 0x00007f00);
7423         I915_WRITE(EG1, 0x0000000e);
7424         I915_WRITE(EG2, 0x000e0000);
7425         I915_WRITE(EG3, 0x68000300);
7426         I915_WRITE(EG4, 0x42000000);
7427         I915_WRITE(EG5, 0x00140031);
7428         I915_WRITE(EG6, 0);
7429         I915_WRITE(EG7, 0);
7430
7431         for (i = 0; i < 8; i++)
7432                 I915_WRITE(PXWL + (i * 4), 0);
7433
7434         /* Enable PMON + select events */
7435         I915_WRITE(ECR, 0x80000019);
7436
7437         lcfuse = I915_READ(LCFUSE02);
7438
7439         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7440 }
7441
7442 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7443 {
7444         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7445         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7446         u32 pcu_mbox, rc6_mask = 0;
7447         int cur_freq, min_freq, max_freq;
7448         int i;
7449
7450         /* Here begins a magic sequence of register writes to enable
7451          * auto-downclocking.
7452          *
7453          * Perhaps there might be some value in exposing these to
7454          * userspace...
7455          */
7456         I915_WRITE(GEN6_RC_STATE, 0);
7457         mutex_lock(&dev_priv->dev->struct_mutex);
7458         gen6_gt_force_wake_get(dev_priv);
7459
7460         /* disable the counters and set deterministic thresholds */
7461         I915_WRITE(GEN6_RC_CONTROL, 0);
7462
7463         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7464         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7465         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7466         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7467         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7468
7469         for (i = 0; i < I915_NUM_RINGS; i++)
7470                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7471
7472         I915_WRITE(GEN6_RC_SLEEP, 0);
7473         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7474         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7475         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7476         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7477
7478         if (i915_enable_rc6)
7479                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7480                         GEN6_RC_CTL_RC6_ENABLE;
7481
7482         I915_WRITE(GEN6_RC_CONTROL,
7483                    rc6_mask |
7484                    GEN6_RC_CTL_EI_MODE(1) |
7485                    GEN6_RC_CTL_HW_ENABLE);
7486
7487         I915_WRITE(GEN6_RPNSWREQ,
7488                    GEN6_FREQUENCY(10) |
7489                    GEN6_OFFSET(0) |
7490                    GEN6_AGGRESSIVE_TURBO);
7491         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7492                    GEN6_FREQUENCY(12));
7493
7494         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7495         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7496                    18 << 24 |
7497                    6 << 16);
7498         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7499         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7500         I915_WRITE(GEN6_RP_UP_EI, 100000);
7501         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7502         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7503         I915_WRITE(GEN6_RP_CONTROL,
7504                    GEN6_RP_MEDIA_TURBO |
7505                    GEN6_RP_USE_NORMAL_FREQ |
7506                    GEN6_RP_MEDIA_IS_GFX |
7507                    GEN6_RP_ENABLE |
7508                    GEN6_RP_UP_BUSY_AVG |
7509                    GEN6_RP_DOWN_IDLE_CONT);
7510
7511         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7512                      500))
7513                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7514
7515         I915_WRITE(GEN6_PCODE_DATA, 0);
7516         I915_WRITE(GEN6_PCODE_MAILBOX,
7517                    GEN6_PCODE_READY |
7518                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7519         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7520                      500))
7521                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7522
7523         min_freq = (rp_state_cap & 0xff0000) >> 16;
7524         max_freq = rp_state_cap & 0xff;
7525         cur_freq = (gt_perf_status & 0xff00) >> 8;
7526
7527         /* Check for overclock support */
7528         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7529                      500))
7530                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7531         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7532         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7533         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7534                      500))
7535                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7536         if (pcu_mbox & (1<<31)) { /* OC supported */
7537                 max_freq = pcu_mbox & 0xff;
7538                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7539         }
7540
7541         /* In units of 100MHz */
7542         dev_priv->max_delay = max_freq;
7543         dev_priv->min_delay = min_freq;
7544         dev_priv->cur_delay = cur_freq;
7545
7546         /* requires MSI enabled */
7547         I915_WRITE(GEN6_PMIER,
7548                    GEN6_PM_MBOX_EVENT |
7549                    GEN6_PM_THERMAL_EVENT |
7550                    GEN6_PM_RP_DOWN_TIMEOUT |
7551                    GEN6_PM_RP_UP_THRESHOLD |
7552                    GEN6_PM_RP_DOWN_THRESHOLD |
7553                    GEN6_PM_RP_UP_EI_EXPIRED |
7554                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7555         spin_lock_irq(&dev_priv->rps_lock);
7556         WARN_ON(dev_priv->pm_iir != 0);
7557         I915_WRITE(GEN6_PMIMR, 0);
7558         spin_unlock_irq(&dev_priv->rps_lock);
7559         /* enable all PM interrupts */
7560         I915_WRITE(GEN6_PMINTRMSK, 0);
7561
7562         gen6_gt_force_wake_put(dev_priv);
7563         mutex_unlock(&dev_priv->dev->struct_mutex);
7564 }
7565
7566 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7567 {
7568         int min_freq = 15;
7569         int gpu_freq, ia_freq, max_ia_freq;
7570         int scaling_factor = 180;
7571
7572         max_ia_freq = cpufreq_quick_get_max(0);
7573         /*
7574          * Default to measured freq if none found, PCU will ensure we don't go
7575          * over
7576          */
7577         if (!max_ia_freq)
7578                 max_ia_freq = tsc_khz;
7579
7580         /* Convert from kHz to MHz */
7581         max_ia_freq /= 1000;
7582
7583         mutex_lock(&dev_priv->dev->struct_mutex);
7584
7585         /*
7586          * For each potential GPU frequency, load a ring frequency we'd like
7587          * to use for memory access.  We do this by specifying the IA frequency
7588          * the PCU should use as a reference to determine the ring frequency.
7589          */
7590         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7591              gpu_freq--) {
7592                 int diff = dev_priv->max_delay - gpu_freq;
7593
7594                 /*
7595                  * For GPU frequencies less than 750MHz, just use the lowest
7596                  * ring freq.
7597                  */
7598                 if (gpu_freq < min_freq)
7599                         ia_freq = 800;
7600                 else
7601                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7602                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7603
7604                 I915_WRITE(GEN6_PCODE_DATA,
7605                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7606                            gpu_freq);
7607                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7608                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7609                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7610                               GEN6_PCODE_READY) == 0, 10)) {
7611                         DRM_ERROR("pcode write of freq table timed out\n");
7612                         continue;
7613                 }
7614         }
7615
7616         mutex_unlock(&dev_priv->dev->struct_mutex);
7617 }
7618
7619 static void ironlake_init_clock_gating(struct drm_device *dev)
7620 {
7621         struct drm_i915_private *dev_priv = dev->dev_private;
7622         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7623
7624         /* Required for FBC */
7625         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7626                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7627                 DPFDUNIT_CLOCK_GATE_DISABLE;
7628         /* Required for CxSR */
7629         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7630
7631         I915_WRITE(PCH_3DCGDIS0,
7632                    MARIUNIT_CLOCK_GATE_DISABLE |
7633                    SVSMUNIT_CLOCK_GATE_DISABLE);
7634         I915_WRITE(PCH_3DCGDIS1,
7635                    VFMUNIT_CLOCK_GATE_DISABLE);
7636
7637         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7638
7639         /*
7640          * According to the spec the following bits should be set in
7641          * order to enable memory self-refresh
7642          * The bit 22/21 of 0x42004
7643          * The bit 5 of 0x42020
7644          * The bit 15 of 0x45000
7645          */
7646         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7647                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7648                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7649         I915_WRITE(ILK_DSPCLK_GATE,
7650                    (I915_READ(ILK_DSPCLK_GATE) |
7651                     ILK_DPARB_CLK_GATE));
7652         I915_WRITE(DISP_ARB_CTL,
7653                    (I915_READ(DISP_ARB_CTL) |
7654                     DISP_FBC_WM_DIS));
7655         I915_WRITE(WM3_LP_ILK, 0);
7656         I915_WRITE(WM2_LP_ILK, 0);
7657         I915_WRITE(WM1_LP_ILK, 0);
7658
7659         /*
7660          * Based on the document from hardware guys the following bits
7661          * should be set unconditionally in order to enable FBC.
7662          * The bit 22 of 0x42000
7663          * The bit 22 of 0x42004
7664          * The bit 7,8,9 of 0x42020.
7665          */
7666         if (IS_IRONLAKE_M(dev)) {
7667                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7668                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7669                            ILK_FBCQ_DIS);
7670                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7671                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7672                            ILK_DPARB_GATE);
7673                 I915_WRITE(ILK_DSPCLK_GATE,
7674                            I915_READ(ILK_DSPCLK_GATE) |
7675                            ILK_DPFC_DIS1 |
7676                            ILK_DPFC_DIS2 |
7677                            ILK_CLK_FBC);
7678         }
7679
7680         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7681                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7682                    ILK_ELPIN_409_SELECT);
7683         I915_WRITE(_3D_CHICKEN2,
7684                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7685                    _3D_CHICKEN2_WM_READ_PIPELINED);
7686 }
7687
7688 static void gen6_init_clock_gating(struct drm_device *dev)
7689 {
7690         struct drm_i915_private *dev_priv = dev->dev_private;
7691         int pipe;
7692         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7693
7694         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7695
7696         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7697                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7698                    ILK_ELPIN_409_SELECT);
7699
7700         I915_WRITE(WM3_LP_ILK, 0);
7701         I915_WRITE(WM2_LP_ILK, 0);
7702         I915_WRITE(WM1_LP_ILK, 0);
7703
7704         /*
7705          * According to the spec the following bits should be
7706          * set in order to enable memory self-refresh and fbc:
7707          * The bit21 and bit22 of 0x42000
7708          * The bit21 and bit22 of 0x42004
7709          * The bit5 and bit7 of 0x42020
7710          * The bit14 of 0x70180
7711          * The bit14 of 0x71180
7712          */
7713         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7714                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7715                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7716         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7717                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7718                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7719         I915_WRITE(ILK_DSPCLK_GATE,
7720                    I915_READ(ILK_DSPCLK_GATE) |
7721                    ILK_DPARB_CLK_GATE  |
7722                    ILK_DPFD_CLK_GATE);
7723
7724         for_each_pipe(pipe)
7725                 I915_WRITE(DSPCNTR(pipe),
7726                            I915_READ(DSPCNTR(pipe)) |
7727                            DISPPLANE_TRICKLE_FEED_DISABLE);
7728 }
7729
7730 static void ivybridge_init_clock_gating(struct drm_device *dev)
7731 {
7732         struct drm_i915_private *dev_priv = dev->dev_private;
7733         int pipe;
7734         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7735
7736         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7737
7738         I915_WRITE(WM3_LP_ILK, 0);
7739         I915_WRITE(WM2_LP_ILK, 0);
7740         I915_WRITE(WM1_LP_ILK, 0);
7741
7742         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7743
7744         for_each_pipe(pipe)
7745                 I915_WRITE(DSPCNTR(pipe),
7746                            I915_READ(DSPCNTR(pipe)) |
7747                            DISPPLANE_TRICKLE_FEED_DISABLE);
7748 }
7749
7750 static void g4x_init_clock_gating(struct drm_device *dev)
7751 {
7752         struct drm_i915_private *dev_priv = dev->dev_private;
7753         uint32_t dspclk_gate;
7754
7755         I915_WRITE(RENCLK_GATE_D1, 0);
7756         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7757                    GS_UNIT_CLOCK_GATE_DISABLE |
7758                    CL_UNIT_CLOCK_GATE_DISABLE);
7759         I915_WRITE(RAMCLK_GATE_D, 0);
7760         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7761                 OVRUNIT_CLOCK_GATE_DISABLE |
7762                 OVCUNIT_CLOCK_GATE_DISABLE;
7763         if (IS_GM45(dev))
7764                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7765         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7766 }
7767
7768 static void crestline_init_clock_gating(struct drm_device *dev)
7769 {
7770         struct drm_i915_private *dev_priv = dev->dev_private;
7771
7772         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7773         I915_WRITE(RENCLK_GATE_D2, 0);
7774         I915_WRITE(DSPCLK_GATE_D, 0);
7775         I915_WRITE(RAMCLK_GATE_D, 0);
7776         I915_WRITE16(DEUC, 0);
7777 }
7778
7779 static void broadwater_init_clock_gating(struct drm_device *dev)
7780 {
7781         struct drm_i915_private *dev_priv = dev->dev_private;
7782
7783         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7784                    I965_RCC_CLOCK_GATE_DISABLE |
7785                    I965_RCPB_CLOCK_GATE_DISABLE |
7786                    I965_ISC_CLOCK_GATE_DISABLE |
7787                    I965_FBC_CLOCK_GATE_DISABLE);
7788         I915_WRITE(RENCLK_GATE_D2, 0);
7789 }
7790
7791 static void gen3_init_clock_gating(struct drm_device *dev)
7792 {
7793         struct drm_i915_private *dev_priv = dev->dev_private;
7794         u32 dstate = I915_READ(D_STATE);
7795
7796         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7797                 DSTATE_DOT_CLOCK_GATING;
7798         I915_WRITE(D_STATE, dstate);
7799 }
7800
7801 static void i85x_init_clock_gating(struct drm_device *dev)
7802 {
7803         struct drm_i915_private *dev_priv = dev->dev_private;
7804
7805         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7806 }
7807
7808 static void i830_init_clock_gating(struct drm_device *dev)
7809 {
7810         struct drm_i915_private *dev_priv = dev->dev_private;
7811
7812         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7813 }
7814
7815 static void ibx_init_clock_gating(struct drm_device *dev)
7816 {
7817         struct drm_i915_private *dev_priv = dev->dev_private;
7818
7819         /*
7820          * On Ibex Peak and Cougar Point, we need to disable clock
7821          * gating for the panel power sequencer or it will fail to
7822          * start up when no ports are active.
7823          */
7824         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7825 }
7826
7827 static void cpt_init_clock_gating(struct drm_device *dev)
7828 {
7829         struct drm_i915_private *dev_priv = dev->dev_private;
7830
7831         /*
7832          * On Ibex Peak and Cougar Point, we need to disable clock
7833          * gating for the panel power sequencer or it will fail to
7834          * start up when no ports are active.
7835          */
7836         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7837         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7838                    DPLS_EDP_PPS_FIX_DIS);
7839 }
7840
7841 static void ironlake_teardown_rc6(struct drm_device *dev)
7842 {
7843         struct drm_i915_private *dev_priv = dev->dev_private;
7844
7845         if (dev_priv->renderctx) {
7846                 i915_gem_object_unpin(dev_priv->renderctx);
7847                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7848                 dev_priv->renderctx = NULL;
7849         }
7850
7851         if (dev_priv->pwrctx) {
7852                 i915_gem_object_unpin(dev_priv->pwrctx);
7853                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7854                 dev_priv->pwrctx = NULL;
7855         }
7856 }
7857
7858 static void ironlake_disable_rc6(struct drm_device *dev)
7859 {
7860         struct drm_i915_private *dev_priv = dev->dev_private;
7861
7862         if (I915_READ(PWRCTXA)) {
7863                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7864                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7865                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7866                          50);
7867
7868                 I915_WRITE(PWRCTXA, 0);
7869                 POSTING_READ(PWRCTXA);
7870
7871                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7872                 POSTING_READ(RSTDBYCTL);
7873         }
7874
7875         ironlake_teardown_rc6(dev);
7876 }
7877
7878 static int ironlake_setup_rc6(struct drm_device *dev)
7879 {
7880         struct drm_i915_private *dev_priv = dev->dev_private;
7881
7882         if (dev_priv->renderctx == NULL)
7883                 dev_priv->renderctx = intel_alloc_context_page(dev);
7884         if (!dev_priv->renderctx)
7885                 return -ENOMEM;
7886
7887         if (dev_priv->pwrctx == NULL)
7888                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7889         if (!dev_priv->pwrctx) {
7890                 ironlake_teardown_rc6(dev);
7891                 return -ENOMEM;
7892         }
7893
7894         return 0;
7895 }
7896
7897 void ironlake_enable_rc6(struct drm_device *dev)
7898 {
7899         struct drm_i915_private *dev_priv = dev->dev_private;
7900         int ret;
7901
7902         /* rc6 disabled by default due to repeated reports of hanging during
7903          * boot and resume.
7904          */
7905         if (!i915_enable_rc6)
7906                 return;
7907
7908         mutex_lock(&dev->struct_mutex);
7909         ret = ironlake_setup_rc6(dev);
7910         if (ret) {
7911                 mutex_unlock(&dev->struct_mutex);
7912                 return;
7913         }
7914
7915         /*
7916          * GPU can automatically power down the render unit if given a page
7917          * to save state.
7918          */
7919         ret = BEGIN_LP_RING(6);
7920         if (ret) {
7921                 ironlake_teardown_rc6(dev);
7922                 mutex_unlock(&dev->struct_mutex);
7923                 return;
7924         }
7925
7926         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7927         OUT_RING(MI_SET_CONTEXT);
7928         OUT_RING(dev_priv->renderctx->gtt_offset |
7929                  MI_MM_SPACE_GTT |
7930                  MI_SAVE_EXT_STATE_EN |
7931                  MI_RESTORE_EXT_STATE_EN |
7932                  MI_RESTORE_INHIBIT);
7933         OUT_RING(MI_SUSPEND_FLUSH);
7934         OUT_RING(MI_NOOP);
7935         OUT_RING(MI_FLUSH);
7936         ADVANCE_LP_RING();
7937
7938         /*
7939          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7940          * does an implicit flush, combined with MI_FLUSH above, it should be
7941          * safe to assume that renderctx is valid
7942          */
7943         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7944         if (ret) {
7945                 DRM_ERROR("failed to enable ironlake power power savings\n");
7946                 ironlake_teardown_rc6(dev);
7947                 mutex_unlock(&dev->struct_mutex);
7948                 return;
7949         }
7950
7951         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7952         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7953         mutex_unlock(&dev->struct_mutex);
7954 }
7955
7956 void intel_init_clock_gating(struct drm_device *dev)
7957 {
7958         struct drm_i915_private *dev_priv = dev->dev_private;
7959
7960         dev_priv->display.init_clock_gating(dev);
7961
7962         if (dev_priv->display.init_pch_clock_gating)
7963                 dev_priv->display.init_pch_clock_gating(dev);
7964 }
7965
7966 /* Set up chip specific display functions */
7967 static void intel_init_display(struct drm_device *dev)
7968 {
7969         struct drm_i915_private *dev_priv = dev->dev_private;
7970
7971         /* We always want a DPMS function */
7972         if (HAS_PCH_SPLIT(dev)) {
7973                 dev_priv->display.dpms = ironlake_crtc_dpms;
7974                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7975                 dev_priv->display.update_plane = ironlake_update_plane;
7976         } else {
7977                 dev_priv->display.dpms = i9xx_crtc_dpms;
7978                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7979                 dev_priv->display.update_plane = i9xx_update_plane;
7980         }
7981
7982         if (I915_HAS_FBC(dev)) {
7983                 if (HAS_PCH_SPLIT(dev)) {
7984                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7985                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7986                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7987                 } else if (IS_GM45(dev)) {
7988                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7989                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7990                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7991                 } else if (IS_CRESTLINE(dev)) {
7992                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7993                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7994                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7995                 }
7996                 /* 855GM needs testing */
7997         }
7998
7999         /* Returns the core display clock speed */
8000         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
8001                 dev_priv->display.get_display_clock_speed =
8002                         i945_get_display_clock_speed;
8003         else if (IS_I915G(dev))
8004                 dev_priv->display.get_display_clock_speed =
8005                         i915_get_display_clock_speed;
8006         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8007                 dev_priv->display.get_display_clock_speed =
8008                         i9xx_misc_get_display_clock_speed;
8009         else if (IS_I915GM(dev))
8010                 dev_priv->display.get_display_clock_speed =
8011                         i915gm_get_display_clock_speed;
8012         else if (IS_I865G(dev))
8013                 dev_priv->display.get_display_clock_speed =
8014                         i865_get_display_clock_speed;
8015         else if (IS_I85X(dev))
8016                 dev_priv->display.get_display_clock_speed =
8017                         i855_get_display_clock_speed;
8018         else /* 852, 830 */
8019                 dev_priv->display.get_display_clock_speed =
8020                         i830_get_display_clock_speed;
8021
8022         /* For FIFO watermark updates */
8023         if (HAS_PCH_SPLIT(dev)) {
8024                 if (HAS_PCH_IBX(dev))
8025                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8026                 else if (HAS_PCH_CPT(dev))
8027                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8028
8029                 if (IS_GEN5(dev)) {
8030                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8031                                 dev_priv->display.update_wm = ironlake_update_wm;
8032                         else {
8033                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8034                                               "Disable CxSR\n");
8035                                 dev_priv->display.update_wm = NULL;
8036                         }
8037                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8038                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8039                 } else if (IS_GEN6(dev)) {
8040                         if (SNB_READ_WM0_LATENCY()) {
8041                                 dev_priv->display.update_wm = sandybridge_update_wm;
8042                         } else {
8043                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8044                                               "Disable CxSR\n");
8045                                 dev_priv->display.update_wm = NULL;
8046                         }
8047                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8048                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8049                 } else if (IS_IVYBRIDGE(dev)) {
8050                         /* FIXME: detect B0+ stepping and use auto training */
8051                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8052                         if (SNB_READ_WM0_LATENCY()) {
8053                                 dev_priv->display.update_wm = sandybridge_update_wm;
8054                         } else {
8055                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8056                                               "Disable CxSR\n");
8057                                 dev_priv->display.update_wm = NULL;
8058                         }
8059                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8060
8061                 } else
8062                         dev_priv->display.update_wm = NULL;
8063         } else if (IS_PINEVIEW(dev)) {
8064                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8065                                             dev_priv->is_ddr3,
8066                                             dev_priv->fsb_freq,
8067                                             dev_priv->mem_freq)) {
8068                         DRM_INFO("failed to find known CxSR latency "
8069                                  "(found ddr%s fsb freq %d, mem freq %d), "
8070                                  "disabling CxSR\n",
8071                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
8072                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8073                         /* Disable CxSR and never update its watermark again */
8074                         pineview_disable_cxsr(dev);
8075                         dev_priv->display.update_wm = NULL;
8076                 } else
8077                         dev_priv->display.update_wm = pineview_update_wm;
8078                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8079         } else if (IS_G4X(dev)) {
8080                 dev_priv->display.update_wm = g4x_update_wm;
8081                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8082         } else if (IS_GEN4(dev)) {
8083                 dev_priv->display.update_wm = i965_update_wm;
8084                 if (IS_CRESTLINE(dev))
8085                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8086                 else if (IS_BROADWATER(dev))
8087                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8088         } else if (IS_GEN3(dev)) {
8089                 dev_priv->display.update_wm = i9xx_update_wm;
8090                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8091                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8092         } else if (IS_I865G(dev)) {
8093                 dev_priv->display.update_wm = i830_update_wm;
8094                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8095                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8096         } else if (IS_I85X(dev)) {
8097                 dev_priv->display.update_wm = i9xx_update_wm;
8098                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8099                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8100         } else {
8101                 dev_priv->display.update_wm = i830_update_wm;
8102                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8103                 if (IS_845G(dev))
8104                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8105                 else
8106                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8107         }
8108
8109         /* Default just returns -ENODEV to indicate unsupported */
8110         dev_priv->display.queue_flip = intel_default_queue_flip;
8111
8112         switch (INTEL_INFO(dev)->gen) {
8113         case 2:
8114                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8115                 break;
8116
8117         case 3:
8118                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8119                 break;
8120
8121         case 4:
8122         case 5:
8123                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8124                 break;
8125
8126         case 6:
8127                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8128                 break;
8129         case 7:
8130                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8131                 break;
8132         }
8133 }
8134
8135 /*
8136  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8137  * resume, or other times.  This quirk makes sure that's the case for
8138  * affected systems.
8139  */
8140 static void quirk_pipea_force (struct drm_device *dev)
8141 {
8142         struct drm_i915_private *dev_priv = dev->dev_private;
8143
8144         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8145         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8146 }
8147
8148 /*
8149  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8150  */
8151 static void quirk_ssc_force_disable(struct drm_device *dev)
8152 {
8153         struct drm_i915_private *dev_priv = dev->dev_private;
8154         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8155 }
8156
8157 struct intel_quirk {
8158         int device;
8159         int subsystem_vendor;
8160         int subsystem_device;
8161         void (*hook)(struct drm_device *dev);
8162 };
8163
8164 struct intel_quirk intel_quirks[] = {
8165         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8166         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8167         /* HP Mini needs pipe A force quirk (LP: #322104) */
8168         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8169
8170         /* Thinkpad R31 needs pipe A force quirk */
8171         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8172         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8173         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8174
8175         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8176         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8177         /* ThinkPad X40 needs pipe A force quirk */
8178
8179         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8180         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8181
8182         /* 855 & before need to leave pipe A & dpll A up */
8183         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8184         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8185
8186         /* Lenovo U160 cannot use SSC on LVDS */
8187         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8188 };
8189
8190 static void intel_init_quirks(struct drm_device *dev)
8191 {
8192         struct pci_dev *d = dev->pdev;
8193         int i;
8194
8195         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8196                 struct intel_quirk *q = &intel_quirks[i];
8197
8198                 if (d->device == q->device &&
8199                     (d->subsystem_vendor == q->subsystem_vendor ||
8200                      q->subsystem_vendor == PCI_ANY_ID) &&
8201                     (d->subsystem_device == q->subsystem_device ||
8202                      q->subsystem_device == PCI_ANY_ID))
8203                         q->hook(dev);
8204         }
8205 }
8206
8207 /* Disable the VGA plane that we never use */
8208 static void i915_disable_vga(struct drm_device *dev)
8209 {
8210         struct drm_i915_private *dev_priv = dev->dev_private;
8211         u8 sr1;
8212         u32 vga_reg;
8213
8214         if (HAS_PCH_SPLIT(dev))
8215                 vga_reg = CPU_VGACNTRL;
8216         else
8217                 vga_reg = VGACNTRL;
8218
8219         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8220         outb(1, VGA_SR_INDEX);
8221         sr1 = inb(VGA_SR_DATA);
8222         outb(sr1 | 1<<5, VGA_SR_DATA);
8223         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8224         udelay(300);
8225
8226         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8227         POSTING_READ(vga_reg);
8228 }
8229
8230 void intel_modeset_init(struct drm_device *dev)
8231 {
8232         struct drm_i915_private *dev_priv = dev->dev_private;
8233         int i;
8234
8235         drm_mode_config_init(dev);
8236
8237         dev->mode_config.min_width = 0;
8238         dev->mode_config.min_height = 0;
8239
8240         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8241
8242         intel_init_quirks(dev);
8243
8244         intel_init_display(dev);
8245
8246         if (IS_GEN2(dev)) {
8247                 dev->mode_config.max_width = 2048;
8248                 dev->mode_config.max_height = 2048;
8249         } else if (IS_GEN3(dev)) {
8250                 dev->mode_config.max_width = 4096;
8251                 dev->mode_config.max_height = 4096;
8252         } else {
8253                 dev->mode_config.max_width = 8192;
8254                 dev->mode_config.max_height = 8192;
8255         }
8256         dev->mode_config.fb_base = dev->agp->base;
8257
8258         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8259                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8260
8261         for (i = 0; i < dev_priv->num_pipe; i++) {
8262                 intel_crtc_init(dev, i);
8263         }
8264
8265         /* Just disable it once at startup */
8266         i915_disable_vga(dev);
8267         intel_setup_outputs(dev);
8268
8269         intel_init_clock_gating(dev);
8270
8271         if (IS_IRONLAKE_M(dev)) {
8272                 ironlake_enable_drps(dev);
8273                 intel_init_emon(dev);
8274         }
8275
8276         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8277                 gen6_enable_rps(dev_priv);
8278                 gen6_update_ring_freq(dev_priv);
8279         }
8280
8281         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8282         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8283                     (unsigned long)dev);
8284 }
8285
8286 void intel_modeset_gem_init(struct drm_device *dev)
8287 {
8288         if (IS_IRONLAKE_M(dev))
8289                 ironlake_enable_rc6(dev);
8290
8291         intel_setup_overlay(dev);
8292 }
8293
8294 void intel_modeset_cleanup(struct drm_device *dev)
8295 {
8296         struct drm_i915_private *dev_priv = dev->dev_private;
8297         struct drm_crtc *crtc;
8298         struct intel_crtc *intel_crtc;
8299
8300         drm_kms_helper_poll_fini(dev);
8301         mutex_lock(&dev->struct_mutex);
8302
8303         intel_unregister_dsm_handler();
8304
8305
8306         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8307                 /* Skip inactive CRTCs */
8308                 if (!crtc->fb)
8309                         continue;
8310
8311                 intel_crtc = to_intel_crtc(crtc);
8312                 intel_increase_pllclock(crtc);
8313         }
8314
8315         intel_disable_fbc(dev);
8316
8317         if (IS_IRONLAKE_M(dev))
8318                 ironlake_disable_drps(dev);
8319         if (IS_GEN6(dev) || IS_GEN7(dev))
8320                 gen6_disable_rps(dev);
8321
8322         if (IS_IRONLAKE_M(dev))
8323                 ironlake_disable_rc6(dev);
8324
8325         mutex_unlock(&dev->struct_mutex);
8326
8327         /* Disable the irq before mode object teardown, for the irq might
8328          * enqueue unpin/hotplug work. */
8329         drm_irq_uninstall(dev);
8330         cancel_work_sync(&dev_priv->hotplug_work);
8331
8332         /* flush any delayed tasks or pending work */
8333         flush_scheduled_work();
8334
8335         /* Shut off idle work before the crtcs get freed. */
8336         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8337                 intel_crtc = to_intel_crtc(crtc);
8338                 del_timer_sync(&intel_crtc->idle_timer);
8339         }
8340         del_timer_sync(&dev_priv->idle_timer);
8341         cancel_work_sync(&dev_priv->idle_work);
8342
8343         drm_mode_config_cleanup(dev);
8344 }
8345
8346 /*
8347  * Return which encoder is currently attached for connector.
8348  */
8349 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8350 {
8351         return &intel_attached_encoder(connector)->base;
8352 }
8353
8354 void intel_connector_attach_encoder(struct intel_connector *connector,
8355                                     struct intel_encoder *encoder)
8356 {
8357         connector->encoder = encoder;
8358         drm_mode_connector_attach_encoder(&connector->base,
8359                                           &encoder->base);
8360 }
8361
8362 /*
8363  * set vga decode state - true == enable VGA decode
8364  */
8365 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8366 {
8367         struct drm_i915_private *dev_priv = dev->dev_private;
8368         u16 gmch_ctrl;
8369
8370         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8371         if (state)
8372                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8373         else
8374                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8375         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8376         return 0;
8377 }
8378
8379 #ifdef CONFIG_DEBUG_FS
8380 #include <linux/seq_file.h>
8381
8382 struct intel_display_error_state {
8383         struct intel_cursor_error_state {
8384                 u32 control;
8385                 u32 position;
8386                 u32 base;
8387                 u32 size;
8388         } cursor[2];
8389
8390         struct intel_pipe_error_state {
8391                 u32 conf;
8392                 u32 source;
8393
8394                 u32 htotal;
8395                 u32 hblank;
8396                 u32 hsync;
8397                 u32 vtotal;
8398                 u32 vblank;
8399                 u32 vsync;
8400         } pipe[2];
8401
8402         struct intel_plane_error_state {
8403                 u32 control;
8404                 u32 stride;
8405                 u32 size;
8406                 u32 pos;
8407                 u32 addr;
8408                 u32 surface;
8409                 u32 tile_offset;
8410         } plane[2];
8411 };
8412
8413 struct intel_display_error_state *
8414 intel_display_capture_error_state(struct drm_device *dev)
8415 {
8416         drm_i915_private_t *dev_priv = dev->dev_private;
8417         struct intel_display_error_state *error;
8418         int i;
8419
8420         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8421         if (error == NULL)
8422                 return NULL;
8423
8424         for (i = 0; i < 2; i++) {
8425                 error->cursor[i].control = I915_READ(CURCNTR(i));
8426                 error->cursor[i].position = I915_READ(CURPOS(i));
8427                 error->cursor[i].base = I915_READ(CURBASE(i));
8428
8429                 error->plane[i].control = I915_READ(DSPCNTR(i));
8430                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8431                 error->plane[i].size = I915_READ(DSPSIZE(i));
8432                 error->plane[i].pos= I915_READ(DSPPOS(i));
8433                 error->plane[i].addr = I915_READ(DSPADDR(i));
8434                 if (INTEL_INFO(dev)->gen >= 4) {
8435                         error->plane[i].surface = I915_READ(DSPSURF(i));
8436                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8437                 }
8438
8439                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8440                 error->pipe[i].source = I915_READ(PIPESRC(i));
8441                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8442                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8443                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8444                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8445                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8446                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8447         }
8448
8449         return error;
8450 }
8451
8452 void
8453 intel_display_print_error_state(struct seq_file *m,
8454                                 struct drm_device *dev,
8455                                 struct intel_display_error_state *error)
8456 {
8457         int i;
8458
8459         for (i = 0; i < 2; i++) {
8460                 seq_printf(m, "Pipe [%d]:\n", i);
8461                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8462                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8463                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8464                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8465                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8466                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8467                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8468                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8469
8470                 seq_printf(m, "Plane [%d]:\n", i);
8471                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8472                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8473                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8474                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8475                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8476                 if (INTEL_INFO(dev)->gen >= 4) {
8477                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8478                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8479                 }
8480
8481                 seq_printf(m, "Cursor [%d]:\n", i);
8482                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8483                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8484                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8485         }
8486 }
8487 #endif