drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "drm_dp_helper.h"
  37
  38 #include "drm_crtc_helper.h"
  39
  40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  41
  42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  43 static void intel_update_watermarks(struct drm_device *dev);
  44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  45
  46 typedef struct {
  47     /* given values */
  48     int n;
  49     int m1, m2;
  50     int p1, p2;
  51     /* derived values */
  52     int dot;
  53     int vco;
  54     int m;
  55     int p;
  56 } intel_clock_t;
  57
  58 typedef struct {
  59     int min, max;
  60 } intel_range_t;
  61
  62 typedef struct {
  63     int dot_limit;
  64     int p2_slow, p2_fast;
  65 } intel_p2_t;
  66
  67 #define INTEL_P2_NUM                  2
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71     intel_p2_t      p2;
  72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  73                       int, int, intel_clock_t *);
  74 };
  75
  76 #define I8XX_DOT_MIN              25000
  77 #define I8XX_DOT_MAX             350000
  78 #define I8XX_VCO_MIN             930000
  79 #define I8XX_VCO_MAX            1400000
  80 #define I8XX_N_MIN                    3
  81 #define I8XX_N_MAX                   16
  82 #define I8XX_M_MIN                   96
  83 #define I8XX_M_MAX                  140
  84 #define I8XX_M1_MIN                  18
  85 #define I8XX_M1_MAX                  26
  86 #define I8XX_M2_MIN                   6
  87 #define I8XX_M2_MAX                  16
  88 #define I8XX_P_MIN                    4
  89 #define I8XX_P_MAX                  128
  90 #define I8XX_P1_MIN                   2
  91 #define I8XX_P1_MAX                  33
  92 #define I8XX_P1_LVDS_MIN              1
  93 #define I8XX_P1_LVDS_MAX              6
  94 #define I8XX_P2_SLOW                  4
  95 #define I8XX_P2_FAST                  2
  96 #define I8XX_P2_LVDS_SLOW             14
  97 #define I8XX_P2_LVDS_FAST             7
  98 #define I8XX_P2_SLOW_LIMIT       165000
  99
 100 #define I9XX_DOT_MIN              20000
 101 #define I9XX_DOT_MAX             400000
 102 #define I9XX_VCO_MIN            1400000
 103 #define I9XX_VCO_MAX            2800000
 104 #define PINEVIEW_VCO_MIN                1700000
 105 #define PINEVIEW_VCO_MAX                3500000
 106 #define I9XX_N_MIN                    1
 107 #define I9XX_N_MAX                    6
 108 /* Pineview's Ncounter is a ring counter */
 109 #define PINEVIEW_N_MIN                3
 110 #define PINEVIEW_N_MAX                6
 111 #define I9XX_M_MIN                   70
 112 #define I9XX_M_MAX                  120
 113 #define PINEVIEW_M_MIN                2
 114 #define PINEVIEW_M_MAX              256
 115 #define I9XX_M1_MIN                  10
 116 #define I9XX_M1_MAX                  22
 117 #define I9XX_M2_MIN                   5
 118 #define I9XX_M2_MAX                   9
 119 /* Pineview M1 is reserved, and must be 0 */
 120 #define PINEVIEW_M1_MIN               0
 121 #define PINEVIEW_M1_MAX               0
 122 #define PINEVIEW_M2_MIN               0
 123 #define PINEVIEW_M2_MAX               254
 124 #define I9XX_P_SDVO_DAC_MIN           5
 125 #define I9XX_P_SDVO_DAC_MAX          80
 126 #define I9XX_P_LVDS_MIN               7
 127 #define I9XX_P_LVDS_MAX              98
 128 #define PINEVIEW_P_LVDS_MIN                   7
 129 #define PINEVIEW_P_LVDS_MAX                  112
 130 #define I9XX_P1_MIN                   1
 131 #define I9XX_P1_MAX                   8
 132 #define I9XX_P2_SDVO_DAC_SLOW                10
 133 #define I9XX_P2_SDVO_DAC_FAST                 5
 134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 135 #define I9XX_P2_LVDS_SLOW                    14
 136 #define I9XX_P2_LVDS_FAST                     7
 137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 138
 139 /*The parameter is for SDVO on G4x platform*/
 140 #define G4X_DOT_SDVO_MIN           25000
 141 #define G4X_DOT_SDVO_MAX           270000
 142 #define G4X_VCO_MIN                1750000
 143 #define G4X_VCO_MAX                3500000
 144 #define G4X_N_SDVO_MIN             1
 145 #define G4X_N_SDVO_MAX             4
 146 #define G4X_M_SDVO_MIN             104
 147 #define G4X_M_SDVO_MAX             138
 148 #define G4X_M1_SDVO_MIN            17
 149 #define G4X_M1_SDVO_MAX            23
 150 #define G4X_M2_SDVO_MIN            5
 151 #define G4X_M2_SDVO_MAX            11
 152 #define G4X_P_SDVO_MIN             10
 153 #define G4X_P_SDVO_MAX             30
 154 #define G4X_P1_SDVO_MIN            1
 155 #define G4X_P1_SDVO_MAX            3
 156 #define G4X_P2_SDVO_SLOW           10
 157 #define G4X_P2_SDVO_FAST           10
 158 #define G4X_P2_SDVO_LIMIT          270000
 159
 160 /*The parameter is for HDMI_DAC on G4x platform*/
 161 #define G4X_DOT_HDMI_DAC_MIN           22000
 162 #define G4X_DOT_HDMI_DAC_MAX           400000
 163 #define G4X_N_HDMI_DAC_MIN             1
 164 #define G4X_N_HDMI_DAC_MAX             4
 165 #define G4X_M_HDMI_DAC_MIN             104
 166 #define G4X_M_HDMI_DAC_MAX             138
 167 #define G4X_M1_HDMI_DAC_MIN            16
 168 #define G4X_M1_HDMI_DAC_MAX            23
 169 #define G4X_M2_HDMI_DAC_MIN            5
 170 #define G4X_M2_HDMI_DAC_MAX            11
 171 #define G4X_P_HDMI_DAC_MIN             5
 172 #define G4X_P_HDMI_DAC_MAX             80
 173 #define G4X_P1_HDMI_DAC_MIN            1
 174 #define G4X_P1_HDMI_DAC_MAX            8
 175 #define G4X_P2_HDMI_DAC_SLOW           10
 176 #define G4X_P2_HDMI_DAC_FAST           5
 177 #define G4X_P2_HDMI_DAC_LIMIT          165000
 178
 179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 197
 198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 216
 217 /*The parameter is for DISPLAY PORT on G4x platform*/
 218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 220 #define G4X_N_DISPLAY_PORT_MIN             1
 221 #define G4X_N_DISPLAY_PORT_MAX             2
 222 #define G4X_M_DISPLAY_PORT_MIN             97
 223 #define G4X_M_DISPLAY_PORT_MAX             108
 224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 228 #define G4X_P_DISPLAY_PORT_MIN             10
 229 #define G4X_P_DISPLAY_PORT_MAX             20
 230 #define G4X_P1_DISPLAY_PORT_MIN            1
 231 #define G4X_P1_DISPLAY_PORT_MAX            2
 232 #define G4X_P2_DISPLAY_PORT_SLOW           10
 233 #define G4X_P2_DISPLAY_PORT_FAST           10
 234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 235
 236 /* Ironlake / Sandybridge */
 237 /* as we calculate clock using (register_value + 2) for
 238    N/M1/M2, so here the range value for them is (actual_value-2).
 239  */
 240 #define IRONLAKE_DOT_MIN         25000
 241 #define IRONLAKE_DOT_MAX         350000
 242 #define IRONLAKE_VCO_MIN         1760000
 243 #define IRONLAKE_VCO_MAX         3510000
 244 #define IRONLAKE_M1_MIN          12
 245 #define IRONLAKE_M1_MAX          22
 246 #define IRONLAKE_M2_MIN          5
 247 #define IRONLAKE_M2_MAX          9
 248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 249
 250 /* We have parameter ranges for different type of outputs. */
 251
 252 /* DAC & HDMI Refclk 120Mhz */
 253 #define IRONLAKE_DAC_N_MIN      1
 254 #define IRONLAKE_DAC_N_MAX      5
 255 #define IRONLAKE_DAC_M_MIN      79
 256 #define IRONLAKE_DAC_M_MAX      127
 257 #define IRONLAKE_DAC_P_MIN      5
 258 #define IRONLAKE_DAC_P_MAX      80
 259 #define IRONLAKE_DAC_P1_MIN     1
 260 #define IRONLAKE_DAC_P1_MAX     8
 261 #define IRONLAKE_DAC_P2_SLOW    10
 262 #define IRONLAKE_DAC_P2_FAST    5
 263
 264 /* LVDS single-channel 120Mhz refclk */
 265 #define IRONLAKE_LVDS_S_N_MIN   1
 266 #define IRONLAKE_LVDS_S_N_MAX   3
 267 #define IRONLAKE_LVDS_S_M_MIN   79
 268 #define IRONLAKE_LVDS_S_M_MAX   118
 269 #define IRONLAKE_LVDS_S_P_MIN   28
 270 #define IRONLAKE_LVDS_S_P_MAX   112
 271 #define IRONLAKE_LVDS_S_P1_MIN  2
 272 #define IRONLAKE_LVDS_S_P1_MAX  8
 273 #define IRONLAKE_LVDS_S_P2_SLOW 14
 274 #define IRONLAKE_LVDS_S_P2_FAST 14
 275
 276 /* LVDS dual-channel 120Mhz refclk */
 277 #define IRONLAKE_LVDS_D_N_MIN   1
 278 #define IRONLAKE_LVDS_D_N_MAX   3
 279 #define IRONLAKE_LVDS_D_M_MIN   79
 280 #define IRONLAKE_LVDS_D_M_MAX   127
 281 #define IRONLAKE_LVDS_D_P_MIN   14
 282 #define IRONLAKE_LVDS_D_P_MAX   56
 283 #define IRONLAKE_LVDS_D_P1_MIN  2
 284 #define IRONLAKE_LVDS_D_P1_MAX  8
 285 #define IRONLAKE_LVDS_D_P2_SLOW 7
 286 #define IRONLAKE_LVDS_D_P2_FAST 7
 287
 288 /* LVDS single-channel 100Mhz refclk */
 289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 299
 300 /* LVDS dual-channel 100Mhz refclk */
 301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 311
 312 /* DisplayPort */
 313 #define IRONLAKE_DP_N_MIN               1
 314 #define IRONLAKE_DP_N_MAX               2
 315 #define IRONLAKE_DP_M_MIN               81
 316 #define IRONLAKE_DP_M_MAX               90
 317 #define IRONLAKE_DP_P_MIN               10
 318 #define IRONLAKE_DP_P_MAX               20
 319 #define IRONLAKE_DP_P2_FAST             10
 320 #define IRONLAKE_DP_P2_SLOW             10
 321 #define IRONLAKE_DP_P2_LIMIT            0
 322 #define IRONLAKE_DP_P1_MIN              1
 323 #define IRONLAKE_DP_P1_MAX              2
 324
 325 static bool
 326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 327                     int target, int refclk, intel_clock_t *best_clock);
 328 static bool
 329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 330                         int target, int refclk, intel_clock_t *best_clock);
 331
 332 static bool
 333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 334                       int target, int refclk, intel_clock_t *best_clock);
 335 static bool
 336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 337                            int target, int refclk, intel_clock_t *best_clock);
 338
 339 static const intel_limit_t intel_limits_i8xx_dvo = {
 340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 350         .find_pll = intel_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_i8xx_lvds = {
 354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 364         .find_pll = intel_find_best_PLL,
 365 };
 366
 367 static const intel_limit_t intel_limits_i9xx_sdvo = {
 368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 378         .find_pll = intel_find_best_PLL,
 379 };
 380
 381 static const intel_limit_t intel_limits_i9xx_lvds = {
 382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 390         /* The single-channel range is 25-112Mhz, and dual-channel
 391          * is 80-224Mhz.  Prefer single channel as much as possible.
 392          */
 393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 395         .find_pll = intel_find_best_PLL,
 396 };
 397
 398     /* below parameter and function is for G4X Chipset Family*/
 399 static const intel_limit_t intel_limits_g4x_sdvo = {
 400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 409                  .p2_slow = G4X_P2_SDVO_SLOW,
 410                  .p2_fast = G4X_P2_SDVO_FAST
 411         },
 412         .find_pll = intel_g4x_find_best_PLL,
 413 };
 414
 415 static const intel_limit_t intel_limits_g4x_hdmi = {
 416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 434         .vco = { .min = G4X_VCO_MIN,
 435                  .max = G4X_VCO_MAX },
 436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 451         },
 452         .find_pll = intel_g4x_find_best_PLL,
 453 };
 454
 455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 458         .vco = { .min = G4X_VCO_MIN,
 459                  .max = G4X_VCO_MAX },
 460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 475         },
 476         .find_pll = intel_g4x_find_best_PLL,
 477 };
 478
 479 static const intel_limit_t intel_limits_g4x_display_port = {
 480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 482         .vco = { .min = G4X_VCO_MIN,
 483                  .max = G4X_VCO_MAX},
 484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 485                  .max = G4X_N_DISPLAY_PORT_MAX },
 486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 487                  .max = G4X_M_DISPLAY_PORT_MAX },
 488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 489                  .max = G4X_M1_DISPLAY_PORT_MAX },
 490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 491                  .max = G4X_M2_DISPLAY_PORT_MAX },
 492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 493                  .max = G4X_P_DISPLAY_PORT_MAX },
 494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 495                  .max = G4X_P1_DISPLAY_PORT_MAX},
 496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 499         .find_pll = intel_find_pll_g4x_dp,
 500 };
 501
 502 static const intel_limit_t intel_limits_pineview_sdvo = {
 503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 513         .find_pll = intel_find_best_PLL,
 514 };
 515
 516 static const intel_limit_t intel_limits_pineview_lvds = {
 517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 525         /* Pineview only supports single-channel mode. */
 526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 528         .find_pll = intel_find_best_PLL,
 529 };
 530
 531 static const intel_limit_t intel_limits_ironlake_dac = {
 532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 543         .find_pll = intel_g4x_find_best_PLL,
 544 };
 545
 546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 558         .find_pll = intel_g4x_find_best_PLL,
 559 };
 560
 561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 573         .find_pll = intel_g4x_find_best_PLL,
 574 };
 575
 576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 588         .find_pll = intel_g4x_find_best_PLL,
 589 };
 590
 591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 603         .find_pll = intel_g4x_find_best_PLL,
 604 };
 605
 606 static const intel_limit_t intel_limits_ironlake_display_port = {
 607         .dot = { .min = IRONLAKE_DOT_MIN,
 608                  .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,
 610                  .max = IRONLAKE_VCO_MAX},
 611         .n   = { .min = IRONLAKE_DP_N_MIN,
 612                  .max = IRONLAKE_DP_N_MAX },
 613         .m   = { .min = IRONLAKE_DP_M_MIN,
 614                  .max = IRONLAKE_DP_M_MAX },
 615         .m1  = { .min = IRONLAKE_M1_MIN,
 616                  .max = IRONLAKE_M1_MAX },
 617         .m2  = { .min = IRONLAKE_M2_MIN,
 618                  .max = IRONLAKE_M2_MAX },
 619         .p   = { .min = IRONLAKE_DP_P_MIN,
 620                  .max = IRONLAKE_DP_P_MAX },
 621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 622                  .max = IRONLAKE_DP_P1_MAX},
 623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 625                  .p2_fast = IRONLAKE_DP_P2_FAST },
 626         .find_pll = intel_find_pll_ironlake_dp,
 627 };
 628
 629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633         const intel_limit_t *limit;
 634         int refclk = 120;
 635
 636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 638                         refclk = 100;
 639
 640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 641                     LVDS_CLKB_POWER_UP) {
 642                         /* LVDS dual channel */
 643                         if (refclk == 100)
 644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 645                         else
 646                                 limit = &intel_limits_ironlake_dual_lvds;
 647                 } else {
 648                         if (refclk == 100)
 649                                 limit = &intel_limits_ironlake_single_lvds_100m;
 650                         else
 651                                 limit = &intel_limits_ironlake_single_lvds;
 652                 }
 653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 654                         HAS_eDP)
 655                 limit = &intel_limits_ironlake_display_port;
 656         else
 657                 limit = &intel_limits_ironlake_dac;
 658
 659         return limit;
 660 }
 661
 662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 663 {
 664         struct drm_device *dev = crtc->dev;
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         const intel_limit_t *limit;
 667
 668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 670                     LVDS_CLKB_POWER_UP)
 671                         /* LVDS with dual channel */
 672                         limit = &intel_limits_g4x_dual_channel_lvds;
 673                 else
 674                         /* LVDS with dual channel */
 675                         limit = &intel_limits_g4x_single_channel_lvds;
 676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 678                 limit = &intel_limits_g4x_hdmi;
 679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 680                 limit = &intel_limits_g4x_sdvo;
 681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 682                 limit = &intel_limits_g4x_display_port;
 683         } else /* The option is for other outputs */
 684                 limit = &intel_limits_i9xx_sdvo;
 685
 686         return limit;
 687 }
 688
 689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 690 {
 691         struct drm_device *dev = crtc->dev;
 692         const intel_limit_t *limit;
 693
 694         if (HAS_PCH_SPLIT(dev))
 695                 limit = intel_ironlake_limit(crtc);
 696         else if (IS_G4X(dev)) {
 697                 limit = intel_g4x_limit(crtc);
 698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 700                         limit = &intel_limits_i9xx_lvds;
 701                 else
 702                         limit = &intel_limits_i9xx_sdvo;
 703         } else if (IS_PINEVIEW(dev)) {
 704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 705                         limit = &intel_limits_pineview_lvds;
 706                 else
 707                         limit = &intel_limits_pineview_sdvo;
 708         } else {
 709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 710                         limit = &intel_limits_i8xx_lvds;
 711                 else
 712                         limit = &intel_limits_i8xx_dvo;
 713         }
 714         return limit;
 715 }
 716
 717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 718 static void pineview_clock(int refclk, intel_clock_t *clock)
 719 {
 720         clock->m = clock->m2 + 2;
 721         clock->p = clock->p1 * clock->p2;
 722         clock->vco = refclk * clock->m / clock->n;
 723         clock->dot = clock->vco / clock->p;
 724 }
 725
 726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 727 {
 728         if (IS_PINEVIEW(dev)) {
 729                 pineview_clock(refclk, clock);
 730                 return;
 731         }
 732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 733         clock->p = clock->p1 * clock->p2;
 734         clock->vco = refclk * clock->m / (clock->n + 2);
 735         clock->dot = clock->vco / clock->p;
 736 }
 737
 738 /**
 739  * Returns whether any output on the specified pipe is of the specified type
 740  */
 741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 742 {
 743     struct drm_device *dev = crtc->dev;
 744     struct drm_mode_config *mode_config = &dev->mode_config;
 745     struct drm_encoder *l_entry;
 746
 747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 748             if (l_entry && l_entry->crtc == crtc) {
 749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 750                     if (intel_encoder->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 758 /**
 759  * Returns whether the given set of divisors are valid for a given refclk with
 760  * the given connectors.
 761  */
 762
 763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 764 {
 765         const intel_limit_t *limit = intel_limit (crtc);
 766         struct drm_device *dev = crtc->dev;
 767
 768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 769                 INTELPllInvalid ("p1 out of range\n");
 770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 771                 INTELPllInvalid ("p out of range\n");
 772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 773                 INTELPllInvalid ("m2 out of range\n");
 774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 775                 INTELPllInvalid ("m1 out of range\n");
 776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 777                 INTELPllInvalid ("m1 <= m2\n");
 778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 779                 INTELPllInvalid ("m out of range\n");
 780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 781                 INTELPllInvalid ("n out of range\n");
 782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 783                 INTELPllInvalid ("vco out of range\n");
 784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 785          * connector, etc., rather than just a single range.
 786          */
 787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 788                 INTELPllInvalid ("dot out of range\n");
 789
 790         return true;
 791 }
 792
 793 static bool
 794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 795                     int target, int refclk, intel_clock_t *best_clock)
 796
 797 {
 798         struct drm_device *dev = crtc->dev;
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         intel_clock_t clock;
 801         int err = target;
 802
 803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 804             (I915_READ(LVDS)) != 0) {
 805                 /*
 806                  * For LVDS, if the panel is on, just rely on its current
 807                  * settings for dual-channel.  We haven't figured out how to
 808                  * reliably set up different single/dual channel state, if we
 809                  * even can.
 810                  */
 811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 812                     LVDS_CLKB_POWER_UP)
 813                         clock.p2 = limit->p2.p2_fast;
 814                 else
 815                         clock.p2 = limit->p2.p2_slow;
 816         } else {
 817                 if (target < limit->p2.dot_limit)
 818                         clock.p2 = limit->p2.p2_slow;
 819                 else
 820                         clock.p2 = limit->p2.p2_fast;
 821         }
 822
 823         memset (best_clock, 0, sizeof (*best_clock));
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         /* m1 is always 0 in Pineview */
 830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 831                                 break;
 832                         for (clock.n = limit->n.min;
 833                              clock.n <= limit->n.max; clock.n++) {
 834                                 for (clock.p1 = limit->p1.min;
 835                                         clock.p1 <= limit->p1.max; clock.p1++) {
 836                                         int this_err;
 837
 838                                         intel_clock(dev, refclk, &clock);
 839
 840                                         if (!intel_PLL_is_valid(crtc, &clock))
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 858                         int target, int refclk, intel_clock_t *best_clock)
 859 {
 860         struct drm_device *dev = crtc->dev;
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862         intel_clock_t clock;
 863         int max_n;
 864         bool found;
 865         /* approximately equals target * 0.00585 */
 866         int err_most = (target >> 8) + (target >> 9);
 867         found = false;
 868
 869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 870                 int lvds_reg;
 871
 872                 if (HAS_PCH_SPLIT(dev))
 873                         lvds_reg = PCH_LVDS;
 874                 else
 875                         lvds_reg = LVDS;
 876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 877                     LVDS_CLKB_POWER_UP)
 878                         clock.p2 = limit->p2.p2_fast;
 879                 else
 880                         clock.p2 = limit->p2.p2_slow;
 881         } else {
 882                 if (target < limit->p2.dot_limit)
 883                         clock.p2 = limit->p2.p2_slow;
 884                 else
 885                         clock.p2 = limit->p2.p2_fast;
 886         }
 887
 888         memset(best_clock, 0, sizeof(*best_clock));
 889         max_n = limit->n.max;
 890         /* based on hardware requirement, prefer smaller n to precision */
 891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 892                 /* based on hardware requirement, prefere larger m1,m2 */
 893                 for (clock.m1 = limit->m1.max;
 894                      clock.m1 >= limit->m1.min; clock.m1--) {
 895                         for (clock.m2 = limit->m2.max;
 896                              clock.m2 >= limit->m2.min; clock.m2--) {
 897                                 for (clock.p1 = limit->p1.max;
 898                                      clock.p1 >= limit->p1.min; clock.p1--) {
 899                                         int this_err;
 900
 901                                         intel_clock(dev, refclk, &clock);
 902                                         if (!intel_PLL_is_valid(crtc, &clock))
 903                                                 continue;
 904                                         this_err = abs(clock.dot - target) ;
 905                                         if (this_err < err_most) {
 906                                                 *best_clock = clock;
 907                                                 err_most = this_err;
 908                                                 max_n = clock.n;
 909                                                 found = true;
 910                                         }
 911                                 }
 912                         }
 913                 }
 914         }
 915         return found;
 916 }
 917
 918 static bool
 919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 920                            int target, int refclk, intel_clock_t *best_clock)
 921 {
 922         struct drm_device *dev = crtc->dev;
 923         intel_clock_t clock;
 924
 925         /* return directly when it is eDP */
 926         if (HAS_eDP)
 927                 return true;
 928
 929         if (target < 200000) {
 930                 clock.n = 1;
 931                 clock.p1 = 2;
 932                 clock.p2 = 10;
 933                 clock.m1 = 12;
 934                 clock.m2 = 9;
 935         } else {
 936                 clock.n = 2;
 937                 clock.p1 = 1;
 938                 clock.p2 = 10;
 939                 clock.m1 = 14;
 940                 clock.m2 = 8;
 941         }
 942         intel_clock(dev, refclk, &clock);
 943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 944         return true;
 945 }
 946
 947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 948 static bool
 949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 950                       int target, int refclk, intel_clock_t *best_clock)
 951 {
 952     intel_clock_t clock;
 953     if (target < 200000) {
 954         clock.p1 = 2;
 955         clock.p2 = 10;
 956         clock.n = 2;
 957         clock.m1 = 23;
 958         clock.m2 = 8;
 959     } else {
 960         clock.p1 = 1;
 961         clock.p2 = 10;
 962         clock.n = 1;
 963         clock.m1 = 14;
 964         clock.m2 = 2;
 965     }
 966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 967     clock.p = (clock.p1 * clock.p2);
 968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 969     clock.vco = 0;
 970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 971     return true;
 972 }
 973
 974 void
 975 intel_wait_for_vblank(struct drm_device *dev)
 976 {
 977         /* Wait for 20ms, i.e. one cycle at 50hz. */
 978         if (in_dbg_master())
 979                 mdelay(20); /* The kernel debugger cannot call msleep() */
 980         else
 981                 msleep(20);
 982 }
 983
 984 /* Parameters have changed, update FBC info */
 985 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 986 {
 987         struct drm_device *dev = crtc->dev;
 988         struct drm_i915_private *dev_priv = dev->dev_private;
 989         struct drm_framebuffer *fb = crtc->fb;
 990         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 991         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 993         int plane, i;
 994         u32 fbc_ctl, fbc_ctl2;
 995
 996         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 997
 998         if (fb->pitch < dev_priv->cfb_pitch)
 999                 dev_priv->cfb_pitch = fb->pitch;
1000
1001         /* FBC_CTL wants 64B units */
1002         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1003         dev_priv->cfb_fence = obj_priv->fence_reg;
1004         dev_priv->cfb_plane = intel_crtc->plane;
1005         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1006
1007         /* Clear old tags */
1008         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1009                 I915_WRITE(FBC_TAG + (i * 4), 0);
1010
1011         /* Set it up... */
1012         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1013         if (obj_priv->tiling_mode != I915_TILING_NONE)
1014                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1015         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1016         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1017
1018         /* enable it... */
1019         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1020         if (IS_I945GM(dev))
1021                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1022         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1023         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1024         if (obj_priv->tiling_mode != I915_TILING_NONE)
1025                 fbc_ctl |= dev_priv->cfb_fence;
1026         I915_WRITE(FBC_CONTROL, fbc_ctl);
1027
1028         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1029                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1030 }
1031
1032 void i8xx_disable_fbc(struct drm_device *dev)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1036         u32 fbc_ctl;
1037
1038         if (!I915_HAS_FBC(dev))
1039                 return;
1040
1041         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1042                 return; /* Already off, just return */
1043
1044         /* Disable compression */
1045         fbc_ctl = I915_READ(FBC_CONTROL);
1046         fbc_ctl &= ~FBC_CTL_EN;
1047         I915_WRITE(FBC_CONTROL, fbc_ctl);
1048
1049         /* Wait for compressing bit to clear */
1050         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1051                 if (time_after(jiffies, timeout)) {
1052                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1053                         break;
1054                 }
1055                 ; /* do nothing */
1056         }
1057
1058         intel_wait_for_vblank(dev);
1059
1060         DRM_DEBUG_KMS("disabled FBC\n");
1061 }
1062
1063 static bool i8xx_fbc_enabled(struct drm_device *dev)
1064 {
1065         struct drm_i915_private *dev_priv = dev->dev_private;
1066
1067         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1068 }
1069
1070 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1071 {
1072         struct drm_device *dev = crtc->dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         struct drm_framebuffer *fb = crtc->fb;
1075         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1076         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1078         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1079                      DPFC_CTL_PLANEB);
1080         unsigned long stall_watermark = 200;
1081         u32 dpfc_ctl;
1082
1083         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1084         dev_priv->cfb_fence = obj_priv->fence_reg;
1085         dev_priv->cfb_plane = intel_crtc->plane;
1086
1087         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1088         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1089                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1090                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1091         } else {
1092                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1093         }
1094
1095         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1096         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1097                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1098                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1099         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1100
1101         /* enable it... */
1102         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1103
1104         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1105 }
1106
1107 void g4x_disable_fbc(struct drm_device *dev)
1108 {
1109         struct drm_i915_private *dev_priv = dev->dev_private;
1110         u32 dpfc_ctl;
1111
1112         /* Disable compression */
1113         dpfc_ctl = I915_READ(DPFC_CONTROL);
1114         dpfc_ctl &= ~DPFC_CTL_EN;
1115         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1116         intel_wait_for_vblank(dev);
1117
1118         DRM_DEBUG_KMS("disabled FBC\n");
1119 }
1120
1121 static bool g4x_fbc_enabled(struct drm_device *dev)
1122 {
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124
1125         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1126 }
1127
1128 bool intel_fbc_enabled(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         if (!dev_priv->display.fbc_enabled)
1133                 return false;
1134
1135         return dev_priv->display.fbc_enabled(dev);
1136 }
1137
1138 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1139 {
1140         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1141
1142         if (!dev_priv->display.enable_fbc)
1143                 return;
1144
1145         dev_priv->display.enable_fbc(crtc, interval);
1146 }
1147
1148 void intel_disable_fbc(struct drm_device *dev)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151
1152         if (!dev_priv->display.disable_fbc)
1153                 return;
1154
1155         dev_priv->display.disable_fbc(dev);
1156 }
1157
1158 /**
1159  * intel_update_fbc - enable/disable FBC as needed
1160  * @crtc: CRTC to point the compressor at
1161  * @mode: mode in use
1162  *
1163  * Set up the framebuffer compression hardware at mode set time.  We
1164  * enable it if possible:
1165  *   - plane A only (on pre-965)
1166  *   - no pixel mulitply/line duplication
1167  *   - no alpha buffer discard
1168  *   - no dual wide
1169  *   - framebuffer <= 2048 in width, 1536 in height
1170  *
1171  * We can't assume that any compression will take place (worst case),
1172  * so the compressed buffer has to be the same size as the uncompressed
1173  * one.  It also must reside (along with the line length buffer) in
1174  * stolen memory.
1175  *
1176  * We need to enable/disable FBC on a global basis.
1177  */
1178 static void intel_update_fbc(struct drm_crtc *crtc,
1179                              struct drm_display_mode *mode)
1180 {
1181         struct drm_device *dev = crtc->dev;
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183         struct drm_framebuffer *fb = crtc->fb;
1184         struct intel_framebuffer *intel_fb;
1185         struct drm_i915_gem_object *obj_priv;
1186         struct drm_crtc *tmp_crtc;
1187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188         int plane = intel_crtc->plane;
1189         int crtcs_enabled = 0;
1190
1191         DRM_DEBUG_KMS("\n");
1192
1193         if (!i915_powersave)
1194                 return;
1195
1196         if (!I915_HAS_FBC(dev))
1197                 return;
1198
1199         if (!crtc->fb)
1200                 return;
1201
1202         intel_fb = to_intel_framebuffer(fb);
1203         obj_priv = to_intel_bo(intel_fb->obj);
1204
1205         /*
1206          * If FBC is already on, we just have to verify that we can
1207          * keep it that way...
1208          * Need to disable if:
1209          *   - more than one pipe is active
1210          *   - changing FBC params (stride, fence, mode)
1211          *   - new fb is too large to fit in compressed buffer
1212          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1213          */
1214         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1215                 if (tmp_crtc->enabled)
1216                         crtcs_enabled++;
1217         }
1218         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1219         if (crtcs_enabled > 1) {
1220                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1221                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1222                 goto out_disable;
1223         }
1224         if (intel_fb->obj->size > dev_priv->cfb_size) {
1225                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1226                                 "compression\n");
1227                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1228                 goto out_disable;
1229         }
1230         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1231             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1232                 DRM_DEBUG_KMS("mode incompatible with compression, "
1233                                 "disabling\n");
1234                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1235                 goto out_disable;
1236         }
1237         if ((mode->hdisplay > 2048) ||
1238             (mode->vdisplay > 1536)) {
1239                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1240                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1241                 goto out_disable;
1242         }
1243         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1244                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1245                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1246                 goto out_disable;
1247         }
1248         if (obj_priv->tiling_mode != I915_TILING_X) {
1249                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1250                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1251                 goto out_disable;
1252         }
1253
1254         /* If the kernel debugger is active, always disable compression */
1255         if (in_dbg_master())
1256                 goto out_disable;
1257
1258         if (intel_fbc_enabled(dev)) {
1259                 /* We can re-enable it in this case, but need to update pitch */
1260                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1261                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1262                     (plane != dev_priv->cfb_plane))
1263                         intel_disable_fbc(dev);
1264         }
1265
1266         /* Now try to turn it back on if possible */
1267         if (!intel_fbc_enabled(dev))
1268                 intel_enable_fbc(crtc, 500);
1269
1270         return;
1271
1272 out_disable:
1273         /* Multiple disables should be harmless */
1274         if (intel_fbc_enabled(dev)) {
1275                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1276                 intel_disable_fbc(dev);
1277         }
1278 }
1279
1280 int
1281 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1282 {
1283         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1284         u32 alignment;
1285         int ret;
1286
1287         switch (obj_priv->tiling_mode) {
1288         case I915_TILING_NONE:
1289                 alignment = 64 * 1024;
1290                 break;
1291         case I915_TILING_X:
1292                 /* pin() will align the object as required by fence */
1293                 alignment = 0;
1294                 break;
1295         case I915_TILING_Y:
1296                 /* FIXME: Is this true? */
1297                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1298                 return -EINVAL;
1299         default:
1300                 BUG();
1301         }
1302
1303         ret = i915_gem_object_pin(obj, alignment);
1304         if (ret != 0)
1305                 return ret;
1306
1307         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1308          * fence, whereas 965+ only requires a fence if using
1309          * framebuffer compression.  For simplicity, we always install
1310          * a fence as the cost is not that onerous.
1311          */
1312         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1313             obj_priv->tiling_mode != I915_TILING_NONE) {
1314                 ret = i915_gem_object_get_fence_reg(obj);
1315                 if (ret != 0) {
1316                         i915_gem_object_unpin(obj);
1317                         return ret;
1318                 }
1319         }
1320
1321         return 0;
1322 }
1323
1324 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1325 static int
1326 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1327                            int x, int y)
1328 {
1329         struct drm_device *dev = crtc->dev;
1330         struct drm_i915_private *dev_priv = dev->dev_private;
1331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1332         struct intel_framebuffer *intel_fb;
1333         struct drm_i915_gem_object *obj_priv;
1334         struct drm_gem_object *obj;
1335         int plane = intel_crtc->plane;
1336         unsigned long Start, Offset;
1337         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1338         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1339         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1340         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1341         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1342         u32 dspcntr;
1343
1344         switch (plane) {
1345         case 0:
1346         case 1:
1347                 break;
1348         default:
1349                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1350                 return -EINVAL;
1351         }
1352
1353         intel_fb = to_intel_framebuffer(fb);
1354         obj = intel_fb->obj;
1355         obj_priv = to_intel_bo(obj);
1356
1357         dspcntr = I915_READ(dspcntr_reg);
1358         /* Mask out pixel format bits in case we change it */
1359         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1360         switch (fb->bits_per_pixel) {
1361         case 8:
1362                 dspcntr |= DISPPLANE_8BPP;
1363                 break;
1364         case 16:
1365                 if (fb->depth == 15)
1366                         dspcntr |= DISPPLANE_15_16BPP;
1367                 else
1368                         dspcntr |= DISPPLANE_16BPP;
1369                 break;
1370         case 24:
1371         case 32:
1372                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1373                 break;
1374         default:
1375                 DRM_ERROR("Unknown color depth\n");
1376                 return -EINVAL;
1377         }
1378         if (IS_I965G(dev)) {
1379                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1380                         dspcntr |= DISPPLANE_TILED;
1381                 else
1382                         dspcntr &= ~DISPPLANE_TILED;
1383         }
1384
1385         if (IS_IRONLAKE(dev))
1386                 /* must disable */
1387                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1388
1389         I915_WRITE(dspcntr_reg, dspcntr);
1390
1391         Start = obj_priv->gtt_offset;
1392         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1393
1394         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1395         I915_WRITE(dspstride, fb->pitch);
1396         if (IS_I965G(dev)) {
1397                 I915_WRITE(dspbase, Offset);
1398                 I915_READ(dspbase);
1399                 I915_WRITE(dspsurf, Start);
1400                 I915_READ(dspsurf);
1401                 I915_WRITE(dsptileoff, (y << 16) | x);
1402         } else {
1403                 I915_WRITE(dspbase, Start + Offset);
1404                 I915_READ(dspbase);
1405         }
1406
1407         if ((IS_I965G(dev) || plane == 0))
1408                 intel_update_fbc(crtc, &crtc->mode);
1409
1410         intel_wait_for_vblank(dev);
1411         intel_increase_pllclock(crtc, true);
1412
1413         return 0;
1414 }
1415
1416 static int
1417 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1418                     struct drm_framebuffer *old_fb)
1419 {
1420         struct drm_device *dev = crtc->dev;
1421         struct drm_i915_private *dev_priv = dev->dev_private;
1422         struct drm_i915_master_private *master_priv;
1423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1424         struct intel_framebuffer *intel_fb;
1425         struct drm_i915_gem_object *obj_priv;
1426         struct drm_gem_object *obj;
1427         int pipe = intel_crtc->pipe;
1428         int plane = intel_crtc->plane;
1429         unsigned long Start, Offset;
1430         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1431         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1432         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1433         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1434         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1435         u32 dspcntr;
1436         int ret;
1437
1438         /* no fb bound */
1439         if (!crtc->fb) {
1440                 DRM_DEBUG_KMS("No FB bound\n");
1441                 return 0;
1442         }
1443
1444         switch (plane) {
1445         case 0:
1446         case 1:
1447                 break;
1448         default:
1449                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1450                 return -EINVAL;
1451         }
1452
1453         intel_fb = to_intel_framebuffer(crtc->fb);
1454         obj = intel_fb->obj;
1455         obj_priv = to_intel_bo(obj);
1456
1457         mutex_lock(&dev->struct_mutex);
1458         ret = intel_pin_and_fence_fb_obj(dev, obj);
1459         if (ret != 0) {
1460                 mutex_unlock(&dev->struct_mutex);
1461                 return ret;
1462         }
1463
1464         ret = i915_gem_object_set_to_display_plane(obj);
1465         if (ret != 0) {
1466                 i915_gem_object_unpin(obj);
1467                 mutex_unlock(&dev->struct_mutex);
1468                 return ret;
1469         }
1470
1471         dspcntr = I915_READ(dspcntr_reg);
1472         /* Mask out pixel format bits in case we change it */
1473         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1474         switch (crtc->fb->bits_per_pixel) {
1475         case 8:
1476                 dspcntr |= DISPPLANE_8BPP;
1477                 break;
1478         case 16:
1479                 if (crtc->fb->depth == 15)
1480                         dspcntr |= DISPPLANE_15_16BPP;
1481                 else
1482                         dspcntr |= DISPPLANE_16BPP;
1483                 break;
1484         case 24:
1485         case 32:
1486                 if (crtc->fb->depth == 30)
1487                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1488                 else
1489                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1490                 break;
1491         default:
1492                 DRM_ERROR("Unknown color depth\n");
1493                 i915_gem_object_unpin(obj);
1494                 mutex_unlock(&dev->struct_mutex);
1495                 return -EINVAL;
1496         }
1497         if (IS_I965G(dev)) {
1498                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1499                         dspcntr |= DISPPLANE_TILED;
1500                 else
1501                         dspcntr &= ~DISPPLANE_TILED;
1502         }
1503
1504         if (HAS_PCH_SPLIT(dev))
1505                 /* must disable */
1506                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1507
1508         I915_WRITE(dspcntr_reg, dspcntr);
1509
1510         Start = obj_priv->gtt_offset;
1511         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1512
1513         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1514                       Start, Offset, x, y, crtc->fb->pitch);
1515         I915_WRITE(dspstride, crtc->fb->pitch);
1516         if (IS_I965G(dev)) {
1517                 I915_WRITE(dspbase, Offset);
1518                 I915_READ(dspbase);
1519                 I915_WRITE(dspsurf, Start);
1520                 I915_READ(dspsurf);
1521                 I915_WRITE(dsptileoff, (y << 16) | x);
1522         } else {
1523                 I915_WRITE(dspbase, Start + Offset);
1524                 I915_READ(dspbase);
1525         }
1526
1527         if ((IS_I965G(dev) || plane == 0))
1528                 intel_update_fbc(crtc, &crtc->mode);
1529
1530         intel_wait_for_vblank(dev);
1531
1532         if (old_fb) {
1533                 intel_fb = to_intel_framebuffer(old_fb);
1534                 obj_priv = to_intel_bo(intel_fb->obj);
1535                 i915_gem_object_unpin(intel_fb->obj);
1536         }
1537         intel_increase_pllclock(crtc, true);
1538
1539         mutex_unlock(&dev->struct_mutex);
1540
1541         if (!dev->primary->master)
1542                 return 0;
1543
1544         master_priv = dev->primary->master->driver_priv;
1545         if (!master_priv->sarea_priv)
1546                 return 0;
1547
1548         if (pipe) {
1549                 master_priv->sarea_priv->pipeB_x = x;
1550                 master_priv->sarea_priv->pipeB_y = y;
1551         } else {
1552                 master_priv->sarea_priv->pipeA_x = x;
1553                 master_priv->sarea_priv->pipeA_y = y;
1554         }
1555
1556         return 0;
1557 }
1558
1559 /* Disable the VGA plane that we never use */
1560 static void i915_disable_vga (struct drm_device *dev)
1561 {
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         u8 sr1;
1564         u32 vga_reg;
1565
1566         if (HAS_PCH_SPLIT(dev))
1567                 vga_reg = CPU_VGACNTRL;
1568         else
1569                 vga_reg = VGACNTRL;
1570
1571         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1572                 return;
1573
1574         I915_WRITE8(VGA_SR_INDEX, 1);
1575         sr1 = I915_READ8(VGA_SR_DATA);
1576         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1577         udelay(100);
1578
1579         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1580 }
1581
1582 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1583 {
1584         struct drm_device *dev = crtc->dev;
1585         struct drm_i915_private *dev_priv = dev->dev_private;
1586         u32 dpa_ctl;
1587
1588         DRM_DEBUG_KMS("\n");
1589         dpa_ctl = I915_READ(DP_A);
1590         dpa_ctl &= ~DP_PLL_ENABLE;
1591         I915_WRITE(DP_A, dpa_ctl);
1592 }
1593
1594 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1595 {
1596         struct drm_device *dev = crtc->dev;
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         u32 dpa_ctl;
1599
1600         dpa_ctl = I915_READ(DP_A);
1601         dpa_ctl |= DP_PLL_ENABLE;
1602         I915_WRITE(DP_A, dpa_ctl);
1603         udelay(200);
1604 }
1605
1606
1607 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1608 {
1609         struct drm_device *dev = crtc->dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         u32 dpa_ctl;
1612
1613         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1614         dpa_ctl = I915_READ(DP_A);
1615         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1616
1617         if (clock < 200000) {
1618                 u32 temp;
1619                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1620                 /* workaround for 160Mhz:
1621                    1) program 0x4600c bits 15:0 = 0x8124
1622                    2) program 0x46010 bit 0 = 1
1623                    3) program 0x46034 bit 24 = 1
1624                    4) program 0x64000 bit 14 = 1
1625                    */
1626                 temp = I915_READ(0x4600c);
1627                 temp &= 0xffff0000;
1628                 I915_WRITE(0x4600c, temp | 0x8124);
1629
1630                 temp = I915_READ(0x46010);
1631                 I915_WRITE(0x46010, temp | 1);
1632
1633                 temp = I915_READ(0x46034);
1634                 I915_WRITE(0x46034, temp | (1 << 24));
1635         } else {
1636                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1637         }
1638         I915_WRITE(DP_A, dpa_ctl);
1639
1640         udelay(500);
1641 }
1642
1643 /* The FDI link training functions for ILK/Ibexpeak. */
1644 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1645 {
1646         struct drm_device *dev = crtc->dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1649         int pipe = intel_crtc->pipe;
1650         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1651         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1652         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1653         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1654         u32 temp, tries = 0;
1655
1656         /* enable CPU FDI TX and PCH FDI RX */
1657         temp = I915_READ(fdi_tx_reg);
1658         temp |= FDI_TX_ENABLE;
1659         temp &= ~(7 << 19);
1660         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1661         temp &= ~FDI_LINK_TRAIN_NONE;
1662         temp |= FDI_LINK_TRAIN_PATTERN_1;
1663         I915_WRITE(fdi_tx_reg, temp);
1664         I915_READ(fdi_tx_reg);
1665
1666         temp = I915_READ(fdi_rx_reg);
1667         temp &= ~FDI_LINK_TRAIN_NONE;
1668         temp |= FDI_LINK_TRAIN_PATTERN_1;
1669         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1670         I915_READ(fdi_rx_reg);
1671         udelay(150);
1672
1673         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1674            for train result */
1675         temp = I915_READ(fdi_rx_imr_reg);
1676         temp &= ~FDI_RX_SYMBOL_LOCK;
1677         temp &= ~FDI_RX_BIT_LOCK;
1678         I915_WRITE(fdi_rx_imr_reg, temp);
1679         I915_READ(fdi_rx_imr_reg);
1680         udelay(150);
1681
1682         for (;;) {
1683                 temp = I915_READ(fdi_rx_iir_reg);
1684                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1685
1686                 if ((temp & FDI_RX_BIT_LOCK)) {
1687                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1688                         I915_WRITE(fdi_rx_iir_reg,
1689                                    temp | FDI_RX_BIT_LOCK);
1690                         break;
1691                 }
1692
1693                 tries++;
1694
1695                 if (tries > 5) {
1696                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1697                         break;
1698                 }
1699         }
1700
1701         /* Train 2 */
1702         temp = I915_READ(fdi_tx_reg);
1703         temp &= ~FDI_LINK_TRAIN_NONE;
1704         temp |= FDI_LINK_TRAIN_PATTERN_2;
1705         I915_WRITE(fdi_tx_reg, temp);
1706
1707         temp = I915_READ(fdi_rx_reg);
1708         temp &= ~FDI_LINK_TRAIN_NONE;
1709         temp |= FDI_LINK_TRAIN_PATTERN_2;
1710         I915_WRITE(fdi_rx_reg, temp);
1711         udelay(150);
1712
1713         tries = 0;
1714
1715         for (;;) {
1716                 temp = I915_READ(fdi_rx_iir_reg);
1717                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1718
1719                 if (temp & FDI_RX_SYMBOL_LOCK) {
1720                         I915_WRITE(fdi_rx_iir_reg,
1721                                    temp | FDI_RX_SYMBOL_LOCK);
1722                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1723                         break;
1724                 }
1725
1726                 tries++;
1727
1728                 if (tries > 5) {
1729                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1730                         break;
1731                 }
1732         }
1733
1734         DRM_DEBUG_KMS("FDI train done\n");
1735 }
1736
1737 static int snb_b_fdi_train_param [] = {
1738         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1739         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1740         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1741         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1742 };
1743
1744 /* The FDI link training functions for SNB/Cougarpoint. */
1745 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1746 {
1747         struct drm_device *dev = crtc->dev;
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1750         int pipe = intel_crtc->pipe;
1751         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1752         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1753         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1754         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1755         u32 temp, i;
1756
1757         /* enable CPU FDI TX and PCH FDI RX */
1758         temp = I915_READ(fdi_tx_reg);
1759         temp |= FDI_TX_ENABLE;
1760         temp &= ~(7 << 19);
1761         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1762         temp &= ~FDI_LINK_TRAIN_NONE;
1763         temp |= FDI_LINK_TRAIN_PATTERN_1;
1764         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1765         /* SNB-B */
1766         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1767         I915_WRITE(fdi_tx_reg, temp);
1768         I915_READ(fdi_tx_reg);
1769
1770         temp = I915_READ(fdi_rx_reg);
1771         if (HAS_PCH_CPT(dev)) {
1772                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1773                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1774         } else {
1775                 temp &= ~FDI_LINK_TRAIN_NONE;
1776                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1777         }
1778         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1779         I915_READ(fdi_rx_reg);
1780         udelay(150);
1781
1782         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1783            for train result */
1784         temp = I915_READ(fdi_rx_imr_reg);
1785         temp &= ~FDI_RX_SYMBOL_LOCK;
1786         temp &= ~FDI_RX_BIT_LOCK;
1787         I915_WRITE(fdi_rx_imr_reg, temp);
1788         I915_READ(fdi_rx_imr_reg);
1789         udelay(150);
1790
1791         for (i = 0; i < 4; i++ ) {
1792                 temp = I915_READ(fdi_tx_reg);
1793                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1794                 temp |= snb_b_fdi_train_param[i];
1795                 I915_WRITE(fdi_tx_reg, temp);
1796                 udelay(500);
1797
1798                 temp = I915_READ(fdi_rx_iir_reg);
1799                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1800
1801                 if (temp & FDI_RX_BIT_LOCK) {
1802                         I915_WRITE(fdi_rx_iir_reg,
1803                                    temp | FDI_RX_BIT_LOCK);
1804                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1805                         break;
1806                 }
1807         }
1808         if (i == 4)
1809                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1810
1811         /* Train 2 */
1812         temp = I915_READ(fdi_tx_reg);
1813         temp &= ~FDI_LINK_TRAIN_NONE;
1814         temp |= FDI_LINK_TRAIN_PATTERN_2;
1815         if (IS_GEN6(dev)) {
1816                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1817                 /* SNB-B */
1818                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1819         }
1820         I915_WRITE(fdi_tx_reg, temp);
1821
1822         temp = I915_READ(fdi_rx_reg);
1823         if (HAS_PCH_CPT(dev)) {
1824                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1825                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1826         } else {
1827                 temp &= ~FDI_LINK_TRAIN_NONE;
1828                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1829         }
1830         I915_WRITE(fdi_rx_reg, temp);
1831         udelay(150);
1832
1833         for (i = 0; i < 4; i++ ) {
1834                 temp = I915_READ(fdi_tx_reg);
1835                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1836                 temp |= snb_b_fdi_train_param[i];
1837                 I915_WRITE(fdi_tx_reg, temp);
1838                 udelay(500);
1839
1840                 temp = I915_READ(fdi_rx_iir_reg);
1841                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1842
1843                 if (temp & FDI_RX_SYMBOL_LOCK) {
1844                         I915_WRITE(fdi_rx_iir_reg,
1845                                    temp | FDI_RX_SYMBOL_LOCK);
1846                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1847                         break;
1848                 }
1849         }
1850         if (i == 4)
1851                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1852
1853         DRM_DEBUG_KMS("FDI train done.\n");
1854 }
1855
1856 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1857 {
1858         struct drm_device *dev = crtc->dev;
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1861         int pipe = intel_crtc->pipe;
1862         int plane = intel_crtc->plane;
1863         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1864         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1865         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1866         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1867         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1868         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1869         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1870         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1871         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1872         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1873         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1874         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1875         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1876         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1877         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1878         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1879         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1880         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1881         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1882         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1883         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1884         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1885         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1886         u32 temp;
1887         int n;
1888         u32 pipe_bpc;
1889
1890         temp = I915_READ(pipeconf_reg);
1891         pipe_bpc = temp & PIPE_BPC_MASK;
1892
1893         /* XXX: When our outputs are all unaware of DPMS modes other than off
1894          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1895          */
1896         switch (mode) {
1897         case DRM_MODE_DPMS_ON:
1898         case DRM_MODE_DPMS_STANDBY:
1899         case DRM_MODE_DPMS_SUSPEND:
1900                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1901
1902                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1903                         temp = I915_READ(PCH_LVDS);
1904                         if ((temp & LVDS_PORT_EN) == 0) {
1905                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1906                                 POSTING_READ(PCH_LVDS);
1907                         }
1908                 }
1909
1910                 if (HAS_eDP) {
1911                         /* enable eDP PLL */
1912                         ironlake_enable_pll_edp(crtc);
1913                 } else {
1914
1915                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1916                         temp = I915_READ(fdi_rx_reg);
1917                         /*
1918                          * make the BPC in FDI Rx be consistent with that in
1919                          * pipeconf reg.
1920                          */
1921                         temp &= ~(0x7 << 16);
1922                         temp |= (pipe_bpc << 11);
1923                         temp &= ~(7 << 19);
1924                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1925                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1926                         I915_READ(fdi_rx_reg);
1927                         udelay(200);
1928
1929                         /* Switch from Rawclk to PCDclk */
1930                         temp = I915_READ(fdi_rx_reg);
1931                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1932                         I915_READ(fdi_rx_reg);
1933                         udelay(200);
1934
1935                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1936                         temp = I915_READ(fdi_tx_reg);
1937                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1938                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1939                                 I915_READ(fdi_tx_reg);
1940                                 udelay(100);
1941                         }
1942                 }
1943
1944                 /* Enable panel fitting for LVDS */
1945                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1946                         temp = I915_READ(pf_ctl_reg);
1947                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1948
1949                         /* currently full aspect */
1950                         I915_WRITE(pf_win_pos, 0);
1951
1952                         I915_WRITE(pf_win_size,
1953                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1954                                    (dev_priv->panel_fixed_mode->vdisplay));
1955                 }
1956
1957                 /* Enable CPU pipe */
1958                 temp = I915_READ(pipeconf_reg);
1959                 if ((temp & PIPEACONF_ENABLE) == 0) {
1960                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1961                         I915_READ(pipeconf_reg);
1962                         udelay(100);
1963                 }
1964
1965                 /* configure and enable CPU plane */
1966                 temp = I915_READ(dspcntr_reg);
1967                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1968                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1969                         /* Flush the plane changes */
1970                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1971                 }
1972
1973                 if (!HAS_eDP) {
1974                         /* For PCH output, training FDI link */
1975                         if (IS_GEN6(dev))
1976                                 gen6_fdi_link_train(crtc);
1977                         else
1978                                 ironlake_fdi_link_train(crtc);
1979
1980                         /* enable PCH DPLL */
1981                         temp = I915_READ(pch_dpll_reg);
1982                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1983                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1984                                 I915_READ(pch_dpll_reg);
1985                         }
1986                         udelay(200);
1987
1988                         if (HAS_PCH_CPT(dev)) {
1989                                 /* Be sure PCH DPLL SEL is set */
1990                                 temp = I915_READ(PCH_DPLL_SEL);
1991                                 if (trans_dpll_sel == 0 &&
1992                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1993                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1994                                 else if (trans_dpll_sel == 1 &&
1995                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1996                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1997                                 I915_WRITE(PCH_DPLL_SEL, temp);
1998                                 I915_READ(PCH_DPLL_SEL);
1999                         }
2000
2001                         /* set transcoder timing */
2002                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2003                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2004                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2005
2006                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2007                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2008                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2009
2010                         /* enable normal train */
2011                         temp = I915_READ(fdi_tx_reg);
2012                         temp &= ~FDI_LINK_TRAIN_NONE;
2013                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2014                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2015                         I915_READ(fdi_tx_reg);
2016
2017                         temp = I915_READ(fdi_rx_reg);
2018                         if (HAS_PCH_CPT(dev)) {
2019                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2020                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2021                         } else {
2022                                 temp &= ~FDI_LINK_TRAIN_NONE;
2023                                 temp |= FDI_LINK_TRAIN_NONE;
2024                         }
2025                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2026                         I915_READ(fdi_rx_reg);
2027
2028                         /* wait one idle pattern time */
2029                         udelay(100);
2030
2031                         /* For PCH DP, enable TRANS_DP_CTL */
2032                         if (HAS_PCH_CPT(dev) &&
2033                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2034                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2035                                 int reg;
2036
2037                                 reg = I915_READ(trans_dp_ctl);
2038                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
2039                                 reg = TRANS_DP_OUTPUT_ENABLE |
2040                                       TRANS_DP_ENH_FRAMING |
2041                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
2042                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
2043
2044                                 switch (intel_trans_dp_port_sel(crtc)) {
2045                                 case PCH_DP_B:
2046                                         reg |= TRANS_DP_PORT_SEL_B;
2047                                         break;
2048                                 case PCH_DP_C:
2049                                         reg |= TRANS_DP_PORT_SEL_C;
2050                                         break;
2051                                 case PCH_DP_D:
2052                                         reg |= TRANS_DP_PORT_SEL_D;
2053                                         break;
2054                                 default:
2055                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2056                                         reg |= TRANS_DP_PORT_SEL_B;
2057                                         break;
2058                                 }
2059
2060                                 I915_WRITE(trans_dp_ctl, reg);
2061                                 POSTING_READ(trans_dp_ctl);
2062                         }
2063
2064                         /* enable PCH transcoder */
2065                         temp = I915_READ(transconf_reg);
2066                         /*
2067                          * make the BPC in transcoder be consistent with
2068                          * that in pipeconf reg.
2069                          */
2070                         temp &= ~PIPE_BPC_MASK;
2071                         temp |= pipe_bpc;
2072                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2073                         I915_READ(transconf_reg);
2074
2075                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2076                                 ;
2077
2078                 }
2079
2080                 intel_crtc_load_lut(crtc);
2081
2082         break;
2083         case DRM_MODE_DPMS_OFF:
2084                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2085
2086                 drm_vblank_off(dev, pipe);
2087                 /* Disable display plane */
2088                 temp = I915_READ(dspcntr_reg);
2089                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2090                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2091                         /* Flush the plane changes */
2092                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2093                         I915_READ(dspbase_reg);
2094                 }
2095
2096                 i915_disable_vga(dev);
2097
2098                 /* disable cpu pipe, disable after all planes disabled */
2099                 temp = I915_READ(pipeconf_reg);
2100                 if ((temp & PIPEACONF_ENABLE) != 0) {
2101                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2102                         I915_READ(pipeconf_reg);
2103                         n = 0;
2104                         /* wait for cpu pipe off, pipe state */
2105                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2106                                 n++;
2107                                 if (n < 60) {
2108                                         udelay(500);
2109                                         continue;
2110                                 } else {
2111                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2112                                                                 pipe);
2113                                         break;
2114                                 }
2115                         }
2116                 } else
2117                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2118
2119                 udelay(100);
2120
2121                 /* Disable PF */
2122                 temp = I915_READ(pf_ctl_reg);
2123                 if ((temp & PF_ENABLE) != 0) {
2124                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2125                         I915_READ(pf_ctl_reg);
2126                 }
2127                 I915_WRITE(pf_win_size, 0);
2128                 POSTING_READ(pf_win_size);
2129
2130
2131                 /* disable CPU FDI tx and PCH FDI rx */
2132                 temp = I915_READ(fdi_tx_reg);
2133                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2134                 I915_READ(fdi_tx_reg);
2135
2136                 temp = I915_READ(fdi_rx_reg);
2137                 /* BPC in FDI rx is consistent with that in pipeconf */
2138                 temp &= ~(0x07 << 16);
2139                 temp |= (pipe_bpc << 11);
2140                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2141                 I915_READ(fdi_rx_reg);
2142
2143                 udelay(100);
2144
2145                 /* still set train pattern 1 */
2146                 temp = I915_READ(fdi_tx_reg);
2147                 temp &= ~FDI_LINK_TRAIN_NONE;
2148                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2149                 I915_WRITE(fdi_tx_reg, temp);
2150                 POSTING_READ(fdi_tx_reg);
2151
2152                 temp = I915_READ(fdi_rx_reg);
2153                 if (HAS_PCH_CPT(dev)) {
2154                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2155                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2156                 } else {
2157                         temp &= ~FDI_LINK_TRAIN_NONE;
2158                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2159                 }
2160                 I915_WRITE(fdi_rx_reg, temp);
2161                 POSTING_READ(fdi_rx_reg);
2162
2163                 udelay(100);
2164
2165                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2166                         temp = I915_READ(PCH_LVDS);
2167                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2168                         I915_READ(PCH_LVDS);
2169                         udelay(100);
2170                 }
2171
2172                 /* disable PCH transcoder */
2173                 temp = I915_READ(transconf_reg);
2174                 if ((temp & TRANS_ENABLE) != 0) {
2175                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2176                         I915_READ(transconf_reg);
2177                         n = 0;
2178                         /* wait for PCH transcoder off, transcoder state */
2179                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2180                                 n++;
2181                                 if (n < 60) {
2182                                         udelay(500);
2183                                         continue;
2184                                 } else {
2185                                         DRM_DEBUG_KMS("transcoder %d off "
2186                                                         "delay\n", pipe);
2187                                         break;
2188                                 }
2189                         }
2190                 }
2191
2192                 temp = I915_READ(transconf_reg);
2193                 /* BPC in transcoder is consistent with that in pipeconf */
2194                 temp &= ~PIPE_BPC_MASK;
2195                 temp |= pipe_bpc;
2196                 I915_WRITE(transconf_reg, temp);
2197                 I915_READ(transconf_reg);
2198                 udelay(100);
2199
2200                 if (HAS_PCH_CPT(dev)) {
2201                         /* disable TRANS_DP_CTL */
2202                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2203                         int reg;
2204
2205                         reg = I915_READ(trans_dp_ctl);
2206                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2207                         I915_WRITE(trans_dp_ctl, reg);
2208                         POSTING_READ(trans_dp_ctl);
2209
2210                         /* disable DPLL_SEL */
2211                         temp = I915_READ(PCH_DPLL_SEL);
2212                         if (trans_dpll_sel == 0)
2213                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2214                         else
2215                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2216                         I915_WRITE(PCH_DPLL_SEL, temp);
2217                         I915_READ(PCH_DPLL_SEL);
2218
2219                 }
2220
2221                 /* disable PCH DPLL */
2222                 temp = I915_READ(pch_dpll_reg);
2223                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2224                 I915_READ(pch_dpll_reg);
2225
2226                 if (HAS_eDP) {
2227                         ironlake_disable_pll_edp(crtc);
2228                 }
2229
2230                 /* Switch from PCDclk to Rawclk */
2231                 temp = I915_READ(fdi_rx_reg);
2232                 temp &= ~FDI_SEL_PCDCLK;
2233                 I915_WRITE(fdi_rx_reg, temp);
2234                 I915_READ(fdi_rx_reg);
2235
2236                 /* Disable CPU FDI TX PLL */
2237                 temp = I915_READ(fdi_tx_reg);
2238                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2239                 I915_READ(fdi_tx_reg);
2240                 udelay(100);
2241
2242                 temp = I915_READ(fdi_rx_reg);
2243                 temp &= ~FDI_RX_PLL_ENABLE;
2244                 I915_WRITE(fdi_rx_reg, temp);
2245                 I915_READ(fdi_rx_reg);
2246
2247                 /* Wait for the clocks to turn off. */
2248                 udelay(100);
2249                 break;
2250         }
2251 }
2252
2253 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2254 {
2255         struct intel_overlay *overlay;
2256         int ret;
2257
2258         if (!enable && intel_crtc->overlay) {
2259                 overlay = intel_crtc->overlay;
2260                 mutex_lock(&overlay->dev->struct_mutex);
2261                 for (;;) {
2262                         ret = intel_overlay_switch_off(overlay);
2263                         if (ret == 0)
2264                                 break;
2265
2266                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2267                         if (ret != 0) {
2268                                 /* overlay doesn't react anymore. Usually
2269                                  * results in a black screen and an unkillable
2270                                  * X server. */
2271                                 BUG();
2272                                 overlay->hw_wedged = HW_WEDGED;
2273                                 break;
2274                         }
2275                 }
2276                 mutex_unlock(&overlay->dev->struct_mutex);
2277         }
2278         /* Let userspace switch the overlay on again. In most cases userspace
2279          * has to recompute where to put it anyway. */
2280
2281         return;
2282 }
2283
2284 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         int pipe = intel_crtc->pipe;
2290         int plane = intel_crtc->plane;
2291         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2292         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2293         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2294         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2295         u32 temp;
2296
2297         /* XXX: When our outputs are all unaware of DPMS modes other than off
2298          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2299          */
2300         switch (mode) {
2301         case DRM_MODE_DPMS_ON:
2302         case DRM_MODE_DPMS_STANDBY:
2303         case DRM_MODE_DPMS_SUSPEND:
2304                 intel_update_watermarks(dev);
2305
2306                 /* Enable the DPLL */
2307                 temp = I915_READ(dpll_reg);
2308                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2309                         I915_WRITE(dpll_reg, temp);
2310                         I915_READ(dpll_reg);
2311                         /* Wait for the clocks to stabilize. */
2312                         udelay(150);
2313                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2314                         I915_READ(dpll_reg);
2315                         /* Wait for the clocks to stabilize. */
2316                         udelay(150);
2317                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2318                         I915_READ(dpll_reg);
2319                         /* Wait for the clocks to stabilize. */
2320                         udelay(150);
2321                 }
2322
2323                 /* Enable the pipe */
2324                 temp = I915_READ(pipeconf_reg);
2325                 if ((temp & PIPEACONF_ENABLE) == 0)
2326                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2327
2328                 /* Enable the plane */
2329                 temp = I915_READ(dspcntr_reg);
2330                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2331                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2332                         /* Flush the plane changes */
2333                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2334                 }
2335
2336                 intel_crtc_load_lut(crtc);
2337
2338                 if ((IS_I965G(dev) || plane == 0))
2339                         intel_update_fbc(crtc, &crtc->mode);
2340
2341                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2342                 intel_crtc_dpms_overlay(intel_crtc, true);
2343         break;
2344         case DRM_MODE_DPMS_OFF:
2345                 intel_update_watermarks(dev);
2346
2347                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2348                 intel_crtc_dpms_overlay(intel_crtc, false);
2349                 drm_vblank_off(dev, pipe);
2350
2351                 if (dev_priv->cfb_plane == plane &&
2352                     dev_priv->display.disable_fbc)
2353                         dev_priv->display.disable_fbc(dev);
2354
2355                 /* Disable the VGA plane that we never use */
2356                 i915_disable_vga(dev);
2357
2358                 /* Disable display plane */
2359                 temp = I915_READ(dspcntr_reg);
2360                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2361                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2362                         /* Flush the plane changes */
2363                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2364                         I915_READ(dspbase_reg);
2365                 }
2366
2367                 if (!IS_I9XX(dev)) {
2368                         /* Wait for vblank for the disable to take effect */
2369                         intel_wait_for_vblank(dev);
2370                 }
2371
2372                 /* Don't disable pipe A or pipe A PLLs if needed */
2373                 if (pipeconf_reg == PIPEACONF &&
2374                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2375                         goto skip_pipe_off;
2376
2377                 /* Next, disable display pipes */
2378                 temp = I915_READ(pipeconf_reg);
2379                 if ((temp & PIPEACONF_ENABLE) != 0) {
2380                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2381                         I915_READ(pipeconf_reg);
2382                 }
2383
2384                 /* Wait for vblank for the disable to take effect. */
2385                 intel_wait_for_vblank(dev);
2386
2387                 temp = I915_READ(dpll_reg);
2388                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2389                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2390                         I915_READ(dpll_reg);
2391                 }
2392         skip_pipe_off:
2393                 /* Wait for the clocks to turn off. */
2394                 udelay(150);
2395                 break;
2396         }
2397 }
2398
2399 /**
2400  * Sets the power management mode of the pipe and plane.
2401  *
2402  * This code should probably grow support for turning the cursor off and back
2403  * on appropriately at the same time as we're turning the pipe off/on.
2404  */
2405 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2406 {
2407         struct drm_device *dev = crtc->dev;
2408         struct drm_i915_private *dev_priv = dev->dev_private;
2409         struct drm_i915_master_private *master_priv;
2410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411         int pipe = intel_crtc->pipe;
2412         bool enabled;
2413
2414         dev_priv->display.dpms(crtc, mode);
2415
2416         intel_crtc->dpms_mode = mode;
2417
2418         if (!dev->primary->master)
2419                 return;
2420
2421         master_priv = dev->primary->master->driver_priv;
2422         if (!master_priv->sarea_priv)
2423                 return;
2424
2425         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2426
2427         switch (pipe) {
2428         case 0:
2429                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2430                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2431                 break;
2432         case 1:
2433                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2434                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2435                 break;
2436         default:
2437                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2438                 break;
2439         }
2440 }
2441
2442 static void intel_crtc_prepare (struct drm_crtc *crtc)
2443 {
2444         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2445         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2446 }
2447
2448 static void intel_crtc_commit (struct drm_crtc *crtc)
2449 {
2450         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2451         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2452 }
2453
2454 void intel_encoder_prepare (struct drm_encoder *encoder)
2455 {
2456         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2457         /* lvds has its own version of prepare see intel_lvds_prepare */
2458         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2459 }
2460
2461 void intel_encoder_commit (struct drm_encoder *encoder)
2462 {
2463         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2464         /* lvds has its own version of commit see intel_lvds_commit */
2465         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2466 }
2467
2468 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2469                                   struct drm_display_mode *mode,
2470                                   struct drm_display_mode *adjusted_mode)
2471 {
2472         struct drm_device *dev = crtc->dev;
2473         if (HAS_PCH_SPLIT(dev)) {
2474                 /* FDI link clock is fixed at 2.7G */
2475                 if (mode->clock * 3 > 27000 * 4)
2476                         return MODE_CLOCK_HIGH;
2477         }
2478         return true;
2479 }
2480
2481 static int i945_get_display_clock_speed(struct drm_device *dev)
2482 {
2483         return 400000;
2484 }
2485
2486 static int i915_get_display_clock_speed(struct drm_device *dev)
2487 {
2488         return 333000;
2489 }
2490
2491 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2492 {
2493         return 200000;
2494 }
2495
2496 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2497 {
2498         u16 gcfgc = 0;
2499
2500         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2501
2502         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2503                 return 133000;
2504         else {
2505                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2506                 case GC_DISPLAY_CLOCK_333_MHZ:
2507                         return 333000;
2508                 default:
2509                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2510                         return 190000;
2511                 }
2512         }
2513 }
2514
2515 static int i865_get_display_clock_speed(struct drm_device *dev)
2516 {
2517         return 266000;
2518 }
2519
2520 static int i855_get_display_clock_speed(struct drm_device *dev)
2521 {
2522         u16 hpllcc = 0;
2523         /* Assume that the hardware is in the high speed state.  This
2524          * should be the default.
2525          */
2526         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2527         case GC_CLOCK_133_200:
2528         case GC_CLOCK_100_200:
2529                 return 200000;
2530         case GC_CLOCK_166_250:
2531                 return 250000;
2532         case GC_CLOCK_100_133:
2533                 return 133000;
2534         }
2535
2536         /* Shouldn't happen */
2537         return 0;
2538 }
2539
2540 static int i830_get_display_clock_speed(struct drm_device *dev)
2541 {
2542         return 133000;
2543 }
2544
2545 /**
2546  * Return the pipe currently connected to the panel fitter,
2547  * or -1 if the panel fitter is not present or not in use
2548  */
2549 int intel_panel_fitter_pipe (struct drm_device *dev)
2550 {
2551         struct drm_i915_private *dev_priv = dev->dev_private;
2552         u32  pfit_control;
2553
2554         /* i830 doesn't have a panel fitter */
2555         if (IS_I830(dev))
2556                 return -1;
2557
2558         pfit_control = I915_READ(PFIT_CONTROL);
2559
2560         /* See if the panel fitter is in use */
2561         if ((pfit_control & PFIT_ENABLE) == 0)
2562                 return -1;
2563
2564         /* 965 can place panel fitter on either pipe */
2565         if (IS_I965G(dev))
2566                 return (pfit_control >> 29) & 0x3;
2567
2568         /* older chips can only use pipe 1 */
2569         return 1;
2570 }
2571
2572 struct fdi_m_n {
2573         u32        tu;
2574         u32        gmch_m;
2575         u32        gmch_n;
2576         u32        link_m;
2577         u32        link_n;
2578 };
2579
2580 static void
2581 fdi_reduce_ratio(u32 *num, u32 *den)
2582 {
2583         while (*num > 0xffffff || *den > 0xffffff) {
2584                 *num >>= 1;
2585                 *den >>= 1;
2586         }
2587 }
2588
2589 #define DATA_N 0x800000
2590 #define LINK_N 0x80000
2591
2592 static void
2593 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2594                      int link_clock, struct fdi_m_n *m_n)
2595 {
2596         u64 temp;
2597
2598         m_n->tu = 64; /* default size */
2599
2600         temp = (u64) DATA_N * pixel_clock;
2601         temp = div_u64(temp, link_clock);
2602         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2603         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2604         m_n->gmch_n = DATA_N;
2605         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2606
2607         temp = (u64) LINK_N * pixel_clock;
2608         m_n->link_m = div_u64(temp, link_clock);
2609         m_n->link_n = LINK_N;
2610         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2611 }
2612
2613
2614 struct intel_watermark_params {
2615         unsigned long fifo_size;
2616         unsigned long max_wm;
2617         unsigned long default_wm;
2618         unsigned long guard_size;
2619         unsigned long cacheline_size;
2620 };
2621
2622 /* Pineview has different values for various configs */
2623 static struct intel_watermark_params pineview_display_wm = {
2624         PINEVIEW_DISPLAY_FIFO,
2625         PINEVIEW_MAX_WM,
2626         PINEVIEW_DFT_WM,
2627         PINEVIEW_GUARD_WM,
2628         PINEVIEW_FIFO_LINE_SIZE
2629 };
2630 static struct intel_watermark_params pineview_display_hplloff_wm = {
2631         PINEVIEW_DISPLAY_FIFO,
2632         PINEVIEW_MAX_WM,
2633         PINEVIEW_DFT_HPLLOFF_WM,
2634         PINEVIEW_GUARD_WM,
2635         PINEVIEW_FIFO_LINE_SIZE
2636 };
2637 static struct intel_watermark_params pineview_cursor_wm = {
2638         PINEVIEW_CURSOR_FIFO,
2639         PINEVIEW_CURSOR_MAX_WM,
2640         PINEVIEW_CURSOR_DFT_WM,
2641         PINEVIEW_CURSOR_GUARD_WM,
2642         PINEVIEW_FIFO_LINE_SIZE,
2643 };
2644 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2645         PINEVIEW_CURSOR_FIFO,
2646         PINEVIEW_CURSOR_MAX_WM,
2647         PINEVIEW_CURSOR_DFT_WM,
2648         PINEVIEW_CURSOR_GUARD_WM,
2649         PINEVIEW_FIFO_LINE_SIZE
2650 };
2651 static struct intel_watermark_params g4x_wm_info = {
2652         G4X_FIFO_SIZE,
2653         G4X_MAX_WM,
2654         G4X_MAX_WM,
2655         2,
2656         G4X_FIFO_LINE_SIZE,
2657 };
2658 static struct intel_watermark_params i945_wm_info = {
2659         I945_FIFO_SIZE,
2660         I915_MAX_WM,
2661         1,
2662         2,
2663         I915_FIFO_LINE_SIZE
2664 };
2665 static struct intel_watermark_params i915_wm_info = {
2666         I915_FIFO_SIZE,
2667         I915_MAX_WM,
2668         1,
2669         2,
2670         I915_FIFO_LINE_SIZE
2671 };
2672 static struct intel_watermark_params i855_wm_info = {
2673         I855GM_FIFO_SIZE,
2674         I915_MAX_WM,
2675         1,
2676         2,
2677         I830_FIFO_LINE_SIZE
2678 };
2679 static struct intel_watermark_params i830_wm_info = {
2680         I830_FIFO_SIZE,
2681         I915_MAX_WM,
2682         1,
2683         2,
2684         I830_FIFO_LINE_SIZE
2685 };
2686
2687 static struct intel_watermark_params ironlake_display_wm_info = {
2688         ILK_DISPLAY_FIFO,
2689         ILK_DISPLAY_MAXWM,
2690         ILK_DISPLAY_DFTWM,
2691         2,
2692         ILK_FIFO_LINE_SIZE
2693 };
2694
2695 static struct intel_watermark_params ironlake_display_srwm_info = {
2696         ILK_DISPLAY_SR_FIFO,
2697         ILK_DISPLAY_MAX_SRWM,
2698         ILK_DISPLAY_DFT_SRWM,
2699         2,
2700         ILK_FIFO_LINE_SIZE
2701 };
2702
2703 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2704         ILK_CURSOR_SR_FIFO,
2705         ILK_CURSOR_MAX_SRWM,
2706         ILK_CURSOR_DFT_SRWM,
2707         2,
2708         ILK_FIFO_LINE_SIZE
2709 };
2710
2711 /**
2712  * intel_calculate_wm - calculate watermark level
2713  * @clock_in_khz: pixel clock
2714  * @wm: chip FIFO params
2715  * @pixel_size: display pixel size
2716  * @latency_ns: memory latency for the platform
2717  *
2718  * Calculate the watermark level (the level at which the display plane will
2719  * start fetching from memory again).  Each chip has a different display
2720  * FIFO size and allocation, so the caller needs to figure that out and pass
2721  * in the correct intel_watermark_params structure.
2722  *
2723  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2724  * on the pixel size.  When it reaches the watermark level, it'll start
2725  * fetching FIFO line sized based chunks from memory until the FIFO fills
2726  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2727  * will occur, and a display engine hang could result.
2728  */
2729 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2730                                         struct intel_watermark_params *wm,
2731                                         int pixel_size,
2732                                         unsigned long latency_ns)
2733 {
2734         long entries_required, wm_size;
2735
2736         /*
2737          * Note: we need to make sure we don't overflow for various clock &
2738          * latency values.
2739          * clocks go from a few thousand to several hundred thousand.
2740          * latency is usually a few thousand
2741          */
2742         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2743                 1000;
2744         entries_required /= wm->cacheline_size;
2745
2746         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2747
2748         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2749
2750         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2751
2752         /* Don't promote wm_size to unsigned... */
2753         if (wm_size > (long)wm->max_wm)
2754                 wm_size = wm->max_wm;
2755         if (wm_size <= 0)
2756                 wm_size = wm->default_wm;
2757         return wm_size;
2758 }
2759
2760 struct cxsr_latency {
2761         int is_desktop;
2762         int is_ddr3;
2763         unsigned long fsb_freq;
2764         unsigned long mem_freq;
2765         unsigned long display_sr;
2766         unsigned long display_hpll_disable;
2767         unsigned long cursor_sr;
2768         unsigned long cursor_hpll_disable;
2769 };
2770
2771 static struct cxsr_latency cxsr_latency_table[] = {
2772         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2773         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2774         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2775         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2776         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2777
2778         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2779         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2780         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2781         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2782         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2783
2784         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2785         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2786         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2787         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2788         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2789
2790         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2791         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2792         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2793         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2794         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2795
2796         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2797         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2798         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2799         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2800         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2801
2802         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2803         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2804         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2805         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2806         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2807 };
2808
2809 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2810                                                    int fsb, int mem)
2811 {
2812         int i;
2813         struct cxsr_latency *latency;
2814
2815         if (fsb == 0 || mem == 0)
2816                 return NULL;
2817
2818         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2819                 latency = &cxsr_latency_table[i];
2820                 if (is_desktop == latency->is_desktop &&
2821                     is_ddr3 == latency->is_ddr3 &&
2822                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2823                         return latency;
2824         }
2825
2826         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2827
2828         return NULL;
2829 }
2830
2831 static void pineview_disable_cxsr(struct drm_device *dev)
2832 {
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         u32 reg;
2835
2836         /* deactivate cxsr */
2837         reg = I915_READ(DSPFW3);
2838         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2839         I915_WRITE(DSPFW3, reg);
2840         DRM_INFO("Big FIFO is disabled\n");
2841 }
2842
2843 /*
2844  * Latency for FIFO fetches is dependent on several factors:
2845  *   - memory configuration (speed, channels)
2846  *   - chipset
2847  *   - current MCH state
2848  * It can be fairly high in some situations, so here we assume a fairly
2849  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2850  * set this value too high, the FIFO will fetch frequently to stay full)
2851  * and power consumption (set it too low to save power and we might see
2852  * FIFO underruns and display "flicker").
2853  *
2854  * A value of 5us seems to be a good balance; safe for very low end
2855  * platforms but not overly aggressive on lower latency configs.
2856  */
2857 static const int latency_ns = 5000;
2858
2859 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2860 {
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         uint32_t dsparb = I915_READ(DSPARB);
2863         int size;
2864
2865         if (plane == 0)
2866                 size = dsparb & 0x7f;
2867         else
2868                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2869                         (dsparb & 0x7f);
2870
2871         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2872                         plane ? "B" : "A", size);
2873
2874         return size;
2875 }
2876
2877 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2878 {
2879         struct drm_i915_private *dev_priv = dev->dev_private;
2880         uint32_t dsparb = I915_READ(DSPARB);
2881         int size;
2882
2883         if (plane == 0)
2884                 size = dsparb & 0x1ff;
2885         else
2886                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2887                         (dsparb & 0x1ff);
2888         size >>= 1; /* Convert to cachelines */
2889
2890         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2891                         plane ? "B" : "A", size);
2892
2893         return size;
2894 }
2895
2896 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2897 {
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         uint32_t dsparb = I915_READ(DSPARB);
2900         int size;
2901
2902         size = dsparb & 0x7f;
2903         size >>= 2; /* Convert to cachelines */
2904
2905         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2906                         plane ? "B" : "A",
2907                   size);
2908
2909         return size;
2910 }
2911
2912 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2913 {
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         uint32_t dsparb = I915_READ(DSPARB);
2916         int size;
2917
2918         size = dsparb & 0x7f;
2919         size >>= 1; /* Convert to cachelines */
2920
2921         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2922                         plane ? "B" : "A", size);
2923
2924         return size;
2925 }
2926
2927 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2928                           int planeb_clock, int sr_hdisplay, int pixel_size)
2929 {
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         u32 reg;
2932         unsigned long wm;
2933         struct cxsr_latency *latency;
2934         int sr_clock;
2935
2936         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2937                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2938         if (!latency) {
2939                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2940                 pineview_disable_cxsr(dev);
2941                 return;
2942         }
2943
2944         if (!planea_clock || !planeb_clock) {
2945                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2946
2947                 /* Display SR */
2948                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2949                                         pixel_size, latency->display_sr);
2950                 reg = I915_READ(DSPFW1);
2951                 reg &= ~DSPFW_SR_MASK;
2952                 reg |= wm << DSPFW_SR_SHIFT;
2953                 I915_WRITE(DSPFW1, reg);
2954                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2955
2956                 /* cursor SR */
2957                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2958                                         pixel_size, latency->cursor_sr);
2959                 reg = I915_READ(DSPFW3);
2960                 reg &= ~DSPFW_CURSOR_SR_MASK;
2961                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2962                 I915_WRITE(DSPFW3, reg);
2963
2964                 /* Display HPLL off SR */
2965                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2966                                         pixel_size, latency->display_hpll_disable);
2967                 reg = I915_READ(DSPFW3);
2968                 reg &= ~DSPFW_HPLL_SR_MASK;
2969                 reg |= wm & DSPFW_HPLL_SR_MASK;
2970                 I915_WRITE(DSPFW3, reg);
2971
2972                 /* cursor HPLL off SR */
2973                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2974                                         pixel_size, latency->cursor_hpll_disable);
2975                 reg = I915_READ(DSPFW3);
2976                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2977                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2978                 I915_WRITE(DSPFW3, reg);
2979                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2980
2981                 /* activate cxsr */
2982                 reg = I915_READ(DSPFW3);
2983                 reg |= PINEVIEW_SELF_REFRESH_EN;
2984                 I915_WRITE(DSPFW3, reg);
2985                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2986         } else {
2987                 pineview_disable_cxsr(dev);
2988                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2989         }
2990 }
2991
2992 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2993                           int planeb_clock, int sr_hdisplay, int pixel_size)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         int total_size, cacheline_size;
2997         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2998         struct intel_watermark_params planea_params, planeb_params;
2999         unsigned long line_time_us;
3000         int sr_clock, sr_entries = 0, entries_required;
3001
3002         /* Create copies of the base settings for each pipe */
3003         planea_params = planeb_params = g4x_wm_info;
3004
3005         /* Grab a couple of global values before we overwrite them */
3006         total_size = planea_params.fifo_size;
3007         cacheline_size = planea_params.cacheline_size;
3008
3009         /*
3010          * Note: we need to make sure we don't overflow for various clock &
3011          * latency values.
3012          * clocks go from a few thousand to several hundred thousand.
3013          * latency is usually a few thousand
3014          */
3015         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3016                 1000;
3017         entries_required /= G4X_FIFO_LINE_SIZE;
3018         planea_wm = entries_required + planea_params.guard_size;
3019
3020         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3021                 1000;
3022         entries_required /= G4X_FIFO_LINE_SIZE;
3023         planeb_wm = entries_required + planeb_params.guard_size;
3024
3025         cursora_wm = cursorb_wm = 16;
3026         cursor_sr = 32;
3027
3028         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3029
3030         /* Calc sr entries for one plane configs */
3031         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3032                 /* self-refresh has much higher latency */
3033                 static const int sr_latency_ns = 12000;
3034
3035                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3036                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3037
3038                 /* Use ns/us then divide to preserve precision */
3039                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3040                               pixel_size * sr_hdisplay) / 1000;
3041                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3042                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3043                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3044         } else {
3045                 /* Turn off self refresh if both pipes are enabled */
3046                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3047                                         & ~FW_BLC_SELF_EN);
3048         }
3049
3050         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3051                   planea_wm, planeb_wm, sr_entries);
3052
3053         planea_wm &= 0x3f;
3054         planeb_wm &= 0x3f;
3055
3056         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3057                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3058                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3059         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3060                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3061         /* HPLL off in SR has some issues on G4x... disable it */
3062         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3063                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3064 }
3065
3066 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3067                            int planeb_clock, int sr_hdisplay, int pixel_size)
3068 {
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         unsigned long line_time_us;
3071         int sr_clock, sr_entries, srwm = 1;
3072
3073         /* Calc sr entries for one plane configs */
3074         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3075                 /* self-refresh has much higher latency */
3076                 static const int sr_latency_ns = 12000;
3077
3078                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3079                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3080
3081                 /* Use ns/us then divide to preserve precision */
3082                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3083                               pixel_size * sr_hdisplay) / 1000;
3084                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
3085                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3086                 srwm = I945_FIFO_SIZE - sr_entries;
3087                 if (srwm < 0)
3088                         srwm = 1;
3089                 srwm &= 0x3f;
3090                 if (IS_I965GM(dev))
3091                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3092         } else {
3093                 /* Turn off self refresh if both pipes are enabled */
3094                 if (IS_I965GM(dev))
3095                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3096                                    & ~FW_BLC_SELF_EN);
3097         }
3098
3099         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3100                       srwm);
3101
3102         /* 965 has limitations... */
3103         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3104                    (8 << 0));
3105         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3106 }
3107
3108 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3109                            int planeb_clock, int sr_hdisplay, int pixel_size)
3110 {
3111         struct drm_i915_private *dev_priv = dev->dev_private;
3112         uint32_t fwater_lo;
3113         uint32_t fwater_hi;
3114         int total_size, cacheline_size, cwm, srwm = 1;
3115         int planea_wm, planeb_wm;
3116         struct intel_watermark_params planea_params, planeb_params;
3117         unsigned long line_time_us;
3118         int sr_clock, sr_entries = 0;
3119
3120         /* Create copies of the base settings for each pipe */
3121         if (IS_I965GM(dev) || IS_I945GM(dev))
3122                 planea_params = planeb_params = i945_wm_info;
3123         else if (IS_I9XX(dev))
3124                 planea_params = planeb_params = i915_wm_info;
3125         else
3126                 planea_params = planeb_params = i855_wm_info;
3127
3128         /* Grab a couple of global values before we overwrite them */
3129         total_size = planea_params.fifo_size;
3130         cacheline_size = planea_params.cacheline_size;
3131
3132         /* Update per-plane FIFO sizes */
3133         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3134         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3135
3136         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3137                                        pixel_size, latency_ns);
3138         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3139                                        pixel_size, latency_ns);
3140         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3141
3142         /*
3143          * Overlay gets an aggressive default since video jitter is bad.
3144          */
3145         cwm = 2;
3146
3147         /* Calc sr entries for one plane configs */
3148         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3149             (!planea_clock || !planeb_clock)) {
3150                 /* self-refresh has much higher latency */
3151                 static const int sr_latency_ns = 6000;
3152
3153                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3154                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3155
3156                 /* Use ns/us then divide to preserve precision */
3157                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3158                               pixel_size * sr_hdisplay) / 1000;
3159                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3160                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3161                 srwm = total_size - sr_entries;
3162                 if (srwm < 0)
3163                         srwm = 1;
3164
3165                 if (IS_I945G(dev) || IS_I945GM(dev))
3166                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3167                 else if (IS_I915GM(dev)) {
3168                         /* 915M has a smaller SRWM field */
3169                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3170                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3171                 }
3172         } else {
3173                 /* Turn off self refresh if both pipes are enabled */
3174                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3175                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3176                                    & ~FW_BLC_SELF_EN);
3177                 } else if (IS_I915GM(dev)) {
3178                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3179                 }
3180         }
3181
3182         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3183                   planea_wm, planeb_wm, cwm, srwm);
3184
3185         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3186         fwater_hi = (cwm & 0x1f);
3187
3188         /* Set request length to 8 cachelines per fetch */
3189         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3190         fwater_hi = fwater_hi | (1 << 8);
3191
3192         I915_WRITE(FW_BLC, fwater_lo);
3193         I915_WRITE(FW_BLC2, fwater_hi);
3194 }
3195
3196 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3197                            int unused2, int pixel_size)
3198 {
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3201         int planea_wm;
3202
3203         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3204
3205         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3206                                        pixel_size, latency_ns);
3207         fwater_lo |= (3<<8) | planea_wm;
3208
3209         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3210
3211         I915_WRITE(FW_BLC, fwater_lo);
3212 }
3213
3214 #define ILK_LP0_PLANE_LATENCY           700
3215
3216 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3217                        int planeb_clock, int sr_hdisplay, int pixel_size)
3218 {
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3221         int sr_wm, cursor_wm;
3222         unsigned long line_time_us;
3223         int sr_clock, entries_required;
3224         u32 reg_value;
3225
3226         /* Calculate and update the watermark for plane A */
3227         if (planea_clock) {
3228                 entries_required = ((planea_clock / 1000) * pixel_size *
3229                                      ILK_LP0_PLANE_LATENCY) / 1000;
3230                 entries_required = DIV_ROUND_UP(entries_required,
3231                                    ironlake_display_wm_info.cacheline_size);
3232                 planea_wm = entries_required +
3233                             ironlake_display_wm_info.guard_size;
3234
3235                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3236                         planea_wm = ironlake_display_wm_info.max_wm;
3237
3238                 cursora_wm = 16;
3239                 reg_value = I915_READ(WM0_PIPEA_ILK);
3240                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3241                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3242                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3243                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3244                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3245                                 "cursor: %d\n", planea_wm, cursora_wm);
3246         }
3247         /* Calculate and update the watermark for plane B */
3248         if (planeb_clock) {
3249                 entries_required = ((planeb_clock / 1000) * pixel_size *
3250                                      ILK_LP0_PLANE_LATENCY) / 1000;
3251                 entries_required = DIV_ROUND_UP(entries_required,
3252                                    ironlake_display_wm_info.cacheline_size);
3253                 planeb_wm = entries_required +
3254                             ironlake_display_wm_info.guard_size;
3255
3256                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3257                         planeb_wm = ironlake_display_wm_info.max_wm;
3258
3259                 cursorb_wm = 16;
3260                 reg_value = I915_READ(WM0_PIPEB_ILK);
3261                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3262                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3263                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3264                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3265                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3266                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3267         }
3268
3269         /*
3270          * Calculate and update the self-refresh watermark only when one
3271          * display plane is used.
3272          */
3273         if (!planea_clock || !planeb_clock) {
3274                 int line_count;
3275                 /* Read the self-refresh latency. The unit is 0.5us */
3276                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3277
3278                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3279                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3280
3281                 /* Use ns/us then divide to preserve precision */
3282                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3283                                / 1000;
3284
3285                 /* calculate the self-refresh watermark for display plane */
3286                 entries_required = line_count * sr_hdisplay * pixel_size;
3287                 entries_required = DIV_ROUND_UP(entries_required,
3288                                    ironlake_display_srwm_info.cacheline_size);
3289                 sr_wm = entries_required +
3290                         ironlake_display_srwm_info.guard_size;
3291
3292                 /* calculate the self-refresh watermark for display cursor */
3293                 entries_required = line_count * pixel_size * 64;
3294                 entries_required = DIV_ROUND_UP(entries_required,
3295                                    ironlake_cursor_srwm_info.cacheline_size);
3296                 cursor_wm = entries_required +
3297                             ironlake_cursor_srwm_info.guard_size;
3298
3299                 /* configure watermark and enable self-refresh */
3300                 reg_value = I915_READ(WM1_LP_ILK);
3301                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3302                                WM1_LP_CURSOR_MASK);
3303                 reg_value |= WM1_LP_SR_EN |
3304                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3305                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3306
3307                 I915_WRITE(WM1_LP_ILK, reg_value);
3308                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3309                                 "cursor %d\n", sr_wm, cursor_wm);
3310
3311         } else {
3312                 /* Turn off self refresh if both pipes are enabled */
3313                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3314         }
3315 }
3316 /**
3317  * intel_update_watermarks - update FIFO watermark values based on current modes
3318  *
3319  * Calculate watermark values for the various WM regs based on current mode
3320  * and plane configuration.
3321  *
3322  * There are several cases to deal with here:
3323  *   - normal (i.e. non-self-refresh)
3324  *   - self-refresh (SR) mode
3325  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3326  *   - lines are small relative to FIFO size (buffer can hold more than 2
3327  *     lines), so need to account for TLB latency
3328  *
3329  *   The normal calculation is:
3330  *     watermark = dotclock * bytes per pixel * latency
3331  *   where latency is platform & configuration dependent (we assume pessimal
3332  *   values here).
3333  *
3334  *   The SR calculation is:
3335  *     watermark = (trunc(latency/line time)+1) * surface width *
3336  *       bytes per pixel
3337  *   where
3338  *     line time = htotal / dotclock
3339  *   and latency is assumed to be high, as above.
3340  *
3341  * The final value programmed to the register should always be rounded up,
3342  * and include an extra 2 entries to account for clock crossings.
3343  *
3344  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3345  * to set the non-SR watermarks to 8.
3346   */
3347 static void intel_update_watermarks(struct drm_device *dev)
3348 {
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct drm_crtc *crtc;
3351         struct intel_crtc *intel_crtc;
3352         int sr_hdisplay = 0;
3353         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3354         int enabled = 0, pixel_size = 0;
3355
3356         if (!dev_priv->display.update_wm)
3357                 return;
3358
3359         /* Get the clock config from both planes */
3360         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3361                 intel_crtc = to_intel_crtc(crtc);
3362                 if (crtc->enabled) {
3363                         enabled++;
3364                         if (intel_crtc->plane == 0) {
3365                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3366                                           intel_crtc->pipe, crtc->mode.clock);
3367                                 planea_clock = crtc->mode.clock;
3368                         } else {
3369                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3370                                           intel_crtc->pipe, crtc->mode.clock);
3371                                 planeb_clock = crtc->mode.clock;
3372                         }
3373                         sr_hdisplay = crtc->mode.hdisplay;
3374                         sr_clock = crtc->mode.clock;
3375                         if (crtc->fb)
3376                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3377                         else
3378                                 pixel_size = 4; /* by default */
3379                 }
3380         }
3381
3382         if (enabled <= 0)
3383                 return;
3384
3385         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3386                                     sr_hdisplay, pixel_size);
3387 }
3388
3389 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3390                                struct drm_display_mode *mode,
3391                                struct drm_display_mode *adjusted_mode,
3392                                int x, int y,
3393                                struct drm_framebuffer *old_fb)
3394 {
3395         struct drm_device *dev = crtc->dev;
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398         int pipe = intel_crtc->pipe;
3399         int plane = intel_crtc->plane;
3400         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3401         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3402         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3403         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3404         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3405         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3406         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3407         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3408         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3409         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3410         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3411         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3412         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3413         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3414         int refclk, num_connectors = 0;
3415         intel_clock_t clock, reduced_clock;
3416         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3417         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3418         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3419         bool is_edp = false;
3420         struct drm_mode_config *mode_config = &dev->mode_config;
3421         struct drm_encoder *encoder;
3422         struct intel_encoder *intel_encoder = NULL;
3423         const intel_limit_t *limit;
3424         int ret;
3425         struct fdi_m_n m_n = {0};
3426         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3427         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3428         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3429         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3430         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3431         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3432         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3433         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3434         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3435         int lvds_reg = LVDS;
3436         u32 temp;
3437         int sdvo_pixel_multiply;
3438         int target_clock;
3439
3440         drm_vblank_pre_modeset(dev, pipe);
3441
3442         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3443
3444                 if (!encoder || encoder->crtc != crtc)
3445                         continue;
3446
3447                 intel_encoder = enc_to_intel_encoder(encoder);
3448
3449                 switch (intel_encoder->type) {
3450                 case INTEL_OUTPUT_LVDS:
3451                         is_lvds = true;
3452                         break;
3453                 case INTEL_OUTPUT_SDVO:
3454                 case INTEL_OUTPUT_HDMI:
3455                         is_sdvo = true;
3456                         if (intel_encoder->needs_tv_clock)
3457                                 is_tv = true;
3458                         break;
3459                 case INTEL_OUTPUT_DVO:
3460                         is_dvo = true;
3461                         break;
3462                 case INTEL_OUTPUT_TVOUT:
3463                         is_tv = true;
3464                         break;
3465                 case INTEL_OUTPUT_ANALOG:
3466                         is_crt = true;
3467                         break;
3468                 case INTEL_OUTPUT_DISPLAYPORT:
3469                         is_dp = true;
3470                         break;
3471                 case INTEL_OUTPUT_EDP:
3472                         is_edp = true;
3473                         break;
3474                 }
3475
3476                 num_connectors++;
3477         }
3478
3479         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3480                 refclk = dev_priv->lvds_ssc_freq * 1000;
3481                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3482                                         refclk / 1000);
3483         } else if (IS_I9XX(dev)) {
3484                 refclk = 96000;
3485                 if (HAS_PCH_SPLIT(dev))
3486                         refclk = 120000; /* 120Mhz refclk */
3487         } else {
3488                 refclk = 48000;
3489         }
3490
3491
3492         /*
3493          * Returns a set of divisors for the desired target clock with the given
3494          * refclk, or FALSE.  The returned values represent the clock equation:
3495          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3496          */
3497         limit = intel_limit(crtc);
3498         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3499         if (!ok) {
3500                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3501                 drm_vblank_post_modeset(dev, pipe);
3502                 return -EINVAL;
3503         }
3504
3505         if (is_lvds && dev_priv->lvds_downclock_avail) {
3506                 has_reduced_clock = limit->find_pll(limit, crtc,
3507                                                             dev_priv->lvds_downclock,
3508                                                             refclk,
3509                                                             &reduced_clock);
3510                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3511                         /*
3512                          * If the different P is found, it means that we can't
3513                          * switch the display clock by using the FP0/FP1.
3514                          * In such case we will disable the LVDS downclock
3515                          * feature.
3516                          */
3517                         DRM_DEBUG_KMS("Different P is found for "
3518                                                 "LVDS clock/downclock\n");
3519                         has_reduced_clock = 0;
3520                 }
3521         }
3522         /* SDVO TV has fixed PLL values depend on its clock range,
3523            this mirrors vbios setting. */
3524         if (is_sdvo && is_tv) {
3525                 if (adjusted_mode->clock >= 100000
3526                                 && adjusted_mode->clock < 140500) {
3527                         clock.p1 = 2;
3528                         clock.p2 = 10;
3529                         clock.n = 3;
3530                         clock.m1 = 16;
3531                         clock.m2 = 8;
3532                 } else if (adjusted_mode->clock >= 140500
3533                                 && adjusted_mode->clock <= 200000) {
3534                         clock.p1 = 1;
3535                         clock.p2 = 10;
3536                         clock.n = 6;
3537                         clock.m1 = 12;
3538                         clock.m2 = 8;
3539                 }
3540         }
3541
3542         /* FDI link */
3543         if (HAS_PCH_SPLIT(dev)) {
3544                 int lane = 0, link_bw, bpp;
3545                 /* eDP doesn't require FDI link, so just set DP M/N
3546                    according to current link config */
3547                 if (is_edp) {
3548                         target_clock = mode->clock;
3549                         intel_edp_link_config(intel_encoder,
3550                                         &lane, &link_bw);
3551                 } else {
3552                         /* DP over FDI requires target mode clock
3553                            instead of link clock */
3554                         if (is_dp)
3555                                 target_clock = mode->clock;
3556                         else
3557                                 target_clock = adjusted_mode->clock;
3558                         link_bw = 270000;
3559                 }
3560
3561                 /* determine panel color depth */
3562                 temp = I915_READ(pipeconf_reg);
3563                 temp &= ~PIPE_BPC_MASK;
3564                 if (is_lvds) {
3565                         int lvds_reg = I915_READ(PCH_LVDS);
3566                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3567                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3568                                 temp |= PIPE_8BPC;
3569                         else
3570                                 temp |= PIPE_6BPC;
3571                 } else if (is_edp) {
3572                         switch (dev_priv->edp_bpp/3) {
3573                         case 8:
3574                                 temp |= PIPE_8BPC;
3575                                 break;
3576                         case 10:
3577                                 temp |= PIPE_10BPC;
3578                                 break;
3579                         case 6:
3580                                 temp |= PIPE_6BPC;
3581                                 break;
3582                         case 12:
3583                                 temp |= PIPE_12BPC;
3584                                 break;
3585                         }
3586                 } else
3587                         temp |= PIPE_8BPC;
3588                 I915_WRITE(pipeconf_reg, temp);
3589                 I915_READ(pipeconf_reg);
3590
3591                 switch (temp & PIPE_BPC_MASK) {
3592                 case PIPE_8BPC:
3593                         bpp = 24;
3594                         break;
3595                 case PIPE_10BPC:
3596                         bpp = 30;
3597                         break;
3598                 case PIPE_6BPC:
3599                         bpp = 18;
3600                         break;
3601                 case PIPE_12BPC:
3602                         bpp = 36;
3603                         break;
3604                 default:
3605                         DRM_ERROR("unknown pipe bpc value\n");
3606                         bpp = 24;
3607                 }
3608
3609                 if (!lane) {
3610                         /*
3611                          * Account for spread spectrum to avoid
3612                          * oversubscribing the link. Max center spread
3613                          * is 2.5%; use 5% for safety's sake.
3614                          */
3615                         u32 bps = target_clock * bpp * 21 / 20;
3616                         lane = bps / (link_bw * 8) + 1;
3617                 }
3618
3619                 intel_crtc->fdi_lanes = lane;
3620
3621                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3622         }
3623
3624         /* Ironlake: try to setup display ref clock before DPLL
3625          * enabling. This is only under driver's control after
3626          * PCH B stepping, previous chipset stepping should be
3627          * ignoring this setting.
3628          */
3629         if (HAS_PCH_SPLIT(dev)) {
3630                 temp = I915_READ(PCH_DREF_CONTROL);
3631                 /* Always enable nonspread source */
3632                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3633                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3634                 I915_WRITE(PCH_DREF_CONTROL, temp);
3635                 POSTING_READ(PCH_DREF_CONTROL);
3636
3637                 temp &= ~DREF_SSC_SOURCE_MASK;
3638                 temp |= DREF_SSC_SOURCE_ENABLE;
3639                 I915_WRITE(PCH_DREF_CONTROL, temp);
3640                 POSTING_READ(PCH_DREF_CONTROL);
3641
3642                 udelay(200);
3643
3644                 if (is_edp) {
3645                         if (dev_priv->lvds_use_ssc) {
3646                                 temp |= DREF_SSC1_ENABLE;
3647                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3648                                 POSTING_READ(PCH_DREF_CONTROL);
3649
3650                                 udelay(200);
3651
3652                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3653                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3654                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3655                                 POSTING_READ(PCH_DREF_CONTROL);
3656                         } else {
3657                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3658                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3659                                 POSTING_READ(PCH_DREF_CONTROL);
3660                         }
3661                 }
3662         }
3663
3664         if (IS_PINEVIEW(dev)) {
3665                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3666                 if (has_reduced_clock)
3667                         fp2 = (1 << reduced_clock.n) << 16 |
3668                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3669         } else {
3670                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3671                 if (has_reduced_clock)
3672                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3673                                 reduced_clock.m2;
3674         }
3675
3676         if (!HAS_PCH_SPLIT(dev))
3677                 dpll = DPLL_VGA_MODE_DIS;
3678
3679         if (IS_I9XX(dev)) {
3680                 if (is_lvds)
3681                         dpll |= DPLLB_MODE_LVDS;
3682                 else
3683                         dpll |= DPLLB_MODE_DAC_SERIAL;
3684                 if (is_sdvo) {
3685                         dpll |= DPLL_DVO_HIGH_SPEED;
3686                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3687                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3688                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3689                         else if (HAS_PCH_SPLIT(dev))
3690                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3691                 }
3692                 if (is_dp)
3693                         dpll |= DPLL_DVO_HIGH_SPEED;
3694
3695                 /* compute bitmask from p1 value */
3696                 if (IS_PINEVIEW(dev))
3697                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3698                 else {
3699                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3700                         /* also FPA1 */
3701                         if (HAS_PCH_SPLIT(dev))
3702                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3703                         if (IS_G4X(dev) && has_reduced_clock)
3704                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3705                 }
3706                 switch (clock.p2) {
3707                 case 5:
3708                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3709                         break;
3710                 case 7:
3711                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3712                         break;
3713                 case 10:
3714                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3715                         break;
3716                 case 14:
3717                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3718                         break;
3719                 }
3720                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3721                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3722         } else {
3723                 if (is_lvds) {
3724                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3725                 } else {
3726                         if (clock.p1 == 2)
3727                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3728                         else
3729                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3730                         if (clock.p2 == 4)
3731                                 dpll |= PLL_P2_DIVIDE_BY_4;
3732                 }
3733         }
3734
3735         if (is_sdvo && is_tv)
3736                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3737         else if (is_tv)
3738                 /* XXX: just matching BIOS for now */
3739                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3740                 dpll |= 3;
3741         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3742                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3743         else
3744                 dpll |= PLL_REF_INPUT_DREFCLK;
3745
3746         /* setup pipeconf */
3747         pipeconf = I915_READ(pipeconf_reg);
3748
3749         /* Set up the display plane register */
3750         dspcntr = DISPPLANE_GAMMA_ENABLE;
3751
3752         /* Ironlake's plane is forced to pipe, bit 24 is to
3753            enable color space conversion */
3754         if (!HAS_PCH_SPLIT(dev)) {
3755                 if (pipe == 0)
3756                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3757                 else
3758                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3759         }
3760
3761         if (pipe == 0 && !IS_I965G(dev)) {
3762                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3763                  * core speed.
3764                  *
3765                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3766                  * pipe == 0 check?
3767                  */
3768                 if (mode->clock >
3769                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3770                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3771                 else
3772                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3773         }
3774
3775         dspcntr |= DISPLAY_PLANE_ENABLE;
3776         pipeconf |= PIPEACONF_ENABLE;
3777         dpll |= DPLL_VCO_ENABLE;
3778
3779
3780         /* Disable the panel fitter if it was on our pipe */
3781         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3782                 I915_WRITE(PFIT_CONTROL, 0);
3783
3784         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3785         drm_mode_debug_printmodeline(mode);
3786
3787         /* assign to Ironlake registers */
3788         if (HAS_PCH_SPLIT(dev)) {
3789                 fp_reg = pch_fp_reg;
3790                 dpll_reg = pch_dpll_reg;
3791         }
3792
3793         if (is_edp) {
3794                 ironlake_disable_pll_edp(crtc);
3795         } else if ((dpll & DPLL_VCO_ENABLE)) {
3796                 I915_WRITE(fp_reg, fp);
3797                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3798                 I915_READ(dpll_reg);
3799                 udelay(150);
3800         }
3801
3802         /* enable transcoder DPLL */
3803         if (HAS_PCH_CPT(dev)) {
3804                 temp = I915_READ(PCH_DPLL_SEL);
3805                 if (trans_dpll_sel == 0)
3806                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3807                 else
3808                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3809                 I915_WRITE(PCH_DPLL_SEL, temp);
3810                 I915_READ(PCH_DPLL_SEL);
3811                 udelay(150);
3812         }
3813
3814         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3815          * This is an exception to the general rule that mode_set doesn't turn
3816          * things on.
3817          */
3818         if (is_lvds) {
3819                 u32 lvds;
3820
3821                 if (HAS_PCH_SPLIT(dev))
3822                         lvds_reg = PCH_LVDS;
3823
3824                 lvds = I915_READ(lvds_reg);
3825                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3826                 if (pipe == 1) {
3827                         if (HAS_PCH_CPT(dev))
3828                                 lvds |= PORT_TRANS_B_SEL_CPT;
3829                         else
3830                                 lvds |= LVDS_PIPEB_SELECT;
3831                 } else {
3832                         if (HAS_PCH_CPT(dev))
3833                                 lvds &= ~PORT_TRANS_SEL_MASK;
3834                         else
3835                                 lvds &= ~LVDS_PIPEB_SELECT;
3836                 }
3837                 /* set the corresponsding LVDS_BORDER bit */
3838                 lvds |= dev_priv->lvds_border_bits;
3839                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3840                  * set the DPLLs for dual-channel mode or not.
3841                  */
3842                 if (clock.p2 == 7)
3843                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3844                 else
3845                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3846
3847                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3848                  * appropriately here, but we need to look more thoroughly into how
3849                  * panels behave in the two modes.
3850                  */
3851                 /* set the dithering flag */
3852                 if (IS_I965G(dev)) {
3853                         if (dev_priv->lvds_dither) {
3854                                 if (HAS_PCH_SPLIT(dev)) {
3855                                         pipeconf |= PIPE_ENABLE_DITHER;
3856                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3857                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3858                                 } else
3859                                         lvds |= LVDS_ENABLE_DITHER;
3860                         } else {
3861                                 if (HAS_PCH_SPLIT(dev)) {
3862                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3863                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3864                                 } else
3865                                         lvds &= ~LVDS_ENABLE_DITHER;
3866                         }
3867                 }
3868                 I915_WRITE(lvds_reg, lvds);
3869                 I915_READ(lvds_reg);
3870         }
3871         if (is_dp)
3872                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3873         else if (HAS_PCH_SPLIT(dev)) {
3874                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3875                 if (pipe == 0) {
3876                         I915_WRITE(TRANSA_DATA_M1, 0);
3877                         I915_WRITE(TRANSA_DATA_N1, 0);
3878                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3879                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3880                 } else {
3881                         I915_WRITE(TRANSB_DATA_M1, 0);
3882                         I915_WRITE(TRANSB_DATA_N1, 0);
3883                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3884                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3885                 }
3886         }
3887
3888         if (!is_edp) {
3889                 I915_WRITE(fp_reg, fp);
3890                 I915_WRITE(dpll_reg, dpll);
3891                 I915_READ(dpll_reg);
3892                 /* Wait for the clocks to stabilize. */
3893                 udelay(150);
3894
3895                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3896                         if (is_sdvo) {
3897                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3898                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3899                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3900                         } else
3901                                 I915_WRITE(dpll_md_reg, 0);
3902                 } else {
3903                         /* write it again -- the BIOS does, after all */
3904                         I915_WRITE(dpll_reg, dpll);
3905                 }
3906                 I915_READ(dpll_reg);
3907                 /* Wait for the clocks to stabilize. */
3908                 udelay(150);
3909         }
3910
3911         if (is_lvds && has_reduced_clock && i915_powersave) {
3912                 I915_WRITE(fp_reg + 4, fp2);
3913                 intel_crtc->lowfreq_avail = true;
3914                 if (HAS_PIPE_CXSR(dev)) {
3915                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3916                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3917                 }
3918         } else {
3919                 I915_WRITE(fp_reg + 4, fp);
3920                 intel_crtc->lowfreq_avail = false;
3921                 if (HAS_PIPE_CXSR(dev)) {
3922                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3923                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3924                 }
3925         }
3926
3927         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3928                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3929                 /* the chip adds 2 halflines automatically */
3930                 adjusted_mode->crtc_vdisplay -= 1;
3931                 adjusted_mode->crtc_vtotal -= 1;
3932                 adjusted_mode->crtc_vblank_start -= 1;
3933                 adjusted_mode->crtc_vblank_end -= 1;
3934                 adjusted_mode->crtc_vsync_end -= 1;
3935                 adjusted_mode->crtc_vsync_start -= 1;
3936         } else
3937                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3938
3939         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3940                    ((adjusted_mode->crtc_htotal - 1) << 16));
3941         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3942                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3943         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3944                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3945         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3946                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3947         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3948                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3949         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3950                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3951         /* pipesrc and dspsize control the size that is scaled from, which should
3952          * always be the user's requested size.
3953          */
3954         if (!HAS_PCH_SPLIT(dev)) {
3955                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3956                                 (mode->hdisplay - 1));
3957                 I915_WRITE(dsppos_reg, 0);
3958         }
3959         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3960
3961         if (HAS_PCH_SPLIT(dev)) {
3962                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3963                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3964                 I915_WRITE(link_m1_reg, m_n.link_m);
3965                 I915_WRITE(link_n1_reg, m_n.link_n);
3966
3967                 if (is_edp) {
3968                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3969                 } else {
3970                         /* enable FDI RX PLL too */
3971                         temp = I915_READ(fdi_rx_reg);
3972                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3973                         I915_READ(fdi_rx_reg);
3974                         udelay(200);
3975
3976                         /* enable FDI TX PLL too */
3977                         temp = I915_READ(fdi_tx_reg);
3978                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3979                         I915_READ(fdi_tx_reg);
3980
3981                         /* enable FDI RX PCDCLK */
3982                         temp = I915_READ(fdi_rx_reg);
3983                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3984                         I915_READ(fdi_rx_reg);
3985                         udelay(200);
3986                 }
3987         }
3988
3989         I915_WRITE(pipeconf_reg, pipeconf);
3990         I915_READ(pipeconf_reg);
3991
3992         intel_wait_for_vblank(dev);
3993
3994         if (IS_IRONLAKE(dev)) {
3995                 /* enable address swizzle for tiling buffer */
3996                 temp = I915_READ(DISP_ARB_CTL);
3997                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3998         }
3999
4000         I915_WRITE(dspcntr_reg, dspcntr);
4001
4002         /* Flush the plane changes */
4003         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4004
4005         if ((IS_I965G(dev) || plane == 0))
4006                 intel_update_fbc(crtc, &crtc->mode);
4007
4008         intel_update_watermarks(dev);
4009
4010         drm_vblank_post_modeset(dev, pipe);
4011
4012         return ret;
4013 }
4014
4015 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4016 void intel_crtc_load_lut(struct drm_crtc *crtc)
4017 {
4018         struct drm_device *dev = crtc->dev;
4019         struct drm_i915_private *dev_priv = dev->dev_private;
4020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4021         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4022         int i;
4023
4024         /* The clocks have to be on to load the palette. */
4025         if (!crtc->enabled)
4026                 return;
4027
4028         /* use legacy palette for Ironlake */
4029         if (HAS_PCH_SPLIT(dev))
4030                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4031                                                    LGC_PALETTE_B;
4032
4033         for (i = 0; i < 256; i++) {
4034                 I915_WRITE(palreg + 4 * i,
4035                            (intel_crtc->lut_r[i] << 16) |
4036                            (intel_crtc->lut_g[i] << 8) |
4037                            intel_crtc->lut_b[i]);
4038         }
4039 }
4040
4041 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4042                                  struct drm_file *file_priv,
4043                                  uint32_t handle,
4044                                  uint32_t width, uint32_t height)
4045 {
4046         struct drm_device *dev = crtc->dev;
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4049         struct drm_gem_object *bo;
4050         struct drm_i915_gem_object *obj_priv;
4051         int pipe = intel_crtc->pipe;
4052         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
4053         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
4054         uint32_t temp = I915_READ(control);
4055         size_t addr;
4056         int ret;
4057
4058         DRM_DEBUG_KMS("\n");
4059
4060         /* if we want to turn off the cursor ignore width and height */
4061         if (!handle) {
4062                 DRM_DEBUG_KMS("cursor off\n");
4063                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4064                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4065                         temp |= CURSOR_MODE_DISABLE;
4066                 } else {
4067                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4068                 }
4069                 addr = 0;
4070                 bo = NULL;
4071                 mutex_lock(&dev->struct_mutex);
4072                 goto finish;
4073         }
4074
4075         /* Currently we only support 64x64 cursors */
4076         if (width != 64 || height != 64) {
4077                 DRM_ERROR("we currently only support 64x64 cursors\n");
4078                 return -EINVAL;
4079         }
4080
4081         bo = drm_gem_object_lookup(dev, file_priv, handle);
4082         if (!bo)
4083                 return -ENOENT;
4084
4085         obj_priv = to_intel_bo(bo);
4086
4087         if (bo->size < width * height * 4) {
4088                 DRM_ERROR("buffer is to small\n");
4089                 ret = -ENOMEM;
4090                 goto fail;
4091         }
4092
4093         /* we only need to pin inside GTT if cursor is non-phy */
4094         mutex_lock(&dev->struct_mutex);
4095         if (!dev_priv->info->cursor_needs_physical) {
4096                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4097                 if (ret) {
4098                         DRM_ERROR("failed to pin cursor bo\n");
4099                         goto fail_locked;
4100                 }
4101
4102                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4103                 if (ret) {
4104                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4105                         goto fail_unpin;
4106                 }
4107
4108                 addr = obj_priv->gtt_offset;
4109         } else {
4110                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4111                 if (ret) {
4112                         DRM_ERROR("failed to attach phys object\n");
4113                         goto fail_locked;
4114                 }
4115                 addr = obj_priv->phys_obj->handle->busaddr;
4116         }
4117
4118         if (!IS_I9XX(dev))
4119                 I915_WRITE(CURSIZE, (height << 12) | width);
4120
4121         /* Hooray for CUR*CNTR differences */
4122         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4123                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4124                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4125                 temp |= (pipe << 28); /* Connect to correct pipe */
4126         } else {
4127                 temp &= ~(CURSOR_FORMAT_MASK);
4128                 temp |= CURSOR_ENABLE;
4129                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4130         }
4131
4132  finish:
4133         I915_WRITE(control, temp);
4134         I915_WRITE(base, addr);
4135
4136         if (intel_crtc->cursor_bo) {
4137                 if (dev_priv->info->cursor_needs_physical) {
4138                         if (intel_crtc->cursor_bo != bo)
4139                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4140                 } else
4141                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4142                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4143         }
4144
4145         mutex_unlock(&dev->struct_mutex);
4146
4147         intel_crtc->cursor_addr = addr;
4148         intel_crtc->cursor_bo = bo;
4149
4150         return 0;
4151 fail_unpin:
4152         i915_gem_object_unpin(bo);
4153 fail_locked:
4154         mutex_unlock(&dev->struct_mutex);
4155 fail:
4156         drm_gem_object_unreference_unlocked(bo);
4157         return ret;
4158 }
4159
4160 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4161 {
4162         struct drm_device *dev = crtc->dev;
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4165         struct intel_framebuffer *intel_fb;
4166         int pipe = intel_crtc->pipe;
4167         uint32_t temp = 0;
4168         uint32_t adder;
4169
4170         if (crtc->fb) {
4171                 intel_fb = to_intel_framebuffer(crtc->fb);
4172                 intel_mark_busy(dev, intel_fb->obj);
4173         }
4174
4175         if (x < 0) {
4176                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4177                 x = -x;
4178         }
4179         if (y < 0) {
4180                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4181                 y = -y;
4182         }
4183
4184         temp |= x << CURSOR_X_SHIFT;
4185         temp |= y << CURSOR_Y_SHIFT;
4186
4187         adder = intel_crtc->cursor_addr;
4188         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4189         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4190
4191         return 0;
4192 }
4193
4194 /** Sets the color ramps on behalf of RandR */
4195 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4196                                  u16 blue, int regno)
4197 {
4198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199
4200         intel_crtc->lut_r[regno] = red >> 8;
4201         intel_crtc->lut_g[regno] = green >> 8;
4202         intel_crtc->lut_b[regno] = blue >> 8;
4203 }
4204
4205 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4206                              u16 *blue, int regno)
4207 {
4208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209
4210         *red = intel_crtc->lut_r[regno] << 8;
4211         *green = intel_crtc->lut_g[regno] << 8;
4212         *blue = intel_crtc->lut_b[regno] << 8;
4213 }
4214
4215 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4216                                  u16 *blue, uint32_t size)
4217 {
4218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219         int i;
4220
4221         if (size != 256)
4222                 return;
4223
4224         for (i = 0; i < 256; i++) {
4225                 intel_crtc->lut_r[i] = red[i] >> 8;
4226                 intel_crtc->lut_g[i] = green[i] >> 8;
4227                 intel_crtc->lut_b[i] = blue[i] >> 8;
4228         }
4229
4230         intel_crtc_load_lut(crtc);
4231 }
4232
4233 /**
4234  * Get a pipe with a simple mode set on it for doing load-based monitor
4235  * detection.
4236  *
4237  * It will be up to the load-detect code to adjust the pipe as appropriate for
4238  * its requirements.  The pipe will be connected to no other encoders.
4239  *
4240  * Currently this code will only succeed if there is a pipe with no encoders
4241  * configured for it.  In the future, it could choose to temporarily disable
4242  * some outputs to free up a pipe for its use.
4243  *
4244  * \return crtc, or NULL if no pipes are available.
4245  */
4246
4247 /* VESA 640x480x72Hz mode to set on the pipe */
4248 static struct drm_display_mode load_detect_mode = {
4249         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4250                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4251 };
4252
4253 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4254                                             struct drm_connector *connector,
4255                                             struct drm_display_mode *mode,
4256                                             int *dpms_mode)
4257 {
4258         struct intel_crtc *intel_crtc;
4259         struct drm_crtc *possible_crtc;
4260         struct drm_crtc *supported_crtc =NULL;
4261         struct drm_encoder *encoder = &intel_encoder->enc;
4262         struct drm_crtc *crtc = NULL;
4263         struct drm_device *dev = encoder->dev;
4264         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4265         struct drm_crtc_helper_funcs *crtc_funcs;
4266         int i = -1;
4267
4268         /*
4269          * Algorithm gets a little messy:
4270          *   - if the connector already has an assigned crtc, use it (but make
4271          *     sure it's on first)
4272          *   - try to find the first unused crtc that can drive this connector,
4273          *     and use that if we find one
4274          *   - if there are no unused crtcs available, try to use the first
4275          *     one we found that supports the connector
4276          */
4277
4278         /* See if we already have a CRTC for this connector */
4279         if (encoder->crtc) {
4280                 crtc = encoder->crtc;
4281                 /* Make sure the crtc and connector are running */
4282                 intel_crtc = to_intel_crtc(crtc);
4283                 *dpms_mode = intel_crtc->dpms_mode;
4284                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4285                         crtc_funcs = crtc->helper_private;
4286                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4287                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4288                 }
4289                 return crtc;
4290         }
4291
4292         /* Find an unused one (if possible) */
4293         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4294                 i++;
4295                 if (!(encoder->possible_crtcs & (1 << i)))
4296                         continue;
4297                 if (!possible_crtc->enabled) {
4298                         crtc = possible_crtc;
4299                         break;
4300                 }
4301                 if (!supported_crtc)
4302                         supported_crtc = possible_crtc;
4303         }
4304
4305         /*
4306          * If we didn't find an unused CRTC, don't use any.
4307          */
4308         if (!crtc) {
4309                 return NULL;
4310         }
4311
4312         encoder->crtc = crtc;
4313         connector->encoder = encoder;
4314         intel_encoder->load_detect_temp = true;
4315
4316         intel_crtc = to_intel_crtc(crtc);
4317         *dpms_mode = intel_crtc->dpms_mode;
4318
4319         if (!crtc->enabled) {
4320                 if (!mode)
4321                         mode = &load_detect_mode;
4322                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4323         } else {
4324                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4325                         crtc_funcs = crtc->helper_private;
4326                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4327                 }
4328
4329                 /* Add this connector to the crtc */
4330                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4331                 encoder_funcs->commit(encoder);
4332         }
4333         /* let the connector get through one full cycle before testing */
4334         intel_wait_for_vblank(dev);
4335
4336         return crtc;
4337 }
4338
4339 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4340                                     struct drm_connector *connector, int dpms_mode)
4341 {
4342         struct drm_encoder *encoder = &intel_encoder->enc;
4343         struct drm_device *dev = encoder->dev;
4344         struct drm_crtc *crtc = encoder->crtc;
4345         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4346         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4347
4348         if (intel_encoder->load_detect_temp) {
4349                 encoder->crtc = NULL;
4350                 connector->encoder = NULL;
4351                 intel_encoder->load_detect_temp = false;
4352                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4353                 drm_helper_disable_unused_functions(dev);
4354         }
4355
4356         /* Switch crtc and encoder back off if necessary */
4357         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4358                 if (encoder->crtc == crtc)
4359                         encoder_funcs->dpms(encoder, dpms_mode);
4360                 crtc_funcs->dpms(crtc, dpms_mode);
4361         }
4362 }
4363
4364 /* Returns the clock of the currently programmed mode of the given pipe. */
4365 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4366 {
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4369         int pipe = intel_crtc->pipe;
4370         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4371         u32 fp;
4372         intel_clock_t clock;
4373
4374         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4375                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4376         else
4377                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4378
4379         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4380         if (IS_PINEVIEW(dev)) {
4381                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4382                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4383         } else {
4384                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4385                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4386         }
4387
4388         if (IS_I9XX(dev)) {
4389                 if (IS_PINEVIEW(dev))
4390                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4391                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4392                 else
4393                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4394                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4395
4396                 switch (dpll & DPLL_MODE_MASK) {
4397                 case DPLLB_MODE_DAC_SERIAL:
4398                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4399                                 5 : 10;
4400                         break;
4401                 case DPLLB_MODE_LVDS:
4402                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4403                                 7 : 14;
4404                         break;
4405                 default:
4406                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4407                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4408                         return 0;
4409                 }
4410
4411                 /* XXX: Handle the 100Mhz refclk */
4412                 intel_clock(dev, 96000, &clock);
4413         } else {
4414                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4415
4416                 if (is_lvds) {
4417                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4418                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4419                         clock.p2 = 14;
4420
4421                         if ((dpll & PLL_REF_INPUT_MASK) ==
4422                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4423                                 /* XXX: might not be 66MHz */
4424                                 intel_clock(dev, 66000, &clock);
4425                         } else
4426                                 intel_clock(dev, 48000, &clock);
4427                 } else {
4428                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4429                                 clock.p1 = 2;
4430                         else {
4431                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4432                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4433                         }
4434                         if (dpll & PLL_P2_DIVIDE_BY_4)
4435                                 clock.p2 = 4;
4436                         else
4437                                 clock.p2 = 2;
4438
4439                         intel_clock(dev, 48000, &clock);
4440                 }
4441         }
4442
4443         /* XXX: It would be nice to validate the clocks, but we can't reuse
4444          * i830PllIsValid() because it relies on the xf86_config connector
4445          * configuration being accurate, which it isn't necessarily.
4446          */
4447
4448         return clock.dot;
4449 }
4450
4451 /** Returns the currently programmed mode of the given pipe. */
4452 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4453                                              struct drm_crtc *crtc)
4454 {
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4457         int pipe = intel_crtc->pipe;
4458         struct drm_display_mode *mode;
4459         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4460         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4461         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4462         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4463
4464         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4465         if (!mode)
4466                 return NULL;
4467
4468         mode->clock = intel_crtc_clock_get(dev, crtc);
4469         mode->hdisplay = (htot & 0xffff) + 1;
4470         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4471         mode->hsync_start = (hsync & 0xffff) + 1;
4472         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4473         mode->vdisplay = (vtot & 0xffff) + 1;
4474         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4475         mode->vsync_start = (vsync & 0xffff) + 1;
4476         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4477
4478         drm_mode_set_name(mode);
4479         drm_mode_set_crtcinfo(mode, 0);
4480
4481         return mode;
4482 }
4483
4484 #define GPU_IDLE_TIMEOUT 500 /* ms */
4485
4486 /* When this timer fires, we've been idle for awhile */
4487 static void intel_gpu_idle_timer(unsigned long arg)
4488 {
4489         struct drm_device *dev = (struct drm_device *)arg;
4490         drm_i915_private_t *dev_priv = dev->dev_private;
4491
4492         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4493
4494         dev_priv->busy = false;
4495
4496         queue_work(dev_priv->wq, &dev_priv->idle_work);
4497 }
4498
4499 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4500
4501 static void intel_crtc_idle_timer(unsigned long arg)
4502 {
4503         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4504         struct drm_crtc *crtc = &intel_crtc->base;
4505         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4506
4507         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4508
4509         intel_crtc->busy = false;
4510
4511         queue_work(dev_priv->wq, &dev_priv->idle_work);
4512 }
4513
4514 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4515 {
4516         struct drm_device *dev = crtc->dev;
4517         drm_i915_private_t *dev_priv = dev->dev_private;
4518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4519         int pipe = intel_crtc->pipe;
4520         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4521         int dpll = I915_READ(dpll_reg);
4522
4523         if (HAS_PCH_SPLIT(dev))
4524                 return;
4525
4526         if (!dev_priv->lvds_downclock_avail)
4527                 return;
4528
4529         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4530                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4531
4532                 /* Unlock panel regs */
4533                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4534                            PANEL_UNLOCK_REGS);
4535
4536                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4537                 I915_WRITE(dpll_reg, dpll);
4538                 dpll = I915_READ(dpll_reg);
4539                 intel_wait_for_vblank(dev);
4540                 dpll = I915_READ(dpll_reg);
4541                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4542                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4543
4544                 /* ...and lock them again */
4545                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4546         }
4547
4548         /* Schedule downclock */
4549         if (schedule)
4550                 mod_timer(&intel_crtc->idle_timer, jiffies +
4551                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4552 }
4553
4554 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4555 {
4556         struct drm_device *dev = crtc->dev;
4557         drm_i915_private_t *dev_priv = dev->dev_private;
4558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4559         int pipe = intel_crtc->pipe;
4560         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4561         int dpll = I915_READ(dpll_reg);
4562
4563         if (HAS_PCH_SPLIT(dev))
4564                 return;
4565
4566         if (!dev_priv->lvds_downclock_avail)
4567                 return;
4568
4569         /*
4570          * Since this is called by a timer, we should never get here in
4571          * the manual case.
4572          */
4573         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4574                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4575
4576                 /* Unlock panel regs */
4577                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4578                            PANEL_UNLOCK_REGS);
4579
4580                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4581                 I915_WRITE(dpll_reg, dpll);
4582                 dpll = I915_READ(dpll_reg);
4583                 intel_wait_for_vblank(dev);
4584                 dpll = I915_READ(dpll_reg);
4585                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4586                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4587
4588                 /* ...and lock them again */
4589                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4590         }
4591
4592 }
4593
4594 /**
4595  * intel_idle_update - adjust clocks for idleness
4596  * @work: work struct
4597  *
4598  * Either the GPU or display (or both) went idle.  Check the busy status
4599  * here and adjust the CRTC and GPU clocks as necessary.
4600  */
4601 static void intel_idle_update(struct work_struct *work)
4602 {
4603         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4604                                                     idle_work);
4605         struct drm_device *dev = dev_priv->dev;
4606         struct drm_crtc *crtc;
4607         struct intel_crtc *intel_crtc;
4608         int enabled = 0;
4609
4610         if (!i915_powersave)
4611                 return;
4612
4613         mutex_lock(&dev->struct_mutex);
4614
4615         i915_update_gfx_val(dev_priv);
4616
4617         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4618                 /* Skip inactive CRTCs */
4619                 if (!crtc->fb)
4620                         continue;
4621
4622                 enabled++;
4623                 intel_crtc = to_intel_crtc(crtc);
4624                 if (!intel_crtc->busy)
4625                         intel_decrease_pllclock(crtc);
4626         }
4627
4628         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4629                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4630                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4631         }
4632
4633         mutex_unlock(&dev->struct_mutex);
4634 }
4635
4636 /**
4637  * intel_mark_busy - mark the GPU and possibly the display busy
4638  * @dev: drm device
4639  * @obj: object we're operating on
4640  *
4641  * Callers can use this function to indicate that the GPU is busy processing
4642  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4643  * buffer), we'll also mark the display as busy, so we know to increase its
4644  * clock frequency.
4645  */
4646 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4647 {
4648         drm_i915_private_t *dev_priv = dev->dev_private;
4649         struct drm_crtc *crtc = NULL;
4650         struct intel_framebuffer *intel_fb;
4651         struct intel_crtc *intel_crtc;
4652
4653         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4654                 return;
4655
4656         if (!dev_priv->busy) {
4657                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4658                         u32 fw_blc_self;
4659
4660                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4661                         fw_blc_self = I915_READ(FW_BLC_SELF);
4662                         fw_blc_self &= ~FW_BLC_SELF_EN;
4663                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4664                 }
4665                 dev_priv->busy = true;
4666         } else
4667                 mod_timer(&dev_priv->idle_timer, jiffies +
4668                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4669
4670         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4671                 if (!crtc->fb)
4672                         continue;
4673
4674                 intel_crtc = to_intel_crtc(crtc);
4675                 intel_fb = to_intel_framebuffer(crtc->fb);
4676                 if (intel_fb->obj == obj) {
4677                         if (!intel_crtc->busy) {
4678                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4679                                         u32 fw_blc_self;
4680
4681                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4682                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4683                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4684                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4685                                 }
4686                                 /* Non-busy -> busy, upclock */
4687                                 intel_increase_pllclock(crtc, true);
4688                                 intel_crtc->busy = true;
4689                         } else {
4690                                 /* Busy -> busy, put off timer */
4691                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4692                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4693                         }
4694                 }
4695         }
4696 }
4697
4698 static void intel_crtc_destroy(struct drm_crtc *crtc)
4699 {
4700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701
4702         drm_crtc_cleanup(crtc);
4703         kfree(intel_crtc);
4704 }
4705
4706 struct intel_unpin_work {
4707         struct work_struct work;
4708         struct drm_device *dev;
4709         struct drm_gem_object *old_fb_obj;
4710         struct drm_gem_object *pending_flip_obj;
4711         struct drm_pending_vblank_event *event;
4712         int pending;
4713 };
4714
4715 static void intel_unpin_work_fn(struct work_struct *__work)
4716 {
4717         struct intel_unpin_work *work =
4718                 container_of(__work, struct intel_unpin_work, work);
4719
4720         mutex_lock(&work->dev->struct_mutex);
4721         i915_gem_object_unpin(work->old_fb_obj);
4722         drm_gem_object_unreference(work->pending_flip_obj);
4723         drm_gem_object_unreference(work->old_fb_obj);
4724         mutex_unlock(&work->dev->struct_mutex);
4725         kfree(work);
4726 }
4727
4728 static void do_intel_finish_page_flip(struct drm_device *dev,
4729                                       struct drm_crtc *crtc)
4730 {
4731         drm_i915_private_t *dev_priv = dev->dev_private;
4732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733         struct intel_unpin_work *work;
4734         struct drm_i915_gem_object *obj_priv;
4735         struct drm_pending_vblank_event *e;
4736         struct timeval now;
4737         unsigned long flags;
4738
4739         /* Ignore early vblank irqs */
4740         if (intel_crtc == NULL)
4741                 return;
4742
4743         spin_lock_irqsave(&dev->event_lock, flags);
4744         work = intel_crtc->unpin_work;
4745         if (work == NULL || !work->pending) {
4746                 spin_unlock_irqrestore(&dev->event_lock, flags);
4747                 return;
4748         }
4749
4750         intel_crtc->unpin_work = NULL;
4751         drm_vblank_put(dev, intel_crtc->pipe);
4752
4753         if (work->event) {
4754                 e = work->event;
4755                 do_gettimeofday(&now);
4756                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4757                 e->event.tv_sec = now.tv_sec;
4758                 e->event.tv_usec = now.tv_usec;
4759                 list_add_tail(&e->base.link,
4760                               &e->base.file_priv->event_list);
4761                 wake_up_interruptible(&e->base.file_priv->event_wait);
4762         }
4763
4764         spin_unlock_irqrestore(&dev->event_lock, flags);
4765
4766         obj_priv = to_intel_bo(work->pending_flip_obj);
4767
4768         /* Initial scanout buffer will have a 0 pending flip count */
4769         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4770             atomic_dec_and_test(&obj_priv->pending_flip))
4771                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4772         schedule_work(&work->work);
4773 }
4774
4775 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4776 {
4777         drm_i915_private_t *dev_priv = dev->dev_private;
4778         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4779
4780         do_intel_finish_page_flip(dev, crtc);
4781 }
4782
4783 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4784 {
4785         drm_i915_private_t *dev_priv = dev->dev_private;
4786         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4787
4788         do_intel_finish_page_flip(dev, crtc);
4789 }
4790
4791 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4792 {
4793         drm_i915_private_t *dev_priv = dev->dev_private;
4794         struct intel_crtc *intel_crtc =
4795                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4796         unsigned long flags;
4797
4798         spin_lock_irqsave(&dev->event_lock, flags);
4799         if (intel_crtc->unpin_work) {
4800                 intel_crtc->unpin_work->pending = 1;
4801         } else {
4802                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4803         }
4804         spin_unlock_irqrestore(&dev->event_lock, flags);
4805 }
4806
4807 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4808                                 struct drm_framebuffer *fb,
4809                                 struct drm_pending_vblank_event *event)
4810 {
4811         struct drm_device *dev = crtc->dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         struct intel_framebuffer *intel_fb;
4814         struct drm_i915_gem_object *obj_priv;
4815         struct drm_gem_object *obj;
4816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4817         struct intel_unpin_work *work;
4818         unsigned long flags, offset;
4819         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4820         int ret, pipesrc;
4821         u32 flip_mask;
4822
4823         work = kzalloc(sizeof *work, GFP_KERNEL);
4824         if (work == NULL)
4825                 return -ENOMEM;
4826
4827         work->event = event;
4828         work->dev = crtc->dev;
4829         intel_fb = to_intel_framebuffer(crtc->fb);
4830         work->old_fb_obj = intel_fb->obj;
4831         INIT_WORK(&work->work, intel_unpin_work_fn);
4832
4833         /* We borrow the event spin lock for protecting unpin_work */
4834         spin_lock_irqsave(&dev->event_lock, flags);
4835         if (intel_crtc->unpin_work) {
4836                 spin_unlock_irqrestore(&dev->event_lock, flags);
4837                 kfree(work);
4838
4839                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4840                 return -EBUSY;
4841         }
4842         intel_crtc->unpin_work = work;
4843         spin_unlock_irqrestore(&dev->event_lock, flags);
4844
4845         intel_fb = to_intel_framebuffer(fb);
4846         obj = intel_fb->obj;
4847
4848         mutex_lock(&dev->struct_mutex);
4849         ret = intel_pin_and_fence_fb_obj(dev, obj);
4850         if (ret != 0) {
4851                 mutex_unlock(&dev->struct_mutex);
4852
4853                 spin_lock_irqsave(&dev->event_lock, flags);
4854                 intel_crtc->unpin_work = NULL;
4855                 spin_unlock_irqrestore(&dev->event_lock, flags);
4856
4857                 kfree(work);
4858
4859                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4860                                  to_intel_bo(obj));
4861                 return ret;
4862         }
4863
4864         /* Reference the objects for the scheduled work. */
4865         drm_gem_object_reference(work->old_fb_obj);
4866         drm_gem_object_reference(obj);
4867
4868         crtc->fb = fb;
4869         i915_gem_object_flush_write_domain(obj);
4870         drm_vblank_get(dev, intel_crtc->pipe);
4871         obj_priv = to_intel_bo(obj);
4872         atomic_inc(&obj_priv->pending_flip);
4873         work->pending_flip_obj = obj;
4874
4875         if (intel_crtc->plane)
4876                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4877         else
4878                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4879
4880         /* Wait for any previous flip to finish */
4881         if (IS_GEN3(dev))
4882                 while (I915_READ(ISR) & flip_mask)
4883                         ;
4884
4885         /* Offset into the new buffer for cases of shared fbs between CRTCs */
4886         offset = obj_priv->gtt_offset;
4887         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
4888
4889         BEGIN_LP_RING(4);
4890         if (IS_I965G(dev)) {
4891                 OUT_RING(MI_DISPLAY_FLIP |
4892                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4893                 OUT_RING(fb->pitch);
4894                 OUT_RING(offset | obj_priv->tiling_mode);
4895                 pipesrc = I915_READ(pipesrc_reg);
4896                 OUT_RING(pipesrc & 0x0fff0fff);
4897         } else {
4898                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4899                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4900                 OUT_RING(fb->pitch);
4901                 OUT_RING(offset);
4902                 OUT_RING(MI_NOOP);
4903         }
4904         ADVANCE_LP_RING();
4905
4906         mutex_unlock(&dev->struct_mutex);
4907
4908         return 0;
4909 }
4910
4911 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4912         .dpms = intel_crtc_dpms,
4913         .mode_fixup = intel_crtc_mode_fixup,
4914         .mode_set = intel_crtc_mode_set,
4915         .mode_set_base = intel_pipe_set_base,
4916         .mode_set_base_atomic = intel_pipe_set_base_atomic,
4917         .prepare = intel_crtc_prepare,
4918         .commit = intel_crtc_commit,
4919         .load_lut = intel_crtc_load_lut,
4920 };
4921
4922 static const struct drm_crtc_funcs intel_crtc_funcs = {
4923         .cursor_set = intel_crtc_cursor_set,
4924         .cursor_move = intel_crtc_cursor_move,
4925         .gamma_set = intel_crtc_gamma_set,
4926         .set_config = drm_crtc_helper_set_config,
4927         .destroy = intel_crtc_destroy,
4928         .page_flip = intel_crtc_page_flip,
4929 };
4930
4931
4932 static void intel_crtc_init(struct drm_device *dev, int pipe)
4933 {
4934         drm_i915_private_t *dev_priv = dev->dev_private;
4935         struct intel_crtc *intel_crtc;
4936         int i;
4937
4938         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4939         if (intel_crtc == NULL)
4940                 return;
4941
4942         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4943
4944         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4945         intel_crtc->pipe = pipe;
4946         intel_crtc->plane = pipe;
4947         for (i = 0; i < 256; i++) {
4948                 intel_crtc->lut_r[i] = i;
4949                 intel_crtc->lut_g[i] = i;
4950                 intel_crtc->lut_b[i] = i;
4951         }
4952
4953         /* Swap pipes & planes for FBC on pre-965 */
4954         intel_crtc->pipe = pipe;
4955         intel_crtc->plane = pipe;
4956         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4957                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4958                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4959         }
4960
4961         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4962                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4963         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4964         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4965
4966         intel_crtc->cursor_addr = 0;
4967         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4968         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4969
4970         intel_crtc->busy = false;
4971
4972         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4973                     (unsigned long)intel_crtc);
4974 }
4975
4976 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4977                                 struct drm_file *file_priv)
4978 {
4979         drm_i915_private_t *dev_priv = dev->dev_private;
4980         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4981         struct drm_mode_object *drmmode_obj;
4982         struct intel_crtc *crtc;
4983
4984         if (!dev_priv) {
4985                 DRM_ERROR("called with no initialization\n");
4986                 return -EINVAL;
4987         }
4988
4989         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4990                         DRM_MODE_OBJECT_CRTC);
4991
4992         if (!drmmode_obj) {
4993                 DRM_ERROR("no such CRTC id\n");
4994                 return -EINVAL;
4995         }
4996
4997         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4998         pipe_from_crtc_id->pipe = crtc->pipe;
4999
5000         return 0;
5001 }
5002
5003 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5004 {
5005         struct drm_crtc *crtc = NULL;
5006
5007         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5008                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5009                 if (intel_crtc->pipe == pipe)
5010                         break;
5011         }
5012         return crtc;
5013 }
5014
5015 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5016 {
5017         int index_mask = 0;
5018         struct drm_encoder *encoder;
5019         int entry = 0;
5020
5021         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5022                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5023                 if (type_mask & intel_encoder->clone_mask)
5024                         index_mask |= (1 << entry);
5025                 entry++;
5026         }
5027         return index_mask;
5028 }
5029
5030
5031 static void intel_setup_outputs(struct drm_device *dev)
5032 {
5033         struct drm_i915_private *dev_priv = dev->dev_private;
5034         struct drm_encoder *encoder;
5035
5036         intel_crt_init(dev);
5037
5038         /* Set up integrated LVDS */
5039         if (IS_MOBILE(dev) && !IS_I830(dev))
5040                 intel_lvds_init(dev);
5041
5042         if (HAS_PCH_SPLIT(dev)) {
5043                 int found;
5044
5045                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5046                         intel_dp_init(dev, DP_A);
5047
5048                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5049                         /* PCH SDVOB multiplex with HDMIB */
5050                         found = intel_sdvo_init(dev, PCH_SDVOB);
5051                         if (!found)
5052                                 intel_hdmi_init(dev, HDMIB);
5053                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5054                                 intel_dp_init(dev, PCH_DP_B);
5055                 }
5056
5057                 if (I915_READ(HDMIC) & PORT_DETECTED)
5058                         intel_hdmi_init(dev, HDMIC);
5059
5060                 if (I915_READ(HDMID) & PORT_DETECTED)
5061                         intel_hdmi_init(dev, HDMID);
5062
5063                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5064                         intel_dp_init(dev, PCH_DP_C);
5065
5066                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
5067                         intel_dp_init(dev, PCH_DP_D);
5068
5069         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5070                 bool found = false;
5071
5072                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5073                         DRM_DEBUG_KMS("probing SDVOB\n");
5074                         found = intel_sdvo_init(dev, SDVOB);
5075                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5076                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5077                                 intel_hdmi_init(dev, SDVOB);
5078                         }
5079
5080                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5081                                 DRM_DEBUG_KMS("probing DP_B\n");
5082                                 intel_dp_init(dev, DP_B);
5083                         }
5084                 }
5085
5086                 /* Before G4X SDVOC doesn't have its own detect register */
5087
5088                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5089                         DRM_DEBUG_KMS("probing SDVOC\n");
5090                         found = intel_sdvo_init(dev, SDVOC);
5091                 }
5092
5093                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5094
5095                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5096                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5097                                 intel_hdmi_init(dev, SDVOC);
5098                         }
5099                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5100                                 DRM_DEBUG_KMS("probing DP_C\n");
5101                                 intel_dp_init(dev, DP_C);
5102                         }
5103                 }
5104
5105                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5106                     (I915_READ(DP_D) & DP_DETECTED)) {
5107                         DRM_DEBUG_KMS("probing DP_D\n");
5108                         intel_dp_init(dev, DP_D);
5109                 }
5110         } else if (IS_GEN2(dev))
5111                 intel_dvo_init(dev);
5112
5113         if (SUPPORTS_TV(dev))
5114                 intel_tv_init(dev);
5115
5116         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5117                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5118
5119                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5120                 encoder->possible_clones = intel_encoder_clones(dev,
5121                                                 intel_encoder->clone_mask);
5122         }
5123 }
5124
5125 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5126 {
5127         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5128
5129         drm_framebuffer_cleanup(fb);
5130         drm_gem_object_unreference_unlocked(intel_fb->obj);
5131
5132         kfree(intel_fb);
5133 }
5134
5135 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5136                                                 struct drm_file *file_priv,
5137                                                 unsigned int *handle)
5138 {
5139         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5140         struct drm_gem_object *object = intel_fb->obj;
5141
5142         return drm_gem_handle_create(file_priv, object, handle);
5143 }
5144
5145 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5146         .destroy = intel_user_framebuffer_destroy,
5147         .create_handle = intel_user_framebuffer_create_handle,
5148 };
5149
5150 int intel_framebuffer_init(struct drm_device *dev,
5151                            struct intel_framebuffer *intel_fb,
5152                            struct drm_mode_fb_cmd *mode_cmd,
5153                            struct drm_gem_object *obj)
5154 {
5155         int ret;
5156
5157         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5158         if (ret) {
5159                 DRM_ERROR("framebuffer init failed %d\n", ret);
5160                 return ret;
5161         }
5162
5163         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5164         intel_fb->obj = obj;
5165         return 0;
5166 }
5167
5168 static struct drm_framebuffer *
5169 intel_user_framebuffer_create(struct drm_device *dev,
5170                               struct drm_file *filp,
5171                               struct drm_mode_fb_cmd *mode_cmd)
5172 {
5173         struct drm_gem_object *obj;
5174         struct intel_framebuffer *intel_fb;
5175         int ret;
5176
5177         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5178         if (!obj)
5179                 return NULL;
5180
5181         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5182         if (!intel_fb)
5183                 return NULL;
5184
5185         ret = intel_framebuffer_init(dev, intel_fb,
5186                                      mode_cmd, obj);
5187         if (ret) {
5188                 drm_gem_object_unreference_unlocked(obj);
5189                 kfree(intel_fb);
5190                 return NULL;
5191         }
5192
5193         return &intel_fb->base;
5194 }
5195
5196 static const struct drm_mode_config_funcs intel_mode_funcs = {
5197         .fb_create = intel_user_framebuffer_create,
5198         .output_poll_changed = intel_fb_output_poll_changed,
5199 };
5200
5201 static struct drm_gem_object *
5202 intel_alloc_power_context(struct drm_device *dev)
5203 {
5204         struct drm_gem_object *pwrctx;
5205         int ret;
5206
5207         pwrctx = i915_gem_alloc_object(dev, 4096);
5208         if (!pwrctx) {
5209                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5210                 return NULL;
5211         }
5212
5213         mutex_lock(&dev->struct_mutex);
5214         ret = i915_gem_object_pin(pwrctx, 4096);
5215         if (ret) {
5216                 DRM_ERROR("failed to pin power context: %d\n", ret);
5217                 goto err_unref;
5218         }
5219
5220         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5221         if (ret) {
5222                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5223                 goto err_unpin;
5224         }
5225         mutex_unlock(&dev->struct_mutex);
5226
5227         return pwrctx;
5228
5229 err_unpin:
5230         i915_gem_object_unpin(pwrctx);
5231 err_unref:
5232         drm_gem_object_unreference(pwrctx);
5233         mutex_unlock(&dev->struct_mutex);
5234         return NULL;
5235 }
5236
5237 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5238 {
5239         struct drm_i915_private *dev_priv = dev->dev_private;
5240         u16 rgvswctl;
5241
5242         rgvswctl = I915_READ16(MEMSWCTL);
5243         if (rgvswctl & MEMCTL_CMD_STS) {
5244                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5245                 return false; /* still busy with another command */
5246         }
5247
5248         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5249                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5250         I915_WRITE16(MEMSWCTL, rgvswctl);
5251         POSTING_READ16(MEMSWCTL);
5252
5253         rgvswctl |= MEMCTL_CMD_STS;
5254         I915_WRITE16(MEMSWCTL, rgvswctl);
5255
5256         return true;
5257 }
5258
5259 void ironlake_enable_drps(struct drm_device *dev)
5260 {
5261         struct drm_i915_private *dev_priv = dev->dev_private;
5262         u32 rgvmodectl = I915_READ(MEMMODECTL);
5263         u8 fmax, fmin, fstart, vstart;
5264         int i = 0;
5265
5266         /* 100ms RC evaluation intervals */
5267         I915_WRITE(RCUPEI, 100000);
5268         I915_WRITE(RCDNEI, 100000);
5269
5270         /* Set max/min thresholds to 90ms and 80ms respectively */
5271         I915_WRITE(RCBMAXAVG, 90000);
5272         I915_WRITE(RCBMINAVG, 80000);
5273
5274         I915_WRITE(MEMIHYST, 1);
5275
5276         /* Set up min, max, and cur for interrupt handling */
5277         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5278         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5279         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5280                 MEMMODE_FSTART_SHIFT;
5281         fstart = fmax;
5282
5283         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5284                 PXVFREQ_PX_SHIFT;
5285
5286         dev_priv->fmax = fstart; /* IPS callback will increase this */
5287         dev_priv->fstart = fstart;
5288
5289         dev_priv->max_delay = fmax;
5290         dev_priv->min_delay = fmin;
5291         dev_priv->cur_delay = fstart;
5292
5293         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5294                          fstart);
5295
5296         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5297
5298         /*
5299          * Interrupts will be enabled in ironlake_irq_postinstall
5300          */
5301
5302         I915_WRITE(VIDSTART, vstart);
5303         POSTING_READ(VIDSTART);
5304
5305         rgvmodectl |= MEMMODE_SWMODE_EN;
5306         I915_WRITE(MEMMODECTL, rgvmodectl);
5307
5308         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5309                 if (i++ > 100) {
5310                         DRM_ERROR("stuck trying to change perf mode\n");
5311                         break;
5312                 }
5313                 msleep(1);
5314         }
5315         msleep(1);
5316
5317         ironlake_set_drps(dev, fstart);
5318
5319         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5320                 I915_READ(0x112e0);
5321         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5322         dev_priv->last_count2 = I915_READ(0x112f4);
5323         getrawmonotonic(&dev_priv->last_time2);
5324 }
5325
5326 void ironlake_disable_drps(struct drm_device *dev)
5327 {
5328         struct drm_i915_private *dev_priv = dev->dev_private;
5329         u16 rgvswctl = I915_READ16(MEMSWCTL);
5330
5331         /* Ack interrupts, disable EFC interrupt */
5332         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5333         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5334         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5335         I915_WRITE(DEIIR, DE_PCU_EVENT);
5336         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5337
5338         /* Go back to the starting frequency */
5339         ironlake_set_drps(dev, dev_priv->fstart);
5340         msleep(1);
5341         rgvswctl |= MEMCTL_CMD_STS;
5342         I915_WRITE(MEMSWCTL, rgvswctl);
5343         msleep(1);
5344
5345 }
5346
5347 static unsigned long intel_pxfreq(u32 vidfreq)
5348 {
5349         unsigned long freq;
5350         int div = (vidfreq & 0x3f0000) >> 16;
5351         int post = (vidfreq & 0x3000) >> 12;
5352         int pre = (vidfreq & 0x7);
5353
5354         if (!pre)
5355                 return 0;
5356
5357         freq = ((div * 133333) / ((1<<post) * pre));
5358
5359         return freq;
5360 }
5361
5362 void intel_init_emon(struct drm_device *dev)
5363 {
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365         u32 lcfuse;
5366         u8 pxw[16];
5367         int i;
5368
5369         /* Disable to program */
5370         I915_WRITE(ECR, 0);
5371         POSTING_READ(ECR);
5372
5373         /* Program energy weights for various events */
5374         I915_WRITE(SDEW, 0x15040d00);
5375         I915_WRITE(CSIEW0, 0x007f0000);
5376         I915_WRITE(CSIEW1, 0x1e220004);
5377         I915_WRITE(CSIEW2, 0x04000004);
5378
5379         for (i = 0; i < 5; i++)
5380                 I915_WRITE(PEW + (i * 4), 0);
5381         for (i = 0; i < 3; i++)
5382                 I915_WRITE(DEW + (i * 4), 0);
5383
5384         /* Program P-state weights to account for frequency power adjustment */
5385         for (i = 0; i < 16; i++) {
5386                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5387                 unsigned long freq = intel_pxfreq(pxvidfreq);
5388                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5389                         PXVFREQ_PX_SHIFT;
5390                 unsigned long val;
5391
5392                 val = vid * vid;
5393                 val *= (freq / 1000);
5394                 val *= 255;
5395                 val /= (127*127*900);
5396                 if (val > 0xff)
5397                         DRM_ERROR("bad pxval: %ld\n", val);
5398                 pxw[i] = val;
5399         }
5400         /* Render standby states get 0 weight */
5401         pxw[14] = 0;
5402         pxw[15] = 0;
5403
5404         for (i = 0; i < 4; i++) {
5405                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5406                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5407                 I915_WRITE(PXW + (i * 4), val);
5408         }
5409
5410         /* Adjust magic regs to magic values (more experimental results) */
5411         I915_WRITE(OGW0, 0);
5412         I915_WRITE(OGW1, 0);
5413         I915_WRITE(EG0, 0x00007f00);
5414         I915_WRITE(EG1, 0x0000000e);
5415         I915_WRITE(EG2, 0x000e0000);
5416         I915_WRITE(EG3, 0x68000300);
5417         I915_WRITE(EG4, 0x42000000);
5418         I915_WRITE(EG5, 0x00140031);
5419         I915_WRITE(EG6, 0);
5420         I915_WRITE(EG7, 0);
5421
5422         for (i = 0; i < 8; i++)
5423                 I915_WRITE(PXWL + (i * 4), 0);
5424
5425         /* Enable PMON + select events */
5426         I915_WRITE(ECR, 0x80000019);
5427
5428         lcfuse = I915_READ(LCFUSE02);
5429
5430         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5431 }
5432
5433 void intel_init_clock_gating(struct drm_device *dev)
5434 {
5435         struct drm_i915_private *dev_priv = dev->dev_private;
5436
5437         /*
5438          * Disable clock gating reported to work incorrectly according to the
5439          * specs, but enable as much else as we can.
5440          */
5441         if (HAS_PCH_SPLIT(dev)) {
5442                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5443
5444                 if (IS_IRONLAKE(dev)) {
5445                         /* Required for FBC */
5446                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5447                         /* Required for CxSR */
5448                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5449
5450                         I915_WRITE(PCH_3DCGDIS0,
5451                                    MARIUNIT_CLOCK_GATE_DISABLE |
5452                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5453                 }
5454
5455                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5456
5457                 /*
5458                  * According to the spec the following bits should be set in
5459                  * order to enable memory self-refresh
5460                  * The bit 22/21 of 0x42004
5461                  * The bit 5 of 0x42020
5462                  * The bit 15 of 0x45000
5463                  */
5464                 if (IS_IRONLAKE(dev)) {
5465                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5466                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5467                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5468                         I915_WRITE(ILK_DSPCLK_GATE,
5469                                         (I915_READ(ILK_DSPCLK_GATE) |
5470                                                 ILK_DPARB_CLK_GATE));
5471                         I915_WRITE(DISP_ARB_CTL,
5472                                         (I915_READ(DISP_ARB_CTL) |
5473                                                 DISP_FBC_WM_DIS));
5474                 }
5475                 return;
5476         } else if (IS_G4X(dev)) {
5477                 uint32_t dspclk_gate;
5478                 I915_WRITE(RENCLK_GATE_D1, 0);
5479                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5480                        GS_UNIT_CLOCK_GATE_DISABLE |
5481                        CL_UNIT_CLOCK_GATE_DISABLE);
5482                 I915_WRITE(RAMCLK_GATE_D, 0);
5483                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5484                         OVRUNIT_CLOCK_GATE_DISABLE |
5485                         OVCUNIT_CLOCK_GATE_DISABLE;
5486                 if (IS_GM45(dev))
5487                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5488                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5489         } else if (IS_I965GM(dev)) {
5490                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5491                 I915_WRITE(RENCLK_GATE_D2, 0);
5492                 I915_WRITE(DSPCLK_GATE_D, 0);
5493                 I915_WRITE(RAMCLK_GATE_D, 0);
5494                 I915_WRITE16(DEUC, 0);
5495         } else if (IS_I965G(dev)) {
5496                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5497                        I965_RCC_CLOCK_GATE_DISABLE |
5498                        I965_RCPB_CLOCK_GATE_DISABLE |
5499                        I965_ISC_CLOCK_GATE_DISABLE |
5500                        I965_FBC_CLOCK_GATE_DISABLE);
5501                 I915_WRITE(RENCLK_GATE_D2, 0);
5502         } else if (IS_I9XX(dev)) {
5503                 u32 dstate = I915_READ(D_STATE);
5504
5505                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5506                         DSTATE_DOT_CLOCK_GATING;
5507                 I915_WRITE(D_STATE, dstate);
5508         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5509                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5510         } else if (IS_I830(dev)) {
5511                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5512         }
5513
5514         /*
5515          * GPU can automatically power down the render unit if given a page
5516          * to save state.
5517          */
5518         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5519                 struct drm_i915_gem_object *obj_priv = NULL;
5520
5521                 if (dev_priv->pwrctx) {
5522                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5523                 } else {
5524                         struct drm_gem_object *pwrctx;
5525
5526                         pwrctx = intel_alloc_power_context(dev);
5527                         if (pwrctx) {
5528                                 dev_priv->pwrctx = pwrctx;
5529                                 obj_priv = to_intel_bo(pwrctx);
5530                         }
5531                 }
5532
5533                 if (obj_priv) {
5534                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5535                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5536                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5537                 }
5538         }
5539 }
5540
5541 /* Set up chip specific display functions */
5542 static void intel_init_display(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545
5546         /* We always want a DPMS function */
5547         if (HAS_PCH_SPLIT(dev))
5548                 dev_priv->display.dpms = ironlake_crtc_dpms;
5549         else
5550                 dev_priv->display.dpms = i9xx_crtc_dpms;
5551
5552         if (I915_HAS_FBC(dev)) {
5553                 if (IS_GM45(dev)) {
5554                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5555                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5556                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5557                 } else if (IS_I965GM(dev)) {
5558                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5559                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5560                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5561                 }
5562                 /* 855GM needs testing */
5563         }
5564
5565         /* Returns the core display clock speed */
5566         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5567                 dev_priv->display.get_display_clock_speed =
5568                         i945_get_display_clock_speed;
5569         else if (IS_I915G(dev))
5570                 dev_priv->display.get_display_clock_speed =
5571                         i915_get_display_clock_speed;
5572         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5573                 dev_priv->display.get_display_clock_speed =
5574                         i9xx_misc_get_display_clock_speed;
5575         else if (IS_I915GM(dev))
5576                 dev_priv->display.get_display_clock_speed =
5577                         i915gm_get_display_clock_speed;
5578         else if (IS_I865G(dev))
5579                 dev_priv->display.get_display_clock_speed =
5580                         i865_get_display_clock_speed;
5581         else if (IS_I85X(dev))
5582                 dev_priv->display.get_display_clock_speed =
5583                         i855_get_display_clock_speed;
5584         else /* 852, 830 */
5585                 dev_priv->display.get_display_clock_speed =
5586                         i830_get_display_clock_speed;
5587
5588         /* For FIFO watermark updates */
5589         if (HAS_PCH_SPLIT(dev)) {
5590                 if (IS_IRONLAKE(dev)) {
5591                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5592                                 dev_priv->display.update_wm = ironlake_update_wm;
5593                         else {
5594                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5595                                               "Disable CxSR\n");
5596                                 dev_priv->display.update_wm = NULL;
5597                         }
5598                 } else
5599                         dev_priv->display.update_wm = NULL;
5600         } else if (IS_PINEVIEW(dev)) {
5601                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5602                                             dev_priv->is_ddr3,
5603                                             dev_priv->fsb_freq,
5604                                             dev_priv->mem_freq)) {
5605                         DRM_INFO("failed to find known CxSR latency "
5606                                  "(found ddr%s fsb freq %d, mem freq %d), "
5607                                  "disabling CxSR\n",
5608                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5609                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5610                         /* Disable CxSR and never update its watermark again */
5611                         pineview_disable_cxsr(dev);
5612                         dev_priv->display.update_wm = NULL;
5613                 } else
5614                         dev_priv->display.update_wm = pineview_update_wm;
5615         } else if (IS_G4X(dev))
5616                 dev_priv->display.update_wm = g4x_update_wm;
5617         else if (IS_I965G(dev))
5618                 dev_priv->display.update_wm = i965_update_wm;
5619         else if (IS_I9XX(dev)) {
5620                 dev_priv->display.update_wm = i9xx_update_wm;
5621                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5622         } else if (IS_I85X(dev)) {
5623                 dev_priv->display.update_wm = i9xx_update_wm;
5624                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5625         } else {
5626                 dev_priv->display.update_wm = i830_update_wm;
5627                 if (IS_845G(dev))
5628                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5629                 else
5630                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5631         }
5632 }
5633
5634 /*
5635  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5636  * resume, or other times.  This quirk makes sure that's the case for
5637  * affected systems.
5638  */
5639 static void quirk_pipea_force (struct drm_device *dev)
5640 {
5641         struct drm_i915_private *dev_priv = dev->dev_private;
5642
5643         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5644         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5645 }
5646
5647 struct intel_quirk {
5648         int device;
5649         int subsystem_vendor;
5650         int subsystem_device;
5651         void (*hook)(struct drm_device *dev);
5652 };
5653
5654 struct intel_quirk intel_quirks[] = {
5655         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5656         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5657         /* HP Mini needs pipe A force quirk (LP: #322104) */
5658         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5659
5660         /* Thinkpad R31 needs pipe A force quirk */
5661         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5662         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5663         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5664
5665         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5666         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5667         /* ThinkPad X40 needs pipe A force quirk */
5668
5669         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5670         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5671
5672         /* 855 & before need to leave pipe A & dpll A up */
5673         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5674         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5675 };
5676
5677 static void intel_init_quirks(struct drm_device *dev)
5678 {
5679         struct pci_dev *d = dev->pdev;
5680         int i;
5681
5682         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5683                 struct intel_quirk *q = &intel_quirks[i];
5684
5685                 if (d->device == q->device &&
5686                     (d->subsystem_vendor == q->subsystem_vendor ||
5687                      q->subsystem_vendor == PCI_ANY_ID) &&
5688                     (d->subsystem_device == q->subsystem_device ||
5689                      q->subsystem_device == PCI_ANY_ID))
5690                         q->hook(dev);
5691         }
5692 }
5693
5694 void intel_modeset_init(struct drm_device *dev)
5695 {
5696         struct drm_i915_private *dev_priv = dev->dev_private;
5697         int i;
5698
5699         drm_mode_config_init(dev);
5700
5701         dev->mode_config.min_width = 0;
5702         dev->mode_config.min_height = 0;
5703
5704         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5705
5706         intel_init_quirks(dev);
5707
5708         intel_init_display(dev);
5709
5710         if (IS_I965G(dev)) {
5711                 dev->mode_config.max_width = 8192;
5712                 dev->mode_config.max_height = 8192;
5713         } else if (IS_I9XX(dev)) {
5714                 dev->mode_config.max_width = 4096;
5715                 dev->mode_config.max_height = 4096;
5716         } else {
5717                 dev->mode_config.max_width = 2048;
5718                 dev->mode_config.max_height = 2048;
5719         }
5720
5721         /* set memory base */
5722         if (IS_I9XX(dev))
5723                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5724         else
5725                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5726
5727         if (IS_MOBILE(dev) || IS_I9XX(dev))
5728                 dev_priv->num_pipe = 2;
5729         else
5730                 dev_priv->num_pipe = 1;
5731         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5732                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5733
5734         for (i = 0; i < dev_priv->num_pipe; i++) {
5735                 intel_crtc_init(dev, i);
5736         }
5737
5738         intel_setup_outputs(dev);
5739
5740         intel_init_clock_gating(dev);
5741
5742         if (IS_IRONLAKE_M(dev)) {
5743                 ironlake_enable_drps(dev);
5744                 intel_init_emon(dev);
5745         }
5746
5747         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5748         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5749                     (unsigned long)dev);
5750
5751         intel_setup_overlay(dev);
5752 }
5753
5754 void intel_modeset_cleanup(struct drm_device *dev)
5755 {
5756         struct drm_i915_private *dev_priv = dev->dev_private;
5757         struct drm_crtc *crtc;
5758         struct intel_crtc *intel_crtc;
5759
5760         mutex_lock(&dev->struct_mutex);
5761
5762         drm_kms_helper_poll_fini(dev);
5763         intel_fbdev_fini(dev);
5764
5765         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5766                 /* Skip inactive CRTCs */
5767                 if (!crtc->fb)
5768                         continue;
5769
5770                 intel_crtc = to_intel_crtc(crtc);
5771                 intel_increase_pllclock(crtc, false);
5772                 del_timer_sync(&intel_crtc->idle_timer);
5773         }
5774
5775         del_timer_sync(&dev_priv->idle_timer);
5776
5777         if (dev_priv->display.disable_fbc)
5778                 dev_priv->display.disable_fbc(dev);
5779
5780         if (dev_priv->pwrctx) {
5781                 struct drm_i915_gem_object *obj_priv;
5782
5783                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5784                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5785                 I915_READ(PWRCTXA);
5786                 i915_gem_object_unpin(dev_priv->pwrctx);
5787                 drm_gem_object_unreference(dev_priv->pwrctx);
5788         }
5789
5790         if (IS_IRONLAKE_M(dev))
5791                 ironlake_disable_drps(dev);
5792
5793         mutex_unlock(&dev->struct_mutex);
5794
5795         drm_mode_config_cleanup(dev);
5796 }
5797
5798
5799 /*
5800  * Return which encoder is currently attached for connector.
5801  */
5802 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5803 {
5804         struct drm_mode_object *obj;
5805         struct drm_encoder *encoder;
5806         int i;
5807
5808         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5809                 if (connector->encoder_ids[i] == 0)
5810                         break;
5811
5812                 obj = drm_mode_object_find(connector->dev,
5813                                            connector->encoder_ids[i],
5814                                            DRM_MODE_OBJECT_ENCODER);
5815                 if (!obj)
5816                         continue;
5817
5818                 encoder = obj_to_encoder(obj);
5819                 return encoder;
5820         }
5821         return NULL;
5822 }
5823
5824 /*
5825  * set vga decode state - true == enable VGA decode
5826  */
5827 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5828 {
5829         struct drm_i915_private *dev_priv = dev->dev_private;
5830         u16 gmch_ctrl;
5831
5832         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5833         if (state)
5834                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5835         else
5836                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5837         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5838         return 0;
5839 }