2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
178 .find_pll = intel_g4x_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
207 .find_pll = intel_g4x_find_best_PLL,
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
222 .find_pll = intel_g4x_find_best_PLL,
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
269 /* Ironlake / Sandybridge
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 const intel_limit_t *limit;
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
370 if (refclk == 100000)
371 limit = &intel_limits_ironlake_dual_lvds_100m;
373 limit = &intel_limits_ironlake_dual_lvds;
375 if (refclk == 100000)
376 limit = &intel_limits_ironlake_single_lvds_100m;
378 limit = &intel_limits_ironlake_single_lvds;
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
382 limit = &intel_limits_ironlake_display_port;
384 limit = &intel_limits_ironlake_dac;
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
398 /* LVDS with dual channel */
399 limit = &intel_limits_g4x_dual_channel_lvds;
401 /* LVDS with dual channel */
402 limit = &intel_limits_g4x_single_channel_lvds;
403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405 limit = &intel_limits_g4x_hdmi;
406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407 limit = &intel_limits_g4x_sdvo;
408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409 limit = &intel_limits_g4x_display_port;
410 } else /* The option is for other outputs */
411 limit = &intel_limits_i9xx_sdvo;
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
421 if (HAS_PCH_SPLIT(dev))
422 limit = intel_ironlake_limit(crtc, refclk);
423 else if (IS_G4X(dev)) {
424 limit = intel_g4x_limit(crtc);
425 } else if (IS_PINEVIEW(dev)) {
426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427 limit = &intel_limits_pineview_lvds;
429 limit = &intel_limits_pineview_sdvo;
430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
434 limit = &intel_limits_i9xx_sdvo;
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437 limit = &intel_limits_i8xx_lvds;
439 limit = &intel_limits_i8xx_dvo;
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
466 * Returns whether any output on the specified pipe is of the specified type
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
481 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
492 INTELPllInvalid("p1 out of range\n");
493 if (clock->p < limit->p.min || limit->p.max < clock->p)
494 INTELPllInvalid("p out of range\n");
495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
496 INTELPllInvalid("m2 out of range\n");
497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
498 INTELPllInvalid("m1 out of range\n");
499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500 INTELPllInvalid("m1 <= m2\n");
501 if (clock->m < limit->m.min || limit->m.max < clock->m)
502 INTELPllInvalid("m out of range\n");
503 if (clock->n < limit->n.min || limit->n.max < clock->n)
504 INTELPllInvalid("n out of range\n");
505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506 INTELPllInvalid("vco out of range\n");
507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511 INTELPllInvalid("dot out of range\n");
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527 (I915_READ(LVDS)) != 0) {
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 clock.p2 = limit->p2.p2_fast;
538 clock.p2 = limit->p2.p2_slow;
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
543 clock.p2 = limit->p2.p2_fast;
546 memset(best_clock, 0, sizeof(*best_clock));
548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
561 intel_clock(dev, refclk, &clock);
562 if (!intel_PLL_is_valid(dev, limit,
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
576 return (err != target);
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
595 if (HAS_PCH_SPLIT(dev))
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
601 clock.p2 = limit->p2.p2_fast;
603 clock.p2 = limit->p2.p2_slow;
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
608 clock.p2 = limit->p2.p2_fast;
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
613 /* based on hardware requirement, prefer smaller n to precision */
614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615 /* based on hardware requirement, prefere larger m1,m2 */
616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
624 intel_clock(dev, refclk, &clock);
625 if (!intel_PLL_is_valid(dev, limit,
629 this_err = abs(clock.dot - target);
630 if (this_err < err_most) {
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
647 struct drm_device *dev = crtc->dev;
650 if (target < 200000) {
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
674 if (target < 200000) {
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
696 * intel_wait_for_vblank - wait for vblank on a given pipe
698 * @pipe: pipe to wait for
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int pipestat_reg = PIPESTAT(pipe);
708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
724 /* Wait for vblank interrupt bit to set */
725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
728 DRM_DEBUG_KMS("vblank wait timed out\n");
732 * intel_wait_for_pipe_off - wait for pipe to turn off
734 * @pipe: pipe to wait for
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
741 * wait for the pipe register state bit to turn off
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
750 struct drm_i915_private *dev_priv = dev->dev_private;
752 if (INTEL_INFO(dev)->gen >= 4) {
753 int reg = PIPECONF(pipe);
755 /* Wait for the Pipe State to go off */
756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
761 int reg = PIPEDSL(pipe);
762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
764 /* Wait for the display line to settle */
766 last_line = I915_READ(reg) & DSL_LINEMASK;
768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
775 static const char *state_string(bool enabled)
777 return enabled ? "on" : "off";
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
806 if (HAS_PCH_CPT(dev_priv->dev)) {
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
892 int pp_reg, lvds_reg;
894 enum pipe panel_pipe = PIPE_A;
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
918 static void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
930 pipe_name(pipe), state_string(state), state_string(cur_state));
932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
935 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
941 reg = DSPCNTR(plane);
942 val = I915_READ(reg);
943 WARN(!(val & DISPLAY_PLANE_ENABLE),
944 "plane %c assertion failure, should be active but is disabled\n",
948 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
955 /* Planes are fixed to pipes on ILK+ */
956 if (HAS_PCH_SPLIT(dev_priv->dev))
959 /* Need to check both planes against the pipe */
960 for (i = 0; i < 2; i++) {
962 val = I915_READ(reg);
963 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964 DISPPLANE_SEL_PIPE_SHIFT;
965 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
966 "plane %c assertion failure, should be off on pipe %c but is still active\n",
967 plane_name(i), pipe_name(pipe));
971 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
976 val = I915_READ(PCH_DREF_CONTROL);
977 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978 DREF_SUPERSPREAD_SOURCE_MASK));
979 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
982 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
989 reg = TRANSCONF(pipe);
990 val = I915_READ(reg);
991 enabled = !!(val & TRANS_ENABLE);
993 "transcoder assertion failed, should be off on pipe %c but is still active\n",
997 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998 enum pipe pipe, u32 port_sel, u32 val)
1000 if ((val & DP_PORT_EN) == 0)
1003 if (HAS_PCH_CPT(dev_priv->dev)) {
1004 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1009 if ((val & DP_PIPE_MASK) != (pipe << 30))
1015 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 val)
1018 if ((val & PORT_ENABLE) == 0)
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1025 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1031 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe, u32 val)
1034 if ((val & LVDS_PORT_EN) == 0)
1037 if (HAS_PCH_CPT(dev_priv->dev)) {
1038 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1041 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1047 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, u32 val)
1050 if ((val & ADPA_DAC_ENABLE) == 0)
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1056 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1062 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1063 enum pipe pipe, int reg, u32 port_sel)
1065 u32 val = I915_READ(reg);
1066 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1067 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1068 reg, pipe_name(pipe));
1071 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, int reg)
1074 u32 val = I915_READ(reg);
1075 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1076 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1077 reg, pipe_name(pipe));
1080 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1091 val = I915_READ(reg);
1092 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1093 "PCH VGA enabled on transcoder %c, should be disabled\n",
1097 val = I915_READ(reg);
1098 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1099 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1108 * intel_enable_pll - enable a PLL
1109 * @dev_priv: i915 private structure
1110 * @pipe: pipe PLL to enable
1112 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1113 * make sure the PLL reg is writable first though, since the panel write
1114 * protect mechanism may be enabled.
1116 * Note! This is for pre-ILK only.
1118 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1123 /* No really, not for ILK+ */
1124 BUG_ON(dev_priv->info->gen >= 5);
1126 /* PLL is protected by panel, make sure we can write it */
1127 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128 assert_panel_unlocked(dev_priv, pipe);
1131 val = I915_READ(reg);
1132 val |= DPLL_VCO_ENABLE;
1134 /* We do this three times for luck */
1135 I915_WRITE(reg, val);
1137 udelay(150); /* wait for warmup */
1138 I915_WRITE(reg, val);
1140 udelay(150); /* wait for warmup */
1141 I915_WRITE(reg, val);
1143 udelay(150); /* wait for warmup */
1147 * intel_disable_pll - disable a PLL
1148 * @dev_priv: i915 private structure
1149 * @pipe: pipe PLL to disable
1151 * Disable the PLL for @pipe, making sure the pipe is off first.
1153 * Note! This is for pre-ILK only.
1155 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1160 /* Don't disable pipe A or pipe A PLLs if needed */
1161 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1164 /* Make sure the pipe isn't still relying on us */
1165 assert_pipe_disabled(dev_priv, pipe);
1168 val = I915_READ(reg);
1169 val &= ~DPLL_VCO_ENABLE;
1170 I915_WRITE(reg, val);
1175 * intel_enable_pch_pll - enable PCH PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to enable
1179 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180 * drives the transcoder clock.
1182 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1191 /* PCH only available on ILK+ */
1192 BUG_ON(dev_priv->info->gen < 5);
1194 /* PCH refclock must be enabled first */
1195 assert_pch_refclk_enabled(dev_priv);
1197 reg = PCH_DPLL(pipe);
1198 val = I915_READ(reg);
1199 val |= DPLL_VCO_ENABLE;
1200 I915_WRITE(reg, val);
1205 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1217 /* Make sure transcoder isn't still depending on us */
1218 assert_transcoder_disabled(dev_priv, pipe);
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1228 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1234 /* PCH only available on ILK+ */
1235 BUG_ON(dev_priv->info->gen < 5);
1237 /* Make sure PCH DPLL is enabled */
1238 assert_pch_pll_enabled(dev_priv, pipe);
1240 /* FDI must be feeding us bits for PCH ports */
1241 assert_fdi_tx_enabled(dev_priv, pipe);
1242 assert_fdi_rx_enabled(dev_priv, pipe);
1244 reg = TRANSCONF(pipe);
1245 val = I915_READ(reg);
1247 if (HAS_PCH_IBX(dev_priv->dev)) {
1249 * make the BPC in transcoder be consistent with
1250 * that in pipeconf reg.
1252 val &= ~PIPE_BPC_MASK;
1253 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1255 I915_WRITE(reg, val | TRANS_ENABLE);
1256 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1260 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1266 /* FDI relies on the transcoder */
1267 assert_fdi_tx_disabled(dev_priv, pipe);
1268 assert_fdi_rx_disabled(dev_priv, pipe);
1270 /* Ports must be off as well */
1271 assert_pch_ports_disabled(dev_priv, pipe);
1273 reg = TRANSCONF(pipe);
1274 val = I915_READ(reg);
1275 val &= ~TRANS_ENABLE;
1276 I915_WRITE(reg, val);
1277 /* wait for PCH transcoder off, transcoder state */
1278 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1283 * intel_enable_pipe - enable a pipe, asserting requirements
1284 * @dev_priv: i915 private structure
1285 * @pipe: pipe to enable
1286 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1288 * Enable @pipe, making sure that various hardware specific requirements
1289 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1291 * @pipe should be %PIPE_A or %PIPE_B.
1293 * Will wait until the pipe is actually running (i.e. first vblank) before
1296 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1303 * A pipe without a PLL won't actually be able to drive bits from
1304 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1307 if (!HAS_PCH_SPLIT(dev_priv->dev))
1308 assert_pll_enabled(dev_priv, pipe);
1311 /* if driving the PCH, we need FDI enabled */
1312 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1315 /* FIXME: assert CPU port conditions for SNB+ */
1318 reg = PIPECONF(pipe);
1319 val = I915_READ(reg);
1320 if (val & PIPECONF_ENABLE)
1323 I915_WRITE(reg, val | PIPECONF_ENABLE);
1324 intel_wait_for_vblank(dev_priv->dev, pipe);
1328 * intel_disable_pipe - disable a pipe, asserting requirements
1329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to disable
1332 * Disable @pipe, making sure that various hardware specific requirements
1333 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1335 * @pipe should be %PIPE_A or %PIPE_B.
1337 * Will wait until the pipe has shut down before returning.
1339 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1346 * Make sure planes won't keep trying to pump pixels to us,
1347 * or we might hang the display.
1349 assert_planes_disabled(dev_priv, pipe);
1351 /* Don't disable pipe A or pipe A PLLs if needed */
1352 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
1357 if ((val & PIPECONF_ENABLE) == 0)
1360 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1361 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1365 * Plane regs are double buffered, going from enabled->disabled needs a
1366 * trigger in order to latch. The display address reg provides this.
1368 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1371 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1376 * intel_enable_plane - enable a display plane on a given pipe
1377 * @dev_priv: i915 private structure
1378 * @plane: plane to enable
1379 * @pipe: pipe being fed
1381 * Enable @plane on @pipe, making sure that @pipe is running first.
1383 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384 enum plane plane, enum pipe pipe)
1389 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390 assert_pipe_enabled(dev_priv, pipe);
1392 reg = DSPCNTR(plane);
1393 val = I915_READ(reg);
1394 if (val & DISPLAY_PLANE_ENABLE)
1397 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1398 intel_flush_display_plane(dev_priv, plane);
1399 intel_wait_for_vblank(dev_priv->dev, pipe);
1403 * intel_disable_plane - disable a display plane
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to disable
1406 * @pipe: pipe consuming the data
1408 * Disable @plane; should be an independent operation.
1410 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1416 reg = DSPCNTR(plane);
1417 val = I915_READ(reg);
1418 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1421 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1422 intel_flush_display_plane(dev_priv, plane);
1423 intel_wait_for_vblank(dev_priv->dev, pipe);
1426 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1427 enum pipe pipe, int reg, u32 port_sel)
1429 u32 val = I915_READ(reg);
1430 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1431 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1432 I915_WRITE(reg, val & ~DP_PORT_EN);
1436 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg)
1439 u32 val = I915_READ(reg);
1440 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1441 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1443 I915_WRITE(reg, val & ~PORT_ENABLE);
1447 /* Disable any ports connected to this transcoder */
1448 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1453 val = I915_READ(PCH_PP_CONTROL);
1454 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1456 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1461 val = I915_READ(reg);
1462 if (adpa_pipe_enabled(dev_priv, pipe, val))
1463 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1466 val = I915_READ(reg);
1467 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1468 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1469 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1474 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476 disable_pch_hdmi(dev_priv, pipe, HDMID);
1479 static void i8xx_disable_fbc(struct drm_device *dev)
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1484 /* Disable compression */
1485 fbc_ctl = I915_READ(FBC_CONTROL);
1486 if ((fbc_ctl & FBC_CTL_EN) == 0)
1489 fbc_ctl &= ~FBC_CTL_EN;
1490 I915_WRITE(FBC_CONTROL, fbc_ctl);
1492 /* Wait for compressing bit to clear */
1493 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494 DRM_DEBUG_KMS("FBC idle timed out\n");
1498 DRM_DEBUG_KMS("disabled FBC\n");
1501 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1503 struct drm_device *dev = crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_framebuffer *fb = crtc->fb;
1506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1507 struct drm_i915_gem_object *obj = intel_fb->obj;
1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1511 u32 fbc_ctl, fbc_ctl2;
1513 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514 if (fb->pitch < cfb_pitch)
1515 cfb_pitch = fb->pitch;
1517 /* FBC_CTL wants 64B units */
1518 cfb_pitch = (cfb_pitch / 64) - 1;
1519 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1521 /* Clear old tags */
1522 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523 I915_WRITE(FBC_TAG + (i * 4), 0);
1526 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1528 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1532 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1534 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1535 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1536 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1537 fbc_ctl |= obj->fence_reg;
1538 I915_WRITE(FBC_CONTROL, fbc_ctl);
1540 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541 cfb_pitch, crtc->y, intel_crtc->plane);
1544 static bool i8xx_fbc_enabled(struct drm_device *dev)
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1548 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1551 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557 struct drm_i915_gem_object *obj = intel_fb->obj;
1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1560 unsigned long stall_watermark = 200;
1563 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1564 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1565 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1567 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1573 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1575 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1578 static void g4x_disable_fbc(struct drm_device *dev)
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1583 /* Disable compression */
1584 dpfc_ctl = I915_READ(DPFC_CONTROL);
1585 if (dpfc_ctl & DPFC_CTL_EN) {
1586 dpfc_ctl &= ~DPFC_CTL_EN;
1587 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1589 DRM_DEBUG_KMS("disabled FBC\n");
1593 static bool g4x_fbc_enabled(struct drm_device *dev)
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1597 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1600 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1605 /* Make sure blitter notifies FBC of writes */
1606 gen6_gt_force_wake_get(dev_priv);
1607 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609 GEN6_BLITTER_LOCK_SHIFT;
1610 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614 GEN6_BLITTER_LOCK_SHIFT);
1615 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1617 gen6_gt_force_wake_put(dev_priv);
1620 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_framebuffer *fb = crtc->fb;
1625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1626 struct drm_i915_gem_object *obj = intel_fb->obj;
1627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1629 unsigned long stall_watermark = 200;
1632 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1633 dpfc_ctl &= DPFC_RESERVED;
1634 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1635 /* Set persistent mode for front-buffer rendering, ala X. */
1636 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1637 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1638 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1640 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1644 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1646 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1649 I915_WRITE(SNB_DPFC_CTL_SA,
1650 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1651 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1652 sandybridge_blit_fbc_update(dev);
1655 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1658 static void ironlake_disable_fbc(struct drm_device *dev)
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1663 /* Disable compression */
1664 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1665 if (dpfc_ctl & DPFC_CTL_EN) {
1666 dpfc_ctl &= ~DPFC_CTL_EN;
1667 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1669 DRM_DEBUG_KMS("disabled FBC\n");
1673 static bool ironlake_fbc_enabled(struct drm_device *dev)
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1677 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1680 bool intel_fbc_enabled(struct drm_device *dev)
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1684 if (!dev_priv->display.fbc_enabled)
1687 return dev_priv->display.fbc_enabled(dev);
1690 static void intel_fbc_work_fn(struct work_struct *__work)
1692 struct intel_fbc_work *work =
1693 container_of(to_delayed_work(__work),
1694 struct intel_fbc_work, work);
1695 struct drm_device *dev = work->crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1698 mutex_lock(&dev->struct_mutex);
1699 if (work == dev_priv->fbc_work) {
1700 /* Double check that we haven't switched fb without cancelling
1703 if (work->crtc->fb == work->fb) {
1704 dev_priv->display.enable_fbc(work->crtc,
1707 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708 dev_priv->cfb_fb = work->crtc->fb->base.id;
1709 dev_priv->cfb_y = work->crtc->y;
1712 dev_priv->fbc_work = NULL;
1714 mutex_unlock(&dev->struct_mutex);
1719 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1721 if (dev_priv->fbc_work == NULL)
1724 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1726 /* Synchronisation is provided by struct_mutex and checking of
1727 * dev_priv->fbc_work, so we can perform the cancellation
1728 * entirely asynchronously.
1730 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731 /* tasklet was killed before being run, clean up */
1732 kfree(dev_priv->fbc_work);
1734 /* Mark the work as no longer wanted so that if it does
1735 * wake-up (because the work was already running and waiting
1736 * for our mutex), it will discover that is no longer
1739 dev_priv->fbc_work = NULL;
1742 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1744 struct intel_fbc_work *work;
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1748 if (!dev_priv->display.enable_fbc)
1751 intel_cancel_fbc_work(dev_priv);
1753 work = kzalloc(sizeof *work, GFP_KERNEL);
1755 dev_priv->display.enable_fbc(crtc, interval);
1760 work->fb = crtc->fb;
1761 work->interval = interval;
1762 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1764 dev_priv->fbc_work = work;
1766 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1768 /* Delay the actual enabling to let pageflipping cease and the
1769 * display to settle before starting the compression. Note that
1770 * this delay also serves a second purpose: it allows for a
1771 * vblank to pass after disabling the FBC before we attempt
1772 * to modify the control registers.
1774 * A more complicated solution would involve tracking vblanks
1775 * following the termination of the page-flipping sequence
1776 * and indeed performing the enable as a co-routine and not
1777 * waiting synchronously upon the vblank.
1779 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1782 void intel_disable_fbc(struct drm_device *dev)
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1786 intel_cancel_fbc_work(dev_priv);
1788 if (!dev_priv->display.disable_fbc)
1791 dev_priv->display.disable_fbc(dev);
1792 dev_priv->cfb_plane = -1;
1796 * intel_update_fbc - enable/disable FBC as needed
1797 * @dev: the drm_device
1799 * Set up the framebuffer compression hardware at mode set time. We
1800 * enable it if possible:
1801 * - plane A only (on pre-965)
1802 * - no pixel mulitply/line duplication
1803 * - no alpha buffer discard
1805 * - framebuffer <= 2048 in width, 1536 in height
1807 * We can't assume that any compression will take place (worst case),
1808 * so the compressed buffer has to be the same size as the uncompressed
1809 * one. It also must reside (along with the line length buffer) in
1812 * We need to enable/disable FBC on a global basis.
1814 static void intel_update_fbc(struct drm_device *dev)
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 struct drm_crtc *crtc = NULL, *tmp_crtc;
1818 struct intel_crtc *intel_crtc;
1819 struct drm_framebuffer *fb;
1820 struct intel_framebuffer *intel_fb;
1821 struct drm_i915_gem_object *obj;
1824 DRM_DEBUG_KMS("\n");
1826 if (!i915_powersave)
1829 if (!I915_HAS_FBC(dev))
1833 * If FBC is already on, we just have to verify that we can
1834 * keep it that way...
1835 * Need to disable if:
1836 * - more than one pipe is active
1837 * - changing FBC params (stride, fence, mode)
1838 * - new fb is too large to fit in compressed buffer
1839 * - going to an unsupported config (interlace, pixel multiply, etc.)
1841 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1842 if (tmp_crtc->enabled && tmp_crtc->fb) {
1844 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1852 if (!crtc || crtc->fb == NULL) {
1853 DRM_DEBUG_KMS("no output, disabling\n");
1854 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1858 intel_crtc = to_intel_crtc(crtc);
1860 intel_fb = to_intel_framebuffer(fb);
1861 obj = intel_fb->obj;
1863 enable_fbc = i915_enable_fbc;
1864 if (enable_fbc < 0) {
1865 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1867 if (INTEL_INFO(dev)->gen <= 6)
1871 DRM_DEBUG_KMS("fbc disabled per module param\n");
1872 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1875 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1876 DRM_DEBUG_KMS("framebuffer too large, disabling "
1878 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1881 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1883 DRM_DEBUG_KMS("mode incompatible with compression, "
1885 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1888 if ((crtc->mode.hdisplay > 2048) ||
1889 (crtc->mode.vdisplay > 1536)) {
1890 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1894 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1895 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1896 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1900 /* The use of a CPU fence is mandatory in order to detect writes
1901 * by the CPU to the scanout and trigger updates to the FBC.
1903 if (obj->tiling_mode != I915_TILING_X ||
1904 obj->fence_reg == I915_FENCE_REG_NONE) {
1905 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1906 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1910 /* If the kernel debugger is active, always disable compression */
1911 if (in_dbg_master())
1914 /* If the scanout has not changed, don't modify the FBC settings.
1915 * Note that we make the fundamental assumption that the fb->obj
1916 * cannot be unpinned (and have its GTT offset and fence revoked)
1917 * without first being decoupled from the scanout and FBC disabled.
1919 if (dev_priv->cfb_plane == intel_crtc->plane &&
1920 dev_priv->cfb_fb == fb->base.id &&
1921 dev_priv->cfb_y == crtc->y)
1924 if (intel_fbc_enabled(dev)) {
1925 /* We update FBC along two paths, after changing fb/crtc
1926 * configuration (modeswitching) and after page-flipping
1927 * finishes. For the latter, we know that not only did
1928 * we disable the FBC at the start of the page-flip
1929 * sequence, but also more than one vblank has passed.
1931 * For the former case of modeswitching, it is possible
1932 * to switch between two FBC valid configurations
1933 * instantaneously so we do need to disable the FBC
1934 * before we can modify its control registers. We also
1935 * have to wait for the next vblank for that to take
1936 * effect. However, since we delay enabling FBC we can
1937 * assume that a vblank has passed since disabling and
1938 * that we can safely alter the registers in the deferred
1941 * In the scenario that we go from a valid to invalid
1942 * and then back to valid FBC configuration we have
1943 * no strict enforcement that a vblank occurred since
1944 * disabling the FBC. However, along all current pipe
1945 * disabling paths we do need to wait for a vblank at
1946 * some point. And we wait before enabling FBC anyway.
1948 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949 intel_disable_fbc(dev);
1952 intel_enable_fbc(crtc, 500);
1956 /* Multiple disables should be harmless */
1957 if (intel_fbc_enabled(dev)) {
1958 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1959 intel_disable_fbc(dev);
1964 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1965 struct drm_i915_gem_object *obj,
1966 struct intel_ring_buffer *pipelined)
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1972 switch (obj->tiling_mode) {
1973 case I915_TILING_NONE:
1974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
1976 else if (INTEL_INFO(dev)->gen >= 4)
1977 alignment = 4 * 1024;
1979 alignment = 64 * 1024;
1982 /* pin() will align the object as required by fence */
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1993 dev_priv->mm.interruptible = false;
1994 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1996 goto err_interruptible;
1998 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999 * fence, whereas 965+ only requires a fence if using
2000 * framebuffer compression. For simplicity, we always install
2001 * a fence as the cost is not that onerous.
2003 if (obj->tiling_mode != I915_TILING_NONE) {
2004 ret = i915_gem_object_get_fence(obj, pipelined);
2009 dev_priv->mm.interruptible = true;
2013 i915_gem_object_unpin(obj);
2015 dev_priv->mm.interruptible = true;
2019 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2022 struct drm_device *dev = crtc->dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025 struct intel_framebuffer *intel_fb;
2026 struct drm_i915_gem_object *obj;
2027 int plane = intel_crtc->plane;
2028 unsigned long Start, Offset;
2037 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->bits_per_pixel) {
2050 dspcntr |= DISPPLANE_8BPP;
2053 if (fb->depth == 15)
2054 dspcntr |= DISPPLANE_15_16BPP;
2056 dspcntr |= DISPPLANE_16BPP;
2060 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2063 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2066 if (INTEL_INFO(dev)->gen >= 4) {
2067 if (obj->tiling_mode != I915_TILING_NONE)
2068 dspcntr |= DISPPLANE_TILED;
2070 dspcntr &= ~DISPPLANE_TILED;
2073 I915_WRITE(reg, dspcntr);
2075 Start = obj->gtt_offset;
2076 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 Start, Offset, x, y, fb->pitch);
2080 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2081 if (INTEL_INFO(dev)->gen >= 4) {
2082 I915_WRITE(DSPSURF(plane), Start);
2083 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084 I915_WRITE(DSPADDR(plane), Offset);
2086 I915_WRITE(DSPADDR(plane), Start + Offset);
2092 static int ironlake_update_plane(struct drm_crtc *crtc,
2093 struct drm_framebuffer *fb, int x, int y)
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098 struct intel_framebuffer *intel_fb;
2099 struct drm_i915_gem_object *obj;
2100 int plane = intel_crtc->plane;
2101 unsigned long Start, Offset;
2111 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2115 intel_fb = to_intel_framebuffer(fb);
2116 obj = intel_fb->obj;
2118 reg = DSPCNTR(plane);
2119 dspcntr = I915_READ(reg);
2120 /* Mask out pixel format bits in case we change it */
2121 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122 switch (fb->bits_per_pixel) {
2124 dspcntr |= DISPPLANE_8BPP;
2127 if (fb->depth != 16)
2130 dspcntr |= DISPPLANE_16BPP;
2134 if (fb->depth == 24)
2135 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136 else if (fb->depth == 30)
2137 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2142 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2146 if (obj->tiling_mode != I915_TILING_NONE)
2147 dspcntr |= DISPPLANE_TILED;
2149 dspcntr &= ~DISPPLANE_TILED;
2152 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2154 I915_WRITE(reg, dspcntr);
2156 Start = obj->gtt_offset;
2157 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 Start, Offset, x, y, fb->pitch);
2161 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2170 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2172 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173 int x, int y, enum mode_set_atomic state)
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2179 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2183 intel_update_fbc(dev);
2184 intel_increase_pllclock(crtc);
2190 intel_finish_fb(struct drm_framebuffer *old_fb)
2192 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194 bool was_interruptible = dev_priv->mm.interruptible;
2197 wait_event(dev_priv->pending_flip_queue,
2198 atomic_read(&dev_priv->mm.wedged) ||
2199 atomic_read(&obj->pending_flip) == 0);
2201 /* Big Hammer, we also need to ensure that any pending
2202 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2203 * current scanout is retired before unpinning the old
2206 * This should only fail upon a hung GPU, in which case we
2207 * can safely continue.
2209 dev_priv->mm.interruptible = false;
2210 ret = i915_gem_object_finish_gpu(obj);
2211 dev_priv->mm.interruptible = was_interruptible;
2217 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2218 struct drm_framebuffer *old_fb)
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_master_private *master_priv;
2222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2227 DRM_ERROR("No FB bound\n");
2231 switch (intel_crtc->plane) {
2236 if (IS_IVYBRIDGE(dev))
2238 /* fall through otherwise */
2240 DRM_ERROR("no plane for crtc\n");
2244 mutex_lock(&dev->struct_mutex);
2245 ret = intel_pin_and_fence_fb_obj(dev,
2246 to_intel_framebuffer(crtc->fb)->obj,
2249 mutex_unlock(&dev->struct_mutex);
2250 DRM_ERROR("pin & fence failed\n");
2255 intel_finish_fb(old_fb);
2257 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2258 LEAVE_ATOMIC_MODE_SET);
2260 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2261 mutex_unlock(&dev->struct_mutex);
2262 DRM_ERROR("failed to update base address\n");
2267 intel_wait_for_vblank(dev, intel_crtc->pipe);
2268 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2271 mutex_unlock(&dev->struct_mutex);
2273 if (!dev->primary->master)
2276 master_priv = dev->primary->master->driver_priv;
2277 if (!master_priv->sarea_priv)
2280 if (intel_crtc->pipe) {
2281 master_priv->sarea_priv->pipeB_x = x;
2282 master_priv->sarea_priv->pipeB_y = y;
2284 master_priv->sarea_priv->pipeA_x = x;
2285 master_priv->sarea_priv->pipeA_y = y;
2291 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2293 struct drm_device *dev = crtc->dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2297 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2298 dpa_ctl = I915_READ(DP_A);
2299 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2301 if (clock < 200000) {
2303 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2304 /* workaround for 160Mhz:
2305 1) program 0x4600c bits 15:0 = 0x8124
2306 2) program 0x46010 bit 0 = 1
2307 3) program 0x46034 bit 24 = 1
2308 4) program 0x64000 bit 14 = 1
2310 temp = I915_READ(0x4600c);
2312 I915_WRITE(0x4600c, temp | 0x8124);
2314 temp = I915_READ(0x46010);
2315 I915_WRITE(0x46010, temp | 1);
2317 temp = I915_READ(0x46034);
2318 I915_WRITE(0x46034, temp | (1 << 24));
2320 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2322 I915_WRITE(DP_A, dpa_ctl);
2328 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2330 struct drm_device *dev = crtc->dev;
2331 struct drm_i915_private *dev_priv = dev->dev_private;
2332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333 int pipe = intel_crtc->pipe;
2336 /* enable normal train */
2337 reg = FDI_TX_CTL(pipe);
2338 temp = I915_READ(reg);
2339 if (IS_IVYBRIDGE(dev)) {
2340 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2341 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2343 temp &= ~FDI_LINK_TRAIN_NONE;
2344 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2346 I915_WRITE(reg, temp);
2348 reg = FDI_RX_CTL(pipe);
2349 temp = I915_READ(reg);
2350 if (HAS_PCH_CPT(dev)) {
2351 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2352 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2354 temp &= ~FDI_LINK_TRAIN_NONE;
2355 temp |= FDI_LINK_TRAIN_NONE;
2357 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2359 /* wait one idle pattern time */
2363 /* IVB wants error correction enabled */
2364 if (IS_IVYBRIDGE(dev))
2365 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2366 FDI_FE_ERRC_ENABLE);
2369 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372 u32 flags = I915_READ(SOUTH_CHICKEN1);
2374 flags |= FDI_PHASE_SYNC_OVR(pipe);
2375 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2376 flags |= FDI_PHASE_SYNC_EN(pipe);
2377 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2378 POSTING_READ(SOUTH_CHICKEN1);
2381 /* The FDI link training functions for ILK/Ibexpeak. */
2382 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2384 struct drm_device *dev = crtc->dev;
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2387 int pipe = intel_crtc->pipe;
2388 int plane = intel_crtc->plane;
2389 u32 reg, temp, tries;
2391 /* FDI needs bits from pipe & plane first */
2392 assert_pipe_enabled(dev_priv, pipe);
2393 assert_plane_enabled(dev_priv, plane);
2395 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 reg = FDI_RX_IMR(pipe);
2398 temp = I915_READ(reg);
2399 temp &= ~FDI_RX_SYMBOL_LOCK;
2400 temp &= ~FDI_RX_BIT_LOCK;
2401 I915_WRITE(reg, temp);
2405 /* enable CPU FDI TX and PCH FDI RX */
2406 reg = FDI_TX_CTL(pipe);
2407 temp = I915_READ(reg);
2409 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2410 temp &= ~FDI_LINK_TRAIN_NONE;
2411 temp |= FDI_LINK_TRAIN_PATTERN_1;
2412 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2414 reg = FDI_RX_CTL(pipe);
2415 temp = I915_READ(reg);
2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_PATTERN_1;
2418 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2423 /* Ironlake workaround, enable clock pointer after FDI enable*/
2424 if (HAS_PCH_IBX(dev)) {
2425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427 FDI_RX_PHASE_SYNC_POINTER_EN);
2430 reg = FDI_RX_IIR(pipe);
2431 for (tries = 0; tries < 5; tries++) {
2432 temp = I915_READ(reg);
2433 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2435 if ((temp & FDI_RX_BIT_LOCK)) {
2436 DRM_DEBUG_KMS("FDI train 1 done.\n");
2437 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2442 DRM_ERROR("FDI train 1 fail!\n");
2445 reg = FDI_TX_CTL(pipe);
2446 temp = I915_READ(reg);
2447 temp &= ~FDI_LINK_TRAIN_NONE;
2448 temp |= FDI_LINK_TRAIN_PATTERN_2;
2449 I915_WRITE(reg, temp);
2451 reg = FDI_RX_CTL(pipe);
2452 temp = I915_READ(reg);
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_PATTERN_2;
2455 I915_WRITE(reg, temp);
2460 reg = FDI_RX_IIR(pipe);
2461 for (tries = 0; tries < 5; tries++) {
2462 temp = I915_READ(reg);
2463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2465 if (temp & FDI_RX_SYMBOL_LOCK) {
2466 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467 DRM_DEBUG_KMS("FDI train 2 done.\n");
2472 DRM_ERROR("FDI train 2 fail!\n");
2474 DRM_DEBUG_KMS("FDI train done\n");
2478 static const int snb_b_fdi_train_param[] = {
2479 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2480 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2481 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2482 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2485 /* The FDI link training functions for SNB/Cougarpoint. */
2486 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2488 struct drm_device *dev = crtc->dev;
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2491 int pipe = intel_crtc->pipe;
2494 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2496 reg = FDI_RX_IMR(pipe);
2497 temp = I915_READ(reg);
2498 temp &= ~FDI_RX_SYMBOL_LOCK;
2499 temp &= ~FDI_RX_BIT_LOCK;
2500 I915_WRITE(reg, temp);
2505 /* enable CPU FDI TX and PCH FDI RX */
2506 reg = FDI_TX_CTL(pipe);
2507 temp = I915_READ(reg);
2509 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2510 temp &= ~FDI_LINK_TRAIN_NONE;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1;
2512 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2515 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2517 reg = FDI_RX_CTL(pipe);
2518 temp = I915_READ(reg);
2519 if (HAS_PCH_CPT(dev)) {
2520 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531 if (HAS_PCH_CPT(dev))
2532 cpt_phase_pointer_enable(dev, pipe);
2534 for (i = 0; i < 4; i++) {
2535 reg = FDI_TX_CTL(pipe);
2536 temp = I915_READ(reg);
2537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538 temp |= snb_b_fdi_train_param[i];
2539 I915_WRITE(reg, temp);
2544 reg = FDI_RX_IIR(pipe);
2545 temp = I915_READ(reg);
2546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2548 if (temp & FDI_RX_BIT_LOCK) {
2549 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2550 DRM_DEBUG_KMS("FDI train 1 done.\n");
2555 DRM_ERROR("FDI train 1 fail!\n");
2558 reg = FDI_TX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2563 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2567 I915_WRITE(reg, temp);
2569 reg = FDI_RX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 if (HAS_PCH_CPT(dev)) {
2572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578 I915_WRITE(reg, temp);
2583 for (i = 0; i < 4; i++) {
2584 reg = FDI_TX_CTL(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 temp |= snb_b_fdi_train_param[i];
2588 I915_WRITE(reg, temp);
2593 reg = FDI_RX_IIR(pipe);
2594 temp = I915_READ(reg);
2595 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2597 if (temp & FDI_RX_SYMBOL_LOCK) {
2598 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2599 DRM_DEBUG_KMS("FDI train 2 done.\n");
2604 DRM_ERROR("FDI train 2 fail!\n");
2606 DRM_DEBUG_KMS("FDI train done.\n");
2609 /* Manual link training for Ivy Bridge A0 parts */
2610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2612 struct drm_device *dev = crtc->dev;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615 int pipe = intel_crtc->pipe;
2618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2620 reg = FDI_RX_IMR(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_RX_SYMBOL_LOCK;
2623 temp &= ~FDI_RX_BIT_LOCK;
2624 I915_WRITE(reg, temp);
2629 /* enable CPU FDI TX and PCH FDI RX */
2630 reg = FDI_TX_CTL(pipe);
2631 temp = I915_READ(reg);
2633 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2634 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2636 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2638 temp |= FDI_COMPOSITE_SYNC;
2639 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2641 reg = FDI_RX_CTL(pipe);
2642 temp = I915_READ(reg);
2643 temp &= ~FDI_LINK_TRAIN_AUTO;
2644 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2646 temp |= FDI_COMPOSITE_SYNC;
2647 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2652 if (HAS_PCH_CPT(dev))
2653 cpt_phase_pointer_enable(dev, pipe);
2655 for (i = 0; i < 4; i++) {
2656 reg = FDI_TX_CTL(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2659 temp |= snb_b_fdi_train_param[i];
2660 I915_WRITE(reg, temp);
2665 reg = FDI_RX_IIR(pipe);
2666 temp = I915_READ(reg);
2667 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2669 if (temp & FDI_RX_BIT_LOCK ||
2670 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2671 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2672 DRM_DEBUG_KMS("FDI train 1 done.\n");
2677 DRM_ERROR("FDI train 1 fail!\n");
2680 reg = FDI_TX_CTL(pipe);
2681 temp = I915_READ(reg);
2682 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2683 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2684 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2686 I915_WRITE(reg, temp);
2688 reg = FDI_RX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2691 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2692 I915_WRITE(reg, temp);
2697 for (i = 0; i < 4; i++) {
2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
2702 I915_WRITE(reg, temp);
2707 reg = FDI_RX_IIR(pipe);
2708 temp = I915_READ(reg);
2709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711 if (temp & FDI_RX_SYMBOL_LOCK) {
2712 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713 DRM_DEBUG_KMS("FDI train 2 done.\n");
2718 DRM_ERROR("FDI train 2 fail!\n");
2720 DRM_DEBUG_KMS("FDI train done.\n");
2723 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2725 struct drm_device *dev = crtc->dev;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728 int pipe = intel_crtc->pipe;
2731 /* Write the TU size bits so error detection works */
2732 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2733 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2735 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2736 reg = FDI_RX_CTL(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~((0x7 << 19) | (0x7 << 16));
2739 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2740 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2741 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2746 /* Switch from Rawclk to PCDclk */
2747 temp = I915_READ(reg);
2748 I915_WRITE(reg, temp | FDI_PCDCLK);
2753 /* Enable CPU FDI TX PLL, always on for Ironlake */
2754 reg = FDI_TX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2757 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2764 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 u32 flags = I915_READ(SOUTH_CHICKEN1);
2769 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2770 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2771 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2772 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2773 POSTING_READ(SOUTH_CHICKEN1);
2775 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2777 struct drm_device *dev = crtc->dev;
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780 int pipe = intel_crtc->pipe;
2783 /* disable CPU FDI tx and PCH FDI rx */
2784 reg = FDI_TX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~(0x7 << 16);
2792 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2793 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2798 /* Ironlake workaround, disable clock pointer after downing FDI */
2799 if (HAS_PCH_IBX(dev)) {
2800 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2801 I915_WRITE(FDI_RX_CHICKEN(pipe),
2802 I915_READ(FDI_RX_CHICKEN(pipe) &
2803 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2804 } else if (HAS_PCH_CPT(dev)) {
2805 cpt_phase_pointer_disable(dev, pipe);
2808 /* still set train pattern 1 */
2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 I915_WRITE(reg, temp);
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 if (HAS_PCH_CPT(dev)) {
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2821 temp &= ~FDI_LINK_TRAIN_NONE;
2822 temp |= FDI_LINK_TRAIN_PATTERN_1;
2824 /* BPC in FDI rx is consistent with that in PIPECONF */
2825 temp &= ~(0x07 << 16);
2826 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2827 I915_WRITE(reg, temp);
2834 * When we disable a pipe, we need to clear any pending scanline wait events
2835 * to avoid hanging the ring, which we assume we are waiting on.
2837 static void intel_clear_scanline_wait(struct drm_device *dev)
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_ring_buffer *ring;
2844 /* Can't break the hang on i8xx */
2847 ring = LP_RING(dev_priv);
2848 tmp = I915_READ_CTL(ring);
2849 if (tmp & RING_WAIT)
2850 I915_WRITE_CTL(ring, tmp);
2853 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 struct drm_device *dev = crtc->dev;
2857 if (crtc->fb == NULL)
2860 mutex_lock(&dev->struct_mutex);
2861 intel_finish_fb(crtc->fb);
2862 mutex_unlock(&dev->struct_mutex);
2865 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_mode_config *mode_config = &dev->mode_config;
2869 struct intel_encoder *encoder;
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2875 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2876 if (encoder->base.crtc != crtc)
2879 switch (encoder->type) {
2880 case INTEL_OUTPUT_EDP:
2881 if (!intel_encoder_is_pch_edp(&encoder->base))
2891 * Enable PCH resources required for PCH ports:
2893 * - FDI training & RX/TX
2894 * - update transcoder timings
2895 * - DP transcoding bits
2898 static void ironlake_pch_enable(struct drm_crtc *crtc)
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
2904 u32 reg, temp, transc_sel;
2906 /* For PCH output, training FDI link */
2907 dev_priv->display.fdi_link_train(crtc);
2909 intel_enable_pch_pll(dev_priv, pipe);
2911 if (HAS_PCH_CPT(dev)) {
2912 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2915 /* Be sure PCH DPLL SEL is set */
2916 temp = I915_READ(PCH_DPLL_SEL);
2918 temp &= ~(TRANSA_DPLLB_SEL);
2919 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2920 } else if (pipe == 1) {
2921 temp &= ~(TRANSB_DPLLB_SEL);
2922 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2923 } else if (pipe == 2) {
2924 temp &= ~(TRANSC_DPLLB_SEL);
2925 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2927 I915_WRITE(PCH_DPLL_SEL, temp);
2930 /* set transcoder timing, panel must allow it */
2931 assert_panel_unlocked(dev_priv, pipe);
2932 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2933 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2934 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2936 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2937 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2938 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2940 intel_fdi_normal_train(crtc);
2942 /* For PCH DP, enable TRANS_DP_CTL */
2943 if (HAS_PCH_CPT(dev) &&
2944 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2945 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2946 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2947 reg = TRANS_DP_CTL(pipe);
2948 temp = I915_READ(reg);
2949 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2950 TRANS_DP_SYNC_MASK |
2952 temp |= (TRANS_DP_OUTPUT_ENABLE |
2953 TRANS_DP_ENH_FRAMING);
2954 temp |= bpc << 9; /* same format but at 11:9 */
2956 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2957 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2958 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2959 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2961 switch (intel_trans_dp_port_sel(crtc)) {
2963 temp |= TRANS_DP_PORT_SEL_B;
2966 temp |= TRANS_DP_PORT_SEL_C;
2969 temp |= TRANS_DP_PORT_SEL_D;
2972 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2973 temp |= TRANS_DP_PORT_SEL_B;
2977 I915_WRITE(reg, temp);
2980 intel_enable_transcoder(dev_priv, pipe);
2983 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2989 temp = I915_READ(dslreg);
2991 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2992 /* Without this, mode sets may fail silently on FDI */
2993 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2995 I915_WRITE(tc2reg, 0);
2996 if (wait_for(I915_READ(dslreg) != temp, 5))
2997 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3001 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006 int pipe = intel_crtc->pipe;
3007 int plane = intel_crtc->plane;
3011 if (intel_crtc->active)
3014 intel_crtc->active = true;
3015 intel_update_watermarks(dev);
3017 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3018 temp = I915_READ(PCH_LVDS);
3019 if ((temp & LVDS_PORT_EN) == 0)
3020 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3023 is_pch_port = intel_crtc_driving_pch(crtc);
3026 ironlake_fdi_pll_enable(crtc);
3028 ironlake_fdi_disable(crtc);
3030 /* Enable panel fitting for LVDS */
3031 if (dev_priv->pch_pf_size &&
3032 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3033 /* Force use of hard-coded filter coefficients
3034 * as some pre-programmed values are broken,
3037 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3038 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3039 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3043 * On ILK+ LUT must be loaded before the pipe is running but with
3046 intel_crtc_load_lut(crtc);
3048 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3049 intel_enable_plane(dev_priv, plane, pipe);
3052 ironlake_pch_enable(crtc);
3054 mutex_lock(&dev->struct_mutex);
3055 intel_update_fbc(dev);
3056 mutex_unlock(&dev->struct_mutex);
3058 intel_crtc_update_cursor(crtc, true);
3061 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3063 struct drm_device *dev = crtc->dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066 int pipe = intel_crtc->pipe;
3067 int plane = intel_crtc->plane;
3070 if (!intel_crtc->active)
3073 intel_crtc_wait_for_pending_flips(crtc);
3074 drm_vblank_off(dev, pipe);
3075 intel_crtc_update_cursor(crtc, false);
3077 intel_disable_plane(dev_priv, plane, pipe);
3079 if (dev_priv->cfb_plane == plane)
3080 intel_disable_fbc(dev);
3082 intel_disable_pipe(dev_priv, pipe);
3085 I915_WRITE(PF_CTL(pipe), 0);
3086 I915_WRITE(PF_WIN_SZ(pipe), 0);
3088 ironlake_fdi_disable(crtc);
3090 /* This is a horrible layering violation; we should be doing this in
3091 * the connector/encoder ->prepare instead, but we don't always have
3092 * enough information there about the config to know whether it will
3093 * actually be necessary or just cause undesired flicker.
3095 intel_disable_pch_ports(dev_priv, pipe);
3097 intel_disable_transcoder(dev_priv, pipe);
3099 if (HAS_PCH_CPT(dev)) {
3100 /* disable TRANS_DP_CTL */
3101 reg = TRANS_DP_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3104 temp |= TRANS_DP_PORT_SEL_NONE;
3105 I915_WRITE(reg, temp);
3107 /* disable DPLL_SEL */
3108 temp = I915_READ(PCH_DPLL_SEL);
3111 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3114 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3117 /* C shares PLL A or B */
3118 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3123 I915_WRITE(PCH_DPLL_SEL, temp);
3126 /* disable PCH DPLL */
3127 if (!intel_crtc->no_pll)
3128 intel_disable_pch_pll(dev_priv, pipe);
3130 /* Switch from PCDclk to Rawclk */
3131 reg = FDI_RX_CTL(pipe);
3132 temp = I915_READ(reg);
3133 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3135 /* Disable CPU FDI TX PLL */
3136 reg = FDI_TX_CTL(pipe);
3137 temp = I915_READ(reg);
3138 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3143 reg = FDI_RX_CTL(pipe);
3144 temp = I915_READ(reg);
3145 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3147 /* Wait for the clocks to turn off. */
3151 intel_crtc->active = false;
3152 intel_update_watermarks(dev);
3154 mutex_lock(&dev->struct_mutex);
3155 intel_update_fbc(dev);
3156 intel_clear_scanline_wait(dev);
3157 mutex_unlock(&dev->struct_mutex);
3160 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163 int pipe = intel_crtc->pipe;
3164 int plane = intel_crtc->plane;
3166 /* XXX: When our outputs are all unaware of DPMS modes other than off
3167 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3170 case DRM_MODE_DPMS_ON:
3171 case DRM_MODE_DPMS_STANDBY:
3172 case DRM_MODE_DPMS_SUSPEND:
3173 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3174 ironlake_crtc_enable(crtc);
3177 case DRM_MODE_DPMS_OFF:
3178 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3179 ironlake_crtc_disable(crtc);
3184 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3186 if (!enable && intel_crtc->overlay) {
3187 struct drm_device *dev = intel_crtc->base.dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3190 mutex_lock(&dev->struct_mutex);
3191 dev_priv->mm.interruptible = false;
3192 (void) intel_overlay_switch_off(intel_crtc->overlay);
3193 dev_priv->mm.interruptible = true;
3194 mutex_unlock(&dev->struct_mutex);
3197 /* Let userspace switch the overlay on again. In most cases userspace
3198 * has to recompute where to put it anyway.
3202 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3204 struct drm_device *dev = crtc->dev;
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207 int pipe = intel_crtc->pipe;
3208 int plane = intel_crtc->plane;
3210 if (intel_crtc->active)
3213 intel_crtc->active = true;
3214 intel_update_watermarks(dev);
3216 intel_enable_pll(dev_priv, pipe);
3217 intel_enable_pipe(dev_priv, pipe, false);
3218 intel_enable_plane(dev_priv, plane, pipe);
3220 intel_crtc_load_lut(crtc);
3221 intel_update_fbc(dev);
3223 /* Give the overlay scaler a chance to enable if it's on this pipe */
3224 intel_crtc_dpms_overlay(intel_crtc, true);
3225 intel_crtc_update_cursor(crtc, true);
3228 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3230 struct drm_device *dev = crtc->dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3233 int pipe = intel_crtc->pipe;
3234 int plane = intel_crtc->plane;
3236 if (!intel_crtc->active)
3239 /* Give the overlay scaler a chance to disable if it's on this pipe */
3240 intel_crtc_wait_for_pending_flips(crtc);
3241 drm_vblank_off(dev, pipe);
3242 intel_crtc_dpms_overlay(intel_crtc, false);
3243 intel_crtc_update_cursor(crtc, false);
3245 if (dev_priv->cfb_plane == plane)
3246 intel_disable_fbc(dev);
3248 intel_disable_plane(dev_priv, plane, pipe);
3249 intel_disable_pipe(dev_priv, pipe);
3250 intel_disable_pll(dev_priv, pipe);
3252 intel_crtc->active = false;
3253 intel_update_fbc(dev);
3254 intel_update_watermarks(dev);
3255 intel_clear_scanline_wait(dev);
3258 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3260 /* XXX: When our outputs are all unaware of DPMS modes other than off
3261 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3264 case DRM_MODE_DPMS_ON:
3265 case DRM_MODE_DPMS_STANDBY:
3266 case DRM_MODE_DPMS_SUSPEND:
3267 i9xx_crtc_enable(crtc);
3269 case DRM_MODE_DPMS_OFF:
3270 i9xx_crtc_disable(crtc);
3276 * Sets the power management mode of the pipe and plane.
3278 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3280 struct drm_device *dev = crtc->dev;
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 struct drm_i915_master_private *master_priv;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
3287 if (intel_crtc->dpms_mode == mode)
3290 intel_crtc->dpms_mode = mode;
3292 dev_priv->display.dpms(crtc, mode);
3294 if (!dev->primary->master)
3297 master_priv = dev->primary->master->driver_priv;
3298 if (!master_priv->sarea_priv)
3301 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3305 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3306 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3309 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3310 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3313 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3318 static void intel_crtc_disable(struct drm_crtc *crtc)
3320 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3321 struct drm_device *dev = crtc->dev;
3323 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3326 mutex_lock(&dev->struct_mutex);
3327 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3328 mutex_unlock(&dev->struct_mutex);
3332 /* Prepare for a mode set.
3334 * Note we could be a lot smarter here. We need to figure out which outputs
3335 * will be enabled, which disabled (in short, how the config will changes)
3336 * and perform the minimum necessary steps to accomplish that, e.g. updating
3337 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3338 * panel fitting is in the proper state, etc.
3340 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3342 i9xx_crtc_disable(crtc);
3345 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3347 i9xx_crtc_enable(crtc);
3350 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3352 ironlake_crtc_disable(crtc);
3355 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3357 ironlake_crtc_enable(crtc);
3360 void intel_encoder_prepare(struct drm_encoder *encoder)
3362 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3363 /* lvds has its own version of prepare see intel_lvds_prepare */
3364 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3367 void intel_encoder_commit(struct drm_encoder *encoder)
3369 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3370 struct drm_device *dev = encoder->dev;
3371 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3372 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3374 /* lvds has its own version of commit see intel_lvds_commit */
3375 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3377 if (HAS_PCH_CPT(dev))
3378 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3381 void intel_encoder_destroy(struct drm_encoder *encoder)
3383 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3385 drm_encoder_cleanup(encoder);
3386 kfree(intel_encoder);
3389 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3390 struct drm_display_mode *mode,
3391 struct drm_display_mode *adjusted_mode)
3393 struct drm_device *dev = crtc->dev;
3395 if (HAS_PCH_SPLIT(dev)) {
3396 /* FDI link clock is fixed at 2.7G */
3397 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3401 /* XXX some encoders set the crtcinfo, others don't.
3402 * Obviously we need some form of conflict resolution here...
3404 if (adjusted_mode->crtc_htotal == 0)
3405 drm_mode_set_crtcinfo(adjusted_mode, 0);
3410 static int i945_get_display_clock_speed(struct drm_device *dev)
3415 static int i915_get_display_clock_speed(struct drm_device *dev)
3420 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3425 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3429 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3431 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3434 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3435 case GC_DISPLAY_CLOCK_333_MHZ:
3438 case GC_DISPLAY_CLOCK_190_200_MHZ:
3444 static int i865_get_display_clock_speed(struct drm_device *dev)
3449 static int i855_get_display_clock_speed(struct drm_device *dev)
3452 /* Assume that the hardware is in the high speed state. This
3453 * should be the default.
3455 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3456 case GC_CLOCK_133_200:
3457 case GC_CLOCK_100_200:
3459 case GC_CLOCK_166_250:
3461 case GC_CLOCK_100_133:
3465 /* Shouldn't happen */
3469 static int i830_get_display_clock_speed(struct drm_device *dev)
3483 fdi_reduce_ratio(u32 *num, u32 *den)
3485 while (*num > 0xffffff || *den > 0xffffff) {
3492 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3493 int link_clock, struct fdi_m_n *m_n)
3495 m_n->tu = 64; /* default size */
3497 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3498 m_n->gmch_m = bits_per_pixel * pixel_clock;
3499 m_n->gmch_n = link_clock * nlanes * 8;
3500 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3502 m_n->link_m = pixel_clock;
3503 m_n->link_n = link_clock;
3504 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3508 struct intel_watermark_params {
3509 unsigned long fifo_size;
3510 unsigned long max_wm;
3511 unsigned long default_wm;
3512 unsigned long guard_size;
3513 unsigned long cacheline_size;
3516 /* Pineview has different values for various configs */
3517 static const struct intel_watermark_params pineview_display_wm = {
3518 PINEVIEW_DISPLAY_FIFO,
3522 PINEVIEW_FIFO_LINE_SIZE
3524 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3525 PINEVIEW_DISPLAY_FIFO,
3527 PINEVIEW_DFT_HPLLOFF_WM,
3529 PINEVIEW_FIFO_LINE_SIZE
3531 static const struct intel_watermark_params pineview_cursor_wm = {
3532 PINEVIEW_CURSOR_FIFO,
3533 PINEVIEW_CURSOR_MAX_WM,
3534 PINEVIEW_CURSOR_DFT_WM,
3535 PINEVIEW_CURSOR_GUARD_WM,
3536 PINEVIEW_FIFO_LINE_SIZE,
3538 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3539 PINEVIEW_CURSOR_FIFO,
3540 PINEVIEW_CURSOR_MAX_WM,
3541 PINEVIEW_CURSOR_DFT_WM,
3542 PINEVIEW_CURSOR_GUARD_WM,
3543 PINEVIEW_FIFO_LINE_SIZE
3545 static const struct intel_watermark_params g4x_wm_info = {
3552 static const struct intel_watermark_params g4x_cursor_wm_info = {
3559 static const struct intel_watermark_params i965_cursor_wm_info = {
3564 I915_FIFO_LINE_SIZE,
3566 static const struct intel_watermark_params i945_wm_info = {
3573 static const struct intel_watermark_params i915_wm_info = {
3580 static const struct intel_watermark_params i855_wm_info = {
3587 static const struct intel_watermark_params i830_wm_info = {
3595 static const struct intel_watermark_params ironlake_display_wm_info = {
3602 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3609 static const struct intel_watermark_params ironlake_display_srwm_info = {
3610 ILK_DISPLAY_SR_FIFO,
3611 ILK_DISPLAY_MAX_SRWM,
3612 ILK_DISPLAY_DFT_SRWM,
3616 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3618 ILK_CURSOR_MAX_SRWM,
3619 ILK_CURSOR_DFT_SRWM,
3624 static const struct intel_watermark_params sandybridge_display_wm_info = {
3631 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3638 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3639 SNB_DISPLAY_SR_FIFO,
3640 SNB_DISPLAY_MAX_SRWM,
3641 SNB_DISPLAY_DFT_SRWM,
3645 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3647 SNB_CURSOR_MAX_SRWM,
3648 SNB_CURSOR_DFT_SRWM,
3655 * intel_calculate_wm - calculate watermark level
3656 * @clock_in_khz: pixel clock
3657 * @wm: chip FIFO params
3658 * @pixel_size: display pixel size
3659 * @latency_ns: memory latency for the platform
3661 * Calculate the watermark level (the level at which the display plane will
3662 * start fetching from memory again). Each chip has a different display
3663 * FIFO size and allocation, so the caller needs to figure that out and pass
3664 * in the correct intel_watermark_params structure.
3666 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3667 * on the pixel size. When it reaches the watermark level, it'll start
3668 * fetching FIFO line sized based chunks from memory until the FIFO fills
3669 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3670 * will occur, and a display engine hang could result.
3672 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3673 const struct intel_watermark_params *wm,
3676 unsigned long latency_ns)
3678 long entries_required, wm_size;
3681 * Note: we need to make sure we don't overflow for various clock &
3683 * clocks go from a few thousand to several hundred thousand.
3684 * latency is usually a few thousand
3686 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3688 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3690 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3692 wm_size = fifo_size - (entries_required + wm->guard_size);
3694 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3696 /* Don't promote wm_size to unsigned... */
3697 if (wm_size > (long)wm->max_wm)
3698 wm_size = wm->max_wm;
3700 wm_size = wm->default_wm;
3704 struct cxsr_latency {
3707 unsigned long fsb_freq;
3708 unsigned long mem_freq;
3709 unsigned long display_sr;
3710 unsigned long display_hpll_disable;
3711 unsigned long cursor_sr;
3712 unsigned long cursor_hpll_disable;
3715 static const struct cxsr_latency cxsr_latency_table[] = {
3716 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3717 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3718 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3719 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3720 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3722 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3723 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3724 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3725 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3726 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3728 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3729 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3730 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3731 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3732 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3734 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3735 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3736 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3737 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3738 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3740 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3741 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3742 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3743 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3744 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3746 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3747 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3748 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3749 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3750 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3753 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3758 const struct cxsr_latency *latency;
3761 if (fsb == 0 || mem == 0)
3764 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3765 latency = &cxsr_latency_table[i];
3766 if (is_desktop == latency->is_desktop &&
3767 is_ddr3 == latency->is_ddr3 &&
3768 fsb == latency->fsb_freq && mem == latency->mem_freq)
3772 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3777 static void pineview_disable_cxsr(struct drm_device *dev)
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3781 /* deactivate cxsr */
3782 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3786 * Latency for FIFO fetches is dependent on several factors:
3787 * - memory configuration (speed, channels)
3789 * - current MCH state
3790 * It can be fairly high in some situations, so here we assume a fairly
3791 * pessimal value. It's a tradeoff between extra memory fetches (if we
3792 * set this value too high, the FIFO will fetch frequently to stay full)
3793 * and power consumption (set it too low to save power and we might see
3794 * FIFO underruns and display "flicker").
3796 * A value of 5us seems to be a good balance; safe for very low end
3797 * platforms but not overly aggressive on lower latency configs.
3799 static const int latency_ns = 5000;
3801 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 uint32_t dsparb = I915_READ(DSPARB);
3807 size = dsparb & 0x7f;
3809 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3811 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3812 plane ? "B" : "A", size);
3817 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820 uint32_t dsparb = I915_READ(DSPARB);
3823 size = dsparb & 0x1ff;
3825 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3826 size >>= 1; /* Convert to cachelines */
3828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3829 plane ? "B" : "A", size);
3834 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 uint32_t dsparb = I915_READ(DSPARB);
3840 size = dsparb & 0x7f;
3841 size >>= 2; /* Convert to cachelines */
3843 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3850 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 uint32_t dsparb = I915_READ(DSPARB);
3856 size = dsparb & 0x7f;
3857 size >>= 1; /* Convert to cachelines */
3859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3860 plane ? "B" : "A", size);
3865 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3867 struct drm_crtc *crtc, *enabled = NULL;
3869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3870 if (crtc->enabled && crtc->fb) {
3880 static void pineview_update_wm(struct drm_device *dev)
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 struct drm_crtc *crtc;
3884 const struct cxsr_latency *latency;
3888 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3889 dev_priv->fsb_freq, dev_priv->mem_freq);
3891 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3892 pineview_disable_cxsr(dev);
3896 crtc = single_enabled_crtc(dev);
3898 int clock = crtc->mode.clock;
3899 int pixel_size = crtc->fb->bits_per_pixel / 8;
3902 wm = intel_calculate_wm(clock, &pineview_display_wm,
3903 pineview_display_wm.fifo_size,
3904 pixel_size, latency->display_sr);
3905 reg = I915_READ(DSPFW1);
3906 reg &= ~DSPFW_SR_MASK;
3907 reg |= wm << DSPFW_SR_SHIFT;
3908 I915_WRITE(DSPFW1, reg);
3909 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3912 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3913 pineview_display_wm.fifo_size,
3914 pixel_size, latency->cursor_sr);
3915 reg = I915_READ(DSPFW3);
3916 reg &= ~DSPFW_CURSOR_SR_MASK;
3917 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3918 I915_WRITE(DSPFW3, reg);
3920 /* Display HPLL off SR */
3921 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3922 pineview_display_hplloff_wm.fifo_size,
3923 pixel_size, latency->display_hpll_disable);
3924 reg = I915_READ(DSPFW3);
3925 reg &= ~DSPFW_HPLL_SR_MASK;
3926 reg |= wm & DSPFW_HPLL_SR_MASK;
3927 I915_WRITE(DSPFW3, reg);
3929 /* cursor HPLL off SR */
3930 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3931 pineview_display_hplloff_wm.fifo_size,
3932 pixel_size, latency->cursor_hpll_disable);
3933 reg = I915_READ(DSPFW3);
3934 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3935 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3936 I915_WRITE(DSPFW3, reg);
3937 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3941 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3942 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3944 pineview_disable_cxsr(dev);
3945 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3949 static bool g4x_compute_wm0(struct drm_device *dev,
3951 const struct intel_watermark_params *display,
3952 int display_latency_ns,
3953 const struct intel_watermark_params *cursor,
3954 int cursor_latency_ns,
3958 struct drm_crtc *crtc;
3959 int htotal, hdisplay, clock, pixel_size;
3960 int line_time_us, line_count;
3961 int entries, tlb_miss;
3963 crtc = intel_get_crtc_for_plane(dev, plane);
3964 if (crtc->fb == NULL || !crtc->enabled) {
3965 *cursor_wm = cursor->guard_size;
3966 *plane_wm = display->guard_size;
3970 htotal = crtc->mode.htotal;
3971 hdisplay = crtc->mode.hdisplay;
3972 clock = crtc->mode.clock;
3973 pixel_size = crtc->fb->bits_per_pixel / 8;
3975 /* Use the small buffer method to calculate plane watermark */
3976 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3977 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3979 entries += tlb_miss;
3980 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3981 *plane_wm = entries + display->guard_size;
3982 if (*plane_wm > (int)display->max_wm)
3983 *plane_wm = display->max_wm;
3985 /* Use the large buffer method to calculate cursor watermark */
3986 line_time_us = ((htotal * 1000) / clock);
3987 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3988 entries = line_count * 64 * pixel_size;
3989 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3991 entries += tlb_miss;
3992 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3993 *cursor_wm = entries + cursor->guard_size;
3994 if (*cursor_wm > (int)cursor->max_wm)
3995 *cursor_wm = (int)cursor->max_wm;
4001 * Check the wm result.
4003 * If any calculated watermark values is larger than the maximum value that
4004 * can be programmed into the associated watermark register, that watermark
4007 static bool g4x_check_srwm(struct drm_device *dev,
4008 int display_wm, int cursor_wm,
4009 const struct intel_watermark_params *display,
4010 const struct intel_watermark_params *cursor)
4012 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4013 display_wm, cursor_wm);
4015 if (display_wm > display->max_wm) {
4016 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4017 display_wm, display->max_wm);
4021 if (cursor_wm > cursor->max_wm) {
4022 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4023 cursor_wm, cursor->max_wm);
4027 if (!(display_wm || cursor_wm)) {
4028 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4035 static bool g4x_compute_srwm(struct drm_device *dev,
4038 const struct intel_watermark_params *display,
4039 const struct intel_watermark_params *cursor,
4040 int *display_wm, int *cursor_wm)
4042 struct drm_crtc *crtc;
4043 int hdisplay, htotal, pixel_size, clock;
4044 unsigned long line_time_us;
4045 int line_count, line_size;
4050 *display_wm = *cursor_wm = 0;
4054 crtc = intel_get_crtc_for_plane(dev, plane);
4055 hdisplay = crtc->mode.hdisplay;
4056 htotal = crtc->mode.htotal;
4057 clock = crtc->mode.clock;
4058 pixel_size = crtc->fb->bits_per_pixel / 8;
4060 line_time_us = (htotal * 1000) / clock;
4061 line_count = (latency_ns / line_time_us + 1000) / 1000;
4062 line_size = hdisplay * pixel_size;
4064 /* Use the minimum of the small and large buffer method for primary */
4065 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066 large = line_count * line_size;
4068 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069 *display_wm = entries + display->guard_size;
4071 /* calculate the self-refresh watermark for display cursor */
4072 entries = line_count * pixel_size * 64;
4073 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4074 *cursor_wm = entries + cursor->guard_size;
4076 return g4x_check_srwm(dev,
4077 *display_wm, *cursor_wm,
4081 #define single_plane_enabled(mask) is_power_of_2(mask)
4083 static void g4x_update_wm(struct drm_device *dev)
4085 static const int sr_latency_ns = 12000;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4088 int plane_sr, cursor_sr;
4089 unsigned int enabled = 0;
4091 if (g4x_compute_wm0(dev, 0,
4092 &g4x_wm_info, latency_ns,
4093 &g4x_cursor_wm_info, latency_ns,
4094 &planea_wm, &cursora_wm))
4097 if (g4x_compute_wm0(dev, 1,
4098 &g4x_wm_info, latency_ns,
4099 &g4x_cursor_wm_info, latency_ns,
4100 &planeb_wm, &cursorb_wm))
4103 plane_sr = cursor_sr = 0;
4104 if (single_plane_enabled(enabled) &&
4105 g4x_compute_srwm(dev, ffs(enabled) - 1,
4108 &g4x_cursor_wm_info,
4109 &plane_sr, &cursor_sr))
4110 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4112 I915_WRITE(FW_BLC_SELF,
4113 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4115 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4116 planea_wm, cursora_wm,
4117 planeb_wm, cursorb_wm,
4118 plane_sr, cursor_sr);
4121 (plane_sr << DSPFW_SR_SHIFT) |
4122 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4123 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4126 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4127 (cursora_wm << DSPFW_CURSORA_SHIFT));
4128 /* HPLL off in SR has some issues on G4x... disable it */
4130 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4131 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4134 static void i965_update_wm(struct drm_device *dev)
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137 struct drm_crtc *crtc;
4141 /* Calc sr entries for one plane configs */
4142 crtc = single_enabled_crtc(dev);
4144 /* self-refresh has much higher latency */
4145 static const int sr_latency_ns = 12000;
4146 int clock = crtc->mode.clock;
4147 int htotal = crtc->mode.htotal;
4148 int hdisplay = crtc->mode.hdisplay;
4149 int pixel_size = crtc->fb->bits_per_pixel / 8;
4150 unsigned long line_time_us;
4153 line_time_us = ((htotal * 1000) / clock);
4155 /* Use ns/us then divide to preserve precision */
4156 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4157 pixel_size * hdisplay;
4158 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4159 srwm = I965_FIFO_SIZE - entries;
4163 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4166 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4168 entries = DIV_ROUND_UP(entries,
4169 i965_cursor_wm_info.cacheline_size);
4170 cursor_sr = i965_cursor_wm_info.fifo_size -
4171 (entries + i965_cursor_wm_info.guard_size);
4173 if (cursor_sr > i965_cursor_wm_info.max_wm)
4174 cursor_sr = i965_cursor_wm_info.max_wm;
4176 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4177 "cursor %d\n", srwm, cursor_sr);
4179 if (IS_CRESTLINE(dev))
4180 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4182 /* Turn off self refresh if both pipes are enabled */
4183 if (IS_CRESTLINE(dev))
4184 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4188 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4191 /* 965 has limitations... */
4192 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4193 (8 << 16) | (8 << 8) | (8 << 0));
4194 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4195 /* update cursor SR watermark */
4196 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4199 static void i9xx_update_wm(struct drm_device *dev)
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 const struct intel_watermark_params *wm_info;
4207 int planea_wm, planeb_wm;
4208 struct drm_crtc *crtc, *enabled = NULL;
4211 wm_info = &i945_wm_info;
4212 else if (!IS_GEN2(dev))
4213 wm_info = &i915_wm_info;
4215 wm_info = &i855_wm_info;
4217 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4218 crtc = intel_get_crtc_for_plane(dev, 0);
4219 if (crtc->enabled && crtc->fb) {
4220 planea_wm = intel_calculate_wm(crtc->mode.clock,
4222 crtc->fb->bits_per_pixel / 8,
4226 planea_wm = fifo_size - wm_info->guard_size;
4228 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4229 crtc = intel_get_crtc_for_plane(dev, 1);
4230 if (crtc->enabled && crtc->fb) {
4231 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4233 crtc->fb->bits_per_pixel / 8,
4235 if (enabled == NULL)
4240 planeb_wm = fifo_size - wm_info->guard_size;
4242 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4245 * Overlay gets an aggressive default since video jitter is bad.
4249 /* Play safe and disable self-refresh before adjusting watermarks. */
4250 if (IS_I945G(dev) || IS_I945GM(dev))
4251 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4252 else if (IS_I915GM(dev))
4253 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4255 /* Calc sr entries for one plane configs */
4256 if (HAS_FW_BLC(dev) && enabled) {
4257 /* self-refresh has much higher latency */
4258 static const int sr_latency_ns = 6000;
4259 int clock = enabled->mode.clock;
4260 int htotal = enabled->mode.htotal;
4261 int hdisplay = enabled->mode.hdisplay;
4262 int pixel_size = enabled->fb->bits_per_pixel / 8;
4263 unsigned long line_time_us;
4266 line_time_us = (htotal * 1000) / clock;
4268 /* Use ns/us then divide to preserve precision */
4269 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4270 pixel_size * hdisplay;
4271 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4272 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4273 srwm = wm_info->fifo_size - entries;
4277 if (IS_I945G(dev) || IS_I945GM(dev))
4278 I915_WRITE(FW_BLC_SELF,
4279 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4280 else if (IS_I915GM(dev))
4281 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4284 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4285 planea_wm, planeb_wm, cwm, srwm);
4287 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4288 fwater_hi = (cwm & 0x1f);
4290 /* Set request length to 8 cachelines per fetch */
4291 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4292 fwater_hi = fwater_hi | (1 << 8);
4294 I915_WRITE(FW_BLC, fwater_lo);
4295 I915_WRITE(FW_BLC2, fwater_hi);
4297 if (HAS_FW_BLC(dev)) {
4299 if (IS_I945G(dev) || IS_I945GM(dev))
4300 I915_WRITE(FW_BLC_SELF,
4301 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4302 else if (IS_I915GM(dev))
4303 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4304 DRM_DEBUG_KMS("memory self refresh enabled\n");
4306 DRM_DEBUG_KMS("memory self refresh disabled\n");
4310 static void i830_update_wm(struct drm_device *dev)
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct drm_crtc *crtc;
4317 crtc = single_enabled_crtc(dev);
4321 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4322 dev_priv->display.get_fifo_size(dev, 0),
4323 crtc->fb->bits_per_pixel / 8,
4325 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4326 fwater_lo |= (3<<8) | planea_wm;
4328 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4330 I915_WRITE(FW_BLC, fwater_lo);
4333 #define ILK_LP0_PLANE_LATENCY 700
4334 #define ILK_LP0_CURSOR_LATENCY 1300
4337 * Check the wm result.
4339 * If any calculated watermark values is larger than the maximum value that
4340 * can be programmed into the associated watermark register, that watermark
4343 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4344 int fbc_wm, int display_wm, int cursor_wm,
4345 const struct intel_watermark_params *display,
4346 const struct intel_watermark_params *cursor)
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4350 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4351 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4353 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4354 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4355 fbc_wm, SNB_FBC_MAX_SRWM, level);
4357 /* fbc has it's own way to disable FBC WM */
4358 I915_WRITE(DISP_ARB_CTL,
4359 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4363 if (display_wm > display->max_wm) {
4364 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4365 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4369 if (cursor_wm > cursor->max_wm) {
4370 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4371 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4375 if (!(fbc_wm || display_wm || cursor_wm)) {
4376 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4384 * Compute watermark values of WM[1-3],
4386 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4388 const struct intel_watermark_params *display,
4389 const struct intel_watermark_params *cursor,
4390 int *fbc_wm, int *display_wm, int *cursor_wm)
4392 struct drm_crtc *crtc;
4393 unsigned long line_time_us;
4394 int hdisplay, htotal, pixel_size, clock;
4395 int line_count, line_size;
4400 *fbc_wm = *display_wm = *cursor_wm = 0;
4404 crtc = intel_get_crtc_for_plane(dev, plane);
4405 hdisplay = crtc->mode.hdisplay;
4406 htotal = crtc->mode.htotal;
4407 clock = crtc->mode.clock;
4408 pixel_size = crtc->fb->bits_per_pixel / 8;
4410 line_time_us = (htotal * 1000) / clock;
4411 line_count = (latency_ns / line_time_us + 1000) / 1000;
4412 line_size = hdisplay * pixel_size;
4414 /* Use the minimum of the small and large buffer method for primary */
4415 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4416 large = line_count * line_size;
4418 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4419 *display_wm = entries + display->guard_size;
4423 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4425 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4427 /* calculate the self-refresh watermark for display cursor */
4428 entries = line_count * pixel_size * 64;
4429 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4430 *cursor_wm = entries + cursor->guard_size;
4432 return ironlake_check_srwm(dev, level,
4433 *fbc_wm, *display_wm, *cursor_wm,
4437 static void ironlake_update_wm(struct drm_device *dev)
4439 struct drm_i915_private *dev_priv = dev->dev_private;
4440 int fbc_wm, plane_wm, cursor_wm;
4441 unsigned int enabled;
4444 if (g4x_compute_wm0(dev, 0,
4445 &ironlake_display_wm_info,
4446 ILK_LP0_PLANE_LATENCY,
4447 &ironlake_cursor_wm_info,
4448 ILK_LP0_CURSOR_LATENCY,
4449 &plane_wm, &cursor_wm)) {
4450 I915_WRITE(WM0_PIPEA_ILK,
4451 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4452 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4453 " plane %d, " "cursor: %d\n",
4454 plane_wm, cursor_wm);
4458 if (g4x_compute_wm0(dev, 1,
4459 &ironlake_display_wm_info,
4460 ILK_LP0_PLANE_LATENCY,
4461 &ironlake_cursor_wm_info,
4462 ILK_LP0_CURSOR_LATENCY,
4463 &plane_wm, &cursor_wm)) {
4464 I915_WRITE(WM0_PIPEB_ILK,
4465 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4466 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4467 " plane %d, cursor: %d\n",
4468 plane_wm, cursor_wm);
4473 * Calculate and update the self-refresh watermark only when one
4474 * display plane is used.
4476 I915_WRITE(WM3_LP_ILK, 0);
4477 I915_WRITE(WM2_LP_ILK, 0);
4478 I915_WRITE(WM1_LP_ILK, 0);
4480 if (!single_plane_enabled(enabled))
4482 enabled = ffs(enabled) - 1;
4485 if (!ironlake_compute_srwm(dev, 1, enabled,
4486 ILK_READ_WM1_LATENCY() * 500,
4487 &ironlake_display_srwm_info,
4488 &ironlake_cursor_srwm_info,
4489 &fbc_wm, &plane_wm, &cursor_wm))
4492 I915_WRITE(WM1_LP_ILK,
4494 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4495 (fbc_wm << WM1_LP_FBC_SHIFT) |
4496 (plane_wm << WM1_LP_SR_SHIFT) |
4500 if (!ironlake_compute_srwm(dev, 2, enabled,
4501 ILK_READ_WM2_LATENCY() * 500,
4502 &ironlake_display_srwm_info,
4503 &ironlake_cursor_srwm_info,
4504 &fbc_wm, &plane_wm, &cursor_wm))
4507 I915_WRITE(WM2_LP_ILK,
4509 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4510 (fbc_wm << WM1_LP_FBC_SHIFT) |
4511 (plane_wm << WM1_LP_SR_SHIFT) |
4515 * WM3 is unsupported on ILK, probably because we don't have latency
4516 * data for that power state
4520 static void sandybridge_update_wm(struct drm_device *dev)
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4524 int fbc_wm, plane_wm, cursor_wm;
4525 unsigned int enabled;
4528 if (g4x_compute_wm0(dev, 0,
4529 &sandybridge_display_wm_info, latency,
4530 &sandybridge_cursor_wm_info, latency,
4531 &plane_wm, &cursor_wm)) {
4532 I915_WRITE(WM0_PIPEA_ILK,
4533 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4534 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4535 " plane %d, " "cursor: %d\n",
4536 plane_wm, cursor_wm);
4540 if (g4x_compute_wm0(dev, 1,
4541 &sandybridge_display_wm_info, latency,
4542 &sandybridge_cursor_wm_info, latency,
4543 &plane_wm, &cursor_wm)) {
4544 I915_WRITE(WM0_PIPEB_ILK,
4545 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547 " plane %d, cursor: %d\n",
4548 plane_wm, cursor_wm);
4552 /* IVB has 3 pipes */
4553 if (IS_IVYBRIDGE(dev) &&
4554 g4x_compute_wm0(dev, 2,
4555 &sandybridge_display_wm_info, latency,
4556 &sandybridge_cursor_wm_info, latency,
4557 &plane_wm, &cursor_wm)) {
4558 I915_WRITE(WM0_PIPEC_IVB,
4559 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4560 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4561 " plane %d, cursor: %d\n",
4562 plane_wm, cursor_wm);
4567 * Calculate and update the self-refresh watermark only when one
4568 * display plane is used.
4570 * SNB support 3 levels of watermark.
4572 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4573 * and disabled in the descending order
4576 I915_WRITE(WM3_LP_ILK, 0);
4577 I915_WRITE(WM2_LP_ILK, 0);
4578 I915_WRITE(WM1_LP_ILK, 0);
4580 if (!single_plane_enabled(enabled))
4582 enabled = ffs(enabled) - 1;
4585 if (!ironlake_compute_srwm(dev, 1, enabled,
4586 SNB_READ_WM1_LATENCY() * 500,
4587 &sandybridge_display_srwm_info,
4588 &sandybridge_cursor_srwm_info,
4589 &fbc_wm, &plane_wm, &cursor_wm))
4592 I915_WRITE(WM1_LP_ILK,
4594 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4595 (fbc_wm << WM1_LP_FBC_SHIFT) |
4596 (plane_wm << WM1_LP_SR_SHIFT) |
4600 if (!ironlake_compute_srwm(dev, 2, enabled,
4601 SNB_READ_WM2_LATENCY() * 500,
4602 &sandybridge_display_srwm_info,
4603 &sandybridge_cursor_srwm_info,
4604 &fbc_wm, &plane_wm, &cursor_wm))
4607 I915_WRITE(WM2_LP_ILK,
4609 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4610 (fbc_wm << WM1_LP_FBC_SHIFT) |
4611 (plane_wm << WM1_LP_SR_SHIFT) |
4615 if (!ironlake_compute_srwm(dev, 3, enabled,
4616 SNB_READ_WM3_LATENCY() * 500,
4617 &sandybridge_display_srwm_info,
4618 &sandybridge_cursor_srwm_info,
4619 &fbc_wm, &plane_wm, &cursor_wm))
4622 I915_WRITE(WM3_LP_ILK,
4624 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4625 (fbc_wm << WM1_LP_FBC_SHIFT) |
4626 (plane_wm << WM1_LP_SR_SHIFT) |
4631 * intel_update_watermarks - update FIFO watermark values based on current modes
4633 * Calculate watermark values for the various WM regs based on current mode
4634 * and plane configuration.
4636 * There are several cases to deal with here:
4637 * - normal (i.e. non-self-refresh)
4638 * - self-refresh (SR) mode
4639 * - lines are large relative to FIFO size (buffer can hold up to 2)
4640 * - lines are small relative to FIFO size (buffer can hold more than 2
4641 * lines), so need to account for TLB latency
4643 * The normal calculation is:
4644 * watermark = dotclock * bytes per pixel * latency
4645 * where latency is platform & configuration dependent (we assume pessimal
4648 * The SR calculation is:
4649 * watermark = (trunc(latency/line time)+1) * surface width *
4652 * line time = htotal / dotclock
4653 * surface width = hdisplay for normal plane and 64 for cursor
4654 * and latency is assumed to be high, as above.
4656 * The final value programmed to the register should always be rounded up,
4657 * and include an extra 2 entries to account for clock crossings.
4659 * We don't use the sprite, so we can ignore that. And on Crestline we have
4660 * to set the non-SR watermarks to 8.
4662 static void intel_update_watermarks(struct drm_device *dev)
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4666 if (dev_priv->display.update_wm)
4667 dev_priv->display.update_wm(dev);
4670 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4672 if (i915_panel_use_ssc >= 0)
4673 return i915_panel_use_ssc != 0;
4674 return dev_priv->lvds_use_ssc
4675 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4679 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4680 * @crtc: CRTC structure
4681 * @mode: requested mode
4683 * A pipe may be connected to one or more outputs. Based on the depth of the
4684 * attached framebuffer, choose a good color depth to use on the pipe.
4686 * If possible, match the pipe depth to the fb depth. In some cases, this
4687 * isn't ideal, because the connected output supports a lesser or restricted
4688 * set of depths. Resolve that here:
4689 * LVDS typically supports only 6bpc, so clamp down in that case
4690 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4691 * Displays may support a restricted set as well, check EDID and clamp as
4693 * DP may want to dither down to 6bpc to fit larger modes
4696 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4697 * true if they don't match).
4699 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4700 unsigned int *pipe_bpp,
4701 struct drm_display_mode *mode)
4703 struct drm_device *dev = crtc->dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 struct drm_encoder *encoder;
4706 struct drm_connector *connector;
4707 unsigned int display_bpc = UINT_MAX, bpc;
4709 /* Walk the encoders & connectors on this crtc, get min bpc */
4710 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4711 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4713 if (encoder->crtc != crtc)
4716 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4717 unsigned int lvds_bpc;
4719 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4725 if (lvds_bpc < display_bpc) {
4726 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4727 display_bpc = lvds_bpc;
4732 /* Not one of the known troublemakers, check the EDID */
4733 list_for_each_entry(connector, &dev->mode_config.connector_list,
4735 if (connector->encoder != encoder)
4738 /* Don't use an invalid EDID bpc value */
4739 if (connector->display_info.bpc &&
4740 connector->display_info.bpc < display_bpc) {
4741 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4742 display_bpc = connector->display_info.bpc;
4747 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4748 * through, clamp it down. (Note: >12bpc will be caught below.)
4750 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4751 if (display_bpc > 8 && display_bpc < 12) {
4752 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4755 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4761 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4762 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4767 * We could just drive the pipe at the highest bpc all the time and
4768 * enable dithering as needed, but that costs bandwidth. So choose
4769 * the minimum value that expresses the full color range of the fb but
4770 * also stays within the max display bpc discovered above.
4773 switch (crtc->fb->depth) {
4775 bpc = 8; /* since we go through a colormap */
4779 bpc = 6; /* min is 18bpp */
4791 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4792 bpc = min((unsigned int)8, display_bpc);
4796 display_bpc = min(display_bpc, bpc);
4798 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4801 *pipe_bpp = display_bpc * 3;
4803 return display_bpc != bpc;
4806 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4807 struct drm_display_mode *mode,
4808 struct drm_display_mode *adjusted_mode,
4810 struct drm_framebuffer *old_fb)
4812 struct drm_device *dev = crtc->dev;
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815 int pipe = intel_crtc->pipe;
4816 int plane = intel_crtc->plane;
4817 int refclk, num_connectors = 0;
4818 intel_clock_t clock, reduced_clock;
4819 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4820 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4821 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4822 struct drm_mode_config *mode_config = &dev->mode_config;
4823 struct intel_encoder *encoder;
4824 const intel_limit_t *limit;
4829 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4830 if (encoder->base.crtc != crtc)
4833 switch (encoder->type) {
4834 case INTEL_OUTPUT_LVDS:
4837 case INTEL_OUTPUT_SDVO:
4838 case INTEL_OUTPUT_HDMI:
4840 if (encoder->needs_tv_clock)
4843 case INTEL_OUTPUT_DVO:
4846 case INTEL_OUTPUT_TVOUT:
4849 case INTEL_OUTPUT_ANALOG:
4852 case INTEL_OUTPUT_DISPLAYPORT:
4860 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4861 refclk = dev_priv->lvds_ssc_freq * 1000;
4862 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4864 } else if (!IS_GEN2(dev)) {
4871 * Returns a set of divisors for the desired target clock with the given
4872 * refclk, or FALSE. The returned values represent the clock equation:
4873 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4875 limit = intel_limit(crtc, refclk);
4876 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4878 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4882 /* Ensure that the cursor is valid for the new mode before changing... */
4883 intel_crtc_update_cursor(crtc, true);
4885 if (is_lvds && dev_priv->lvds_downclock_avail) {
4886 has_reduced_clock = limit->find_pll(limit, crtc,
4887 dev_priv->lvds_downclock,
4890 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4892 * If the different P is found, it means that we can't
4893 * switch the display clock by using the FP0/FP1.
4894 * In such case we will disable the LVDS downclock
4897 DRM_DEBUG_KMS("Different P is found for "
4898 "LVDS clock/downclock\n");
4899 has_reduced_clock = 0;
4902 /* SDVO TV has fixed PLL values depend on its clock range,
4903 this mirrors vbios setting. */
4904 if (is_sdvo && is_tv) {
4905 if (adjusted_mode->clock >= 100000
4906 && adjusted_mode->clock < 140500) {
4912 } else if (adjusted_mode->clock >= 140500
4913 && adjusted_mode->clock <= 200000) {
4922 if (IS_PINEVIEW(dev)) {
4923 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4924 if (has_reduced_clock)
4925 fp2 = (1 << reduced_clock.n) << 16 |
4926 reduced_clock.m1 << 8 | reduced_clock.m2;
4928 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4929 if (has_reduced_clock)
4930 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4934 dpll = DPLL_VGA_MODE_DIS;
4936 if (!IS_GEN2(dev)) {
4938 dpll |= DPLLB_MODE_LVDS;
4940 dpll |= DPLLB_MODE_DAC_SERIAL;
4942 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4943 if (pixel_multiplier > 1) {
4944 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4945 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4947 dpll |= DPLL_DVO_HIGH_SPEED;
4950 dpll |= DPLL_DVO_HIGH_SPEED;
4952 /* compute bitmask from p1 value */
4953 if (IS_PINEVIEW(dev))
4954 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4956 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4957 if (IS_G4X(dev) && has_reduced_clock)
4958 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4962 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4965 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4968 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4971 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4974 if (INTEL_INFO(dev)->gen >= 4)
4975 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4978 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4981 dpll |= PLL_P1_DIVIDE_BY_TWO;
4983 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4985 dpll |= PLL_P2_DIVIDE_BY_4;
4989 if (is_sdvo && is_tv)
4990 dpll |= PLL_REF_INPUT_TVCLKINBC;
4992 /* XXX: just matching BIOS for now */
4993 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4995 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4996 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4998 dpll |= PLL_REF_INPUT_DREFCLK;
5000 /* setup pipeconf */
5001 pipeconf = I915_READ(PIPECONF(pipe));
5003 /* Set up the display plane register */
5004 dspcntr = DISPPLANE_GAMMA_ENABLE;
5006 /* Ironlake's plane is forced to pipe, bit 24 is to
5007 enable color space conversion */
5009 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5011 dspcntr |= DISPPLANE_SEL_PIPE_B;
5013 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5014 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5017 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5021 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5022 pipeconf |= PIPECONF_DOUBLE_WIDE;
5024 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5027 /* default to 8bpc */
5028 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5030 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5031 pipeconf |= PIPECONF_BPP_6 |
5032 PIPECONF_DITHER_EN |
5033 PIPECONF_DITHER_TYPE_SP;
5037 dpll |= DPLL_VCO_ENABLE;
5039 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5040 drm_mode_debug_printmodeline(mode);
5042 I915_WRITE(FP0(pipe), fp);
5043 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5045 POSTING_READ(DPLL(pipe));
5048 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5049 * This is an exception to the general rule that mode_set doesn't turn
5053 temp = I915_READ(LVDS);
5054 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5056 temp |= LVDS_PIPEB_SELECT;
5058 temp &= ~LVDS_PIPEB_SELECT;
5060 /* set the corresponsding LVDS_BORDER bit */
5061 temp |= dev_priv->lvds_border_bits;
5062 /* Set the B0-B3 data pairs corresponding to whether we're going to
5063 * set the DPLLs for dual-channel mode or not.
5066 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5068 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5070 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5071 * appropriately here, but we need to look more thoroughly into how
5072 * panels behave in the two modes.
5074 /* set the dithering flag on LVDS as needed */
5075 if (INTEL_INFO(dev)->gen >= 4) {
5076 if (dev_priv->lvds_dither)
5077 temp |= LVDS_ENABLE_DITHER;
5079 temp &= ~LVDS_ENABLE_DITHER;
5081 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5082 lvds_sync |= LVDS_HSYNC_POLARITY;
5083 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5084 lvds_sync |= LVDS_VSYNC_POLARITY;
5085 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5087 char flags[2] = "-+";
5088 DRM_INFO("Changing LVDS panel from "
5089 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5090 flags[!(temp & LVDS_HSYNC_POLARITY)],
5091 flags[!(temp & LVDS_VSYNC_POLARITY)],
5092 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5093 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5094 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5097 I915_WRITE(LVDS, temp);
5101 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5104 I915_WRITE(DPLL(pipe), dpll);
5106 /* Wait for the clocks to stabilize. */
5107 POSTING_READ(DPLL(pipe));
5110 if (INTEL_INFO(dev)->gen >= 4) {
5113 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5115 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5119 I915_WRITE(DPLL_MD(pipe), temp);
5121 /* The pixel multiplier can only be updated once the
5122 * DPLL is enabled and the clocks are stable.
5124 * So write it again.
5126 I915_WRITE(DPLL(pipe), dpll);
5129 intel_crtc->lowfreq_avail = false;
5130 if (is_lvds && has_reduced_clock && i915_powersave) {
5131 I915_WRITE(FP1(pipe), fp2);
5132 intel_crtc->lowfreq_avail = true;
5133 if (HAS_PIPE_CXSR(dev)) {
5134 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5135 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5138 I915_WRITE(FP1(pipe), fp);
5139 if (HAS_PIPE_CXSR(dev)) {
5140 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5141 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5145 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5146 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5147 /* the chip adds 2 halflines automatically */
5148 adjusted_mode->crtc_vdisplay -= 1;
5149 adjusted_mode->crtc_vtotal -= 1;
5150 adjusted_mode->crtc_vblank_start -= 1;
5151 adjusted_mode->crtc_vblank_end -= 1;
5152 adjusted_mode->crtc_vsync_end -= 1;
5153 adjusted_mode->crtc_vsync_start -= 1;
5155 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5157 I915_WRITE(HTOTAL(pipe),
5158 (adjusted_mode->crtc_hdisplay - 1) |
5159 ((adjusted_mode->crtc_htotal - 1) << 16));
5160 I915_WRITE(HBLANK(pipe),
5161 (adjusted_mode->crtc_hblank_start - 1) |
5162 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5163 I915_WRITE(HSYNC(pipe),
5164 (adjusted_mode->crtc_hsync_start - 1) |
5165 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5167 I915_WRITE(VTOTAL(pipe),
5168 (adjusted_mode->crtc_vdisplay - 1) |
5169 ((adjusted_mode->crtc_vtotal - 1) << 16));
5170 I915_WRITE(VBLANK(pipe),
5171 (adjusted_mode->crtc_vblank_start - 1) |
5172 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5173 I915_WRITE(VSYNC(pipe),
5174 (adjusted_mode->crtc_vsync_start - 1) |
5175 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5177 /* pipesrc and dspsize control the size that is scaled from,
5178 * which should always be the user's requested size.
5180 I915_WRITE(DSPSIZE(plane),
5181 ((mode->vdisplay - 1) << 16) |
5182 (mode->hdisplay - 1));
5183 I915_WRITE(DSPPOS(plane), 0);
5184 I915_WRITE(PIPESRC(pipe),
5185 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5187 I915_WRITE(PIPECONF(pipe), pipeconf);
5188 POSTING_READ(PIPECONF(pipe));
5189 intel_enable_pipe(dev_priv, pipe, false);
5191 intel_wait_for_vblank(dev, pipe);
5193 I915_WRITE(DSPCNTR(plane), dspcntr);
5194 POSTING_READ(DSPCNTR(plane));
5195 intel_enable_plane(dev_priv, plane, pipe);
5197 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5199 intel_update_watermarks(dev);
5205 * Initialize reference clocks when the driver loads
5207 void ironlake_init_pch_refclk(struct drm_device *dev)
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 struct drm_mode_config *mode_config = &dev->mode_config;
5211 struct intel_encoder *encoder;
5213 bool has_lvds = false;
5214 bool has_cpu_edp = false;
5215 bool has_pch_edp = false;
5216 bool has_panel = false;
5217 bool has_ck505 = false;
5218 bool can_ssc = false;
5220 /* We need to take the global config into account */
5221 list_for_each_entry(encoder, &mode_config->encoder_list,
5223 switch (encoder->type) {
5224 case INTEL_OUTPUT_LVDS:
5228 case INTEL_OUTPUT_EDP:
5230 if (intel_encoder_is_pch_edp(&encoder->base))
5238 if (HAS_PCH_IBX(dev)) {
5239 has_ck505 = dev_priv->display_clock_mode;
5240 can_ssc = has_ck505;
5246 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5247 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5250 /* Ironlake: try to setup display ref clock before DPLL
5251 * enabling. This is only under driver's control after
5252 * PCH B stepping, previous chipset stepping should be
5253 * ignoring this setting.
5255 temp = I915_READ(PCH_DREF_CONTROL);
5256 /* Always enable nonspread source */
5257 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5260 temp |= DREF_NONSPREAD_CK505_ENABLE;
5262 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5265 temp &= ~DREF_SSC_SOURCE_MASK;
5266 temp |= DREF_SSC_SOURCE_ENABLE;
5268 /* SSC must be turned on before enabling the CPU output */
5269 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5270 DRM_DEBUG_KMS("Using SSC on panel\n");
5271 temp |= DREF_SSC1_ENABLE;
5274 /* Get SSC going before enabling the outputs */
5275 I915_WRITE(PCH_DREF_CONTROL, temp);
5276 POSTING_READ(PCH_DREF_CONTROL);
5279 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5281 /* Enable CPU source on CPU attached eDP */
5283 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5284 DRM_DEBUG_KMS("Using SSC on eDP\n");
5285 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5288 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5290 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5292 I915_WRITE(PCH_DREF_CONTROL, temp);
5293 POSTING_READ(PCH_DREF_CONTROL);
5296 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5298 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5300 /* Turn off CPU output */
5301 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5303 I915_WRITE(PCH_DREF_CONTROL, temp);
5304 POSTING_READ(PCH_DREF_CONTROL);
5307 /* Turn off the SSC source */
5308 temp &= ~DREF_SSC_SOURCE_MASK;
5309 temp |= DREF_SSC_SOURCE_DISABLE;
5312 temp &= ~ DREF_SSC1_ENABLE;
5314 I915_WRITE(PCH_DREF_CONTROL, temp);
5315 POSTING_READ(PCH_DREF_CONTROL);
5320 static int ironlake_get_refclk(struct drm_crtc *crtc)
5322 struct drm_device *dev = crtc->dev;
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324 struct intel_encoder *encoder;
5325 struct drm_mode_config *mode_config = &dev->mode_config;
5326 struct intel_encoder *edp_encoder = NULL;
5327 int num_connectors = 0;
5328 bool is_lvds = false;
5330 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5331 if (encoder->base.crtc != crtc)
5334 switch (encoder->type) {
5335 case INTEL_OUTPUT_LVDS:
5338 case INTEL_OUTPUT_EDP:
5339 edp_encoder = encoder;
5345 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5346 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5347 dev_priv->lvds_ssc_freq);
5348 return dev_priv->lvds_ssc_freq * 1000;
5354 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5355 struct drm_display_mode *mode,
5356 struct drm_display_mode *adjusted_mode,
5358 struct drm_framebuffer *old_fb)
5360 struct drm_device *dev = crtc->dev;
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363 int pipe = intel_crtc->pipe;
5364 int plane = intel_crtc->plane;
5365 int refclk, num_connectors = 0;
5366 intel_clock_t clock, reduced_clock;
5367 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5368 bool ok, has_reduced_clock = false, is_sdvo = false;
5369 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5370 struct intel_encoder *has_edp_encoder = NULL;
5371 struct drm_mode_config *mode_config = &dev->mode_config;
5372 struct intel_encoder *encoder;
5373 const intel_limit_t *limit;
5375 struct fdi_m_n m_n = {0};
5378 int target_clock, pixel_multiplier, lane, link_bw, factor;
5379 unsigned int pipe_bpp;
5382 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5383 if (encoder->base.crtc != crtc)
5386 switch (encoder->type) {
5387 case INTEL_OUTPUT_LVDS:
5390 case INTEL_OUTPUT_SDVO:
5391 case INTEL_OUTPUT_HDMI:
5393 if (encoder->needs_tv_clock)
5396 case INTEL_OUTPUT_TVOUT:
5399 case INTEL_OUTPUT_ANALOG:
5402 case INTEL_OUTPUT_DISPLAYPORT:
5405 case INTEL_OUTPUT_EDP:
5406 has_edp_encoder = encoder;
5413 refclk = ironlake_get_refclk(crtc);
5416 * Returns a set of divisors for the desired target clock with the given
5417 * refclk, or FALSE. The returned values represent the clock equation:
5418 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5420 limit = intel_limit(crtc, refclk);
5421 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5423 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5427 /* Ensure that the cursor is valid for the new mode before changing... */
5428 intel_crtc_update_cursor(crtc, true);
5430 if (is_lvds && dev_priv->lvds_downclock_avail) {
5431 has_reduced_clock = limit->find_pll(limit, crtc,
5432 dev_priv->lvds_downclock,
5435 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5437 * If the different P is found, it means that we can't
5438 * switch the display clock by using the FP0/FP1.
5439 * In such case we will disable the LVDS downclock
5442 DRM_DEBUG_KMS("Different P is found for "
5443 "LVDS clock/downclock\n");
5444 has_reduced_clock = 0;
5447 /* SDVO TV has fixed PLL values depend on its clock range,
5448 this mirrors vbios setting. */
5449 if (is_sdvo && is_tv) {
5450 if (adjusted_mode->clock >= 100000
5451 && adjusted_mode->clock < 140500) {
5457 } else if (adjusted_mode->clock >= 140500
5458 && adjusted_mode->clock <= 200000) {
5468 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5470 /* CPU eDP doesn't require FDI link, so just set DP M/N
5471 according to current link config */
5472 if (has_edp_encoder &&
5473 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5474 target_clock = mode->clock;
5475 intel_edp_link_config(has_edp_encoder,
5478 /* [e]DP over FDI requires target mode clock
5479 instead of link clock */
5480 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5481 target_clock = mode->clock;
5483 target_clock = adjusted_mode->clock;
5485 /* FDI is a binary signal running at ~2.7GHz, encoding
5486 * each output octet as 10 bits. The actual frequency
5487 * is stored as a divider into a 100MHz clock, and the
5488 * mode pixel clock is stored in units of 1KHz.
5489 * Hence the bw of each lane in terms of the mode signal
5492 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5495 /* determine panel color depth */
5496 temp = I915_READ(PIPECONF(pipe));
5497 temp &= ~PIPE_BPC_MASK;
5498 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5513 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5520 intel_crtc->bpp = pipe_bpp;
5521 I915_WRITE(PIPECONF(pipe), temp);
5525 * Account for spread spectrum to avoid
5526 * oversubscribing the link. Max center spread
5527 * is 2.5%; use 5% for safety's sake.
5529 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5530 lane = bps / (link_bw * 8) + 1;
5533 intel_crtc->fdi_lanes = lane;
5535 if (pixel_multiplier > 1)
5536 link_bw *= pixel_multiplier;
5537 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5540 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5541 if (has_reduced_clock)
5542 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5545 /* Enable autotuning of the PLL clock (if permissible) */
5548 if ((intel_panel_use_ssc(dev_priv) &&
5549 dev_priv->lvds_ssc_freq == 100) ||
5550 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5552 } else if (is_sdvo && is_tv)
5555 if (clock.m < factor * clock.n)
5561 dpll |= DPLLB_MODE_LVDS;
5563 dpll |= DPLLB_MODE_DAC_SERIAL;
5565 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5566 if (pixel_multiplier > 1) {
5567 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5569 dpll |= DPLL_DVO_HIGH_SPEED;
5571 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5572 dpll |= DPLL_DVO_HIGH_SPEED;
5574 /* compute bitmask from p1 value */
5575 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5577 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5581 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5584 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5587 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5590 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5594 if (is_sdvo && is_tv)
5595 dpll |= PLL_REF_INPUT_TVCLKINBC;
5597 /* XXX: just matching BIOS for now */
5598 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5600 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5603 dpll |= PLL_REF_INPUT_DREFCLK;
5605 /* setup pipeconf */
5606 pipeconf = I915_READ(PIPECONF(pipe));
5608 /* Set up the display plane register */
5609 dspcntr = DISPPLANE_GAMMA_ENABLE;
5611 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5612 drm_mode_debug_printmodeline(mode);
5614 /* PCH eDP needs FDI, but CPU eDP does not */
5615 if (!intel_crtc->no_pll) {
5616 if (!has_edp_encoder ||
5617 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5618 I915_WRITE(PCH_FP0(pipe), fp);
5619 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5621 POSTING_READ(PCH_DPLL(pipe));
5625 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5626 fp == I915_READ(PCH_FP0(0))) {
5627 intel_crtc->use_pll_a = true;
5628 DRM_DEBUG_KMS("using pipe a dpll\n");
5629 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5630 fp == I915_READ(PCH_FP0(1))) {
5631 intel_crtc->use_pll_a = false;
5632 DRM_DEBUG_KMS("using pipe b dpll\n");
5634 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5639 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5640 * This is an exception to the general rule that mode_set doesn't turn
5644 temp = I915_READ(PCH_LVDS);
5645 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5646 if (HAS_PCH_CPT(dev)) {
5647 temp &= ~PORT_TRANS_SEL_MASK;
5648 temp |= PORT_TRANS_SEL_CPT(pipe);
5651 temp |= LVDS_PIPEB_SELECT;
5653 temp &= ~LVDS_PIPEB_SELECT;
5656 /* set the corresponsding LVDS_BORDER bit */
5657 temp |= dev_priv->lvds_border_bits;
5658 /* Set the B0-B3 data pairs corresponding to whether we're going to
5659 * set the DPLLs for dual-channel mode or not.
5662 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5664 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5666 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5667 * appropriately here, but we need to look more thoroughly into how
5668 * panels behave in the two modes.
5670 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5671 lvds_sync |= LVDS_HSYNC_POLARITY;
5672 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5673 lvds_sync |= LVDS_VSYNC_POLARITY;
5674 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5676 char flags[2] = "-+";
5677 DRM_INFO("Changing LVDS panel from "
5678 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5679 flags[!(temp & LVDS_HSYNC_POLARITY)],
5680 flags[!(temp & LVDS_VSYNC_POLARITY)],
5681 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5682 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5683 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5686 I915_WRITE(PCH_LVDS, temp);
5689 pipeconf &= ~PIPECONF_DITHER_EN;
5690 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5691 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5692 pipeconf |= PIPECONF_DITHER_EN;
5693 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5695 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5696 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5698 /* For non-DP output, clear any trans DP clock recovery setting.*/
5699 I915_WRITE(TRANSDATA_M1(pipe), 0);
5700 I915_WRITE(TRANSDATA_N1(pipe), 0);
5701 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5702 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5705 if (!intel_crtc->no_pll &&
5706 (!has_edp_encoder ||
5707 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5708 I915_WRITE(PCH_DPLL(pipe), dpll);
5710 /* Wait for the clocks to stabilize. */
5711 POSTING_READ(PCH_DPLL(pipe));
5714 /* The pixel multiplier can only be updated once the
5715 * DPLL is enabled and the clocks are stable.
5717 * So write it again.
5719 I915_WRITE(PCH_DPLL(pipe), dpll);
5722 intel_crtc->lowfreq_avail = false;
5723 if (!intel_crtc->no_pll) {
5724 if (is_lvds && has_reduced_clock && i915_powersave) {
5725 I915_WRITE(PCH_FP1(pipe), fp2);
5726 intel_crtc->lowfreq_avail = true;
5727 if (HAS_PIPE_CXSR(dev)) {
5728 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5729 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5732 I915_WRITE(PCH_FP1(pipe), fp);
5733 if (HAS_PIPE_CXSR(dev)) {
5734 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5735 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5740 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5741 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5742 /* the chip adds 2 halflines automatically */
5743 adjusted_mode->crtc_vdisplay -= 1;
5744 adjusted_mode->crtc_vtotal -= 1;
5745 adjusted_mode->crtc_vblank_start -= 1;
5746 adjusted_mode->crtc_vblank_end -= 1;
5747 adjusted_mode->crtc_vsync_end -= 1;
5748 adjusted_mode->crtc_vsync_start -= 1;
5750 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5752 I915_WRITE(HTOTAL(pipe),
5753 (adjusted_mode->crtc_hdisplay - 1) |
5754 ((adjusted_mode->crtc_htotal - 1) << 16));
5755 I915_WRITE(HBLANK(pipe),
5756 (adjusted_mode->crtc_hblank_start - 1) |
5757 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5758 I915_WRITE(HSYNC(pipe),
5759 (adjusted_mode->crtc_hsync_start - 1) |
5760 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5762 I915_WRITE(VTOTAL(pipe),
5763 (adjusted_mode->crtc_vdisplay - 1) |
5764 ((adjusted_mode->crtc_vtotal - 1) << 16));
5765 I915_WRITE(VBLANK(pipe),
5766 (adjusted_mode->crtc_vblank_start - 1) |
5767 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5768 I915_WRITE(VSYNC(pipe),
5769 (adjusted_mode->crtc_vsync_start - 1) |
5770 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5772 /* pipesrc controls the size that is scaled from, which should
5773 * always be the user's requested size.
5775 I915_WRITE(PIPESRC(pipe),
5776 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5778 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5779 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5780 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5781 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5783 if (has_edp_encoder &&
5784 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5785 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5788 I915_WRITE(PIPECONF(pipe), pipeconf);
5789 POSTING_READ(PIPECONF(pipe));
5791 intel_wait_for_vblank(dev, pipe);
5794 /* enable address swizzle for tiling buffer */
5795 temp = I915_READ(DISP_ARB_CTL);
5796 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5799 I915_WRITE(DSPCNTR(plane), dspcntr);
5800 POSTING_READ(DSPCNTR(plane));
5802 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5804 intel_update_watermarks(dev);
5809 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5810 struct drm_display_mode *mode,
5811 struct drm_display_mode *adjusted_mode,
5813 struct drm_framebuffer *old_fb)
5815 struct drm_device *dev = crtc->dev;
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5818 int pipe = intel_crtc->pipe;
5821 drm_vblank_pre_modeset(dev, pipe);
5823 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5826 drm_vblank_post_modeset(dev, pipe);
5828 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5833 static void g4x_write_eld(struct drm_connector *connector,
5834 struct drm_crtc *crtc)
5836 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5837 uint8_t *eld = connector->eld;
5842 i = I915_READ(G4X_AUD_VID_DID);
5844 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5845 eldv = G4X_ELDV_DEVCL_DEVBLC;
5847 eldv = G4X_ELDV_DEVCTG;
5849 i = I915_READ(G4X_AUD_CNTL_ST);
5850 i &= ~(eldv | G4X_ELD_ADDR);
5851 len = (i >> 9) & 0x1f; /* ELD buffer size */
5852 I915_WRITE(G4X_AUD_CNTL_ST, i);
5857 len = min_t(uint8_t, eld[2], len);
5858 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5859 for (i = 0; i < len; i++)
5860 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5862 i = I915_READ(G4X_AUD_CNTL_ST);
5864 I915_WRITE(G4X_AUD_CNTL_ST, i);
5867 static void ironlake_write_eld(struct drm_connector *connector,
5868 struct drm_crtc *crtc)
5870 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5871 uint8_t *eld = connector->eld;
5879 if (HAS_PCH_IBX(connector->dev)) {
5880 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5881 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5882 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5884 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5885 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5886 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5889 i = to_intel_crtc(crtc)->pipe;
5890 hdmiw_hdmiedid += i * 0x100;
5891 aud_cntl_st += i * 0x100;
5893 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5895 i = I915_READ(aud_cntl_st);
5896 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5898 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5899 /* operate blindly on all ports */
5900 eldv = GEN5_ELD_VALIDB;
5901 eldv |= GEN5_ELD_VALIDB << 4;
5902 eldv |= GEN5_ELD_VALIDB << 8;
5904 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5905 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5908 i = I915_READ(aud_cntrl_st2);
5910 I915_WRITE(aud_cntrl_st2, i);
5915 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5916 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5917 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5920 i = I915_READ(aud_cntl_st);
5921 i &= ~GEN5_ELD_ADDRESS;
5922 I915_WRITE(aud_cntl_st, i);
5924 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5925 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5926 for (i = 0; i < len; i++)
5927 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5929 i = I915_READ(aud_cntrl_st2);
5931 I915_WRITE(aud_cntrl_st2, i);
5934 void intel_write_eld(struct drm_encoder *encoder,
5935 struct drm_display_mode *mode)
5937 struct drm_crtc *crtc = encoder->crtc;
5938 struct drm_connector *connector;
5939 struct drm_device *dev = encoder->dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5942 connector = drm_select_eld(encoder, mode);
5946 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5948 drm_get_connector_name(connector),
5949 connector->encoder->base.id,
5950 drm_get_encoder_name(connector->encoder));
5952 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5954 if (dev_priv->display.write_eld)
5955 dev_priv->display.write_eld(connector, crtc);
5958 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5959 void intel_crtc_load_lut(struct drm_crtc *crtc)
5961 struct drm_device *dev = crtc->dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5964 int palreg = PALETTE(intel_crtc->pipe);
5967 /* The clocks have to be on to load the palette. */
5968 if (!crtc->enabled || !intel_crtc->active)
5971 /* use legacy palette for Ironlake */
5972 if (HAS_PCH_SPLIT(dev))
5973 palreg = LGC_PALETTE(intel_crtc->pipe);
5975 for (i = 0; i < 256; i++) {
5976 I915_WRITE(palreg + 4 * i,
5977 (intel_crtc->lut_r[i] << 16) |
5978 (intel_crtc->lut_g[i] << 8) |
5979 intel_crtc->lut_b[i]);
5983 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5985 struct drm_device *dev = crtc->dev;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 bool visible = base != 0;
5991 if (intel_crtc->cursor_visible == visible)
5994 cntl = I915_READ(_CURACNTR);
5996 /* On these chipsets we can only modify the base whilst
5997 * the cursor is disabled.
5999 I915_WRITE(_CURABASE, base);
6001 cntl &= ~(CURSOR_FORMAT_MASK);
6002 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6003 cntl |= CURSOR_ENABLE |
6004 CURSOR_GAMMA_ENABLE |
6007 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6008 I915_WRITE(_CURACNTR, cntl);
6010 intel_crtc->cursor_visible = visible;
6013 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6015 struct drm_device *dev = crtc->dev;
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6018 int pipe = intel_crtc->pipe;
6019 bool visible = base != 0;
6021 if (intel_crtc->cursor_visible != visible) {
6022 uint32_t cntl = I915_READ(CURCNTR(pipe));
6024 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6025 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6026 cntl |= pipe << 28; /* Connect to correct pipe */
6028 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6029 cntl |= CURSOR_MODE_DISABLE;
6031 I915_WRITE(CURCNTR(pipe), cntl);
6033 intel_crtc->cursor_visible = visible;
6035 /* and commit changes on next vblank */
6036 I915_WRITE(CURBASE(pipe), base);
6039 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6041 struct drm_device *dev = crtc->dev;
6042 struct drm_i915_private *dev_priv = dev->dev_private;
6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6044 int pipe = intel_crtc->pipe;
6045 bool visible = base != 0;
6047 if (intel_crtc->cursor_visible != visible) {
6048 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6050 cntl &= ~CURSOR_MODE;
6051 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6053 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6054 cntl |= CURSOR_MODE_DISABLE;
6056 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6058 intel_crtc->cursor_visible = visible;
6060 /* and commit changes on next vblank */
6061 I915_WRITE(CURBASE_IVB(pipe), base);
6064 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6065 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6068 struct drm_device *dev = crtc->dev;
6069 struct drm_i915_private *dev_priv = dev->dev_private;
6070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6071 int pipe = intel_crtc->pipe;
6072 int x = intel_crtc->cursor_x;
6073 int y = intel_crtc->cursor_y;
6079 if (on && crtc->enabled && crtc->fb) {
6080 base = intel_crtc->cursor_addr;
6081 if (x > (int) crtc->fb->width)
6084 if (y > (int) crtc->fb->height)
6090 if (x + intel_crtc->cursor_width < 0)
6093 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6096 pos |= x << CURSOR_X_SHIFT;
6099 if (y + intel_crtc->cursor_height < 0)
6102 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6105 pos |= y << CURSOR_Y_SHIFT;
6107 visible = base != 0;
6108 if (!visible && !intel_crtc->cursor_visible)
6111 if (IS_IVYBRIDGE(dev)) {
6112 I915_WRITE(CURPOS_IVB(pipe), pos);
6113 ivb_update_cursor(crtc, base);
6115 I915_WRITE(CURPOS(pipe), pos);
6116 if (IS_845G(dev) || IS_I865G(dev))
6117 i845_update_cursor(crtc, base);
6119 i9xx_update_cursor(crtc, base);
6123 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6126 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6127 struct drm_file *file,
6129 uint32_t width, uint32_t height)
6131 struct drm_device *dev = crtc->dev;
6132 struct drm_i915_private *dev_priv = dev->dev_private;
6133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6134 struct drm_i915_gem_object *obj;
6138 DRM_DEBUG_KMS("\n");
6140 /* if we want to turn off the cursor ignore width and height */
6142 DRM_DEBUG_KMS("cursor off\n");
6145 mutex_lock(&dev->struct_mutex);
6149 /* Currently we only support 64x64 cursors */
6150 if (width != 64 || height != 64) {
6151 DRM_ERROR("we currently only support 64x64 cursors\n");
6155 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6156 if (&obj->base == NULL)
6159 if (obj->base.size < width * height * 4) {
6160 DRM_ERROR("buffer is to small\n");
6165 /* we only need to pin inside GTT if cursor is non-phy */
6166 mutex_lock(&dev->struct_mutex);
6167 if (!dev_priv->info->cursor_needs_physical) {
6168 if (obj->tiling_mode) {
6169 DRM_ERROR("cursor cannot be tiled\n");
6174 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6176 DRM_ERROR("failed to move cursor bo into the GTT\n");
6180 ret = i915_gem_object_put_fence(obj);
6182 DRM_ERROR("failed to release fence for cursor");
6186 addr = obj->gtt_offset;
6188 int align = IS_I830(dev) ? 16 * 1024 : 256;
6189 ret = i915_gem_attach_phys_object(dev, obj,
6190 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6193 DRM_ERROR("failed to attach phys object\n");
6196 addr = obj->phys_obj->handle->busaddr;
6200 I915_WRITE(CURSIZE, (height << 12) | width);
6203 if (intel_crtc->cursor_bo) {
6204 if (dev_priv->info->cursor_needs_physical) {
6205 if (intel_crtc->cursor_bo != obj)
6206 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6208 i915_gem_object_unpin(intel_crtc->cursor_bo);
6209 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6212 mutex_unlock(&dev->struct_mutex);
6214 intel_crtc->cursor_addr = addr;
6215 intel_crtc->cursor_bo = obj;
6216 intel_crtc->cursor_width = width;
6217 intel_crtc->cursor_height = height;
6219 intel_crtc_update_cursor(crtc, true);
6223 i915_gem_object_unpin(obj);
6225 mutex_unlock(&dev->struct_mutex);
6227 drm_gem_object_unreference_unlocked(&obj->base);
6231 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6235 intel_crtc->cursor_x = x;
6236 intel_crtc->cursor_y = y;
6238 intel_crtc_update_cursor(crtc, true);
6243 /** Sets the color ramps on behalf of RandR */
6244 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6245 u16 blue, int regno)
6247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249 intel_crtc->lut_r[regno] = red >> 8;
6250 intel_crtc->lut_g[regno] = green >> 8;
6251 intel_crtc->lut_b[regno] = blue >> 8;
6254 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6255 u16 *blue, int regno)
6257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259 *red = intel_crtc->lut_r[regno] << 8;
6260 *green = intel_crtc->lut_g[regno] << 8;
6261 *blue = intel_crtc->lut_b[regno] << 8;
6264 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6265 u16 *blue, uint32_t start, uint32_t size)
6267 int end = (start + size > 256) ? 256 : start + size, i;
6268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270 for (i = start; i < end; i++) {
6271 intel_crtc->lut_r[i] = red[i] >> 8;
6272 intel_crtc->lut_g[i] = green[i] >> 8;
6273 intel_crtc->lut_b[i] = blue[i] >> 8;
6276 intel_crtc_load_lut(crtc);
6280 * Get a pipe with a simple mode set on it for doing load-based monitor
6283 * It will be up to the load-detect code to adjust the pipe as appropriate for
6284 * its requirements. The pipe will be connected to no other encoders.
6286 * Currently this code will only succeed if there is a pipe with no encoders
6287 * configured for it. In the future, it could choose to temporarily disable
6288 * some outputs to free up a pipe for its use.
6290 * \return crtc, or NULL if no pipes are available.
6293 /* VESA 640x480x72Hz mode to set on the pipe */
6294 static struct drm_display_mode load_detect_mode = {
6295 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6296 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6299 static struct drm_framebuffer *
6300 intel_framebuffer_create(struct drm_device *dev,
6301 struct drm_mode_fb_cmd *mode_cmd,
6302 struct drm_i915_gem_object *obj)
6304 struct intel_framebuffer *intel_fb;
6307 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6309 drm_gem_object_unreference_unlocked(&obj->base);
6310 return ERR_PTR(-ENOMEM);
6313 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6315 drm_gem_object_unreference_unlocked(&obj->base);
6317 return ERR_PTR(ret);
6320 return &intel_fb->base;
6324 intel_framebuffer_pitch_for_width(int width, int bpp)
6326 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6327 return ALIGN(pitch, 64);
6331 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6333 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6334 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6337 static struct drm_framebuffer *
6338 intel_framebuffer_create_for_mode(struct drm_device *dev,
6339 struct drm_display_mode *mode,
6342 struct drm_i915_gem_object *obj;
6343 struct drm_mode_fb_cmd mode_cmd;
6345 obj = i915_gem_alloc_object(dev,
6346 intel_framebuffer_size_for_mode(mode, bpp));
6348 return ERR_PTR(-ENOMEM);
6350 mode_cmd.width = mode->hdisplay;
6351 mode_cmd.height = mode->vdisplay;
6352 mode_cmd.depth = depth;
6354 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6356 return intel_framebuffer_create(dev, &mode_cmd, obj);
6359 static struct drm_framebuffer *
6360 mode_fits_in_fbdev(struct drm_device *dev,
6361 struct drm_display_mode *mode)
6363 struct drm_i915_private *dev_priv = dev->dev_private;
6364 struct drm_i915_gem_object *obj;
6365 struct drm_framebuffer *fb;
6367 if (dev_priv->fbdev == NULL)
6370 obj = dev_priv->fbdev->ifb.obj;
6374 fb = &dev_priv->fbdev->ifb.base;
6375 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6376 fb->bits_per_pixel))
6379 if (obj->base.size < mode->vdisplay * fb->pitch)
6385 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6386 struct drm_connector *connector,
6387 struct drm_display_mode *mode,
6388 struct intel_load_detect_pipe *old)
6390 struct intel_crtc *intel_crtc;
6391 struct drm_crtc *possible_crtc;
6392 struct drm_encoder *encoder = &intel_encoder->base;
6393 struct drm_crtc *crtc = NULL;
6394 struct drm_device *dev = encoder->dev;
6395 struct drm_framebuffer *old_fb;
6398 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6399 connector->base.id, drm_get_connector_name(connector),
6400 encoder->base.id, drm_get_encoder_name(encoder));
6403 * Algorithm gets a little messy:
6405 * - if the connector already has an assigned crtc, use it (but make
6406 * sure it's on first)
6408 * - try to find the first unused crtc that can drive this connector,
6409 * and use that if we find one
6412 /* See if we already have a CRTC for this connector */
6413 if (encoder->crtc) {
6414 crtc = encoder->crtc;
6416 intel_crtc = to_intel_crtc(crtc);
6417 old->dpms_mode = intel_crtc->dpms_mode;
6418 old->load_detect_temp = false;
6420 /* Make sure the crtc and connector are running */
6421 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6422 struct drm_encoder_helper_funcs *encoder_funcs;
6423 struct drm_crtc_helper_funcs *crtc_funcs;
6425 crtc_funcs = crtc->helper_private;
6426 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6428 encoder_funcs = encoder->helper_private;
6429 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6435 /* Find an unused one (if possible) */
6436 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6438 if (!(encoder->possible_crtcs & (1 << i)))
6440 if (!possible_crtc->enabled) {
6441 crtc = possible_crtc;
6447 * If we didn't find an unused CRTC, don't use any.
6450 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6454 encoder->crtc = crtc;
6455 connector->encoder = encoder;
6457 intel_crtc = to_intel_crtc(crtc);
6458 old->dpms_mode = intel_crtc->dpms_mode;
6459 old->load_detect_temp = true;
6460 old->release_fb = NULL;
6463 mode = &load_detect_mode;
6467 /* We need a framebuffer large enough to accommodate all accesses
6468 * that the plane may generate whilst we perform load detection.
6469 * We can not rely on the fbcon either being present (we get called
6470 * during its initialisation to detect all boot displays, or it may
6471 * not even exist) or that it is large enough to satisfy the
6474 crtc->fb = mode_fits_in_fbdev(dev, mode);
6475 if (crtc->fb == NULL) {
6476 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6477 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6478 old->release_fb = crtc->fb;
6480 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6481 if (IS_ERR(crtc->fb)) {
6482 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6487 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6488 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6489 if (old->release_fb)
6490 old->release_fb->funcs->destroy(old->release_fb);
6495 /* let the connector get through one full cycle before testing */
6496 intel_wait_for_vblank(dev, intel_crtc->pipe);
6501 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6502 struct drm_connector *connector,
6503 struct intel_load_detect_pipe *old)
6505 struct drm_encoder *encoder = &intel_encoder->base;
6506 struct drm_device *dev = encoder->dev;
6507 struct drm_crtc *crtc = encoder->crtc;
6508 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6509 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6511 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6512 connector->base.id, drm_get_connector_name(connector),
6513 encoder->base.id, drm_get_encoder_name(encoder));
6515 if (old->load_detect_temp) {
6516 connector->encoder = NULL;
6517 drm_helper_disable_unused_functions(dev);
6519 if (old->release_fb)
6520 old->release_fb->funcs->destroy(old->release_fb);
6525 /* Switch crtc and encoder back off if necessary */
6526 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6527 encoder_funcs->dpms(encoder, old->dpms_mode);
6528 crtc_funcs->dpms(crtc, old->dpms_mode);
6532 /* Returns the clock of the currently programmed mode of the given pipe. */
6533 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6537 int pipe = intel_crtc->pipe;
6538 u32 dpll = I915_READ(DPLL(pipe));
6540 intel_clock_t clock;
6542 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6543 fp = I915_READ(FP0(pipe));
6545 fp = I915_READ(FP1(pipe));
6547 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6548 if (IS_PINEVIEW(dev)) {
6549 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6550 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6552 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6553 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6556 if (!IS_GEN2(dev)) {
6557 if (IS_PINEVIEW(dev))
6558 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6559 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6561 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6562 DPLL_FPA01_P1_POST_DIV_SHIFT);
6564 switch (dpll & DPLL_MODE_MASK) {
6565 case DPLLB_MODE_DAC_SERIAL:
6566 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6569 case DPLLB_MODE_LVDS:
6570 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6574 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6575 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6579 /* XXX: Handle the 100Mhz refclk */
6580 intel_clock(dev, 96000, &clock);
6582 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6585 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6586 DPLL_FPA01_P1_POST_DIV_SHIFT);
6589 if ((dpll & PLL_REF_INPUT_MASK) ==
6590 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6591 /* XXX: might not be 66MHz */
6592 intel_clock(dev, 66000, &clock);
6594 intel_clock(dev, 48000, &clock);
6596 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6599 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6600 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6602 if (dpll & PLL_P2_DIVIDE_BY_4)
6607 intel_clock(dev, 48000, &clock);
6611 /* XXX: It would be nice to validate the clocks, but we can't reuse
6612 * i830PllIsValid() because it relies on the xf86_config connector
6613 * configuration being accurate, which it isn't necessarily.
6619 /** Returns the currently programmed mode of the given pipe. */
6620 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6621 struct drm_crtc *crtc)
6623 struct drm_i915_private *dev_priv = dev->dev_private;
6624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6625 int pipe = intel_crtc->pipe;
6626 struct drm_display_mode *mode;
6627 int htot = I915_READ(HTOTAL(pipe));
6628 int hsync = I915_READ(HSYNC(pipe));
6629 int vtot = I915_READ(VTOTAL(pipe));
6630 int vsync = I915_READ(VSYNC(pipe));
6632 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6636 mode->clock = intel_crtc_clock_get(dev, crtc);
6637 mode->hdisplay = (htot & 0xffff) + 1;
6638 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6639 mode->hsync_start = (hsync & 0xffff) + 1;
6640 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6641 mode->vdisplay = (vtot & 0xffff) + 1;
6642 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6643 mode->vsync_start = (vsync & 0xffff) + 1;
6644 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6646 drm_mode_set_name(mode);
6647 drm_mode_set_crtcinfo(mode, 0);
6652 #define GPU_IDLE_TIMEOUT 500 /* ms */
6654 /* When this timer fires, we've been idle for awhile */
6655 static void intel_gpu_idle_timer(unsigned long arg)
6657 struct drm_device *dev = (struct drm_device *)arg;
6658 drm_i915_private_t *dev_priv = dev->dev_private;
6660 if (!list_empty(&dev_priv->mm.active_list)) {
6661 /* Still processing requests, so just re-arm the timer. */
6662 mod_timer(&dev_priv->idle_timer, jiffies +
6663 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6667 dev_priv->busy = false;
6668 queue_work(dev_priv->wq, &dev_priv->idle_work);
6671 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6673 static void intel_crtc_idle_timer(unsigned long arg)
6675 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6676 struct drm_crtc *crtc = &intel_crtc->base;
6677 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6678 struct intel_framebuffer *intel_fb;
6680 intel_fb = to_intel_framebuffer(crtc->fb);
6681 if (intel_fb && intel_fb->obj->active) {
6682 /* The framebuffer is still being accessed by the GPU. */
6683 mod_timer(&intel_crtc->idle_timer, jiffies +
6684 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6688 intel_crtc->busy = false;
6689 queue_work(dev_priv->wq, &dev_priv->idle_work);
6692 static void intel_increase_pllclock(struct drm_crtc *crtc)
6694 struct drm_device *dev = crtc->dev;
6695 drm_i915_private_t *dev_priv = dev->dev_private;
6696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697 int pipe = intel_crtc->pipe;
6698 int dpll_reg = DPLL(pipe);
6701 if (HAS_PCH_SPLIT(dev))
6704 if (!dev_priv->lvds_downclock_avail)
6707 dpll = I915_READ(dpll_reg);
6708 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6709 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6711 /* Unlock panel regs */
6712 I915_WRITE(PP_CONTROL,
6713 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6715 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6716 I915_WRITE(dpll_reg, dpll);
6717 intel_wait_for_vblank(dev, pipe);
6719 dpll = I915_READ(dpll_reg);
6720 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6721 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6723 /* ...and lock them again */
6724 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6727 /* Schedule downclock */
6728 mod_timer(&intel_crtc->idle_timer, jiffies +
6729 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6732 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6734 struct drm_device *dev = crtc->dev;
6735 drm_i915_private_t *dev_priv = dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 int pipe = intel_crtc->pipe;
6738 int dpll_reg = DPLL(pipe);
6739 int dpll = I915_READ(dpll_reg);
6741 if (HAS_PCH_SPLIT(dev))
6744 if (!dev_priv->lvds_downclock_avail)
6748 * Since this is called by a timer, we should never get here in
6751 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6752 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6754 /* Unlock panel regs */
6755 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6758 dpll |= DISPLAY_RATE_SELECT_FPA1;
6759 I915_WRITE(dpll_reg, dpll);
6760 intel_wait_for_vblank(dev, pipe);
6761 dpll = I915_READ(dpll_reg);
6762 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6763 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6765 /* ...and lock them again */
6766 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6772 * intel_idle_update - adjust clocks for idleness
6773 * @work: work struct
6775 * Either the GPU or display (or both) went idle. Check the busy status
6776 * here and adjust the CRTC and GPU clocks as necessary.
6778 static void intel_idle_update(struct work_struct *work)
6780 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6782 struct drm_device *dev = dev_priv->dev;
6783 struct drm_crtc *crtc;
6784 struct intel_crtc *intel_crtc;
6786 if (!i915_powersave)
6789 mutex_lock(&dev->struct_mutex);
6791 i915_update_gfx_val(dev_priv);
6793 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6794 /* Skip inactive CRTCs */
6798 intel_crtc = to_intel_crtc(crtc);
6799 if (!intel_crtc->busy)
6800 intel_decrease_pllclock(crtc);
6804 mutex_unlock(&dev->struct_mutex);
6808 * intel_mark_busy - mark the GPU and possibly the display busy
6810 * @obj: object we're operating on
6812 * Callers can use this function to indicate that the GPU is busy processing
6813 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6814 * buffer), we'll also mark the display as busy, so we know to increase its
6817 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6819 drm_i915_private_t *dev_priv = dev->dev_private;
6820 struct drm_crtc *crtc = NULL;
6821 struct intel_framebuffer *intel_fb;
6822 struct intel_crtc *intel_crtc;
6824 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6827 if (!dev_priv->busy)
6828 dev_priv->busy = true;
6830 mod_timer(&dev_priv->idle_timer, jiffies +
6831 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6833 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6837 intel_crtc = to_intel_crtc(crtc);
6838 intel_fb = to_intel_framebuffer(crtc->fb);
6839 if (intel_fb->obj == obj) {
6840 if (!intel_crtc->busy) {
6841 /* Non-busy -> busy, upclock */
6842 intel_increase_pllclock(crtc);
6843 intel_crtc->busy = true;
6845 /* Busy -> busy, put off timer */
6846 mod_timer(&intel_crtc->idle_timer, jiffies +
6847 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6853 static void intel_crtc_destroy(struct drm_crtc *crtc)
6855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6856 struct drm_device *dev = crtc->dev;
6857 struct intel_unpin_work *work;
6858 unsigned long flags;
6860 spin_lock_irqsave(&dev->event_lock, flags);
6861 work = intel_crtc->unpin_work;
6862 intel_crtc->unpin_work = NULL;
6863 spin_unlock_irqrestore(&dev->event_lock, flags);
6866 cancel_work_sync(&work->work);
6870 drm_crtc_cleanup(crtc);
6875 static void intel_unpin_work_fn(struct work_struct *__work)
6877 struct intel_unpin_work *work =
6878 container_of(__work, struct intel_unpin_work, work);
6880 mutex_lock(&work->dev->struct_mutex);
6881 i915_gem_object_unpin(work->old_fb_obj);
6882 drm_gem_object_unreference(&work->pending_flip_obj->base);
6883 drm_gem_object_unreference(&work->old_fb_obj->base);
6885 intel_update_fbc(work->dev);
6886 mutex_unlock(&work->dev->struct_mutex);
6890 static void do_intel_finish_page_flip(struct drm_device *dev,
6891 struct drm_crtc *crtc)
6893 drm_i915_private_t *dev_priv = dev->dev_private;
6894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895 struct intel_unpin_work *work;
6896 struct drm_i915_gem_object *obj;
6897 struct drm_pending_vblank_event *e;
6898 struct timeval tnow, tvbl;
6899 unsigned long flags;
6901 /* Ignore early vblank irqs */
6902 if (intel_crtc == NULL)
6905 do_gettimeofday(&tnow);
6907 spin_lock_irqsave(&dev->event_lock, flags);
6908 work = intel_crtc->unpin_work;
6909 if (work == NULL || !work->pending) {
6910 spin_unlock_irqrestore(&dev->event_lock, flags);
6914 intel_crtc->unpin_work = NULL;
6918 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6920 /* Called before vblank count and timestamps have
6921 * been updated for the vblank interval of flip
6922 * completion? Need to increment vblank count and
6923 * add one videorefresh duration to returned timestamp
6924 * to account for this. We assume this happened if we
6925 * get called over 0.9 frame durations after the last
6926 * timestamped vblank.
6928 * This calculation can not be used with vrefresh rates
6929 * below 5Hz (10Hz to be on the safe side) without
6930 * promoting to 64 integers.
6932 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6933 9 * crtc->framedur_ns) {
6934 e->event.sequence++;
6935 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6939 e->event.tv_sec = tvbl.tv_sec;
6940 e->event.tv_usec = tvbl.tv_usec;
6942 list_add_tail(&e->base.link,
6943 &e->base.file_priv->event_list);
6944 wake_up_interruptible(&e->base.file_priv->event_wait);
6947 drm_vblank_put(dev, intel_crtc->pipe);
6949 spin_unlock_irqrestore(&dev->event_lock, flags);
6951 obj = work->old_fb_obj;
6953 atomic_clear_mask(1 << intel_crtc->plane,
6954 &obj->pending_flip.counter);
6955 if (atomic_read(&obj->pending_flip) == 0)
6956 wake_up(&dev_priv->pending_flip_queue);
6958 schedule_work(&work->work);
6960 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6963 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6965 drm_i915_private_t *dev_priv = dev->dev_private;
6966 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6968 do_intel_finish_page_flip(dev, crtc);
6971 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6973 drm_i915_private_t *dev_priv = dev->dev_private;
6974 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6976 do_intel_finish_page_flip(dev, crtc);
6979 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6981 drm_i915_private_t *dev_priv = dev->dev_private;
6982 struct intel_crtc *intel_crtc =
6983 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6984 unsigned long flags;
6986 spin_lock_irqsave(&dev->event_lock, flags);
6987 if (intel_crtc->unpin_work) {
6988 if ((++intel_crtc->unpin_work->pending) > 1)
6989 DRM_ERROR("Prepared flip multiple times\n");
6991 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6993 spin_unlock_irqrestore(&dev->event_lock, flags);
6996 static int intel_gen2_queue_flip(struct drm_device *dev,
6997 struct drm_crtc *crtc,
6998 struct drm_framebuffer *fb,
6999 struct drm_i915_gem_object *obj)
7001 struct drm_i915_private *dev_priv = dev->dev_private;
7002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7003 unsigned long offset;
7007 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7011 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7012 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7014 ret = BEGIN_LP_RING(6);
7018 /* Can't queue multiple flips, so wait for the previous
7019 * one to finish before executing the next.
7021 if (intel_crtc->plane)
7022 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7024 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7025 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7027 OUT_RING(MI_DISPLAY_FLIP |
7028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029 OUT_RING(fb->pitch);
7030 OUT_RING(obj->gtt_offset + offset);
7036 i915_gem_object_unpin(obj);
7041 static int intel_gen3_queue_flip(struct drm_device *dev,
7042 struct drm_crtc *crtc,
7043 struct drm_framebuffer *fb,
7044 struct drm_i915_gem_object *obj)
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048 unsigned long offset;
7052 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7056 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7057 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7059 ret = BEGIN_LP_RING(6);
7063 if (intel_crtc->plane)
7064 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7066 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7067 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7069 OUT_RING(MI_DISPLAY_FLIP_I915 |
7070 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7071 OUT_RING(fb->pitch);
7072 OUT_RING(obj->gtt_offset + offset);
7079 i915_gem_object_unpin(obj);
7084 static int intel_gen4_queue_flip(struct drm_device *dev,
7085 struct drm_crtc *crtc,
7086 struct drm_framebuffer *fb,
7087 struct drm_i915_gem_object *obj)
7089 struct drm_i915_private *dev_priv = dev->dev_private;
7090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091 uint32_t pf, pipesrc;
7094 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7098 ret = BEGIN_LP_RING(4);
7102 /* i965+ uses the linear or tiled offsets from the
7103 * Display Registers (which do not change across a page-flip)
7104 * so we need only reprogram the base address.
7106 OUT_RING(MI_DISPLAY_FLIP |
7107 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7108 OUT_RING(fb->pitch);
7109 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7111 /* XXX Enabling the panel-fitter across page-flip is so far
7112 * untested on non-native modes, so ignore it for now.
7113 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7116 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7117 OUT_RING(pf | pipesrc);
7122 i915_gem_object_unpin(obj);
7127 static int intel_gen6_queue_flip(struct drm_device *dev,
7128 struct drm_crtc *crtc,
7129 struct drm_framebuffer *fb,
7130 struct drm_i915_gem_object *obj)
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7134 uint32_t pf, pipesrc;
7137 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7141 ret = BEGIN_LP_RING(4);
7145 OUT_RING(MI_DISPLAY_FLIP |
7146 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7147 OUT_RING(fb->pitch | obj->tiling_mode);
7148 OUT_RING(obj->gtt_offset);
7150 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7151 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7152 OUT_RING(pf | pipesrc);
7157 i915_gem_object_unpin(obj);
7163 * On gen7 we currently use the blit ring because (in early silicon at least)
7164 * the render ring doesn't give us interrpts for page flip completion, which
7165 * means clients will hang after the first flip is queued. Fortunately the
7166 * blit ring generates interrupts properly, so use it instead.
7168 static int intel_gen7_queue_flip(struct drm_device *dev,
7169 struct drm_crtc *crtc,
7170 struct drm_framebuffer *fb,
7171 struct drm_i915_gem_object *obj)
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7175 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7176 uint32_t plane_bit = 0;
7179 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7183 switch(intel_crtc->plane) {
7185 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7188 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7191 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7194 WARN_ONCE(1, "unknown plane in flip command\n");
7199 ret = intel_ring_begin(ring, 4);
7203 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7204 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7205 intel_ring_emit(ring, (obj->gtt_offset));
7206 intel_ring_emit(ring, (MI_NOOP));
7207 intel_ring_advance(ring);
7211 i915_gem_object_unpin(obj);
7216 static int intel_default_queue_flip(struct drm_device *dev,
7217 struct drm_crtc *crtc,
7218 struct drm_framebuffer *fb,
7219 struct drm_i915_gem_object *obj)
7224 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7225 struct drm_framebuffer *fb,
7226 struct drm_pending_vblank_event *event)
7228 struct drm_device *dev = crtc->dev;
7229 struct drm_i915_private *dev_priv = dev->dev_private;
7230 struct intel_framebuffer *intel_fb;
7231 struct drm_i915_gem_object *obj;
7232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7233 struct intel_unpin_work *work;
7234 unsigned long flags;
7237 work = kzalloc(sizeof *work, GFP_KERNEL);
7241 work->event = event;
7242 work->dev = crtc->dev;
7243 intel_fb = to_intel_framebuffer(crtc->fb);
7244 work->old_fb_obj = intel_fb->obj;
7245 INIT_WORK(&work->work, intel_unpin_work_fn);
7247 ret = drm_vblank_get(dev, intel_crtc->pipe);
7251 /* We borrow the event spin lock for protecting unpin_work */
7252 spin_lock_irqsave(&dev->event_lock, flags);
7253 if (intel_crtc->unpin_work) {
7254 spin_unlock_irqrestore(&dev->event_lock, flags);
7256 drm_vblank_put(dev, intel_crtc->pipe);
7258 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7261 intel_crtc->unpin_work = work;
7262 spin_unlock_irqrestore(&dev->event_lock, flags);
7264 intel_fb = to_intel_framebuffer(fb);
7265 obj = intel_fb->obj;
7267 mutex_lock(&dev->struct_mutex);
7269 /* Reference the objects for the scheduled work. */
7270 drm_gem_object_reference(&work->old_fb_obj->base);
7271 drm_gem_object_reference(&obj->base);
7275 work->pending_flip_obj = obj;
7277 work->enable_stall_check = true;
7279 /* Block clients from rendering to the new back buffer until
7280 * the flip occurs and the object is no longer visible.
7282 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7284 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7286 goto cleanup_pending;
7288 intel_disable_fbc(dev);
7289 mutex_unlock(&dev->struct_mutex);
7291 trace_i915_flip_request(intel_crtc->plane, obj);
7296 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7297 drm_gem_object_unreference(&work->old_fb_obj->base);
7298 drm_gem_object_unreference(&obj->base);
7299 mutex_unlock(&dev->struct_mutex);
7301 spin_lock_irqsave(&dev->event_lock, flags);
7302 intel_crtc->unpin_work = NULL;
7303 spin_unlock_irqrestore(&dev->event_lock, flags);
7305 drm_vblank_put(dev, intel_crtc->pipe);
7312 static void intel_sanitize_modesetting(struct drm_device *dev,
7313 int pipe, int plane)
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7319 /* Clear any frame start delays used for debugging left by the BIOS */
7322 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7325 if (HAS_PCH_SPLIT(dev))
7328 /* Who knows what state these registers were left in by the BIOS or
7331 * If we leave the registers in a conflicting state (e.g. with the
7332 * display plane reading from the other pipe than the one we intend
7333 * to use) then when we attempt to teardown the active mode, we will
7334 * not disable the pipes and planes in the correct order -- leaving
7335 * a plane reading from a disabled pipe and possibly leading to
7336 * undefined behaviour.
7339 reg = DSPCNTR(plane);
7340 val = I915_READ(reg);
7342 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7344 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7347 /* This display plane is active and attached to the other CPU pipe. */
7350 /* Disable the plane and wait for it to stop reading from the pipe. */
7351 intel_disable_plane(dev_priv, plane, pipe);
7352 intel_disable_pipe(dev_priv, pipe);
7355 static void intel_crtc_reset(struct drm_crtc *crtc)
7357 struct drm_device *dev = crtc->dev;
7358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7360 /* Reset flags back to the 'unknown' status so that they
7361 * will be correctly set on the initial modeset.
7363 intel_crtc->dpms_mode = -1;
7365 /* We need to fix up any BIOS configuration that conflicts with
7368 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7371 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7372 .dpms = intel_crtc_dpms,
7373 .mode_fixup = intel_crtc_mode_fixup,
7374 .mode_set = intel_crtc_mode_set,
7375 .mode_set_base = intel_pipe_set_base,
7376 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7377 .load_lut = intel_crtc_load_lut,
7378 .disable = intel_crtc_disable,
7381 static const struct drm_crtc_funcs intel_crtc_funcs = {
7382 .reset = intel_crtc_reset,
7383 .cursor_set = intel_crtc_cursor_set,
7384 .cursor_move = intel_crtc_cursor_move,
7385 .gamma_set = intel_crtc_gamma_set,
7386 .set_config = drm_crtc_helper_set_config,
7387 .destroy = intel_crtc_destroy,
7388 .page_flip = intel_crtc_page_flip,
7391 static void intel_crtc_init(struct drm_device *dev, int pipe)
7393 drm_i915_private_t *dev_priv = dev->dev_private;
7394 struct intel_crtc *intel_crtc;
7397 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7398 if (intel_crtc == NULL)
7401 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7403 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7404 for (i = 0; i < 256; i++) {
7405 intel_crtc->lut_r[i] = i;
7406 intel_crtc->lut_g[i] = i;
7407 intel_crtc->lut_b[i] = i;
7410 /* Swap pipes & planes for FBC on pre-965 */
7411 intel_crtc->pipe = pipe;
7412 intel_crtc->plane = pipe;
7413 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7414 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7415 intel_crtc->plane = !pipe;
7418 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7419 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7420 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7421 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7423 intel_crtc_reset(&intel_crtc->base);
7424 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7425 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7427 if (HAS_PCH_SPLIT(dev)) {
7428 if (pipe == 2 && IS_IVYBRIDGE(dev))
7429 intel_crtc->no_pll = true;
7430 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7431 intel_helper_funcs.commit = ironlake_crtc_commit;
7433 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7434 intel_helper_funcs.commit = i9xx_crtc_commit;
7437 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7439 intel_crtc->busy = false;
7441 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7442 (unsigned long)intel_crtc);
7445 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7446 struct drm_file *file)
7448 drm_i915_private_t *dev_priv = dev->dev_private;
7449 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7450 struct drm_mode_object *drmmode_obj;
7451 struct intel_crtc *crtc;
7454 DRM_ERROR("called with no initialization\n");
7458 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7459 DRM_MODE_OBJECT_CRTC);
7462 DRM_ERROR("no such CRTC id\n");
7466 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7467 pipe_from_crtc_id->pipe = crtc->pipe;
7472 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7474 struct intel_encoder *encoder;
7478 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7479 if (type_mask & encoder->clone_mask)
7480 index_mask |= (1 << entry);
7487 static bool has_edp_a(struct drm_device *dev)
7489 struct drm_i915_private *dev_priv = dev->dev_private;
7491 if (!IS_MOBILE(dev))
7494 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7498 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7504 static void intel_setup_outputs(struct drm_device *dev)
7506 struct drm_i915_private *dev_priv = dev->dev_private;
7507 struct intel_encoder *encoder;
7508 bool dpd_is_edp = false;
7509 bool has_lvds = false;
7511 if (IS_MOBILE(dev) && !IS_I830(dev))
7512 has_lvds = intel_lvds_init(dev);
7513 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7514 /* disable the panel fitter on everything but LVDS */
7515 I915_WRITE(PFIT_CONTROL, 0);
7518 if (HAS_PCH_SPLIT(dev)) {
7519 dpd_is_edp = intel_dpd_is_edp(dev);
7522 intel_dp_init(dev, DP_A);
7524 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7525 intel_dp_init(dev, PCH_DP_D);
7528 intel_crt_init(dev);
7530 if (HAS_PCH_SPLIT(dev)) {
7533 if (I915_READ(HDMIB) & PORT_DETECTED) {
7534 /* PCH SDVOB multiplex with HDMIB */
7535 found = intel_sdvo_init(dev, PCH_SDVOB);
7537 intel_hdmi_init(dev, HDMIB);
7538 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7539 intel_dp_init(dev, PCH_DP_B);
7542 if (I915_READ(HDMIC) & PORT_DETECTED)
7543 intel_hdmi_init(dev, HDMIC);
7545 if (I915_READ(HDMID) & PORT_DETECTED)
7546 intel_hdmi_init(dev, HDMID);
7548 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7549 intel_dp_init(dev, PCH_DP_C);
7551 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7552 intel_dp_init(dev, PCH_DP_D);
7554 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7557 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7558 DRM_DEBUG_KMS("probing SDVOB\n");
7559 found = intel_sdvo_init(dev, SDVOB);
7560 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7561 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7562 intel_hdmi_init(dev, SDVOB);
7565 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7566 DRM_DEBUG_KMS("probing DP_B\n");
7567 intel_dp_init(dev, DP_B);
7571 /* Before G4X SDVOC doesn't have its own detect register */
7573 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7574 DRM_DEBUG_KMS("probing SDVOC\n");
7575 found = intel_sdvo_init(dev, SDVOC);
7578 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7580 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7581 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7582 intel_hdmi_init(dev, SDVOC);
7584 if (SUPPORTS_INTEGRATED_DP(dev)) {
7585 DRM_DEBUG_KMS("probing DP_C\n");
7586 intel_dp_init(dev, DP_C);
7590 if (SUPPORTS_INTEGRATED_DP(dev) &&
7591 (I915_READ(DP_D) & DP_DETECTED)) {
7592 DRM_DEBUG_KMS("probing DP_D\n");
7593 intel_dp_init(dev, DP_D);
7595 } else if (IS_GEN2(dev))
7596 intel_dvo_init(dev);
7598 if (SUPPORTS_TV(dev))
7601 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7602 encoder->base.possible_crtcs = encoder->crtc_mask;
7603 encoder->base.possible_clones =
7604 intel_encoder_clones(dev, encoder->clone_mask);
7607 /* disable all the possible outputs/crtcs before entering KMS mode */
7608 drm_helper_disable_unused_functions(dev);
7610 if (HAS_PCH_SPLIT(dev))
7611 ironlake_init_pch_refclk(dev);
7614 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7616 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7618 drm_framebuffer_cleanup(fb);
7619 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7624 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7625 struct drm_file *file,
7626 unsigned int *handle)
7628 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7629 struct drm_i915_gem_object *obj = intel_fb->obj;
7631 return drm_gem_handle_create(file, &obj->base, handle);
7634 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7635 .destroy = intel_user_framebuffer_destroy,
7636 .create_handle = intel_user_framebuffer_create_handle,
7639 int intel_framebuffer_init(struct drm_device *dev,
7640 struct intel_framebuffer *intel_fb,
7641 struct drm_mode_fb_cmd *mode_cmd,
7642 struct drm_i915_gem_object *obj)
7646 if (obj->tiling_mode == I915_TILING_Y)
7649 if (mode_cmd->pitch & 63)
7652 switch (mode_cmd->bpp) {
7655 /* Only pre-ILK can handle 5:5:5 */
7656 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7667 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7669 DRM_ERROR("framebuffer init failed %d\n", ret);
7673 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7674 intel_fb->obj = obj;
7678 static struct drm_framebuffer *
7679 intel_user_framebuffer_create(struct drm_device *dev,
7680 struct drm_file *filp,
7681 struct drm_mode_fb_cmd *mode_cmd)
7683 struct drm_i915_gem_object *obj;
7685 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7686 if (&obj->base == NULL)
7687 return ERR_PTR(-ENOENT);
7689 return intel_framebuffer_create(dev, mode_cmd, obj);
7692 static const struct drm_mode_config_funcs intel_mode_funcs = {
7693 .fb_create = intel_user_framebuffer_create,
7694 .output_poll_changed = intel_fb_output_poll_changed,
7697 static struct drm_i915_gem_object *
7698 intel_alloc_context_page(struct drm_device *dev)
7700 struct drm_i915_gem_object *ctx;
7703 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7705 ctx = i915_gem_alloc_object(dev, 4096);
7707 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7711 ret = i915_gem_object_pin(ctx, 4096, true);
7713 DRM_ERROR("failed to pin power context: %d\n", ret);
7717 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7719 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7726 i915_gem_object_unpin(ctx);
7728 drm_gem_object_unreference(&ctx->base);
7729 mutex_unlock(&dev->struct_mutex);
7733 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7735 struct drm_i915_private *dev_priv = dev->dev_private;
7738 rgvswctl = I915_READ16(MEMSWCTL);
7739 if (rgvswctl & MEMCTL_CMD_STS) {
7740 DRM_DEBUG("gpu busy, RCS change rejected\n");
7741 return false; /* still busy with another command */
7744 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7745 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7746 I915_WRITE16(MEMSWCTL, rgvswctl);
7747 POSTING_READ16(MEMSWCTL);
7749 rgvswctl |= MEMCTL_CMD_STS;
7750 I915_WRITE16(MEMSWCTL, rgvswctl);
7755 void ironlake_enable_drps(struct drm_device *dev)
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7758 u32 rgvmodectl = I915_READ(MEMMODECTL);
7759 u8 fmax, fmin, fstart, vstart;
7761 /* Enable temp reporting */
7762 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7763 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7765 /* 100ms RC evaluation intervals */
7766 I915_WRITE(RCUPEI, 100000);
7767 I915_WRITE(RCDNEI, 100000);
7769 /* Set max/min thresholds to 90ms and 80ms respectively */
7770 I915_WRITE(RCBMAXAVG, 90000);
7771 I915_WRITE(RCBMINAVG, 80000);
7773 I915_WRITE(MEMIHYST, 1);
7775 /* Set up min, max, and cur for interrupt handling */
7776 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7777 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7778 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7779 MEMMODE_FSTART_SHIFT;
7781 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7784 dev_priv->fmax = fmax; /* IPS callback will increase this */
7785 dev_priv->fstart = fstart;
7787 dev_priv->max_delay = fstart;
7788 dev_priv->min_delay = fmin;
7789 dev_priv->cur_delay = fstart;
7791 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7792 fmax, fmin, fstart);
7794 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7797 * Interrupts will be enabled in ironlake_irq_postinstall
7800 I915_WRITE(VIDSTART, vstart);
7801 POSTING_READ(VIDSTART);
7803 rgvmodectl |= MEMMODE_SWMODE_EN;
7804 I915_WRITE(MEMMODECTL, rgvmodectl);
7806 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7807 DRM_ERROR("stuck trying to change perf mode\n");
7810 ironlake_set_drps(dev, fstart);
7812 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7814 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7815 dev_priv->last_count2 = I915_READ(0x112f4);
7816 getrawmonotonic(&dev_priv->last_time2);
7819 void ironlake_disable_drps(struct drm_device *dev)
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 u16 rgvswctl = I915_READ16(MEMSWCTL);
7824 /* Ack interrupts, disable EFC interrupt */
7825 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7826 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7827 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7828 I915_WRITE(DEIIR, DE_PCU_EVENT);
7829 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7831 /* Go back to the starting frequency */
7832 ironlake_set_drps(dev, dev_priv->fstart);
7834 rgvswctl |= MEMCTL_CMD_STS;
7835 I915_WRITE(MEMSWCTL, rgvswctl);
7840 void gen6_set_rps(struct drm_device *dev, u8 val)
7842 struct drm_i915_private *dev_priv = dev->dev_private;
7845 swreq = (val & 0x3ff) << 25;
7846 I915_WRITE(GEN6_RPNSWREQ, swreq);
7849 void gen6_disable_rps(struct drm_device *dev)
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7853 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7854 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7855 I915_WRITE(GEN6_PMIER, 0);
7856 /* Complete PM interrupt masking here doesn't race with the rps work
7857 * item again unmasking PM interrupts because that is using a different
7858 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7859 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7861 spin_lock_irq(&dev_priv->rps_lock);
7862 dev_priv->pm_iir = 0;
7863 spin_unlock_irq(&dev_priv->rps_lock);
7865 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7868 static unsigned long intel_pxfreq(u32 vidfreq)
7871 int div = (vidfreq & 0x3f0000) >> 16;
7872 int post = (vidfreq & 0x3000) >> 12;
7873 int pre = (vidfreq & 0x7);
7878 freq = ((div * 133333) / ((1<<post) * pre));
7883 void intel_init_emon(struct drm_device *dev)
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7890 /* Disable to program */
7894 /* Program energy weights for various events */
7895 I915_WRITE(SDEW, 0x15040d00);
7896 I915_WRITE(CSIEW0, 0x007f0000);
7897 I915_WRITE(CSIEW1, 0x1e220004);
7898 I915_WRITE(CSIEW2, 0x04000004);
7900 for (i = 0; i < 5; i++)
7901 I915_WRITE(PEW + (i * 4), 0);
7902 for (i = 0; i < 3; i++)
7903 I915_WRITE(DEW + (i * 4), 0);
7905 /* Program P-state weights to account for frequency power adjustment */
7906 for (i = 0; i < 16; i++) {
7907 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7908 unsigned long freq = intel_pxfreq(pxvidfreq);
7909 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7914 val *= (freq / 1000);
7916 val /= (127*127*900);
7918 DRM_ERROR("bad pxval: %ld\n", val);
7921 /* Render standby states get 0 weight */
7925 for (i = 0; i < 4; i++) {
7926 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7927 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7928 I915_WRITE(PXW + (i * 4), val);
7931 /* Adjust magic regs to magic values (more experimental results) */
7932 I915_WRITE(OGW0, 0);
7933 I915_WRITE(OGW1, 0);
7934 I915_WRITE(EG0, 0x00007f00);
7935 I915_WRITE(EG1, 0x0000000e);
7936 I915_WRITE(EG2, 0x000e0000);
7937 I915_WRITE(EG3, 0x68000300);
7938 I915_WRITE(EG4, 0x42000000);
7939 I915_WRITE(EG5, 0x00140031);
7943 for (i = 0; i < 8; i++)
7944 I915_WRITE(PXWL + (i * 4), 0);
7946 /* Enable PMON + select events */
7947 I915_WRITE(ECR, 0x80000019);
7949 lcfuse = I915_READ(LCFUSE02);
7951 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7954 static bool intel_enable_rc6(struct drm_device *dev)
7957 * Respect the kernel parameter if it is set
7959 if (i915_enable_rc6 >= 0)
7960 return i915_enable_rc6;
7963 * Disable RC6 on Ironlake
7965 if (INTEL_INFO(dev)->gen == 5)
7969 * Disable rc6 on Sandybridge
7971 if (INTEL_INFO(dev)->gen == 6) {
7972 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
7975 DRM_DEBUG_DRIVER("RC6 enabled\n");
7979 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7981 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7982 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7983 u32 pcu_mbox, rc6_mask = 0;
7984 int cur_freq, min_freq, max_freq;
7987 /* Here begins a magic sequence of register writes to enable
7988 * auto-downclocking.
7990 * Perhaps there might be some value in exposing these to
7993 I915_WRITE(GEN6_RC_STATE, 0);
7994 mutex_lock(&dev_priv->dev->struct_mutex);
7995 gen6_gt_force_wake_get(dev_priv);
7997 /* disable the counters and set deterministic thresholds */
7998 I915_WRITE(GEN6_RC_CONTROL, 0);
8000 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8001 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8002 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8003 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8004 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8006 for (i = 0; i < I915_NUM_RINGS; i++)
8007 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8009 I915_WRITE(GEN6_RC_SLEEP, 0);
8010 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8011 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8012 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8013 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8015 if (intel_enable_rc6(dev_priv->dev))
8016 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8017 ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8019 I915_WRITE(GEN6_RC_CONTROL,
8021 GEN6_RC_CTL_EI_MODE(1) |
8022 GEN6_RC_CTL_HW_ENABLE);
8024 I915_WRITE(GEN6_RPNSWREQ,
8025 GEN6_FREQUENCY(10) |
8027 GEN6_AGGRESSIVE_TURBO);
8028 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8029 GEN6_FREQUENCY(12));
8031 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8032 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8035 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8036 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8037 I915_WRITE(GEN6_RP_UP_EI, 100000);
8038 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8039 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8040 I915_WRITE(GEN6_RP_CONTROL,
8041 GEN6_RP_MEDIA_TURBO |
8042 GEN6_RP_MEDIA_HW_NORMAL_MODE |
8043 GEN6_RP_MEDIA_IS_GFX |
8045 GEN6_RP_UP_BUSY_AVG |
8046 GEN6_RP_DOWN_IDLE_CONT);
8048 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8050 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8052 I915_WRITE(GEN6_PCODE_DATA, 0);
8053 I915_WRITE(GEN6_PCODE_MAILBOX,
8055 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8056 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8058 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8060 min_freq = (rp_state_cap & 0xff0000) >> 16;
8061 max_freq = rp_state_cap & 0xff;
8062 cur_freq = (gt_perf_status & 0xff00) >> 8;
8064 /* Check for overclock support */
8065 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8067 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8068 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8069 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8070 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8072 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8073 if (pcu_mbox & (1<<31)) { /* OC supported */
8074 max_freq = pcu_mbox & 0xff;
8075 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8078 /* In units of 100MHz */
8079 dev_priv->max_delay = max_freq;
8080 dev_priv->min_delay = min_freq;
8081 dev_priv->cur_delay = cur_freq;
8083 /* requires MSI enabled */
8084 I915_WRITE(GEN6_PMIER,
8085 GEN6_PM_MBOX_EVENT |
8086 GEN6_PM_THERMAL_EVENT |
8087 GEN6_PM_RP_DOWN_TIMEOUT |
8088 GEN6_PM_RP_UP_THRESHOLD |
8089 GEN6_PM_RP_DOWN_THRESHOLD |
8090 GEN6_PM_RP_UP_EI_EXPIRED |
8091 GEN6_PM_RP_DOWN_EI_EXPIRED);
8092 spin_lock_irq(&dev_priv->rps_lock);
8093 WARN_ON(dev_priv->pm_iir != 0);
8094 I915_WRITE(GEN6_PMIMR, 0);
8095 spin_unlock_irq(&dev_priv->rps_lock);
8096 /* enable all PM interrupts */
8097 I915_WRITE(GEN6_PMINTRMSK, 0);
8099 gen6_gt_force_wake_put(dev_priv);
8100 mutex_unlock(&dev_priv->dev->struct_mutex);
8103 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8106 int gpu_freq, ia_freq, max_ia_freq;
8107 int scaling_factor = 180;
8109 max_ia_freq = cpufreq_quick_get_max(0);
8111 * Default to measured freq if none found, PCU will ensure we don't go
8115 max_ia_freq = tsc_khz;
8117 /* Convert from kHz to MHz */
8118 max_ia_freq /= 1000;
8120 mutex_lock(&dev_priv->dev->struct_mutex);
8123 * For each potential GPU frequency, load a ring frequency we'd like
8124 * to use for memory access. We do this by specifying the IA frequency
8125 * the PCU should use as a reference to determine the ring frequency.
8127 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8129 int diff = dev_priv->max_delay - gpu_freq;
8132 * For GPU frequencies less than 750MHz, just use the lowest
8135 if (gpu_freq < min_freq)
8138 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8139 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8141 I915_WRITE(GEN6_PCODE_DATA,
8142 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8144 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8145 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8146 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8147 GEN6_PCODE_READY) == 0, 10)) {
8148 DRM_ERROR("pcode write of freq table timed out\n");
8153 mutex_unlock(&dev_priv->dev->struct_mutex);
8156 static void ironlake_init_clock_gating(struct drm_device *dev)
8158 struct drm_i915_private *dev_priv = dev->dev_private;
8159 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8161 /* Required for FBC */
8162 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8163 DPFCRUNIT_CLOCK_GATE_DISABLE |
8164 DPFDUNIT_CLOCK_GATE_DISABLE;
8165 /* Required for CxSR */
8166 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8168 I915_WRITE(PCH_3DCGDIS0,
8169 MARIUNIT_CLOCK_GATE_DISABLE |
8170 SVSMUNIT_CLOCK_GATE_DISABLE);
8171 I915_WRITE(PCH_3DCGDIS1,
8172 VFMUNIT_CLOCK_GATE_DISABLE);
8174 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8177 * According to the spec the following bits should be set in
8178 * order to enable memory self-refresh
8179 * The bit 22/21 of 0x42004
8180 * The bit 5 of 0x42020
8181 * The bit 15 of 0x45000
8183 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8184 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8185 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8186 I915_WRITE(ILK_DSPCLK_GATE,
8187 (I915_READ(ILK_DSPCLK_GATE) |
8188 ILK_DPARB_CLK_GATE));
8189 I915_WRITE(DISP_ARB_CTL,
8190 (I915_READ(DISP_ARB_CTL) |
8192 I915_WRITE(WM3_LP_ILK, 0);
8193 I915_WRITE(WM2_LP_ILK, 0);
8194 I915_WRITE(WM1_LP_ILK, 0);
8197 * Based on the document from hardware guys the following bits
8198 * should be set unconditionally in order to enable FBC.
8199 * The bit 22 of 0x42000
8200 * The bit 22 of 0x42004
8201 * The bit 7,8,9 of 0x42020.
8203 if (IS_IRONLAKE_M(dev)) {
8204 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8205 I915_READ(ILK_DISPLAY_CHICKEN1) |
8207 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8208 I915_READ(ILK_DISPLAY_CHICKEN2) |
8210 I915_WRITE(ILK_DSPCLK_GATE,
8211 I915_READ(ILK_DSPCLK_GATE) |
8217 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8218 I915_READ(ILK_DISPLAY_CHICKEN2) |
8219 ILK_ELPIN_409_SELECT);
8220 I915_WRITE(_3D_CHICKEN2,
8221 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8222 _3D_CHICKEN2_WM_READ_PIPELINED);
8225 static void gen6_init_clock_gating(struct drm_device *dev)
8227 struct drm_i915_private *dev_priv = dev->dev_private;
8229 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8231 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8233 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8234 I915_READ(ILK_DISPLAY_CHICKEN2) |
8235 ILK_ELPIN_409_SELECT);
8237 I915_WRITE(WM3_LP_ILK, 0);
8238 I915_WRITE(WM2_LP_ILK, 0);
8239 I915_WRITE(WM1_LP_ILK, 0);
8241 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8242 * gating disable must be set. Failure to set it results in
8243 * flickering pixels due to Z write ordering failures after
8244 * some amount of runtime in the Mesa "fire" demo, and Unigine
8245 * Sanctuary and Tropics, and apparently anything else with
8246 * alpha test or pixel discard.
8248 * According to the spec, bit 11 (RCCUNIT) must also be set,
8249 * but we didn't debug actual testcases to find it out.
8251 I915_WRITE(GEN6_UCGCTL2,
8252 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8253 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8256 * According to the spec the following bits should be
8257 * set in order to enable memory self-refresh and fbc:
8258 * The bit21 and bit22 of 0x42000
8259 * The bit21 and bit22 of 0x42004
8260 * The bit5 and bit7 of 0x42020
8261 * The bit14 of 0x70180
8262 * The bit14 of 0x71180
8264 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8265 I915_READ(ILK_DISPLAY_CHICKEN1) |
8266 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8267 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8268 I915_READ(ILK_DISPLAY_CHICKEN2) |
8269 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8270 I915_WRITE(ILK_DSPCLK_GATE,
8271 I915_READ(ILK_DSPCLK_GATE) |
8272 ILK_DPARB_CLK_GATE |
8275 for_each_pipe(pipe) {
8276 I915_WRITE(DSPCNTR(pipe),
8277 I915_READ(DSPCNTR(pipe)) |
8278 DISPPLANE_TRICKLE_FEED_DISABLE);
8279 intel_flush_display_plane(dev_priv, pipe);
8283 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8285 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8287 reg &= ~GEN7_FF_SCHED_MASK;
8288 reg |= GEN7_FF_TS_SCHED_HW;
8289 reg |= GEN7_FF_VS_SCHED_HW;
8290 reg |= GEN7_FF_DS_SCHED_HW;
8292 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8295 static void ivybridge_init_clock_gating(struct drm_device *dev)
8297 struct drm_i915_private *dev_priv = dev->dev_private;
8299 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8301 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8303 I915_WRITE(WM3_LP_ILK, 0);
8304 I915_WRITE(WM2_LP_ILK, 0);
8305 I915_WRITE(WM1_LP_ILK, 0);
8307 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8308 * This implements the WaDisableRCZUnitClockGating workaround.
8310 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8312 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8314 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8315 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8316 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8318 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8319 I915_WRITE(GEN7_L3CNTLREG1,
8320 GEN7_WA_FOR_GEN7_L3_CONTROL);
8321 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8322 GEN7_WA_L3_CHICKEN_MODE);
8324 /* This is required by WaCatErrorRejectionIssue */
8325 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8326 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8327 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8329 for_each_pipe(pipe) {
8330 I915_WRITE(DSPCNTR(pipe),
8331 I915_READ(DSPCNTR(pipe)) |
8332 DISPPLANE_TRICKLE_FEED_DISABLE);
8333 intel_flush_display_plane(dev_priv, pipe);
8336 gen7_setup_fixed_func_scheduler(dev_priv);
8339 static void g4x_init_clock_gating(struct drm_device *dev)
8341 struct drm_i915_private *dev_priv = dev->dev_private;
8342 uint32_t dspclk_gate;
8344 I915_WRITE(RENCLK_GATE_D1, 0);
8345 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8346 GS_UNIT_CLOCK_GATE_DISABLE |
8347 CL_UNIT_CLOCK_GATE_DISABLE);
8348 I915_WRITE(RAMCLK_GATE_D, 0);
8349 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8350 OVRUNIT_CLOCK_GATE_DISABLE |
8351 OVCUNIT_CLOCK_GATE_DISABLE;
8353 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8354 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8357 static void crestline_init_clock_gating(struct drm_device *dev)
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8361 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8362 I915_WRITE(RENCLK_GATE_D2, 0);
8363 I915_WRITE(DSPCLK_GATE_D, 0);
8364 I915_WRITE(RAMCLK_GATE_D, 0);
8365 I915_WRITE16(DEUC, 0);
8368 static void broadwater_init_clock_gating(struct drm_device *dev)
8370 struct drm_i915_private *dev_priv = dev->dev_private;
8372 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8373 I965_RCC_CLOCK_GATE_DISABLE |
8374 I965_RCPB_CLOCK_GATE_DISABLE |
8375 I965_ISC_CLOCK_GATE_DISABLE |
8376 I965_FBC_CLOCK_GATE_DISABLE);
8377 I915_WRITE(RENCLK_GATE_D2, 0);
8380 static void gen3_init_clock_gating(struct drm_device *dev)
8382 struct drm_i915_private *dev_priv = dev->dev_private;
8383 u32 dstate = I915_READ(D_STATE);
8385 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8386 DSTATE_DOT_CLOCK_GATING;
8387 I915_WRITE(D_STATE, dstate);
8390 static void i85x_init_clock_gating(struct drm_device *dev)
8392 struct drm_i915_private *dev_priv = dev->dev_private;
8394 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8397 static void i830_init_clock_gating(struct drm_device *dev)
8399 struct drm_i915_private *dev_priv = dev->dev_private;
8401 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8404 static void ibx_init_clock_gating(struct drm_device *dev)
8406 struct drm_i915_private *dev_priv = dev->dev_private;
8409 * On Ibex Peak and Cougar Point, we need to disable clock
8410 * gating for the panel power sequencer or it will fail to
8411 * start up when no ports are active.
8413 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8416 static void cpt_init_clock_gating(struct drm_device *dev)
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8422 * On Ibex Peak and Cougar Point, we need to disable clock
8423 * gating for the panel power sequencer or it will fail to
8424 * start up when no ports are active.
8426 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8427 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8428 DPLS_EDP_PPS_FIX_DIS);
8429 /* Without this, mode sets may fail silently on FDI */
8431 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8434 static void ironlake_teardown_rc6(struct drm_device *dev)
8436 struct drm_i915_private *dev_priv = dev->dev_private;
8438 if (dev_priv->renderctx) {
8439 i915_gem_object_unpin(dev_priv->renderctx);
8440 drm_gem_object_unreference(&dev_priv->renderctx->base);
8441 dev_priv->renderctx = NULL;
8444 if (dev_priv->pwrctx) {
8445 i915_gem_object_unpin(dev_priv->pwrctx);
8446 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8447 dev_priv->pwrctx = NULL;
8451 static void ironlake_disable_rc6(struct drm_device *dev)
8453 struct drm_i915_private *dev_priv = dev->dev_private;
8455 if (I915_READ(PWRCTXA)) {
8456 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8457 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8458 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8461 I915_WRITE(PWRCTXA, 0);
8462 POSTING_READ(PWRCTXA);
8464 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8465 POSTING_READ(RSTDBYCTL);
8468 ironlake_teardown_rc6(dev);
8471 static int ironlake_setup_rc6(struct drm_device *dev)
8473 struct drm_i915_private *dev_priv = dev->dev_private;
8475 if (dev_priv->renderctx == NULL)
8476 dev_priv->renderctx = intel_alloc_context_page(dev);
8477 if (!dev_priv->renderctx)
8480 if (dev_priv->pwrctx == NULL)
8481 dev_priv->pwrctx = intel_alloc_context_page(dev);
8482 if (!dev_priv->pwrctx) {
8483 ironlake_teardown_rc6(dev);
8490 void ironlake_enable_rc6(struct drm_device *dev)
8492 struct drm_i915_private *dev_priv = dev->dev_private;
8495 /* rc6 disabled by default due to repeated reports of hanging during
8498 if (!intel_enable_rc6(dev))
8501 mutex_lock(&dev->struct_mutex);
8502 ret = ironlake_setup_rc6(dev);
8504 mutex_unlock(&dev->struct_mutex);
8509 * GPU can automatically power down the render unit if given a page
8512 ret = BEGIN_LP_RING(6);
8514 ironlake_teardown_rc6(dev);
8515 mutex_unlock(&dev->struct_mutex);
8519 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8520 OUT_RING(MI_SET_CONTEXT);
8521 OUT_RING(dev_priv->renderctx->gtt_offset |
8523 MI_SAVE_EXT_STATE_EN |
8524 MI_RESTORE_EXT_STATE_EN |
8525 MI_RESTORE_INHIBIT);
8526 OUT_RING(MI_SUSPEND_FLUSH);
8532 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8533 * does an implicit flush, combined with MI_FLUSH above, it should be
8534 * safe to assume that renderctx is valid
8536 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8538 DRM_ERROR("failed to enable ironlake power power savings\n");
8539 ironlake_teardown_rc6(dev);
8540 mutex_unlock(&dev->struct_mutex);
8544 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8545 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8546 mutex_unlock(&dev->struct_mutex);
8549 void intel_init_clock_gating(struct drm_device *dev)
8551 struct drm_i915_private *dev_priv = dev->dev_private;
8553 dev_priv->display.init_clock_gating(dev);
8555 if (dev_priv->display.init_pch_clock_gating)
8556 dev_priv->display.init_pch_clock_gating(dev);
8559 /* Set up chip specific display functions */
8560 static void intel_init_display(struct drm_device *dev)
8562 struct drm_i915_private *dev_priv = dev->dev_private;
8564 /* We always want a DPMS function */
8565 if (HAS_PCH_SPLIT(dev)) {
8566 dev_priv->display.dpms = ironlake_crtc_dpms;
8567 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8568 dev_priv->display.update_plane = ironlake_update_plane;
8570 dev_priv->display.dpms = i9xx_crtc_dpms;
8571 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8572 dev_priv->display.update_plane = i9xx_update_plane;
8575 if (I915_HAS_FBC(dev)) {
8576 if (HAS_PCH_SPLIT(dev)) {
8577 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8578 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8579 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8580 } else if (IS_GM45(dev)) {
8581 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8582 dev_priv->display.enable_fbc = g4x_enable_fbc;
8583 dev_priv->display.disable_fbc = g4x_disable_fbc;
8584 } else if (IS_CRESTLINE(dev)) {
8585 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8586 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8587 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8589 /* 855GM needs testing */
8592 /* Returns the core display clock speed */
8593 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8594 dev_priv->display.get_display_clock_speed =
8595 i945_get_display_clock_speed;
8596 else if (IS_I915G(dev))
8597 dev_priv->display.get_display_clock_speed =
8598 i915_get_display_clock_speed;
8599 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8600 dev_priv->display.get_display_clock_speed =
8601 i9xx_misc_get_display_clock_speed;
8602 else if (IS_I915GM(dev))
8603 dev_priv->display.get_display_clock_speed =
8604 i915gm_get_display_clock_speed;
8605 else if (IS_I865G(dev))
8606 dev_priv->display.get_display_clock_speed =
8607 i865_get_display_clock_speed;
8608 else if (IS_I85X(dev))
8609 dev_priv->display.get_display_clock_speed =
8610 i855_get_display_clock_speed;
8612 dev_priv->display.get_display_clock_speed =
8613 i830_get_display_clock_speed;
8615 /* For FIFO watermark updates */
8616 if (HAS_PCH_SPLIT(dev)) {
8617 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8618 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8620 /* IVB configs may use multi-threaded forcewake */
8621 if (IS_IVYBRIDGE(dev)) {
8624 mutex_lock(&dev->struct_mutex);
8625 __gen6_gt_force_wake_mt_get(dev_priv);
8626 ecobus = I915_READ(ECOBUS);
8627 __gen6_gt_force_wake_mt_put(dev_priv);
8628 mutex_unlock(&dev->struct_mutex);
8630 if (ecobus & FORCEWAKE_MT_ENABLE) {
8631 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8632 dev_priv->display.force_wake_get =
8633 __gen6_gt_force_wake_mt_get;
8634 dev_priv->display.force_wake_put =
8635 __gen6_gt_force_wake_mt_put;
8639 if (HAS_PCH_IBX(dev))
8640 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8641 else if (HAS_PCH_CPT(dev))
8642 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8645 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8646 dev_priv->display.update_wm = ironlake_update_wm;
8648 DRM_DEBUG_KMS("Failed to get proper latency. "
8650 dev_priv->display.update_wm = NULL;
8652 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8653 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8654 dev_priv->display.write_eld = ironlake_write_eld;
8655 } else if (IS_GEN6(dev)) {
8656 if (SNB_READ_WM0_LATENCY()) {
8657 dev_priv->display.update_wm = sandybridge_update_wm;
8659 DRM_DEBUG_KMS("Failed to read display plane latency. "
8661 dev_priv->display.update_wm = NULL;
8663 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8664 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8665 dev_priv->display.write_eld = ironlake_write_eld;
8666 } else if (IS_IVYBRIDGE(dev)) {
8667 /* FIXME: detect B0+ stepping and use auto training */
8668 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8669 if (SNB_READ_WM0_LATENCY()) {
8670 dev_priv->display.update_wm = sandybridge_update_wm;
8672 DRM_DEBUG_KMS("Failed to read display plane latency. "
8674 dev_priv->display.update_wm = NULL;
8676 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8677 dev_priv->display.write_eld = ironlake_write_eld;
8679 dev_priv->display.update_wm = NULL;
8680 } else if (IS_PINEVIEW(dev)) {
8681 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8684 dev_priv->mem_freq)) {
8685 DRM_INFO("failed to find known CxSR latency "
8686 "(found ddr%s fsb freq %d, mem freq %d), "
8688 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8689 dev_priv->fsb_freq, dev_priv->mem_freq);
8690 /* Disable CxSR and never update its watermark again */
8691 pineview_disable_cxsr(dev);
8692 dev_priv->display.update_wm = NULL;
8694 dev_priv->display.update_wm = pineview_update_wm;
8695 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8696 } else if (IS_G4X(dev)) {
8697 dev_priv->display.write_eld = g4x_write_eld;
8698 dev_priv->display.update_wm = g4x_update_wm;
8699 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8700 } else if (IS_GEN4(dev)) {
8701 dev_priv->display.update_wm = i965_update_wm;
8702 if (IS_CRESTLINE(dev))
8703 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8704 else if (IS_BROADWATER(dev))
8705 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8706 } else if (IS_GEN3(dev)) {
8707 dev_priv->display.update_wm = i9xx_update_wm;
8708 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8709 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8710 } else if (IS_I865G(dev)) {
8711 dev_priv->display.update_wm = i830_update_wm;
8712 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8713 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8714 } else if (IS_I85X(dev)) {
8715 dev_priv->display.update_wm = i9xx_update_wm;
8716 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8717 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8719 dev_priv->display.update_wm = i830_update_wm;
8720 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8722 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8724 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8727 /* Default just returns -ENODEV to indicate unsupported */
8728 dev_priv->display.queue_flip = intel_default_queue_flip;
8730 switch (INTEL_INFO(dev)->gen) {
8732 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8736 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8741 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8745 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8748 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8754 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8755 * resume, or other times. This quirk makes sure that's the case for
8758 static void quirk_pipea_force(struct drm_device *dev)
8760 struct drm_i915_private *dev_priv = dev->dev_private;
8762 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8763 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8767 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8769 static void quirk_ssc_force_disable(struct drm_device *dev)
8771 struct drm_i915_private *dev_priv = dev->dev_private;
8772 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8775 struct intel_quirk {
8777 int subsystem_vendor;
8778 int subsystem_device;
8779 void (*hook)(struct drm_device *dev);
8782 struct intel_quirk intel_quirks[] = {
8783 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8784 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8785 /* HP Mini needs pipe A force quirk (LP: #322104) */
8786 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8788 /* Thinkpad R31 needs pipe A force quirk */
8789 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8790 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8791 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8793 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8794 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8795 /* ThinkPad X40 needs pipe A force quirk */
8797 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8798 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8800 /* 855 & before need to leave pipe A & dpll A up */
8801 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8802 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8804 /* Lenovo U160 cannot use SSC on LVDS */
8805 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8807 /* Sony Vaio Y cannot use SSC on LVDS */
8808 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8811 static void intel_init_quirks(struct drm_device *dev)
8813 struct pci_dev *d = dev->pdev;
8816 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8817 struct intel_quirk *q = &intel_quirks[i];
8819 if (d->device == q->device &&
8820 (d->subsystem_vendor == q->subsystem_vendor ||
8821 q->subsystem_vendor == PCI_ANY_ID) &&
8822 (d->subsystem_device == q->subsystem_device ||
8823 q->subsystem_device == PCI_ANY_ID))
8828 /* Disable the VGA plane that we never use */
8829 static void i915_disable_vga(struct drm_device *dev)
8831 struct drm_i915_private *dev_priv = dev->dev_private;
8835 if (HAS_PCH_SPLIT(dev))
8836 vga_reg = CPU_VGACNTRL;
8840 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8841 outb(1, VGA_SR_INDEX);
8842 sr1 = inb(VGA_SR_DATA);
8843 outb(sr1 | 1<<5, VGA_SR_DATA);
8844 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8847 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8848 POSTING_READ(vga_reg);
8851 void intel_modeset_init(struct drm_device *dev)
8853 struct drm_i915_private *dev_priv = dev->dev_private;
8856 drm_mode_config_init(dev);
8858 dev->mode_config.min_width = 0;
8859 dev->mode_config.min_height = 0;
8861 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8863 intel_init_quirks(dev);
8865 intel_init_display(dev);
8868 dev->mode_config.max_width = 2048;
8869 dev->mode_config.max_height = 2048;
8870 } else if (IS_GEN3(dev)) {
8871 dev->mode_config.max_width = 4096;
8872 dev->mode_config.max_height = 4096;
8874 dev->mode_config.max_width = 8192;
8875 dev->mode_config.max_height = 8192;
8877 dev->mode_config.fb_base = dev->agp->base;
8879 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8880 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8882 for (i = 0; i < dev_priv->num_pipe; i++) {
8883 intel_crtc_init(dev, i);
8886 /* Just disable it once at startup */
8887 i915_disable_vga(dev);
8888 intel_setup_outputs(dev);
8890 intel_init_clock_gating(dev);
8892 if (IS_IRONLAKE_M(dev)) {
8893 ironlake_enable_drps(dev);
8894 intel_init_emon(dev);
8897 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8898 gen6_enable_rps(dev_priv);
8899 gen6_update_ring_freq(dev_priv);
8902 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8903 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8904 (unsigned long)dev);
8907 void intel_modeset_gem_init(struct drm_device *dev)
8909 if (IS_IRONLAKE_M(dev))
8910 ironlake_enable_rc6(dev);
8912 intel_setup_overlay(dev);
8915 void intel_modeset_cleanup(struct drm_device *dev)
8917 struct drm_i915_private *dev_priv = dev->dev_private;
8918 struct drm_crtc *crtc;
8919 struct intel_crtc *intel_crtc;
8921 drm_kms_helper_poll_fini(dev);
8922 mutex_lock(&dev->struct_mutex);
8924 intel_unregister_dsm_handler();
8927 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8928 /* Skip inactive CRTCs */
8932 intel_crtc = to_intel_crtc(crtc);
8933 intel_increase_pllclock(crtc);
8936 intel_disable_fbc(dev);
8938 if (IS_IRONLAKE_M(dev))
8939 ironlake_disable_drps(dev);
8940 if (IS_GEN6(dev) || IS_GEN7(dev))
8941 gen6_disable_rps(dev);
8943 if (IS_IRONLAKE_M(dev))
8944 ironlake_disable_rc6(dev);
8946 mutex_unlock(&dev->struct_mutex);
8948 /* Disable the irq before mode object teardown, for the irq might
8949 * enqueue unpin/hotplug work. */
8950 drm_irq_uninstall(dev);
8951 cancel_work_sync(&dev_priv->hotplug_work);
8952 cancel_work_sync(&dev_priv->rps_work);
8954 /* flush any delayed tasks or pending work */
8955 flush_scheduled_work();
8957 /* Shut off idle work before the crtcs get freed. */
8958 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8959 intel_crtc = to_intel_crtc(crtc);
8960 del_timer_sync(&intel_crtc->idle_timer);
8962 del_timer_sync(&dev_priv->idle_timer);
8963 cancel_work_sync(&dev_priv->idle_work);
8965 drm_mode_config_cleanup(dev);
8969 * Return which encoder is currently attached for connector.
8971 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8973 return &intel_attached_encoder(connector)->base;
8976 void intel_connector_attach_encoder(struct intel_connector *connector,
8977 struct intel_encoder *encoder)
8979 connector->encoder = encoder;
8980 drm_mode_connector_attach_encoder(&connector->base,
8985 * set vga decode state - true == enable VGA decode
8987 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8989 struct drm_i915_private *dev_priv = dev->dev_private;
8992 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8994 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8996 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8997 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9001 #ifdef CONFIG_DEBUG_FS
9002 #include <linux/seq_file.h>
9004 struct intel_display_error_state {
9005 struct intel_cursor_error_state {
9012 struct intel_pipe_error_state {
9024 struct intel_plane_error_state {
9035 struct intel_display_error_state *
9036 intel_display_capture_error_state(struct drm_device *dev)
9038 drm_i915_private_t *dev_priv = dev->dev_private;
9039 struct intel_display_error_state *error;
9042 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9046 for (i = 0; i < 2; i++) {
9047 error->cursor[i].control = I915_READ(CURCNTR(i));
9048 error->cursor[i].position = I915_READ(CURPOS(i));
9049 error->cursor[i].base = I915_READ(CURBASE(i));
9051 error->plane[i].control = I915_READ(DSPCNTR(i));
9052 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9053 error->plane[i].size = I915_READ(DSPSIZE(i));
9054 error->plane[i].pos = I915_READ(DSPPOS(i));
9055 error->plane[i].addr = I915_READ(DSPADDR(i));
9056 if (INTEL_INFO(dev)->gen >= 4) {
9057 error->plane[i].surface = I915_READ(DSPSURF(i));
9058 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9061 error->pipe[i].conf = I915_READ(PIPECONF(i));
9062 error->pipe[i].source = I915_READ(PIPESRC(i));
9063 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9064 error->pipe[i].hblank = I915_READ(HBLANK(i));
9065 error->pipe[i].hsync = I915_READ(HSYNC(i));
9066 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9067 error->pipe[i].vblank = I915_READ(VBLANK(i));
9068 error->pipe[i].vsync = I915_READ(VSYNC(i));
9075 intel_display_print_error_state(struct seq_file *m,
9076 struct drm_device *dev,
9077 struct intel_display_error_state *error)
9081 for (i = 0; i < 2; i++) {
9082 seq_printf(m, "Pipe [%d]:\n", i);
9083 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9084 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9085 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9086 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9087 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9088 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9089 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9090 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9092 seq_printf(m, "Plane [%d]:\n", i);
9093 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9094 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9095 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9096 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9097 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9098 if (INTEL_INFO(dev)->gen >= 4) {
9099 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9100 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9103 seq_printf(m, "Cursor [%d]:\n", i);
9104 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9105 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9106 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);