2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eric Anholt <eric@anholt.net>
34 u8 signature[20]; /**< Always starts with 'VBT$' */
35 u16 version; /**< decimal */
36 u16 header_size; /**< in bytes */
37 u16 vbt_size; /**< in bytes */
40 u32 bdb_offset; /**< from beginning of VBT */
41 u32 aim_offset[4]; /**< from beginning of VBT */
45 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
46 u16 version; /**< decimal */
47 u16 header_size; /**< in bytes */
48 u16 bdb_size; /**< in bytes */
51 /* strictly speaking, this is a "skip" block, but it has interesting info */
53 u8 type; /* 0 == desktop, 1 == mobile */
58 u8 rsvd2:6; /* finish byte */
65 u8 rsvd4; /* popup memory size */
67 u8 rsvd5; /* is crt already on ddc2 */
71 * There are several types of BIOS data blocks (BDBs), each block has
72 * an ID and size in the first 3 bytes (ID in first, size in next 2).
73 * Known types are listed below.
75 #define BDB_GENERAL_FEATURES 1
76 #define BDB_GENERAL_DEFINITIONS 2
77 #define BDB_OLD_TOGGLE_LIST 3
78 #define BDB_MODE_SUPPORT_LIST 4
79 #define BDB_GENERIC_MODE_TABLE 5
80 #define BDB_EXT_MMIO_REGS 6
82 #define BDB_SWF_MMIO 8
83 #define BDB_DOT_CLOCK_TABLE 9
84 #define BDB_MODE_REMOVAL_TABLE 10
85 #define BDB_CHILD_DEVICE_TABLE 11
86 #define BDB_DRIVER_FEATURES 12
87 #define BDB_DRIVER_PERSISTENCE 13
88 #define BDB_EXT_TABLE_PTRS 14
89 #define BDB_DOT_CLOCK_OVERRIDE 15
90 #define BDB_DISPLAY_SELECT 16
92 #define BDB_DRIVER_ROTATION 18
93 #define BDB_DISPLAY_REMOVE 19
94 #define BDB_OEM_CUSTOM 20
95 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
96 #define BDB_SDVO_LVDS_OPTIONS 22
97 #define BDB_SDVO_PANEL_DTDS 23
98 #define BDB_SDVO_LVDS_PNP_IDS 24
99 #define BDB_SDVO_LVDS_POWER_SEQ 25
100 #define BDB_TV_OPTIONS 26
102 #define BDB_LVDS_OPTIONS 40
103 #define BDB_LVDS_LFP_DATA_PTRS 41
104 #define BDB_LVDS_LFP_DATA 42
105 #define BDB_LVDS_BACKLIGHT 43
106 #define BDB_LVDS_POWER 44
107 #define BDB_MIPI_CONFIG 52
108 #define BDB_MIPI_SEQUENCE 53
109 #define BDB_SKIP 254 /* VBIOS private block, ignore */
111 struct bdb_general_features {
120 u8 download_ext_vbt:1;
123 u8 enable_lfp_on_override:1;
124 u8 disable_ssc_ddt:1;
126 u8 display_clock_mode:1;
127 u8 rsvd8:1; /* finish byte */
130 u8 disable_smooth_vision:1;
133 u8 fdi_rx_polarity_inverted:1;
134 u8 rsvd10:4; /* finish byte */
137 u8 legacy_monitor_detect;
140 u8 int_crt_support:1;
142 u8 int_efp_support:1;
143 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
144 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
145 u8 rsvd11:3; /* finish byte */
149 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
150 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
151 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
152 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
155 #define DEVICE_TYPE_NONE 0x00
156 #define DEVICE_TYPE_CRT 0x01
157 #define DEVICE_TYPE_TV 0x09
158 #define DEVICE_TYPE_EFP 0x12
159 #define DEVICE_TYPE_LFP 0x22
161 #define DEVICE_TYPE_CRT_DPMS 0x6001
162 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
163 #define DEVICE_TYPE_TV_COMPOSITE 0x0209
164 #define DEVICE_TYPE_TV_MACROVISION 0x0289
165 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
166 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
167 #define DEVICE_TYPE_TV_SCART 0x0209
168 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
169 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
170 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
171 #define DEVICE_TYPE_EFP_DVI_I 0x6053
172 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
173 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
174 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
175 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
176 #define DEVICE_TYPE_LFP_PANELLINK 0x5012
177 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
178 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
179 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
180 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
182 #define DEVICE_CFG_NONE 0x00
183 #define DEVICE_CFG_12BIT_DVOB 0x01
184 #define DEVICE_CFG_12BIT_DVOC 0x02
185 #define DEVICE_CFG_24BIT_DVOBC 0x09
186 #define DEVICE_CFG_24BIT_DVOCB 0x0a
187 #define DEVICE_CFG_DUAL_DVOB 0x11
188 #define DEVICE_CFG_DUAL_DVOC 0x12
189 #define DEVICE_CFG_DUAL_DVOBC 0x13
190 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
191 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
193 #define DEVICE_WIRE_NONE 0x00
194 #define DEVICE_WIRE_DVOB 0x01
195 #define DEVICE_WIRE_DVOC 0x02
196 #define DEVICE_WIRE_DVOBC 0x03
197 #define DEVICE_WIRE_DVOBB 0x05
198 #define DEVICE_WIRE_DVOCC 0x06
199 #define DEVICE_WIRE_DVOB_MASTER 0x0d
200 #define DEVICE_WIRE_DVOC_MASTER 0x0e
202 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
203 #define DEVICE_PORT_DVOB 0x01
204 #define DEVICE_PORT_DVOC 0x02
206 /* We used to keep this struct but without any version control. We should avoid
207 * using it in the future, but it should be safe to keep using it in the old
209 struct old_child_dev_config {
212 u8 device_id[10]; /* ascii string */
214 u8 dvo_port; /* See Device_PORT_* above */
219 u8 dvo_cfg; /* See DEVICE_CFG_* above */
225 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
231 /* This one contains field offsets that are known to be common for all BDB
232 * versions. Notice that the meaning of the contents contents may still change,
233 * but at least the offsets are consistent. */
234 struct common_child_dev_config {
244 /* This field changes depending on the BDB version, so the most reliable way to
245 * read it is by checking the BDB version and reading the raw pointer. */
246 union child_device_config {
247 /* This one is safe to be used anywhere, but the code should still check
248 * the BDB version. */
250 /* This one should only be kept for legacy code. */
251 struct old_child_dev_config old;
252 /* This one should also be safe to use anywhere, even without version
254 struct common_child_dev_config common;
257 struct bdb_general_definitions {
259 u8 crt_ddc_gmbus_pin;
263 u8 skip_boot_crt_detect:1;
265 u8 rsvd1:5; /* finish byte */
267 /* boot device bits */
273 * If TV is present, it'll be at devices[0].
274 * LVDS will be next, either devices[0] or [1], if present.
275 * On some platforms the number of device is 6. But could be as few as
276 * 4 if both TV and LVDS are missing.
277 * And the device num is related with the size of general definition
278 * block. It is obtained by using the following formula:
279 * number = (block_size - sizeof(bdb_general_definitions))/
280 * sizeof(child_device_config);
282 union child_device_config devices[0];
285 struct bdb_lvds_options {
288 /* LVDS capabilities, stored in a dword */
290 u8 pfit_text_mode_enhanced:1;
291 u8 pfit_gfx_mode_enhanced:1;
292 u8 pfit_ratio_auto:1;
299 /* LFP pointer table contains entries to the struct below */
300 struct bdb_lvds_lfp_data_ptr {
301 u16 fp_timing_offset; /* offsets are from start of bdb */
303 u16 dvo_timing_offset;
305 u16 panel_pnp_id_offset;
309 struct bdb_lvds_lfp_data_ptrs {
310 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
311 struct bdb_lvds_lfp_data_ptr ptr[16];
314 /* LFP data has 3 blocks per entry */
315 struct lvds_fp_timing {
325 u32 pp_cycle_reg_val;
331 struct lvds_dvo_timing {
332 u16 clock; /**< In 10khz */
342 u8 hsync_pulse_width;
343 u8 vsync_pulse_width:4;
367 struct bdb_lvds_lfp_data_entry {
368 struct lvds_fp_timing fp_timing;
369 struct lvds_dvo_timing dvo_timing;
370 struct lvds_pnp_id pnp_id;
373 struct bdb_lvds_lfp_data {
374 struct bdb_lvds_lfp_data_entry data[16];
377 #define BDB_BACKLIGHT_TYPE_NONE 0
378 #define BDB_BACKLIGHT_TYPE_PWM 2
380 struct bdb_lfp_backlight_data_entry {
390 struct bdb_lfp_backlight_data {
392 struct bdb_lfp_backlight_data_entry data[16];
396 struct aimdb_header {
400 u16 aimdb_header_size;
409 struct vch_panel_data {
410 u16 fp_timing_offset;
412 u16 dvo_timing_offset;
414 u16 text_fitting_offset;
415 u8 text_fitting_size;
416 u16 graphics_fitting_offset;
417 u8 graphics_fitting_size;
421 struct aimdb_block aimdb_block;
422 struct vch_panel_data panels[16];
425 struct bdb_sdvo_lvds_options {
427 u8 h40_set_panel_type;
432 u8 sclalarcoeff_tab_row_num;
433 u8 sclalarcoeff_tab_row_size;
435 u8 panel_misc_bits_1;
436 u8 panel_misc_bits_2;
437 u8 panel_misc_bits_3;
438 u8 panel_misc_bits_4;
442 #define BDB_DRIVER_FEATURE_NO_LVDS 0
443 #define BDB_DRIVER_FEATURE_INT_LVDS 1
444 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
445 #define BDB_DRIVER_FEATURE_EDP 3
447 struct bdb_driver_features {
448 u8 boot_dev_algorithm:1;
449 u8 block_display_switch:1;
450 u8 allow_display_switch:1;
454 u8 sprite_in_clone:1;
460 u8 boot_mode_refresh;
462 u16 enable_lfp_primary:1;
463 u16 selective_mode_pruning:1;
464 u16 dual_frequency:1;
465 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
466 u16 nt_clone_support:1;
467 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
468 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
469 u16 cui_aspect_scaling:1;
470 u16 preserve_aspect_ratio:1;
471 u16 sdvo_device_power_down:1;
479 u16 legacy_crt_max_x;
480 u16 legacy_crt_max_y;
481 u8 legacy_crt_max_refresh;
484 u8 custom_vbt_version;
490 #define EDP_RATE_1_62 0
491 #define EDP_RATE_2_7 1
495 #define EDP_PREEMPHASIS_NONE 0
496 #define EDP_PREEMPHASIS_3_5dB 1
497 #define EDP_PREEMPHASIS_6dB 2
498 #define EDP_PREEMPHASIS_9_5dB 3
499 #define EDP_VSWING_0_4V 0
500 #define EDP_VSWING_0_6V 1
501 #define EDP_VSWING_0_8V 2
502 #define EDP_VSWING_1_2V 3
504 struct edp_power_seq {
512 struct edp_link_params {
520 struct edp_power_seq power_seqs[16];
522 struct edp_link_params link_params[16];
523 u32 sdrrs_msa_timing_delay;
525 /* ith bit indicates enabled/disabled for (i+1)th panel */
527 u16 edp_t3_optimization;
530 void intel_setup_bios(struct drm_device *dev);
531 int intel_parse_bios(struct drm_device *dev);
534 * Driver<->VBIOS interaction occurs through scratch bits in
538 /* GR18 bits are set on display switch and hotkey events */
539 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
540 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
541 #define GR18_HK_NONE (0x0<<3)
542 #define GR18_HK_LFP_STRETCH (0x1<<3)
543 #define GR18_HK_TOGGLE_DISP (0x2<<3)
544 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
545 #define GR18_HK_POPUP_DISABLED (0x6<<3)
546 #define GR18_HK_POPUP_ENABLED (0x7<<3)
547 #define GR18_HK_PFIT (0x8<<3)
548 #define GR18_HK_APM_CHANGE (0xa<<3)
549 #define GR18_HK_MULTIPLE (0xc<<3)
550 #define GR18_USER_INT_EN (1<<2)
551 #define GR18_A0000_FLUSH_EN (1<<1)
552 #define GR18_SMM_EN (1<<0)
554 /* Set by driver, cleared by VBIOS */
555 #define SWF00_YRES_SHIFT 16
556 #define SWF00_XRES_SHIFT 0
557 #define SWF00_RES_MASK 0xffff
559 /* Set by VBIOS at boot time and driver at runtime */
560 #define SWF01_TV2_FORMAT_SHIFT 8
561 #define SWF01_TV1_FORMAT_SHIFT 0
562 #define SWF01_TV_FORMAT_MASK 0xffff
564 #define SWF10_VBIOS_BLC_I2C_EN (1<<29)
565 #define SWF10_GTT_OVERRIDE_EN (1<<28)
566 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
567 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
568 #define SWF10_OLD_TOGGLE 0x0
569 #define SWF10_TOGGLE_LIST_1 0x1
570 #define SWF10_TOGGLE_LIST_2 0x2
571 #define SWF10_TOGGLE_LIST_3 0x3
572 #define SWF10_TOGGLE_LIST_4 0x4
573 #define SWF10_PANNING_EN (1<<23)
574 #define SWF10_DRIVER_LOADED (1<<22)
575 #define SWF10_EXTENDED_DESKTOP (1<<21)
576 #define SWF10_EXCLUSIVE_MODE (1<<20)
577 #define SWF10_OVERLAY_EN (1<<19)
578 #define SWF10_PLANEB_HOLDOFF (1<<18)
579 #define SWF10_PLANEA_HOLDOFF (1<<17)
580 #define SWF10_VGA_HOLDOFF (1<<16)
581 #define SWF10_ACTIVE_DISP_MASK 0xffff
582 #define SWF10_PIPEB_LFP2 (1<<15)
583 #define SWF10_PIPEB_EFP2 (1<<14)
584 #define SWF10_PIPEB_TV2 (1<<13)
585 #define SWF10_PIPEB_CRT2 (1<<12)
586 #define SWF10_PIPEB_LFP (1<<11)
587 #define SWF10_PIPEB_EFP (1<<10)
588 #define SWF10_PIPEB_TV (1<<9)
589 #define SWF10_PIPEB_CRT (1<<8)
590 #define SWF10_PIPEA_LFP2 (1<<7)
591 #define SWF10_PIPEA_EFP2 (1<<6)
592 #define SWF10_PIPEA_TV2 (1<<5)
593 #define SWF10_PIPEA_CRT2 (1<<4)
594 #define SWF10_PIPEA_LFP (1<<3)
595 #define SWF10_PIPEA_EFP (1<<2)
596 #define SWF10_PIPEA_TV (1<<1)
597 #define SWF10_PIPEA_CRT (1<<0)
599 #define SWF11_MEMORY_SIZE_SHIFT 16
600 #define SWF11_SV_TEST_EN (1<<15)
601 #define SWF11_IS_AGP (1<<14)
602 #define SWF11_DISPLAY_HOLDOFF (1<<13)
603 #define SWF11_DPMS_REDUCED (1<<12)
604 #define SWF11_IS_VBE_MODE (1<<11)
605 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
606 #define SWF11_DPMS_MASK 0x07
607 #define SWF11_DPMS_OFF (1<<2)
608 #define SWF11_DPMS_SUSPEND (1<<1)
609 #define SWF11_DPMS_STANDBY (1<<0)
610 #define SWF11_DPMS_ON 0
612 #define SWF14_GFX_PFIT_EN (1<<31)
613 #define SWF14_TEXT_PFIT_EN (1<<30)
614 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
615 #define SWF14_POPUP_EN (1<<28)
616 #define SWF14_DISPLAY_HOLDOFF (1<<27)
617 #define SWF14_DISP_DETECT_EN (1<<26)
618 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
619 #define SWF14_DRIVER_STATUS (1<<24)
620 #define SWF14_OS_TYPE_WIN9X (1<<23)
621 #define SWF14_OS_TYPE_WINNT (1<<22)
623 #define SWF14_PM_TYPE_MASK 0x00070000
624 #define SWF14_PM_ACPI_VIDEO (0x4 << 16)
625 #define SWF14_PM_ACPI (0x3 << 16)
626 #define SWF14_PM_APM_12 (0x2 << 16)
627 #define SWF14_PM_APM_11 (0x1 << 16)
628 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
629 /* if GR18 indicates a display switch */
630 #define SWF14_DS_PIPEB_LFP2_EN (1<<15)
631 #define SWF14_DS_PIPEB_EFP2_EN (1<<14)
632 #define SWF14_DS_PIPEB_TV2_EN (1<<13)
633 #define SWF14_DS_PIPEB_CRT2_EN (1<<12)
634 #define SWF14_DS_PIPEB_LFP_EN (1<<11)
635 #define SWF14_DS_PIPEB_EFP_EN (1<<10)
636 #define SWF14_DS_PIPEB_TV_EN (1<<9)
637 #define SWF14_DS_PIPEB_CRT_EN (1<<8)
638 #define SWF14_DS_PIPEA_LFP2_EN (1<<7)
639 #define SWF14_DS_PIPEA_EFP2_EN (1<<6)
640 #define SWF14_DS_PIPEA_TV2_EN (1<<5)
641 #define SWF14_DS_PIPEA_CRT2_EN (1<<4)
642 #define SWF14_DS_PIPEA_LFP_EN (1<<3)
643 #define SWF14_DS_PIPEA_EFP_EN (1<<2)
644 #define SWF14_DS_PIPEA_TV_EN (1<<1)
645 #define SWF14_DS_PIPEA_CRT_EN (1<<0)
646 /* if GR18 indicates a panel fitting request */
647 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */
648 /* if GR18 indicates an APM change request */
649 #define SWF14_APM_HIBERNATE 0x4
650 #define SWF14_APM_SUSPEND 0x3
651 #define SWF14_APM_STANDBY 0x1
652 #define SWF14_APM_RESTORE 0x0
654 /* Add the device class for LFP, TV, HDMI */
655 #define DEVICE_TYPE_INT_LFP 0x1022
656 #define DEVICE_TYPE_INT_TV 0x1009
657 #define DEVICE_TYPE_HDMI 0x60D2
658 #define DEVICE_TYPE_DP 0x68C6
659 #define DEVICE_TYPE_eDP 0x78C6
661 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
662 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
663 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
664 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
665 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
666 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
667 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
668 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
669 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
670 #define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
671 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
672 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
673 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
674 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
675 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
678 * Bits we care about when checking for DEVICE_TYPE_eDP
679 * Depending on the system, the other bits may or may not
680 * be set for eDP outputs.
682 #define DEVICE_TYPE_eDP_BITS \
683 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
684 DEVICE_TYPE_NOT_HDMI_OUTPUT | \
685 DEVICE_TYPE_MIPI_OUTPUT | \
686 DEVICE_TYPE_COMPOSITE_OUTPUT | \
687 DEVICE_TYPE_DUAL_CHANNEL | \
688 DEVICE_TYPE_LVDS_SINGALING | \
689 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
690 DEVICE_TYPE_VIDEO_SIGNALING | \
691 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
692 DEVICE_TYPE_DIGITAL_OUTPUT | \
693 DEVICE_TYPE_ANALOG_OUTPUT)
695 /* define the DVO port for HDMI output type */
700 /* define the PORT for DP output type */
705 /* Possible values for the "DVO Port" field for versions >= 155: */
706 #define DVO_PORT_HDMIA 0
707 #define DVO_PORT_HDMIB 1
708 #define DVO_PORT_HDMIC 2
709 #define DVO_PORT_HDMID 3
710 #define DVO_PORT_LVDS 4
711 #define DVO_PORT_TV 5
712 #define DVO_PORT_CRT 6
713 #define DVO_PORT_DPB 7
714 #define DVO_PORT_DPC 8
715 #define DVO_PORT_DPD 9
716 #define DVO_PORT_DPA 10
718 /* Block 52 contains MIPI Panel info
719 * 6 such enteries will there. Index into correct
720 * entery is based on the panel_index in #40 LFP
722 #define MAX_MIPI_CONFIGURATIONS 6
724 #define MIPI_DSI_UNDEFINED_PANEL_ID 0
725 #define MIPI_DSI_GENERIC_PANEL_ID 1
731 u32 enable_dithering:1;
735 u32 panel_arch_type:2;
738 #define NON_BURST_SYNC_PULSE 0x1
739 #define NON_BURST_SYNC_EVENTS 0x2
740 #define BURST_MODE 0x3
741 u32 video_transfer_mode:2;
743 u32 cabc_supported:1;
747 #define PIXEL_FORMAT_RGB565 0x1
748 #define PIXEL_FORMAT_RGB666 0x2
749 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
750 #define PIXEL_FORMAT_RGB888 0x4
751 u32 videomode_color_format:4;
754 #define ENABLE_ROTATION_0 0x0
755 #define ENABLE_ROTATION_90 0x1
756 #define ENABLE_ROTATION_180 0x2
757 #define ENABLE_ROTATION_270 0x3
762 /* 2 byte Port Description */
763 #define DUAL_LINK_NOT_SUPPORTED 0
764 #define DUAL_LINK_FRONT_BACK 1
765 #define DUAL_LINK_PIXEL_ALT 2
776 #define BYTE_CLK_SEL_20MHZ 0
777 #define BYTE_CLK_SEL_10MHZ 1
778 #define BYTE_CLK_SEL_5MHZ 2
784 u16 dphy_param_valid:1;
785 u16 eot_pkt_disabled:1;
786 u16 enable_clk_stop:1;
791 u32 turn_around_timeout;
792 u32 device_reset_timer;
793 u32 master_init_timer;
797 /* 4 byte Dphy Params */
806 u32 clk_lane_switch_cnt;
811 /* timings based on dphy spec */
820 u16 tclk_prepare_clkzero;
826 u16 ths_prepare_hszero;
845 /* Block 52 contains MIPI configuration block
846 * 6 * bdb_mipi_config, followed by 6 pps data
849 * all delays has a unit of 100us
851 struct mipi_pps_data {
854 u16 bl_disable_delay;
856 u16 panel_power_cycle_delay;
859 struct bdb_mipi_config {
860 struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
861 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
864 /* Block 53 contains MIPI sequences as needed by the panel
865 * for enabling it. This block can be variable in size and
866 * can be maximum of 6 blocks
868 struct bdb_mipi_sequence {
873 #endif /* _I830_BIOS_H_ */