1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_ENABLED 0x4
34 #define INTEL_GMCH_MEM_MASK 0x1
35 #define INTEL_GMCH_MEM_64M 0x1
36 #define INTEL_GMCH_MEM_128M 0
38 #define INTEL_GMCH_GMS_MASK (0xf << 4)
39 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
40 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
46 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
48 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
51 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
52 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
53 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
55 /* PCI config space */
57 #define HPLLCC 0xc0 /* 855 only */
58 #define GC_CLOCK_CONTROL_MASK (3 << 0)
59 #define GC_CLOCK_133_200 (0 << 0)
60 #define GC_CLOCK_100_200 (1 << 0)
61 #define GC_CLOCK_100_133 (2 << 0)
62 #define GC_CLOCK_166_250 (3 << 0)
63 #define GCFGC 0xf0 /* 915+ only */
64 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
65 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
66 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
67 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
72 #define VGA_ST01_MDA 0x3ba
73 #define VGA_ST01_CGA 0x3da
75 #define VGA_MSR_WRITE 0x3c2
76 #define VGA_MSR_READ 0x3cc
77 #define VGA_MSR_MEM_EN (1<<1)
78 #define VGA_MSR_CGA_MODE (1<<0)
80 #define VGA_SR_INDEX 0x3c4
81 #define VGA_SR_DATA 0x3c5
83 #define VGA_AR_INDEX 0x3c0
84 #define VGA_AR_VID_EN (1<<5)
85 #define VGA_AR_DATA_WRITE 0x3c0
86 #define VGA_AR_DATA_READ 0x3c1
88 #define VGA_GR_INDEX 0x3ce
89 #define VGA_GR_DATA 0x3cf
91 #define VGA_GR_MEM_READ_MODE_SHIFT 3
92 #define VGA_GR_MEM_READ_MODE_PLANE 1
94 #define VGA_GR_MEM_MODE_MASK 0xc
95 #define VGA_GR_MEM_MODE_SHIFT 2
96 #define VGA_GR_MEM_A0000_AFFFF 0
97 #define VGA_GR_MEM_A0000_BFFFF 1
98 #define VGA_GR_MEM_B0000_B7FFF 2
99 #define VGA_GR_MEM_B0000_BFFFF 3
101 #define VGA_DACMASK 0x3c6
102 #define VGA_DACRX 0x3c7
103 #define VGA_DACWX 0x3c8
104 #define VGA_DACDATA 0x3c9
106 #define VGA_CR_INDEX_MDA 0x3b4
107 #define VGA_CR_DATA_MDA 0x3b5
108 #define VGA_CR_INDEX_CGA 0x3d4
109 #define VGA_CR_DATA_CGA 0x3d5
112 * Memory interface instructions used by the kernel
114 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
116 #define MI_NOOP MI_INSTR(0, 0)
117 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
118 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
119 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
120 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
121 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
122 #define MI_FLUSH MI_INSTR(0x04, 0)
123 #define MI_READ_FLUSH (1 << 0)
124 #define MI_EXE_FLUSH (1 << 1)
125 #define MI_NO_WRITE_FLUSH (1 << 2)
126 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
127 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
128 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
129 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
130 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
131 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
132 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
133 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
134 #define MI_STORE_DWORD_INDEX_SHIFT 2
135 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
136 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
137 #define MI_BATCH_NON_SECURE (1)
138 #define MI_BATCH_NON_SECURE_I965 (1<<8)
139 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
142 * 3D instructions used by the kernel
144 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
146 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
147 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
148 #define SC_UPDATE_SCISSOR (0x1<<1)
149 #define SC_ENABLE_MASK (0x1<<0)
150 #define SC_ENABLE (0x1<<0)
151 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
152 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
153 #define SCI_YMIN_MASK (0xffff<<16)
154 #define SCI_XMIN_MASK (0xffff<<0)
155 #define SCI_YMAX_MASK (0xffff<<16)
156 #define SCI_XMAX_MASK (0xffff<<0)
157 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
158 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
159 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
160 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
161 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
162 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
163 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
164 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
165 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
166 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
167 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
168 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
169 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
170 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
171 #define BLT_DEPTH_8 (0<<24)
172 #define BLT_DEPTH_16_565 (1<<24)
173 #define BLT_DEPTH_16_1555 (2<<24)
174 #define BLT_DEPTH_32 (3<<24)
175 #define BLT_ROP_GXCOPY (0xcc<<16)
176 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
177 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
178 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
179 #define ASYNC_FLIP (1<<22)
180 #define DISPLAY_PLANE_A (0<<20)
181 #define DISPLAY_PLANE_B (1<<20)
186 #define FENCE_REG_830_0 0x2000
187 #define FENCE_REG_945_8 0x3000
188 #define I830_FENCE_START_MASK 0x07f80000
189 #define I830_FENCE_TILING_Y_SHIFT 12
190 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
191 #define I830_FENCE_PITCH_SHIFT 4
192 #define I830_FENCE_REG_VALID (1<<0)
193 #define I915_FENCE_MAX_PITCH_VAL 0x10
194 #define I830_FENCE_MAX_PITCH_VAL 6
195 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
197 #define I915_FENCE_START_MASK 0x0ff00000
198 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
200 #define FENCE_REG_965_0 0x03000
201 #define I965_FENCE_PITCH_SHIFT 2
202 #define I965_FENCE_TILING_Y_SHIFT 1
203 #define I965_FENCE_REG_VALID (1<<0)
204 #define I965_FENCE_MAX_PITCH_VAL 0x0400
207 * Instruction and interrupt control regs
209 #define PRB0_TAIL 0x02030
210 #define PRB0_HEAD 0x02034
211 #define PRB0_START 0x02038
212 #define PRB0_CTL 0x0203c
213 #define TAIL_ADDR 0x001FFFF8
214 #define HEAD_WRAP_COUNT 0xFFE00000
215 #define HEAD_WRAP_ONE 0x00200000
216 #define HEAD_ADDR 0x001FFFFC
217 #define RING_NR_PAGES 0x001FF000
218 #define RING_REPORT_MASK 0x00000006
219 #define RING_REPORT_64K 0x00000002
220 #define RING_REPORT_128K 0x00000004
221 #define RING_NO_REPORT 0x00000000
222 #define RING_VALID_MASK 0x00000001
223 #define RING_VALID 0x00000001
224 #define RING_INVALID 0x00000000
225 #define PRB1_TAIL 0x02040 /* 915+ only */
226 #define PRB1_HEAD 0x02044 /* 915+ only */
227 #define PRB1_START 0x02048 /* 915+ only */
228 #define PRB1_CTL 0x0204c /* 915+ only */
229 #define ACTHD_I965 0x02074
230 #define HWS_PGA 0x02080
231 #define HWS_ADDRESS_MASK 0xfffff000
232 #define HWS_START_ADDRESS_SHIFT 4
233 #define IPEIR 0x02088
234 #define NOPID 0x02094
235 #define HWSTAM 0x02098
236 #define SCPD0 0x0209c /* 915+ only */
241 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
242 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
243 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
244 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
245 #define I915_HWB_OOM_INTERRUPT (1<<13)
246 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
247 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
248 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
249 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
250 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
251 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
252 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
253 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
254 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
255 #define I915_DEBUG_INTERRUPT (1<<2)
256 #define I915_USER_INTERRUPT (1<<1)
257 #define I915_ASLE_INTERRUPT (1<<0)
261 #define INSTPM 0x020c0
262 #define ACTHD 0x020c8
263 #define FW_BLC 0x020d8
264 #define FW_BLC_SELF 0x020e0 /* 915+ only */
265 #define MI_ARB_STATE 0x020e4 /* 915+ only */
266 #define CACHE_MODE_0 0x02120 /* 915+ only */
267 #define CM0_MASK_SHIFT 16
268 #define CM0_IZ_OPT_DISABLE (1<<6)
269 #define CM0_ZR_OPT_DISABLE (1<<5)
270 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
271 #define CM0_COLOR_EVICT_DISABLE (1<<3)
272 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
273 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
274 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
278 * Framebuffer compression (915+ only)
281 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
282 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
283 #define FBC_CONTROL 0x03208
284 #define FBC_CTL_EN (1<<31)
285 #define FBC_CTL_PERIODIC (1<<30)
286 #define FBC_CTL_INTERVAL_SHIFT (16)
287 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
288 #define FBC_CTL_STRIDE_SHIFT (5)
289 #define FBC_CTL_FENCENO (1<<0)
290 #define FBC_COMMAND 0x0320c
291 #define FBC_CMD_COMPRESS (1<<0)
292 #define FBC_STATUS 0x03210
293 #define FBC_STAT_COMPRESSING (1<<31)
294 #define FBC_STAT_COMPRESSED (1<<30)
295 #define FBC_STAT_MODIFIED (1<<29)
296 #define FBC_STAT_CURRENT_LINE (1<<0)
297 #define FBC_CONTROL2 0x03214
298 #define FBC_CTL_FENCE_DBL (0<<4)
299 #define FBC_CTL_IDLE_IMM (0<<2)
300 #define FBC_CTL_IDLE_FULL (1<<2)
301 #define FBC_CTL_IDLE_LINE (2<<2)
302 #define FBC_CTL_IDLE_DEBUG (3<<2)
303 #define FBC_CTL_CPU_FENCE (1<<1)
304 #define FBC_CTL_PLANEA (0<<0)
305 #define FBC_CTL_PLANEB (1<<0)
306 #define FBC_FENCE_OFF 0x0321b
308 #define FBC_LL_SIZE (1536)
321 # define GPIO_CLOCK_DIR_MASK (1 << 0)
322 # define GPIO_CLOCK_DIR_IN (0 << 1)
323 # define GPIO_CLOCK_DIR_OUT (1 << 1)
324 # define GPIO_CLOCK_VAL_MASK (1 << 2)
325 # define GPIO_CLOCK_VAL_OUT (1 << 3)
326 # define GPIO_CLOCK_VAL_IN (1 << 4)
327 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
328 # define GPIO_DATA_DIR_MASK (1 << 8)
329 # define GPIO_DATA_DIR_IN (0 << 9)
330 # define GPIO_DATA_DIR_OUT (1 << 9)
331 # define GPIO_DATA_VAL_MASK (1 << 10)
332 # define GPIO_DATA_VAL_OUT (1 << 11)
333 # define GPIO_DATA_VAL_IN (1 << 12)
334 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
337 * Clock control & power management
342 #define VGA_PD 0x6010
343 #define VGA0_PD_P2_DIV_4 (1 << 7)
344 #define VGA0_PD_P1_DIV_2 (1 << 5)
345 #define VGA0_PD_P1_SHIFT 0
346 #define VGA0_PD_P1_MASK (0x1f << 0)
347 #define VGA1_PD_P2_DIV_4 (1 << 15)
348 #define VGA1_PD_P1_DIV_2 (1 << 13)
349 #define VGA1_PD_P1_SHIFT 8
350 #define VGA1_PD_P1_MASK (0x1f << 8)
351 #define DPLL_A 0x06014
352 #define DPLL_B 0x06018
353 #define DPLL_VCO_ENABLE (1 << 31)
354 #define DPLL_DVO_HIGH_SPEED (1 << 30)
355 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
356 #define DPLL_VGA_MODE_DIS (1 << 28)
357 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
358 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
359 #define DPLL_MODE_MASK (3 << 26)
360 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
361 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
362 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
363 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
364 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
365 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
366 #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
368 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
369 #define I915_CRC_ERROR_ENABLE (1UL<<29)
370 #define I915_CRC_DONE_ENABLE (1UL<<28)
371 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
372 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
373 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
374 #define I915_DPST_EVENT_ENABLE (1UL<<23)
375 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
376 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
377 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
378 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
379 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
380 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
381 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
382 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
383 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
384 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
385 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
386 #define I915_DPST_EVENT_STATUS (1UL<<7)
387 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
388 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
389 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
390 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
391 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
392 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
394 #define SRX_INDEX 0x3c4
395 #define SRX_DATA 0x3c5
397 #define SR01_SCREEN_OFF (1<<5)
400 #define PPCR_ON (1<<0)
403 #define DVOB_ON (1<<31)
405 #define DVOC_ON (1<<31)
407 #define LVDS_ON (1<<31)
410 #define ADPA_DPMS_MASK (~(3<<10))
411 #define ADPA_DPMS_ON (0<<10)
412 #define ADPA_DPMS_SUSPEND (1<<10)
413 #define ADPA_DPMS_STANDBY (2<<10)
414 #define ADPA_DPMS_OFF (3<<10)
416 #define RING_TAIL 0x00
417 #define TAIL_ADDR 0x001FFFF8
418 #define RING_HEAD 0x04
419 #define HEAD_WRAP_COUNT 0xFFE00000
420 #define HEAD_WRAP_ONE 0x00200000
421 #define HEAD_ADDR 0x001FFFFC
422 #define RING_START 0x08
423 #define START_ADDR 0xFFFFF000
424 #define RING_LEN 0x0C
425 #define RING_NR_PAGES 0x001FF000
426 #define RING_REPORT_MASK 0x00000006
427 #define RING_REPORT_64K 0x00000002
428 #define RING_REPORT_128K 0x00000004
429 #define RING_NO_REPORT 0x00000000
430 #define RING_VALID_MASK 0x00000001
431 #define RING_VALID 0x00000001
432 #define RING_INVALID 0x00000000
434 /* Scratch pad debug 0 reg:
436 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
438 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
439 * this field (only one bit may be set).
441 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
442 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
443 #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
444 /* i830, required in DVO non-gang */
445 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
446 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
447 #define PLL_REF_INPUT_DREFCLK (0 << 13)
448 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
449 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
450 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
451 #define PLL_REF_INPUT_MASK (3 << 13)
452 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
454 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
455 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
456 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
457 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
458 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
461 * Parallel to Serial Load Pulse phase selection.
462 * Selects the phase for the 10X DPLL clock for the PCIe
463 * digital display port. The range is 4 to 13; 10 or more
464 * is just a flip delay. The default is 6
466 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
467 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
469 * SDVO multiplier for 945G/GM. Not used on 965.
471 #define SDVO_MULTIPLIER_MASK 0x000000ff
472 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
473 #define SDVO_MULTIPLIER_SHIFT_VGA 0
474 #define DPLL_A_MD 0x0601c /* 965+ only */
476 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
478 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
480 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
481 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
482 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
483 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
484 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
486 * SDVO/UDI pixel multiplier.
488 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
489 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
490 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
491 * dummy bytes in the datastream at an increased clock rate, with both sides of
492 * the link knowing how many bytes are fill.
494 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
495 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
496 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
497 * through an SDVO command.
499 * This register field has values of multiplication factor minus 1, with
500 * a maximum multiplier of 5 for SDVO.
502 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
503 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
505 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
506 * This best be set to the default value (3) or the CRT won't work. No,
507 * I don't entirely understand what this does...
509 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
510 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
511 #define DPLL_B_MD 0x06020 /* 965+ only */
516 #define FP_N_DIV_MASK 0x003f0000
517 #define FP_N_IGD_DIV_MASK 0x00ff0000
518 #define FP_N_DIV_SHIFT 16
519 #define FP_M1_DIV_MASK 0x00003f00
520 #define FP_M1_DIV_SHIFT 8
521 #define FP_M2_DIV_MASK 0x0000003f
522 #define FP_M2_IGD_DIV_MASK 0x000000ff
523 #define FP_M2_DIV_SHIFT 0
524 #define DPLL_TEST 0x606c
525 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
526 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
527 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
528 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
529 #define DPLLB_TEST_N_BYPASS (1 << 19)
530 #define DPLLB_TEST_M_BYPASS (1 << 18)
531 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
532 #define DPLLA_TEST_N_BYPASS (1 << 3)
533 #define DPLLA_TEST_M_BYPASS (1 << 2)
534 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
535 #define D_STATE 0x6104
536 #define CG_2D_DIS 0x6200
537 #define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24)
538 #define CG_3D_DIS 0x6204
544 #define PALETTE_A 0x0a000
545 #define PALETTE_B 0x0a800
552 * This mirrors the MCHBAR MMIO space whose location is determined by
553 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
554 * every way. It is not accessible from the CP register read instructions.
557 #define MCHBAR_MIRROR_BASE 0x10000
559 /** 915-945 and GM965 MCH register controlling DRAM channel access */
561 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
562 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
563 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
564 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
565 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
566 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
568 /** 965 MCH register controlling DRAM channel configuration */
569 #define C0DRB3 0x10206
570 #define C1DRB3 0x10606
572 /* Clocking configuration register */
573 #define CLKCFG 0x10c00
574 #define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
575 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
576 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
577 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
578 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
579 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
580 /* this is a guess, could be 5 as well */
581 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
582 #define CLKCFG_FSB_1600_ALT (5 << 0) /* hrawclk 400 */
583 #define CLKCFG_FSB_MASK (7 << 0)
585 /** GM965 GM45 render standby register */
586 #define MCHBAR_RENDER_STANDBY 0x111B8
588 #define PEG_BAND_GAP_DATA 0x14d68
594 #define OVADD 0x30000
595 #define DOVSTA 0x30008
596 #define OC_BUF (0x3<<20)
597 #define OGAMC5 0x30010
598 #define OGAMC4 0x30014
599 #define OGAMC3 0x30018
600 #define OGAMC2 0x3001c
601 #define OGAMC1 0x30020
602 #define OGAMC0 0x30024
605 * Display engine regs
608 /* Pipe A timing regs */
609 #define HTOTAL_A 0x60000
610 #define HBLANK_A 0x60004
611 #define HSYNC_A 0x60008
612 #define VTOTAL_A 0x6000c
613 #define VBLANK_A 0x60010
614 #define VSYNC_A 0x60014
615 #define PIPEASRC 0x6001c
616 #define BCLRPAT_A 0x60020
618 /* Pipe B timing regs */
619 #define HTOTAL_B 0x61000
620 #define HBLANK_B 0x61004
621 #define HSYNC_B 0x61008
622 #define VTOTAL_B 0x6100c
623 #define VBLANK_B 0x61010
624 #define VSYNC_B 0x61014
625 #define PIPEBSRC 0x6101c
626 #define BCLRPAT_B 0x61020
628 /* VGA port control */
630 #define ADPA_DAC_ENABLE (1<<31)
631 #define ADPA_DAC_DISABLE 0
632 #define ADPA_PIPE_SELECT_MASK (1<<30)
633 #define ADPA_PIPE_A_SELECT 0
634 #define ADPA_PIPE_B_SELECT (1<<30)
635 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
636 #define ADPA_SETS_HVPOLARITY 0
637 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
638 #define ADPA_VSYNC_CNTL_ENABLE 0
639 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
640 #define ADPA_HSYNC_CNTL_ENABLE 0
641 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
642 #define ADPA_VSYNC_ACTIVE_LOW 0
643 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
644 #define ADPA_HSYNC_ACTIVE_LOW 0
645 #define ADPA_DPMS_MASK (~(3<<10))
646 #define ADPA_DPMS_ON (0<<10)
647 #define ADPA_DPMS_SUSPEND (1<<10)
648 #define ADPA_DPMS_STANDBY (2<<10)
649 #define ADPA_DPMS_OFF (3<<10)
651 /* Hotplug control (945+ only) */
652 #define PORT_HOTPLUG_EN 0x61110
653 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
654 #define DPB_HOTPLUG_INT_EN (1 << 29)
655 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
656 #define DPC_HOTPLUG_INT_EN (1 << 28)
657 #define HDMID_HOTPLUG_INT_EN (1 << 27)
658 #define DPD_HOTPLUG_INT_EN (1 << 27)
659 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
660 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
661 #define TV_HOTPLUG_INT_EN (1 << 18)
662 #define CRT_HOTPLUG_INT_EN (1 << 9)
663 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
664 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
665 /* must use period 64 on GM45 according to docs */
666 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
667 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
668 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
669 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
670 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
671 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
672 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
673 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
674 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
675 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
676 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
677 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
678 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
679 #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
680 #define HOTPLUG_EN_MASK (HDMIB_HOTPLUG_INT_EN | \
681 HDMIC_HOTPLUG_INT_EN | \
682 HDMID_HOTPLUG_INT_EN | \
683 SDVOB_HOTPLUG_INT_EN | \
684 SDVOC_HOTPLUG_INT_EN | \
685 TV_HOTPLUG_INT_EN | \
689 #define PORT_HOTPLUG_STAT 0x61114
690 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
691 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
692 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
693 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
694 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
695 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
696 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
697 #define TV_HOTPLUG_INT_STATUS (1 << 10)
698 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
699 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
700 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
701 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
702 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
703 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
705 /* SDVO port control */
706 #define SDVOB 0x61140
707 #define SDVOC 0x61160
708 #define SDVO_ENABLE (1 << 31)
709 #define SDVO_PIPE_B_SELECT (1 << 30)
710 #define SDVO_STALL_SELECT (1 << 29)
711 #define SDVO_INTERRUPT_ENABLE (1 << 26)
713 * 915G/GM SDVO pixel multiplier.
715 * Programmed value is multiplier - 1, up to 5x.
717 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
719 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
720 #define SDVO_PORT_MULTIPLY_SHIFT 23
721 #define SDVO_PHASE_SELECT_MASK (15 << 19)
722 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
723 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
724 #define SDVOC_GANG_MODE (1 << 16)
725 #define SDVO_ENCODING_SDVO (0x0 << 10)
726 #define SDVO_ENCODING_HDMI (0x2 << 10)
727 /** Requird for HDMI operation */
728 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
729 #define SDVO_BORDER_ENABLE (1 << 7)
730 #define SDVO_AUDIO_ENABLE (1 << 6)
731 /** New with 965, default is to be set */
732 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
733 /** New with 965, default is to be set */
734 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
735 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
736 #define SDVO_DETECTED (1 << 2)
737 /* Bits to be preserved when writing */
738 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
739 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
741 /* DVO port control */
745 #define DVO_ENABLE (1 << 31)
746 #define DVO_PIPE_B_SELECT (1 << 30)
747 #define DVO_PIPE_STALL_UNUSED (0 << 28)
748 #define DVO_PIPE_STALL (1 << 28)
749 #define DVO_PIPE_STALL_TV (2 << 28)
750 #define DVO_PIPE_STALL_MASK (3 << 28)
751 #define DVO_USE_VGA_SYNC (1 << 15)
752 #define DVO_DATA_ORDER_I740 (0 << 14)
753 #define DVO_DATA_ORDER_FP (1 << 14)
754 #define DVO_VSYNC_DISABLE (1 << 11)
755 #define DVO_HSYNC_DISABLE (1 << 10)
756 #define DVO_VSYNC_TRISTATE (1 << 9)
757 #define DVO_HSYNC_TRISTATE (1 << 8)
758 #define DVO_BORDER_ENABLE (1 << 7)
759 #define DVO_DATA_ORDER_GBRG (1 << 6)
760 #define DVO_DATA_ORDER_RGGB (0 << 6)
761 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
762 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
763 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
764 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
765 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
766 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
767 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
768 #define DVO_PRESERVE_MASK (0x7<<24)
769 #define DVOA_SRCDIM 0x61124
770 #define DVOB_SRCDIM 0x61144
771 #define DVOC_SRCDIM 0x61164
772 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
773 #define DVO_SRCDIM_VERTICAL_SHIFT 0
775 /* LVDS port control */
778 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
779 * the DPLL semantics change when the LVDS is assigned to that pipe.
781 #define LVDS_PORT_EN (1 << 31)
782 /* Selects pipe B for LVDS data. Must be set on pre-965. */
783 #define LVDS_PIPEB_SELECT (1 << 30)
785 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
788 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
789 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
790 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
792 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
793 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
796 #define LVDS_A3_POWER_MASK (3 << 6)
797 #define LVDS_A3_POWER_DOWN (0 << 6)
798 #define LVDS_A3_POWER_UP (3 << 6)
800 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
803 #define LVDS_CLKB_POWER_MASK (3 << 4)
804 #define LVDS_CLKB_POWER_DOWN (0 << 4)
805 #define LVDS_CLKB_POWER_UP (3 << 4)
807 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
808 * setting for whether we are in dual-channel mode. The B3 pair will
809 * additionally only be powered up when LVDS_A3_POWER_UP is set.
811 #define LVDS_B0B3_POWER_MASK (3 << 2)
812 #define LVDS_B0B3_POWER_DOWN (0 << 2)
813 #define LVDS_B0B3_POWER_UP (3 << 2)
815 /* Panel power sequencing */
816 #define PP_STATUS 0x61200
817 #define PP_ON (1 << 31)
819 * Indicates that all dependencies of the panel are on:
823 * - LVDS/DVOB/DVOC on
825 #define PP_READY (1 << 30)
826 #define PP_SEQUENCE_NONE (0 << 28)
827 #define PP_SEQUENCE_ON (1 << 28)
828 #define PP_SEQUENCE_OFF (2 << 28)
829 #define PP_SEQUENCE_MASK 0x30000000
830 #define PP_CONTROL 0x61204
831 #define POWER_TARGET_ON (1 << 0)
832 #define PP_ON_DELAYS 0x61208
833 #define PP_OFF_DELAYS 0x6120c
834 #define PP_DIVISOR 0x61210
837 #define PFIT_CONTROL 0x61230
838 #define PFIT_ENABLE (1 << 31)
839 #define PFIT_PIPE_MASK (3 << 29)
840 #define PFIT_PIPE_SHIFT 29
841 #define VERT_INTERP_DISABLE (0 << 10)
842 #define VERT_INTERP_BILINEAR (1 << 10)
843 #define VERT_INTERP_MASK (3 << 10)
844 #define VERT_AUTO_SCALE (1 << 9)
845 #define HORIZ_INTERP_DISABLE (0 << 6)
846 #define HORIZ_INTERP_BILINEAR (1 << 6)
847 #define HORIZ_INTERP_MASK (3 << 6)
848 #define HORIZ_AUTO_SCALE (1 << 5)
849 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
850 #define PFIT_FILTER_FUZZY (0 << 24)
851 #define PFIT_SCALING_AUTO (0 << 26)
852 #define PFIT_SCALING_PROGRAMMED (1 << 26)
853 #define PFIT_SCALING_PILLAR (2 << 26)
854 #define PFIT_SCALING_LETTER (3 << 26)
855 #define PFIT_PGM_RATIOS 0x61234
856 #define PFIT_VERT_SCALE_MASK 0xfff00000
857 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
859 #define PFIT_VERT_SCALE_SHIFT 20
860 #define PFIT_VERT_SCALE_MASK 0xfff00000
861 #define PFIT_HORIZ_SCALE_SHIFT 4
862 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
864 #define PFIT_VERT_SCALE_SHIFT_965 16
865 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
866 #define PFIT_HORIZ_SCALE_SHIFT_965 0
867 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
869 #define PFIT_AUTO_RATIOS 0x61238
871 /* Backlight control */
872 #define BLC_PWM_CTL 0x61254
873 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
874 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
875 #define BLM_COMBINATION_MODE (1 << 30)
877 * This is the most significant 15 bits of the number of backlight cycles in a
878 * complete cycle of the modulated backlight control.
880 * The actual value is this field multiplied by two.
882 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
883 #define BLM_LEGACY_MODE (1 << 16)
885 * This is the number of cycles out of the backlight modulation cycle for which
886 * the backlight is on.
888 * This field must be no greater than the number of cycles in the complete
889 * backlight modulation cycle.
891 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
892 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
894 /* TV port control */
895 #define TV_CTL 0x68000
896 /** Enables the TV encoder */
897 # define TV_ENC_ENABLE (1 << 31)
898 /** Sources the TV encoder input from pipe B instead of A. */
899 # define TV_ENC_PIPEB_SELECT (1 << 30)
900 /** Outputs composite video (DAC A only) */
901 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
902 /** Outputs SVideo video (DAC B/C) */
903 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
904 /** Outputs Component video (DAC A/B/C) */
905 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
906 /** Outputs Composite and SVideo (DAC A/B/C) */
907 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
908 # define TV_TRILEVEL_SYNC (1 << 21)
909 /** Enables slow sync generation (945GM only) */
910 # define TV_SLOW_SYNC (1 << 20)
911 /** Selects 4x oversampling for 480i and 576p */
912 # define TV_OVERSAMPLE_4X (0 << 18)
913 /** Selects 2x oversampling for 720p and 1080i */
914 # define TV_OVERSAMPLE_2X (1 << 18)
915 /** Selects no oversampling for 1080p */
916 # define TV_OVERSAMPLE_NONE (2 << 18)
917 /** Selects 8x oversampling */
918 # define TV_OVERSAMPLE_8X (3 << 18)
919 /** Selects progressive mode rather than interlaced */
920 # define TV_PROGRESSIVE (1 << 17)
921 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
922 # define TV_PAL_BURST (1 << 16)
923 /** Field for setting delay of Y compared to C */
924 # define TV_YC_SKEW_MASK (7 << 12)
925 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
926 # define TV_ENC_SDP_FIX (1 << 11)
928 * Enables a fix for the 915GM only.
930 * Not sure what it does.
932 # define TV_ENC_C0_FIX (1 << 10)
933 /** Bits that must be preserved by software */
934 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
935 # define TV_FUSE_STATE_MASK (3 << 4)
936 /** Read-only state that reports all features enabled */
937 # define TV_FUSE_STATE_ENABLED (0 << 4)
938 /** Read-only state that reports that Macrovision is disabled in hardware*/
939 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
940 /** Read-only state that reports that TV-out is disabled in hardware. */
941 # define TV_FUSE_STATE_DISABLED (2 << 4)
942 /** Normal operation */
943 # define TV_TEST_MODE_NORMAL (0 << 0)
944 /** Encoder test pattern 1 - combo pattern */
945 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
946 /** Encoder test pattern 2 - full screen vertical 75% color bars */
947 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
948 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
949 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
950 /** Encoder test pattern 4 - random noise */
951 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
952 /** Encoder test pattern 5 - linear color ramps */
953 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
955 * This test mode forces the DACs to 50% of full output.
957 * This is used for load detection in combination with TVDAC_SENSE_MASK
959 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
960 # define TV_TEST_MODE_MASK (7 << 0)
962 #define TV_DAC 0x68004
964 * Reports that DAC state change logic has reported change (RO).
966 * This gets cleared when TV_DAC_STATE_EN is cleared
968 # define TVDAC_STATE_CHG (1 << 31)
969 # define TVDAC_SENSE_MASK (7 << 28)
970 /** Reports that DAC A voltage is above the detect threshold */
971 # define TVDAC_A_SENSE (1 << 30)
972 /** Reports that DAC B voltage is above the detect threshold */
973 # define TVDAC_B_SENSE (1 << 29)
974 /** Reports that DAC C voltage is above the detect threshold */
975 # define TVDAC_C_SENSE (1 << 28)
977 * Enables DAC state detection logic, for load-based TV detection.
979 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
980 * to off, for load detection to work.
982 # define TVDAC_STATE_CHG_EN (1 << 27)
983 /** Sets the DAC A sense value to high */
984 # define TVDAC_A_SENSE_CTL (1 << 26)
985 /** Sets the DAC B sense value to high */
986 # define TVDAC_B_SENSE_CTL (1 << 25)
987 /** Sets the DAC C sense value to high */
988 # define TVDAC_C_SENSE_CTL (1 << 24)
989 /** Overrides the ENC_ENABLE and DAC voltage levels */
990 # define DAC_CTL_OVERRIDE (1 << 7)
991 /** Sets the slew rate. Must be preserved in software */
992 # define ENC_TVDAC_SLEW_FAST (1 << 6)
993 # define DAC_A_1_3_V (0 << 4)
994 # define DAC_A_1_1_V (1 << 4)
995 # define DAC_A_0_7_V (2 << 4)
996 # define DAC_A_MASK (3 << 4)
997 # define DAC_B_1_3_V (0 << 2)
998 # define DAC_B_1_1_V (1 << 2)
999 # define DAC_B_0_7_V (2 << 2)
1000 # define DAC_B_MASK (3 << 2)
1001 # define DAC_C_1_3_V (0 << 0)
1002 # define DAC_C_1_1_V (1 << 0)
1003 # define DAC_C_0_7_V (2 << 0)
1004 # define DAC_C_MASK (3 << 0)
1007 * CSC coefficients are stored in a floating point format with 9 bits of
1008 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1009 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1010 * -1 (0x3) being the only legal negative value.
1012 #define TV_CSC_Y 0x68010
1013 # define TV_RY_MASK 0x07ff0000
1014 # define TV_RY_SHIFT 16
1015 # define TV_GY_MASK 0x00000fff
1016 # define TV_GY_SHIFT 0
1018 #define TV_CSC_Y2 0x68014
1019 # define TV_BY_MASK 0x07ff0000
1020 # define TV_BY_SHIFT 16
1022 * Y attenuation for component video.
1024 * Stored in 1.9 fixed point.
1026 # define TV_AY_MASK 0x000003ff
1027 # define TV_AY_SHIFT 0
1029 #define TV_CSC_U 0x68018
1030 # define TV_RU_MASK 0x07ff0000
1031 # define TV_RU_SHIFT 16
1032 # define TV_GU_MASK 0x000007ff
1033 # define TV_GU_SHIFT 0
1035 #define TV_CSC_U2 0x6801c
1036 # define TV_BU_MASK 0x07ff0000
1037 # define TV_BU_SHIFT 16
1039 * U attenuation for component video.
1041 * Stored in 1.9 fixed point.
1043 # define TV_AU_MASK 0x000003ff
1044 # define TV_AU_SHIFT 0
1046 #define TV_CSC_V 0x68020
1047 # define TV_RV_MASK 0x0fff0000
1048 # define TV_RV_SHIFT 16
1049 # define TV_GV_MASK 0x000007ff
1050 # define TV_GV_SHIFT 0
1052 #define TV_CSC_V2 0x68024
1053 # define TV_BV_MASK 0x07ff0000
1054 # define TV_BV_SHIFT 16
1056 * V attenuation for component video.
1058 * Stored in 1.9 fixed point.
1060 # define TV_AV_MASK 0x000007ff
1061 # define TV_AV_SHIFT 0
1063 #define TV_CLR_KNOBS 0x68028
1064 /** 2s-complement brightness adjustment */
1065 # define TV_BRIGHTNESS_MASK 0xff000000
1066 # define TV_BRIGHTNESS_SHIFT 24
1067 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1068 # define TV_CONTRAST_MASK 0x00ff0000
1069 # define TV_CONTRAST_SHIFT 16
1070 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1071 # define TV_SATURATION_MASK 0x0000ff00
1072 # define TV_SATURATION_SHIFT 8
1073 /** Hue adjustment, as an integer phase angle in degrees */
1074 # define TV_HUE_MASK 0x000000ff
1075 # define TV_HUE_SHIFT 0
1077 #define TV_CLR_LEVEL 0x6802c
1078 /** Controls the DAC level for black */
1079 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1080 # define TV_BLACK_LEVEL_SHIFT 16
1081 /** Controls the DAC level for blanking */
1082 # define TV_BLANK_LEVEL_MASK 0x000001ff
1083 # define TV_BLANK_LEVEL_SHIFT 0
1085 #define TV_H_CTL_1 0x68030
1086 /** Number of pixels in the hsync. */
1087 # define TV_HSYNC_END_MASK 0x1fff0000
1088 # define TV_HSYNC_END_SHIFT 16
1089 /** Total number of pixels minus one in the line (display and blanking). */
1090 # define TV_HTOTAL_MASK 0x00001fff
1091 # define TV_HTOTAL_SHIFT 0
1093 #define TV_H_CTL_2 0x68034
1094 /** Enables the colorburst (needed for non-component color) */
1095 # define TV_BURST_ENA (1 << 31)
1096 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1097 # define TV_HBURST_START_SHIFT 16
1098 # define TV_HBURST_START_MASK 0x1fff0000
1099 /** Length of the colorburst */
1100 # define TV_HBURST_LEN_SHIFT 0
1101 # define TV_HBURST_LEN_MASK 0x0001fff
1103 #define TV_H_CTL_3 0x68038
1104 /** End of hblank, measured in pixels minus one from start of hsync */
1105 # define TV_HBLANK_END_SHIFT 16
1106 # define TV_HBLANK_END_MASK 0x1fff0000
1107 /** Start of hblank, measured in pixels minus one from start of hsync */
1108 # define TV_HBLANK_START_SHIFT 0
1109 # define TV_HBLANK_START_MASK 0x0001fff
1111 #define TV_V_CTL_1 0x6803c
1113 # define TV_NBR_END_SHIFT 16
1114 # define TV_NBR_END_MASK 0x07ff0000
1116 # define TV_VI_END_F1_SHIFT 8
1117 # define TV_VI_END_F1_MASK 0x00003f00
1119 # define TV_VI_END_F2_SHIFT 0
1120 # define TV_VI_END_F2_MASK 0x0000003f
1122 #define TV_V_CTL_2 0x68040
1123 /** Length of vsync, in half lines */
1124 # define TV_VSYNC_LEN_MASK 0x07ff0000
1125 # define TV_VSYNC_LEN_SHIFT 16
1126 /** Offset of the start of vsync in field 1, measured in one less than the
1127 * number of half lines.
1129 # define TV_VSYNC_START_F1_MASK 0x00007f00
1130 # define TV_VSYNC_START_F1_SHIFT 8
1132 * Offset of the start of vsync in field 2, measured in one less than the
1133 * number of half lines.
1135 # define TV_VSYNC_START_F2_MASK 0x0000007f
1136 # define TV_VSYNC_START_F2_SHIFT 0
1138 #define TV_V_CTL_3 0x68044
1139 /** Enables generation of the equalization signal */
1140 # define TV_EQUAL_ENA (1 << 31)
1141 /** Length of vsync, in half lines */
1142 # define TV_VEQ_LEN_MASK 0x007f0000
1143 # define TV_VEQ_LEN_SHIFT 16
1144 /** Offset of the start of equalization in field 1, measured in one less than
1145 * the number of half lines.
1147 # define TV_VEQ_START_F1_MASK 0x0007f00
1148 # define TV_VEQ_START_F1_SHIFT 8
1150 * Offset of the start of equalization in field 2, measured in one less than
1151 * the number of half lines.
1153 # define TV_VEQ_START_F2_MASK 0x000007f
1154 # define TV_VEQ_START_F2_SHIFT 0
1156 #define TV_V_CTL_4 0x68048
1158 * Offset to start of vertical colorburst, measured in one less than the
1159 * number of lines from vertical start.
1161 # define TV_VBURST_START_F1_MASK 0x003f0000
1162 # define TV_VBURST_START_F1_SHIFT 16
1164 * Offset to the end of vertical colorburst, measured in one less than the
1165 * number of lines from the start of NBR.
1167 # define TV_VBURST_END_F1_MASK 0x000000ff
1168 # define TV_VBURST_END_F1_SHIFT 0
1170 #define TV_V_CTL_5 0x6804c
1172 * Offset to start of vertical colorburst, measured in one less than the
1173 * number of lines from vertical start.
1175 # define TV_VBURST_START_F2_MASK 0x003f0000
1176 # define TV_VBURST_START_F2_SHIFT 16
1178 * Offset to the end of vertical colorburst, measured in one less than the
1179 * number of lines from the start of NBR.
1181 # define TV_VBURST_END_F2_MASK 0x000000ff
1182 # define TV_VBURST_END_F2_SHIFT 0
1184 #define TV_V_CTL_6 0x68050
1186 * Offset to start of vertical colorburst, measured in one less than the
1187 * number of lines from vertical start.
1189 # define TV_VBURST_START_F3_MASK 0x003f0000
1190 # define TV_VBURST_START_F3_SHIFT 16
1192 * Offset to the end of vertical colorburst, measured in one less than the
1193 * number of lines from the start of NBR.
1195 # define TV_VBURST_END_F3_MASK 0x000000ff
1196 # define TV_VBURST_END_F3_SHIFT 0
1198 #define TV_V_CTL_7 0x68054
1200 * Offset to start of vertical colorburst, measured in one less than the
1201 * number of lines from vertical start.
1203 # define TV_VBURST_START_F4_MASK 0x003f0000
1204 # define TV_VBURST_START_F4_SHIFT 16
1206 * Offset to the end of vertical colorburst, measured in one less than the
1207 * number of lines from the start of NBR.
1209 # define TV_VBURST_END_F4_MASK 0x000000ff
1210 # define TV_VBURST_END_F4_SHIFT 0
1212 #define TV_SC_CTL_1 0x68060
1213 /** Turns on the first subcarrier phase generation DDA */
1214 # define TV_SC_DDA1_EN (1 << 31)
1215 /** Turns on the first subcarrier phase generation DDA */
1216 # define TV_SC_DDA2_EN (1 << 30)
1217 /** Turns on the first subcarrier phase generation DDA */
1218 # define TV_SC_DDA3_EN (1 << 29)
1219 /** Sets the subcarrier DDA to reset frequency every other field */
1220 # define TV_SC_RESET_EVERY_2 (0 << 24)
1221 /** Sets the subcarrier DDA to reset frequency every fourth field */
1222 # define TV_SC_RESET_EVERY_4 (1 << 24)
1223 /** Sets the subcarrier DDA to reset frequency every eighth field */
1224 # define TV_SC_RESET_EVERY_8 (2 << 24)
1225 /** Sets the subcarrier DDA to never reset the frequency */
1226 # define TV_SC_RESET_NEVER (3 << 24)
1227 /** Sets the peak amplitude of the colorburst.*/
1228 # define TV_BURST_LEVEL_MASK 0x00ff0000
1229 # define TV_BURST_LEVEL_SHIFT 16
1230 /** Sets the increment of the first subcarrier phase generation DDA */
1231 # define TV_SCDDA1_INC_MASK 0x00000fff
1232 # define TV_SCDDA1_INC_SHIFT 0
1234 #define TV_SC_CTL_2 0x68064
1235 /** Sets the rollover for the second subcarrier phase generation DDA */
1236 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1237 # define TV_SCDDA2_SIZE_SHIFT 16
1238 /** Sets the increent of the second subcarrier phase generation DDA */
1239 # define TV_SCDDA2_INC_MASK 0x00007fff
1240 # define TV_SCDDA2_INC_SHIFT 0
1242 #define TV_SC_CTL_3 0x68068
1243 /** Sets the rollover for the third subcarrier phase generation DDA */
1244 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1245 # define TV_SCDDA3_SIZE_SHIFT 16
1246 /** Sets the increent of the third subcarrier phase generation DDA */
1247 # define TV_SCDDA3_INC_MASK 0x00007fff
1248 # define TV_SCDDA3_INC_SHIFT 0
1250 #define TV_WIN_POS 0x68070
1251 /** X coordinate of the display from the start of horizontal active */
1252 # define TV_XPOS_MASK 0x1fff0000
1253 # define TV_XPOS_SHIFT 16
1254 /** Y coordinate of the display from the start of vertical active (NBR) */
1255 # define TV_YPOS_MASK 0x00000fff
1256 # define TV_YPOS_SHIFT 0
1258 #define TV_WIN_SIZE 0x68074
1259 /** Horizontal size of the display window, measured in pixels*/
1260 # define TV_XSIZE_MASK 0x1fff0000
1261 # define TV_XSIZE_SHIFT 16
1263 * Vertical size of the display window, measured in pixels.
1265 * Must be even for interlaced modes.
1267 # define TV_YSIZE_MASK 0x00000fff
1268 # define TV_YSIZE_SHIFT 0
1270 #define TV_FILTER_CTL_1 0x68080
1272 * Enables automatic scaling calculation.
1274 * If set, the rest of the registers are ignored, and the calculated values can
1275 * be read back from the register.
1277 # define TV_AUTO_SCALE (1 << 31)
1279 * Disables the vertical filter.
1281 * This is required on modes more than 1024 pixels wide */
1282 # define TV_V_FILTER_BYPASS (1 << 29)
1283 /** Enables adaptive vertical filtering */
1284 # define TV_VADAPT (1 << 28)
1285 # define TV_VADAPT_MODE_MASK (3 << 26)
1286 /** Selects the least adaptive vertical filtering mode */
1287 # define TV_VADAPT_MODE_LEAST (0 << 26)
1288 /** Selects the moderately adaptive vertical filtering mode */
1289 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1290 /** Selects the most adaptive vertical filtering mode */
1291 # define TV_VADAPT_MODE_MOST (3 << 26)
1293 * Sets the horizontal scaling factor.
1295 * This should be the fractional part of the horizontal scaling factor divided
1296 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1298 * (src width - 1) / ((oversample * dest width) - 1)
1300 # define TV_HSCALE_FRAC_MASK 0x00003fff
1301 # define TV_HSCALE_FRAC_SHIFT 0
1303 #define TV_FILTER_CTL_2 0x68084
1305 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1307 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1309 # define TV_VSCALE_INT_MASK 0x00038000
1310 # define TV_VSCALE_INT_SHIFT 15
1312 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1314 * \sa TV_VSCALE_INT_MASK
1316 # define TV_VSCALE_FRAC_MASK 0x00007fff
1317 # define TV_VSCALE_FRAC_SHIFT 0
1319 #define TV_FILTER_CTL_3 0x68088
1321 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1323 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1325 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1327 # define TV_VSCALE_IP_INT_MASK 0x00038000
1328 # define TV_VSCALE_IP_INT_SHIFT 15
1330 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1332 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1334 * \sa TV_VSCALE_IP_INT_MASK
1336 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1337 # define TV_VSCALE_IP_FRAC_SHIFT 0
1339 #define TV_CC_CONTROL 0x68090
1340 # define TV_CC_ENABLE (1 << 31)
1342 * Specifies which field to send the CC data in.
1344 * CC data is usually sent in field 0.
1346 # define TV_CC_FID_MASK (1 << 27)
1347 # define TV_CC_FID_SHIFT 27
1348 /** Sets the horizontal position of the CC data. Usually 135. */
1349 # define TV_CC_HOFF_MASK 0x03ff0000
1350 # define TV_CC_HOFF_SHIFT 16
1351 /** Sets the vertical position of the CC data. Usually 21 */
1352 # define TV_CC_LINE_MASK 0x0000003f
1353 # define TV_CC_LINE_SHIFT 0
1355 #define TV_CC_DATA 0x68094
1356 # define TV_CC_RDY (1 << 31)
1357 /** Second word of CC data to be transmitted. */
1358 # define TV_CC_DATA_2_MASK 0x007f0000
1359 # define TV_CC_DATA_2_SHIFT 16
1360 /** First word of CC data to be transmitted. */
1361 # define TV_CC_DATA_1_MASK 0x0000007f
1362 # define TV_CC_DATA_1_SHIFT 0
1364 #define TV_H_LUMA_0 0x68100
1365 #define TV_H_LUMA_59 0x681ec
1366 #define TV_H_CHROMA_0 0x68200
1367 #define TV_H_CHROMA_59 0x682ec
1368 #define TV_V_LUMA_0 0x68300
1369 #define TV_V_LUMA_42 0x683a8
1370 #define TV_V_CHROMA_0 0x68400
1371 #define TV_V_CHROMA_42 0x684a8
1374 #define DP_B 0x64100
1375 #define DP_C 0x64200
1376 #define DP_D 0x64300
1378 #define DP_PORT_EN (1 << 31)
1379 #define DP_PIPEB_SELECT (1 << 30)
1381 /* Link training mode - select a suitable mode for each stage */
1382 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1383 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1384 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1385 #define DP_LINK_TRAIN_OFF (3 << 28)
1386 #define DP_LINK_TRAIN_MASK (3 << 28)
1387 #define DP_LINK_TRAIN_SHIFT 28
1389 /* Signal voltages. These are mostly controlled by the other end */
1390 #define DP_VOLTAGE_0_4 (0 << 25)
1391 #define DP_VOLTAGE_0_6 (1 << 25)
1392 #define DP_VOLTAGE_0_8 (2 << 25)
1393 #define DP_VOLTAGE_1_2 (3 << 25)
1394 #define DP_VOLTAGE_MASK (7 << 25)
1395 #define DP_VOLTAGE_SHIFT 25
1397 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1400 #define DP_PRE_EMPHASIS_0 (0 << 22)
1401 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1402 #define DP_PRE_EMPHASIS_6 (2 << 22)
1403 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1404 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1405 #define DP_PRE_EMPHASIS_SHIFT 22
1407 /* How many wires to use. I guess 3 was too hard */
1408 #define DP_PORT_WIDTH_1 (0 << 19)
1409 #define DP_PORT_WIDTH_2 (1 << 19)
1410 #define DP_PORT_WIDTH_4 (3 << 19)
1411 #define DP_PORT_WIDTH_MASK (7 << 19)
1413 /* Mystic DPCD version 1.1 special mode */
1414 #define DP_ENHANCED_FRAMING (1 << 18)
1416 /** locked once port is enabled */
1417 #define DP_PORT_REVERSAL (1 << 15)
1419 /** sends the clock on lane 15 of the PEG for debug */
1420 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1422 #define DP_SCRAMBLING_DISABLE (1 << 12)
1424 /** limit RGB values to avoid confusing TVs */
1425 #define DP_COLOR_RANGE_16_235 (1 << 8)
1427 /** Turn on the audio link */
1428 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1430 /** vs and hs sync polarity */
1431 #define DP_SYNC_VS_HIGH (1 << 4)
1432 #define DP_SYNC_HS_HIGH (1 << 3)
1435 #define DP_DETECTED (1 << 2)
1437 /** The aux channel provides a way to talk to the
1438 * signal sink for DDC etc. Max packet size supported
1439 * is 20 bytes in each direction, hence the 5 fixed
1442 #define DPB_AUX_CH_CTL 0x64110
1443 #define DPB_AUX_CH_DATA1 0x64114
1444 #define DPB_AUX_CH_DATA2 0x64118
1445 #define DPB_AUX_CH_DATA3 0x6411c
1446 #define DPB_AUX_CH_DATA4 0x64120
1447 #define DPB_AUX_CH_DATA5 0x64124
1449 #define DPC_AUX_CH_CTL 0x64210
1450 #define DPC_AUX_CH_DATA1 0x64214
1451 #define DPC_AUX_CH_DATA2 0x64218
1452 #define DPC_AUX_CH_DATA3 0x6421c
1453 #define DPC_AUX_CH_DATA4 0x64220
1454 #define DPC_AUX_CH_DATA5 0x64224
1456 #define DPD_AUX_CH_CTL 0x64310
1457 #define DPD_AUX_CH_DATA1 0x64314
1458 #define DPD_AUX_CH_DATA2 0x64318
1459 #define DPD_AUX_CH_DATA3 0x6431c
1460 #define DPD_AUX_CH_DATA4 0x64320
1461 #define DPD_AUX_CH_DATA5 0x64324
1463 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1464 #define DP_AUX_CH_CTL_DONE (1 << 30)
1465 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1466 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1467 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1468 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1469 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1470 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1471 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1472 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1473 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1474 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1475 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1476 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1477 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1478 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1479 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1480 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1481 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1482 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1483 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1486 * Computing GMCH M and N values for the Display Port link
1488 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1490 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1492 * The GMCH value is used internally
1494 * bytes_per_pixel is the number of bytes coming out of the plane,
1495 * which is after the LUTs, so we want the bytes for our color format.
1496 * For our current usage, this is always 3, one byte for R, G and B.
1498 #define PIPEA_GMCH_DATA_M 0x70050
1499 #define PIPEB_GMCH_DATA_M 0x71050
1501 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1502 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1503 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1505 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1507 #define PIPEA_GMCH_DATA_N 0x70054
1508 #define PIPEB_GMCH_DATA_N 0x71054
1509 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1512 * Computing Link M and N values for the Display Port link
1514 * Link M / N = pixel_clock / ls_clk
1516 * (the DP spec calls pixel_clock the 'strm_clk')
1518 * The Link value is transmitted in the Main Stream
1519 * Attributes and VB-ID.
1522 #define PIPEA_DP_LINK_M 0x70060
1523 #define PIPEB_DP_LINK_M 0x71060
1524 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1526 #define PIPEA_DP_LINK_N 0x70064
1527 #define PIPEB_DP_LINK_N 0x71064
1528 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1530 /* Display & cursor control */
1533 #define PIPEADSL 0x70000
1534 #define PIPEACONF 0x70008
1535 #define PIPEACONF_ENABLE (1<<31)
1536 #define PIPEACONF_DISABLE 0
1537 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1538 #define I965_PIPECONF_ACTIVE (1<<30)
1539 #define PIPEACONF_SINGLE_WIDE 0
1540 #define PIPEACONF_PIPE_UNLOCKED 0
1541 #define PIPEACONF_PIPE_LOCKED (1<<25)
1542 #define PIPEACONF_PALETTE 0
1543 #define PIPEACONF_GAMMA (1<<24)
1544 #define PIPECONF_FORCE_BORDER (1<<25)
1545 #define PIPECONF_PROGRESSIVE (0 << 21)
1546 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1547 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1548 #define PIPEASTAT 0x70024
1549 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1550 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1551 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1552 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1553 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1554 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1555 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1556 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1557 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1558 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1559 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1560 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1561 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1562 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1563 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1564 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1565 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1566 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1567 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1568 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1569 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1570 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1571 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1572 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1573 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1574 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1575 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1576 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1577 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1579 #define DSPARB 0x70030
1580 #define DSPARB_CSTART_MASK (0x7f << 7)
1581 #define DSPARB_CSTART_SHIFT 7
1582 #define DSPARB_BSTART_MASK (0x7f)
1583 #define DSPARB_BSTART_SHIFT 0
1585 * The two pipe frame counter registers are not synchronized, so
1586 * reading a stable value is somewhat tricky. The following code
1590 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1591 * PIPE_FRAME_HIGH_SHIFT;
1592 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1593 * PIPE_FRAME_LOW_SHIFT);
1594 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1595 * PIPE_FRAME_HIGH_SHIFT);
1596 * } while (high1 != high2);
1597 * frame = (high1 << 8) | low1;
1599 #define PIPEAFRAMEHIGH 0x70040
1600 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1601 #define PIPE_FRAME_HIGH_SHIFT 0
1602 #define PIPEAFRAMEPIXEL 0x70044
1603 #define PIPE_FRAME_LOW_MASK 0xff000000
1604 #define PIPE_FRAME_LOW_SHIFT 24
1605 #define PIPE_PIXEL_MASK 0x00ffffff
1606 #define PIPE_PIXEL_SHIFT 0
1607 /* GM45+ just has to be different */
1608 #define PIPEA_FRMCOUNT_GM45 0x70040
1609 #define PIPEA_FLIPCOUNT_GM45 0x70044
1611 /* Cursor A & B regs */
1612 #define CURACNTR 0x70080
1613 /* Old style CUR*CNTR flags (desktop 8xx) */
1614 #define CURSOR_ENABLE 0x80000000
1615 #define CURSOR_GAMMA_ENABLE 0x40000000
1616 #define CURSOR_STRIDE_MASK 0x30000000
1617 #define CURSOR_FORMAT_SHIFT 24
1618 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
1619 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
1620 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
1621 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
1622 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
1623 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
1624 /* New style CUR*CNTR flags */
1625 #define CURSOR_MODE 0x27
1626 #define CURSOR_MODE_DISABLE 0x00
1627 #define CURSOR_MODE_64_32B_AX 0x07
1628 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1629 #define MCURSOR_PIPE_SELECT (1 << 28)
1630 #define MCURSOR_PIPE_A 0x00
1631 #define MCURSOR_PIPE_B (1 << 28)
1632 #define MCURSOR_GAMMA_ENABLE (1 << 26)
1633 #define CURABASE 0x70084
1634 #define CURAPOS 0x70088
1635 #define CURSOR_POS_MASK 0x007FF
1636 #define CURSOR_POS_SIGN 0x8000
1637 #define CURSOR_X_SHIFT 0
1638 #define CURSOR_Y_SHIFT 16
1639 #define CURSIZE 0x700a0
1640 #define CURBCNTR 0x700c0
1641 #define CURBBASE 0x700c4
1642 #define CURBPOS 0x700c8
1644 /* Display A control */
1645 #define DSPACNTR 0x70180
1646 #define DISPLAY_PLANE_ENABLE (1<<31)
1647 #define DISPLAY_PLANE_DISABLE 0
1648 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1649 #define DISPPLANE_GAMMA_DISABLE 0
1650 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1651 #define DISPPLANE_8BPP (0x2<<26)
1652 #define DISPPLANE_15_16BPP (0x4<<26)
1653 #define DISPPLANE_16BPP (0x5<<26)
1654 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1655 #define DISPPLANE_32BPP (0x7<<26)
1656 #define DISPPLANE_STEREO_ENABLE (1<<25)
1657 #define DISPPLANE_STEREO_DISABLE 0
1658 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1659 #define DISPPLANE_SEL_PIPE_A 0
1660 #define DISPPLANE_SEL_PIPE_B (1<<24)
1661 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1662 #define DISPPLANE_SRC_KEY_DISABLE 0
1663 #define DISPPLANE_LINE_DOUBLE (1<<20)
1664 #define DISPPLANE_NO_LINE_DOUBLE 0
1665 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1666 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1667 #define DISPPLANE_TILED (1<<10)
1668 #define DSPAADDR 0x70184
1669 #define DSPASTRIDE 0x70188
1670 #define DSPAPOS 0x7018C /* reserved */
1671 #define DSPASIZE 0x70190
1672 #define DSPASURF 0x7019C /* 965+ only */
1673 #define DSPATILEOFF 0x701A4 /* 965+ only */
1676 #define SWF00 0x71410
1677 #define SWF01 0x71414
1678 #define SWF02 0x71418
1679 #define SWF03 0x7141c
1680 #define SWF04 0x71420
1681 #define SWF05 0x71424
1682 #define SWF06 0x71428
1683 #define SWF10 0x70410
1684 #define SWF11 0x70414
1685 #define SWF14 0x71420
1686 #define SWF30 0x72414
1687 #define SWF31 0x72418
1688 #define SWF32 0x7241c
1691 #define PIPEBDSL 0x71000
1692 #define PIPEBCONF 0x71008
1693 #define PIPEBSTAT 0x71024
1694 #define PIPEBFRAMEHIGH 0x71040
1695 #define PIPEBFRAMEPIXEL 0x71044
1696 #define PIPEB_FRMCOUNT_GM45 0x71040
1697 #define PIPEB_FLIPCOUNT_GM45 0x71044
1700 /* Display B control */
1701 #define DSPBCNTR 0x71180
1702 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1703 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1704 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1705 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1706 #define DSPBADDR 0x71184
1707 #define DSPBSTRIDE 0x71188
1708 #define DSPBPOS 0x7118C
1709 #define DSPBSIZE 0x71190
1710 #define DSPBSURF 0x7119C
1711 #define DSPBTILEOFF 0x711A4
1714 #define VGACNTRL 0x71400
1715 # define VGA_DISP_DISABLE (1 << 31)
1716 # define VGA_2X_MODE (1 << 30)
1717 # define VGA_PIPE_B_SELECT (1 << 29)
1721 #define CPU_VGACNTRL 0x41000
1723 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
1724 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
1725 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
1726 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
1727 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
1728 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
1729 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
1730 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
1731 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
1733 /* refresh rate hardware control */
1734 #define RR_HW_CTL 0x45300
1735 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
1736 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
1738 #define FDI_PLL_BIOS_0 0x46000
1739 #define FDI_PLL_BIOS_1 0x46004
1740 #define FDI_PLL_BIOS_2 0x46008
1741 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
1742 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
1743 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
1745 #define FDI_PLL_FREQ_CTL 0x46030
1746 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
1747 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
1748 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
1751 #define PIPEA_DATA_M1 0x60030
1752 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
1753 #define TU_SIZE_MASK 0x7e000000
1754 #define PIPEA_DATA_M1_OFFSET 0
1755 #define PIPEA_DATA_N1 0x60034
1756 #define PIPEA_DATA_N1_OFFSET 0
1758 #define PIPEA_DATA_M2 0x60038
1759 #define PIPEA_DATA_M2_OFFSET 0
1760 #define PIPEA_DATA_N2 0x6003c
1761 #define PIPEA_DATA_N2_OFFSET 0
1763 #define PIPEA_LINK_M1 0x60040
1764 #define PIPEA_LINK_M1_OFFSET 0
1765 #define PIPEA_LINK_N1 0x60044
1766 #define PIPEA_LINK_N1_OFFSET 0
1768 #define PIPEA_LINK_M2 0x60048
1769 #define PIPEA_LINK_M2_OFFSET 0
1770 #define PIPEA_LINK_N2 0x6004c
1771 #define PIPEA_LINK_N2_OFFSET 0
1773 /* PIPEB timing regs are same start from 0x61000 */
1775 #define PIPEB_DATA_M1 0x61030
1776 #define PIPEB_DATA_M1_OFFSET 0
1777 #define PIPEB_DATA_N1 0x61034
1778 #define PIPEB_DATA_N1_OFFSET 0
1780 #define PIPEB_DATA_M2 0x61038
1781 #define PIPEB_DATA_M2_OFFSET 0
1782 #define PIPEB_DATA_N2 0x6103c
1783 #define PIPEB_DATA_N2_OFFSET 0
1785 #define PIPEB_LINK_M1 0x61040
1786 #define PIPEB_LINK_M1_OFFSET 0
1787 #define PIPEB_LINK_N1 0x61044
1788 #define PIPEB_LINK_N1_OFFSET 0
1790 #define PIPEB_LINK_M2 0x61048
1791 #define PIPEB_LINK_M2_OFFSET 0
1792 #define PIPEB_LINK_N2 0x6104c
1793 #define PIPEB_LINK_N2_OFFSET 0
1795 /* CPU panel fitter */
1796 #define PFA_CTL_1 0x68080
1797 #define PFB_CTL_1 0x68880
1798 #define PF_ENABLE (1<<31)
1800 /* legacy palette */
1801 #define LGC_PALETTE_A 0x4a000
1802 #define LGC_PALETTE_B 0x4a800
1805 #define DE_MASTER_IRQ_CONTROL (1 << 31)
1806 #define DE_SPRITEB_FLIP_DONE (1 << 29)
1807 #define DE_SPRITEA_FLIP_DONE (1 << 28)
1808 #define DE_PLANEB_FLIP_DONE (1 << 27)
1809 #define DE_PLANEA_FLIP_DONE (1 << 26)
1810 #define DE_PCU_EVENT (1 << 25)
1811 #define DE_GTT_FAULT (1 << 24)
1812 #define DE_POISON (1 << 23)
1813 #define DE_PERFORM_COUNTER (1 << 22)
1814 #define DE_PCH_EVENT (1 << 21)
1815 #define DE_AUX_CHANNEL_A (1 << 20)
1816 #define DE_DP_A_HOTPLUG (1 << 19)
1817 #define DE_GSE (1 << 18)
1818 #define DE_PIPEB_VBLANK (1 << 15)
1819 #define DE_PIPEB_EVEN_FIELD (1 << 14)
1820 #define DE_PIPEB_ODD_FIELD (1 << 13)
1821 #define DE_PIPEB_LINE_COMPARE (1 << 12)
1822 #define DE_PIPEB_VSYNC (1 << 11)
1823 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
1824 #define DE_PIPEA_VBLANK (1 << 7)
1825 #define DE_PIPEA_EVEN_FIELD (1 << 6)
1826 #define DE_PIPEA_ODD_FIELD (1 << 5)
1827 #define DE_PIPEA_LINE_COMPARE (1 << 4)
1828 #define DE_PIPEA_VSYNC (1 << 3)
1829 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
1831 #define DEISR 0x44000
1832 #define DEIMR 0x44004
1833 #define DEIIR 0x44008
1834 #define DEIER 0x4400c
1837 #define GT_SYNC_STATUS (1 << 2)
1838 #define GT_USER_INTERRUPT (1 << 0)
1840 #define GTISR 0x44010
1841 #define GTIMR 0x44014
1842 #define GTIIR 0x44018
1843 #define GTIER 0x4401c
1847 /* south display engine interrupt */
1848 #define SDE_CRT_HOTPLUG (1 << 11)
1849 #define SDE_PORTD_HOTPLUG (1 << 10)
1850 #define SDE_PORTC_HOTPLUG (1 << 9)
1851 #define SDE_PORTB_HOTPLUG (1 << 8)
1852 #define SDE_SDVOB_HOTPLUG (1 << 6)
1854 #define SDEISR 0xc4000
1855 #define SDEIMR 0xc4004
1856 #define SDEIIR 0xc4008
1857 #define SDEIER 0xc400c
1859 /* digital port hotplug */
1860 #define PCH_PORT_HOTPLUG 0xc4030
1861 #define PORTD_HOTPLUG_ENABLE (1 << 20)
1862 #define PORTD_PULSE_DURATION_2ms (0)
1863 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
1864 #define PORTD_PULSE_DURATION_6ms (2 << 18)
1865 #define PORTD_PULSE_DURATION_100ms (3 << 18)
1866 #define PORTD_HOTPLUG_NO_DETECT (0)
1867 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
1868 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
1869 #define PORTC_HOTPLUG_ENABLE (1 << 12)
1870 #define PORTC_PULSE_DURATION_2ms (0)
1871 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
1872 #define PORTC_PULSE_DURATION_6ms (2 << 10)
1873 #define PORTC_PULSE_DURATION_100ms (3 << 10)
1874 #define PORTC_HOTPLUG_NO_DETECT (0)
1875 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
1876 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
1877 #define PORTB_HOTPLUG_ENABLE (1 << 4)
1878 #define PORTB_PULSE_DURATION_2ms (0)
1879 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
1880 #define PORTB_PULSE_DURATION_6ms (2 << 2)
1881 #define PORTB_PULSE_DURATION_100ms (3 << 2)
1882 #define PORTB_HOTPLUG_NO_DETECT (0)
1883 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
1884 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
1886 #define PCH_GPIOA 0xc5010
1887 #define PCH_GPIOB 0xc5014
1888 #define PCH_GPIOC 0xc5018
1889 #define PCH_GPIOD 0xc501c
1890 #define PCH_GPIOE 0xc5020
1891 #define PCH_GPIOF 0xc5024
1893 #define PCH_DPLL_A 0xc6014
1894 #define PCH_DPLL_B 0xc6018
1896 #define PCH_FPA0 0xc6040
1897 #define PCH_FPA1 0xc6044
1898 #define PCH_FPB0 0xc6048
1899 #define PCH_FPB1 0xc604c
1901 #define PCH_DPLL_TEST 0xc606c
1903 #define PCH_DREF_CONTROL 0xC6200
1904 #define DREF_CONTROL_MASK 0x7fc3
1905 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
1906 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
1907 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
1908 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
1909 #define DREF_SSC_SOURCE_DISABLE (0<<11)
1910 #define DREF_SSC_SOURCE_ENABLE (2<<11)
1911 #define DREF_SSC_SOURCE_MASK (2<<11)
1912 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
1913 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
1914 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
1915 #define DREF_NONSPREAD_SOURCE_MASK (2<<9)
1916 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
1917 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
1918 #define DREF_SSC4_DOWNSPREAD (0<<6)
1919 #define DREF_SSC4_CENTERSPREAD (1<<6)
1920 #define DREF_SSC1_DISABLE (0<<1)
1921 #define DREF_SSC1_ENABLE (1<<1)
1922 #define DREF_SSC4_DISABLE (0)
1923 #define DREF_SSC4_ENABLE (1)
1925 #define PCH_RAWCLK_FREQ 0xc6204
1926 #define FDL_TP1_TIMER_SHIFT 12
1927 #define FDL_TP1_TIMER_MASK (3<<12)
1928 #define FDL_TP2_TIMER_SHIFT 10
1929 #define FDL_TP2_TIMER_MASK (3<<10)
1930 #define RAWCLK_FREQ_MASK 0x3ff
1932 #define PCH_DPLL_TMR_CFG 0xc6208
1934 #define PCH_SSC4_PARMS 0xc6210
1935 #define PCH_SSC4_AUX_PARMS 0xc6214
1939 #define TRANS_HTOTAL_A 0xe0000
1940 #define TRANS_HTOTAL_SHIFT 16
1941 #define TRANS_HACTIVE_SHIFT 0
1942 #define TRANS_HBLANK_A 0xe0004
1943 #define TRANS_HBLANK_END_SHIFT 16
1944 #define TRANS_HBLANK_START_SHIFT 0
1945 #define TRANS_HSYNC_A 0xe0008
1946 #define TRANS_HSYNC_END_SHIFT 16
1947 #define TRANS_HSYNC_START_SHIFT 0
1948 #define TRANS_VTOTAL_A 0xe000c
1949 #define TRANS_VTOTAL_SHIFT 16
1950 #define TRANS_VACTIVE_SHIFT 0
1951 #define TRANS_VBLANK_A 0xe0010
1952 #define TRANS_VBLANK_END_SHIFT 16
1953 #define TRANS_VBLANK_START_SHIFT 0
1954 #define TRANS_VSYNC_A 0xe0014
1955 #define TRANS_VSYNC_END_SHIFT 16
1956 #define TRANS_VSYNC_START_SHIFT 0
1958 #define TRANSA_DATA_M1 0xe0030
1959 #define TRANSA_DATA_N1 0xe0034
1960 #define TRANSA_DATA_M2 0xe0038
1961 #define TRANSA_DATA_N2 0xe003c
1962 #define TRANSA_DP_LINK_M1 0xe0040
1963 #define TRANSA_DP_LINK_N1 0xe0044
1964 #define TRANSA_DP_LINK_M2 0xe0048
1965 #define TRANSA_DP_LINK_N2 0xe004c
1967 #define TRANS_HTOTAL_B 0xe1000
1968 #define TRANS_HBLANK_B 0xe1004
1969 #define TRANS_HSYNC_B 0xe1008
1970 #define TRANS_VTOTAL_B 0xe100c
1971 #define TRANS_VBLANK_B 0xe1010
1972 #define TRANS_VSYNC_B 0xe1014
1974 #define TRANSB_DATA_M1 0xe1030
1975 #define TRANSB_DATA_N1 0xe1034
1976 #define TRANSB_DATA_M2 0xe1038
1977 #define TRANSB_DATA_N2 0xe103c
1978 #define TRANSB_DP_LINK_M1 0xe1040
1979 #define TRANSB_DP_LINK_N1 0xe1044
1980 #define TRANSB_DP_LINK_M2 0xe1048
1981 #define TRANSB_DP_LINK_N2 0xe104c
1983 #define TRANSACONF 0xf0008
1984 #define TRANSBCONF 0xf1008
1985 #define TRANS_DISABLE (0<<31)
1986 #define TRANS_ENABLE (1<<31)
1987 #define TRANS_STATE_MASK (1<<30)
1988 #define TRANS_STATE_DISABLE (0<<30)
1989 #define TRANS_STATE_ENABLE (1<<30)
1990 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
1991 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
1992 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
1993 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
1994 #define TRANS_DP_AUDIO_ONLY (1<<26)
1995 #define TRANS_DP_VIDEO_AUDIO (0<<26)
1996 #define TRANS_PROGRESSIVE (0<<21)
1997 #define TRANS_8BPC (0<<5)
1998 #define TRANS_10BPC (1<<5)
1999 #define TRANS_6BPC (2<<5)
2000 #define TRANS_12BPC (3<<5)
2002 #define FDI_RXA_CHICKEN 0xc200c
2003 #define FDI_RXB_CHICKEN 0xc2010
2004 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2007 #define FDI_TXA_CTL 0x60100
2008 #define FDI_TXB_CTL 0x61100
2009 #define FDI_TX_DISABLE (0<<31)
2010 #define FDI_TX_ENABLE (1<<31)
2011 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2012 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2013 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2014 #define FDI_LINK_TRAIN_NONE (3<<28)
2015 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2016 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2017 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2018 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2019 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2020 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2021 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2022 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2023 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2024 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2025 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2026 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2027 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2028 /* IGDNG: hardwired to 1 */
2029 #define FDI_TX_PLL_ENABLE (1<<14)
2030 /* both Tx and Rx */
2031 #define FDI_SCRAMBLING_ENABLE (0<<7)
2032 #define FDI_SCRAMBLING_DISABLE (1<<7)
2034 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2035 #define FDI_RXA_CTL 0xf000c
2036 #define FDI_RXB_CTL 0xf100c
2037 #define FDI_RX_ENABLE (1<<31)
2038 #define FDI_RX_DISABLE (0<<31)
2039 /* train, dp width same as FDI_TX */
2040 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2041 #define FDI_8BPC (0<<16)
2042 #define FDI_10BPC (1<<16)
2043 #define FDI_6BPC (2<<16)
2044 #define FDI_12BPC (3<<16)
2045 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2046 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2047 #define FDI_RX_PLL_ENABLE (1<<13)
2048 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2049 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2050 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2051 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2052 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2053 #define FDI_SEL_RAWCLK (0<<4)
2054 #define FDI_SEL_PCDCLK (1<<4)
2056 #define FDI_RXA_MISC 0xf0010
2057 #define FDI_RXB_MISC 0xf1010
2058 #define FDI_RXA_TUSIZE1 0xf0030
2059 #define FDI_RXA_TUSIZE2 0xf0038
2060 #define FDI_RXB_TUSIZE1 0xf1030
2061 #define FDI_RXB_TUSIZE2 0xf1038
2063 /* FDI_RX interrupt register format */
2064 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2065 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2066 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2067 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2068 #define FDI_RX_FS_CODE_ERR (1<<6)
2069 #define FDI_RX_FE_CODE_ERR (1<<5)
2070 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2071 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2072 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2073 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2074 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2076 #define FDI_RXA_IIR 0xf0014
2077 #define FDI_RXA_IMR 0xf0018
2078 #define FDI_RXB_IIR 0xf1014
2079 #define FDI_RXB_IMR 0xf1018
2081 #define FDI_PLL_CTL_1 0xfe000
2082 #define FDI_PLL_CTL_2 0xfe004
2085 #define PCH_ADPA 0xe1100
2086 #define ADPA_TRANS_SELECT_MASK (1<<30)
2087 #define ADPA_TRANS_A_SELECT 0
2088 #define ADPA_TRANS_B_SELECT (1<<30)
2089 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2090 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2091 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2092 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2093 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2094 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2095 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2096 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2097 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2098 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2099 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2100 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2101 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2102 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2103 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2104 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2105 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2106 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2107 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2110 #define HDMIB 0xe1140
2111 #define PORT_ENABLE (1 << 31)
2112 #define TRANSCODER_A (0)
2113 #define TRANSCODER_B (1 << 30)
2114 #define COLOR_FORMAT_8bpc (0)
2115 #define COLOR_FORMAT_12bpc (3 << 26)
2116 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2117 #define SDVO_ENCODING (0)
2118 #define TMDS_ENCODING (2 << 10)
2119 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2120 #define SDVOB_BORDER_ENABLE (1 << 7)
2121 #define AUDIO_ENABLE (1 << 6)
2122 #define VSYNC_ACTIVE_HIGH (1 << 4)
2123 #define HSYNC_ACTIVE_HIGH (1 << 3)
2124 #define PORT_DETECTED (1 << 2)
2126 #define HDMIC 0xe1150
2127 #define HDMID 0xe1160
2129 #define PCH_LVDS 0xe1180
2130 #define LVDS_DETECTED (1 << 1)
2132 #define BLC_PWM_CPU_CTL2 0x48250
2133 #define PWM_ENABLE (1 << 31)
2134 #define PWM_PIPE_A (0 << 29)
2135 #define PWM_PIPE_B (1 << 29)
2136 #define BLC_PWM_CPU_CTL 0x48254
2138 #define BLC_PWM_PCH_CTL1 0xc8250
2139 #define PWM_PCH_ENABLE (1 << 31)
2140 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2141 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2142 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2143 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2145 #define BLC_PWM_PCH_CTL2 0xc8254
2147 #define PCH_PP_STATUS 0xc7200
2148 #define PCH_PP_CONTROL 0xc7204
2149 #define EDP_FORCE_VDD (1 << 3)
2150 #define EDP_BLC_ENABLE (1 << 2)
2151 #define PANEL_POWER_RESET (1 << 1)
2152 #define PANEL_POWER_OFF (0 << 0)
2153 #define PANEL_POWER_ON (1 << 0)
2154 #define PCH_PP_ON_DELAYS 0xc7208
2155 #define EDP_PANEL (1 << 30)
2156 #define PCH_PP_OFF_DELAYS 0xc720c
2157 #define PCH_PP_DIVISOR 0xc7210
2159 #endif /* _I915_REG_H_ */
git.openpandora.org / pandora-kernel.git / blob