1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #define MAX_NOPID ((u32)~0)
40 * Interrupts that are always left unmasked.
42 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
43 * we leave them always unmasked in IMR and then control enabling them through
46 #define I915_INTERRUPT_ENABLE_FIX \
47 (I915_ASLE_INTERRUPT | \
48 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
49 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
50 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
51 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
52 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54 /** Interrupts that we mask and unmask at runtime. */
55 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
57 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
58 PIPE_VBLANK_INTERRUPT_STATUS)
60 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
61 PIPE_VBLANK_INTERRUPT_ENABLE)
63 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
64 DRM_I915_VBLANK_PIPE_B)
67 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
69 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
70 dev_priv->gt_irq_mask_reg &= ~mask;
71 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
72 (void) I915_READ(GTIMR);
77 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
79 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
80 dev_priv->gt_irq_mask_reg |= mask;
81 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
82 (void) I915_READ(GTIMR);
86 /* For display hotplug interrupt */
88 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
90 if ((dev_priv->irq_mask_reg & mask) != 0) {
91 dev_priv->irq_mask_reg &= ~mask;
92 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
93 (void) I915_READ(DEIMR);
98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
100 if ((dev_priv->irq_mask_reg & mask) != mask) {
101 dev_priv->irq_mask_reg |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
103 (void) I915_READ(DEIMR);
108 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110 if ((dev_priv->irq_mask_reg & mask) != 0) {
111 dev_priv->irq_mask_reg &= ~mask;
112 I915_WRITE(IMR, dev_priv->irq_mask_reg);
113 (void) I915_READ(IMR);
118 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120 if ((dev_priv->irq_mask_reg & mask) != mask) {
121 dev_priv->irq_mask_reg |= mask;
122 I915_WRITE(IMR, dev_priv->irq_mask_reg);
123 (void) I915_READ(IMR);
128 i915_pipestat(int pipe)
138 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140 if ((dev_priv->pipestat[pipe] & mask) != mask) {
141 u32 reg = i915_pipestat(pipe);
143 dev_priv->pipestat[pipe] |= mask;
144 /* Enable the interrupt, clear any pending status */
145 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
146 (void) I915_READ(reg);
151 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153 if ((dev_priv->pipestat[pipe] & mask) != 0) {
154 u32 reg = i915_pipestat(pipe);
156 dev_priv->pipestat[pipe] &= ~mask;
157 I915_WRITE(reg, dev_priv->pipestat[pipe]);
158 (void) I915_READ(reg);
163 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 void intel_enable_asle (struct drm_device *dev)
167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169 if (IS_IRONLAKE(dev))
170 ironlake_enable_display_irq(dev_priv, DE_GSE);
172 i915_enable_pipestat(dev_priv, 1,
173 I915_LEGACY_BLC_EVENT_ENABLE);
177 * i915_pipe_enabled - check if a pipe is enabled
179 * @pipe: pipe to check
181 * Reading certain registers when the pipe is disabled can hang the chip.
182 * Use this routine to make sure the PLL is running and the pipe is active
183 * before reading such registers if unsure.
186 i915_pipe_enabled(struct drm_device *dev, int pipe)
188 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
189 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
191 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
197 /* Called from drm generic code, passed a 'crtc', which
198 * we use as a pipe index
200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
203 unsigned long high_frame;
204 unsigned long low_frame;
205 u32 high1, high2, low, count;
207 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
208 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
210 if (!i915_pipe_enabled(dev, pipe)) {
211 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
217 * High & low register fields aren't synchronized, so make sure
218 * we get a low value that's stable across two reads of the high
222 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
223 PIPE_FRAME_HIGH_SHIFT);
224 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
225 PIPE_FRAME_LOW_SHIFT);
226 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
227 PIPE_FRAME_HIGH_SHIFT);
228 } while (high1 != high2);
230 count = (high1 << 8) | low;
235 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
237 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
238 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
240 if (!i915_pipe_enabled(dev, pipe)) {
241 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
246 return I915_READ(reg);
250 * Handle hotplug events outside the interrupt handler proper.
252 static void i915_hotplug_work_func(struct work_struct *work)
254 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
256 struct drm_device *dev = dev_priv->dev;
257 struct drm_mode_config *mode_config = &dev->mode_config;
258 struct drm_connector *connector;
260 if (mode_config->num_connector) {
261 list_for_each_entry(connector, &mode_config->connector_list, head) {
262 struct intel_output *intel_output = to_intel_output(connector);
264 if (intel_output->hot_plug)
265 (*intel_output->hot_plug) (intel_output);
268 /* Just fire off a uevent and let userspace tell us what to do */
269 drm_sysfs_hotplug_event(dev);
272 static void i915_handle_rps_change(struct drm_device *dev)
274 drm_i915_private_t *dev_priv = dev->dev_private;
275 u32 slow_up, slow_down, max_avg, min_avg;
277 u8 new_delay = dev_priv->cur_delay;
279 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
280 slow_up = I915_READ(RCPREVBSYTUPAVG);
281 slow_down = I915_READ(RCPREVBSYTDNAVG);
282 max_avg = I915_READ(RCBMAXAVG);
283 min_avg = I915_READ(RCBMINAVG);
285 /* Handle RCS change request from hw */
286 if (slow_up > max_avg) {
287 if (dev_priv->cur_delay != dev_priv->max_delay)
288 new_delay = dev_priv->cur_delay - 1;
289 if (new_delay < dev_priv->max_delay)
290 new_delay = dev_priv->max_delay;
291 } else if (slow_down < min_avg) {
292 if (dev_priv->cur_delay != dev_priv->min_delay)
293 new_delay = dev_priv->cur_delay + 1;
294 if (new_delay > dev_priv->min_delay)
295 new_delay = dev_priv->min_delay;
298 DRM_DEBUG("rps change requested: %d -> %d\n",
299 dev_priv->cur_delay, new_delay);
301 rgvswctl = I915_READ(MEMSWCTL);
302 if (rgvswctl & MEMCTL_CMD_STS) {
303 DRM_ERROR("gpu slow, RCS change rejected\n");
304 return; /* still slow with another command */
307 /* Program the new state */
308 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
309 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
310 I915_WRITE(MEMSWCTL, rgvswctl);
311 POSTING_READ(MEMSWCTL);
313 rgvswctl |= MEMCTL_CMD_STS;
314 I915_WRITE(MEMSWCTL, rgvswctl);
316 dev_priv->cur_delay = new_delay;
318 DRM_DEBUG("rps changed\n");
323 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
325 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
327 u32 de_iir, gt_iir, de_ier, pch_iir;
328 struct drm_i915_master_private *master_priv;
330 /* disable master interrupt before clearing iir */
331 de_ier = I915_READ(DEIER);
332 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
333 (void)I915_READ(DEIER);
335 de_iir = I915_READ(DEIIR);
336 gt_iir = I915_READ(GTIIR);
337 pch_iir = I915_READ(SDEIIR);
339 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
344 if (dev->primary->master) {
345 master_priv = dev->primary->master->driver_priv;
346 if (master_priv->sarea_priv)
347 master_priv->sarea_priv->last_dispatch =
348 READ_BREADCRUMB(dev_priv);
351 if (gt_iir & GT_USER_INTERRUPT) {
352 u32 seqno = i915_get_gem_seqno(dev);
353 dev_priv->mm.irq_gem_seqno = seqno;
354 trace_i915_gem_request_complete(dev, seqno);
355 DRM_WAKEUP(&dev_priv->irq_queue);
356 dev_priv->hangcheck_count = 0;
357 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
361 ironlake_opregion_gse_intr(dev);
363 if (de_iir & DE_PLANEA_FLIP_DONE) {
364 intel_prepare_page_flip(dev, 0);
365 intel_finish_page_flip(dev, 0);
368 if (de_iir & DE_PLANEB_FLIP_DONE) {
369 intel_prepare_page_flip(dev, 1);
370 intel_finish_page_flip(dev, 1);
373 if (de_iir & DE_PIPEA_VBLANK)
374 drm_handle_vblank(dev, 0);
376 if (de_iir & DE_PIPEB_VBLANK)
377 drm_handle_vblank(dev, 1);
379 /* check event from PCH */
380 if ((de_iir & DE_PCH_EVENT) &&
381 (pch_iir & SDE_HOTPLUG_MASK)) {
382 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
385 if (de_iir & DE_PCU_EVENT) {
386 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
387 i915_handle_rps_change(dev);
390 /* should clear PCH hotplug event before clear CPU irq */
391 I915_WRITE(SDEIIR, pch_iir);
392 I915_WRITE(GTIIR, gt_iir);
393 I915_WRITE(DEIIR, de_iir);
396 I915_WRITE(DEIER, de_ier);
397 (void)I915_READ(DEIER);
403 * i915_error_work_func - do process context error handling work
406 * Fire an error uevent so userspace can see that a hang or error
409 static void i915_error_work_func(struct work_struct *work)
411 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
413 struct drm_device *dev = dev_priv->dev;
414 char *error_event[] = { "ERROR=1", NULL };
415 char *reset_event[] = { "RESET=1", NULL };
416 char *reset_done_event[] = { "ERROR=0", NULL };
418 DRM_DEBUG_DRIVER("generating error event\n");
419 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
421 if (atomic_read(&dev_priv->mm.wedged)) {
423 DRM_DEBUG_DRIVER("resetting chip\n");
424 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
425 if (!i965_reset(dev, GDRST_RENDER)) {
426 atomic_set(&dev_priv->mm.wedged, 0);
427 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
430 DRM_DEBUG_DRIVER("reboot required\n");
436 * i915_capture_error_state - capture an error record for later analysis
439 * Should be called when an error is detected (either a hang or an error
440 * interrupt) to capture error state from the time of the error. Fills
441 * out a structure which becomes available in debugfs for user level tools
444 static void i915_capture_error_state(struct drm_device *dev)
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 struct drm_i915_error_state *error;
450 spin_lock_irqsave(&dev_priv->error_lock, flags);
451 if (dev_priv->first_error)
454 error = kmalloc(sizeof(*error), GFP_ATOMIC);
456 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
460 error->eir = I915_READ(EIR);
461 error->pgtbl_er = I915_READ(PGTBL_ER);
462 error->pipeastat = I915_READ(PIPEASTAT);
463 error->pipebstat = I915_READ(PIPEBSTAT);
464 error->instpm = I915_READ(INSTPM);
465 if (!IS_I965G(dev)) {
466 error->ipeir = I915_READ(IPEIR);
467 error->ipehr = I915_READ(IPEHR);
468 error->instdone = I915_READ(INSTDONE);
469 error->acthd = I915_READ(ACTHD);
471 error->ipeir = I915_READ(IPEIR_I965);
472 error->ipehr = I915_READ(IPEHR_I965);
473 error->instdone = I915_READ(INSTDONE_I965);
474 error->instps = I915_READ(INSTPS);
475 error->instdone1 = I915_READ(INSTDONE1);
476 error->acthd = I915_READ(ACTHD_I965);
479 do_gettimeofday(&error->time);
481 dev_priv->first_error = error;
484 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
488 * i915_handle_error - handle an error interrupt
491 * Do some basic checking of regsiter state at error interrupt time and
492 * dump it to the syslog. Also call i915_capture_error_state() to make
493 * sure we get a record and make it available in debugfs. Fire a uevent
494 * so userspace knows something bad happened (should trigger collection
495 * of a ring dump etc.).
497 static void i915_handle_error(struct drm_device *dev, bool wedged)
499 struct drm_i915_private *dev_priv = dev->dev_private;
500 u32 eir = I915_READ(EIR);
501 u32 pipea_stats = I915_READ(PIPEASTAT);
502 u32 pipeb_stats = I915_READ(PIPEBSTAT);
504 i915_capture_error_state(dev);
506 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
510 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
511 u32 ipeir = I915_READ(IPEIR_I965);
513 printk(KERN_ERR " IPEIR: 0x%08x\n",
514 I915_READ(IPEIR_I965));
515 printk(KERN_ERR " IPEHR: 0x%08x\n",
516 I915_READ(IPEHR_I965));
517 printk(KERN_ERR " INSTDONE: 0x%08x\n",
518 I915_READ(INSTDONE_I965));
519 printk(KERN_ERR " INSTPS: 0x%08x\n",
521 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
522 I915_READ(INSTDONE1));
523 printk(KERN_ERR " ACTHD: 0x%08x\n",
524 I915_READ(ACTHD_I965));
525 I915_WRITE(IPEIR_I965, ipeir);
526 (void)I915_READ(IPEIR_I965);
528 if (eir & GM45_ERROR_PAGE_TABLE) {
529 u32 pgtbl_err = I915_READ(PGTBL_ER);
530 printk(KERN_ERR "page table error\n");
531 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
533 I915_WRITE(PGTBL_ER, pgtbl_err);
534 (void)I915_READ(PGTBL_ER);
539 if (eir & I915_ERROR_PAGE_TABLE) {
540 u32 pgtbl_err = I915_READ(PGTBL_ER);
541 printk(KERN_ERR "page table error\n");
542 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
544 I915_WRITE(PGTBL_ER, pgtbl_err);
545 (void)I915_READ(PGTBL_ER);
549 if (eir & I915_ERROR_MEMORY_REFRESH) {
550 printk(KERN_ERR "memory refresh error\n");
551 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
553 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
555 /* pipestat has already been acked */
557 if (eir & I915_ERROR_INSTRUCTION) {
558 printk(KERN_ERR "instruction error\n");
559 printk(KERN_ERR " INSTPM: 0x%08x\n",
561 if (!IS_I965G(dev)) {
562 u32 ipeir = I915_READ(IPEIR);
564 printk(KERN_ERR " IPEIR: 0x%08x\n",
566 printk(KERN_ERR " IPEHR: 0x%08x\n",
568 printk(KERN_ERR " INSTDONE: 0x%08x\n",
569 I915_READ(INSTDONE));
570 printk(KERN_ERR " ACTHD: 0x%08x\n",
572 I915_WRITE(IPEIR, ipeir);
573 (void)I915_READ(IPEIR);
575 u32 ipeir = I915_READ(IPEIR_I965);
577 printk(KERN_ERR " IPEIR: 0x%08x\n",
578 I915_READ(IPEIR_I965));
579 printk(KERN_ERR " IPEHR: 0x%08x\n",
580 I915_READ(IPEHR_I965));
581 printk(KERN_ERR " INSTDONE: 0x%08x\n",
582 I915_READ(INSTDONE_I965));
583 printk(KERN_ERR " INSTPS: 0x%08x\n",
585 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
586 I915_READ(INSTDONE1));
587 printk(KERN_ERR " ACTHD: 0x%08x\n",
588 I915_READ(ACTHD_I965));
589 I915_WRITE(IPEIR_I965, ipeir);
590 (void)I915_READ(IPEIR_I965);
594 I915_WRITE(EIR, eir);
595 (void)I915_READ(EIR);
596 eir = I915_READ(EIR);
599 * some errors might have become stuck,
602 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
603 I915_WRITE(EMR, I915_READ(EMR) | eir);
604 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
608 atomic_set(&dev_priv->mm.wedged, 1);
611 * Wakeup waiting processes so they don't hang
613 DRM_WAKEUP(&dev_priv->irq_queue);
616 queue_work(dev_priv->wq, &dev_priv->error_work);
619 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
621 struct drm_device *dev = (struct drm_device *) arg;
622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
623 struct drm_i915_master_private *master_priv;
625 u32 pipea_stats, pipeb_stats;
629 unsigned long irqflags;
633 atomic_inc(&dev_priv->irq_received);
635 if (IS_IRONLAKE(dev))
636 return ironlake_irq_handler(dev);
638 iir = I915_READ(IIR);
641 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
642 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
644 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
645 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
649 irq_received = iir != 0;
651 /* Can't rely on pipestat interrupt bit in iir as it might
652 * have been cleared after the pipestat interrupt was received.
653 * It doesn't set the bit in iir again, but it still produces
654 * interrupts (for non-MSI).
656 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
657 pipea_stats = I915_READ(PIPEASTAT);
658 pipeb_stats = I915_READ(PIPEBSTAT);
660 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
661 i915_handle_error(dev, false);
664 * Clear the PIPE(A|B)STAT regs before the IIR
666 if (pipea_stats & 0x8000ffff) {
667 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
668 DRM_DEBUG_DRIVER("pipe a underrun\n");
669 I915_WRITE(PIPEASTAT, pipea_stats);
673 if (pipeb_stats & 0x8000ffff) {
674 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
675 DRM_DEBUG_DRIVER("pipe b underrun\n");
676 I915_WRITE(PIPEBSTAT, pipeb_stats);
679 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
686 /* Consume port. Then clear IIR or we'll miss events */
687 if ((I915_HAS_HOTPLUG(dev)) &&
688 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
689 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
691 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
693 if (hotplug_status & dev_priv->hotplug_supported_mask)
694 queue_work(dev_priv->wq,
695 &dev_priv->hotplug_work);
697 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
698 I915_READ(PORT_HOTPLUG_STAT);
701 I915_WRITE(IIR, iir);
702 new_iir = I915_READ(IIR); /* Flush posted writes */
704 if (dev->primary->master) {
705 master_priv = dev->primary->master->driver_priv;
706 if (master_priv->sarea_priv)
707 master_priv->sarea_priv->last_dispatch =
708 READ_BREADCRUMB(dev_priv);
711 if (iir & I915_USER_INTERRUPT) {
712 u32 seqno = i915_get_gem_seqno(dev);
713 dev_priv->mm.irq_gem_seqno = seqno;
714 trace_i915_gem_request_complete(dev, seqno);
715 DRM_WAKEUP(&dev_priv->irq_queue);
716 dev_priv->hangcheck_count = 0;
717 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
720 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
721 intel_prepare_page_flip(dev, 0);
723 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
724 intel_prepare_page_flip(dev, 1);
726 if (pipea_stats & vblank_status) {
728 drm_handle_vblank(dev, 0);
729 intel_finish_page_flip(dev, 0);
732 if (pipeb_stats & vblank_status) {
734 drm_handle_vblank(dev, 1);
735 intel_finish_page_flip(dev, 1);
738 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
739 (iir & I915_ASLE_INTERRUPT))
740 opregion_asle_intr(dev);
742 /* With MSI, interrupts are only generated when iir
743 * transitions from zero to nonzero. If another bit got
744 * set while we were handling the existing iir bits, then
745 * we would never get another interrupt.
747 * This is fine on non-MSI as well, as if we hit this path
748 * we avoid exiting the interrupt handler only to generate
751 * Note that for MSI this could cause a stray interrupt report
752 * if an interrupt landed in the time between writing IIR and
753 * the posting read. This should be rare enough to never
754 * trigger the 99% of 100,000 interrupts test for disabling
763 static int i915_emit_irq(struct drm_device * dev)
765 drm_i915_private_t *dev_priv = dev->dev_private;
766 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
769 i915_kernel_lost_context(dev);
771 DRM_DEBUG_DRIVER("\n");
774 if (dev_priv->counter > 0x7FFFFFFFUL)
775 dev_priv->counter = 1;
776 if (master_priv->sarea_priv)
777 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
780 OUT_RING(MI_STORE_DWORD_INDEX);
781 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
782 OUT_RING(dev_priv->counter);
783 OUT_RING(MI_USER_INTERRUPT);
786 return dev_priv->counter;
789 void i915_user_irq_get(struct drm_device *dev)
791 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
792 unsigned long irqflags;
794 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
795 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
796 if (IS_IRONLAKE(dev))
797 ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
799 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
801 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
804 void i915_user_irq_put(struct drm_device *dev)
806 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
807 unsigned long irqflags;
809 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
810 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
811 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
812 if (IS_IRONLAKE(dev))
813 ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
815 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
817 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
820 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
822 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
824 if (dev_priv->trace_irq_seqno == 0)
825 i915_user_irq_get(dev);
827 dev_priv->trace_irq_seqno = seqno;
830 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
832 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
833 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
836 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
837 READ_BREADCRUMB(dev_priv));
839 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
840 if (master_priv->sarea_priv)
841 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
845 if (master_priv->sarea_priv)
846 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
848 i915_user_irq_get(dev);
849 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
850 READ_BREADCRUMB(dev_priv) >= irq_nr);
851 i915_user_irq_put(dev);
854 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
855 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
861 /* Needs the lock as it touches the ring.
863 int i915_irq_emit(struct drm_device *dev, void *data,
864 struct drm_file *file_priv)
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 drm_i915_irq_emit_t *emit = data;
870 if (!dev_priv || !dev_priv->ring.virtual_start) {
871 DRM_ERROR("called with no initialization\n");
875 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
877 mutex_lock(&dev->struct_mutex);
878 result = i915_emit_irq(dev);
879 mutex_unlock(&dev->struct_mutex);
881 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
882 DRM_ERROR("copy_to_user\n");
889 /* Doesn't need the hardware lock.
891 int i915_irq_wait(struct drm_device *dev, void *data,
892 struct drm_file *file_priv)
894 drm_i915_private_t *dev_priv = dev->dev_private;
895 drm_i915_irq_wait_t *irqwait = data;
898 DRM_ERROR("called with no initialization\n");
902 return i915_wait_irq(dev, irqwait->irq_seq);
905 /* Called from drm generic code, passed 'crtc' which
906 * we use as a pipe index
908 int i915_enable_vblank(struct drm_device *dev, int pipe)
910 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
911 unsigned long irqflags;
912 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
915 pipeconf = I915_READ(pipeconf_reg);
916 if (!(pipeconf & PIPEACONF_ENABLE))
919 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
920 if (IS_IRONLAKE(dev))
921 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
922 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
923 else if (IS_I965G(dev))
924 i915_enable_pipestat(dev_priv, pipe,
925 PIPE_START_VBLANK_INTERRUPT_ENABLE);
927 i915_enable_pipestat(dev_priv, pipe,
928 PIPE_VBLANK_INTERRUPT_ENABLE);
929 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
933 /* Called from drm generic code, passed 'crtc' which
934 * we use as a pipe index
936 void i915_disable_vblank(struct drm_device *dev, int pipe)
938 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
939 unsigned long irqflags;
941 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
942 if (IS_IRONLAKE(dev))
943 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
944 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
946 i915_disable_pipestat(dev_priv, pipe,
947 PIPE_VBLANK_INTERRUPT_ENABLE |
948 PIPE_START_VBLANK_INTERRUPT_ENABLE);
949 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
952 void i915_enable_interrupt (struct drm_device *dev)
954 struct drm_i915_private *dev_priv = dev->dev_private;
956 if (!IS_IRONLAKE(dev))
957 opregion_enable_asle(dev);
958 dev_priv->irq_enabled = 1;
962 /* Set the vblank monitor pipe
964 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
965 struct drm_file *file_priv)
967 drm_i915_private_t *dev_priv = dev->dev_private;
970 DRM_ERROR("called with no initialization\n");
977 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
978 struct drm_file *file_priv)
980 drm_i915_private_t *dev_priv = dev->dev_private;
981 drm_i915_vblank_pipe_t *pipe = data;
984 DRM_ERROR("called with no initialization\n");
988 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
994 * Schedule buffer swap at given vertical blank.
996 int i915_vblank_swap(struct drm_device *dev, void *data,
997 struct drm_file *file_priv)
999 /* The delayed swap mechanism was fundamentally racy, and has been
1000 * removed. The model was that the client requested a delayed flip/swap
1001 * from the kernel, then waited for vblank before continuing to perform
1002 * rendering. The problem was that the kernel might wake the client
1003 * up before it dispatched the vblank swap (since the lock has to be
1004 * held while touching the ringbuffer), in which case the client would
1005 * clear and start the next frame before the swap occurred, and
1006 * flicker would occur in addition to likely missing the vblank.
1008 * In the absence of this ioctl, userland falls back to a correct path
1009 * of waiting for a vblank, then dispatching the swap on its own.
1010 * Context switching to userland and back is plenty fast enough for
1011 * meeting the requirements of vblank swapping.
1016 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1017 drm_i915_private_t *dev_priv = dev->dev_private;
1018 return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1022 * This is called when the chip hasn't reported back with completed
1023 * batchbuffers in a long time. The first time this is called we simply record
1024 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1025 * again, we assume the chip is wedged and try to fix it.
1027 void i915_hangcheck_elapsed(unsigned long data)
1029 struct drm_device *dev = (struct drm_device *)data;
1030 drm_i915_private_t *dev_priv = dev->dev_private;
1034 acthd = I915_READ(ACTHD);
1036 acthd = I915_READ(ACTHD_I965);
1038 /* If all work is done then ACTHD clearly hasn't advanced. */
1039 if (list_empty(&dev_priv->mm.request_list) ||
1040 i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1041 dev_priv->hangcheck_count = 0;
1045 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1046 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1047 i915_handle_error(dev, true);
1051 /* Reset timer case chip hangs without another request being added */
1052 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1054 if (acthd != dev_priv->last_acthd)
1055 dev_priv->hangcheck_count = 0;
1057 dev_priv->hangcheck_count++;
1059 dev_priv->last_acthd = acthd;
1064 static void ironlake_irq_preinstall(struct drm_device *dev)
1066 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1068 I915_WRITE(HWSTAM, 0xeffe);
1070 /* XXX hotplug from PCH */
1072 I915_WRITE(DEIMR, 0xffffffff);
1073 I915_WRITE(DEIER, 0x0);
1074 (void) I915_READ(DEIER);
1077 I915_WRITE(GTIMR, 0xffffffff);
1078 I915_WRITE(GTIER, 0x0);
1079 (void) I915_READ(GTIER);
1081 /* south display irq */
1082 I915_WRITE(SDEIMR, 0xffffffff);
1083 I915_WRITE(SDEIER, 0x0);
1084 (void) I915_READ(SDEIER);
1087 static int ironlake_irq_postinstall(struct drm_device *dev)
1089 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1090 /* enable kind of interrupts always enabled */
1091 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1092 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1093 u32 render_mask = GT_USER_INTERRUPT;
1094 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1095 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1097 dev_priv->irq_mask_reg = ~display_mask;
1098 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1100 /* should always can generate irq */
1101 I915_WRITE(DEIIR, I915_READ(DEIIR));
1102 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1103 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1104 (void) I915_READ(DEIER);
1106 /* user interrupt should be enabled, but masked initial */
1107 dev_priv->gt_irq_mask_reg = 0xffffffff;
1108 dev_priv->gt_irq_enable_reg = render_mask;
1110 I915_WRITE(GTIIR, I915_READ(GTIIR));
1111 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1112 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1113 (void) I915_READ(GTIER);
1115 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1116 dev_priv->pch_irq_enable_reg = hotplug_mask;
1118 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1119 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1120 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1121 (void) I915_READ(SDEIER);
1123 if (IS_IRONLAKE_M(dev)) {
1124 /* Clear & enable PCU event interrupts */
1125 I915_WRITE(DEIIR, DE_PCU_EVENT);
1126 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1127 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1133 void i915_driver_irq_preinstall(struct drm_device * dev)
1135 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1137 atomic_set(&dev_priv->irq_received, 0);
1139 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1140 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1142 if (IS_IRONLAKE(dev)) {
1143 ironlake_irq_preinstall(dev);
1147 if (I915_HAS_HOTPLUG(dev)) {
1148 I915_WRITE(PORT_HOTPLUG_EN, 0);
1149 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1152 I915_WRITE(HWSTAM, 0xeffe);
1153 I915_WRITE(PIPEASTAT, 0);
1154 I915_WRITE(PIPEBSTAT, 0);
1155 I915_WRITE(IMR, 0xffffffff);
1156 I915_WRITE(IER, 0x0);
1157 (void) I915_READ(IER);
1161 * Must be called after intel_modeset_init or hotplug interrupts won't be
1162 * enabled correctly.
1164 int i915_driver_irq_postinstall(struct drm_device *dev)
1166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1167 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1170 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1172 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1174 if (IS_IRONLAKE(dev))
1175 return ironlake_irq_postinstall(dev);
1177 /* Unmask the interrupts that we always want on. */
1178 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1180 dev_priv->pipestat[0] = 0;
1181 dev_priv->pipestat[1] = 0;
1183 if (I915_HAS_HOTPLUG(dev)) {
1184 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1186 /* Note HDMI and DP share bits */
1187 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1188 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1189 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1190 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1191 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1192 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1193 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1194 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1195 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1196 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1197 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1198 hotplug_en |= CRT_HOTPLUG_INT_EN;
1199 /* Ignore TV since it's buggy */
1201 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1203 /* Enable in IER... */
1204 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1205 /* and unmask in IMR */
1206 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1210 * Enable some error detection, note the instruction error mask
1211 * bit is reserved, so we leave it masked.
1214 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1215 GM45_ERROR_MEM_PRIV |
1216 GM45_ERROR_CP_PRIV |
1217 I915_ERROR_MEMORY_REFRESH);
1219 error_mask = ~(I915_ERROR_PAGE_TABLE |
1220 I915_ERROR_MEMORY_REFRESH);
1222 I915_WRITE(EMR, error_mask);
1224 /* Disable pipe interrupt enables, clear pending pipe status */
1225 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1226 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1227 /* Clear pending interrupt status */
1228 I915_WRITE(IIR, I915_READ(IIR));
1230 I915_WRITE(IER, enable_mask);
1231 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1232 (void) I915_READ(IER);
1234 opregion_enable_asle(dev);
1239 static void ironlake_irq_uninstall(struct drm_device *dev)
1241 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1242 I915_WRITE(HWSTAM, 0xffffffff);
1244 I915_WRITE(DEIMR, 0xffffffff);
1245 I915_WRITE(DEIER, 0x0);
1246 I915_WRITE(DEIIR, I915_READ(DEIIR));
1248 I915_WRITE(GTIMR, 0xffffffff);
1249 I915_WRITE(GTIER, 0x0);
1250 I915_WRITE(GTIIR, I915_READ(GTIIR));
1253 void i915_driver_irq_uninstall(struct drm_device * dev)
1255 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1260 dev_priv->vblank_pipe = 0;
1262 if (IS_IRONLAKE(dev)) {
1263 ironlake_irq_uninstall(dev);
1267 if (I915_HAS_HOTPLUG(dev)) {
1268 I915_WRITE(PORT_HOTPLUG_EN, 0);
1269 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1272 I915_WRITE(HWSTAM, 0xffffffff);
1273 I915_WRITE(PIPEASTAT, 0);
1274 I915_WRITE(PIPEBSTAT, 0);
1275 I915_WRITE(IMR, 0xffffffff);
1276 I915_WRITE(IER, 0x0);
1278 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1279 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1280 I915_WRITE(IIR, I915_READ(IIR));