drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static void notify_ring(struct drm_device *dev,
 297                         struct intel_ring_buffer *ring)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         u32 seqno = ring->get_seqno(dev, ring);
 301         ring->irq_gem_seqno = seqno;
 302         trace_i915_gem_request_complete(dev, seqno);
 303         wake_up_all(&ring->irq_queue);
 304         dev_priv->hangcheck_count = 0;
 305         mod_timer(&dev_priv->hangcheck_timer,
 306                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 307 }
 308
 309 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 310 {
 311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 312         int ret = IRQ_NONE;
 313         u32 de_iir, gt_iir, de_ier, pch_iir;
 314         u32 hotplug_mask;
 315         struct drm_i915_master_private *master_priv;
 316         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 317
 318         if (IS_GEN6(dev))
 319                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 320
 321         /* disable master interrupt before clearing iir  */
 322         de_ier = I915_READ(DEIER);
 323         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 324         (void)I915_READ(DEIER);
 325
 326         de_iir = I915_READ(DEIIR);
 327         gt_iir = I915_READ(GTIIR);
 328         pch_iir = I915_READ(SDEIIR);
 329
 330         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 331                 goto done;
 332
 333         if (HAS_PCH_CPT(dev))
 334                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 335         else
 336                 hotplug_mask = SDE_HOTPLUG_MASK;
 337
 338         ret = IRQ_HANDLED;
 339
 340         if (dev->primary->master) {
 341                 master_priv = dev->primary->master->driver_priv;
 342                 if (master_priv->sarea_priv)
 343                         master_priv->sarea_priv->last_dispatch =
 344                                 READ_BREADCRUMB(dev_priv);
 345         }
 346
 347         if (gt_iir & GT_PIPE_NOTIFY)
 348                 notify_ring(dev, &dev_priv->render_ring);
 349         if (gt_iir & bsd_usr_interrupt)
 350                 notify_ring(dev, &dev_priv->bsd_ring);
 351         if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
 352                 notify_ring(dev, &dev_priv->blt_ring);
 353
 354         if (de_iir & DE_GSE)
 355                 intel_opregion_gse_intr(dev);
 356
 357         if (de_iir & DE_PLANEA_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 0);
 359                 intel_finish_page_flip_plane(dev, 0);
 360         }
 361
 362         if (de_iir & DE_PLANEB_FLIP_DONE) {
 363                 intel_prepare_page_flip(dev, 1);
 364                 intel_finish_page_flip_plane(dev, 1);
 365         }
 366
 367         if (de_iir & DE_PIPEA_VBLANK)
 368                 drm_handle_vblank(dev, 0);
 369
 370         if (de_iir & DE_PIPEB_VBLANK)
 371                 drm_handle_vblank(dev, 1);
 372
 373         /* check event from PCH */
 374         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 375                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 376
 377         if (de_iir & DE_PCU_EVENT) {
 378                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 379                 i915_handle_rps_change(dev);
 380         }
 381
 382         /* should clear PCH hotplug event before clear CPU irq */
 383         I915_WRITE(SDEIIR, pch_iir);
 384         I915_WRITE(GTIIR, gt_iir);
 385         I915_WRITE(DEIIR, de_iir);
 386
 387 done:
 388         I915_WRITE(DEIER, de_ier);
 389         (void)I915_READ(DEIER);
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * i915_error_work_func - do process context error handling work
 396  * @work: work struct
 397  *
 398  * Fire an error uevent so userspace can see that a hang or error
 399  * was detected.
 400  */
 401 static void i915_error_work_func(struct work_struct *work)
 402 {
 403         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 404                                                     error_work);
 405         struct drm_device *dev = dev_priv->dev;
 406         char *error_event[] = { "ERROR=1", NULL };
 407         char *reset_event[] = { "RESET=1", NULL };
 408         char *reset_done_event[] = { "ERROR=0", NULL };
 409
 410         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 411
 412         if (atomic_read(&dev_priv->mm.wedged)) {
 413                 DRM_DEBUG_DRIVER("resetting chip\n");
 414                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 415                 if (!i915_reset(dev, GRDOM_RENDER)) {
 416                         atomic_set(&dev_priv->mm.wedged, 0);
 417                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 418                 }
 419                 complete_all(&dev_priv->error_completion);
 420         }
 421 }
 422
 423 #ifdef CONFIG_DEBUG_FS
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         struct drm_i915_gem_object *src_priv;
 431         int page, page_count;
 432         u32 reloc_offset;
 433
 434         if (src == NULL)
 435                 return NULL;
 436
 437         src_priv = to_intel_bo(src);
 438         if (src_priv->pages == NULL)
 439                 return NULL;
 440
 441         page_count = src->size / PAGE_SIZE;
 442
 443         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 444         if (dst == NULL)
 445                 return NULL;
 446
 447         reloc_offset = src_priv->gtt_offset;
 448         for (page = 0; page < page_count; page++) {
 449                 unsigned long flags;
 450                 void __iomem *s;
 451                 void *d;
 452
 453                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 454                 if (d == NULL)
 455                         goto unwind;
 456
 457                 local_irq_save(flags);
 458                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 459                                              reloc_offset,
 460                                              KM_IRQ0);
 461                 memcpy_fromio(d, s, PAGE_SIZE);
 462                 io_mapping_unmap_atomic(s, KM_IRQ0);
 463                 local_irq_restore(flags);
 464
 465                 dst->pages[page] = d;
 466
 467                 reloc_offset += PAGE_SIZE;
 468         }
 469         dst->page_count = page_count;
 470         dst->gtt_offset = src_priv->gtt_offset;
 471
 472         return dst;
 473
 474 unwind:
 475         while (page--)
 476                 kfree(dst->pages[page]);
 477         kfree(dst);
 478         return NULL;
 479 }
 480
 481 static void
 482 i915_error_object_free(struct drm_i915_error_object *obj)
 483 {
 484         int page;
 485
 486         if (obj == NULL)
 487                 return;
 488
 489         for (page = 0; page < obj->page_count; page++)
 490                 kfree(obj->pages[page]);
 491
 492         kfree(obj);
 493 }
 494
 495 static void
 496 i915_error_state_free(struct drm_device *dev,
 497                       struct drm_i915_error_state *error)
 498 {
 499         i915_error_object_free(error->batchbuffer[0]);
 500         i915_error_object_free(error->batchbuffer[1]);
 501         i915_error_object_free(error->ringbuffer);
 502         kfree(error->active_bo);
 503         kfree(error->overlay);
 504         kfree(error);
 505 }
 506
 507 static u32
 508 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 509 {
 510         u32 cmd;
 511
 512         if (IS_I830(dev) || IS_845G(dev))
 513                 cmd = MI_BATCH_BUFFER;
 514         else if (INTEL_INFO(dev)->gen >= 4)
 515                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 516                        MI_BATCH_NON_SECURE_I965);
 517         else
 518                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 519
 520         return ring[0] == cmd ? ring[1] : 0;
 521 }
 522
 523 static u32
 524 i915_ringbuffer_last_batch(struct drm_device *dev)
 525 {
 526         struct drm_i915_private *dev_priv = dev->dev_private;
 527         u32 head, bbaddr;
 528         u32 *ring;
 529
 530         /* Locate the current position in the ringbuffer and walk back
 531          * to find the most recently dispatched batch buffer.
 532          */
 533         bbaddr = 0;
 534         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 535         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 536
 537         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 538                 bbaddr = i915_get_bbaddr(dev, ring);
 539                 if (bbaddr)
 540                         break;
 541         }
 542
 543         if (bbaddr == 0) {
 544                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 545                                 + dev_priv->render_ring.size);
 546                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 547                         bbaddr = i915_get_bbaddr(dev, ring);
 548                         if (bbaddr)
 549                                 break;
 550                 }
 551         }
 552
 553         return bbaddr;
 554 }
 555
 556 /**
 557  * i915_capture_error_state - capture an error record for later analysis
 558  * @dev: drm device
 559  *
 560  * Should be called when an error is detected (either a hang or an error
 561  * interrupt) to capture error state from the time of the error.  Fills
 562  * out a structure which becomes available in debugfs for user level tools
 563  * to pick up.
 564  */
 565 static void i915_capture_error_state(struct drm_device *dev)
 566 {
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct drm_i915_gem_object *obj_priv;
 569         struct drm_i915_error_state *error;
 570         struct drm_gem_object *batchbuffer[2];
 571         unsigned long flags;
 572         u32 bbaddr;
 573         int count;
 574
 575         spin_lock_irqsave(&dev_priv->error_lock, flags);
 576         error = dev_priv->first_error;
 577         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 578         if (error)
 579                 return;
 580
 581         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 582         if (!error) {
 583                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 584                 return;
 585         }
 586
 587         DRM_DEBUG_DRIVER("generating error event\n");
 588
 589         error->seqno =
 590                 dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring);
 591         error->eir = I915_READ(EIR);
 592         error->pgtbl_er = I915_READ(PGTBL_ER);
 593         error->pipeastat = I915_READ(PIPEASTAT);
 594         error->pipebstat = I915_READ(PIPEBSTAT);
 595         error->instpm = I915_READ(INSTPM);
 596         if (INTEL_INFO(dev)->gen < 4) {
 597                 error->ipeir = I915_READ(IPEIR);
 598                 error->ipehr = I915_READ(IPEHR);
 599                 error->instdone = I915_READ(INSTDONE);
 600                 error->acthd = I915_READ(ACTHD);
 601                 error->bbaddr = 0;
 602         } else {
 603                 error->ipeir = I915_READ(IPEIR_I965);
 604                 error->ipehr = I915_READ(IPEHR_I965);
 605                 error->instdone = I915_READ(INSTDONE_I965);
 606                 error->instps = I915_READ(INSTPS);
 607                 error->instdone1 = I915_READ(INSTDONE1);
 608                 error->acthd = I915_READ(ACTHD_I965);
 609                 error->bbaddr = I915_READ64(BB_ADDR);
 610         }
 611
 612         bbaddr = i915_ringbuffer_last_batch(dev);
 613
 614         /* Grab the current batchbuffer, most likely to have crashed. */
 615         batchbuffer[0] = NULL;
 616         batchbuffer[1] = NULL;
 617         count = 0;
 618         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 619                 struct drm_gem_object *obj = &obj_priv->base;
 620
 621                 if (batchbuffer[0] == NULL &&
 622                     bbaddr >= obj_priv->gtt_offset &&
 623                     bbaddr < obj_priv->gtt_offset + obj->size)
 624                         batchbuffer[0] = obj;
 625
 626                 if (batchbuffer[1] == NULL &&
 627                     error->acthd >= obj_priv->gtt_offset &&
 628                     error->acthd < obj_priv->gtt_offset + obj->size)
 629                         batchbuffer[1] = obj;
 630
 631                 count++;
 632         }
 633         /* Scan the other lists for completeness for those bizarre errors. */
 634         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 635                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) {
 636                         struct drm_gem_object *obj = &obj_priv->base;
 637
 638                         if (batchbuffer[0] == NULL &&
 639                             bbaddr >= obj_priv->gtt_offset &&
 640                             bbaddr < obj_priv->gtt_offset + obj->size)
 641                                 batchbuffer[0] = obj;
 642
 643                         if (batchbuffer[1] == NULL &&
 644                             error->acthd >= obj_priv->gtt_offset &&
 645                             error->acthd < obj_priv->gtt_offset + obj->size)
 646                                 batchbuffer[1] = obj;
 647
 648                         if (batchbuffer[0] && batchbuffer[1])
 649                                 break;
 650                 }
 651         }
 652         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 653                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) {
 654                         struct drm_gem_object *obj = &obj_priv->base;
 655
 656                         if (batchbuffer[0] == NULL &&
 657                             bbaddr >= obj_priv->gtt_offset &&
 658                             bbaddr < obj_priv->gtt_offset + obj->size)
 659                                 batchbuffer[0] = obj;
 660
 661                         if (batchbuffer[1] == NULL &&
 662                             error->acthd >= obj_priv->gtt_offset &&
 663                             error->acthd < obj_priv->gtt_offset + obj->size)
 664                                 batchbuffer[1] = obj;
 665
 666                         if (batchbuffer[0] && batchbuffer[1])
 667                                 break;
 668                 }
 669         }
 670
 671         /* We need to copy these to an anonymous buffer as the simplest
 672          * method to avoid being overwritten by userspace.
 673          */
 674         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 675         if (batchbuffer[1] != batchbuffer[0])
 676                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 677         else
 678                 error->batchbuffer[1] = NULL;
 679
 680         /* Record the ringbuffer */
 681         error->ringbuffer = i915_error_object_create(dev,
 682                         dev_priv->render_ring.gem_object);
 683
 684         /* Record buffers on the active list. */
 685         error->active_bo = NULL;
 686         error->active_bo_count = 0;
 687
 688         if (count)
 689                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 690                                            GFP_ATOMIC);
 691
 692         if (error->active_bo) {
 693                 int i = 0;
 694                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 695                         struct drm_gem_object *obj = &obj_priv->base;
 696
 697                         error->active_bo[i].size = obj->size;
 698                         error->active_bo[i].name = obj->name;
 699                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 700                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 701                         error->active_bo[i].read_domains = obj->read_domains;
 702                         error->active_bo[i].write_domain = obj->write_domain;
 703                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 704                         error->active_bo[i].pinned = 0;
 705                         if (obj_priv->pin_count > 0)
 706                                 error->active_bo[i].pinned = 1;
 707                         if (obj_priv->user_pin_count > 0)
 708                                 error->active_bo[i].pinned = -1;
 709                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 710                         error->active_bo[i].dirty = obj_priv->dirty;
 711                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 712
 713                         if (++i == count)
 714                                 break;
 715                 }
 716                 error->active_bo_count = i;
 717         }
 718
 719         do_gettimeofday(&error->time);
 720
 721         error->overlay = intel_overlay_capture_error_state(dev);
 722
 723         spin_lock_irqsave(&dev_priv->error_lock, flags);
 724         if (dev_priv->first_error == NULL) {
 725                 dev_priv->first_error = error;
 726                 error = NULL;
 727         }
 728         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 729
 730         if (error)
 731                 i915_error_state_free(dev, error);
 732 }
 733
 734 void i915_destroy_error_state(struct drm_device *dev)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737         struct drm_i915_error_state *error;
 738
 739         spin_lock(&dev_priv->error_lock);
 740         error = dev_priv->first_error;
 741         dev_priv->first_error = NULL;
 742         spin_unlock(&dev_priv->error_lock);
 743
 744         if (error)
 745                 i915_error_state_free(dev, error);
 746 }
 747 #else
 748 #define i915_capture_error_state(x)
 749 #endif
 750
 751 static void i915_report_and_clear_eir(struct drm_device *dev)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 eir = I915_READ(EIR);
 755
 756         if (!eir)
 757                 return;
 758
 759         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 760                eir);
 761
 762         if (IS_G4X(dev)) {
 763                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 764                         u32 ipeir = I915_READ(IPEIR_I965);
 765
 766                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 767                                I915_READ(IPEIR_I965));
 768                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 769                                I915_READ(IPEHR_I965));
 770                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 771                                I915_READ(INSTDONE_I965));
 772                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 773                                I915_READ(INSTPS));
 774                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 775                                I915_READ(INSTDONE1));
 776                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 777                                I915_READ(ACTHD_I965));
 778                         I915_WRITE(IPEIR_I965, ipeir);
 779                         (void)I915_READ(IPEIR_I965);
 780                 }
 781                 if (eir & GM45_ERROR_PAGE_TABLE) {
 782                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 783                         printk(KERN_ERR "page table error\n");
 784                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 785                                pgtbl_err);
 786                         I915_WRITE(PGTBL_ER, pgtbl_err);
 787                         (void)I915_READ(PGTBL_ER);
 788                 }
 789         }
 790
 791         if (!IS_GEN2(dev)) {
 792                 if (eir & I915_ERROR_PAGE_TABLE) {
 793                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 794                         printk(KERN_ERR "page table error\n");
 795                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 796                                pgtbl_err);
 797                         I915_WRITE(PGTBL_ER, pgtbl_err);
 798                         (void)I915_READ(PGTBL_ER);
 799                 }
 800         }
 801
 802         if (eir & I915_ERROR_MEMORY_REFRESH) {
 803                 u32 pipea_stats = I915_READ(PIPEASTAT);
 804                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 805
 806                 printk(KERN_ERR "memory refresh error\n");
 807                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 808                        pipea_stats);
 809                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 810                        pipeb_stats);
 811                 /* pipestat has already been acked */
 812         }
 813         if (eir & I915_ERROR_INSTRUCTION) {
 814                 printk(KERN_ERR "instruction error\n");
 815                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 816                        I915_READ(INSTPM));
 817                 if (INTEL_INFO(dev)->gen < 4) {
 818                         u32 ipeir = I915_READ(IPEIR);
 819
 820                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 821                                I915_READ(IPEIR));
 822                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 823                                I915_READ(IPEHR));
 824                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 825                                I915_READ(INSTDONE));
 826                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 827                                I915_READ(ACTHD));
 828                         I915_WRITE(IPEIR, ipeir);
 829                         (void)I915_READ(IPEIR);
 830                 } else {
 831                         u32 ipeir = I915_READ(IPEIR_I965);
 832
 833                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 834                                I915_READ(IPEIR_I965));
 835                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 836                                I915_READ(IPEHR_I965));
 837                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 838                                I915_READ(INSTDONE_I965));
 839                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 840                                I915_READ(INSTPS));
 841                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 842                                I915_READ(INSTDONE1));
 843                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 844                                I915_READ(ACTHD_I965));
 845                         I915_WRITE(IPEIR_I965, ipeir);
 846                         (void)I915_READ(IPEIR_I965);
 847                 }
 848         }
 849
 850         I915_WRITE(EIR, eir);
 851         (void)I915_READ(EIR);
 852         eir = I915_READ(EIR);
 853         if (eir) {
 854                 /*
 855                  * some errors might have become stuck,
 856                  * mask them.
 857                  */
 858                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 859                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 860                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 861         }
 862 }
 863
 864 /**
 865  * i915_handle_error - handle an error interrupt
 866  * @dev: drm device
 867  *
 868  * Do some basic checking of regsiter state at error interrupt time and
 869  * dump it to the syslog.  Also call i915_capture_error_state() to make
 870  * sure we get a record and make it available in debugfs.  Fire a uevent
 871  * so userspace knows something bad happened (should trigger collection
 872  * of a ring dump etc.).
 873  */
 874 static void i915_handle_error(struct drm_device *dev, bool wedged)
 875 {
 876         struct drm_i915_private *dev_priv = dev->dev_private;
 877
 878         i915_capture_error_state(dev);
 879         i915_report_and_clear_eir(dev);
 880
 881         if (wedged) {
 882                 INIT_COMPLETION(dev_priv->error_completion);
 883                 atomic_set(&dev_priv->mm.wedged, 1);
 884
 885                 /*
 886                  * Wakeup waiting processes so they don't hang
 887                  */
 888                 wake_up_all(&dev_priv->render_ring.irq_queue);
 889                 if (HAS_BSD(dev))
 890                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 891                 if (HAS_BLT(dev))
 892                         wake_up_all(&dev_priv->blt_ring.irq_queue);
 893         }
 894
 895         queue_work(dev_priv->wq, &dev_priv->error_work);
 896 }
 897
 898 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 899 {
 900         drm_i915_private_t *dev_priv = dev->dev_private;
 901         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 903         struct drm_i915_gem_object *obj_priv;
 904         struct intel_unpin_work *work;
 905         unsigned long flags;
 906         bool stall_detected;
 907
 908         /* Ignore early vblank irqs */
 909         if (intel_crtc == NULL)
 910                 return;
 911
 912         spin_lock_irqsave(&dev->event_lock, flags);
 913         work = intel_crtc->unpin_work;
 914
 915         if (work == NULL || work->pending || !work->enable_stall_check) {
 916                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 917                 spin_unlock_irqrestore(&dev->event_lock, flags);
 918                 return;
 919         }
 920
 921         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 922         obj_priv = to_intel_bo(work->pending_flip_obj);
 923         if (INTEL_INFO(dev)->gen >= 4) {
 924                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 925                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 926         } else {
 927                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 928                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 929                                                         crtc->y * crtc->fb->pitch +
 930                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 931         }
 932
 933         spin_unlock_irqrestore(&dev->event_lock, flags);
 934
 935         if (stall_detected) {
 936                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 937                 intel_prepare_page_flip(dev, intel_crtc->plane);
 938         }
 939 }
 940
 941 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 942 {
 943         struct drm_device *dev = (struct drm_device *) arg;
 944         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 945         struct drm_i915_master_private *master_priv;
 946         u32 iir, new_iir;
 947         u32 pipea_stats, pipeb_stats;
 948         u32 vblank_status;
 949         int vblank = 0;
 950         unsigned long irqflags;
 951         int irq_received;
 952         int ret = IRQ_NONE;
 953
 954         atomic_inc(&dev_priv->irq_received);
 955
 956         if (HAS_PCH_SPLIT(dev))
 957                 return ironlake_irq_handler(dev);
 958
 959         iir = I915_READ(IIR);
 960
 961         if (INTEL_INFO(dev)->gen >= 4)
 962                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 963         else
 964                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 965
 966         for (;;) {
 967                 irq_received = iir != 0;
 968
 969                 /* Can't rely on pipestat interrupt bit in iir as it might
 970                  * have been cleared after the pipestat interrupt was received.
 971                  * It doesn't set the bit in iir again, but it still produces
 972                  * interrupts (for non-MSI).
 973                  */
 974                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 975                 pipea_stats = I915_READ(PIPEASTAT);
 976                 pipeb_stats = I915_READ(PIPEBSTAT);
 977
 978                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 979                         i915_handle_error(dev, false);
 980
 981                 /*
 982                  * Clear the PIPE(A|B)STAT regs before the IIR
 983                  */
 984                 if (pipea_stats & 0x8000ffff) {
 985                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 986                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 987                         I915_WRITE(PIPEASTAT, pipea_stats);
 988                         irq_received = 1;
 989                 }
 990
 991                 if (pipeb_stats & 0x8000ffff) {
 992                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 993                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 994                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 995                         irq_received = 1;
 996                 }
 997                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 998
 999                 if (!irq_received)
1000                         break;
1001
1002                 ret = IRQ_HANDLED;
1003
1004                 /* Consume port.  Then clear IIR or we'll miss events */
1005                 if ((I915_HAS_HOTPLUG(dev)) &&
1006                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1007                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1008
1009                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1010                                   hotplug_status);
1011                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1012                                 queue_work(dev_priv->wq,
1013                                            &dev_priv->hotplug_work);
1014
1015                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1016                         I915_READ(PORT_HOTPLUG_STAT);
1017                 }
1018
1019                 I915_WRITE(IIR, iir);
1020                 new_iir = I915_READ(IIR); /* Flush posted writes */
1021
1022                 if (dev->primary->master) {
1023                         master_priv = dev->primary->master->driver_priv;
1024                         if (master_priv->sarea_priv)
1025                                 master_priv->sarea_priv->last_dispatch =
1026                                         READ_BREADCRUMB(dev_priv);
1027                 }
1028
1029                 if (iir & I915_USER_INTERRUPT)
1030                         notify_ring(dev, &dev_priv->render_ring);
1031                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1032                         notify_ring(dev, &dev_priv->bsd_ring);
1033
1034                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1035                         intel_prepare_page_flip(dev, 0);
1036                         if (dev_priv->flip_pending_is_done)
1037                                 intel_finish_page_flip_plane(dev, 0);
1038                 }
1039
1040                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1041                         intel_prepare_page_flip(dev, 1);
1042                         if (dev_priv->flip_pending_is_done)
1043                                 intel_finish_page_flip_plane(dev, 1);
1044                 }
1045
1046                 if (pipea_stats & vblank_status) {
1047                         vblank++;
1048                         drm_handle_vblank(dev, 0);
1049                         if (!dev_priv->flip_pending_is_done) {
1050                                 i915_pageflip_stall_check(dev, 0);
1051                                 intel_finish_page_flip(dev, 0);
1052                         }
1053                 }
1054
1055                 if (pipeb_stats & vblank_status) {
1056                         vblank++;
1057                         drm_handle_vblank(dev, 1);
1058                         if (!dev_priv->flip_pending_is_done) {
1059                                 i915_pageflip_stall_check(dev, 1);
1060                                 intel_finish_page_flip(dev, 1);
1061                         }
1062                 }
1063
1064                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1065                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1066                     (iir & I915_ASLE_INTERRUPT))
1067                         intel_opregion_asle_intr(dev);
1068
1069                 /* With MSI, interrupts are only generated when iir
1070                  * transitions from zero to nonzero.  If another bit got
1071                  * set while we were handling the existing iir bits, then
1072                  * we would never get another interrupt.
1073                  *
1074                  * This is fine on non-MSI as well, as if we hit this path
1075                  * we avoid exiting the interrupt handler only to generate
1076                  * another one.
1077                  *
1078                  * Note that for MSI this could cause a stray interrupt report
1079                  * if an interrupt landed in the time between writing IIR and
1080                  * the posting read.  This should be rare enough to never
1081                  * trigger the 99% of 100,000 interrupts test for disabling
1082                  * stray interrupts.
1083                  */
1084                 iir = new_iir;
1085         }
1086
1087         return ret;
1088 }
1089
1090 static int i915_emit_irq(struct drm_device * dev)
1091 {
1092         drm_i915_private_t *dev_priv = dev->dev_private;
1093         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1094
1095         i915_kernel_lost_context(dev);
1096
1097         DRM_DEBUG_DRIVER("\n");
1098
1099         dev_priv->counter++;
1100         if (dev_priv->counter > 0x7FFFFFFFUL)
1101                 dev_priv->counter = 1;
1102         if (master_priv->sarea_priv)
1103                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1104
1105         BEGIN_LP_RING(4);
1106         OUT_RING(MI_STORE_DWORD_INDEX);
1107         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1108         OUT_RING(dev_priv->counter);
1109         OUT_RING(MI_USER_INTERRUPT);
1110         ADVANCE_LP_RING();
1111
1112         return dev_priv->counter;
1113 }
1114
1115 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1116 {
1117         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1118         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1119
1120         if (dev_priv->trace_irq_seqno == 0)
1121                 render_ring->user_irq_get(dev, render_ring);
1122
1123         dev_priv->trace_irq_seqno = seqno;
1124 }
1125
1126 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1127 {
1128         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1129         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1130         int ret = 0;
1131         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1132
1133         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1134                   READ_BREADCRUMB(dev_priv));
1135
1136         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1137                 if (master_priv->sarea_priv)
1138                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1139                 return 0;
1140         }
1141
1142         if (master_priv->sarea_priv)
1143                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1144
1145         render_ring->user_irq_get(dev, render_ring);
1146         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1147                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1148         render_ring->user_irq_put(dev, render_ring);
1149
1150         if (ret == -EBUSY) {
1151                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1152                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1153         }
1154
1155         return ret;
1156 }
1157
1158 /* Needs the lock as it touches the ring.
1159  */
1160 int i915_irq_emit(struct drm_device *dev, void *data,
1161                          struct drm_file *file_priv)
1162 {
1163         drm_i915_private_t *dev_priv = dev->dev_private;
1164         drm_i915_irq_emit_t *emit = data;
1165         int result;
1166
1167         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1168                 DRM_ERROR("called with no initialization\n");
1169                 return -EINVAL;
1170         }
1171
1172         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1173
1174         mutex_lock(&dev->struct_mutex);
1175         result = i915_emit_irq(dev);
1176         mutex_unlock(&dev->struct_mutex);
1177
1178         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1179                 DRM_ERROR("copy_to_user\n");
1180                 return -EFAULT;
1181         }
1182
1183         return 0;
1184 }
1185
1186 /* Doesn't need the hardware lock.
1187  */
1188 int i915_irq_wait(struct drm_device *dev, void *data,
1189                          struct drm_file *file_priv)
1190 {
1191         drm_i915_private_t *dev_priv = dev->dev_private;
1192         drm_i915_irq_wait_t *irqwait = data;
1193
1194         if (!dev_priv) {
1195                 DRM_ERROR("called with no initialization\n");
1196                 return -EINVAL;
1197         }
1198
1199         return i915_wait_irq(dev, irqwait->irq_seq);
1200 }
1201
1202 /* Called from drm generic code, passed 'crtc' which
1203  * we use as a pipe index
1204  */
1205 int i915_enable_vblank(struct drm_device *dev, int pipe)
1206 {
1207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1208         unsigned long irqflags;
1209
1210         if (!i915_pipe_enabled(dev, pipe))
1211                 return -EINVAL;
1212
1213         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1214         if (HAS_PCH_SPLIT(dev))
1215                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1216                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1217         else if (INTEL_INFO(dev)->gen >= 4)
1218                 i915_enable_pipestat(dev_priv, pipe,
1219                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1220         else
1221                 i915_enable_pipestat(dev_priv, pipe,
1222                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1223         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1224         return 0;
1225 }
1226
1227 /* Called from drm generic code, passed 'crtc' which
1228  * we use as a pipe index
1229  */
1230 void i915_disable_vblank(struct drm_device *dev, int pipe)
1231 {
1232         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1233         unsigned long irqflags;
1234
1235         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1236         if (HAS_PCH_SPLIT(dev))
1237                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1238                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1239         else
1240                 i915_disable_pipestat(dev_priv, pipe,
1241                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1242                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1243         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1244 }
1245
1246 void i915_enable_interrupt (struct drm_device *dev)
1247 {
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249
1250         if (!HAS_PCH_SPLIT(dev))
1251                 intel_opregion_enable_asle(dev);
1252         dev_priv->irq_enabled = 1;
1253 }
1254
1255
1256 /* Set the vblank monitor pipe
1257  */
1258 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1259                          struct drm_file *file_priv)
1260 {
1261         drm_i915_private_t *dev_priv = dev->dev_private;
1262
1263         if (!dev_priv) {
1264                 DRM_ERROR("called with no initialization\n");
1265                 return -EINVAL;
1266         }
1267
1268         return 0;
1269 }
1270
1271 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1272                          struct drm_file *file_priv)
1273 {
1274         drm_i915_private_t *dev_priv = dev->dev_private;
1275         drm_i915_vblank_pipe_t *pipe = data;
1276
1277         if (!dev_priv) {
1278                 DRM_ERROR("called with no initialization\n");
1279                 return -EINVAL;
1280         }
1281
1282         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1283
1284         return 0;
1285 }
1286
1287 /**
1288  * Schedule buffer swap at given vertical blank.
1289  */
1290 int i915_vblank_swap(struct drm_device *dev, void *data,
1291                      struct drm_file *file_priv)
1292 {
1293         /* The delayed swap mechanism was fundamentally racy, and has been
1294          * removed.  The model was that the client requested a delayed flip/swap
1295          * from the kernel, then waited for vblank before continuing to perform
1296          * rendering.  The problem was that the kernel might wake the client
1297          * up before it dispatched the vblank swap (since the lock has to be
1298          * held while touching the ringbuffer), in which case the client would
1299          * clear and start the next frame before the swap occurred, and
1300          * flicker would occur in addition to likely missing the vblank.
1301          *
1302          * In the absence of this ioctl, userland falls back to a correct path
1303          * of waiting for a vblank, then dispatching the swap on its own.
1304          * Context switching to userland and back is plenty fast enough for
1305          * meeting the requirements of vblank swapping.
1306          */
1307         return -EINVAL;
1308 }
1309
1310 static struct drm_i915_gem_request *
1311 i915_get_tail_request(struct drm_device *dev)
1312 {
1313         drm_i915_private_t *dev_priv = dev->dev_private;
1314         return list_entry(dev_priv->render_ring.request_list.prev,
1315                         struct drm_i915_gem_request, list);
1316 }
1317
1318 /**
1319  * This is called when the chip hasn't reported back with completed
1320  * batchbuffers in a long time. The first time this is called we simply record
1321  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1322  * again, we assume the chip is wedged and try to fix it.
1323  */
1324 void i915_hangcheck_elapsed(unsigned long data)
1325 {
1326         struct drm_device *dev = (struct drm_device *)data;
1327         drm_i915_private_t *dev_priv = dev->dev_private;
1328         uint32_t acthd, instdone, instdone1;
1329
1330         if (INTEL_INFO(dev)->gen < 4) {
1331                 acthd = I915_READ(ACTHD);
1332                 instdone = I915_READ(INSTDONE);
1333                 instdone1 = 0;
1334         } else {
1335                 acthd = I915_READ(ACTHD_I965);
1336                 instdone = I915_READ(INSTDONE_I965);
1337                 instdone1 = I915_READ(INSTDONE1);
1338         }
1339
1340         /* If all work is done then ACTHD clearly hasn't advanced. */
1341         if (list_empty(&dev_priv->render_ring.request_list) ||
1342                 i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring),
1343                                   i915_get_tail_request(dev)->seqno)) {
1344                 bool missed_wakeup = false;
1345
1346                 dev_priv->hangcheck_count = 0;
1347
1348                 /* Issue a wake-up to catch stuck h/w. */
1349                 if (dev_priv->render_ring.waiting_gem_seqno &&
1350                     waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1351                         wake_up_all(&dev_priv->render_ring.irq_queue);
1352                         missed_wakeup = true;
1353                 }
1354
1355                 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1356                     waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1357                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1358                         missed_wakeup = true;
1359                 }
1360
1361                 if (dev_priv->blt_ring.waiting_gem_seqno &&
1362                     waitqueue_active(&dev_priv->blt_ring.irq_queue)) {
1363                         wake_up_all(&dev_priv->blt_ring.irq_queue);
1364                         missed_wakeup = true;
1365                 }
1366
1367                 if (missed_wakeup)
1368                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1369                 return;
1370         }
1371
1372         if (dev_priv->last_acthd == acthd &&
1373             dev_priv->last_instdone == instdone &&
1374             dev_priv->last_instdone1 == instdone1) {
1375                 if (dev_priv->hangcheck_count++ > 1) {
1376                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1377
1378                         if (!IS_GEN2(dev)) {
1379                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1380                                  * If so we can simply poke the RB_WAIT bit
1381                                  * and break the hang. This should work on
1382                                  * all but the second generation chipsets.
1383                                  */
1384                                 u32 tmp = I915_READ(PRB0_CTL);
1385                                 if (tmp & RING_WAIT) {
1386                                         I915_WRITE(PRB0_CTL, tmp);
1387                                         POSTING_READ(PRB0_CTL);
1388                                         goto out;
1389                                 }
1390                         }
1391
1392                         i915_handle_error(dev, true);
1393                         return;
1394                 }
1395         } else {
1396                 dev_priv->hangcheck_count = 0;
1397
1398                 dev_priv->last_acthd = acthd;
1399                 dev_priv->last_instdone = instdone;
1400                 dev_priv->last_instdone1 = instdone1;
1401         }
1402
1403 out:
1404         /* Reset timer case chip hangs without another request being added */
1405         mod_timer(&dev_priv->hangcheck_timer,
1406                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1407 }
1408
1409 /* drm_dma.h hooks
1410 */
1411 static void ironlake_irq_preinstall(struct drm_device *dev)
1412 {
1413         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1414
1415         I915_WRITE(HWSTAM, 0xeffe);
1416
1417         /* XXX hotplug from PCH */
1418
1419         I915_WRITE(DEIMR, 0xffffffff);
1420         I915_WRITE(DEIER, 0x0);
1421         (void) I915_READ(DEIER);
1422
1423         /* and GT */
1424         I915_WRITE(GTIMR, 0xffffffff);
1425         I915_WRITE(GTIER, 0x0);
1426         (void) I915_READ(GTIER);
1427
1428         /* south display irq */
1429         I915_WRITE(SDEIMR, 0xffffffff);
1430         I915_WRITE(SDEIER, 0x0);
1431         (void) I915_READ(SDEIER);
1432 }
1433
1434 static int ironlake_irq_postinstall(struct drm_device *dev)
1435 {
1436         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1437         /* enable kind of interrupts always enabled */
1438         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1439                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1440         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1441         u32 hotplug_mask;
1442
1443         dev_priv->irq_mask_reg = ~display_mask;
1444         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1445
1446         /* should always can generate irq */
1447         I915_WRITE(DEIIR, I915_READ(DEIIR));
1448         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1449         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1450         (void) I915_READ(DEIER);
1451
1452         if (IS_GEN6(dev)) {
1453                 render_mask =
1454                         GT_PIPE_NOTIFY |
1455                         GT_GEN6_BSD_USER_INTERRUPT |
1456                         GT_BLT_USER_INTERRUPT;
1457         }
1458
1459         dev_priv->gt_irq_mask_reg = ~render_mask;
1460         dev_priv->gt_irq_enable_reg = render_mask;
1461
1462         I915_WRITE(GTIIR, I915_READ(GTIIR));
1463         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1464         if (IS_GEN6(dev)) {
1465                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1466                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1467                 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1468         }
1469
1470         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1471         (void) I915_READ(GTIER);
1472
1473         if (HAS_PCH_CPT(dev)) {
1474                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1475                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1476         } else {
1477                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1478                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1479         }
1480
1481         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1482         dev_priv->pch_irq_enable_reg = hotplug_mask;
1483
1484         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1485         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1486         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1487         (void) I915_READ(SDEIER);
1488
1489         if (IS_IRONLAKE_M(dev)) {
1490                 /* Clear & enable PCU event interrupts */
1491                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1492                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1493                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1494         }
1495
1496         return 0;
1497 }
1498
1499 void i915_driver_irq_preinstall(struct drm_device * dev)
1500 {
1501         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1502
1503         atomic_set(&dev_priv->irq_received, 0);
1504
1505         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1506         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1507
1508         if (HAS_PCH_SPLIT(dev)) {
1509                 ironlake_irq_preinstall(dev);
1510                 return;
1511         }
1512
1513         if (I915_HAS_HOTPLUG(dev)) {
1514                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1515                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1516         }
1517
1518         I915_WRITE(HWSTAM, 0xeffe);
1519         I915_WRITE(PIPEASTAT, 0);
1520         I915_WRITE(PIPEBSTAT, 0);
1521         I915_WRITE(IMR, 0xffffffff);
1522         I915_WRITE(IER, 0x0);
1523         (void) I915_READ(IER);
1524 }
1525
1526 /*
1527  * Must be called after intel_modeset_init or hotplug interrupts won't be
1528  * enabled correctly.
1529  */
1530 int i915_driver_irq_postinstall(struct drm_device *dev)
1531 {
1532         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1533         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1534         u32 error_mask;
1535
1536         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1537         if (HAS_BSD(dev))
1538                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1539         if (HAS_BLT(dev))
1540                 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1541
1542         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1543
1544         if (HAS_PCH_SPLIT(dev))
1545                 return ironlake_irq_postinstall(dev);
1546
1547         /* Unmask the interrupts that we always want on. */
1548         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1549
1550         dev_priv->pipestat[0] = 0;
1551         dev_priv->pipestat[1] = 0;
1552
1553         if (I915_HAS_HOTPLUG(dev)) {
1554                 /* Enable in IER... */
1555                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1556                 /* and unmask in IMR */
1557                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1558         }
1559
1560         /*
1561          * Enable some error detection, note the instruction error mask
1562          * bit is reserved, so we leave it masked.
1563          */
1564         if (IS_G4X(dev)) {
1565                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1566                                GM45_ERROR_MEM_PRIV |
1567                                GM45_ERROR_CP_PRIV |
1568                                I915_ERROR_MEMORY_REFRESH);
1569         } else {
1570                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1571                                I915_ERROR_MEMORY_REFRESH);
1572         }
1573         I915_WRITE(EMR, error_mask);
1574
1575         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1576         I915_WRITE(IER, enable_mask);
1577         (void) I915_READ(IER);
1578
1579         if (I915_HAS_HOTPLUG(dev)) {
1580                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1581
1582                 /* Note HDMI and DP share bits */
1583                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1584                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1585                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1586                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1587                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1588                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1589                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1590                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1591                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1592                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1593                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1594                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1595
1596                         /* Programming the CRT detection parameters tends
1597                            to generate a spurious hotplug event about three
1598                            seconds later.  So just do it once.
1599                         */
1600                         if (IS_G4X(dev))
1601                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1602                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1603                 }
1604
1605                 /* Ignore TV since it's buggy */
1606
1607                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1608         }
1609
1610         intel_opregion_enable_asle(dev);
1611
1612         return 0;
1613 }
1614
1615 static void ironlake_irq_uninstall(struct drm_device *dev)
1616 {
1617         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1618         I915_WRITE(HWSTAM, 0xffffffff);
1619
1620         I915_WRITE(DEIMR, 0xffffffff);
1621         I915_WRITE(DEIER, 0x0);
1622         I915_WRITE(DEIIR, I915_READ(DEIIR));
1623
1624         I915_WRITE(GTIMR, 0xffffffff);
1625         I915_WRITE(GTIER, 0x0);
1626         I915_WRITE(GTIIR, I915_READ(GTIIR));
1627 }
1628
1629 void i915_driver_irq_uninstall(struct drm_device * dev)
1630 {
1631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1632
1633         if (!dev_priv)
1634                 return;
1635
1636         dev_priv->vblank_pipe = 0;
1637
1638         if (HAS_PCH_SPLIT(dev)) {
1639                 ironlake_irq_uninstall(dev);
1640                 return;
1641         }
1642
1643         if (I915_HAS_HOTPLUG(dev)) {
1644                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1645                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1646         }
1647
1648         I915_WRITE(HWSTAM, 0xffffffff);
1649         I915_WRITE(PIPEASTAT, 0);
1650         I915_WRITE(PIPEBSTAT, 0);
1651         I915_WRITE(IMR, 0xffffffff);
1652         I915_WRITE(IER, 0x0);
1653
1654         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1655         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1656         I915_WRITE(IIR, I915_READ(IIR));
1657 }