drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 POSTING_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 POSTING_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 POSTING_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 POSTING_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 POSTING_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 POSTING_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 POSTING_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 POSTING_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static void notify_ring(struct drm_device *dev,
 297                         struct intel_ring_buffer *ring)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         u32 seqno = ring->get_seqno(ring);
 301         ring->irq_seqno = seqno;
 302         trace_i915_gem_request_complete(dev, seqno);
 303         wake_up_all(&ring->irq_queue);
 304         dev_priv->hangcheck_count = 0;
 305         mod_timer(&dev_priv->hangcheck_timer,
 306                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 307 }
 308
 309 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 310 {
 311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 312         int ret = IRQ_NONE;
 313         u32 de_iir, gt_iir, de_ier, pch_iir;
 314         u32 hotplug_mask;
 315         struct drm_i915_master_private *master_priv;
 316         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 317
 318         if (IS_GEN6(dev))
 319                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 320
 321         /* disable master interrupt before clearing iir  */
 322         de_ier = I915_READ(DEIER);
 323         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 324         POSTING_READ(DEIER);
 325
 326         de_iir = I915_READ(DEIIR);
 327         gt_iir = I915_READ(GTIIR);
 328         pch_iir = I915_READ(SDEIIR);
 329
 330         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 331                 goto done;
 332
 333         if (HAS_PCH_CPT(dev))
 334                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 335         else
 336                 hotplug_mask = SDE_HOTPLUG_MASK;
 337
 338         ret = IRQ_HANDLED;
 339
 340         if (dev->primary->master) {
 341                 master_priv = dev->primary->master->driver_priv;
 342                 if (master_priv->sarea_priv)
 343                         master_priv->sarea_priv->last_dispatch =
 344                                 READ_BREADCRUMB(dev_priv);
 345         }
 346
 347         if (gt_iir & GT_PIPE_NOTIFY)
 348                 notify_ring(dev, &dev_priv->render_ring);
 349         if (gt_iir & bsd_usr_interrupt)
 350                 notify_ring(dev, &dev_priv->bsd_ring);
 351         if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
 352                 notify_ring(dev, &dev_priv->blt_ring);
 353
 354         if (de_iir & DE_GSE)
 355                 intel_opregion_gse_intr(dev);
 356
 357         if (de_iir & DE_PLANEA_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 0);
 359                 intel_finish_page_flip_plane(dev, 0);
 360         }
 361
 362         if (de_iir & DE_PLANEB_FLIP_DONE) {
 363                 intel_prepare_page_flip(dev, 1);
 364                 intel_finish_page_flip_plane(dev, 1);
 365         }
 366
 367         if (de_iir & DE_PIPEA_VBLANK)
 368                 drm_handle_vblank(dev, 0);
 369
 370         if (de_iir & DE_PIPEB_VBLANK)
 371                 drm_handle_vblank(dev, 1);
 372
 373         /* check event from PCH */
 374         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 375                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 376
 377         if (de_iir & DE_PCU_EVENT) {
 378                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 379                 i915_handle_rps_change(dev);
 380         }
 381
 382         /* should clear PCH hotplug event before clear CPU irq */
 383         I915_WRITE(SDEIIR, pch_iir);
 384         I915_WRITE(GTIIR, gt_iir);
 385         I915_WRITE(DEIIR, de_iir);
 386
 387 done:
 388         I915_WRITE(DEIER, de_ier);
 389         POSTING_READ(DEIER);
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * i915_error_work_func - do process context error handling work
 396  * @work: work struct
 397  *
 398  * Fire an error uevent so userspace can see that a hang or error
 399  * was detected.
 400  */
 401 static void i915_error_work_func(struct work_struct *work)
 402 {
 403         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 404                                                     error_work);
 405         struct drm_device *dev = dev_priv->dev;
 406         char *error_event[] = { "ERROR=1", NULL };
 407         char *reset_event[] = { "RESET=1", NULL };
 408         char *reset_done_event[] = { "ERROR=0", NULL };
 409
 410         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 411
 412         if (atomic_read(&dev_priv->mm.wedged)) {
 413                 DRM_DEBUG_DRIVER("resetting chip\n");
 414                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 415                 if (!i915_reset(dev, GRDOM_RENDER)) {
 416                         atomic_set(&dev_priv->mm.wedged, 0);
 417                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 418                 }
 419                 complete_all(&dev_priv->error_completion);
 420         }
 421 }
 422
 423 #ifdef CONFIG_DEBUG_FS
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_i915_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         int page, page_count;
 431         u32 reloc_offset;
 432
 433         if (src == NULL || src->pages == NULL)
 434                 return NULL;
 435
 436         page_count = src->base.size / PAGE_SIZE;
 437
 438         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 439         if (dst == NULL)
 440                 return NULL;
 441
 442         reloc_offset = src->gtt_offset;
 443         for (page = 0; page < page_count; page++) {
 444                 unsigned long flags;
 445                 void __iomem *s;
 446                 void *d;
 447
 448                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 449                 if (d == NULL)
 450                         goto unwind;
 451
 452                 local_irq_save(flags);
 453                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 454                                              reloc_offset);
 455                 memcpy_fromio(d, s, PAGE_SIZE);
 456                 io_mapping_unmap_atomic(s);
 457                 local_irq_restore(flags);
 458
 459                 dst->pages[page] = d;
 460
 461                 reloc_offset += PAGE_SIZE;
 462         }
 463         dst->page_count = page_count;
 464         dst->gtt_offset = src->gtt_offset;
 465
 466         return dst;
 467
 468 unwind:
 469         while (page--)
 470                 kfree(dst->pages[page]);
 471         kfree(dst);
 472         return NULL;
 473 }
 474
 475 static void
 476 i915_error_object_free(struct drm_i915_error_object *obj)
 477 {
 478         int page;
 479
 480         if (obj == NULL)
 481                 return;
 482
 483         for (page = 0; page < obj->page_count; page++)
 484                 kfree(obj->pages[page]);
 485
 486         kfree(obj);
 487 }
 488
 489 static void
 490 i915_error_state_free(struct drm_device *dev,
 491                       struct drm_i915_error_state *error)
 492 {
 493         i915_error_object_free(error->batchbuffer[0]);
 494         i915_error_object_free(error->batchbuffer[1]);
 495         i915_error_object_free(error->ringbuffer);
 496         kfree(error->active_bo);
 497         kfree(error->overlay);
 498         kfree(error);
 499 }
 500
 501 static u32
 502 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 503 {
 504         u32 cmd;
 505
 506         if (IS_I830(dev) || IS_845G(dev))
 507                 cmd = MI_BATCH_BUFFER;
 508         else if (INTEL_INFO(dev)->gen >= 4)
 509                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 510                        MI_BATCH_NON_SECURE_I965);
 511         else
 512                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 513
 514         return ring[0] == cmd ? ring[1] : 0;
 515 }
 516
 517 static u32
 518 i915_ringbuffer_last_batch(struct drm_device *dev,
 519                            struct intel_ring_buffer *ring)
 520 {
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         u32 head, bbaddr;
 523         u32 *val;
 524
 525         /* Locate the current position in the ringbuffer and walk back
 526          * to find the most recently dispatched batch buffer.
 527          */
 528         bbaddr = 0;
 529         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 530         val = (u32 *)(ring->virtual_start + head);
 531
 532         while (--val >= (u32 *)ring->virtual_start) {
 533                 bbaddr = i915_get_bbaddr(dev, val);
 534                 if (bbaddr)
 535                         break;
 536         }
 537
 538         if (bbaddr == 0) {
 539                 val = (u32 *)(ring->virtual_start + ring->size);
 540                 while (--val >= (u32 *)ring->virtual_start) {
 541                         bbaddr = i915_get_bbaddr(dev, val);
 542                         if (bbaddr)
 543                                 break;
 544                 }
 545         }
 546
 547         return bbaddr;
 548 }
 549
 550 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 551                            int count,
 552                            struct list_head *head)
 553 {
 554         struct drm_i915_gem_object *obj;
 555         int i = 0;
 556
 557         list_for_each_entry(obj, head, mm_list) {
 558                 err->size = obj->base.size;
 559                 err->name = obj->base.name;
 560                 err->seqno = obj->last_rendering_seqno;
 561                 err->gtt_offset = obj->gtt_offset;
 562                 err->read_domains = obj->base.read_domains;
 563                 err->write_domain = obj->base.write_domain;
 564                 err->fence_reg = obj->fence_reg;
 565                 err->pinned = 0;
 566                 if (obj->pin_count > 0)
 567                         err->pinned = 1;
 568                 if (obj->user_pin_count > 0)
 569                         err->pinned = -1;
 570                 err->tiling = obj->tiling_mode;
 571                 err->dirty = obj->dirty;
 572                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 573                 err->ring = obj->ring ? obj->ring->id : 0;
 574
 575                 if (++i == count)
 576                         break;
 577
 578                 err++;
 579         }
 580
 581         return i;
 582 }
 583
 584 /**
 585  * i915_capture_error_state - capture an error record for later analysis
 586  * @dev: drm device
 587  *
 588  * Should be called when an error is detected (either a hang or an error
 589  * interrupt) to capture error state from the time of the error.  Fills
 590  * out a structure which becomes available in debugfs for user level tools
 591  * to pick up.
 592  */
 593 static void i915_capture_error_state(struct drm_device *dev)
 594 {
 595         struct drm_i915_private *dev_priv = dev->dev_private;
 596         struct drm_i915_gem_object *obj;
 597         struct drm_i915_error_state *error;
 598         struct drm_i915_gem_object *batchbuffer[2];
 599         unsigned long flags;
 600         u32 bbaddr;
 601         int count;
 602
 603         spin_lock_irqsave(&dev_priv->error_lock, flags);
 604         error = dev_priv->first_error;
 605         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 606         if (error)
 607                 return;
 608
 609         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 610         if (!error) {
 611                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 612                 return;
 613         }
 614
 615         DRM_DEBUG_DRIVER("generating error event\n");
 616
 617         error->seqno =
 618                 dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
 619         error->eir = I915_READ(EIR);
 620         error->pgtbl_er = I915_READ(PGTBL_ER);
 621         error->pipeastat = I915_READ(PIPEASTAT);
 622         error->pipebstat = I915_READ(PIPEBSTAT);
 623         error->instpm = I915_READ(INSTPM);
 624         error->error = 0;
 625         if (INTEL_INFO(dev)->gen >= 6) {
 626                 error->error = I915_READ(ERROR_GEN6);
 627
 628                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 629                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 630                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 631                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 632                 error->bcs_seqno = 0;
 633                 if (dev_priv->blt_ring.get_seqno)
 634                         error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring);
 635
 636                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 637                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 638                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 639                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 640                 error->vcs_seqno = 0;
 641                 if (dev_priv->bsd_ring.get_seqno)
 642                         error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring);
 643         }
 644         if (INTEL_INFO(dev)->gen >= 4) {
 645                 error->ipeir = I915_READ(IPEIR_I965);
 646                 error->ipehr = I915_READ(IPEHR_I965);
 647                 error->instdone = I915_READ(INSTDONE_I965);
 648                 error->instps = I915_READ(INSTPS);
 649                 error->instdone1 = I915_READ(INSTDONE1);
 650                 error->acthd = I915_READ(ACTHD_I965);
 651                 error->bbaddr = I915_READ64(BB_ADDR);
 652         } else {
 653                 error->ipeir = I915_READ(IPEIR);
 654                 error->ipehr = I915_READ(IPEHR);
 655                 error->instdone = I915_READ(INSTDONE);
 656                 error->acthd = I915_READ(ACTHD);
 657                 error->bbaddr = 0;
 658         }
 659
 660         bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->render_ring);
 661
 662         /* Grab the current batchbuffer, most likely to have crashed. */
 663         batchbuffer[0] = NULL;
 664         batchbuffer[1] = NULL;
 665         count = 0;
 666         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 667                 if (batchbuffer[0] == NULL &&
 668                     bbaddr >= obj->gtt_offset &&
 669                     bbaddr < obj->gtt_offset + obj->base.size)
 670                         batchbuffer[0] = obj;
 671
 672                 if (batchbuffer[1] == NULL &&
 673                     error->acthd >= obj->gtt_offset &&
 674                     error->acthd < obj->gtt_offset + obj->base.size)
 675                         batchbuffer[1] = obj;
 676
 677                 count++;
 678         }
 679         /* Scan the other lists for completeness for those bizarre errors. */
 680         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 681                 list_for_each_entry(obj, &dev_priv->mm.flushing_list, mm_list) {
 682                         if (batchbuffer[0] == NULL &&
 683                             bbaddr >= obj->gtt_offset &&
 684                             bbaddr < obj->gtt_offset + obj->base.size)
 685                                 batchbuffer[0] = obj;
 686
 687                         if (batchbuffer[1] == NULL &&
 688                             error->acthd >= obj->gtt_offset &&
 689                             error->acthd < obj->gtt_offset + obj->base.size)
 690                                 batchbuffer[1] = obj;
 691
 692                         if (batchbuffer[0] && batchbuffer[1])
 693                                 break;
 694                 }
 695         }
 696         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 697                 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
 698                         if (batchbuffer[0] == NULL &&
 699                             bbaddr >= obj->gtt_offset &&
 700                             bbaddr < obj->gtt_offset + obj->base.size)
 701                                 batchbuffer[0] = obj;
 702
 703                         if (batchbuffer[1] == NULL &&
 704                             error->acthd >= obj->gtt_offset &&
 705                             error->acthd < obj->gtt_offset + obj->base.size)
 706                                 batchbuffer[1] = obj;
 707
 708                         if (batchbuffer[0] && batchbuffer[1])
 709                                 break;
 710                 }
 711         }
 712
 713         /* We need to copy these to an anonymous buffer as the simplest
 714          * method to avoid being overwritten by userspace.
 715          */
 716         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 717         if (batchbuffer[1] != batchbuffer[0])
 718                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 719         else
 720                 error->batchbuffer[1] = NULL;
 721
 722         /* Record the ringbuffer */
 723         error->ringbuffer = i915_error_object_create(dev,
 724                                                      dev_priv->render_ring.obj);
 725
 726         /* Record buffers on the active and pinned lists. */
 727         error->active_bo = NULL;
 728         error->pinned_bo = NULL;
 729
 730         error->active_bo_count = count;
 731         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 732                 count++;
 733         error->pinned_bo_count = count - error->active_bo_count;
 734
 735         if (count) {
 736                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 737                                            GFP_ATOMIC);
 738                 if (error->active_bo)
 739                         error->pinned_bo =
 740                                 error->active_bo + error->active_bo_count;
 741         }
 742
 743         if (error->active_bo)
 744                 error->active_bo_count =
 745                         capture_bo_list(error->active_bo,
 746                                         error->active_bo_count,
 747                                         &dev_priv->mm.active_list);
 748
 749         if (error->pinned_bo)
 750                 error->pinned_bo_count =
 751                         capture_bo_list(error->pinned_bo,
 752                                         error->pinned_bo_count,
 753                                         &dev_priv->mm.pinned_list);
 754
 755         do_gettimeofday(&error->time);
 756
 757         error->overlay = intel_overlay_capture_error_state(dev);
 758         error->display = intel_display_capture_error_state(dev);
 759
 760         spin_lock_irqsave(&dev_priv->error_lock, flags);
 761         if (dev_priv->first_error == NULL) {
 762                 dev_priv->first_error = error;
 763                 error = NULL;
 764         }
 765         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 766
 767         if (error)
 768                 i915_error_state_free(dev, error);
 769 }
 770
 771 void i915_destroy_error_state(struct drm_device *dev)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         struct drm_i915_error_state *error;
 775
 776         spin_lock(&dev_priv->error_lock);
 777         error = dev_priv->first_error;
 778         dev_priv->first_error = NULL;
 779         spin_unlock(&dev_priv->error_lock);
 780
 781         if (error)
 782                 i915_error_state_free(dev, error);
 783 }
 784 #else
 785 #define i915_capture_error_state(x)
 786 #endif
 787
 788 static void i915_report_and_clear_eir(struct drm_device *dev)
 789 {
 790         struct drm_i915_private *dev_priv = dev->dev_private;
 791         u32 eir = I915_READ(EIR);
 792
 793         if (!eir)
 794                 return;
 795
 796         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 797                eir);
 798
 799         if (IS_G4X(dev)) {
 800                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 801                         u32 ipeir = I915_READ(IPEIR_I965);
 802
 803                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 804                                I915_READ(IPEIR_I965));
 805                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 806                                I915_READ(IPEHR_I965));
 807                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 808                                I915_READ(INSTDONE_I965));
 809                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 810                                I915_READ(INSTPS));
 811                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 812                                I915_READ(INSTDONE1));
 813                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 814                                I915_READ(ACTHD_I965));
 815                         I915_WRITE(IPEIR_I965, ipeir);
 816                         POSTING_READ(IPEIR_I965);
 817                 }
 818                 if (eir & GM45_ERROR_PAGE_TABLE) {
 819                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 820                         printk(KERN_ERR "page table error\n");
 821                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 822                                pgtbl_err);
 823                         I915_WRITE(PGTBL_ER, pgtbl_err);
 824                         POSTING_READ(PGTBL_ER);
 825                 }
 826         }
 827
 828         if (!IS_GEN2(dev)) {
 829                 if (eir & I915_ERROR_PAGE_TABLE) {
 830                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 831                         printk(KERN_ERR "page table error\n");
 832                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 833                                pgtbl_err);
 834                         I915_WRITE(PGTBL_ER, pgtbl_err);
 835                         POSTING_READ(PGTBL_ER);
 836                 }
 837         }
 838
 839         if (eir & I915_ERROR_MEMORY_REFRESH) {
 840                 u32 pipea_stats = I915_READ(PIPEASTAT);
 841                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 842
 843                 printk(KERN_ERR "memory refresh error\n");
 844                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 845                        pipea_stats);
 846                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 847                        pipeb_stats);
 848                 /* pipestat has already been acked */
 849         }
 850         if (eir & I915_ERROR_INSTRUCTION) {
 851                 printk(KERN_ERR "instruction error\n");
 852                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 853                        I915_READ(INSTPM));
 854                 if (INTEL_INFO(dev)->gen < 4) {
 855                         u32 ipeir = I915_READ(IPEIR);
 856
 857                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 858                                I915_READ(IPEIR));
 859                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 860                                I915_READ(IPEHR));
 861                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 862                                I915_READ(INSTDONE));
 863                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 864                                I915_READ(ACTHD));
 865                         I915_WRITE(IPEIR, ipeir);
 866                         POSTING_READ(IPEIR);
 867                 } else {
 868                         u32 ipeir = I915_READ(IPEIR_I965);
 869
 870                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 871                                I915_READ(IPEIR_I965));
 872                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 873                                I915_READ(IPEHR_I965));
 874                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 875                                I915_READ(INSTDONE_I965));
 876                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 877                                I915_READ(INSTPS));
 878                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 879                                I915_READ(INSTDONE1));
 880                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 881                                I915_READ(ACTHD_I965));
 882                         I915_WRITE(IPEIR_I965, ipeir);
 883                         POSTING_READ(IPEIR_I965);
 884                 }
 885         }
 886
 887         I915_WRITE(EIR, eir);
 888         POSTING_READ(EIR);
 889         eir = I915_READ(EIR);
 890         if (eir) {
 891                 /*
 892                  * some errors might have become stuck,
 893                  * mask them.
 894                  */
 895                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 896                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 897                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 898         }
 899 }
 900
 901 /**
 902  * i915_handle_error - handle an error interrupt
 903  * @dev: drm device
 904  *
 905  * Do some basic checking of regsiter state at error interrupt time and
 906  * dump it to the syslog.  Also call i915_capture_error_state() to make
 907  * sure we get a record and make it available in debugfs.  Fire a uevent
 908  * so userspace knows something bad happened (should trigger collection
 909  * of a ring dump etc.).
 910  */
 911 void i915_handle_error(struct drm_device *dev, bool wedged)
 912 {
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914
 915         i915_capture_error_state(dev);
 916         i915_report_and_clear_eir(dev);
 917
 918         if (wedged) {
 919                 INIT_COMPLETION(dev_priv->error_completion);
 920                 atomic_set(&dev_priv->mm.wedged, 1);
 921
 922                 /*
 923                  * Wakeup waiting processes so they don't hang
 924                  */
 925                 wake_up_all(&dev_priv->render_ring.irq_queue);
 926                 if (HAS_BSD(dev))
 927                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 928                 if (HAS_BLT(dev))
 929                         wake_up_all(&dev_priv->blt_ring.irq_queue);
 930         }
 931
 932         queue_work(dev_priv->wq, &dev_priv->error_work);
 933 }
 934
 935 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 936 {
 937         drm_i915_private_t *dev_priv = dev->dev_private;
 938         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 940         struct drm_i915_gem_object *obj;
 941         struct intel_unpin_work *work;
 942         unsigned long flags;
 943         bool stall_detected;
 944
 945         /* Ignore early vblank irqs */
 946         if (intel_crtc == NULL)
 947                 return;
 948
 949         spin_lock_irqsave(&dev->event_lock, flags);
 950         work = intel_crtc->unpin_work;
 951
 952         if (work == NULL || work->pending || !work->enable_stall_check) {
 953                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 954                 spin_unlock_irqrestore(&dev->event_lock, flags);
 955                 return;
 956         }
 957
 958         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 959         obj = work->pending_flip_obj;
 960         if (INTEL_INFO(dev)->gen >= 4) {
 961                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 962                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
 963         } else {
 964                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 965                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
 966                                                         crtc->y * crtc->fb->pitch +
 967                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 968         }
 969
 970         spin_unlock_irqrestore(&dev->event_lock, flags);
 971
 972         if (stall_detected) {
 973                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 974                 intel_prepare_page_flip(dev, intel_crtc->plane);
 975         }
 976 }
 977
 978 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 979 {
 980         struct drm_device *dev = (struct drm_device *) arg;
 981         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 982         struct drm_i915_master_private *master_priv;
 983         u32 iir, new_iir;
 984         u32 pipea_stats, pipeb_stats;
 985         u32 vblank_status;
 986         int vblank = 0;
 987         unsigned long irqflags;
 988         int irq_received;
 989         int ret = IRQ_NONE;
 990
 991         atomic_inc(&dev_priv->irq_received);
 992
 993         if (HAS_PCH_SPLIT(dev))
 994                 return ironlake_irq_handler(dev);
 995
 996         iir = I915_READ(IIR);
 997
 998         if (INTEL_INFO(dev)->gen >= 4)
 999                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1000         else
1001                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1002
1003         for (;;) {
1004                 irq_received = iir != 0;
1005
1006                 /* Can't rely on pipestat interrupt bit in iir as it might
1007                  * have been cleared after the pipestat interrupt was received.
1008                  * It doesn't set the bit in iir again, but it still produces
1009                  * interrupts (for non-MSI).
1010                  */
1011                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1012                 pipea_stats = I915_READ(PIPEASTAT);
1013                 pipeb_stats = I915_READ(PIPEBSTAT);
1014
1015                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1016                         i915_handle_error(dev, false);
1017
1018                 /*
1019                  * Clear the PIPE(A|B)STAT regs before the IIR
1020                  */
1021                 if (pipea_stats & 0x8000ffff) {
1022                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1023                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1024                         I915_WRITE(PIPEASTAT, pipea_stats);
1025                         irq_received = 1;
1026                 }
1027
1028                 if (pipeb_stats & 0x8000ffff) {
1029                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1030                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1031                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1032                         irq_received = 1;
1033                 }
1034                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1035
1036                 if (!irq_received)
1037                         break;
1038
1039                 ret = IRQ_HANDLED;
1040
1041                 /* Consume port.  Then clear IIR or we'll miss events */
1042                 if ((I915_HAS_HOTPLUG(dev)) &&
1043                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1044                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1045
1046                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1047                                   hotplug_status);
1048                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1049                                 queue_work(dev_priv->wq,
1050                                            &dev_priv->hotplug_work);
1051
1052                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1053                         I915_READ(PORT_HOTPLUG_STAT);
1054                 }
1055
1056                 I915_WRITE(IIR, iir);
1057                 new_iir = I915_READ(IIR); /* Flush posted writes */
1058
1059                 if (dev->primary->master) {
1060                         master_priv = dev->primary->master->driver_priv;
1061                         if (master_priv->sarea_priv)
1062                                 master_priv->sarea_priv->last_dispatch =
1063                                         READ_BREADCRUMB(dev_priv);
1064                 }
1065
1066                 if (iir & I915_USER_INTERRUPT)
1067                         notify_ring(dev, &dev_priv->render_ring);
1068                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1069                         notify_ring(dev, &dev_priv->bsd_ring);
1070
1071                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1072                         intel_prepare_page_flip(dev, 0);
1073                         if (dev_priv->flip_pending_is_done)
1074                                 intel_finish_page_flip_plane(dev, 0);
1075                 }
1076
1077                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1078                         intel_prepare_page_flip(dev, 1);
1079                         if (dev_priv->flip_pending_is_done)
1080                                 intel_finish_page_flip_plane(dev, 1);
1081                 }
1082
1083                 if (pipea_stats & vblank_status) {
1084                         vblank++;
1085                         drm_handle_vblank(dev, 0);
1086                         if (!dev_priv->flip_pending_is_done) {
1087                                 i915_pageflip_stall_check(dev, 0);
1088                                 intel_finish_page_flip(dev, 0);
1089                         }
1090                 }
1091
1092                 if (pipeb_stats & vblank_status) {
1093                         vblank++;
1094                         drm_handle_vblank(dev, 1);
1095                         if (!dev_priv->flip_pending_is_done) {
1096                                 i915_pageflip_stall_check(dev, 1);
1097                                 intel_finish_page_flip(dev, 1);
1098                         }
1099                 }
1100
1101                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1102                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1103                     (iir & I915_ASLE_INTERRUPT))
1104                         intel_opregion_asle_intr(dev);
1105
1106                 /* With MSI, interrupts are only generated when iir
1107                  * transitions from zero to nonzero.  If another bit got
1108                  * set while we were handling the existing iir bits, then
1109                  * we would never get another interrupt.
1110                  *
1111                  * This is fine on non-MSI as well, as if we hit this path
1112                  * we avoid exiting the interrupt handler only to generate
1113                  * another one.
1114                  *
1115                  * Note that for MSI this could cause a stray interrupt report
1116                  * if an interrupt landed in the time between writing IIR and
1117                  * the posting read.  This should be rare enough to never
1118                  * trigger the 99% of 100,000 interrupts test for disabling
1119                  * stray interrupts.
1120                  */
1121                 iir = new_iir;
1122         }
1123
1124         return ret;
1125 }
1126
1127 static int i915_emit_irq(struct drm_device * dev)
1128 {
1129         drm_i915_private_t *dev_priv = dev->dev_private;
1130         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1131
1132         i915_kernel_lost_context(dev);
1133
1134         DRM_DEBUG_DRIVER("\n");
1135
1136         dev_priv->counter++;
1137         if (dev_priv->counter > 0x7FFFFFFFUL)
1138                 dev_priv->counter = 1;
1139         if (master_priv->sarea_priv)
1140                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1141
1142         if (BEGIN_LP_RING(4) == 0) {
1143                 OUT_RING(MI_STORE_DWORD_INDEX);
1144                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1145                 OUT_RING(dev_priv->counter);
1146                 OUT_RING(MI_USER_INTERRUPT);
1147                 ADVANCE_LP_RING();
1148         }
1149
1150         return dev_priv->counter;
1151 }
1152
1153 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1154 {
1155         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1156         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1157
1158         if (dev_priv->trace_irq_seqno == 0)
1159                 render_ring->user_irq_get(render_ring);
1160
1161         dev_priv->trace_irq_seqno = seqno;
1162 }
1163
1164 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1165 {
1166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1167         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1168         int ret = 0;
1169         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1170
1171         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1172                   READ_BREADCRUMB(dev_priv));
1173
1174         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1175                 if (master_priv->sarea_priv)
1176                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1177                 return 0;
1178         }
1179
1180         if (master_priv->sarea_priv)
1181                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1182
1183         render_ring->user_irq_get(render_ring);
1184         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1185                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1186         render_ring->user_irq_put(render_ring);
1187
1188         if (ret == -EBUSY) {
1189                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1190                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1191         }
1192
1193         return ret;
1194 }
1195
1196 /* Needs the lock as it touches the ring.
1197  */
1198 int i915_irq_emit(struct drm_device *dev, void *data,
1199                          struct drm_file *file_priv)
1200 {
1201         drm_i915_private_t *dev_priv = dev->dev_private;
1202         drm_i915_irq_emit_t *emit = data;
1203         int result;
1204
1205         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1206                 DRM_ERROR("called with no initialization\n");
1207                 return -EINVAL;
1208         }
1209
1210         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1211
1212         mutex_lock(&dev->struct_mutex);
1213         result = i915_emit_irq(dev);
1214         mutex_unlock(&dev->struct_mutex);
1215
1216         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1217                 DRM_ERROR("copy_to_user\n");
1218                 return -EFAULT;
1219         }
1220
1221         return 0;
1222 }
1223
1224 /* Doesn't need the hardware lock.
1225  */
1226 int i915_irq_wait(struct drm_device *dev, void *data,
1227                          struct drm_file *file_priv)
1228 {
1229         drm_i915_private_t *dev_priv = dev->dev_private;
1230         drm_i915_irq_wait_t *irqwait = data;
1231
1232         if (!dev_priv) {
1233                 DRM_ERROR("called with no initialization\n");
1234                 return -EINVAL;
1235         }
1236
1237         return i915_wait_irq(dev, irqwait->irq_seq);
1238 }
1239
1240 /* Called from drm generic code, passed 'crtc' which
1241  * we use as a pipe index
1242  */
1243 int i915_enable_vblank(struct drm_device *dev, int pipe)
1244 {
1245         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1246         unsigned long irqflags;
1247
1248         if (!i915_pipe_enabled(dev, pipe))
1249                 return -EINVAL;
1250
1251         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1252         if (HAS_PCH_SPLIT(dev))
1253                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1254                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1255         else if (INTEL_INFO(dev)->gen >= 4)
1256                 i915_enable_pipestat(dev_priv, pipe,
1257                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1258         else
1259                 i915_enable_pipestat(dev_priv, pipe,
1260                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1261         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1262         return 0;
1263 }
1264
1265 /* Called from drm generic code, passed 'crtc' which
1266  * we use as a pipe index
1267  */
1268 void i915_disable_vblank(struct drm_device *dev, int pipe)
1269 {
1270         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1271         unsigned long irqflags;
1272
1273         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1274         if (HAS_PCH_SPLIT(dev))
1275                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1276                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1277         else
1278                 i915_disable_pipestat(dev_priv, pipe,
1279                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1280                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1281         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1282 }
1283
1284 void i915_enable_interrupt (struct drm_device *dev)
1285 {
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287
1288         if (!HAS_PCH_SPLIT(dev))
1289                 intel_opregion_enable_asle(dev);
1290         dev_priv->irq_enabled = 1;
1291 }
1292
1293
1294 /* Set the vblank monitor pipe
1295  */
1296 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1297                          struct drm_file *file_priv)
1298 {
1299         drm_i915_private_t *dev_priv = dev->dev_private;
1300
1301         if (!dev_priv) {
1302                 DRM_ERROR("called with no initialization\n");
1303                 return -EINVAL;
1304         }
1305
1306         return 0;
1307 }
1308
1309 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1310                          struct drm_file *file_priv)
1311 {
1312         drm_i915_private_t *dev_priv = dev->dev_private;
1313         drm_i915_vblank_pipe_t *pipe = data;
1314
1315         if (!dev_priv) {
1316                 DRM_ERROR("called with no initialization\n");
1317                 return -EINVAL;
1318         }
1319
1320         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1321
1322         return 0;
1323 }
1324
1325 /**
1326  * Schedule buffer swap at given vertical blank.
1327  */
1328 int i915_vblank_swap(struct drm_device *dev, void *data,
1329                      struct drm_file *file_priv)
1330 {
1331         /* The delayed swap mechanism was fundamentally racy, and has been
1332          * removed.  The model was that the client requested a delayed flip/swap
1333          * from the kernel, then waited for vblank before continuing to perform
1334          * rendering.  The problem was that the kernel might wake the client
1335          * up before it dispatched the vblank swap (since the lock has to be
1336          * held while touching the ringbuffer), in which case the client would
1337          * clear and start the next frame before the swap occurred, and
1338          * flicker would occur in addition to likely missing the vblank.
1339          *
1340          * In the absence of this ioctl, userland falls back to a correct path
1341          * of waiting for a vblank, then dispatching the swap on its own.
1342          * Context switching to userland and back is plenty fast enough for
1343          * meeting the requirements of vblank swapping.
1344          */
1345         return -EINVAL;
1346 }
1347
1348 static u32
1349 ring_last_seqno(struct intel_ring_buffer *ring)
1350 {
1351         return list_entry(ring->request_list.prev,
1352                           struct drm_i915_gem_request, list)->seqno;
1353 }
1354
1355 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1356 {
1357         if (list_empty(&ring->request_list) ||
1358             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1359                 /* Issue a wake-up to catch stuck h/w. */
1360                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1361                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1362                                   ring->name,
1363                                   ring->waiting_seqno,
1364                                   ring->get_seqno(ring));
1365                         wake_up_all(&ring->irq_queue);
1366                         *err = true;
1367                 }
1368                 return true;
1369         }
1370         return false;
1371 }
1372
1373 /**
1374  * This is called when the chip hasn't reported back with completed
1375  * batchbuffers in a long time. The first time this is called we simply record
1376  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1377  * again, we assume the chip is wedged and try to fix it.
1378  */
1379 void i915_hangcheck_elapsed(unsigned long data)
1380 {
1381         struct drm_device *dev = (struct drm_device *)data;
1382         drm_i915_private_t *dev_priv = dev->dev_private;
1383         uint32_t acthd, instdone, instdone1;
1384         bool err = false;
1385
1386         /* If all work is done then ACTHD clearly hasn't advanced. */
1387         if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) &&
1388             i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) &&
1389             i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) {
1390                 dev_priv->hangcheck_count = 0;
1391                 if (err)
1392                         goto repeat;
1393                 return;
1394         }
1395
1396         if (INTEL_INFO(dev)->gen < 4) {
1397                 acthd = I915_READ(ACTHD);
1398                 instdone = I915_READ(INSTDONE);
1399                 instdone1 = 0;
1400         } else {
1401                 acthd = I915_READ(ACTHD_I965);
1402                 instdone = I915_READ(INSTDONE_I965);
1403                 instdone1 = I915_READ(INSTDONE1);
1404         }
1405
1406         if (dev_priv->last_acthd == acthd &&
1407             dev_priv->last_instdone == instdone &&
1408             dev_priv->last_instdone1 == instdone1) {
1409                 if (dev_priv->hangcheck_count++ > 1) {
1410                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1411
1412                         if (!IS_GEN2(dev)) {
1413                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1414                                  * If so we can simply poke the RB_WAIT bit
1415                                  * and break the hang. This should work on
1416                                  * all but the second generation chipsets.
1417                                  */
1418                                 struct intel_ring_buffer *ring = &dev_priv->render_ring;
1419                                 u32 tmp = I915_READ_CTL(ring);
1420                                 if (tmp & RING_WAIT) {
1421                                         I915_WRITE_CTL(ring, tmp);
1422                                         goto repeat;
1423                                 }
1424                         }
1425
1426                         i915_handle_error(dev, true);
1427                         return;
1428                 }
1429         } else {
1430                 dev_priv->hangcheck_count = 0;
1431
1432                 dev_priv->last_acthd = acthd;
1433                 dev_priv->last_instdone = instdone;
1434                 dev_priv->last_instdone1 = instdone1;
1435         }
1436
1437 repeat:
1438         /* Reset timer case chip hangs without another request being added */
1439         mod_timer(&dev_priv->hangcheck_timer,
1440                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1441 }
1442
1443 /* drm_dma.h hooks
1444 */
1445 static void ironlake_irq_preinstall(struct drm_device *dev)
1446 {
1447         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1448
1449         I915_WRITE(HWSTAM, 0xeffe);
1450
1451         /* XXX hotplug from PCH */
1452
1453         I915_WRITE(DEIMR, 0xffffffff);
1454         I915_WRITE(DEIER, 0x0);
1455         POSTING_READ(DEIER);
1456
1457         /* and GT */
1458         I915_WRITE(GTIMR, 0xffffffff);
1459         I915_WRITE(GTIER, 0x0);
1460         POSTING_READ(GTIER);
1461
1462         /* south display irq */
1463         I915_WRITE(SDEIMR, 0xffffffff);
1464         I915_WRITE(SDEIER, 0x0);
1465         POSTING_READ(SDEIER);
1466 }
1467
1468 static int ironlake_irq_postinstall(struct drm_device *dev)
1469 {
1470         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1471         /* enable kind of interrupts always enabled */
1472         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1473                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1474         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1475         u32 hotplug_mask;
1476
1477         dev_priv->irq_mask_reg = ~display_mask;
1478         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1479
1480         /* should always can generate irq */
1481         I915_WRITE(DEIIR, I915_READ(DEIIR));
1482         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1483         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1484         POSTING_READ(DEIER);
1485
1486         if (IS_GEN6(dev)) {
1487                 render_mask =
1488                         GT_PIPE_NOTIFY |
1489                         GT_GEN6_BSD_USER_INTERRUPT |
1490                         GT_BLT_USER_INTERRUPT;
1491         }
1492
1493         dev_priv->gt_irq_mask_reg = ~render_mask;
1494         dev_priv->gt_irq_enable_reg = render_mask;
1495
1496         I915_WRITE(GTIIR, I915_READ(GTIIR));
1497         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1498         if (IS_GEN6(dev)) {
1499                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1500                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1501                 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1502         }
1503
1504         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1505         POSTING_READ(GTIER);
1506
1507         if (HAS_PCH_CPT(dev)) {
1508                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1509                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1510         } else {
1511                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1512                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1513         }
1514
1515         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1516         dev_priv->pch_irq_enable_reg = hotplug_mask;
1517
1518         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1519         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1520         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1521         POSTING_READ(SDEIER);
1522
1523         if (IS_IRONLAKE_M(dev)) {
1524                 /* Clear & enable PCU event interrupts */
1525                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1526                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1527                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1528         }
1529
1530         return 0;
1531 }
1532
1533 void i915_driver_irq_preinstall(struct drm_device * dev)
1534 {
1535         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1536
1537         atomic_set(&dev_priv->irq_received, 0);
1538
1539         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1540         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1541
1542         if (HAS_PCH_SPLIT(dev)) {
1543                 ironlake_irq_preinstall(dev);
1544                 return;
1545         }
1546
1547         if (I915_HAS_HOTPLUG(dev)) {
1548                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1549                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1550         }
1551
1552         I915_WRITE(HWSTAM, 0xeffe);
1553         I915_WRITE(PIPEASTAT, 0);
1554         I915_WRITE(PIPEBSTAT, 0);
1555         I915_WRITE(IMR, 0xffffffff);
1556         I915_WRITE(IER, 0x0);
1557         POSTING_READ(IER);
1558 }
1559
1560 /*
1561  * Must be called after intel_modeset_init or hotplug interrupts won't be
1562  * enabled correctly.
1563  */
1564 int i915_driver_irq_postinstall(struct drm_device *dev)
1565 {
1566         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1567         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1568         u32 error_mask;
1569
1570         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1571         if (HAS_BSD(dev))
1572                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1573         if (HAS_BLT(dev))
1574                 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1575
1576         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1577
1578         if (HAS_PCH_SPLIT(dev))
1579                 return ironlake_irq_postinstall(dev);
1580
1581         /* Unmask the interrupts that we always want on. */
1582         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1583
1584         dev_priv->pipestat[0] = 0;
1585         dev_priv->pipestat[1] = 0;
1586
1587         if (I915_HAS_HOTPLUG(dev)) {
1588                 /* Enable in IER... */
1589                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1590                 /* and unmask in IMR */
1591                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1592         }
1593
1594         /*
1595          * Enable some error detection, note the instruction error mask
1596          * bit is reserved, so we leave it masked.
1597          */
1598         if (IS_G4X(dev)) {
1599                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1600                                GM45_ERROR_MEM_PRIV |
1601                                GM45_ERROR_CP_PRIV |
1602                                I915_ERROR_MEMORY_REFRESH);
1603         } else {
1604                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1605                                I915_ERROR_MEMORY_REFRESH);
1606         }
1607         I915_WRITE(EMR, error_mask);
1608
1609         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1610         I915_WRITE(IER, enable_mask);
1611         POSTING_READ(IER);
1612
1613         if (I915_HAS_HOTPLUG(dev)) {
1614                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1615
1616                 /* Note HDMI and DP share bits */
1617                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1618                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1619                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1620                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1621                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1622                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1623                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1624                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1625                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1626                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1627                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1628                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1629
1630                         /* Programming the CRT detection parameters tends
1631                            to generate a spurious hotplug event about three
1632                            seconds later.  So just do it once.
1633                         */
1634                         if (IS_G4X(dev))
1635                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1636                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1637                 }
1638
1639                 /* Ignore TV since it's buggy */
1640
1641                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1642         }
1643
1644         intel_opregion_enable_asle(dev);
1645
1646         return 0;
1647 }
1648
1649 static void ironlake_irq_uninstall(struct drm_device *dev)
1650 {
1651         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1652         I915_WRITE(HWSTAM, 0xffffffff);
1653
1654         I915_WRITE(DEIMR, 0xffffffff);
1655         I915_WRITE(DEIER, 0x0);
1656         I915_WRITE(DEIIR, I915_READ(DEIIR));
1657
1658         I915_WRITE(GTIMR, 0xffffffff);
1659         I915_WRITE(GTIER, 0x0);
1660         I915_WRITE(GTIIR, I915_READ(GTIIR));
1661 }
1662
1663 void i915_driver_irq_uninstall(struct drm_device * dev)
1664 {
1665         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1666
1667         if (!dev_priv)
1668                 return;
1669
1670         dev_priv->vblank_pipe = 0;
1671
1672         if (HAS_PCH_SPLIT(dev)) {
1673                 ironlake_irq_uninstall(dev);
1674                 return;
1675         }
1676
1677         if (I915_HAS_HOTPLUG(dev)) {
1678                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1679                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1680         }
1681
1682         I915_WRITE(HWSTAM, 0xffffffff);
1683         I915_WRITE(PIPEASTAT, 0);
1684         I915_WRITE(PIPEBSTAT, 0);
1685         I915_WRITE(IMR, 0xffffffff);
1686         I915_WRITE(IER, 0x0);
1687
1688         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1689         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1690         I915_WRITE(IIR, I915_READ(IIR));
1691 }