drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include <linux/dma_remapping.h>
  36
  37 struct change_domains {
  38         uint32_t invalidate_domains;
  39         uint32_t flush_domains;
  40         uint32_t flush_rings;
  41         uint32_t flips;
  42 };
  43
  44 /*
  45  * Set the next domain for the specified object. This
  46  * may not actually perform the necessary flushing/invaliding though,
  47  * as that may want to be batched with other set_domain operations
  48  *
  49  * This is (we hope) the only really tricky part of gem. The goal
  50  * is fairly simple -- track which caches hold bits of the object
  51  * and make sure they remain coherent. A few concrete examples may
  52  * help to explain how it works. For shorthand, we use the notation
  53  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
  54  * a pair of read and write domain masks.
  55  *
  56  * Case 1: the batch buffer
  57  *
  58  *      1. Allocated
  59  *      2. Written by CPU
  60  *      3. Mapped to GTT
  61  *      4. Read by GPU
  62  *      5. Unmapped from GTT
  63  *      6. Freed
  64  *
  65  *      Let's take these a step at a time
  66  *
  67  *      1. Allocated
  68  *              Pages allocated from the kernel may still have
  69  *              cache contents, so we set them to (CPU, CPU) always.
  70  *      2. Written by CPU (using pwrite)
  71  *              The pwrite function calls set_domain (CPU, CPU) and
  72  *              this function does nothing (as nothing changes)
  73  *      3. Mapped by GTT
  74  *              This function asserts that the object is not
  75  *              currently in any GPU-based read or write domains
  76  *      4. Read by GPU
  77  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
  78  *              As write_domain is zero, this function adds in the
  79  *              current read domains (CPU+COMMAND, 0).
  80  *              flush_domains is set to CPU.
  81  *              invalidate_domains is set to COMMAND
  82  *              clflush is run to get data out of the CPU caches
  83  *              then i915_dev_set_domain calls i915_gem_flush to
  84  *              emit an MI_FLUSH and drm_agp_chipset_flush
  85  *      5. Unmapped from GTT
  86  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
  87  *              flush_domains and invalidate_domains end up both zero
  88  *              so no flushing/invalidating happens
  89  *      6. Freed
  90  *              yay, done
  91  *
  92  * Case 2: The shared render buffer
  93  *
  94  *      1. Allocated
  95  *      2. Mapped to GTT
  96  *      3. Read/written by GPU
  97  *      4. set_domain to (CPU,CPU)
  98  *      5. Read/written by CPU
  99  *      6. Read/written by GPU
 100  *
 101  *      1. Allocated
 102  *              Same as last example, (CPU, CPU)
 103  *      2. Mapped to GTT
 104  *              Nothing changes (assertions find that it is not in the GPU)
 105  *      3. Read/written by GPU
 106  *              execbuffer calls set_domain (RENDER, RENDER)
 107  *              flush_domains gets CPU
 108  *              invalidate_domains gets GPU
 109  *              clflush (obj)
 110  *              MI_FLUSH and drm_agp_chipset_flush
 111  *      4. set_domain (CPU, CPU)
 112  *              flush_domains gets GPU
 113  *              invalidate_domains gets CPU
 114  *              wait_rendering (obj) to make sure all drawing is complete.
 115  *              This will include an MI_FLUSH to get the data from GPU
 116  *              to memory
 117  *              clflush (obj) to invalidate the CPU cache
 118  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
 119  *      5. Read/written by CPU
 120  *              cache lines are loaded and dirtied
 121  *      6. Read written by GPU
 122  *              Same as last GPU access
 123  *
 124  * Case 3: The constant buffer
 125  *
 126  *      1. Allocated
 127  *      2. Written by CPU
 128  *      3. Read by GPU
 129  *      4. Updated (written) by CPU again
 130  *      5. Read by GPU
 131  *
 132  *      1. Allocated
 133  *              (CPU, CPU)
 134  *      2. Written by CPU
 135  *              (CPU, CPU)
 136  *      3. Read by GPU
 137  *              (CPU+RENDER, 0)
 138  *              flush_domains = CPU
 139  *              invalidate_domains = RENDER
 140  *              clflush (obj)
 141  *              MI_FLUSH
 142  *              drm_agp_chipset_flush
 143  *      4. Updated (written) by CPU again
 144  *              (CPU, CPU)
 145  *              flush_domains = 0 (no previous write domain)
 146  *              invalidate_domains = 0 (no new read domains)
 147  *      5. Read by GPU
 148  *              (CPU+RENDER, 0)
 149  *              flush_domains = CPU
 150  *              invalidate_domains = RENDER
 151  *              clflush (obj)
 152  *              MI_FLUSH
 153  *              drm_agp_chipset_flush
 154  */
 155 static void
 156 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
 157                                   struct intel_ring_buffer *ring,
 158                                   struct change_domains *cd)
 159 {
 160         uint32_t invalidate_domains = 0, flush_domains = 0;
 161
 162         /*
 163          * If the object isn't moving to a new write domain,
 164          * let the object stay in multiple read domains
 165          */
 166         if (obj->base.pending_write_domain == 0)
 167                 obj->base.pending_read_domains |= obj->base.read_domains;
 168
 169         /*
 170          * Flush the current write domain if
 171          * the new read domains don't match. Invalidate
 172          * any read domains which differ from the old
 173          * write domain
 174          */
 175         if (obj->base.write_domain &&
 176             (((obj->base.write_domain != obj->base.pending_read_domains ||
 177                obj->ring != ring)) ||
 178              (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
 179                 flush_domains |= obj->base.write_domain;
 180                 invalidate_domains |=
 181                         obj->base.pending_read_domains & ~obj->base.write_domain;
 182         }
 183         /*
 184          * Invalidate any read caches which may have
 185          * stale data. That is, any new read domains.
 186          */
 187         invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
 188         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
 189                 i915_gem_clflush_object(obj);
 190
 191         if (obj->base.pending_write_domain)
 192                 cd->flips |= atomic_read(&obj->pending_flip);
 193
 194         /* The actual obj->write_domain will be updated with
 195          * pending_write_domain after we emit the accumulated flush for all
 196          * of our domain changes in execbuffers (which clears objects'
 197          * write_domains).  So if we have a current write domain that we
 198          * aren't changing, set pending_write_domain to that.
 199          */
 200         if (flush_domains == 0 && obj->base.pending_write_domain == 0)
 201                 obj->base.pending_write_domain = obj->base.write_domain;
 202
 203         cd->invalidate_domains |= invalidate_domains;
 204         cd->flush_domains |= flush_domains;
 205         if (flush_domains & I915_GEM_GPU_DOMAINS)
 206                 cd->flush_rings |= intel_ring_flag(obj->ring);
 207         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
 208                 cd->flush_rings |= intel_ring_flag(ring);
 209 }
 210
 211 struct eb_objects {
 212         int and;
 213         struct hlist_head buckets[0];
 214 };
 215
 216 static struct eb_objects *
 217 eb_create(int size)
 218 {
 219         struct eb_objects *eb;
 220         int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
 221         while (count > size)
 222                 count >>= 1;
 223         eb = kzalloc(count*sizeof(struct hlist_head) +
 224                      sizeof(struct eb_objects),
 225                      GFP_KERNEL);
 226         if (eb == NULL)
 227                 return eb;
 228
 229         eb->and = count - 1;
 230         return eb;
 231 }
 232
 233 static void
 234 eb_reset(struct eb_objects *eb)
 235 {
 236         memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 237 }
 238
 239 static void
 240 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
 241 {
 242         hlist_add_head(&obj->exec_node,
 243                        &eb->buckets[obj->exec_handle & eb->and]);
 244 }
 245
 246 static struct drm_i915_gem_object *
 247 eb_get_object(struct eb_objects *eb, unsigned long handle)
 248 {
 249         struct hlist_head *head;
 250         struct hlist_node *node;
 251         struct drm_i915_gem_object *obj;
 252
 253         head = &eb->buckets[handle & eb->and];
 254         hlist_for_each(node, head) {
 255                 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
 256                 if (obj->exec_handle == handle)
 257                         return obj;
 258         }
 259
 260         return NULL;
 261 }
 262
 263 static void
 264 eb_destroy(struct eb_objects *eb)
 265 {
 266         kfree(eb);
 267 }
 268
 269 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 270 {
 271         return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 272                 obj->cache_level != I915_CACHE_NONE);
 273 }
 274
 275 static int
 276 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 277                                    struct eb_objects *eb,
 278                                    struct drm_i915_gem_relocation_entry *reloc)
 279 {
 280         struct drm_device *dev = obj->base.dev;
 281         struct drm_gem_object *target_obj;
 282         struct drm_i915_gem_object *target_i915_obj;
 283         uint32_t target_offset;
 284         int ret = -EINVAL;
 285
 286         /* we've already hold a reference to all valid objects */
 287         target_obj = &eb_get_object(eb, reloc->target_handle)->base;
 288         if (unlikely(target_obj == NULL))
 289                 return -ENOENT;
 290
 291         target_i915_obj = to_intel_bo(target_obj);
 292         target_offset = target_i915_obj->gtt_offset;
 293
 294         /* The target buffer should have appeared before us in the
 295          * exec_object list, so it should have a GTT space bound by now.
 296          */
 297         if (unlikely(target_offset == 0)) {
 298                 DRM_DEBUG("No GTT space found for object %d\n",
 299                           reloc->target_handle);
 300                 return ret;
 301         }
 302
 303         /* Validate that the target is in a valid r/w GPU domain */
 304         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 305                 DRM_DEBUG("reloc with multiple write domains: "
 306                           "obj %p target %d offset %d "
 307                           "read %08x write %08x",
 308                           obj, reloc->target_handle,
 309                           (int) reloc->offset,
 310                           reloc->read_domains,
 311                           reloc->write_domain);
 312                 return ret;
 313         }
 314         if (unlikely((reloc->write_domain | reloc->read_domains)
 315                      & ~I915_GEM_GPU_DOMAINS)) {
 316                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 317                           "obj %p target %d offset %d "
 318                           "read %08x write %08x",
 319                           obj, reloc->target_handle,
 320                           (int) reloc->offset,
 321                           reloc->read_domains,
 322                           reloc->write_domain);
 323                 return ret;
 324         }
 325         if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
 326                      reloc->write_domain != target_obj->pending_write_domain)) {
 327                 DRM_DEBUG("Write domain conflict: "
 328                           "obj %p target %d offset %d "
 329                           "new %08x old %08x\n",
 330                           obj, reloc->target_handle,
 331                           (int) reloc->offset,
 332                           reloc->write_domain,
 333                           target_obj->pending_write_domain);
 334                 return ret;
 335         }
 336
 337         target_obj->pending_read_domains |= reloc->read_domains;
 338         target_obj->pending_write_domain |= reloc->write_domain;
 339
 340         /* If the relocation already has the right value in it, no
 341          * more work needs to be done.
 342          */
 343         if (target_offset == reloc->presumed_offset)
 344                 return 0;
 345
 346         /* Check that the relocation address is valid... */
 347         if (unlikely(reloc->offset > obj->base.size - 4)) {
 348                 DRM_DEBUG("Relocation beyond object bounds: "
 349                           "obj %p target %d offset %d size %d.\n",
 350                           obj, reloc->target_handle,
 351                           (int) reloc->offset,
 352                           (int) obj->base.size);
 353                 return ret;
 354         }
 355         if (unlikely(reloc->offset & 3)) {
 356                 DRM_DEBUG("Relocation not 4-byte aligned: "
 357                           "obj %p target %d offset %d.\n",
 358                           obj, reloc->target_handle,
 359                           (int) reloc->offset);
 360                 return ret;
 361         }
 362
 363         /* We can't wait for rendering with pagefaults disabled */
 364         if (obj->active && in_atomic())
 365                 return -EFAULT;
 366
 367         reloc->delta += target_offset;
 368         if (use_cpu_reloc(obj)) {
 369                 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
 370                 char *vaddr;
 371
 372                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 373                 if (ret)
 374                         return ret;
 375
 376                 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
 377                 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
 378                 kunmap_atomic(vaddr);
 379         } else {
 380                 struct drm_i915_private *dev_priv = dev->dev_private;
 381                 uint32_t __iomem *reloc_entry;
 382                 void __iomem *reloc_page;
 383
 384                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 385                 if (ret)
 386                         return ret;
 387
 388                 /* Map the page containing the relocation we're going to perform.  */
 389                 reloc->offset += obj->gtt_offset;
 390                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 391                                                       reloc->offset & PAGE_MASK);
 392                 reloc_entry = (uint32_t __iomem *)
 393                         (reloc_page + (reloc->offset & ~PAGE_MASK));
 394                 iowrite32(reloc->delta, reloc_entry);
 395                 io_mapping_unmap_atomic(reloc_page);
 396         }
 397
 398         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 399          * pipe_control writes because the gpu doesn't properly redirect them
 400          * through the ppgtt for non_secure batchbuffers. */
 401         if (unlikely(IS_GEN6(dev) &&
 402             reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
 403             !target_i915_obj->has_global_gtt_mapping)) {
 404                 i915_gem_gtt_bind_object(target_i915_obj,
 405                                          target_i915_obj->cache_level);
 406         }
 407
 408         /* and update the user's relocation entry */
 409         reloc->presumed_offset = target_offset;
 410
 411         return 0;
 412 }
 413
 414 static int
 415 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
 416                                     struct eb_objects *eb)
 417 {
 418 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
 419         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
 420         struct drm_i915_gem_relocation_entry __user *user_relocs;
 421         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 422         int remain, ret;
 423
 424         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
 425
 426         remain = entry->relocation_count;
 427         while (remain) {
 428                 struct drm_i915_gem_relocation_entry *r = stack_reloc;
 429                 int count = remain;
 430                 if (count > ARRAY_SIZE(stack_reloc))
 431                         count = ARRAY_SIZE(stack_reloc);
 432                 remain -= count;
 433
 434                 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
 435                         return -EFAULT;
 436
 437                 do {
 438                         u64 offset = r->presumed_offset;
 439
 440                         ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
 441                         if (ret)
 442                                 return ret;
 443
 444                         if (r->presumed_offset != offset &&
 445                             __copy_to_user_inatomic(&user_relocs->presumed_offset,
 446                                                     &r->presumed_offset,
 447                                                     sizeof(r->presumed_offset))) {
 448                                 return -EFAULT;
 449                         }
 450
 451                         user_relocs++;
 452                         r++;
 453                 } while (--count);
 454         }
 455
 456         return 0;
 457 #undef N_RELOC
 458 }
 459
 460 static int
 461 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
 462                                          struct eb_objects *eb,
 463                                          struct drm_i915_gem_relocation_entry *relocs)
 464 {
 465         const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 466         int i, ret;
 467
 468         for (i = 0; i < entry->relocation_count; i++) {
 469                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
 470                 if (ret)
 471                         return ret;
 472         }
 473
 474         return 0;
 475 }
 476
 477 static int
 478 i915_gem_execbuffer_relocate(struct drm_device *dev,
 479                              struct eb_objects *eb,
 480                              struct list_head *objects)
 481 {
 482         struct drm_i915_gem_object *obj;
 483         int ret = 0;
 484
 485         /* This is the fast path and we cannot handle a pagefault whilst
 486          * holding the struct mutex lest the user pass in the relocations
 487          * contained within a mmaped bo. For in such a case we, the page
 488          * fault handler would call i915_gem_fault() and we would try to
 489          * acquire the struct mutex again. Obviously this is bad and so
 490          * lockdep complains vehemently.
 491          */
 492         pagefault_disable();
 493         list_for_each_entry(obj, objects, exec_list) {
 494                 ret = i915_gem_execbuffer_relocate_object(obj, eb);
 495                 if (ret)
 496                         break;
 497         }
 498         pagefault_enable();
 499
 500         return ret;
 501 }
 502
 503 #define  __EXEC_OBJECT_HAS_FENCE (1<<31)
 504
 505 static int
 506 need_reloc_mappable(struct drm_i915_gem_object *obj)
 507 {
 508         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 509         return entry->relocation_count && !use_cpu_reloc(obj);
 510 }
 511
 512 static int
 513 pin_and_fence_object(struct drm_i915_gem_object *obj,
 514                      struct intel_ring_buffer *ring)
 515 {
 516         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 517         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 518         bool need_fence, need_mappable;
 519         int ret;
 520
 521         need_fence =
 522                 has_fenced_gpu_access &&
 523                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 524                 obj->tiling_mode != I915_TILING_NONE;
 525         need_mappable = need_fence || need_reloc_mappable(obj);
 526
 527         ret = i915_gem_object_pin(obj, entry->alignment, need_mappable);
 528         if (ret)
 529                 return ret;
 530
 531         if (has_fenced_gpu_access) {
 532                 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 533                         if (obj->tiling_mode) {
 534                                 ret = i915_gem_object_get_fence(obj, ring);
 535                                 if (ret)
 536                                         goto err_unpin;
 537
 538                                 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 539                                 i915_gem_object_pin_fence(obj);
 540                         } else {
 541                                 ret = i915_gem_object_put_fence(obj);
 542                                 if (ret)
 543                                         goto err_unpin;
 544                         }
 545                         obj->pending_fenced_gpu_access = true;
 546                 }
 547         }
 548
 549         entry->offset = obj->gtt_offset;
 550         return 0;
 551
 552 err_unpin:
 553         i915_gem_object_unpin(obj);
 554         return ret;
 555 }
 556
 557 static int
 558 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
 559                             struct drm_file *file,
 560                             struct list_head *objects)
 561 {
 562         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 563         struct drm_i915_gem_object *obj;
 564         int ret, retry;
 565         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 566         struct list_head ordered_objects;
 567
 568         INIT_LIST_HEAD(&ordered_objects);
 569         while (!list_empty(objects)) {
 570                 struct drm_i915_gem_exec_object2 *entry;
 571                 bool need_fence, need_mappable;
 572
 573                 obj = list_first_entry(objects,
 574                                        struct drm_i915_gem_object,
 575                                        exec_list);
 576                 entry = obj->exec_entry;
 577
 578                 need_fence =
 579                         has_fenced_gpu_access &&
 580                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 581                         obj->tiling_mode != I915_TILING_NONE;
 582                 need_mappable = need_fence || need_reloc_mappable(obj);
 583
 584                 if (need_mappable)
 585                         list_move(&obj->exec_list, &ordered_objects);
 586                 else
 587                         list_move_tail(&obj->exec_list, &ordered_objects);
 588
 589                 obj->base.pending_read_domains = 0;
 590                 obj->base.pending_write_domain = 0;
 591         }
 592         list_splice(&ordered_objects, objects);
 593
 594         /* Attempt to pin all of the buffers into the GTT.
 595          * This is done in 3 phases:
 596          *
 597          * 1a. Unbind all objects that do not match the GTT constraints for
 598          *     the execbuffer (fenceable, mappable, alignment etc).
 599          * 1b. Increment pin count for already bound objects.
 600          * 2.  Bind new objects.
 601          * 3.  Decrement pin count.
 602          *
 603          * This avoid unnecessary unbinding of later objects in order to makr
 604          * room for the earlier objects *unless* we need to defragment.
 605          */
 606         retry = 0;
 607         do {
 608                 ret = 0;
 609
 610                 /* Unbind any ill-fitting objects or pin. */
 611                 list_for_each_entry(obj, objects, exec_list) {
 612                         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 613                         bool need_fence, need_mappable;
 614
 615                         if (!obj->gtt_space)
 616                                 continue;
 617
 618                         need_fence =
 619                                 has_fenced_gpu_access &&
 620                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 621                                 obj->tiling_mode != I915_TILING_NONE;
 622                         need_mappable = need_fence || need_reloc_mappable(obj);
 623
 624                         if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
 625                             (need_mappable && !obj->map_and_fenceable))
 626                                 ret = i915_gem_object_unbind(obj);
 627                         else
 628                                 ret = pin_and_fence_object(obj, ring);
 629                         if (ret)
 630                                 goto err;
 631                 }
 632
 633                 /* Bind fresh objects */
 634                 list_for_each_entry(obj, objects, exec_list) {
 635                         if (obj->gtt_space)
 636                                 continue;
 637
 638                         ret = pin_and_fence_object(obj, ring);
 639                         if (ret) {
 640                                 int ret_ignore;
 641
 642                                 /* This can potentially raise a harmless
 643                                  * -EINVAL if we failed to bind in the above
 644                                  * call. It cannot raise -EINTR since we know
 645                                  * that the bo is freshly bound and so will
 646                                  * not need to be flushed or waited upon.
 647                                  */
 648                                 ret_ignore = i915_gem_object_unbind(obj);
 649                                 (void)ret_ignore;
 650                                 WARN_ON(obj->gtt_space);
 651                                 break;
 652                         }
 653                 }
 654
 655                 /* Decrement pin count for bound objects */
 656                 list_for_each_entry(obj, objects, exec_list) {
 657                         struct drm_i915_gem_exec_object2 *entry;
 658
 659                         if (!obj->gtt_space)
 660                                 continue;
 661
 662                         entry = obj->exec_entry;
 663                         if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
 664                                 i915_gem_object_unpin_fence(obj);
 665                                 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
 666                         }
 667
 668                         i915_gem_object_unpin(obj);
 669
 670                         /* ... and ensure ppgtt mapping exist if needed. */
 671                         if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
 672                                 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
 673                                                        obj, obj->cache_level);
 674
 675                                 obj->has_aliasing_ppgtt_mapping = 1;
 676                         }
 677                 }
 678
 679                 if (ret != -ENOSPC || retry > 1)
 680                         return ret;
 681
 682                 /* First attempt, just clear anything that is purgeable.
 683                  * Second attempt, clear the entire GTT.
 684                  */
 685                 ret = i915_gem_evict_everything(ring->dev, retry == 0);
 686                 if (ret)
 687                         return ret;
 688
 689                 retry++;
 690         } while (1);
 691
 692 err:
 693         list_for_each_entry_continue_reverse(obj, objects, exec_list) {
 694                 struct drm_i915_gem_exec_object2 *entry;
 695
 696                 if (!obj->gtt_space)
 697                         continue;
 698
 699                 entry = obj->exec_entry;
 700                 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
 701                         i915_gem_object_unpin_fence(obj);
 702                         entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
 703                 }
 704
 705                 i915_gem_object_unpin(obj);
 706         }
 707
 708         return ret;
 709 }
 710
 711 static int
 712 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 713                                   struct drm_file *file,
 714                                   struct intel_ring_buffer *ring,
 715                                   struct list_head *objects,
 716                                   struct eb_objects *eb,
 717                                   struct drm_i915_gem_exec_object2 *exec,
 718                                   int count)
 719 {
 720         struct drm_i915_gem_relocation_entry *reloc;
 721         struct drm_i915_gem_object *obj;
 722         int *reloc_offset;
 723         int i, total, ret;
 724
 725         /* We may process another execbuffer during the unlock... */
 726         while (!list_empty(objects)) {
 727                 obj = list_first_entry(objects,
 728                                        struct drm_i915_gem_object,
 729                                        exec_list);
 730                 list_del_init(&obj->exec_list);
 731                 drm_gem_object_unreference(&obj->base);
 732         }
 733
 734         mutex_unlock(&dev->struct_mutex);
 735
 736         total = 0;
 737         for (i = 0; i < count; i++)
 738                 total += exec[i].relocation_count;
 739
 740         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
 741         reloc = drm_malloc_ab(total, sizeof(*reloc));
 742         if (reloc == NULL || reloc_offset == NULL) {
 743                 drm_free_large(reloc);
 744                 drm_free_large(reloc_offset);
 745                 mutex_lock(&dev->struct_mutex);
 746                 return -ENOMEM;
 747         }
 748
 749         total = 0;
 750         for (i = 0; i < count; i++) {
 751                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 752
 753                 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
 754
 755                 if (copy_from_user(reloc+total, user_relocs,
 756                                    exec[i].relocation_count * sizeof(*reloc))) {
 757                         ret = -EFAULT;
 758                         mutex_lock(&dev->struct_mutex);
 759                         goto err;
 760                 }
 761
 762                 reloc_offset[i] = total;
 763                 total += exec[i].relocation_count;
 764         }
 765
 766         ret = i915_mutex_lock_interruptible(dev);
 767         if (ret) {
 768                 mutex_lock(&dev->struct_mutex);
 769                 goto err;
 770         }
 771
 772         /* reacquire the objects */
 773         eb_reset(eb);
 774         for (i = 0; i < count; i++) {
 775                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
 776                                                         exec[i].handle));
 777                 if (&obj->base == NULL) {
 778                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 779                                    exec[i].handle, i);
 780                         ret = -ENOENT;
 781                         goto err;
 782                 }
 783
 784                 list_add_tail(&obj->exec_list, objects);
 785                 obj->exec_handle = exec[i].handle;
 786                 obj->exec_entry = &exec[i];
 787                 eb_add_object(eb, obj);
 788         }
 789
 790         ret = i915_gem_execbuffer_reserve(ring, file, objects);
 791         if (ret)
 792                 goto err;
 793
 794         list_for_each_entry(obj, objects, exec_list) {
 795                 int offset = obj->exec_entry - exec;
 796                 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
 797                                                                reloc + reloc_offset[offset]);
 798                 if (ret)
 799                         goto err;
 800         }
 801
 802         /* Leave the user relocations as are, this is the painfully slow path,
 803          * and we want to avoid the complication of dropping the lock whilst
 804          * having buffers reserved in the aperture and so causing spurious
 805          * ENOSPC for random operations.
 806          */
 807
 808 err:
 809         drm_free_large(reloc);
 810         drm_free_large(reloc_offset);
 811         return ret;
 812 }
 813
 814 static int
 815 i915_gem_execbuffer_flush(struct drm_device *dev,
 816                           uint32_t invalidate_domains,
 817                           uint32_t flush_domains,
 818                           uint32_t flush_rings)
 819 {
 820         drm_i915_private_t *dev_priv = dev->dev_private;
 821         int i, ret;
 822
 823         if (flush_domains & I915_GEM_DOMAIN_CPU)
 824                 intel_gtt_chipset_flush();
 825
 826         if (flush_domains & I915_GEM_DOMAIN_GTT)
 827                 wmb();
 828
 829         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
 830                 for (i = 0; i < I915_NUM_RINGS; i++)
 831                         if (flush_rings & (1 << i)) {
 832                                 ret = i915_gem_flush_ring(&dev_priv->ring[i],
 833                                                           invalidate_domains,
 834                                                           flush_domains);
 835                                 if (ret)
 836                                         return ret;
 837                         }
 838         }
 839
 840         return 0;
 841 }
 842
 843 static bool
 844 intel_enable_semaphores(struct drm_device *dev)
 845 {
 846         if (INTEL_INFO(dev)->gen < 6)
 847                 return 0;
 848
 849         if (i915_semaphores >= 0)
 850                 return i915_semaphores;
 851
 852         /* Disable semaphores on SNB */
 853         if (INTEL_INFO(dev)->gen == 6)
 854                 return 0;
 855
 856         return 1;
 857 }
 858
 859 static int
 860 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
 861                                struct intel_ring_buffer *to)
 862 {
 863         struct intel_ring_buffer *from = obj->ring;
 864         u32 seqno;
 865         int ret, idx;
 866
 867         if (from == NULL || to == from)
 868                 return 0;
 869
 870         /* XXX gpu semaphores are implicated in various hard hangs on SNB */
 871         if (!intel_enable_semaphores(obj->base.dev))
 872                 return i915_gem_object_wait_rendering(obj);
 873
 874         idx = intel_ring_sync_index(from, to);
 875
 876         seqno = obj->last_rendering_seqno;
 877         if (seqno <= from->sync_seqno[idx])
 878                 return 0;
 879
 880         if (seqno == from->outstanding_lazy_request) {
 881                 struct drm_i915_gem_request *request;
 882
 883                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 884                 if (request == NULL)
 885                         return -ENOMEM;
 886
 887                 ret = i915_add_request(from, NULL, request);
 888                 if (ret) {
 889                         kfree(request);
 890                         return ret;
 891                 }
 892
 893                 seqno = request->seqno;
 894         }
 895
 896         from->sync_seqno[idx] = seqno;
 897
 898         return to->sync_to(to, from, seqno - 1);
 899 }
 900
 901 static int
 902 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
 903 {
 904         u32 plane, flip_mask;
 905         int ret;
 906
 907         /* Check for any pending flips. As we only maintain a flip queue depth
 908          * of 1, we can simply insert a WAIT for the next display flip prior
 909          * to executing the batch and avoid stalling the CPU.
 910          */
 911
 912         for (plane = 0; flips >> plane; plane++) {
 913                 if (((flips >> plane) & 1) == 0)
 914                         continue;
 915
 916                 if (plane)
 917                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
 918                 else
 919                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
 920
 921                 ret = intel_ring_begin(ring, 2);
 922                 if (ret)
 923                         return ret;
 924
 925                 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
 926                 intel_ring_emit(ring, MI_NOOP);
 927                 intel_ring_advance(ring);
 928         }
 929
 930         return 0;
 931 }
 932
 933
 934 static int
 935 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
 936                                 struct list_head *objects)
 937 {
 938         struct drm_i915_gem_object *obj;
 939         struct change_domains cd;
 940         int ret;
 941
 942         memset(&cd, 0, sizeof(cd));
 943         list_for_each_entry(obj, objects, exec_list)
 944                 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
 945
 946         if (cd.invalidate_domains | cd.flush_domains) {
 947                 ret = i915_gem_execbuffer_flush(ring->dev,
 948                                                 cd.invalidate_domains,
 949                                                 cd.flush_domains,
 950                                                 cd.flush_rings);
 951                 if (ret)
 952                         return ret;
 953         }
 954
 955         if (cd.flips) {
 956                 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
 957                 if (ret)
 958                         return ret;
 959         }
 960
 961         list_for_each_entry(obj, objects, exec_list) {
 962                 ret = i915_gem_execbuffer_sync_rings(obj, ring);
 963                 if (ret)
 964                         return ret;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static bool
 971 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
 972 {
 973         return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
 974 }
 975
 976 static int
 977 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 978                    int count)
 979 {
 980         int i;
 981
 982         for (i = 0; i < count; i++) {
 983                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
 984                 int length; /* limited by fault_in_pages_readable() */
 985
 986                 /* First check for malicious input causing overflow */
 987                 if (exec[i].relocation_count >
 988                     INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
 989                         return -EINVAL;
 990
 991                 length = exec[i].relocation_count *
 992                         sizeof(struct drm_i915_gem_relocation_entry);
 993                 if (!access_ok(VERIFY_READ, ptr, length))
 994                         return -EFAULT;
 995
 996                 /* we may also need to update the presumed offsets */
 997                 if (!access_ok(VERIFY_WRITE, ptr, length))
 998                         return -EFAULT;
 999
1000                 if (fault_in_multipages_readable(ptr, length))
1001                         return -EFAULT;
1002         }
1003
1004         return 0;
1005 }
1006
1007 static void
1008 i915_gem_execbuffer_move_to_active(struct list_head *objects,
1009                                    struct intel_ring_buffer *ring,
1010                                    u32 seqno)
1011 {
1012         struct drm_i915_gem_object *obj;
1013
1014         list_for_each_entry(obj, objects, exec_list) {
1015                   u32 old_read = obj->base.read_domains;
1016                   u32 old_write = obj->base.write_domain;
1017
1018
1019                 obj->base.read_domains = obj->base.pending_read_domains;
1020                 obj->base.write_domain = obj->base.pending_write_domain;
1021                 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
1022
1023                 i915_gem_object_move_to_active(obj, ring, seqno);
1024                 if (obj->base.write_domain) {
1025                         obj->dirty = 1;
1026                         obj->pending_gpu_write = true;
1027                         list_move_tail(&obj->gpu_write_list,
1028                                        &ring->gpu_write_list);
1029                         intel_mark_busy(ring->dev, obj);
1030                 }
1031
1032                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1033         }
1034 }
1035
1036 static void
1037 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
1038                                     struct drm_file *file,
1039                                     struct intel_ring_buffer *ring)
1040 {
1041         struct drm_i915_gem_request *request;
1042         u32 invalidate;
1043
1044         /*
1045          * Ensure that the commands in the batch buffer are
1046          * finished before the interrupt fires.
1047          *
1048          * The sampler always gets flushed on i965 (sigh).
1049          */
1050         invalidate = I915_GEM_DOMAIN_COMMAND;
1051         if (INTEL_INFO(dev)->gen >= 4)
1052                 invalidate |= I915_GEM_DOMAIN_SAMPLER;
1053         if (ring->flush(ring, invalidate, 0)) {
1054                 i915_gem_next_request_seqno(ring);
1055                 return;
1056         }
1057
1058         /* Add a breadcrumb for the completion of the batch buffer */
1059         request = kzalloc(sizeof(*request), GFP_KERNEL);
1060         if (request == NULL || i915_add_request(ring, file, request)) {
1061                 i915_gem_next_request_seqno(ring);
1062                 kfree(request);
1063         }
1064 }
1065
1066 static int
1067 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1068                             struct intel_ring_buffer *ring)
1069 {
1070         drm_i915_private_t *dev_priv = dev->dev_private;
1071         int ret, i;
1072
1073         if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
1074                 return 0;
1075
1076         ret = intel_ring_begin(ring, 4 * 3);
1077         if (ret)
1078                 return ret;
1079
1080         for (i = 0; i < 4; i++) {
1081                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1082                 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1083                 intel_ring_emit(ring, 0);
1084         }
1085
1086         intel_ring_advance(ring);
1087
1088         return 0;
1089 }
1090
1091 static int
1092 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1093                        struct drm_file *file,
1094                        struct drm_i915_gem_execbuffer2 *args,
1095                        struct drm_i915_gem_exec_object2 *exec)
1096 {
1097         drm_i915_private_t *dev_priv = dev->dev_private;
1098         struct list_head objects;
1099         struct eb_objects *eb;
1100         struct drm_i915_gem_object *batch_obj;
1101         struct drm_clip_rect *cliprects = NULL;
1102         struct intel_ring_buffer *ring;
1103         u32 exec_start, exec_len;
1104         u32 seqno;
1105         u32 mask;
1106         int ret, mode, i;
1107
1108         if (!i915_gem_check_execbuffer(args)) {
1109                 DRM_DEBUG("execbuf with invalid offset/length\n");
1110                 return -EINVAL;
1111         }
1112
1113         ret = validate_exec_list(exec, args->buffer_count);
1114         if (ret)
1115                 return ret;
1116
1117         switch (args->flags & I915_EXEC_RING_MASK) {
1118         case I915_EXEC_DEFAULT:
1119         case I915_EXEC_RENDER:
1120                 ring = &dev_priv->ring[RCS];
1121                 break;
1122         case I915_EXEC_BSD:
1123                 if (!HAS_BSD(dev)) {
1124                         DRM_DEBUG("execbuf with invalid ring (BSD)\n");
1125                         return -EINVAL;
1126                 }
1127                 ring = &dev_priv->ring[VCS];
1128                 break;
1129         case I915_EXEC_BLT:
1130                 if (!HAS_BLT(dev)) {
1131                         DRM_DEBUG("execbuf with invalid ring (BLT)\n");
1132                         return -EINVAL;
1133                 }
1134                 ring = &dev_priv->ring[BCS];
1135                 break;
1136         default:
1137                 DRM_DEBUG("execbuf with unknown ring: %d\n",
1138                           (int)(args->flags & I915_EXEC_RING_MASK));
1139                 return -EINVAL;
1140         }
1141
1142         mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1143         mask = I915_EXEC_CONSTANTS_MASK;
1144         switch (mode) {
1145         case I915_EXEC_CONSTANTS_REL_GENERAL:
1146         case I915_EXEC_CONSTANTS_ABSOLUTE:
1147         case I915_EXEC_CONSTANTS_REL_SURFACE:
1148                 if (ring == &dev_priv->ring[RCS] &&
1149                     mode != dev_priv->relative_constants_mode) {
1150                         if (INTEL_INFO(dev)->gen < 4)
1151                                 return -EINVAL;
1152
1153                         if (INTEL_INFO(dev)->gen > 5 &&
1154                             mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1155                                 return -EINVAL;
1156
1157                         /* The HW changed the meaning on this bit on gen6 */
1158                         if (INTEL_INFO(dev)->gen >= 6)
1159                                 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1160                 }
1161                 break;
1162         default:
1163                 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1164                 return -EINVAL;
1165         }
1166
1167         if (args->buffer_count < 1) {
1168                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1169                 return -EINVAL;
1170         }
1171
1172         if (args->num_cliprects != 0) {
1173                 if (ring != &dev_priv->ring[RCS]) {
1174                         DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1175                         return -EINVAL;
1176                 }
1177
1178                 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1179                                     GFP_KERNEL);
1180                 if (cliprects == NULL) {
1181                         ret = -ENOMEM;
1182                         goto pre_mutex_err;
1183                 }
1184
1185                 if (copy_from_user(cliprects,
1186                                      (struct drm_clip_rect __user *)(uintptr_t)
1187                                      args->cliprects_ptr,
1188                                      sizeof(*cliprects)*args->num_cliprects)) {
1189                         ret = -EFAULT;
1190                         goto pre_mutex_err;
1191                 }
1192         }
1193
1194         ret = i915_mutex_lock_interruptible(dev);
1195         if (ret)
1196                 goto pre_mutex_err;
1197
1198         if (dev_priv->mm.suspended) {
1199                 mutex_unlock(&dev->struct_mutex);
1200                 ret = -EBUSY;
1201                 goto pre_mutex_err;
1202         }
1203
1204         eb = eb_create(args->buffer_count);
1205         if (eb == NULL) {
1206                 mutex_unlock(&dev->struct_mutex);
1207                 ret = -ENOMEM;
1208                 goto pre_mutex_err;
1209         }
1210
1211         /* Look up object handles */
1212         INIT_LIST_HEAD(&objects);
1213         for (i = 0; i < args->buffer_count; i++) {
1214                 struct drm_i915_gem_object *obj;
1215
1216                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1217                                                         exec[i].handle));
1218                 if (&obj->base == NULL) {
1219                         DRM_DEBUG("Invalid object handle %d at index %d\n",
1220                                    exec[i].handle, i);
1221                         /* prevent error path from reading uninitialized data */
1222                         ret = -ENOENT;
1223                         goto err;
1224                 }
1225
1226                 if (!list_empty(&obj->exec_list)) {
1227                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
1228                                    obj, exec[i].handle, i);
1229                         ret = -EINVAL;
1230                         goto err;
1231                 }
1232
1233                 list_add_tail(&obj->exec_list, &objects);
1234                 obj->exec_handle = exec[i].handle;
1235                 obj->exec_entry = &exec[i];
1236                 eb_add_object(eb, obj);
1237         }
1238
1239         /* take note of the batch buffer before we might reorder the lists */
1240         batch_obj = list_entry(objects.prev,
1241                                struct drm_i915_gem_object,
1242                                exec_list);
1243
1244         /* Move the objects en-masse into the GTT, evicting if necessary. */
1245         ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1246         if (ret)
1247                 goto err;
1248
1249         /* The objects are in their final locations, apply the relocations. */
1250         ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1251         if (ret) {
1252                 if (ret == -EFAULT) {
1253                         ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1254                                                                 &objects, eb,
1255                                                                 exec,
1256                                                                 args->buffer_count);
1257                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1258                 }
1259                 if (ret)
1260                         goto err;
1261         }
1262
1263         /* Set the pending read domains for the batch buffer to COMMAND */
1264         if (batch_obj->base.pending_write_domain) {
1265                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1266                 ret = -EINVAL;
1267                 goto err;
1268         }
1269         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1270
1271         ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1272         if (ret)
1273                 goto err;
1274
1275         seqno = i915_gem_next_request_seqno(ring);
1276         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1277                 if (seqno < ring->sync_seqno[i]) {
1278                         /* The GPU can not handle its semaphore value wrapping,
1279                          * so every billion or so execbuffers, we need to stall
1280                          * the GPU in order to reset the counters.
1281                          */
1282                         ret = i915_gpu_idle(dev, true);
1283                         if (ret)
1284                                 goto err;
1285
1286                         BUG_ON(ring->sync_seqno[i]);
1287                 }
1288         }
1289
1290         if (ring == &dev_priv->ring[RCS] &&
1291             mode != dev_priv->relative_constants_mode) {
1292                 ret = intel_ring_begin(ring, 4);
1293                 if (ret)
1294                                 goto err;
1295
1296                 intel_ring_emit(ring, MI_NOOP);
1297                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1298                 intel_ring_emit(ring, INSTPM);
1299                 intel_ring_emit(ring, mask << 16 | mode);
1300                 intel_ring_advance(ring);
1301
1302                 dev_priv->relative_constants_mode = mode;
1303         }
1304
1305         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1306                 ret = i915_reset_gen7_sol_offsets(dev, ring);
1307                 if (ret)
1308                         goto err;
1309         }
1310
1311         trace_i915_gem_ring_dispatch(ring, seqno);
1312
1313         exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1314         exec_len = args->batch_len;
1315         if (cliprects) {
1316                 for (i = 0; i < args->num_cliprects; i++) {
1317                         ret = i915_emit_box(dev, &cliprects[i],
1318                                             args->DR1, args->DR4);
1319                         if (ret)
1320                                 goto err;
1321
1322                         ret = ring->dispatch_execbuffer(ring,
1323                                                         exec_start, exec_len);
1324                         if (ret)
1325                                 goto err;
1326                 }
1327         } else {
1328                 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1329                 if (ret)
1330                         goto err;
1331         }
1332
1333         i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1334         i915_gem_execbuffer_retire_commands(dev, file, ring);
1335
1336 err:
1337         eb_destroy(eb);
1338         while (!list_empty(&objects)) {
1339                 struct drm_i915_gem_object *obj;
1340
1341                 obj = list_first_entry(&objects,
1342                                        struct drm_i915_gem_object,
1343                                        exec_list);
1344                 list_del_init(&obj->exec_list);
1345                 drm_gem_object_unreference(&obj->base);
1346         }
1347
1348         mutex_unlock(&dev->struct_mutex);
1349
1350 pre_mutex_err:
1351         kfree(cliprects);
1352         return ret;
1353 }
1354
1355 /*
1356  * Legacy execbuffer just creates an exec2 list from the original exec object
1357  * list array and passes it to the real function.
1358  */
1359 int
1360 i915_gem_execbuffer(struct drm_device *dev, void *data,
1361                     struct drm_file *file)
1362 {
1363         struct drm_i915_gem_execbuffer *args = data;
1364         struct drm_i915_gem_execbuffer2 exec2;
1365         struct drm_i915_gem_exec_object *exec_list = NULL;
1366         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1367         int ret, i;
1368
1369         if (args->buffer_count < 1) {
1370                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1371                 return -EINVAL;
1372         }
1373
1374         /* Copy in the exec list from userland */
1375         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1376         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1377         if (exec_list == NULL || exec2_list == NULL) {
1378                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1379                           args->buffer_count);
1380                 drm_free_large(exec_list);
1381                 drm_free_large(exec2_list);
1382                 return -ENOMEM;
1383         }
1384         ret = copy_from_user(exec_list,
1385                              (struct drm_i915_relocation_entry __user *)
1386                              (uintptr_t) args->buffers_ptr,
1387                              sizeof(*exec_list) * args->buffer_count);
1388         if (ret != 0) {
1389                 DRM_DEBUG("copy %d exec entries failed %d\n",
1390                           args->buffer_count, ret);
1391                 drm_free_large(exec_list);
1392                 drm_free_large(exec2_list);
1393                 return -EFAULT;
1394         }
1395
1396         for (i = 0; i < args->buffer_count; i++) {
1397                 exec2_list[i].handle = exec_list[i].handle;
1398                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1399                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1400                 exec2_list[i].alignment = exec_list[i].alignment;
1401                 exec2_list[i].offset = exec_list[i].offset;
1402                 if (INTEL_INFO(dev)->gen < 4)
1403                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1404                 else
1405                         exec2_list[i].flags = 0;
1406         }
1407
1408         exec2.buffers_ptr = args->buffers_ptr;
1409         exec2.buffer_count = args->buffer_count;
1410         exec2.batch_start_offset = args->batch_start_offset;
1411         exec2.batch_len = args->batch_len;
1412         exec2.DR1 = args->DR1;
1413         exec2.DR4 = args->DR4;
1414         exec2.num_cliprects = args->num_cliprects;
1415         exec2.cliprects_ptr = args->cliprects_ptr;
1416         exec2.flags = I915_EXEC_RENDER;
1417
1418         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1419         if (!ret) {
1420                 /* Copy the new buffer offsets back to the user's exec list. */
1421                 for (i = 0; i < args->buffer_count; i++)
1422                         exec_list[i].offset = exec2_list[i].offset;
1423                 /* ... and back out to userspace */
1424                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1425                                    (uintptr_t) args->buffers_ptr,
1426                                    exec_list,
1427                                    sizeof(*exec_list) * args->buffer_count);
1428                 if (ret) {
1429                         ret = -EFAULT;
1430                         DRM_DEBUG("failed to copy %d exec entries "
1431                                   "back to user (%d)\n",
1432                                   args->buffer_count, ret);
1433                 }
1434         }
1435
1436         drm_free_large(exec_list);
1437         drm_free_large(exec2_list);
1438         return ret;
1439 }
1440
1441 int
1442 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1443                      struct drm_file *file)
1444 {
1445         struct drm_i915_gem_execbuffer2 *args = data;
1446         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1447         int ret;
1448
1449         if (args->buffer_count < 1) {
1450                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1451                 return -EINVAL;
1452         }
1453
1454         exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1455                              GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1456         if (exec2_list == NULL)
1457                 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1458                                            args->buffer_count);
1459         if (exec2_list == NULL) {
1460                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1461                           args->buffer_count);
1462                 return -ENOMEM;
1463         }
1464         ret = copy_from_user(exec2_list,
1465                              (struct drm_i915_relocation_entry __user *)
1466                              (uintptr_t) args->buffers_ptr,
1467                              sizeof(*exec2_list) * args->buffer_count);
1468         if (ret != 0) {
1469                 DRM_DEBUG("copy %d exec entries failed %d\n",
1470                           args->buffer_count, ret);
1471                 drm_free_large(exec2_list);
1472                 return -EFAULT;
1473         }
1474
1475         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1476         if (!ret) {
1477                 /* Copy the new buffer offsets back to the user's exec list. */
1478                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1479                                    (uintptr_t) args->buffers_ptr,
1480                                    exec2_list,
1481                                    sizeof(*exec2_list) * args->buffer_count);
1482                 if (ret) {
1483                         ret = -EFAULT;
1484                         DRM_DEBUG("failed to copy %d exec entries "
1485                                   "back to user (%d)\n",
1486                                   args->buffer_count, ret);
1487                 }
1488         }
1489
1490         drm_free_large(exec2_list);
1491         return ret;
1492 }