2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
39 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
44 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
48 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
50 bool map_and_fenceable);
51 static void i915_gem_clear_fence_reg(struct drm_device *dev,
52 struct drm_i915_fence_reg *reg);
53 static int i915_gem_phys_pwrite(struct drm_device *dev,
54 struct drm_i915_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file);
57 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
59 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
60 struct shrink_control *sc);
62 /* some bookkeeping */
63 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
66 dev_priv->mm.object_count++;
67 dev_priv->mm.object_memory += size;
70 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
73 dev_priv->mm.object_count--;
74 dev_priv->mm.object_memory -= size;
78 i915_gem_wait_for_error(struct drm_device *dev)
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct completion *x = &dev_priv->error_completion;
85 if (!atomic_read(&dev_priv->mm.wedged))
88 ret = wait_for_completion_interruptible(x);
92 if (atomic_read(&dev_priv->mm.wedged)) {
93 /* GPU is hung, bump the completion count to account for
94 * the token we just consumed so that we never hit zero and
95 * end up waiting upon a subsequent completion event that
98 spin_lock_irqsave(&x->wait.lock, flags);
100 spin_unlock_irqrestore(&x->wait.lock, flags);
105 int i915_mutex_lock_interruptible(struct drm_device *dev)
109 ret = i915_gem_wait_for_error(dev);
113 ret = mutex_lock_interruptible(&dev->struct_mutex);
117 WARN_ON(i915_verify_lists(dev));
122 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
124 return obj->gtt_space && !obj->active && obj->pin_count == 0;
127 void i915_gem_do_init(struct drm_device *dev,
129 unsigned long mappable_end,
132 drm_i915_private_t *dev_priv = dev->dev_private;
134 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
136 dev_priv->mm.gtt_start = start;
137 dev_priv->mm.gtt_mappable_end = mappable_end;
138 dev_priv->mm.gtt_end = end;
139 dev_priv->mm.gtt_total = end - start;
140 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
142 /* Take over this portion of the GTT */
143 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
147 i915_gem_init_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_gem_init *args = data;
152 if (args->gtt_start >= args->gtt_end ||
153 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
156 mutex_lock(&dev->struct_mutex);
157 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
164 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
172 if (!(dev->driver->driver_features & DRIVER_GEM))
176 mutex_lock(&dev->struct_mutex);
177 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
178 pinned += obj->gtt_space->size;
179 mutex_unlock(&dev->struct_mutex);
181 args->aper_size = dev_priv->mm.gtt_total;
182 args->aper_available_size = args->aper_size -pinned;
188 i915_gem_create(struct drm_file *file,
189 struct drm_device *dev,
193 struct drm_i915_gem_object *obj;
197 size = roundup(size, PAGE_SIZE);
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
221 i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
232 int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
236 return drm_gem_handle_delete(file, handle);
240 * Creates a new mm object and returns a handle to it.
243 i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
246 struct drm_i915_gem_create *args = data;
247 return i915_gem_create(file, dev,
248 args->size, &args->handle);
251 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
253 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
255 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
256 obj->tiling_mode != I915_TILING_NONE;
260 slow_shmem_copy(struct page *dst_page,
262 struct page *src_page,
266 char *dst_vaddr, *src_vaddr;
268 dst_vaddr = kmap(dst_page);
269 src_vaddr = kmap(src_page);
271 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
278 slow_shmem_bit17_copy(struct page *gpu_page,
280 struct page *cpu_page,
285 char *gpu_vaddr, *cpu_vaddr;
287 /* Use the unswizzled path if this page isn't affected. */
288 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
290 return slow_shmem_copy(cpu_page, cpu_offset,
291 gpu_page, gpu_offset, length);
293 return slow_shmem_copy(gpu_page, gpu_offset,
294 cpu_page, cpu_offset, length);
297 gpu_vaddr = kmap(gpu_page);
298 cpu_vaddr = kmap(cpu_page);
300 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
301 * XORing with the other bits (A9 for Y, A9 and A10 for X)
304 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305 int this_length = min(cacheline_end - gpu_offset, length);
306 int swizzled_gpu_offset = gpu_offset ^ 64;
309 memcpy(cpu_vaddr + cpu_offset,
310 gpu_vaddr + swizzled_gpu_offset,
313 memcpy(gpu_vaddr + swizzled_gpu_offset,
314 cpu_vaddr + cpu_offset,
317 cpu_offset += this_length;
318 gpu_offset += this_length;
319 length -= this_length;
327 * This is the fast shmem pread path, which attempts to copy_from_user directly
328 * from the backing pages of the object to the user's address space. On a
329 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
332 i915_gem_shmem_pread_fast(struct drm_device *dev,
333 struct drm_i915_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file)
337 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
340 char __user *user_data;
341 int page_offset, page_length;
343 user_data = (char __user *) (uintptr_t) args->data_ptr;
346 offset = args->offset;
353 /* Operation in this page
355 * page_offset = offset within page
356 * page_length = bytes to copy for this page
358 page_offset = offset_in_page(offset);
359 page_length = remain;
360 if ((page_offset + remain) > PAGE_SIZE)
361 page_length = PAGE_SIZE - page_offset;
363 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
365 return PTR_ERR(page);
367 vaddr = kmap_atomic(page);
368 ret = __copy_to_user_inatomic(user_data,
371 kunmap_atomic(vaddr);
373 mark_page_accessed(page);
374 page_cache_release(page);
378 remain -= page_length;
379 user_data += page_length;
380 offset += page_length;
387 * This is the fallback shmem pread path, which allocates temporary storage
388 * in kernel space to copy_to_user into outside of the struct_mutex, so we
389 * can copy out of the object's backing pages while holding the struct mutex
390 * and not take page faults.
393 i915_gem_shmem_pread_slow(struct drm_device *dev,
394 struct drm_i915_gem_object *obj,
395 struct drm_i915_gem_pread *args,
396 struct drm_file *file)
398 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
399 struct mm_struct *mm = current->mm;
400 struct page **user_pages;
402 loff_t offset, pinned_pages, i;
403 loff_t first_data_page, last_data_page, num_pages;
404 int shmem_page_offset;
405 int data_page_index, data_page_offset;
408 uint64_t data_ptr = args->data_ptr;
409 int do_bit17_swizzling;
413 /* Pin the user pages containing the data. We can't fault while
414 * holding the struct mutex, yet we want to hold it while
415 * dereferencing the user data.
417 first_data_page = data_ptr / PAGE_SIZE;
418 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
419 num_pages = last_data_page - first_data_page + 1;
421 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
422 if (user_pages == NULL)
425 mutex_unlock(&dev->struct_mutex);
426 down_read(&mm->mmap_sem);
427 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
428 num_pages, 1, 0, user_pages, NULL);
429 up_read(&mm->mmap_sem);
430 mutex_lock(&dev->struct_mutex);
431 if (pinned_pages < num_pages) {
436 ret = i915_gem_object_set_cpu_read_domain_range(obj,
442 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
444 offset = args->offset;
449 /* Operation in this page
451 * shmem_page_offset = offset within page in shmem file
452 * data_page_index = page number in get_user_pages return
453 * data_page_offset = offset with data_page_index page.
454 * page_length = bytes to copy for this page
456 shmem_page_offset = offset_in_page(offset);
457 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
458 data_page_offset = offset_in_page(data_ptr);
460 page_length = remain;
461 if ((shmem_page_offset + page_length) > PAGE_SIZE)
462 page_length = PAGE_SIZE - shmem_page_offset;
463 if ((data_page_offset + page_length) > PAGE_SIZE)
464 page_length = PAGE_SIZE - data_page_offset;
466 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
472 if (do_bit17_swizzling) {
473 slow_shmem_bit17_copy(page,
475 user_pages[data_page_index],
480 slow_shmem_copy(user_pages[data_page_index],
487 mark_page_accessed(page);
488 page_cache_release(page);
490 remain -= page_length;
491 data_ptr += page_length;
492 offset += page_length;
496 for (i = 0; i < pinned_pages; i++) {
497 SetPageDirty(user_pages[i]);
498 mark_page_accessed(user_pages[i]);
499 page_cache_release(user_pages[i]);
501 drm_free_large(user_pages);
507 * Reads data from the object referenced by handle.
509 * On error, the contents of *data are undefined.
512 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file)
515 struct drm_i915_gem_pread *args = data;
516 struct drm_i915_gem_object *obj;
522 if (!access_ok(VERIFY_WRITE,
523 (char __user *)(uintptr_t)args->data_ptr,
527 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
532 ret = i915_mutex_lock_interruptible(dev);
536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
537 if (&obj->base == NULL) {
542 /* Bounds check source. */
543 if (args->offset > obj->base.size ||
544 args->size > obj->base.size - args->offset) {
549 trace_i915_gem_object_pread(obj, args->offset, args->size);
551 ret = i915_gem_object_set_cpu_read_domain_range(obj,
558 if (!i915_gem_object_needs_bit17_swizzle(obj))
559 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
561 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
564 drm_gem_object_unreference(&obj->base);
566 mutex_unlock(&dev->struct_mutex);
570 /* This is the fast write path which cannot handle
571 * page faults in the source data
575 fast_user_write(struct io_mapping *mapping,
576 loff_t page_base, int page_offset,
577 char __user *user_data,
581 unsigned long unwritten;
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
586 io_mapping_unmap_atomic(vaddr_atomic);
590 /* Here's the write path which can sleep for
595 slow_kernel_write(struct io_mapping *mapping,
596 loff_t gtt_base, int gtt_offset,
597 struct page *user_page, int user_offset,
600 char __iomem *dst_vaddr;
603 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
604 src_vaddr = kmap(user_page);
606 memcpy_toio(dst_vaddr + gtt_offset,
607 src_vaddr + user_offset,
611 io_mapping_unmap(dst_vaddr);
615 * This is the fast pwrite path, where we copy the data directly from the
616 * user into the GTT, uncached.
619 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
620 struct drm_i915_gem_object *obj,
621 struct drm_i915_gem_pwrite *args,
622 struct drm_file *file)
624 drm_i915_private_t *dev_priv = dev->dev_private;
626 loff_t offset, page_base;
627 char __user *user_data;
628 int page_offset, page_length;
630 user_data = (char __user *) (uintptr_t) args->data_ptr;
633 offset = obj->gtt_offset + args->offset;
636 /* Operation in this page
638 * page_base = page offset within aperture
639 * page_offset = offset within page
640 * page_length = bytes to copy for this page
642 page_base = offset & PAGE_MASK;
643 page_offset = offset_in_page(offset);
644 page_length = remain;
645 if ((page_offset + remain) > PAGE_SIZE)
646 page_length = PAGE_SIZE - page_offset;
648 /* If we get a fault while copying data, then (presumably) our
649 * source page isn't available. Return the error and we'll
650 * retry in the slow path.
652 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
653 page_offset, user_data, page_length))
656 remain -= page_length;
657 user_data += page_length;
658 offset += page_length;
665 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
666 * the memory and maps it using kmap_atomic for copying.
668 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
669 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
672 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
673 struct drm_i915_gem_object *obj,
674 struct drm_i915_gem_pwrite *args,
675 struct drm_file *file)
677 drm_i915_private_t *dev_priv = dev->dev_private;
679 loff_t gtt_page_base, offset;
680 loff_t first_data_page, last_data_page, num_pages;
681 loff_t pinned_pages, i;
682 struct page **user_pages;
683 struct mm_struct *mm = current->mm;
684 int gtt_page_offset, data_page_offset, data_page_index, page_length;
686 uint64_t data_ptr = args->data_ptr;
690 /* Pin the user pages containing the data. We can't fault while
691 * holding the struct mutex, and all of the pwrite implementations
692 * want to hold it while dereferencing the user data.
694 first_data_page = data_ptr / PAGE_SIZE;
695 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
696 num_pages = last_data_page - first_data_page + 1;
698 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
699 if (user_pages == NULL)
702 mutex_unlock(&dev->struct_mutex);
703 down_read(&mm->mmap_sem);
704 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
705 num_pages, 0, 0, user_pages, NULL);
706 up_read(&mm->mmap_sem);
707 mutex_lock(&dev->struct_mutex);
708 if (pinned_pages < num_pages) {
710 goto out_unpin_pages;
713 ret = i915_gem_object_set_to_gtt_domain(obj, true);
715 goto out_unpin_pages;
717 ret = i915_gem_object_put_fence(obj);
719 goto out_unpin_pages;
721 offset = obj->gtt_offset + args->offset;
724 /* Operation in this page
726 * gtt_page_base = page offset within aperture
727 * gtt_page_offset = offset within page in aperture
728 * data_page_index = page number in get_user_pages return
729 * data_page_offset = offset with data_page_index page.
730 * page_length = bytes to copy for this page
732 gtt_page_base = offset & PAGE_MASK;
733 gtt_page_offset = offset_in_page(offset);
734 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
735 data_page_offset = offset_in_page(data_ptr);
737 page_length = remain;
738 if ((gtt_page_offset + page_length) > PAGE_SIZE)
739 page_length = PAGE_SIZE - gtt_page_offset;
740 if ((data_page_offset + page_length) > PAGE_SIZE)
741 page_length = PAGE_SIZE - data_page_offset;
743 slow_kernel_write(dev_priv->mm.gtt_mapping,
744 gtt_page_base, gtt_page_offset,
745 user_pages[data_page_index],
749 remain -= page_length;
750 offset += page_length;
751 data_ptr += page_length;
755 for (i = 0; i < pinned_pages; i++)
756 page_cache_release(user_pages[i]);
757 drm_free_large(user_pages);
763 * This is the fast shmem pwrite path, which attempts to directly
764 * copy_from_user into the kmapped pages backing the object.
767 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
768 struct drm_i915_gem_object *obj,
769 struct drm_i915_gem_pwrite *args,
770 struct drm_file *file)
772 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
775 char __user *user_data;
776 int page_offset, page_length;
778 user_data = (char __user *) (uintptr_t) args->data_ptr;
781 offset = args->offset;
789 /* Operation in this page
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
794 page_offset = offset_in_page(offset);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
799 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
801 return PTR_ERR(page);
803 vaddr = kmap_atomic(page, KM_USER0);
804 ret = __copy_from_user_inatomic(vaddr + page_offset,
807 kunmap_atomic(vaddr, KM_USER0);
809 set_page_dirty(page);
810 mark_page_accessed(page);
811 page_cache_release(page);
813 /* If we get a fault while copying data, then (presumably) our
814 * source page isn't available. Return the error and we'll
815 * retry in the slow path.
820 remain -= page_length;
821 user_data += page_length;
822 offset += page_length;
829 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
830 * the memory and maps it using kmap_atomic for copying.
832 * This avoids taking mmap_sem for faulting on the user's address while the
833 * struct_mutex is held.
836 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
837 struct drm_i915_gem_object *obj,
838 struct drm_i915_gem_pwrite *args,
839 struct drm_file *file)
841 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
842 struct mm_struct *mm = current->mm;
843 struct page **user_pages;
845 loff_t offset, pinned_pages, i;
846 loff_t first_data_page, last_data_page, num_pages;
847 int shmem_page_offset;
848 int data_page_index, data_page_offset;
851 uint64_t data_ptr = args->data_ptr;
852 int do_bit17_swizzling;
856 /* Pin the user pages containing the data. We can't fault while
857 * holding the struct mutex, and all of the pwrite implementations
858 * want to hold it while dereferencing the user data.
860 first_data_page = data_ptr / PAGE_SIZE;
861 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
862 num_pages = last_data_page - first_data_page + 1;
864 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
865 if (user_pages == NULL)
868 mutex_unlock(&dev->struct_mutex);
869 down_read(&mm->mmap_sem);
870 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
871 num_pages, 0, 0, user_pages, NULL);
872 up_read(&mm->mmap_sem);
873 mutex_lock(&dev->struct_mutex);
874 if (pinned_pages < num_pages) {
879 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
883 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
885 offset = args->offset;
891 /* Operation in this page
893 * shmem_page_offset = offset within page in shmem file
894 * data_page_index = page number in get_user_pages return
895 * data_page_offset = offset with data_page_index page.
896 * page_length = bytes to copy for this page
898 shmem_page_offset = offset_in_page(offset);
899 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
900 data_page_offset = offset_in_page(data_ptr);
902 page_length = remain;
903 if ((shmem_page_offset + page_length) > PAGE_SIZE)
904 page_length = PAGE_SIZE - shmem_page_offset;
905 if ((data_page_offset + page_length) > PAGE_SIZE)
906 page_length = PAGE_SIZE - data_page_offset;
908 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
914 if (do_bit17_swizzling) {
915 slow_shmem_bit17_copy(page,
917 user_pages[data_page_index],
922 slow_shmem_copy(page,
924 user_pages[data_page_index],
929 set_page_dirty(page);
930 mark_page_accessed(page);
931 page_cache_release(page);
933 remain -= page_length;
934 data_ptr += page_length;
935 offset += page_length;
939 for (i = 0; i < pinned_pages; i++)
940 page_cache_release(user_pages[i]);
941 drm_free_large(user_pages);
947 * Writes data to the object referenced by handle.
949 * On error, the contents of the buffer that were to be modified are undefined.
952 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
953 struct drm_file *file)
955 struct drm_i915_gem_pwrite *args = data;
956 struct drm_i915_gem_object *obj;
962 if (!access_ok(VERIFY_READ,
963 (char __user *)(uintptr_t)args->data_ptr,
967 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
972 ret = i915_mutex_lock_interruptible(dev);
976 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
977 if (&obj->base == NULL) {
982 /* Bounds check destination. */
983 if (args->offset > obj->base.size ||
984 args->size > obj->base.size - args->offset) {
989 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
991 /* We can only do the GTT pwrite on untiled buffers, as otherwise
992 * it would end up going through the fenced access, and we'll get
993 * different detiling behavior between reading and writing.
994 * pread/pwrite currently are reading and writing from the CPU
995 * perspective, requiring manual detiling by the client.
998 ret = i915_gem_phys_pwrite(dev, obj, args, file);
999 else if (obj->gtt_space &&
1000 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1001 ret = i915_gem_object_pin(obj, 0, true);
1005 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1009 ret = i915_gem_object_put_fence(obj);
1013 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1015 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1018 i915_gem_object_unpin(obj);
1020 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1025 if (!i915_gem_object_needs_bit17_swizzle(obj))
1026 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1028 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1032 drm_gem_object_unreference(&obj->base);
1034 mutex_unlock(&dev->struct_mutex);
1039 * Called when user space prepares to use an object with the CPU, either
1040 * through the mmap ioctl's mapping or a GTT mapping.
1043 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1044 struct drm_file *file)
1046 struct drm_i915_gem_set_domain *args = data;
1047 struct drm_i915_gem_object *obj;
1048 uint32_t read_domains = args->read_domains;
1049 uint32_t write_domain = args->write_domain;
1052 if (!(dev->driver->driver_features & DRIVER_GEM))
1055 /* Only handle setting domains to types used by the CPU. */
1056 if (write_domain & I915_GEM_GPU_DOMAINS)
1059 if (read_domains & I915_GEM_GPU_DOMAINS)
1062 /* Having something in the write domain implies it's in the read
1063 * domain, and only that read domain. Enforce that in the request.
1065 if (write_domain != 0 && read_domains != write_domain)
1068 ret = i915_mutex_lock_interruptible(dev);
1072 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1073 if (&obj->base == NULL) {
1078 if (read_domains & I915_GEM_DOMAIN_GTT) {
1079 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1081 /* Silently promote "you're not bound, there was nothing to do"
1082 * to success, since the client was just asking us to
1083 * make sure everything was done.
1088 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1091 drm_gem_object_unreference(&obj->base);
1093 mutex_unlock(&dev->struct_mutex);
1098 * Called when user space has done writes to this buffer
1101 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1102 struct drm_file *file)
1104 struct drm_i915_gem_sw_finish *args = data;
1105 struct drm_i915_gem_object *obj;
1108 if (!(dev->driver->driver_features & DRIVER_GEM))
1111 ret = i915_mutex_lock_interruptible(dev);
1115 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1116 if (&obj->base == NULL) {
1121 /* Pinned buffers may be scanout, so flush the cache */
1123 i915_gem_object_flush_cpu_write_domain(obj);
1125 drm_gem_object_unreference(&obj->base);
1127 mutex_unlock(&dev->struct_mutex);
1132 * Maps the contents of an object, returning the address it is mapped
1135 * While the mapping holds a reference on the contents of the object, it doesn't
1136 * imply a ref on the object itself.
1139 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1140 struct drm_file *file)
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 struct drm_i915_gem_mmap *args = data;
1144 struct drm_gem_object *obj;
1147 if (!(dev->driver->driver_features & DRIVER_GEM))
1150 obj = drm_gem_object_lookup(dev, file, args->handle);
1154 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1155 drm_gem_object_unreference_unlocked(obj);
1159 down_write(¤t->mm->mmap_sem);
1160 addr = do_mmap(obj->filp, 0, args->size,
1161 PROT_READ | PROT_WRITE, MAP_SHARED,
1163 up_write(¤t->mm->mmap_sem);
1164 drm_gem_object_unreference_unlocked(obj);
1165 if (IS_ERR((void *)addr))
1168 args->addr_ptr = (uint64_t) addr;
1174 * i915_gem_fault - fault a page into the GTT
1175 * vma: VMA in question
1178 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1179 * from userspace. The fault handler takes care of binding the object to
1180 * the GTT (if needed), allocating and programming a fence register (again,
1181 * only if needed based on whether the old reg is still valid or the object
1182 * is tiled) and inserting a new PTE into the faulting process.
1184 * Note that the faulting process may involve evicting existing objects
1185 * from the GTT and/or fence registers to make room. So performance may
1186 * suffer if the GTT working set is large or there are few fence registers
1189 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1191 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1192 struct drm_device *dev = obj->base.dev;
1193 drm_i915_private_t *dev_priv = dev->dev_private;
1194 pgoff_t page_offset;
1197 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1199 /* We don't use vmf->pgoff since that has the fake offset */
1200 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1203 ret = i915_mutex_lock_interruptible(dev);
1207 trace_i915_gem_object_fault(obj, page_offset, true, write);
1209 /* Now bind it into the GTT if needed */
1210 if (!obj->map_and_fenceable) {
1211 ret = i915_gem_object_unbind(obj);
1215 if (!obj->gtt_space) {
1216 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1220 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1225 if (obj->tiling_mode == I915_TILING_NONE)
1226 ret = i915_gem_object_put_fence(obj);
1228 ret = i915_gem_object_get_fence(obj, NULL);
1232 if (i915_gem_object_is_inactive(obj))
1233 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1235 obj->fault_mappable = true;
1237 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1240 /* Finally, remap it using the new GTT offset */
1241 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1243 mutex_unlock(&dev->struct_mutex);
1248 /* Give the error handler a chance to run and move the
1249 * objects off the GPU active list. Next time we service the
1250 * fault, we should be able to transition the page into the
1251 * GTT without touching the GPU (and so avoid further
1252 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1253 * with coherency, just lost writes.
1259 return VM_FAULT_NOPAGE;
1261 return VM_FAULT_OOM;
1263 return VM_FAULT_SIGBUS;
1268 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1269 * @obj: obj in question
1271 * GEM memory mapping works by handing back to userspace a fake mmap offset
1272 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1273 * up the object based on the offset and sets up the various memory mapping
1276 * This routine allocates and attaches a fake offset for @obj.
1279 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1281 struct drm_device *dev = obj->base.dev;
1282 struct drm_gem_mm *mm = dev->mm_private;
1283 struct drm_map_list *list;
1284 struct drm_local_map *map;
1287 /* Set the object up for mmap'ing */
1288 list = &obj->base.map_list;
1289 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1294 map->type = _DRM_GEM;
1295 map->size = obj->base.size;
1298 /* Get a DRM GEM mmap offset allocated... */
1299 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1300 obj->base.size / PAGE_SIZE,
1302 if (!list->file_offset_node) {
1303 DRM_ERROR("failed to allocate offset for bo %d\n",
1309 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1310 obj->base.size / PAGE_SIZE,
1312 if (!list->file_offset_node) {
1317 list->hash.key = list->file_offset_node->start;
1318 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1320 DRM_ERROR("failed to add to map hash\n");
1327 drm_mm_put_block(list->file_offset_node);
1336 * i915_gem_release_mmap - remove physical page mappings
1337 * @obj: obj in question
1339 * Preserve the reservation of the mmapping with the DRM core code, but
1340 * relinquish ownership of the pages back to the system.
1342 * It is vital that we remove the page mapping if we have mapped a tiled
1343 * object through the GTT and then lose the fence register due to
1344 * resource pressure. Similarly if the object has been moved out of the
1345 * aperture, than pages mapped into userspace must be revoked. Removing the
1346 * mapping will then trigger a page fault on the next user access, allowing
1347 * fixup by i915_gem_fault().
1350 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1352 if (!obj->fault_mappable)
1355 if (obj->base.dev->dev_mapping)
1356 unmap_mapping_range(obj->base.dev->dev_mapping,
1357 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1360 obj->fault_mappable = false;
1364 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1366 struct drm_device *dev = obj->base.dev;
1367 struct drm_gem_mm *mm = dev->mm_private;
1368 struct drm_map_list *list = &obj->base.map_list;
1370 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1371 drm_mm_put_block(list->file_offset_node);
1377 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1379 struct drm_device *dev = obj->base.dev;
1382 if (INTEL_INFO(dev)->gen >= 4 ||
1383 obj->tiling_mode == I915_TILING_NONE)
1384 return obj->base.size;
1386 /* Previous chips need a power-of-two fence region when tiling */
1387 if (INTEL_INFO(dev)->gen == 3)
1392 while (size < obj->base.size)
1399 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1400 * @obj: object to check
1402 * Return the required GTT alignment for an object, taking into account
1403 * potential fence register mapping.
1406 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1408 struct drm_device *dev = obj->base.dev;
1411 * Minimum alignment is 4k (GTT page size), but might be greater
1412 * if a fence register is needed for the object.
1414 if (INTEL_INFO(dev)->gen >= 4 ||
1415 obj->tiling_mode == I915_TILING_NONE)
1419 * Previous chips need to be aligned to the size of the smallest
1420 * fence register that can contain the object.
1422 return i915_gem_get_gtt_size(obj);
1426 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1428 * @obj: object to check
1430 * Return the required GTT alignment for an object, only taking into account
1431 * unfenced tiled surface requirements.
1434 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1436 struct drm_device *dev = obj->base.dev;
1440 * Minimum alignment is 4k (GTT page size) for sane hw.
1442 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1443 obj->tiling_mode == I915_TILING_NONE)
1447 * Older chips need unfenced tiled buffers to be aligned to the left
1448 * edge of an even tile row (where tile rows are counted as if the bo is
1449 * placed in a fenced gtt region).
1453 else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1458 return tile_height * obj->stride * 2;
1462 i915_gem_mmap_gtt(struct drm_file *file,
1463 struct drm_device *dev,
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468 struct drm_i915_gem_object *obj;
1471 if (!(dev->driver->driver_features & DRIVER_GEM))
1474 ret = i915_mutex_lock_interruptible(dev);
1478 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1479 if (&obj->base == NULL) {
1484 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1489 if (obj->madv != I915_MADV_WILLNEED) {
1490 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1495 if (!obj->base.map_list.map) {
1496 ret = i915_gem_create_mmap_offset(obj);
1501 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1504 drm_gem_object_unreference(&obj->base);
1506 mutex_unlock(&dev->struct_mutex);
1511 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1513 * @data: GTT mapping ioctl data
1514 * @file: GEM object info
1516 * Simply returns the fake offset to userspace so it can mmap it.
1517 * The mmap call will end up in drm_gem_mmap(), which will set things
1518 * up so we can get faults in the handler above.
1520 * The fault handler will take care of binding the object into the GTT
1521 * (since it may have been evicted to make room for something), allocating
1522 * a fence register, and mapping the appropriate aperture address into
1526 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1527 struct drm_file *file)
1529 struct drm_i915_gem_mmap_gtt *args = data;
1531 if (!(dev->driver->driver_features & DRIVER_GEM))
1534 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1539 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1543 struct address_space *mapping;
1544 struct inode *inode;
1547 /* Get the list of pages out of our struct file. They'll be pinned
1548 * at this point until we release them.
1550 page_count = obj->base.size / PAGE_SIZE;
1551 BUG_ON(obj->pages != NULL);
1552 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1553 if (obj->pages == NULL)
1556 inode = obj->base.filp->f_path.dentry->d_inode;
1557 mapping = inode->i_mapping;
1558 gfpmask |= mapping_gfp_mask(mapping);
1560 for (i = 0; i < page_count; i++) {
1561 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1565 obj->pages[i] = page;
1568 if (obj->tiling_mode != I915_TILING_NONE)
1569 i915_gem_object_do_bit_17_swizzle(obj);
1575 page_cache_release(obj->pages[i]);
1577 drm_free_large(obj->pages);
1579 return PTR_ERR(page);
1583 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1585 int page_count = obj->base.size / PAGE_SIZE;
1588 BUG_ON(obj->madv == __I915_MADV_PURGED);
1590 if (obj->tiling_mode != I915_TILING_NONE)
1591 i915_gem_object_save_bit_17_swizzle(obj);
1593 if (obj->madv == I915_MADV_DONTNEED)
1596 for (i = 0; i < page_count; i++) {
1598 set_page_dirty(obj->pages[i]);
1600 if (obj->madv == I915_MADV_WILLNEED)
1601 mark_page_accessed(obj->pages[i]);
1603 page_cache_release(obj->pages[i]);
1607 drm_free_large(obj->pages);
1612 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1613 struct intel_ring_buffer *ring,
1616 struct drm_device *dev = obj->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1619 BUG_ON(ring == NULL);
1622 /* Add a reference if we're newly entering the active list. */
1624 drm_gem_object_reference(&obj->base);
1628 /* Move from whatever list we were on to the tail of execution. */
1629 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1630 list_move_tail(&obj->ring_list, &ring->active_list);
1632 obj->last_rendering_seqno = seqno;
1633 if (obj->fenced_gpu_access) {
1634 struct drm_i915_fence_reg *reg;
1636 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1638 obj->last_fenced_seqno = seqno;
1639 obj->last_fenced_ring = ring;
1641 reg = &dev_priv->fence_regs[obj->fence_reg];
1642 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1647 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1649 list_del_init(&obj->ring_list);
1650 obj->last_rendering_seqno = 0;
1654 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1656 struct drm_device *dev = obj->base.dev;
1657 drm_i915_private_t *dev_priv = dev->dev_private;
1659 BUG_ON(!obj->active);
1660 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1662 i915_gem_object_move_off_active(obj);
1666 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1668 struct drm_device *dev = obj->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1671 if (obj->pin_count != 0)
1672 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1674 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1676 BUG_ON(!list_empty(&obj->gpu_write_list));
1677 BUG_ON(!obj->active);
1680 i915_gem_object_move_off_active(obj);
1681 obj->fenced_gpu_access = false;
1684 obj->pending_gpu_write = false;
1685 drm_gem_object_unreference(&obj->base);
1687 WARN_ON(i915_verify_lists(dev));
1690 /* Immediately discard the backing storage */
1692 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1694 struct inode *inode;
1696 /* Our goal here is to return as much of the memory as
1697 * is possible back to the system as we are called from OOM.
1698 * To do this we must instruct the shmfs to drop all of its
1699 * backing pages, *now*.
1701 inode = obj->base.filp->f_path.dentry->d_inode;
1702 shmem_truncate_range(inode, 0, (loff_t)-1);
1704 obj->madv = __I915_MADV_PURGED;
1708 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1710 return obj->madv == I915_MADV_DONTNEED;
1714 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1715 uint32_t flush_domains)
1717 struct drm_i915_gem_object *obj, *next;
1719 list_for_each_entry_safe(obj, next,
1720 &ring->gpu_write_list,
1722 if (obj->base.write_domain & flush_domains) {
1723 uint32_t old_write_domain = obj->base.write_domain;
1725 obj->base.write_domain = 0;
1726 list_del_init(&obj->gpu_write_list);
1727 i915_gem_object_move_to_active(obj, ring,
1728 i915_gem_next_request_seqno(ring));
1730 trace_i915_gem_object_change_domain(obj,
1731 obj->base.read_domains,
1738 i915_add_request(struct intel_ring_buffer *ring,
1739 struct drm_file *file,
1740 struct drm_i915_gem_request *request)
1742 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1747 BUG_ON(request == NULL);
1749 ret = ring->add_request(ring, &seqno);
1753 trace_i915_gem_request_add(ring, seqno);
1755 request->seqno = seqno;
1756 request->ring = ring;
1757 request->emitted_jiffies = jiffies;
1758 was_empty = list_empty(&ring->request_list);
1759 list_add_tail(&request->list, &ring->request_list);
1762 struct drm_i915_file_private *file_priv = file->driver_priv;
1764 spin_lock(&file_priv->mm.lock);
1765 request->file_priv = file_priv;
1766 list_add_tail(&request->client_list,
1767 &file_priv->mm.request_list);
1768 spin_unlock(&file_priv->mm.lock);
1771 ring->outstanding_lazy_request = false;
1773 if (!dev_priv->mm.suspended) {
1774 mod_timer(&dev_priv->hangcheck_timer,
1775 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1777 queue_delayed_work(dev_priv->wq,
1778 &dev_priv->mm.retire_work, HZ);
1784 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1786 struct drm_i915_file_private *file_priv = request->file_priv;
1791 spin_lock(&file_priv->mm.lock);
1792 if (request->file_priv) {
1793 list_del(&request->client_list);
1794 request->file_priv = NULL;
1796 spin_unlock(&file_priv->mm.lock);
1799 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1800 struct intel_ring_buffer *ring)
1802 while (!list_empty(&ring->request_list)) {
1803 struct drm_i915_gem_request *request;
1805 request = list_first_entry(&ring->request_list,
1806 struct drm_i915_gem_request,
1809 list_del(&request->list);
1810 i915_gem_request_remove_from_client(request);
1814 while (!list_empty(&ring->active_list)) {
1815 struct drm_i915_gem_object *obj;
1817 obj = list_first_entry(&ring->active_list,
1818 struct drm_i915_gem_object,
1821 obj->base.write_domain = 0;
1822 list_del_init(&obj->gpu_write_list);
1823 i915_gem_object_move_to_inactive(obj);
1827 static void i915_gem_reset_fences(struct drm_device *dev)
1829 struct drm_i915_private *dev_priv = dev->dev_private;
1832 for (i = 0; i < 16; i++) {
1833 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1834 struct drm_i915_gem_object *obj = reg->obj;
1839 if (obj->tiling_mode)
1840 i915_gem_release_mmap(obj);
1842 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1843 reg->obj->fenced_gpu_access = false;
1844 reg->obj->last_fenced_seqno = 0;
1845 reg->obj->last_fenced_ring = NULL;
1846 i915_gem_clear_fence_reg(dev, reg);
1850 void i915_gem_reset(struct drm_device *dev)
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct drm_i915_gem_object *obj;
1856 for (i = 0; i < I915_NUM_RINGS; i++)
1857 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1859 /* Remove anything from the flushing lists. The GPU cache is likely
1860 * to be lost on reset along with the data, so simply move the
1861 * lost bo to the inactive list.
1863 while (!list_empty(&dev_priv->mm.flushing_list)) {
1864 obj= list_first_entry(&dev_priv->mm.flushing_list,
1865 struct drm_i915_gem_object,
1868 obj->base.write_domain = 0;
1869 list_del_init(&obj->gpu_write_list);
1870 i915_gem_object_move_to_inactive(obj);
1873 /* Move everything out of the GPU domains to ensure we do any
1874 * necessary invalidation upon reuse.
1876 list_for_each_entry(obj,
1877 &dev_priv->mm.inactive_list,
1880 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1883 /* The fence registers are invalidated so clear them out */
1884 i915_gem_reset_fences(dev);
1888 * This function clears the request list as sequence numbers are passed.
1891 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1896 if (list_empty(&ring->request_list))
1899 WARN_ON(i915_verify_lists(ring->dev));
1901 seqno = ring->get_seqno(ring);
1903 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1904 if (seqno >= ring->sync_seqno[i])
1905 ring->sync_seqno[i] = 0;
1907 while (!list_empty(&ring->request_list)) {
1908 struct drm_i915_gem_request *request;
1910 request = list_first_entry(&ring->request_list,
1911 struct drm_i915_gem_request,
1914 if (!i915_seqno_passed(seqno, request->seqno))
1917 trace_i915_gem_request_retire(ring, request->seqno);
1919 list_del(&request->list);
1920 i915_gem_request_remove_from_client(request);
1924 /* Move any buffers on the active list that are no longer referenced
1925 * by the ringbuffer to the flushing/inactive lists as appropriate.
1927 while (!list_empty(&ring->active_list)) {
1928 struct drm_i915_gem_object *obj;
1930 obj= list_first_entry(&ring->active_list,
1931 struct drm_i915_gem_object,
1934 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1937 if (obj->base.write_domain != 0)
1938 i915_gem_object_move_to_flushing(obj);
1940 i915_gem_object_move_to_inactive(obj);
1943 if (unlikely(ring->trace_irq_seqno &&
1944 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1945 ring->irq_put(ring);
1946 ring->trace_irq_seqno = 0;
1949 WARN_ON(i915_verify_lists(ring->dev));
1953 i915_gem_retire_requests(struct drm_device *dev)
1955 drm_i915_private_t *dev_priv = dev->dev_private;
1958 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1959 struct drm_i915_gem_object *obj, *next;
1961 /* We must be careful that during unbind() we do not
1962 * accidentally infinitely recurse into retire requests.
1964 * retire -> free -> unbind -> wait -> retire_ring
1966 list_for_each_entry_safe(obj, next,
1967 &dev_priv->mm.deferred_free_list,
1969 i915_gem_free_object_tail(obj);
1972 for (i = 0; i < I915_NUM_RINGS; i++)
1973 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1977 i915_gem_retire_work_handler(struct work_struct *work)
1979 drm_i915_private_t *dev_priv;
1980 struct drm_device *dev;
1984 dev_priv = container_of(work, drm_i915_private_t,
1985 mm.retire_work.work);
1986 dev = dev_priv->dev;
1988 /* Come back later if the device is busy... */
1989 if (!mutex_trylock(&dev->struct_mutex)) {
1990 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1994 i915_gem_retire_requests(dev);
1996 /* Send a periodic flush down the ring so we don't hold onto GEM
1997 * objects indefinitely.
2000 for (i = 0; i < I915_NUM_RINGS; i++) {
2001 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2003 if (!list_empty(&ring->gpu_write_list)) {
2004 struct drm_i915_gem_request *request;
2007 ret = i915_gem_flush_ring(ring,
2008 0, I915_GEM_GPU_DOMAINS);
2009 request = kzalloc(sizeof(*request), GFP_KERNEL);
2010 if (ret || request == NULL ||
2011 i915_add_request(ring, NULL, request))
2015 idle &= list_empty(&ring->request_list);
2018 if (!dev_priv->mm.suspended && !idle)
2019 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2021 mutex_unlock(&dev->struct_mutex);
2025 * Waits for a sequence number to be signaled, and cleans up the
2026 * request and object lists appropriately for that event.
2029 i915_wait_request(struct intel_ring_buffer *ring,
2032 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2038 if (atomic_read(&dev_priv->mm.wedged)) {
2039 struct completion *x = &dev_priv->error_completion;
2040 bool recovery_complete;
2041 unsigned long flags;
2043 /* Give the error handler a chance to run. */
2044 spin_lock_irqsave(&x->wait.lock, flags);
2045 recovery_complete = x->done > 0;
2046 spin_unlock_irqrestore(&x->wait.lock, flags);
2048 return recovery_complete ? -EIO : -EAGAIN;
2051 if (seqno == ring->outstanding_lazy_request) {
2052 struct drm_i915_gem_request *request;
2054 request = kzalloc(sizeof(*request), GFP_KERNEL);
2055 if (request == NULL)
2058 ret = i915_add_request(ring, NULL, request);
2064 seqno = request->seqno;
2067 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2068 if (HAS_PCH_SPLIT(ring->dev))
2069 ier = I915_READ(DEIER) | I915_READ(GTIER);
2071 ier = I915_READ(IER);
2073 DRM_ERROR("something (likely vbetool) disabled "
2074 "interrupts, re-enabling\n");
2075 ring->dev->driver->irq_preinstall(ring->dev);
2076 ring->dev->driver->irq_postinstall(ring->dev);
2079 trace_i915_gem_request_wait_begin(ring, seqno);
2081 ring->waiting_seqno = seqno;
2082 if (ring->irq_get(ring)) {
2083 if (dev_priv->mm.interruptible)
2084 ret = wait_event_interruptible(ring->irq_queue,
2085 i915_seqno_passed(ring->get_seqno(ring), seqno)
2086 || atomic_read(&dev_priv->mm.wedged));
2088 wait_event(ring->irq_queue,
2089 i915_seqno_passed(ring->get_seqno(ring), seqno)
2090 || atomic_read(&dev_priv->mm.wedged));
2092 ring->irq_put(ring);
2093 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2095 atomic_read(&dev_priv->mm.wedged), 3000))
2097 ring->waiting_seqno = 0;
2099 trace_i915_gem_request_wait_end(ring, seqno);
2101 if (atomic_read(&dev_priv->mm.wedged))
2104 if (ret && ret != -ERESTARTSYS)
2105 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2106 __func__, ret, seqno, ring->get_seqno(ring),
2107 dev_priv->next_seqno);
2109 /* Directly dispatch request retiring. While we have the work queue
2110 * to handle this, the waiter on a request often wants an associated
2111 * buffer to have made it to the inactive list, and we would need
2112 * a separate wait queue to handle that.
2115 i915_gem_retire_requests_ring(ring);
2121 * Ensures that all rendering to the object has completed and the object is
2122 * safe to unbind from the GTT or access from the CPU.
2125 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2129 /* This function only exists to support waiting for existing rendering,
2130 * not for emitting required flushes.
2132 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2134 /* If there is rendering queued on the buffer being evicted, wait for
2138 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2147 * Unbinds an object from the GTT aperture.
2150 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2154 if (obj->gtt_space == NULL)
2157 if (obj->pin_count != 0) {
2158 DRM_ERROR("Attempting to unbind pinned buffer\n");
2162 /* blow away mappings if mapped through GTT */
2163 i915_gem_release_mmap(obj);
2165 /* Move the object to the CPU domain to ensure that
2166 * any possible CPU writes while it's not in the GTT
2167 * are flushed when we go to remap it. This will
2168 * also ensure that all pending GPU writes are finished
2171 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2172 if (ret == -ERESTARTSYS)
2174 /* Continue on if we fail due to EIO, the GPU is hung so we
2175 * should be safe and we need to cleanup or else we might
2176 * cause memory corruption through use-after-free.
2179 i915_gem_clflush_object(obj);
2180 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2183 /* release the fence reg _after_ flushing */
2184 ret = i915_gem_object_put_fence(obj);
2185 if (ret == -ERESTARTSYS)
2188 trace_i915_gem_object_unbind(obj);
2190 i915_gem_gtt_unbind_object(obj);
2191 i915_gem_object_put_pages_gtt(obj);
2193 list_del_init(&obj->gtt_list);
2194 list_del_init(&obj->mm_list);
2195 /* Avoid an unnecessary call to unbind on rebind. */
2196 obj->map_and_fenceable = true;
2198 drm_mm_put_block(obj->gtt_space);
2199 obj->gtt_space = NULL;
2200 obj->gtt_offset = 0;
2202 if (i915_gem_object_is_purgeable(obj))
2203 i915_gem_object_truncate(obj);
2209 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2210 uint32_t invalidate_domains,
2211 uint32_t flush_domains)
2215 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2218 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2220 ret = ring->flush(ring, invalidate_domains, flush_domains);
2224 if (flush_domains & I915_GEM_GPU_DOMAINS)
2225 i915_gem_process_flushing_list(ring, flush_domains);
2230 static int i915_ring_idle(struct intel_ring_buffer *ring)
2234 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2237 if (!list_empty(&ring->gpu_write_list)) {
2238 ret = i915_gem_flush_ring(ring,
2239 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2244 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2248 i915_gpu_idle(struct drm_device *dev)
2250 drm_i915_private_t *dev_priv = dev->dev_private;
2254 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2255 list_empty(&dev_priv->mm.active_list));
2259 /* Flush everything onto the inactive list. */
2260 for (i = 0; i < I915_NUM_RINGS; i++) {
2261 ret = i915_ring_idle(&dev_priv->ring[i]);
2269 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2270 struct intel_ring_buffer *pipelined)
2272 struct drm_device *dev = obj->base.dev;
2273 drm_i915_private_t *dev_priv = dev->dev_private;
2274 u32 size = obj->gtt_space->size;
2275 int regnum = obj->fence_reg;
2278 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2280 val |= obj->gtt_offset & 0xfffff000;
2281 val |= (uint64_t)((obj->stride / 128) - 1) <<
2282 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2284 if (obj->tiling_mode == I915_TILING_Y)
2285 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2286 val |= I965_FENCE_REG_VALID;
2289 int ret = intel_ring_begin(pipelined, 6);
2293 intel_ring_emit(pipelined, MI_NOOP);
2294 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2295 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2296 intel_ring_emit(pipelined, (u32)val);
2297 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2298 intel_ring_emit(pipelined, (u32)(val >> 32));
2299 intel_ring_advance(pipelined);
2301 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2306 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2307 struct intel_ring_buffer *pipelined)
2309 struct drm_device *dev = obj->base.dev;
2310 drm_i915_private_t *dev_priv = dev->dev_private;
2311 u32 size = obj->gtt_space->size;
2312 int regnum = obj->fence_reg;
2315 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2317 val |= obj->gtt_offset & 0xfffff000;
2318 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2319 if (obj->tiling_mode == I915_TILING_Y)
2320 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2321 val |= I965_FENCE_REG_VALID;
2324 int ret = intel_ring_begin(pipelined, 6);
2328 intel_ring_emit(pipelined, MI_NOOP);
2329 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2330 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2331 intel_ring_emit(pipelined, (u32)val);
2332 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2333 intel_ring_emit(pipelined, (u32)(val >> 32));
2334 intel_ring_advance(pipelined);
2336 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2341 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2342 struct intel_ring_buffer *pipelined)
2344 struct drm_device *dev = obj->base.dev;
2345 drm_i915_private_t *dev_priv = dev->dev_private;
2346 u32 size = obj->gtt_space->size;
2347 u32 fence_reg, val, pitch_val;
2350 if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2351 (size & -size) != size ||
2352 (obj->gtt_offset & (size - 1)),
2353 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2354 obj->gtt_offset, obj->map_and_fenceable, size))
2357 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2362 /* Note: pitch better be a power of two tile widths */
2363 pitch_val = obj->stride / tile_width;
2364 pitch_val = ffs(pitch_val) - 1;
2366 val = obj->gtt_offset;
2367 if (obj->tiling_mode == I915_TILING_Y)
2368 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2369 val |= I915_FENCE_SIZE_BITS(size);
2370 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2371 val |= I830_FENCE_REG_VALID;
2373 fence_reg = obj->fence_reg;
2375 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2377 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2380 int ret = intel_ring_begin(pipelined, 4);
2384 intel_ring_emit(pipelined, MI_NOOP);
2385 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2386 intel_ring_emit(pipelined, fence_reg);
2387 intel_ring_emit(pipelined, val);
2388 intel_ring_advance(pipelined);
2390 I915_WRITE(fence_reg, val);
2395 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2396 struct intel_ring_buffer *pipelined)
2398 struct drm_device *dev = obj->base.dev;
2399 drm_i915_private_t *dev_priv = dev->dev_private;
2400 u32 size = obj->gtt_space->size;
2401 int regnum = obj->fence_reg;
2405 if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2406 (size & -size) != size ||
2407 (obj->gtt_offset & (size - 1)),
2408 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2409 obj->gtt_offset, size))
2412 pitch_val = obj->stride / 128;
2413 pitch_val = ffs(pitch_val) - 1;
2415 val = obj->gtt_offset;
2416 if (obj->tiling_mode == I915_TILING_Y)
2417 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2418 val |= I830_FENCE_SIZE_BITS(size);
2419 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2420 val |= I830_FENCE_REG_VALID;
2423 int ret = intel_ring_begin(pipelined, 4);
2427 intel_ring_emit(pipelined, MI_NOOP);
2428 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2429 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2430 intel_ring_emit(pipelined, val);
2431 intel_ring_advance(pipelined);
2433 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2438 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2440 return i915_seqno_passed(ring->get_seqno(ring), seqno);
2444 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2445 struct intel_ring_buffer *pipelined)
2449 if (obj->fenced_gpu_access) {
2450 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2451 ret = i915_gem_flush_ring(obj->last_fenced_ring,
2452 0, obj->base.write_domain);
2457 obj->fenced_gpu_access = false;
2460 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2461 if (!ring_passed_seqno(obj->last_fenced_ring,
2462 obj->last_fenced_seqno)) {
2463 ret = i915_wait_request(obj->last_fenced_ring,
2464 obj->last_fenced_seqno);
2469 obj->last_fenced_seqno = 0;
2470 obj->last_fenced_ring = NULL;
2473 /* Ensure that all CPU reads are completed before installing a fence
2474 * and all writes before removing the fence.
2476 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2483 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2487 if (obj->tiling_mode)
2488 i915_gem_release_mmap(obj);
2490 ret = i915_gem_object_flush_fence(obj, NULL);
2494 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2495 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2496 i915_gem_clear_fence_reg(obj->base.dev,
2497 &dev_priv->fence_regs[obj->fence_reg]);
2499 obj->fence_reg = I915_FENCE_REG_NONE;
2505 static struct drm_i915_fence_reg *
2506 i915_find_fence_reg(struct drm_device *dev,
2507 struct intel_ring_buffer *pipelined)
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct drm_i915_fence_reg *reg, *first, *avail;
2513 /* First try to find a free reg */
2515 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2516 reg = &dev_priv->fence_regs[i];
2520 if (!reg->obj->pin_count)
2527 /* None available, try to steal one or wait for a user to finish */
2528 avail = first = NULL;
2529 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2530 if (reg->obj->pin_count)
2537 !reg->obj->last_fenced_ring ||
2538 reg->obj->last_fenced_ring == pipelined) {
2551 * i915_gem_object_get_fence - set up a fence reg for an object
2552 * @obj: object to map through a fence reg
2553 * @pipelined: ring on which to queue the change, or NULL for CPU access
2554 * @interruptible: must we wait uninterruptibly for the register to retire?
2556 * When mapping objects through the GTT, userspace wants to be able to write
2557 * to them without having to worry about swizzling if the object is tiled.
2559 * This function walks the fence regs looking for a free one for @obj,
2560 * stealing one if it can't find any.
2562 * It then sets up the reg based on the object's properties: address, pitch
2563 * and tiling format.
2566 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2567 struct intel_ring_buffer *pipelined)
2569 struct drm_device *dev = obj->base.dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct drm_i915_fence_reg *reg;
2574 /* XXX disable pipelining. There are bugs. Shocking. */
2577 /* Just update our place in the LRU if our fence is getting reused. */
2578 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2579 reg = &dev_priv->fence_regs[obj->fence_reg];
2580 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2582 if (obj->tiling_changed) {
2583 ret = i915_gem_object_flush_fence(obj, pipelined);
2587 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2592 i915_gem_next_request_seqno(pipelined);
2593 obj->last_fenced_seqno = reg->setup_seqno;
2594 obj->last_fenced_ring = pipelined;
2601 if (reg->setup_seqno) {
2602 if (!ring_passed_seqno(obj->last_fenced_ring,
2603 reg->setup_seqno)) {
2604 ret = i915_wait_request(obj->last_fenced_ring,
2610 reg->setup_seqno = 0;
2612 } else if (obj->last_fenced_ring &&
2613 obj->last_fenced_ring != pipelined) {
2614 ret = i915_gem_object_flush_fence(obj, pipelined);
2622 reg = i915_find_fence_reg(dev, pipelined);
2626 ret = i915_gem_object_flush_fence(obj, pipelined);
2631 struct drm_i915_gem_object *old = reg->obj;
2633 drm_gem_object_reference(&old->base);
2635 if (old->tiling_mode)
2636 i915_gem_release_mmap(old);
2638 ret = i915_gem_object_flush_fence(old, pipelined);
2640 drm_gem_object_unreference(&old->base);
2644 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2647 old->fence_reg = I915_FENCE_REG_NONE;
2648 old->last_fenced_ring = pipelined;
2649 old->last_fenced_seqno =
2650 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2652 drm_gem_object_unreference(&old->base);
2653 } else if (obj->last_fenced_seqno == 0)
2657 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2658 obj->fence_reg = reg - dev_priv->fence_regs;
2659 obj->last_fenced_ring = pipelined;
2662 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2663 obj->last_fenced_seqno = reg->setup_seqno;
2666 obj->tiling_changed = false;
2667 switch (INTEL_INFO(dev)->gen) {
2670 ret = sandybridge_write_fence_reg(obj, pipelined);
2674 ret = i965_write_fence_reg(obj, pipelined);
2677 ret = i915_write_fence_reg(obj, pipelined);
2680 ret = i830_write_fence_reg(obj, pipelined);
2688 * i915_gem_clear_fence_reg - clear out fence register info
2689 * @obj: object to clear
2691 * Zeroes out the fence register itself and clears out the associated
2692 * data structures in dev_priv and obj.
2695 i915_gem_clear_fence_reg(struct drm_device *dev,
2696 struct drm_i915_fence_reg *reg)
2698 drm_i915_private_t *dev_priv = dev->dev_private;
2699 uint32_t fence_reg = reg - dev_priv->fence_regs;
2701 switch (INTEL_INFO(dev)->gen) {
2704 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2708 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2712 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2715 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2717 I915_WRITE(fence_reg, 0);
2721 list_del_init(®->lru_list);
2723 reg->setup_seqno = 0;
2727 * Finds free space in the GTT aperture and binds the object there.
2730 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2732 bool map_and_fenceable)
2734 struct drm_device *dev = obj->base.dev;
2735 drm_i915_private_t *dev_priv = dev->dev_private;
2736 struct drm_mm_node *free_space;
2737 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2738 u32 size, fence_size, fence_alignment, unfenced_alignment;
2739 bool mappable, fenceable;
2742 if (obj->madv != I915_MADV_WILLNEED) {
2743 DRM_ERROR("Attempting to bind a purgeable object\n");
2747 fence_size = i915_gem_get_gtt_size(obj);
2748 fence_alignment = i915_gem_get_gtt_alignment(obj);
2749 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2752 alignment = map_and_fenceable ? fence_alignment :
2754 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2755 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2759 size = map_and_fenceable ? fence_size : obj->base.size;
2761 /* If the object is bigger than the entire aperture, reject it early
2762 * before evicting everything in a vain attempt to find space.
2764 if (obj->base.size >
2765 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2766 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2771 if (map_and_fenceable)
2773 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2775 dev_priv->mm.gtt_mappable_end,
2778 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2779 size, alignment, 0);
2781 if (free_space != NULL) {
2782 if (map_and_fenceable)
2784 drm_mm_get_block_range_generic(free_space,
2786 dev_priv->mm.gtt_mappable_end,
2790 drm_mm_get_block(free_space, size, alignment);
2792 if (obj->gtt_space == NULL) {
2793 /* If the gtt is empty and we're still having trouble
2794 * fitting our object in, we're out of memory.
2796 ret = i915_gem_evict_something(dev, size, alignment,
2804 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2806 drm_mm_put_block(obj->gtt_space);
2807 obj->gtt_space = NULL;
2809 if (ret == -ENOMEM) {
2810 /* first try to reclaim some memory by clearing the GTT */
2811 ret = i915_gem_evict_everything(dev, false);
2813 /* now try to shrink everyone else */
2828 ret = i915_gem_gtt_bind_object(obj);
2830 i915_gem_object_put_pages_gtt(obj);
2831 drm_mm_put_block(obj->gtt_space);
2832 obj->gtt_space = NULL;
2834 if (i915_gem_evict_everything(dev, false))
2840 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2841 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2843 /* Assert that the object is not currently in any GPU domain. As it
2844 * wasn't in the GTT, there shouldn't be any way it could have been in
2847 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2848 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2850 obj->gtt_offset = obj->gtt_space->start;
2853 obj->gtt_space->size == fence_size &&
2854 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2857 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2859 obj->map_and_fenceable = mappable && fenceable;
2861 trace_i915_gem_object_bind(obj, map_and_fenceable);
2866 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2868 /* If we don't have a page list set up, then we're not pinned
2869 * to GPU, and we can ignore the cache flush because it'll happen
2870 * again at bind time.
2872 if (obj->pages == NULL)
2875 /* If the GPU is snooping the contents of the CPU cache,
2876 * we do not need to manually clear the CPU cache lines. However,
2877 * the caches are only snooped when the render cache is
2878 * flushed/invalidated. As we always have to emit invalidations
2879 * and flushes when moving into and out of the RENDER domain, correct
2880 * snooping behaviour occurs naturally as the result of our domain
2883 if (obj->cache_level != I915_CACHE_NONE)
2886 trace_i915_gem_object_clflush(obj);
2888 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2891 /** Flushes any GPU write domain for the object if it's dirty. */
2893 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2895 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2898 /* Queue the GPU write cache flushing we need. */
2899 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2902 /** Flushes the GTT write domain for the object if it's dirty. */
2904 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2906 uint32_t old_write_domain;
2908 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2911 /* No actual flushing is required for the GTT write domain. Writes
2912 * to it immediately go to main memory as far as we know, so there's
2913 * no chipset flush. It also doesn't land in render cache.
2915 * However, we do have to enforce the order so that all writes through
2916 * the GTT land before any writes to the device, such as updates to
2921 old_write_domain = obj->base.write_domain;
2922 obj->base.write_domain = 0;
2924 trace_i915_gem_object_change_domain(obj,
2925 obj->base.read_domains,
2929 /** Flushes the CPU write domain for the object if it's dirty. */
2931 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2933 uint32_t old_write_domain;
2935 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2938 i915_gem_clflush_object(obj);
2939 intel_gtt_chipset_flush();
2940 old_write_domain = obj->base.write_domain;
2941 obj->base.write_domain = 0;
2943 trace_i915_gem_object_change_domain(obj,
2944 obj->base.read_domains,
2949 * Moves a single object to the GTT read, and possibly write domain.
2951 * This function returns when the move is complete, including waiting on
2955 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2957 uint32_t old_write_domain, old_read_domains;
2960 /* Not valid to be called on unbound objects. */
2961 if (obj->gtt_space == NULL)
2964 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2967 ret = i915_gem_object_flush_gpu_write_domain(obj);
2971 if (obj->pending_gpu_write || write) {
2972 ret = i915_gem_object_wait_rendering(obj);
2977 i915_gem_object_flush_cpu_write_domain(obj);
2979 old_write_domain = obj->base.write_domain;
2980 old_read_domains = obj->base.read_domains;
2982 /* It should now be out of any other write domains, and we can update
2983 * the domain values for our changes.
2985 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2986 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2988 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2989 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2993 trace_i915_gem_object_change_domain(obj,
3001 * Prepare buffer for display plane. Use uninterruptible for possible flush
3002 * wait, as in modesetting process we're not supposed to be interrupted.
3005 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
3006 struct intel_ring_buffer *pipelined)
3008 uint32_t old_read_domains;
3011 /* Not valid to be called on unbound objects. */
3012 if (obj->gtt_space == NULL)
3015 ret = i915_gem_object_flush_gpu_write_domain(obj);
3020 /* Currently, we are always called from an non-interruptible context. */
3021 if (pipelined != obj->ring) {
3022 ret = i915_gem_object_wait_rendering(obj);
3027 i915_gem_object_flush_cpu_write_domain(obj);
3029 old_read_domains = obj->base.read_domains;
3030 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3032 trace_i915_gem_object_change_domain(obj,
3034 obj->base.write_domain);
3040 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
3047 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3048 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3053 return i915_gem_object_wait_rendering(obj);
3057 * Moves a single object to the CPU read, and possibly write domain.
3059 * This function returns when the move is complete, including waiting on
3063 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3065 uint32_t old_write_domain, old_read_domains;
3068 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3071 ret = i915_gem_object_flush_gpu_write_domain(obj);
3075 ret = i915_gem_object_wait_rendering(obj);
3079 i915_gem_object_flush_gtt_write_domain(obj);
3081 /* If we have a partially-valid cache of the object in the CPU,
3082 * finish invalidating it and free the per-page flags.
3084 i915_gem_object_set_to_full_cpu_read_domain(obj);
3086 old_write_domain = obj->base.write_domain;
3087 old_read_domains = obj->base.read_domains;
3089 /* Flush the CPU cache if it's still invalid. */
3090 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3091 i915_gem_clflush_object(obj);
3093 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3096 /* It should now be out of any other write domains, and we can update
3097 * the domain values for our changes.
3099 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3101 /* If we're writing through the CPU, then the GPU read domains will
3102 * need to be invalidated at next use.
3105 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3106 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3109 trace_i915_gem_object_change_domain(obj,
3117 * Moves the object from a partially CPU read to a full one.
3119 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3120 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3123 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3125 if (!obj->page_cpu_valid)
3128 /* If we're partially in the CPU read domain, finish moving it in.
3130 if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3133 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3134 if (obj->page_cpu_valid[i])
3136 drm_clflush_pages(obj->pages + i, 1);
3140 /* Free the page_cpu_valid mappings which are now stale, whether
3141 * or not we've got I915_GEM_DOMAIN_CPU.
3143 kfree(obj->page_cpu_valid);
3144 obj->page_cpu_valid = NULL;
3148 * Set the CPU read domain on a range of the object.
3150 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3151 * not entirely valid. The page_cpu_valid member of the object flags which
3152 * pages have been flushed, and will be respected by
3153 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3154 * of the whole object.
3156 * This function returns when the move is complete, including waiting on
3160 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3161 uint64_t offset, uint64_t size)
3163 uint32_t old_read_domains;
3166 if (offset == 0 && size == obj->base.size)
3167 return i915_gem_object_set_to_cpu_domain(obj, 0);
3169 ret = i915_gem_object_flush_gpu_write_domain(obj);
3173 ret = i915_gem_object_wait_rendering(obj);
3177 i915_gem_object_flush_gtt_write_domain(obj);
3179 /* If we're already fully in the CPU read domain, we're done. */
3180 if (obj->page_cpu_valid == NULL &&
3181 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3184 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3185 * newly adding I915_GEM_DOMAIN_CPU
3187 if (obj->page_cpu_valid == NULL) {
3188 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3190 if (obj->page_cpu_valid == NULL)
3192 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3193 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3195 /* Flush the cache on any pages that are still invalid from the CPU's
3198 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3200 if (obj->page_cpu_valid[i])
3203 drm_clflush_pages(obj->pages + i, 1);
3205 obj->page_cpu_valid[i] = 1;
3208 /* It should now be out of any other write domains, and we can update
3209 * the domain values for our changes.
3211 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3213 old_read_domains = obj->base.read_domains;
3214 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3216 trace_i915_gem_object_change_domain(obj,
3218 obj->base.write_domain);
3223 /* Throttle our rendering by waiting until the ring has completed our requests
3224 * emitted over 20 msec ago.
3226 * Note that if we were to use the current jiffies each time around the loop,
3227 * we wouldn't escape the function with any frames outstanding if the time to
3228 * render a frame was over 20ms.
3230 * This should get us reasonable parallelism between CPU and GPU but also
3231 * relatively low latency when blocking on a particular request to finish.
3234 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 struct drm_i915_file_private *file_priv = file->driver_priv;
3238 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3239 struct drm_i915_gem_request *request;
3240 struct intel_ring_buffer *ring = NULL;
3244 if (atomic_read(&dev_priv->mm.wedged))
3247 spin_lock(&file_priv->mm.lock);
3248 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3249 if (time_after_eq(request->emitted_jiffies, recent_enough))
3252 ring = request->ring;
3253 seqno = request->seqno;
3255 spin_unlock(&file_priv->mm.lock);
3261 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3262 /* And wait for the seqno passing without holding any locks and
3263 * causing extra latency for others. This is safe as the irq
3264 * generation is designed to be run atomically and so is
3267 if (ring->irq_get(ring)) {
3268 ret = wait_event_interruptible(ring->irq_queue,
3269 i915_seqno_passed(ring->get_seqno(ring), seqno)
3270 || atomic_read(&dev_priv->mm.wedged));
3271 ring->irq_put(ring);
3273 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3279 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3285 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3287 bool map_and_fenceable)
3289 struct drm_device *dev = obj->base.dev;
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3293 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3294 WARN_ON(i915_verify_lists(dev));
3296 if (obj->gtt_space != NULL) {
3297 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3298 (map_and_fenceable && !obj->map_and_fenceable)) {
3299 WARN(obj->pin_count,
3300 "bo is already pinned with incorrect alignment:"
3301 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3302 " obj->map_and_fenceable=%d\n",
3303 obj->gtt_offset, alignment,
3305 obj->map_and_fenceable);
3306 ret = i915_gem_object_unbind(obj);
3312 if (obj->gtt_space == NULL) {
3313 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3319 if (obj->pin_count++ == 0) {
3321 list_move_tail(&obj->mm_list,
3322 &dev_priv->mm.pinned_list);
3324 obj->pin_mappable |= map_and_fenceable;
3326 WARN_ON(i915_verify_lists(dev));
3331 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3333 struct drm_device *dev = obj->base.dev;
3334 drm_i915_private_t *dev_priv = dev->dev_private;
3336 WARN_ON(i915_verify_lists(dev));
3337 BUG_ON(obj->pin_count == 0);
3338 BUG_ON(obj->gtt_space == NULL);
3340 if (--obj->pin_count == 0) {
3342 list_move_tail(&obj->mm_list,
3343 &dev_priv->mm.inactive_list);
3344 obj->pin_mappable = false;
3346 WARN_ON(i915_verify_lists(dev));
3350 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3351 struct drm_file *file)
3353 struct drm_i915_gem_pin *args = data;
3354 struct drm_i915_gem_object *obj;
3357 ret = i915_mutex_lock_interruptible(dev);
3361 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3362 if (&obj->base == NULL) {
3367 if (obj->madv != I915_MADV_WILLNEED) {
3368 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3373 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3374 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3380 obj->user_pin_count++;
3381 obj->pin_filp = file;
3382 if (obj->user_pin_count == 1) {
3383 ret = i915_gem_object_pin(obj, args->alignment, true);
3388 /* XXX - flush the CPU caches for pinned objects
3389 * as the X server doesn't manage domains yet
3391 i915_gem_object_flush_cpu_write_domain(obj);
3392 args->offset = obj->gtt_offset;
3394 drm_gem_object_unreference(&obj->base);
3396 mutex_unlock(&dev->struct_mutex);
3401 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3402 struct drm_file *file)
3404 struct drm_i915_gem_pin *args = data;
3405 struct drm_i915_gem_object *obj;
3408 ret = i915_mutex_lock_interruptible(dev);
3412 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3413 if (&obj->base == NULL) {
3418 if (obj->pin_filp != file) {
3419 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3424 obj->user_pin_count--;
3425 if (obj->user_pin_count == 0) {
3426 obj->pin_filp = NULL;
3427 i915_gem_object_unpin(obj);
3431 drm_gem_object_unreference(&obj->base);
3433 mutex_unlock(&dev->struct_mutex);
3438 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3439 struct drm_file *file)
3441 struct drm_i915_gem_busy *args = data;
3442 struct drm_i915_gem_object *obj;
3445 ret = i915_mutex_lock_interruptible(dev);
3449 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3450 if (&obj->base == NULL) {
3455 /* Count all active objects as busy, even if they are currently not used
3456 * by the gpu. Users of this interface expect objects to eventually
3457 * become non-busy without any further actions, therefore emit any
3458 * necessary flushes here.
3460 args->busy = obj->active;
3462 /* Unconditionally flush objects, even when the gpu still uses this
3463 * object. Userspace calling this function indicates that it wants to
3464 * use this buffer rather sooner than later, so issuing the required
3465 * flush earlier is beneficial.
3467 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3468 ret = i915_gem_flush_ring(obj->ring,
3469 0, obj->base.write_domain);
3470 } else if (obj->ring->outstanding_lazy_request ==
3471 obj->last_rendering_seqno) {
3472 struct drm_i915_gem_request *request;
3474 /* This ring is not being cleared by active usage,
3475 * so emit a request to do so.
3477 request = kzalloc(sizeof(*request), GFP_KERNEL);
3479 ret = i915_add_request(obj->ring, NULL,request);
3484 /* Update the active list for the hardware's current position.
3485 * Otherwise this only updates on a delayed timer or when irqs
3486 * are actually unmasked, and our working set ends up being
3487 * larger than required.
3489 i915_gem_retire_requests_ring(obj->ring);
3491 args->busy = obj->active;
3494 drm_gem_object_unreference(&obj->base);
3496 mutex_unlock(&dev->struct_mutex);
3501 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3502 struct drm_file *file_priv)
3504 return i915_gem_ring_throttle(dev, file_priv);
3508 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3509 struct drm_file *file_priv)
3511 struct drm_i915_gem_madvise *args = data;
3512 struct drm_i915_gem_object *obj;
3515 switch (args->madv) {
3516 case I915_MADV_DONTNEED:
3517 case I915_MADV_WILLNEED:
3523 ret = i915_mutex_lock_interruptible(dev);
3527 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3528 if (&obj->base == NULL) {
3533 if (obj->pin_count) {
3538 if (obj->madv != __I915_MADV_PURGED)
3539 obj->madv = args->madv;
3541 /* if the object is no longer bound, discard its backing storage */
3542 if (i915_gem_object_is_purgeable(obj) &&
3543 obj->gtt_space == NULL)
3544 i915_gem_object_truncate(obj);
3546 args->retained = obj->madv != __I915_MADV_PURGED;
3549 drm_gem_object_unreference(&obj->base);
3551 mutex_unlock(&dev->struct_mutex);
3555 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct drm_i915_gem_object *obj;
3560 struct address_space *mapping;
3562 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3566 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3571 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3572 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3574 i915_gem_info_add_obj(dev_priv, size);
3576 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3577 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3579 obj->cache_level = I915_CACHE_NONE;
3580 obj->base.driver_private = NULL;
3581 obj->fence_reg = I915_FENCE_REG_NONE;
3582 INIT_LIST_HEAD(&obj->mm_list);
3583 INIT_LIST_HEAD(&obj->gtt_list);
3584 INIT_LIST_HEAD(&obj->ring_list);
3585 INIT_LIST_HEAD(&obj->exec_list);
3586 INIT_LIST_HEAD(&obj->gpu_write_list);
3587 obj->madv = I915_MADV_WILLNEED;
3588 /* Avoid an unnecessary call to unbind on the first bind. */
3589 obj->map_and_fenceable = true;
3594 int i915_gem_init_object(struct drm_gem_object *obj)
3601 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3603 struct drm_device *dev = obj->base.dev;
3604 drm_i915_private_t *dev_priv = dev->dev_private;
3607 ret = i915_gem_object_unbind(obj);
3608 if (ret == -ERESTARTSYS) {
3609 list_move(&obj->mm_list,
3610 &dev_priv->mm.deferred_free_list);
3614 trace_i915_gem_object_destroy(obj);
3616 if (obj->base.map_list.map)
3617 i915_gem_free_mmap_offset(obj);
3619 drm_gem_object_release(&obj->base);
3620 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3622 kfree(obj->page_cpu_valid);
3627 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3629 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3630 struct drm_device *dev = obj->base.dev;
3632 while (obj->pin_count > 0)
3633 i915_gem_object_unpin(obj);
3636 i915_gem_detach_phys_object(dev, obj);
3638 i915_gem_free_object_tail(obj);
3642 i915_gem_idle(struct drm_device *dev)
3644 drm_i915_private_t *dev_priv = dev->dev_private;
3647 mutex_lock(&dev->struct_mutex);
3649 if (dev_priv->mm.suspended) {
3650 mutex_unlock(&dev->struct_mutex);
3654 ret = i915_gpu_idle(dev);
3656 mutex_unlock(&dev->struct_mutex);
3660 /* Under UMS, be paranoid and evict. */
3661 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3662 ret = i915_gem_evict_inactive(dev, false);
3664 mutex_unlock(&dev->struct_mutex);
3669 i915_gem_reset_fences(dev);
3671 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3672 * We need to replace this with a semaphore, or something.
3673 * And not confound mm.suspended!
3675 dev_priv->mm.suspended = 1;
3676 del_timer_sync(&dev_priv->hangcheck_timer);
3678 i915_kernel_lost_context(dev);
3679 i915_gem_cleanup_ringbuffer(dev);
3681 mutex_unlock(&dev->struct_mutex);
3683 /* Cancel the retire work handler, which should be idle now. */
3684 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3690 i915_gem_init_ringbuffer(struct drm_device *dev)
3692 drm_i915_private_t *dev_priv = dev->dev_private;
3695 ret = intel_init_render_ring_buffer(dev);
3700 ret = intel_init_bsd_ring_buffer(dev);
3702 goto cleanup_render_ring;
3706 ret = intel_init_blt_ring_buffer(dev);
3708 goto cleanup_bsd_ring;
3711 dev_priv->next_seqno = 1;
3716 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3717 cleanup_render_ring:
3718 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3723 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3725 drm_i915_private_t *dev_priv = dev->dev_private;
3728 for (i = 0; i < I915_NUM_RINGS; i++)
3729 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3733 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3734 struct drm_file *file_priv)
3736 drm_i915_private_t *dev_priv = dev->dev_private;
3739 if (drm_core_check_feature(dev, DRIVER_MODESET))
3742 if (atomic_read(&dev_priv->mm.wedged)) {
3743 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3744 atomic_set(&dev_priv->mm.wedged, 0);
3747 mutex_lock(&dev->struct_mutex);
3748 dev_priv->mm.suspended = 0;
3750 ret = i915_gem_init_ringbuffer(dev);
3752 mutex_unlock(&dev->struct_mutex);
3756 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3757 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3758 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3759 for (i = 0; i < I915_NUM_RINGS; i++) {
3760 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3761 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3763 mutex_unlock(&dev->struct_mutex);
3765 ret = drm_irq_install(dev);
3767 goto cleanup_ringbuffer;
3772 mutex_lock(&dev->struct_mutex);
3773 i915_gem_cleanup_ringbuffer(dev);
3774 dev_priv->mm.suspended = 1;
3775 mutex_unlock(&dev->struct_mutex);
3781 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3782 struct drm_file *file_priv)
3784 if (drm_core_check_feature(dev, DRIVER_MODESET))
3787 drm_irq_uninstall(dev);
3788 return i915_gem_idle(dev);
3792 i915_gem_lastclose(struct drm_device *dev)
3796 if (drm_core_check_feature(dev, DRIVER_MODESET))
3799 ret = i915_gem_idle(dev);
3801 DRM_ERROR("failed to idle hardware: %d\n", ret);
3805 init_ring_lists(struct intel_ring_buffer *ring)
3807 INIT_LIST_HEAD(&ring->active_list);
3808 INIT_LIST_HEAD(&ring->request_list);
3809 INIT_LIST_HEAD(&ring->gpu_write_list);
3813 i915_gem_load(struct drm_device *dev)
3816 drm_i915_private_t *dev_priv = dev->dev_private;
3818 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3819 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3820 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3821 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3822 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3823 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3824 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3825 for (i = 0; i < I915_NUM_RINGS; i++)
3826 init_ring_lists(&dev_priv->ring[i]);
3827 for (i = 0; i < 16; i++)
3828 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3829 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3830 i915_gem_retire_work_handler);
3831 init_completion(&dev_priv->error_completion);
3833 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3835 u32 tmp = I915_READ(MI_ARB_STATE);
3836 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3837 /* arb state is a masked write, so set bit + bit in mask */
3838 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3839 I915_WRITE(MI_ARB_STATE, tmp);
3843 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3845 /* Old X drivers will take 0-2 for front, back, depth buffers */
3846 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3847 dev_priv->fence_reg_start = 3;
3849 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3850 dev_priv->num_fence_regs = 16;
3852 dev_priv->num_fence_regs = 8;
3854 /* Initialize fence registers to zero */
3855 for (i = 0; i < dev_priv->num_fence_regs; i++) {
3856 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3859 i915_gem_detect_bit_6_swizzle(dev);
3860 init_waitqueue_head(&dev_priv->pending_flip_queue);
3862 dev_priv->mm.interruptible = true;
3864 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3865 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3866 register_shrinker(&dev_priv->mm.inactive_shrinker);
3870 * Create a physically contiguous memory object for this object
3871 * e.g. for cursor + overlay regs
3873 static int i915_gem_init_phys_object(struct drm_device *dev,
3874 int id, int size, int align)
3876 drm_i915_private_t *dev_priv = dev->dev_private;
3877 struct drm_i915_gem_phys_object *phys_obj;
3880 if (dev_priv->mm.phys_objs[id - 1] || !size)
3883 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3889 phys_obj->handle = drm_pci_alloc(dev, size, align);
3890 if (!phys_obj->handle) {
3895 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3898 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3906 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3908 drm_i915_private_t *dev_priv = dev->dev_private;
3909 struct drm_i915_gem_phys_object *phys_obj;
3911 if (!dev_priv->mm.phys_objs[id - 1])
3914 phys_obj = dev_priv->mm.phys_objs[id - 1];
3915 if (phys_obj->cur_obj) {
3916 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3920 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3922 drm_pci_free(dev, phys_obj->handle);
3924 dev_priv->mm.phys_objs[id - 1] = NULL;
3927 void i915_gem_free_all_phys_object(struct drm_device *dev)
3931 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3932 i915_gem_free_phys_object(dev, i);
3935 void i915_gem_detach_phys_object(struct drm_device *dev,
3936 struct drm_i915_gem_object *obj)
3938 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3945 vaddr = obj->phys_obj->handle->vaddr;
3947 page_count = obj->base.size / PAGE_SIZE;
3948 for (i = 0; i < page_count; i++) {
3949 struct page *page = shmem_read_mapping_page(mapping, i);
3950 if (!IS_ERR(page)) {
3951 char *dst = kmap_atomic(page);
3952 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3955 drm_clflush_pages(&page, 1);
3957 set_page_dirty(page);
3958 mark_page_accessed(page);
3959 page_cache_release(page);
3962 intel_gtt_chipset_flush();
3964 obj->phys_obj->cur_obj = NULL;
3965 obj->phys_obj = NULL;
3969 i915_gem_attach_phys_object(struct drm_device *dev,
3970 struct drm_i915_gem_object *obj,
3974 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3975 drm_i915_private_t *dev_priv = dev->dev_private;
3980 if (id > I915_MAX_PHYS_OBJECT)
3983 if (obj->phys_obj) {
3984 if (obj->phys_obj->id == id)
3986 i915_gem_detach_phys_object(dev, obj);
3989 /* create a new object */
3990 if (!dev_priv->mm.phys_objs[id - 1]) {
3991 ret = i915_gem_init_phys_object(dev, id,
3992 obj->base.size, align);
3994 DRM_ERROR("failed to init phys object %d size: %zu\n",
3995 id, obj->base.size);
4000 /* bind to the object */
4001 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4002 obj->phys_obj->cur_obj = obj;
4004 page_count = obj->base.size / PAGE_SIZE;
4006 for (i = 0; i < page_count; i++) {
4010 page = shmem_read_mapping_page(mapping, i);
4012 return PTR_ERR(page);
4014 src = kmap_atomic(page);
4015 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4016 memcpy(dst, src, PAGE_SIZE);
4019 mark_page_accessed(page);
4020 page_cache_release(page);
4027 i915_gem_phys_pwrite(struct drm_device *dev,
4028 struct drm_i915_gem_object *obj,
4029 struct drm_i915_gem_pwrite *args,
4030 struct drm_file *file_priv)
4032 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4033 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4035 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4036 unsigned long unwritten;
4038 /* The physical object once assigned is fixed for the lifetime
4039 * of the obj, so we can safely drop the lock and continue
4042 mutex_unlock(&dev->struct_mutex);
4043 unwritten = copy_from_user(vaddr, user_data, args->size);
4044 mutex_lock(&dev->struct_mutex);
4049 intel_gtt_chipset_flush();
4053 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4055 struct drm_i915_file_private *file_priv = file->driver_priv;
4057 /* Clean up our request list when the client is going away, so that
4058 * later retire_requests won't dereference our soon-to-be-gone
4061 spin_lock(&file_priv->mm.lock);
4062 while (!list_empty(&file_priv->mm.request_list)) {
4063 struct drm_i915_gem_request *request;
4065 request = list_first_entry(&file_priv->mm.request_list,
4066 struct drm_i915_gem_request,
4068 list_del(&request->client_list);
4069 request->file_priv = NULL;
4071 spin_unlock(&file_priv->mm.lock);
4075 i915_gpu_is_active(struct drm_device *dev)
4077 drm_i915_private_t *dev_priv = dev->dev_private;
4080 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4081 list_empty(&dev_priv->mm.active_list);
4083 return !lists_empty;
4087 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4089 struct drm_i915_private *dev_priv =
4090 container_of(shrinker,
4091 struct drm_i915_private,
4092 mm.inactive_shrinker);
4093 struct drm_device *dev = dev_priv->dev;
4094 struct drm_i915_gem_object *obj, *next;
4095 int nr_to_scan = sc->nr_to_scan;
4098 if (!mutex_trylock(&dev->struct_mutex))
4101 /* "fast-path" to count number of available objects */
4102 if (nr_to_scan == 0) {
4104 list_for_each_entry(obj,
4105 &dev_priv->mm.inactive_list,
4108 mutex_unlock(&dev->struct_mutex);
4109 return cnt / 100 * sysctl_vfs_cache_pressure;
4113 /* first scan for clean buffers */
4114 i915_gem_retire_requests(dev);
4116 list_for_each_entry_safe(obj, next,
4117 &dev_priv->mm.inactive_list,
4119 if (i915_gem_object_is_purgeable(obj)) {
4120 if (i915_gem_object_unbind(obj) == 0 &&
4126 /* second pass, evict/count anything still on the inactive list */
4128 list_for_each_entry_safe(obj, next,
4129 &dev_priv->mm.inactive_list,
4132 i915_gem_object_unbind(obj) == 0)
4138 if (nr_to_scan && i915_gpu_is_active(dev)) {
4140 * We are desperate for pages, so as a last resort, wait
4141 * for the GPU to finish and discard whatever we can.
4142 * This has a dramatic impact to reduce the number of
4143 * OOM-killer events whilst running the GPU aggressively.
4145 if (i915_gpu_idle(dev) == 0)
4148 mutex_unlock(&dev->struct_mutex);
4149 return cnt / 100 * sysctl_vfs_cache_pressure;