drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/shmem_fs.h>
  35 #include <linux/slab.h>
  36 #include <linux/swap.h>
  37 #include <linux/pci.h>
  38
  39 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  42 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  43                                                           bool write);
  44 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  45                                                                   uint64_t offset,
  46                                                                   uint64_t size);
  47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  48 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  49                                                     unsigned alignment,
  50                                                     bool map_and_fenceable);
  51 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  52                                      struct drm_i915_fence_reg *reg);
  53 static int i915_gem_phys_pwrite(struct drm_device *dev,
  54                                 struct drm_i915_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file);
  57 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  58
  59 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  60                                     struct shrink_control *sc);
  61
  62 /* some bookkeeping */
  63 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  64                                   size_t size)
  65 {
  66         dev_priv->mm.object_count++;
  67         dev_priv->mm.object_memory += size;
  68 }
  69
  70 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  71                                      size_t size)
  72 {
  73         dev_priv->mm.object_count--;
  74         dev_priv->mm.object_memory -= size;
  75 }
  76
  77 static int
  78 i915_gem_wait_for_error(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct completion *x = &dev_priv->error_completion;
  82         unsigned long flags;
  83         int ret;
  84
  85         if (!atomic_read(&dev_priv->mm.wedged))
  86                 return 0;
  87
  88         ret = wait_for_completion_interruptible(x);
  89         if (ret)
  90                 return ret;
  91
  92         if (atomic_read(&dev_priv->mm.wedged)) {
  93                 /* GPU is hung, bump the completion count to account for
  94                  * the token we just consumed so that we never hit zero and
  95                  * end up waiting upon a subsequent completion event that
  96                  * will never happen.
  97                  */
  98                 spin_lock_irqsave(&x->wait.lock, flags);
  99                 x->done++;
 100                 spin_unlock_irqrestore(&x->wait.lock, flags);
 101         }
 102         return 0;
 103 }
 104
 105 int i915_mutex_lock_interruptible(struct drm_device *dev)
 106 {
 107         int ret;
 108
 109         ret = i915_gem_wait_for_error(dev);
 110         if (ret)
 111                 return ret;
 112
 113         ret = mutex_lock_interruptible(&dev->struct_mutex);
 114         if (ret)
 115                 return ret;
 116
 117         WARN_ON(i915_verify_lists(dev));
 118         return 0;
 119 }
 120
 121 static inline bool
 122 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 123 {
 124         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 125 }
 126
 127 void i915_gem_do_init(struct drm_device *dev,
 128                       unsigned long start,
 129                       unsigned long mappable_end,
 130                       unsigned long end)
 131 {
 132         drm_i915_private_t *dev_priv = dev->dev_private;
 133
 134         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 135
 136         dev_priv->mm.gtt_start = start;
 137         dev_priv->mm.gtt_mappable_end = mappable_end;
 138         dev_priv->mm.gtt_end = end;
 139         dev_priv->mm.gtt_total = end - start;
 140         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 141
 142         /* Take over this portion of the GTT */
 143         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 144 }
 145
 146 int
 147 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 148                     struct drm_file *file)
 149 {
 150         struct drm_i915_gem_init *args = data;
 151
 152         if (args->gtt_start >= args->gtt_end ||
 153             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 154                 return -EINVAL;
 155
 156         mutex_lock(&dev->struct_mutex);
 157         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 158         mutex_unlock(&dev->struct_mutex);
 159
 160         return 0;
 161 }
 162
 163 int
 164 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 165                             struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_get_aperture *args = data;
 169         struct drm_i915_gem_object *obj;
 170         size_t pinned;
 171
 172         if (!(dev->driver->driver_features & DRIVER_GEM))
 173                 return -ENODEV;
 174
 175         pinned = 0;
 176         mutex_lock(&dev->struct_mutex);
 177         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 178                 pinned += obj->gtt_space->size;
 179         mutex_unlock(&dev->struct_mutex);
 180
 181         args->aper_size = dev_priv->mm.gtt_total;
 182         args->aper_available_size = args->aper_size - pinned;
 183
 184         return 0;
 185 }
 186
 187 static int
 188 i915_gem_create(struct drm_file *file,
 189                 struct drm_device *dev,
 190                 uint64_t size,
 191                 uint32_t *handle_p)
 192 {
 193         struct drm_i915_gem_object *obj;
 194         int ret;
 195         u32 handle;
 196
 197         size = roundup(size, PAGE_SIZE);
 198
 199         /* Allocate the new object */
 200         obj = i915_gem_alloc_object(dev, size);
 201         if (obj == NULL)
 202                 return -ENOMEM;
 203
 204         ret = drm_gem_handle_create(file, &obj->base, &handle);
 205         if (ret) {
 206                 drm_gem_object_release(&obj->base);
 207                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 208                 kfree(obj);
 209                 return ret;
 210         }
 211
 212         /* drop reference from allocate - handle holds it now */
 213         drm_gem_object_unreference(&obj->base);
 214         trace_i915_gem_object_create(obj);
 215
 216         *handle_p = handle;
 217         return 0;
 218 }
 219
 220 int
 221 i915_gem_dumb_create(struct drm_file *file,
 222                      struct drm_device *dev,
 223                      struct drm_mode_create_dumb *args)
 224 {
 225         /* have to work out size/pitch and return them */
 226         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 227         args->size = args->pitch * args->height;
 228         return i915_gem_create(file, dev,
 229                                args->size, &args->handle);
 230 }
 231
 232 int i915_gem_dumb_destroy(struct drm_file *file,
 233                           struct drm_device *dev,
 234                           uint32_t handle)
 235 {
 236         return drm_gem_handle_delete(file, handle);
 237 }
 238
 239 /**
 240  * Creates a new mm object and returns a handle to it.
 241  */
 242 int
 243 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 244                       struct drm_file *file)
 245 {
 246         struct drm_i915_gem_create *args = data;
 247         return i915_gem_create(file, dev,
 248                                args->size, &args->handle);
 249 }
 250
 251 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 252 {
 253         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 254
 255         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 256                 obj->tiling_mode != I915_TILING_NONE;
 257 }
 258
 259 static inline void
 260 slow_shmem_copy(struct page *dst_page,
 261                 int dst_offset,
 262                 struct page *src_page,
 263                 int src_offset,
 264                 int length)
 265 {
 266         char *dst_vaddr, *src_vaddr;
 267
 268         dst_vaddr = kmap(dst_page);
 269         src_vaddr = kmap(src_page);
 270
 271         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 272
 273         kunmap(src_page);
 274         kunmap(dst_page);
 275 }
 276
 277 static inline void
 278 slow_shmem_bit17_copy(struct page *gpu_page,
 279                       int gpu_offset,
 280                       struct page *cpu_page,
 281                       int cpu_offset,
 282                       int length,
 283                       int is_read)
 284 {
 285         char *gpu_vaddr, *cpu_vaddr;
 286
 287         /* Use the unswizzled path if this page isn't affected. */
 288         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 289                 if (is_read)
 290                         return slow_shmem_copy(cpu_page, cpu_offset,
 291                                                gpu_page, gpu_offset, length);
 292                 else
 293                         return slow_shmem_copy(gpu_page, gpu_offset,
 294                                                cpu_page, cpu_offset, length);
 295         }
 296
 297         gpu_vaddr = kmap(gpu_page);
 298         cpu_vaddr = kmap(cpu_page);
 299
 300         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 301          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 302          */
 303         while (length > 0) {
 304                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 305                 int this_length = min(cacheline_end - gpu_offset, length);
 306                 int swizzled_gpu_offset = gpu_offset ^ 64;
 307
 308                 if (is_read) {
 309                         memcpy(cpu_vaddr + cpu_offset,
 310                                gpu_vaddr + swizzled_gpu_offset,
 311                                this_length);
 312                 } else {
 313                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 314                                cpu_vaddr + cpu_offset,
 315                                this_length);
 316                 }
 317                 cpu_offset += this_length;
 318                 gpu_offset += this_length;
 319                 length -= this_length;
 320         }
 321
 322         kunmap(cpu_page);
 323         kunmap(gpu_page);
 324 }
 325
 326 /**
 327  * This is the fast shmem pread path, which attempts to copy_from_user directly
 328  * from the backing pages of the object to the user's address space.  On a
 329  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 330  */
 331 static int
 332 i915_gem_shmem_pread_fast(struct drm_device *dev,
 333                           struct drm_i915_gem_object *obj,
 334                           struct drm_i915_gem_pread *args,
 335                           struct drm_file *file)
 336 {
 337         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 338         ssize_t remain;
 339         loff_t offset;
 340         char __user *user_data;
 341         int page_offset, page_length;
 342
 343         user_data = (char __user *) (uintptr_t) args->data_ptr;
 344         remain = args->size;
 345
 346         offset = args->offset;
 347
 348         while (remain > 0) {
 349                 struct page *page;
 350                 char *vaddr;
 351                 int ret;
 352
 353                 /* Operation in this page
 354                  *
 355                  * page_offset = offset within page
 356                  * page_length = bytes to copy for this page
 357                  */
 358                 page_offset = offset_in_page(offset);
 359                 page_length = remain;
 360                 if ((page_offset + remain) > PAGE_SIZE)
 361                         page_length = PAGE_SIZE - page_offset;
 362
 363                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 364                 if (IS_ERR(page))
 365                         return PTR_ERR(page);
 366
 367                 vaddr = kmap_atomic(page);
 368                 ret = __copy_to_user_inatomic(user_data,
 369                                               vaddr + page_offset,
 370                                               page_length);
 371                 kunmap_atomic(vaddr);
 372
 373                 mark_page_accessed(page);
 374                 page_cache_release(page);
 375                 if (ret)
 376                         return -EFAULT;
 377
 378                 remain -= page_length;
 379                 user_data += page_length;
 380                 offset += page_length;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * This is the fallback shmem pread path, which allocates temporary storage
 388  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 389  * can copy out of the object's backing pages while holding the struct mutex
 390  * and not take page faults.
 391  */
 392 static int
 393 i915_gem_shmem_pread_slow(struct drm_device *dev,
 394                           struct drm_i915_gem_object *obj,
 395                           struct drm_i915_gem_pread *args,
 396                           struct drm_file *file)
 397 {
 398         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 399         struct mm_struct *mm = current->mm;
 400         struct page **user_pages;
 401         ssize_t remain;
 402         loff_t offset, pinned_pages, i;
 403         loff_t first_data_page, last_data_page, num_pages;
 404         int shmem_page_offset;
 405         int data_page_index, data_page_offset;
 406         int page_length;
 407         int ret;
 408         uint64_t data_ptr = args->data_ptr;
 409         int do_bit17_swizzling;
 410
 411         remain = args->size;
 412
 413         /* Pin the user pages containing the data.  We can't fault while
 414          * holding the struct mutex, yet we want to hold it while
 415          * dereferencing the user data.
 416          */
 417         first_data_page = data_ptr / PAGE_SIZE;
 418         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 419         num_pages = last_data_page - first_data_page + 1;
 420
 421         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 422         if (user_pages == NULL)
 423                 return -ENOMEM;
 424
 425         mutex_unlock(&dev->struct_mutex);
 426         down_read(&mm->mmap_sem);
 427         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 428                                       num_pages, 1, 0, user_pages, NULL);
 429         up_read(&mm->mmap_sem);
 430         mutex_lock(&dev->struct_mutex);
 431         if (pinned_pages < num_pages) {
 432                 ret = -EFAULT;
 433                 goto out;
 434         }
 435
 436         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 437                                                         args->offset,
 438                                                         args->size);
 439         if (ret)
 440                 goto out;
 441
 442         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 443
 444         offset = args->offset;
 445
 446         while (remain > 0) {
 447                 struct page *page;
 448
 449                 /* Operation in this page
 450                  *
 451                  * shmem_page_offset = offset within page in shmem file
 452                  * data_page_index = page number in get_user_pages return
 453                  * data_page_offset = offset with data_page_index page.
 454                  * page_length = bytes to copy for this page
 455                  */
 456                 shmem_page_offset = offset_in_page(offset);
 457                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 458                 data_page_offset = offset_in_page(data_ptr);
 459
 460                 page_length = remain;
 461                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 462                         page_length = PAGE_SIZE - shmem_page_offset;
 463                 if ((data_page_offset + page_length) > PAGE_SIZE)
 464                         page_length = PAGE_SIZE - data_page_offset;
 465
 466                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 467                 if (IS_ERR(page)) {
 468                         ret = PTR_ERR(page);
 469                         goto out;
 470                 }
 471
 472                 if (do_bit17_swizzling) {
 473                         slow_shmem_bit17_copy(page,
 474                                               shmem_page_offset,
 475                                               user_pages[data_page_index],
 476                                               data_page_offset,
 477                                               page_length,
 478                                               1);
 479                 } else {
 480                         slow_shmem_copy(user_pages[data_page_index],
 481                                         data_page_offset,
 482                                         page,
 483                                         shmem_page_offset,
 484                                         page_length);
 485                 }
 486
 487                 mark_page_accessed(page);
 488                 page_cache_release(page);
 489
 490                 remain -= page_length;
 491                 data_ptr += page_length;
 492                 offset += page_length;
 493         }
 494
 495 out:
 496         for (i = 0; i < pinned_pages; i++) {
 497                 SetPageDirty(user_pages[i]);
 498                 mark_page_accessed(user_pages[i]);
 499                 page_cache_release(user_pages[i]);
 500         }
 501         drm_free_large(user_pages);
 502
 503         return ret;
 504 }
 505
 506 /**
 507  * Reads data from the object referenced by handle.
 508  *
 509  * On error, the contents of *data are undefined.
 510  */
 511 int
 512 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 513                      struct drm_file *file)
 514 {
 515         struct drm_i915_gem_pread *args = data;
 516         struct drm_i915_gem_object *obj;
 517         int ret = 0;
 518
 519         if (args->size == 0)
 520                 return 0;
 521
 522         if (!access_ok(VERIFY_WRITE,
 523                        (char __user *)(uintptr_t)args->data_ptr,
 524                        args->size))
 525                 return -EFAULT;
 526
 527         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 528                                        args->size);
 529         if (ret)
 530                 return -EFAULT;
 531
 532         ret = i915_mutex_lock_interruptible(dev);
 533         if (ret)
 534                 return ret;
 535
 536         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 537         if (&obj->base == NULL) {
 538                 ret = -ENOENT;
 539                 goto unlock;
 540         }
 541
 542         /* Bounds check source.  */
 543         if (args->offset > obj->base.size ||
 544             args->size > obj->base.size - args->offset) {
 545                 ret = -EINVAL;
 546                 goto out;
 547         }
 548
 549         trace_i915_gem_object_pread(obj, args->offset, args->size);
 550
 551         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 552                                                         args->offset,
 553                                                         args->size);
 554         if (ret)
 555                 goto out;
 556
 557         ret = -EFAULT;
 558         if (!i915_gem_object_needs_bit17_swizzle(obj))
 559                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 560         if (ret == -EFAULT)
 561                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 562
 563 out:
 564         drm_gem_object_unreference(&obj->base);
 565 unlock:
 566         mutex_unlock(&dev->struct_mutex);
 567         return ret;
 568 }
 569
 570 /* This is the fast write path which cannot handle
 571  * page faults in the source data
 572  */
 573
 574 static inline int
 575 fast_user_write(struct io_mapping *mapping,
 576                 loff_t page_base, int page_offset,
 577                 char __user *user_data,
 578                 int length)
 579 {
 580         char *vaddr_atomic;
 581         unsigned long unwritten;
 582
 583         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 584         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 585                                                       user_data, length);
 586         io_mapping_unmap_atomic(vaddr_atomic);
 587         return unwritten;
 588 }
 589
 590 /* Here's the write path which can sleep for
 591  * page faults
 592  */
 593
 594 static inline void
 595 slow_kernel_write(struct io_mapping *mapping,
 596                   loff_t gtt_base, int gtt_offset,
 597                   struct page *user_page, int user_offset,
 598                   int length)
 599 {
 600         char __iomem *dst_vaddr;
 601         char *src_vaddr;
 602
 603         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 604         src_vaddr = kmap(user_page);
 605
 606         memcpy_toio(dst_vaddr + gtt_offset,
 607                     src_vaddr + user_offset,
 608                     length);
 609
 610         kunmap(user_page);
 611         io_mapping_unmap(dst_vaddr);
 612 }
 613
 614 /**
 615  * This is the fast pwrite path, where we copy the data directly from the
 616  * user into the GTT, uncached.
 617  */
 618 static int
 619 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 620                          struct drm_i915_gem_object *obj,
 621                          struct drm_i915_gem_pwrite *args,
 622                          struct drm_file *file)
 623 {
 624         drm_i915_private_t *dev_priv = dev->dev_private;
 625         ssize_t remain;
 626         loff_t offset, page_base;
 627         char __user *user_data;
 628         int page_offset, page_length;
 629
 630         user_data = (char __user *) (uintptr_t) args->data_ptr;
 631         remain = args->size;
 632
 633         offset = obj->gtt_offset + args->offset;
 634
 635         while (remain > 0) {
 636                 /* Operation in this page
 637                  *
 638                  * page_base = page offset within aperture
 639                  * page_offset = offset within page
 640                  * page_length = bytes to copy for this page
 641                  */
 642                 page_base = offset & PAGE_MASK;
 643                 page_offset = offset_in_page(offset);
 644                 page_length = remain;
 645                 if ((page_offset + remain) > PAGE_SIZE)
 646                         page_length = PAGE_SIZE - page_offset;
 647
 648                 /* If we get a fault while copying data, then (presumably) our
 649                  * source page isn't available.  Return the error and we'll
 650                  * retry in the slow path.
 651                  */
 652                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 653                                     page_offset, user_data, page_length))
 654                         return -EFAULT;
 655
 656                 remain -= page_length;
 657                 user_data += page_length;
 658                 offset += page_length;
 659         }
 660
 661         return 0;
 662 }
 663
 664 /**
 665  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 666  * the memory and maps it using kmap_atomic for copying.
 667  *
 668  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 669  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 670  */
 671 static int
 672 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 673                          struct drm_i915_gem_object *obj,
 674                          struct drm_i915_gem_pwrite *args,
 675                          struct drm_file *file)
 676 {
 677         drm_i915_private_t *dev_priv = dev->dev_private;
 678         ssize_t remain;
 679         loff_t gtt_page_base, offset;
 680         loff_t first_data_page, last_data_page, num_pages;
 681         loff_t pinned_pages, i;
 682         struct page **user_pages;
 683         struct mm_struct *mm = current->mm;
 684         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 685         int ret;
 686         uint64_t data_ptr = args->data_ptr;
 687
 688         remain = args->size;
 689
 690         /* Pin the user pages containing the data.  We can't fault while
 691          * holding the struct mutex, and all of the pwrite implementations
 692          * want to hold it while dereferencing the user data.
 693          */
 694         first_data_page = data_ptr / PAGE_SIZE;
 695         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 696         num_pages = last_data_page - first_data_page + 1;
 697
 698         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 699         if (user_pages == NULL)
 700                 return -ENOMEM;
 701
 702         mutex_unlock(&dev->struct_mutex);
 703         down_read(&mm->mmap_sem);
 704         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 705                                       num_pages, 0, 0, user_pages, NULL);
 706         up_read(&mm->mmap_sem);
 707         mutex_lock(&dev->struct_mutex);
 708         if (pinned_pages < num_pages) {
 709                 ret = -EFAULT;
 710                 goto out_unpin_pages;
 711         }
 712
 713         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 714         if (ret)
 715                 goto out_unpin_pages;
 716
 717         ret = i915_gem_object_put_fence(obj);
 718         if (ret)
 719                 goto out_unpin_pages;
 720
 721         offset = obj->gtt_offset + args->offset;
 722
 723         while (remain > 0) {
 724                 /* Operation in this page
 725                  *
 726                  * gtt_page_base = page offset within aperture
 727                  * gtt_page_offset = offset within page in aperture
 728                  * data_page_index = page number in get_user_pages return
 729                  * data_page_offset = offset with data_page_index page.
 730                  * page_length = bytes to copy for this page
 731                  */
 732                 gtt_page_base = offset & PAGE_MASK;
 733                 gtt_page_offset = offset_in_page(offset);
 734                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 735                 data_page_offset = offset_in_page(data_ptr);
 736
 737                 page_length = remain;
 738                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 739                         page_length = PAGE_SIZE - gtt_page_offset;
 740                 if ((data_page_offset + page_length) > PAGE_SIZE)
 741                         page_length = PAGE_SIZE - data_page_offset;
 742
 743                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 744                                   gtt_page_base, gtt_page_offset,
 745                                   user_pages[data_page_index],
 746                                   data_page_offset,
 747                                   page_length);
 748
 749                 remain -= page_length;
 750                 offset += page_length;
 751                 data_ptr += page_length;
 752         }
 753
 754 out_unpin_pages:
 755         for (i = 0; i < pinned_pages; i++)
 756                 page_cache_release(user_pages[i]);
 757         drm_free_large(user_pages);
 758
 759         return ret;
 760 }
 761
 762 /**
 763  * This is the fast shmem pwrite path, which attempts to directly
 764  * copy_from_user into the kmapped pages backing the object.
 765  */
 766 static int
 767 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 768                            struct drm_i915_gem_object *obj,
 769                            struct drm_i915_gem_pwrite *args,
 770                            struct drm_file *file)
 771 {
 772         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 773         ssize_t remain;
 774         loff_t offset;
 775         char __user *user_data;
 776         int page_offset, page_length;
 777
 778         user_data = (char __user *) (uintptr_t) args->data_ptr;
 779         remain = args->size;
 780
 781         offset = args->offset;
 782         obj->dirty = 1;
 783
 784         while (remain > 0) {
 785                 struct page *page;
 786                 char *vaddr;
 787                 int ret;
 788
 789                 /* Operation in this page
 790                  *
 791                  * page_offset = offset within page
 792                  * page_length = bytes to copy for this page
 793                  */
 794                 page_offset = offset_in_page(offset);
 795                 page_length = remain;
 796                 if ((page_offset + remain) > PAGE_SIZE)
 797                         page_length = PAGE_SIZE - page_offset;
 798
 799                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 800                 if (IS_ERR(page))
 801                         return PTR_ERR(page);
 802
 803                 vaddr = kmap_atomic(page, KM_USER0);
 804                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 805                                                 user_data,
 806                                                 page_length);
 807                 kunmap_atomic(vaddr, KM_USER0);
 808
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811                 page_cache_release(page);
 812
 813                 /* If we get a fault while copying data, then (presumably) our
 814                  * source page isn't available.  Return the error and we'll
 815                  * retry in the slow path.
 816                  */
 817                 if (ret)
 818                         return -EFAULT;
 819
 820                 remain -= page_length;
 821                 user_data += page_length;
 822                 offset += page_length;
 823         }
 824
 825         return 0;
 826 }
 827
 828 /**
 829  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 830  * the memory and maps it using kmap_atomic for copying.
 831  *
 832  * This avoids taking mmap_sem for faulting on the user's address while the
 833  * struct_mutex is held.
 834  */
 835 static int
 836 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 837                            struct drm_i915_gem_object *obj,
 838                            struct drm_i915_gem_pwrite *args,
 839                            struct drm_file *file)
 840 {
 841         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 842         struct mm_struct *mm = current->mm;
 843         struct page **user_pages;
 844         ssize_t remain;
 845         loff_t offset, pinned_pages, i;
 846         loff_t first_data_page, last_data_page, num_pages;
 847         int shmem_page_offset;
 848         int data_page_index,  data_page_offset;
 849         int page_length;
 850         int ret;
 851         uint64_t data_ptr = args->data_ptr;
 852         int do_bit17_swizzling;
 853
 854         remain = args->size;
 855
 856         /* Pin the user pages containing the data.  We can't fault while
 857          * holding the struct mutex, and all of the pwrite implementations
 858          * want to hold it while dereferencing the user data.
 859          */
 860         first_data_page = data_ptr / PAGE_SIZE;
 861         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 862         num_pages = last_data_page - first_data_page + 1;
 863
 864         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 865         if (user_pages == NULL)
 866                 return -ENOMEM;
 867
 868         mutex_unlock(&dev->struct_mutex);
 869         down_read(&mm->mmap_sem);
 870         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 871                                       num_pages, 0, 0, user_pages, NULL);
 872         up_read(&mm->mmap_sem);
 873         mutex_lock(&dev->struct_mutex);
 874         if (pinned_pages < num_pages) {
 875                 ret = -EFAULT;
 876                 goto out;
 877         }
 878
 879         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 880         if (ret)
 881                 goto out;
 882
 883         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         offset = args->offset;
 886         obj->dirty = 1;
 887
 888         while (remain > 0) {
 889                 struct page *page;
 890
 891                 /* Operation in this page
 892                  *
 893                  * shmem_page_offset = offset within page in shmem file
 894                  * data_page_index = page number in get_user_pages return
 895                  * data_page_offset = offset with data_page_index page.
 896                  * page_length = bytes to copy for this page
 897                  */
 898                 shmem_page_offset = offset_in_page(offset);
 899                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 900                 data_page_offset = offset_in_page(data_ptr);
 901
 902                 page_length = remain;
 903                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 904                         page_length = PAGE_SIZE - shmem_page_offset;
 905                 if ((data_page_offset + page_length) > PAGE_SIZE)
 906                         page_length = PAGE_SIZE - data_page_offset;
 907
 908                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 909                 if (IS_ERR(page)) {
 910                         ret = PTR_ERR(page);
 911                         goto out;
 912                 }
 913
 914                 if (do_bit17_swizzling) {
 915                         slow_shmem_bit17_copy(page,
 916                                               shmem_page_offset,
 917                                               user_pages[data_page_index],
 918                                               data_page_offset,
 919                                               page_length,
 920                                               0);
 921                 } else {
 922                         slow_shmem_copy(page,
 923                                         shmem_page_offset,
 924                                         user_pages[data_page_index],
 925                                         data_page_offset,
 926                                         page_length);
 927                 }
 928
 929                 set_page_dirty(page);
 930                 mark_page_accessed(page);
 931                 page_cache_release(page);
 932
 933                 remain -= page_length;
 934                 data_ptr += page_length;
 935                 offset += page_length;
 936         }
 937
 938 out:
 939         for (i = 0; i < pinned_pages; i++)
 940                 page_cache_release(user_pages[i]);
 941         drm_free_large(user_pages);
 942
 943         return ret;
 944 }
 945
 946 /**
 947  * Writes data to the object referenced by handle.
 948  *
 949  * On error, the contents of the buffer that were to be modified are undefined.
 950  */
 951 int
 952 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 953                       struct drm_file *file)
 954 {
 955         struct drm_i915_gem_pwrite *args = data;
 956         struct drm_i915_gem_object *obj;
 957         int ret;
 958
 959         if (args->size == 0)
 960                 return 0;
 961
 962         if (!access_ok(VERIFY_READ,
 963                        (char __user *)(uintptr_t)args->data_ptr,
 964                        args->size))
 965                 return -EFAULT;
 966
 967         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 968                                       args->size);
 969         if (ret)
 970                 return -EFAULT;
 971
 972         ret = i915_mutex_lock_interruptible(dev);
 973         if (ret)
 974                 return ret;
 975
 976         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 977         if (&obj->base == NULL) {
 978                 ret = -ENOENT;
 979                 goto unlock;
 980         }
 981
 982         /* Bounds check destination. */
 983         if (args->offset > obj->base.size ||
 984             args->size > obj->base.size - args->offset) {
 985                 ret = -EINVAL;
 986                 goto out;
 987         }
 988
 989         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 990
 991         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 992          * it would end up going through the fenced access, and we'll get
 993          * different detiling behavior between reading and writing.
 994          * pread/pwrite currently are reading and writing from the CPU
 995          * perspective, requiring manual detiling by the client.
 996          */
 997         if (obj->phys_obj)
 998                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 999         else if (obj->gtt_space &&
1000                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1001                 ret = i915_gem_object_pin(obj, 0, true);
1002                 if (ret)
1003                         goto out;
1004
1005                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1006                 if (ret)
1007                         goto out_unpin;
1008
1009                 ret = i915_gem_object_put_fence(obj);
1010                 if (ret)
1011                         goto out_unpin;
1012
1013                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1014                 if (ret == -EFAULT)
1015                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1016
1017 out_unpin:
1018                 i915_gem_object_unpin(obj);
1019         } else {
1020                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1021                 if (ret)
1022                         goto out;
1023
1024                 ret = -EFAULT;
1025                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1026                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1027                 if (ret == -EFAULT)
1028                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1029         }
1030
1031 out:
1032         drm_gem_object_unreference(&obj->base);
1033 unlock:
1034         mutex_unlock(&dev->struct_mutex);
1035         return ret;
1036 }
1037
1038 /**
1039  * Called when user space prepares to use an object with the CPU, either
1040  * through the mmap ioctl's mapping or a GTT mapping.
1041  */
1042 int
1043 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1044                           struct drm_file *file)
1045 {
1046         struct drm_i915_gem_set_domain *args = data;
1047         struct drm_i915_gem_object *obj;
1048         uint32_t read_domains = args->read_domains;
1049         uint32_t write_domain = args->write_domain;
1050         int ret;
1051
1052         if (!(dev->driver->driver_features & DRIVER_GEM))
1053                 return -ENODEV;
1054
1055         /* Only handle setting domains to types used by the CPU. */
1056         if (write_domain & I915_GEM_GPU_DOMAINS)
1057                 return -EINVAL;
1058
1059         if (read_domains & I915_GEM_GPU_DOMAINS)
1060                 return -EINVAL;
1061
1062         /* Having something in the write domain implies it's in the read
1063          * domain, and only that read domain.  Enforce that in the request.
1064          */
1065         if (write_domain != 0 && read_domains != write_domain)
1066                 return -EINVAL;
1067
1068         ret = i915_mutex_lock_interruptible(dev);
1069         if (ret)
1070                 return ret;
1071
1072         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1073         if (&obj->base == NULL) {
1074                 ret = -ENOENT;
1075                 goto unlock;
1076         }
1077
1078         if (read_domains & I915_GEM_DOMAIN_GTT) {
1079                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1080
1081                 /* Silently promote "you're not bound, there was nothing to do"
1082                  * to success, since the client was just asking us to
1083                  * make sure everything was done.
1084                  */
1085                 if (ret == -EINVAL)
1086                         ret = 0;
1087         } else {
1088                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1089         }
1090
1091         drm_gem_object_unreference(&obj->base);
1092 unlock:
1093         mutex_unlock(&dev->struct_mutex);
1094         return ret;
1095 }
1096
1097 /**
1098  * Called when user space has done writes to this buffer
1099  */
1100 int
1101 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1102                          struct drm_file *file)
1103 {
1104         struct drm_i915_gem_sw_finish *args = data;
1105         struct drm_i915_gem_object *obj;
1106         int ret = 0;
1107
1108         if (!(dev->driver->driver_features & DRIVER_GEM))
1109                 return -ENODEV;
1110
1111         ret = i915_mutex_lock_interruptible(dev);
1112         if (ret)
1113                 return ret;
1114
1115         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1116         if (&obj->base == NULL) {
1117                 ret = -ENOENT;
1118                 goto unlock;
1119         }
1120
1121         /* Pinned buffers may be scanout, so flush the cache */
1122         if (obj->pin_count)
1123                 i915_gem_object_flush_cpu_write_domain(obj);
1124
1125         drm_gem_object_unreference(&obj->base);
1126 unlock:
1127         mutex_unlock(&dev->struct_mutex);
1128         return ret;
1129 }
1130
1131 /**
1132  * Maps the contents of an object, returning the address it is mapped
1133  * into.
1134  *
1135  * While the mapping holds a reference on the contents of the object, it doesn't
1136  * imply a ref on the object itself.
1137  */
1138 int
1139 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1140                     struct drm_file *file)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143         struct drm_i915_gem_mmap *args = data;
1144         struct drm_gem_object *obj;
1145         unsigned long addr;
1146
1147         if (!(dev->driver->driver_features & DRIVER_GEM))
1148                 return -ENODEV;
1149
1150         obj = drm_gem_object_lookup(dev, file, args->handle);
1151         if (obj == NULL)
1152                 return -ENOENT;
1153
1154         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1155                 drm_gem_object_unreference_unlocked(obj);
1156                 return -E2BIG;
1157         }
1158
1159         down_write(&current->mm->mmap_sem);
1160         addr = do_mmap(obj->filp, 0, args->size,
1161                        PROT_READ | PROT_WRITE, MAP_SHARED,
1162                        args->offset);
1163         up_write(&current->mm->mmap_sem);
1164         drm_gem_object_unreference_unlocked(obj);
1165         if (IS_ERR((void *)addr))
1166                 return addr;
1167
1168         args->addr_ptr = (uint64_t) addr;
1169
1170         return 0;
1171 }
1172
1173 /**
1174  * i915_gem_fault - fault a page into the GTT
1175  * vma: VMA in question
1176  * vmf: fault info
1177  *
1178  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1179  * from userspace.  The fault handler takes care of binding the object to
1180  * the GTT (if needed), allocating and programming a fence register (again,
1181  * only if needed based on whether the old reg is still valid or the object
1182  * is tiled) and inserting a new PTE into the faulting process.
1183  *
1184  * Note that the faulting process may involve evicting existing objects
1185  * from the GTT and/or fence registers to make room.  So performance may
1186  * suffer if the GTT working set is large or there are few fence registers
1187  * left.
1188  */
1189 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1190 {
1191         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1192         struct drm_device *dev = obj->base.dev;
1193         drm_i915_private_t *dev_priv = dev->dev_private;
1194         pgoff_t page_offset;
1195         unsigned long pfn;
1196         int ret = 0;
1197         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1198
1199         /* We don't use vmf->pgoff since that has the fake offset */
1200         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1201                 PAGE_SHIFT;
1202
1203         ret = i915_mutex_lock_interruptible(dev);
1204         if (ret)
1205                 goto out;
1206
1207         trace_i915_gem_object_fault(obj, page_offset, true, write);
1208
1209         /* Now bind it into the GTT if needed */
1210         if (!obj->map_and_fenceable) {
1211                 ret = i915_gem_object_unbind(obj);
1212                 if (ret)
1213                         goto unlock;
1214         }
1215         if (!obj->gtt_space) {
1216                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1217                 if (ret)
1218                         goto unlock;
1219
1220                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1221                 if (ret)
1222                         goto unlock;
1223         }
1224
1225         if (obj->tiling_mode == I915_TILING_NONE)
1226                 ret = i915_gem_object_put_fence(obj);
1227         else
1228                 ret = i915_gem_object_get_fence(obj, NULL);
1229         if (ret)
1230                 goto unlock;
1231
1232         if (i915_gem_object_is_inactive(obj))
1233                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1234
1235         obj->fault_mappable = true;
1236
1237         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1238                 page_offset;
1239
1240         /* Finally, remap it using the new GTT offset */
1241         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1242 unlock:
1243         mutex_unlock(&dev->struct_mutex);
1244 out:
1245         switch (ret) {
1246         case -EIO:
1247         case -EAGAIN:
1248                 /* Give the error handler a chance to run and move the
1249                  * objects off the GPU active list. Next time we service the
1250                  * fault, we should be able to transition the page into the
1251                  * GTT without touching the GPU (and so avoid further
1252                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1253                  * with coherency, just lost writes.
1254                  */
1255                 set_need_resched();
1256         case 0:
1257         case -ERESTARTSYS:
1258         case -EINTR:
1259                 return VM_FAULT_NOPAGE;
1260         case -ENOMEM:
1261                 return VM_FAULT_OOM;
1262         default:
1263                 return VM_FAULT_SIGBUS;
1264         }
1265 }
1266
1267 /**
1268  * i915_gem_release_mmap - remove physical page mappings
1269  * @obj: obj in question
1270  *
1271  * Preserve the reservation of the mmapping with the DRM core code, but
1272  * relinquish ownership of the pages back to the system.
1273  *
1274  * It is vital that we remove the page mapping if we have mapped a tiled
1275  * object through the GTT and then lose the fence register due to
1276  * resource pressure. Similarly if the object has been moved out of the
1277  * aperture, than pages mapped into userspace must be revoked. Removing the
1278  * mapping will then trigger a page fault on the next user access, allowing
1279  * fixup by i915_gem_fault().
1280  */
1281 void
1282 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1283 {
1284         if (!obj->fault_mappable)
1285                 return;
1286
1287         if (obj->base.dev->dev_mapping)
1288                 unmap_mapping_range(obj->base.dev->dev_mapping,
1289                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1290                                     obj->base.size, 1);
1291
1292         obj->fault_mappable = false;
1293 }
1294
1295 static uint32_t
1296 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1297 {
1298         uint32_t gtt_size;
1299
1300         if (INTEL_INFO(dev)->gen >= 4 ||
1301             tiling_mode == I915_TILING_NONE)
1302                 return size;
1303
1304         /* Previous chips need a power-of-two fence region when tiling */
1305         if (INTEL_INFO(dev)->gen == 3)
1306                 gtt_size = 1024*1024;
1307         else
1308                 gtt_size = 512*1024;
1309
1310         while (gtt_size < size)
1311                 gtt_size <<= 1;
1312
1313         return gtt_size;
1314 }
1315
1316 /**
1317  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1318  * @obj: object to check
1319  *
1320  * Return the required GTT alignment for an object, taking into account
1321  * potential fence register mapping.
1322  */
1323 static uint32_t
1324 i915_gem_get_gtt_alignment(struct drm_device *dev,
1325                            uint32_t size,
1326                            int tiling_mode)
1327 {
1328         /*
1329          * Minimum alignment is 4k (GTT page size), but might be greater
1330          * if a fence register is needed for the object.
1331          */
1332         if (INTEL_INFO(dev)->gen >= 4 ||
1333             tiling_mode == I915_TILING_NONE)
1334                 return 4096;
1335
1336         /*
1337          * Previous chips need to be aligned to the size of the smallest
1338          * fence register that can contain the object.
1339          */
1340         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1341 }
1342
1343 /**
1344  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1345  *                                       unfenced object
1346  * @dev: the device
1347  * @size: size of the object
1348  * @tiling_mode: tiling mode of the object
1349  *
1350  * Return the required GTT alignment for an object, only taking into account
1351  * unfenced tiled surface requirements.
1352  */
1353 uint32_t
1354 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1355                                     uint32_t size,
1356                                     int tiling_mode)
1357 {
1358         /*
1359          * Minimum alignment is 4k (GTT page size) for sane hw.
1360          */
1361         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1362             tiling_mode == I915_TILING_NONE)
1363                 return 4096;
1364
1365         /* Previous hardware however needs to be aligned to a power-of-two
1366          * tile height. The simplest method for determining this is to reuse
1367          * the power-of-tile object size.
1368          */
1369         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1370 }
1371
1372 int
1373 i915_gem_mmap_gtt(struct drm_file *file,
1374                   struct drm_device *dev,
1375                   uint32_t handle,
1376                   uint64_t *offset)
1377 {
1378         struct drm_i915_private *dev_priv = dev->dev_private;
1379         struct drm_i915_gem_object *obj;
1380         int ret;
1381
1382         if (!(dev->driver->driver_features & DRIVER_GEM))
1383                 return -ENODEV;
1384
1385         ret = i915_mutex_lock_interruptible(dev);
1386         if (ret)
1387                 return ret;
1388
1389         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1390         if (&obj->base == NULL) {
1391                 ret = -ENOENT;
1392                 goto unlock;
1393         }
1394
1395         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1396                 ret = -E2BIG;
1397                 goto unlock;
1398         }
1399
1400         if (obj->madv != I915_MADV_WILLNEED) {
1401                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1402                 ret = -EINVAL;
1403                 goto out;
1404         }
1405
1406         if (!obj->base.map_list.map) {
1407                 ret = drm_gem_create_mmap_offset(&obj->base);
1408                 if (ret)
1409                         goto out;
1410         }
1411
1412         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1413
1414 out:
1415         drm_gem_object_unreference(&obj->base);
1416 unlock:
1417         mutex_unlock(&dev->struct_mutex);
1418         return ret;
1419 }
1420
1421 /**
1422  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1423  * @dev: DRM device
1424  * @data: GTT mapping ioctl data
1425  * @file: GEM object info
1426  *
1427  * Simply returns the fake offset to userspace so it can mmap it.
1428  * The mmap call will end up in drm_gem_mmap(), which will set things
1429  * up so we can get faults in the handler above.
1430  *
1431  * The fault handler will take care of binding the object into the GTT
1432  * (since it may have been evicted to make room for something), allocating
1433  * a fence register, and mapping the appropriate aperture address into
1434  * userspace.
1435  */
1436 int
1437 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1438                         struct drm_file *file)
1439 {
1440         struct drm_i915_gem_mmap_gtt *args = data;
1441
1442         if (!(dev->driver->driver_features & DRIVER_GEM))
1443                 return -ENODEV;
1444
1445         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1446 }
1447
1448
1449 static int
1450 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1451                               gfp_t gfpmask)
1452 {
1453         int page_count, i;
1454         struct address_space *mapping;
1455         struct inode *inode;
1456         struct page *page;
1457
1458         /* Get the list of pages out of our struct file.  They'll be pinned
1459          * at this point until we release them.
1460          */
1461         page_count = obj->base.size / PAGE_SIZE;
1462         BUG_ON(obj->pages != NULL);
1463         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1464         if (obj->pages == NULL)
1465                 return -ENOMEM;
1466
1467         inode = obj->base.filp->f_path.dentry->d_inode;
1468         mapping = inode->i_mapping;
1469         gfpmask |= mapping_gfp_mask(mapping);
1470
1471         for (i = 0; i < page_count; i++) {
1472                 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1473                 if (IS_ERR(page))
1474                         goto err_pages;
1475
1476                 obj->pages[i] = page;
1477         }
1478
1479         if (obj->tiling_mode != I915_TILING_NONE)
1480                 i915_gem_object_do_bit_17_swizzle(obj);
1481
1482         return 0;
1483
1484 err_pages:
1485         while (i--)
1486                 page_cache_release(obj->pages[i]);
1487
1488         drm_free_large(obj->pages);
1489         obj->pages = NULL;
1490         return PTR_ERR(page);
1491 }
1492
1493 static void
1494 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1495 {
1496         int page_count = obj->base.size / PAGE_SIZE;
1497         int i;
1498
1499         BUG_ON(obj->madv == __I915_MADV_PURGED);
1500
1501         if (obj->tiling_mode != I915_TILING_NONE)
1502                 i915_gem_object_save_bit_17_swizzle(obj);
1503
1504         if (obj->madv == I915_MADV_DONTNEED)
1505                 obj->dirty = 0;
1506
1507         for (i = 0; i < page_count; i++) {
1508                 if (obj->dirty)
1509                         set_page_dirty(obj->pages[i]);
1510
1511                 if (obj->madv == I915_MADV_WILLNEED)
1512                         mark_page_accessed(obj->pages[i]);
1513
1514                 page_cache_release(obj->pages[i]);
1515         }
1516         obj->dirty = 0;
1517
1518         drm_free_large(obj->pages);
1519         obj->pages = NULL;
1520 }
1521
1522 void
1523 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1524                                struct intel_ring_buffer *ring,
1525                                u32 seqno)
1526 {
1527         struct drm_device *dev = obj->base.dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530         BUG_ON(ring == NULL);
1531         obj->ring = ring;
1532
1533         /* Add a reference if we're newly entering the active list. */
1534         if (!obj->active) {
1535                 drm_gem_object_reference(&obj->base);
1536                 obj->active = 1;
1537         }
1538
1539         /* Move from whatever list we were on to the tail of execution. */
1540         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1541         list_move_tail(&obj->ring_list, &ring->active_list);
1542
1543         obj->last_rendering_seqno = seqno;
1544         if (obj->fenced_gpu_access) {
1545                 struct drm_i915_fence_reg *reg;
1546
1547                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1548
1549                 obj->last_fenced_seqno = seqno;
1550                 obj->last_fenced_ring = ring;
1551
1552                 reg = &dev_priv->fence_regs[obj->fence_reg];
1553                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1554         }
1555 }
1556
1557 static void
1558 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1559 {
1560         list_del_init(&obj->ring_list);
1561         obj->last_rendering_seqno = 0;
1562 }
1563
1564 static void
1565 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1566 {
1567         struct drm_device *dev = obj->base.dev;
1568         drm_i915_private_t *dev_priv = dev->dev_private;
1569
1570         BUG_ON(!obj->active);
1571         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1572
1573         i915_gem_object_move_off_active(obj);
1574 }
1575
1576 static void
1577 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1578 {
1579         struct drm_device *dev = obj->base.dev;
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582         if (obj->pin_count != 0)
1583                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1584         else
1585                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1586
1587         BUG_ON(!list_empty(&obj->gpu_write_list));
1588         BUG_ON(!obj->active);
1589         obj->ring = NULL;
1590
1591         i915_gem_object_move_off_active(obj);
1592         obj->fenced_gpu_access = false;
1593
1594         obj->active = 0;
1595         obj->pending_gpu_write = false;
1596         drm_gem_object_unreference(&obj->base);
1597
1598         WARN_ON(i915_verify_lists(dev));
1599 }
1600
1601 /* Immediately discard the backing storage */
1602 static void
1603 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1604 {
1605         struct inode *inode;
1606
1607         /* Our goal here is to return as much of the memory as
1608          * is possible back to the system as we are called from OOM.
1609          * To do this we must instruct the shmfs to drop all of its
1610          * backing pages, *now*.
1611          */
1612         inode = obj->base.filp->f_path.dentry->d_inode;
1613         shmem_truncate_range(inode, 0, (loff_t)-1);
1614
1615         obj->madv = __I915_MADV_PURGED;
1616 }
1617
1618 static inline int
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1620 {
1621         return obj->madv == I915_MADV_DONTNEED;
1622 }
1623
1624 static void
1625 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1626                                uint32_t flush_domains)
1627 {
1628         struct drm_i915_gem_object *obj, *next;
1629
1630         list_for_each_entry_safe(obj, next,
1631                                  &ring->gpu_write_list,
1632                                  gpu_write_list) {
1633                 if (obj->base.write_domain & flush_domains) {
1634                         uint32_t old_write_domain = obj->base.write_domain;
1635
1636                         obj->base.write_domain = 0;
1637                         list_del_init(&obj->gpu_write_list);
1638                         i915_gem_object_move_to_active(obj, ring,
1639                                                        i915_gem_next_request_seqno(ring));
1640
1641                         trace_i915_gem_object_change_domain(obj,
1642                                                             obj->base.read_domains,
1643                                                             old_write_domain);
1644                 }
1645         }
1646 }
1647
1648 int
1649 i915_add_request(struct intel_ring_buffer *ring,
1650                  struct drm_file *file,
1651                  struct drm_i915_gem_request *request)
1652 {
1653         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1654         uint32_t seqno;
1655         int was_empty;
1656         int ret;
1657
1658         BUG_ON(request == NULL);
1659
1660         ret = ring->add_request(ring, &seqno);
1661         if (ret)
1662             return ret;
1663
1664         trace_i915_gem_request_add(ring, seqno);
1665
1666         request->seqno = seqno;
1667         request->ring = ring;
1668         request->emitted_jiffies = jiffies;
1669         was_empty = list_empty(&ring->request_list);
1670         list_add_tail(&request->list, &ring->request_list);
1671
1672         if (file) {
1673                 struct drm_i915_file_private *file_priv = file->driver_priv;
1674
1675                 spin_lock(&file_priv->mm.lock);
1676                 request->file_priv = file_priv;
1677                 list_add_tail(&request->client_list,
1678                               &file_priv->mm.request_list);
1679                 spin_unlock(&file_priv->mm.lock);
1680         }
1681
1682         ring->outstanding_lazy_request = false;
1683
1684         if (!dev_priv->mm.suspended) {
1685                 if (i915_enable_hangcheck) {
1686                         mod_timer(&dev_priv->hangcheck_timer,
1687                                   jiffies +
1688                                   msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1689                 }
1690                 if (was_empty)
1691                         queue_delayed_work(dev_priv->wq,
1692                                            &dev_priv->mm.retire_work, HZ);
1693         }
1694         return 0;
1695 }
1696
1697 static inline void
1698 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1699 {
1700         struct drm_i915_file_private *file_priv = request->file_priv;
1701
1702         if (!file_priv)
1703                 return;
1704
1705         spin_lock(&file_priv->mm.lock);
1706         if (request->file_priv) {
1707                 list_del(&request->client_list);
1708                 request->file_priv = NULL;
1709         }
1710         spin_unlock(&file_priv->mm.lock);
1711 }
1712
1713 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1714                                       struct intel_ring_buffer *ring)
1715 {
1716         while (!list_empty(&ring->request_list)) {
1717                 struct drm_i915_gem_request *request;
1718
1719                 request = list_first_entry(&ring->request_list,
1720                                            struct drm_i915_gem_request,
1721                                            list);
1722
1723                 list_del(&request->list);
1724                 i915_gem_request_remove_from_client(request);
1725                 kfree(request);
1726         }
1727
1728         while (!list_empty(&ring->active_list)) {
1729                 struct drm_i915_gem_object *obj;
1730
1731                 obj = list_first_entry(&ring->active_list,
1732                                        struct drm_i915_gem_object,
1733                                        ring_list);
1734
1735                 obj->base.write_domain = 0;
1736                 list_del_init(&obj->gpu_write_list);
1737                 i915_gem_object_move_to_inactive(obj);
1738         }
1739 }
1740
1741 static void i915_gem_reset_fences(struct drm_device *dev)
1742 {
1743         struct drm_i915_private *dev_priv = dev->dev_private;
1744         int i;
1745
1746         for (i = 0; i < 16; i++) {
1747                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1748                 struct drm_i915_gem_object *obj = reg->obj;
1749
1750                 if (!obj)
1751                         continue;
1752
1753                 if (obj->tiling_mode)
1754                         i915_gem_release_mmap(obj);
1755
1756                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1757                 reg->obj->fenced_gpu_access = false;
1758                 reg->obj->last_fenced_seqno = 0;
1759                 reg->obj->last_fenced_ring = NULL;
1760                 i915_gem_clear_fence_reg(dev, reg);
1761         }
1762 }
1763
1764 void i915_gem_reset(struct drm_device *dev)
1765 {
1766         struct drm_i915_private *dev_priv = dev->dev_private;
1767         struct drm_i915_gem_object *obj;
1768         int i;
1769
1770         for (i = 0; i < I915_NUM_RINGS; i++)
1771                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1772
1773         /* Remove anything from the flushing lists. The GPU cache is likely
1774          * to be lost on reset along with the data, so simply move the
1775          * lost bo to the inactive list.
1776          */
1777         while (!list_empty(&dev_priv->mm.flushing_list)) {
1778                 obj = list_first_entry(&dev_priv->mm.flushing_list,
1779                                       struct drm_i915_gem_object,
1780                                       mm_list);
1781
1782                 obj->base.write_domain = 0;
1783                 list_del_init(&obj->gpu_write_list);
1784                 i915_gem_object_move_to_inactive(obj);
1785         }
1786
1787         /* Move everything out of the GPU domains to ensure we do any
1788          * necessary invalidation upon reuse.
1789          */
1790         list_for_each_entry(obj,
1791                             &dev_priv->mm.inactive_list,
1792                             mm_list)
1793         {
1794                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1795         }
1796
1797         /* The fence registers are invalidated so clear them out */
1798         i915_gem_reset_fences(dev);
1799 }
1800
1801 /**
1802  * This function clears the request list as sequence numbers are passed.
1803  */
1804 static void
1805 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1806 {
1807         uint32_t seqno;
1808         int i;
1809
1810         if (list_empty(&ring->request_list))
1811                 return;
1812
1813         WARN_ON(i915_verify_lists(ring->dev));
1814
1815         seqno = ring->get_seqno(ring);
1816
1817         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1818                 if (seqno >= ring->sync_seqno[i])
1819                         ring->sync_seqno[i] = 0;
1820
1821         while (!list_empty(&ring->request_list)) {
1822                 struct drm_i915_gem_request *request;
1823
1824                 request = list_first_entry(&ring->request_list,
1825                                            struct drm_i915_gem_request,
1826                                            list);
1827
1828                 if (!i915_seqno_passed(seqno, request->seqno))
1829                         break;
1830
1831                 trace_i915_gem_request_retire(ring, request->seqno);
1832
1833                 list_del(&request->list);
1834                 i915_gem_request_remove_from_client(request);
1835                 kfree(request);
1836         }
1837
1838         /* Move any buffers on the active list that are no longer referenced
1839          * by the ringbuffer to the flushing/inactive lists as appropriate.
1840          */
1841         while (!list_empty(&ring->active_list)) {
1842                 struct drm_i915_gem_object *obj;
1843
1844                 obj = list_first_entry(&ring->active_list,
1845                                       struct drm_i915_gem_object,
1846                                       ring_list);
1847
1848                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1849                         break;
1850
1851                 if (obj->base.write_domain != 0)
1852                         i915_gem_object_move_to_flushing(obj);
1853                 else
1854                         i915_gem_object_move_to_inactive(obj);
1855         }
1856
1857         if (unlikely(ring->trace_irq_seqno &&
1858                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1859                 ring->irq_put(ring);
1860                 ring->trace_irq_seqno = 0;
1861         }
1862
1863         WARN_ON(i915_verify_lists(ring->dev));
1864 }
1865
1866 void
1867 i915_gem_retire_requests(struct drm_device *dev)
1868 {
1869         drm_i915_private_t *dev_priv = dev->dev_private;
1870         int i;
1871
1872         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1873             struct drm_i915_gem_object *obj, *next;
1874
1875             /* We must be careful that during unbind() we do not
1876              * accidentally infinitely recurse into retire requests.
1877              * Currently:
1878              *   retire -> free -> unbind -> wait -> retire_ring
1879              */
1880             list_for_each_entry_safe(obj, next,
1881                                      &dev_priv->mm.deferred_free_list,
1882                                      mm_list)
1883                     i915_gem_free_object_tail(obj);
1884         }
1885
1886         for (i = 0; i < I915_NUM_RINGS; i++)
1887                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1888 }
1889
1890 static void
1891 i915_gem_retire_work_handler(struct work_struct *work)
1892 {
1893         drm_i915_private_t *dev_priv;
1894         struct drm_device *dev;
1895         bool idle;
1896         int i;
1897
1898         dev_priv = container_of(work, drm_i915_private_t,
1899                                 mm.retire_work.work);
1900         dev = dev_priv->dev;
1901
1902         /* Come back later if the device is busy... */
1903         if (!mutex_trylock(&dev->struct_mutex)) {
1904                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1905                 return;
1906         }
1907
1908         i915_gem_retire_requests(dev);
1909
1910         /* Send a periodic flush down the ring so we don't hold onto GEM
1911          * objects indefinitely.
1912          */
1913         idle = true;
1914         for (i = 0; i < I915_NUM_RINGS; i++) {
1915                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1916
1917                 if (!list_empty(&ring->gpu_write_list)) {
1918                         struct drm_i915_gem_request *request;
1919                         int ret;
1920
1921                         ret = i915_gem_flush_ring(ring,
1922                                                   0, I915_GEM_GPU_DOMAINS);
1923                         request = kzalloc(sizeof(*request), GFP_KERNEL);
1924                         if (ret || request == NULL ||
1925                             i915_add_request(ring, NULL, request))
1926                             kfree(request);
1927                 }
1928
1929                 idle &= list_empty(&ring->request_list);
1930         }
1931
1932         if (!dev_priv->mm.suspended && !idle)
1933                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1934
1935         mutex_unlock(&dev->struct_mutex);
1936 }
1937
1938 /**
1939  * Waits for a sequence number to be signaled, and cleans up the
1940  * request and object lists appropriately for that event.
1941  */
1942 int
1943 i915_wait_request(struct intel_ring_buffer *ring,
1944                   uint32_t seqno)
1945 {
1946         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1947         u32 ier;
1948         int ret = 0;
1949
1950         BUG_ON(seqno == 0);
1951
1952         if (atomic_read(&dev_priv->mm.wedged)) {
1953                 struct completion *x = &dev_priv->error_completion;
1954                 bool recovery_complete;
1955                 unsigned long flags;
1956
1957                 /* Give the error handler a chance to run. */
1958                 spin_lock_irqsave(&x->wait.lock, flags);
1959                 recovery_complete = x->done > 0;
1960                 spin_unlock_irqrestore(&x->wait.lock, flags);
1961
1962                 return recovery_complete ? -EIO : -EAGAIN;
1963         }
1964
1965         if (seqno == ring->outstanding_lazy_request) {
1966                 struct drm_i915_gem_request *request;
1967
1968                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1969                 if (request == NULL)
1970                         return -ENOMEM;
1971
1972                 ret = i915_add_request(ring, NULL, request);
1973                 if (ret) {
1974                         kfree(request);
1975                         return ret;
1976                 }
1977
1978                 seqno = request->seqno;
1979         }
1980
1981         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
1982                 if (HAS_PCH_SPLIT(ring->dev))
1983                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1984                 else
1985                         ier = I915_READ(IER);
1986                 if (!ier) {
1987                         DRM_ERROR("something (likely vbetool) disabled "
1988                                   "interrupts, re-enabling\n");
1989                         ring->dev->driver->irq_preinstall(ring->dev);
1990                         ring->dev->driver->irq_postinstall(ring->dev);
1991                 }
1992
1993                 trace_i915_gem_request_wait_begin(ring, seqno);
1994
1995                 ring->waiting_seqno = seqno;
1996                 if (ring->irq_get(ring)) {
1997                         if (dev_priv->mm.interruptible)
1998                                 ret = wait_event_interruptible(ring->irq_queue,
1999                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2000                                                                || atomic_read(&dev_priv->mm.wedged));
2001                         else
2002                                 wait_event(ring->irq_queue,
2003                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2004                                            || atomic_read(&dev_priv->mm.wedged));
2005
2006                         ring->irq_put(ring);
2007                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2008                                                       seqno) ||
2009                                     atomic_read(&dev_priv->mm.wedged), 3000))
2010                         ret = -EBUSY;
2011                 ring->waiting_seqno = 0;
2012
2013                 trace_i915_gem_request_wait_end(ring, seqno);
2014         }
2015         if (atomic_read(&dev_priv->mm.wedged))
2016                 ret = -EAGAIN;
2017
2018         if (ret && ret != -ERESTARTSYS)
2019                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2020                           __func__, ret, seqno, ring->get_seqno(ring),
2021                           dev_priv->next_seqno);
2022
2023         /* Directly dispatch request retiring.  While we have the work queue
2024          * to handle this, the waiter on a request often wants an associated
2025          * buffer to have made it to the inactive list, and we would need
2026          * a separate wait queue to handle that.
2027          */
2028         if (ret == 0)
2029                 i915_gem_retire_requests_ring(ring);
2030
2031         return ret;
2032 }
2033
2034 /**
2035  * Ensures that all rendering to the object has completed and the object is
2036  * safe to unbind from the GTT or access from the CPU.
2037  */
2038 int
2039 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2040 {
2041         int ret;
2042
2043         /* This function only exists to support waiting for existing rendering,
2044          * not for emitting required flushes.
2045          */
2046         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2047
2048         /* If there is rendering queued on the buffer being evicted, wait for
2049          * it.
2050          */
2051         if (obj->active) {
2052                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2053                 if (ret)
2054                         return ret;
2055         }
2056
2057         return 0;
2058 }
2059
2060 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2061 {
2062         u32 old_write_domain, old_read_domains;
2063
2064         /* Act a barrier for all accesses through the GTT */
2065         mb();
2066
2067         /* Force a pagefault for domain tracking on next user access */
2068         i915_gem_release_mmap(obj);
2069
2070         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2071                 return;
2072
2073         old_read_domains = obj->base.read_domains;
2074         old_write_domain = obj->base.write_domain;
2075
2076         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2077         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2078
2079         trace_i915_gem_object_change_domain(obj,
2080                                             old_read_domains,
2081                                             old_write_domain);
2082 }
2083
2084 /**
2085  * Unbinds an object from the GTT aperture.
2086  */
2087 int
2088 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2089 {
2090         int ret = 0;
2091
2092         if (obj->gtt_space == NULL)
2093                 return 0;
2094
2095         if (obj->pin_count != 0) {
2096                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2097                 return -EINVAL;
2098         }
2099
2100         ret = i915_gem_object_finish_gpu(obj);
2101         if (ret == -ERESTARTSYS)
2102                 return ret;
2103         /* Continue on if we fail due to EIO, the GPU is hung so we
2104          * should be safe and we need to cleanup or else we might
2105          * cause memory corruption through use-after-free.
2106          */
2107
2108         i915_gem_object_finish_gtt(obj);
2109
2110         /* Move the object to the CPU domain to ensure that
2111          * any possible CPU writes while it's not in the GTT
2112          * are flushed when we go to remap it.
2113          */
2114         if (ret == 0)
2115                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2116         if (ret == -ERESTARTSYS)
2117                 return ret;
2118         if (ret) {
2119                 /* In the event of a disaster, abandon all caches and
2120                  * hope for the best.
2121                  */
2122                 i915_gem_clflush_object(obj);
2123                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2124         }
2125
2126         /* release the fence reg _after_ flushing */
2127         ret = i915_gem_object_put_fence(obj);
2128         if (ret == -ERESTARTSYS)
2129                 return ret;
2130
2131         trace_i915_gem_object_unbind(obj);
2132
2133         i915_gem_gtt_unbind_object(obj);
2134         i915_gem_object_put_pages_gtt(obj);
2135
2136         list_del_init(&obj->gtt_list);
2137         list_del_init(&obj->mm_list);
2138         /* Avoid an unnecessary call to unbind on rebind. */
2139         obj->map_and_fenceable = true;
2140
2141         drm_mm_put_block(obj->gtt_space);
2142         obj->gtt_space = NULL;
2143         obj->gtt_offset = 0;
2144
2145         if (i915_gem_object_is_purgeable(obj))
2146                 i915_gem_object_truncate(obj);
2147
2148         return ret;
2149 }
2150
2151 int
2152 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2153                     uint32_t invalidate_domains,
2154                     uint32_t flush_domains)
2155 {
2156         int ret;
2157
2158         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2159                 return 0;
2160
2161         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2162
2163         ret = ring->flush(ring, invalidate_domains, flush_domains);
2164         if (ret)
2165                 return ret;
2166
2167         if (flush_domains & I915_GEM_GPU_DOMAINS)
2168                 i915_gem_process_flushing_list(ring, flush_domains);
2169
2170         return 0;
2171 }
2172
2173 static int i915_ring_idle(struct intel_ring_buffer *ring)
2174 {
2175         int ret;
2176
2177         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2178                 return 0;
2179
2180         if (!list_empty(&ring->gpu_write_list)) {
2181                 ret = i915_gem_flush_ring(ring,
2182                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2183                 if (ret)
2184                         return ret;
2185         }
2186
2187         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2188 }
2189
2190 int
2191 i915_gpu_idle(struct drm_device *dev)
2192 {
2193         drm_i915_private_t *dev_priv = dev->dev_private;
2194         bool lists_empty;
2195         int ret, i;
2196
2197         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2198                        list_empty(&dev_priv->mm.active_list));
2199         if (lists_empty)
2200                 return 0;
2201
2202         /* Flush everything onto the inactive list. */
2203         for (i = 0; i < I915_NUM_RINGS; i++) {
2204                 ret = i915_ring_idle(&dev_priv->ring[i]);
2205                 if (ret)
2206                         return ret;
2207         }
2208
2209         return 0;
2210 }
2211
2212 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2213                                        struct intel_ring_buffer *pipelined)
2214 {
2215         struct drm_device *dev = obj->base.dev;
2216         drm_i915_private_t *dev_priv = dev->dev_private;
2217         u32 size = obj->gtt_space->size;
2218         int regnum = obj->fence_reg;
2219         uint64_t val;
2220
2221         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2222                          0xfffff000) << 32;
2223         val |= obj->gtt_offset & 0xfffff000;
2224         val |= (uint64_t)((obj->stride / 128) - 1) <<
2225                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2226
2227         if (obj->tiling_mode == I915_TILING_Y)
2228                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2229         val |= I965_FENCE_REG_VALID;
2230
2231         if (pipelined) {
2232                 int ret = intel_ring_begin(pipelined, 6);
2233                 if (ret)
2234                         return ret;
2235
2236                 intel_ring_emit(pipelined, MI_NOOP);
2237                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2238                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2239                 intel_ring_emit(pipelined, (u32)val);
2240                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2241                 intel_ring_emit(pipelined, (u32)(val >> 32));
2242                 intel_ring_advance(pipelined);
2243         } else
2244                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2245
2246         return 0;
2247 }
2248
2249 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2250                                 struct intel_ring_buffer *pipelined)
2251 {
2252         struct drm_device *dev = obj->base.dev;
2253         drm_i915_private_t *dev_priv = dev->dev_private;
2254         u32 size = obj->gtt_space->size;
2255         int regnum = obj->fence_reg;
2256         uint64_t val;
2257
2258         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2259                     0xfffff000) << 32;
2260         val |= obj->gtt_offset & 0xfffff000;
2261         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2262         if (obj->tiling_mode == I915_TILING_Y)
2263                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2264         val |= I965_FENCE_REG_VALID;
2265
2266         if (pipelined) {
2267                 int ret = intel_ring_begin(pipelined, 6);
2268                 if (ret)
2269                         return ret;
2270
2271                 intel_ring_emit(pipelined, MI_NOOP);
2272                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2273                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2274                 intel_ring_emit(pipelined, (u32)val);
2275                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2276                 intel_ring_emit(pipelined, (u32)(val >> 32));
2277                 intel_ring_advance(pipelined);
2278         } else
2279                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2280
2281         return 0;
2282 }
2283
2284 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2285                                 struct intel_ring_buffer *pipelined)
2286 {
2287         struct drm_device *dev = obj->base.dev;
2288         drm_i915_private_t *dev_priv = dev->dev_private;
2289         u32 size = obj->gtt_space->size;
2290         u32 fence_reg, val, pitch_val;
2291         int tile_width;
2292
2293         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2294                  (size & -size) != size ||
2295                  (obj->gtt_offset & (size - 1)),
2296                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2297                  obj->gtt_offset, obj->map_and_fenceable, size))
2298                 return -EINVAL;
2299
2300         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2301                 tile_width = 128;
2302         else
2303                 tile_width = 512;
2304
2305         /* Note: pitch better be a power of two tile widths */
2306         pitch_val = obj->stride / tile_width;
2307         pitch_val = ffs(pitch_val) - 1;
2308
2309         val = obj->gtt_offset;
2310         if (obj->tiling_mode == I915_TILING_Y)
2311                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2312         val |= I915_FENCE_SIZE_BITS(size);
2313         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2314         val |= I830_FENCE_REG_VALID;
2315
2316         fence_reg = obj->fence_reg;
2317         if (fence_reg < 8)
2318                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2319         else
2320                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2321
2322         if (pipelined) {
2323                 int ret = intel_ring_begin(pipelined, 4);
2324                 if (ret)
2325                         return ret;
2326
2327                 intel_ring_emit(pipelined, MI_NOOP);
2328                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2329                 intel_ring_emit(pipelined, fence_reg);
2330                 intel_ring_emit(pipelined, val);
2331                 intel_ring_advance(pipelined);
2332         } else
2333                 I915_WRITE(fence_reg, val);
2334
2335         return 0;
2336 }
2337
2338 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2339                                 struct intel_ring_buffer *pipelined)
2340 {
2341         struct drm_device *dev = obj->base.dev;
2342         drm_i915_private_t *dev_priv = dev->dev_private;
2343         u32 size = obj->gtt_space->size;
2344         int regnum = obj->fence_reg;
2345         uint32_t val;
2346         uint32_t pitch_val;
2347
2348         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2349                  (size & -size) != size ||
2350                  (obj->gtt_offset & (size - 1)),
2351                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2352                  obj->gtt_offset, size))
2353                 return -EINVAL;
2354
2355         pitch_val = obj->stride / 128;
2356         pitch_val = ffs(pitch_val) - 1;
2357
2358         val = obj->gtt_offset;
2359         if (obj->tiling_mode == I915_TILING_Y)
2360                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2361         val |= I830_FENCE_SIZE_BITS(size);
2362         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2363         val |= I830_FENCE_REG_VALID;
2364
2365         if (pipelined) {
2366                 int ret = intel_ring_begin(pipelined, 4);
2367                 if (ret)
2368                         return ret;
2369
2370                 intel_ring_emit(pipelined, MI_NOOP);
2371                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2372                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2373                 intel_ring_emit(pipelined, val);
2374                 intel_ring_advance(pipelined);
2375         } else
2376                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2377
2378         return 0;
2379 }
2380
2381 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2382 {
2383         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2384 }
2385
2386 static int
2387 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2388                             struct intel_ring_buffer *pipelined)
2389 {
2390         int ret;
2391
2392         if (obj->fenced_gpu_access) {
2393                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2394                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2395                                                   0, obj->base.write_domain);
2396                         if (ret)
2397                                 return ret;
2398                 }
2399
2400                 obj->fenced_gpu_access = false;
2401         }
2402
2403         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2404                 if (!ring_passed_seqno(obj->last_fenced_ring,
2405                                        obj->last_fenced_seqno)) {
2406                         ret = i915_wait_request(obj->last_fenced_ring,
2407                                                 obj->last_fenced_seqno);
2408                         if (ret)
2409                                 return ret;
2410                 }
2411
2412                 obj->last_fenced_seqno = 0;
2413                 obj->last_fenced_ring = NULL;
2414         }
2415
2416         /* Ensure that all CPU reads are completed before installing a fence
2417          * and all writes before removing the fence.
2418          */
2419         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2420                 mb();
2421
2422         return 0;
2423 }
2424
2425 int
2426 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2427 {
2428         int ret;
2429
2430         if (obj->tiling_mode)
2431                 i915_gem_release_mmap(obj);
2432
2433         ret = i915_gem_object_flush_fence(obj, NULL);
2434         if (ret)
2435                 return ret;
2436
2437         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2438                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2439                 i915_gem_clear_fence_reg(obj->base.dev,
2440                                          &dev_priv->fence_regs[obj->fence_reg]);
2441
2442                 obj->fence_reg = I915_FENCE_REG_NONE;
2443         }
2444
2445         return 0;
2446 }
2447
2448 static struct drm_i915_fence_reg *
2449 i915_find_fence_reg(struct drm_device *dev,
2450                     struct intel_ring_buffer *pipelined)
2451 {
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         struct drm_i915_fence_reg *reg, *first, *avail;
2454         int i;
2455
2456         /* First try to find a free reg */
2457         avail = NULL;
2458         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2459                 reg = &dev_priv->fence_regs[i];
2460                 if (!reg->obj)
2461                         return reg;
2462
2463                 if (!reg->obj->pin_count)
2464                         avail = reg;
2465         }
2466
2467         if (avail == NULL)
2468                 return NULL;
2469
2470         /* None available, try to steal one or wait for a user to finish */
2471         avail = first = NULL;
2472         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2473                 if (reg->obj->pin_count)
2474                         continue;
2475
2476                 if (first == NULL)
2477                         first = reg;
2478
2479                 if (!pipelined ||
2480                     !reg->obj->last_fenced_ring ||
2481                     reg->obj->last_fenced_ring == pipelined) {
2482                         avail = reg;
2483                         break;
2484                 }
2485         }
2486
2487         if (avail == NULL)
2488                 avail = first;
2489
2490         return avail;
2491 }
2492
2493 /**
2494  * i915_gem_object_get_fence - set up a fence reg for an object
2495  * @obj: object to map through a fence reg
2496  * @pipelined: ring on which to queue the change, or NULL for CPU access
2497  * @interruptible: must we wait uninterruptibly for the register to retire?
2498  *
2499  * When mapping objects through the GTT, userspace wants to be able to write
2500  * to them without having to worry about swizzling if the object is tiled.
2501  *
2502  * This function walks the fence regs looking for a free one for @obj,
2503  * stealing one if it can't find any.
2504  *
2505  * It then sets up the reg based on the object's properties: address, pitch
2506  * and tiling format.
2507  */
2508 int
2509 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2510                           struct intel_ring_buffer *pipelined)
2511 {
2512         struct drm_device *dev = obj->base.dev;
2513         struct drm_i915_private *dev_priv = dev->dev_private;
2514         struct drm_i915_fence_reg *reg;
2515         int ret;
2516
2517         /* XXX disable pipelining. There are bugs. Shocking. */
2518         pipelined = NULL;
2519
2520         /* Just update our place in the LRU if our fence is getting reused. */
2521         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2522                 reg = &dev_priv->fence_regs[obj->fence_reg];
2523                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2524
2525                 if (obj->tiling_changed) {
2526                         ret = i915_gem_object_flush_fence(obj, pipelined);
2527                         if (ret)
2528                                 return ret;
2529
2530                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2531                                 pipelined = NULL;
2532
2533                         if (pipelined) {
2534                                 reg->setup_seqno =
2535                                         i915_gem_next_request_seqno(pipelined);
2536                                 obj->last_fenced_seqno = reg->setup_seqno;
2537                                 obj->last_fenced_ring = pipelined;
2538                         }
2539
2540                         goto update;
2541                 }
2542
2543                 if (!pipelined) {
2544                         if (reg->setup_seqno) {
2545                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2546                                                        reg->setup_seqno)) {
2547                                         ret = i915_wait_request(obj->last_fenced_ring,
2548                                                                 reg->setup_seqno);
2549                                         if (ret)
2550                                                 return ret;
2551                                 }
2552
2553                                 reg->setup_seqno = 0;
2554                         }
2555                 } else if (obj->last_fenced_ring &&
2556                            obj->last_fenced_ring != pipelined) {
2557                         ret = i915_gem_object_flush_fence(obj, pipelined);
2558                         if (ret)
2559                                 return ret;
2560                 }
2561
2562                 return 0;
2563         }
2564
2565         reg = i915_find_fence_reg(dev, pipelined);
2566         if (reg == NULL)
2567                 return -ENOSPC;
2568
2569         ret = i915_gem_object_flush_fence(obj, pipelined);
2570         if (ret)
2571                 return ret;
2572
2573         if (reg->obj) {
2574                 struct drm_i915_gem_object *old = reg->obj;
2575
2576                 drm_gem_object_reference(&old->base);
2577
2578                 if (old->tiling_mode)
2579                         i915_gem_release_mmap(old);
2580
2581                 ret = i915_gem_object_flush_fence(old, pipelined);
2582                 if (ret) {
2583                         drm_gem_object_unreference(&old->base);
2584                         return ret;
2585                 }
2586
2587                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2588                         pipelined = NULL;
2589
2590                 old->fence_reg = I915_FENCE_REG_NONE;
2591                 old->last_fenced_ring = pipelined;
2592                 old->last_fenced_seqno =
2593                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2594
2595                 drm_gem_object_unreference(&old->base);
2596         } else if (obj->last_fenced_seqno == 0)
2597                 pipelined = NULL;
2598
2599         reg->obj = obj;
2600         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2601         obj->fence_reg = reg - dev_priv->fence_regs;
2602         obj->last_fenced_ring = pipelined;
2603
2604         reg->setup_seqno =
2605                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2606         obj->last_fenced_seqno = reg->setup_seqno;
2607
2608 update:
2609         obj->tiling_changed = false;
2610         switch (INTEL_INFO(dev)->gen) {
2611         case 7:
2612         case 6:
2613                 ret = sandybridge_write_fence_reg(obj, pipelined);
2614                 break;
2615         case 5:
2616         case 4:
2617                 ret = i965_write_fence_reg(obj, pipelined);
2618                 break;
2619         case 3:
2620                 ret = i915_write_fence_reg(obj, pipelined);
2621                 break;
2622         case 2:
2623                 ret = i830_write_fence_reg(obj, pipelined);
2624                 break;
2625         }
2626
2627         return ret;
2628 }
2629
2630 /**
2631  * i915_gem_clear_fence_reg - clear out fence register info
2632  * @obj: object to clear
2633  *
2634  * Zeroes out the fence register itself and clears out the associated
2635  * data structures in dev_priv and obj.
2636  */
2637 static void
2638 i915_gem_clear_fence_reg(struct drm_device *dev,
2639                          struct drm_i915_fence_reg *reg)
2640 {
2641         drm_i915_private_t *dev_priv = dev->dev_private;
2642         uint32_t fence_reg = reg - dev_priv->fence_regs;
2643
2644         switch (INTEL_INFO(dev)->gen) {
2645         case 7:
2646         case 6:
2647                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2648                 break;
2649         case 5:
2650         case 4:
2651                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2652                 break;
2653         case 3:
2654                 if (fence_reg >= 8)
2655                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2656                 else
2657         case 2:
2658                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2659
2660                 I915_WRITE(fence_reg, 0);
2661                 break;
2662         }
2663
2664         list_del_init(&reg->lru_list);
2665         reg->obj = NULL;
2666         reg->setup_seqno = 0;
2667 }
2668
2669 /**
2670  * Finds free space in the GTT aperture and binds the object there.
2671  */
2672 static int
2673 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2674                             unsigned alignment,
2675                             bool map_and_fenceable)
2676 {
2677         struct drm_device *dev = obj->base.dev;
2678         drm_i915_private_t *dev_priv = dev->dev_private;
2679         struct drm_mm_node *free_space;
2680         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2681         u32 size, fence_size, fence_alignment, unfenced_alignment;
2682         bool mappable, fenceable;
2683         int ret;
2684
2685         if (obj->madv != I915_MADV_WILLNEED) {
2686                 DRM_ERROR("Attempting to bind a purgeable object\n");
2687                 return -EINVAL;
2688         }
2689
2690         fence_size = i915_gem_get_gtt_size(dev,
2691                                            obj->base.size,
2692                                            obj->tiling_mode);
2693         fence_alignment = i915_gem_get_gtt_alignment(dev,
2694                                                      obj->base.size,
2695                                                      obj->tiling_mode);
2696         unfenced_alignment =
2697                 i915_gem_get_unfenced_gtt_alignment(dev,
2698                                                     obj->base.size,
2699                                                     obj->tiling_mode);
2700
2701         if (alignment == 0)
2702                 alignment = map_and_fenceable ? fence_alignment :
2703                                                 unfenced_alignment;
2704         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2705                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2706                 return -EINVAL;
2707         }
2708
2709         size = map_and_fenceable ? fence_size : obj->base.size;
2710
2711         /* If the object is bigger than the entire aperture, reject it early
2712          * before evicting everything in a vain attempt to find space.
2713          */
2714         if (obj->base.size >
2715             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2716                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2717                 return -E2BIG;
2718         }
2719
2720  search_free:
2721         if (map_and_fenceable)
2722                 free_space =
2723                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2724                                                     size, alignment, 0,
2725                                                     dev_priv->mm.gtt_mappable_end,
2726                                                     0);
2727         else
2728                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2729                                                 size, alignment, 0);
2730
2731         if (free_space != NULL) {
2732                 if (map_and_fenceable)
2733                         obj->gtt_space =
2734                                 drm_mm_get_block_range_generic(free_space,
2735                                                                size, alignment, 0,
2736                                                                dev_priv->mm.gtt_mappable_end,
2737                                                                0);
2738                 else
2739                         obj->gtt_space =
2740                                 drm_mm_get_block(free_space, size, alignment);
2741         }
2742         if (obj->gtt_space == NULL) {
2743                 /* If the gtt is empty and we're still having trouble
2744                  * fitting our object in, we're out of memory.
2745                  */
2746                 ret = i915_gem_evict_something(dev, size, alignment,
2747                                                map_and_fenceable);
2748                 if (ret)
2749                         return ret;
2750
2751                 goto search_free;
2752         }
2753
2754         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2755         if (ret) {
2756                 drm_mm_put_block(obj->gtt_space);
2757                 obj->gtt_space = NULL;
2758
2759                 if (ret == -ENOMEM) {
2760                         /* first try to reclaim some memory by clearing the GTT */
2761                         ret = i915_gem_evict_everything(dev, false);
2762                         if (ret) {
2763                                 /* now try to shrink everyone else */
2764                                 if (gfpmask) {
2765                                         gfpmask = 0;
2766                                         goto search_free;
2767                                 }
2768
2769                                 return -ENOMEM;
2770                         }
2771
2772                         goto search_free;
2773                 }
2774
2775                 return ret;
2776         }
2777
2778         ret = i915_gem_gtt_bind_object(obj);
2779         if (ret) {
2780                 i915_gem_object_put_pages_gtt(obj);
2781                 drm_mm_put_block(obj->gtt_space);
2782                 obj->gtt_space = NULL;
2783
2784                 if (i915_gem_evict_everything(dev, false))
2785                         return ret;
2786
2787                 goto search_free;
2788         }
2789
2790         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2791         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2792
2793         /* Assert that the object is not currently in any GPU domain. As it
2794          * wasn't in the GTT, there shouldn't be any way it could have been in
2795          * a GPU cache
2796          */
2797         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2798         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2799
2800         obj->gtt_offset = obj->gtt_space->start;
2801
2802         fenceable =
2803                 obj->gtt_space->size == fence_size &&
2804                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2805
2806         mappable =
2807                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2808
2809         obj->map_and_fenceable = mappable && fenceable;
2810
2811         trace_i915_gem_object_bind(obj, map_and_fenceable);
2812         return 0;
2813 }
2814
2815 void
2816 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2817 {
2818         /* If we don't have a page list set up, then we're not pinned
2819          * to GPU, and we can ignore the cache flush because it'll happen
2820          * again at bind time.
2821          */
2822         if (obj->pages == NULL)
2823                 return;
2824
2825         /* If the GPU is snooping the contents of the CPU cache,
2826          * we do not need to manually clear the CPU cache lines.  However,
2827          * the caches are only snooped when the render cache is
2828          * flushed/invalidated.  As we always have to emit invalidations
2829          * and flushes when moving into and out of the RENDER domain, correct
2830          * snooping behaviour occurs naturally as the result of our domain
2831          * tracking.
2832          */
2833         if (obj->cache_level != I915_CACHE_NONE)
2834                 return;
2835
2836         trace_i915_gem_object_clflush(obj);
2837
2838         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2839 }
2840
2841 /** Flushes any GPU write domain for the object if it's dirty. */
2842 static int
2843 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2844 {
2845         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2846                 return 0;
2847
2848         /* Queue the GPU write cache flushing we need. */
2849         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2850 }
2851
2852 /** Flushes the GTT write domain for the object if it's dirty. */
2853 static void
2854 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2855 {
2856         uint32_t old_write_domain;
2857
2858         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2859                 return;
2860
2861         /* No actual flushing is required for the GTT write domain.  Writes
2862          * to it immediately go to main memory as far as we know, so there's
2863          * no chipset flush.  It also doesn't land in render cache.
2864          *
2865          * However, we do have to enforce the order so that all writes through
2866          * the GTT land before any writes to the device, such as updates to
2867          * the GATT itself.
2868          */
2869         wmb();
2870
2871         old_write_domain = obj->base.write_domain;
2872         obj->base.write_domain = 0;
2873
2874         trace_i915_gem_object_change_domain(obj,
2875                                             obj->base.read_domains,
2876                                             old_write_domain);
2877 }
2878
2879 /** Flushes the CPU write domain for the object if it's dirty. */
2880 static void
2881 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2882 {
2883         uint32_t old_write_domain;
2884
2885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2886                 return;
2887
2888         i915_gem_clflush_object(obj);
2889         intel_gtt_chipset_flush();
2890         old_write_domain = obj->base.write_domain;
2891         obj->base.write_domain = 0;
2892
2893         trace_i915_gem_object_change_domain(obj,
2894                                             obj->base.read_domains,
2895                                             old_write_domain);
2896 }
2897
2898 /**
2899  * Moves a single object to the GTT read, and possibly write domain.
2900  *
2901  * This function returns when the move is complete, including waiting on
2902  * flushes to occur.
2903  */
2904 int
2905 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2906 {
2907         uint32_t old_write_domain, old_read_domains;
2908         int ret;
2909
2910         /* Not valid to be called on unbound objects. */
2911         if (obj->gtt_space == NULL)
2912                 return -EINVAL;
2913
2914         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2915                 return 0;
2916
2917         ret = i915_gem_object_flush_gpu_write_domain(obj);
2918         if (ret)
2919                 return ret;
2920
2921         if (obj->pending_gpu_write || write) {
2922                 ret = i915_gem_object_wait_rendering(obj);
2923                 if (ret)
2924                         return ret;
2925         }
2926
2927         i915_gem_object_flush_cpu_write_domain(obj);
2928
2929         old_write_domain = obj->base.write_domain;
2930         old_read_domains = obj->base.read_domains;
2931
2932         /* It should now be out of any other write domains, and we can update
2933          * the domain values for our changes.
2934          */
2935         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2936         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2937         if (write) {
2938                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2939                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2940                 obj->dirty = 1;
2941         }
2942
2943         trace_i915_gem_object_change_domain(obj,
2944                                             old_read_domains,
2945                                             old_write_domain);
2946
2947         return 0;
2948 }
2949
2950 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2951                                     enum i915_cache_level cache_level)
2952 {
2953         int ret;
2954
2955         if (obj->cache_level == cache_level)
2956                 return 0;
2957
2958         if (obj->pin_count) {
2959                 DRM_DEBUG("can not change the cache level of pinned objects\n");
2960                 return -EBUSY;
2961         }
2962
2963         if (obj->gtt_space) {
2964                 ret = i915_gem_object_finish_gpu(obj);
2965                 if (ret)
2966                         return ret;
2967
2968                 i915_gem_object_finish_gtt(obj);
2969
2970                 /* Before SandyBridge, you could not use tiling or fence
2971                  * registers with snooped memory, so relinquish any fences
2972                  * currently pointing to our region in the aperture.
2973                  */
2974                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2975                         ret = i915_gem_object_put_fence(obj);
2976                         if (ret)
2977                                 return ret;
2978                 }
2979
2980                 i915_gem_gtt_rebind_object(obj, cache_level);
2981         }
2982
2983         if (cache_level == I915_CACHE_NONE) {
2984                 u32 old_read_domains, old_write_domain;
2985
2986                 /* If we're coming from LLC cached, then we haven't
2987                  * actually been tracking whether the data is in the
2988                  * CPU cache or not, since we only allow one bit set
2989                  * in obj->write_domain and have been skipping the clflushes.
2990                  * Just set it to the CPU cache for now.
2991                  */
2992                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2993                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2994
2995                 old_read_domains = obj->base.read_domains;
2996                 old_write_domain = obj->base.write_domain;
2997
2998                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2999                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3000
3001                 trace_i915_gem_object_change_domain(obj,
3002                                                     old_read_domains,
3003                                                     old_write_domain);
3004         }
3005
3006         obj->cache_level = cache_level;
3007         return 0;
3008 }
3009
3010 /*
3011  * Prepare buffer for display plane (scanout, cursors, etc).
3012  * Can be called from an uninterruptible phase (modesetting) and allows
3013  * any flushes to be pipelined (for pageflips).
3014  *
3015  * For the display plane, we want to be in the GTT but out of any write
3016  * domains. So in many ways this looks like set_to_gtt_domain() apart from the
3017  * ability to pipeline the waits, pinning and any additional subtleties
3018  * that may differentiate the display plane from ordinary buffers.
3019  */
3020 int
3021 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3022                                      u32 alignment,
3023                                      struct intel_ring_buffer *pipelined)
3024 {
3025         u32 old_read_domains, old_write_domain;
3026         int ret;
3027
3028         ret = i915_gem_object_flush_gpu_write_domain(obj);
3029         if (ret)
3030                 return ret;
3031
3032         if (pipelined != obj->ring) {
3033                 ret = i915_gem_object_wait_rendering(obj);
3034                 if (ret == -ERESTARTSYS)
3035                         return ret;
3036         }
3037
3038         /* The display engine is not coherent with the LLC cache on gen6.  As
3039          * a result, we make sure that the pinning that is about to occur is
3040          * done with uncached PTEs. This is lowest common denominator for all
3041          * chipsets.
3042          *
3043          * However for gen6+, we could do better by using the GFDT bit instead
3044          * of uncaching, which would allow us to flush all the LLC-cached data
3045          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3046          */
3047         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3048         if (ret)
3049                 return ret;
3050
3051         /* As the user may map the buffer once pinned in the display plane
3052          * (e.g. libkms for the bootup splash), we have to ensure that we
3053          * always use map_and_fenceable for all scanout buffers.
3054          */
3055         ret = i915_gem_object_pin(obj, alignment, true);
3056         if (ret)
3057                 return ret;
3058
3059         i915_gem_object_flush_cpu_write_domain(obj);
3060
3061         old_write_domain = obj->base.write_domain;
3062         old_read_domains = obj->base.read_domains;
3063
3064         /* It should now be out of any other write domains, and we can update
3065          * the domain values for our changes.
3066          */
3067         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3068         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3069
3070         trace_i915_gem_object_change_domain(obj,
3071                                             old_read_domains,
3072                                             old_write_domain);
3073
3074         return 0;
3075 }
3076
3077 int
3078 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3079 {
3080         int ret;
3081
3082         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3083                 return 0;
3084
3085         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3086                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3087                 if (ret)
3088                         return ret;
3089         }
3090
3091         /* Ensure that we invalidate the GPU's caches and TLBs. */
3092         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3093
3094         return i915_gem_object_wait_rendering(obj);
3095 }
3096
3097 /**
3098  * Moves a single object to the CPU read, and possibly write domain.
3099  *
3100  * This function returns when the move is complete, including waiting on
3101  * flushes to occur.
3102  */
3103 static int
3104 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3105 {
3106         uint32_t old_write_domain, old_read_domains;
3107         int ret;
3108
3109         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3110                 return 0;
3111
3112         ret = i915_gem_object_flush_gpu_write_domain(obj);
3113         if (ret)
3114                 return ret;
3115
3116         ret = i915_gem_object_wait_rendering(obj);
3117         if (ret)
3118                 return ret;
3119
3120         i915_gem_object_flush_gtt_write_domain(obj);
3121
3122         /* If we have a partially-valid cache of the object in the CPU,
3123          * finish invalidating it and free the per-page flags.
3124          */
3125         i915_gem_object_set_to_full_cpu_read_domain(obj);
3126
3127         old_write_domain = obj->base.write_domain;
3128         old_read_domains = obj->base.read_domains;
3129
3130         /* Flush the CPU cache if it's still invalid. */
3131         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3132                 i915_gem_clflush_object(obj);
3133
3134                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3135         }
3136
3137         /* It should now be out of any other write domains, and we can update
3138          * the domain values for our changes.
3139          */
3140         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3141
3142         /* If we're writing through the CPU, then the GPU read domains will
3143          * need to be invalidated at next use.
3144          */
3145         if (write) {
3146                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3147                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3148         }
3149
3150         trace_i915_gem_object_change_domain(obj,
3151                                             old_read_domains,
3152                                             old_write_domain);
3153
3154         return 0;
3155 }
3156
3157 /**
3158  * Moves the object from a partially CPU read to a full one.
3159  *
3160  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3161  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3162  */
3163 static void
3164 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3165 {
3166         if (!obj->page_cpu_valid)
3167                 return;
3168
3169         /* If we're partially in the CPU read domain, finish moving it in.
3170          */
3171         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3172                 int i;
3173
3174                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3175                         if (obj->page_cpu_valid[i])
3176                                 continue;
3177                         drm_clflush_pages(obj->pages + i, 1);
3178                 }
3179         }
3180
3181         /* Free the page_cpu_valid mappings which are now stale, whether
3182          * or not we've got I915_GEM_DOMAIN_CPU.
3183          */
3184         kfree(obj->page_cpu_valid);
3185         obj->page_cpu_valid = NULL;
3186 }
3187
3188 /**
3189  * Set the CPU read domain on a range of the object.
3190  *
3191  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3192  * not entirely valid.  The page_cpu_valid member of the object flags which
3193  * pages have been flushed, and will be respected by
3194  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3195  * of the whole object.
3196  *
3197  * This function returns when the move is complete, including waiting on
3198  * flushes to occur.
3199  */
3200 static int
3201 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3202                                           uint64_t offset, uint64_t size)
3203 {
3204         uint32_t old_read_domains;
3205         int i, ret;
3206
3207         if (offset == 0 && size == obj->base.size)
3208                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3209
3210         ret = i915_gem_object_flush_gpu_write_domain(obj);
3211         if (ret)
3212                 return ret;
3213
3214         ret = i915_gem_object_wait_rendering(obj);
3215         if (ret)
3216                 return ret;
3217
3218         i915_gem_object_flush_gtt_write_domain(obj);
3219
3220         /* If we're already fully in the CPU read domain, we're done. */
3221         if (obj->page_cpu_valid == NULL &&
3222             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3223                 return 0;
3224
3225         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3226          * newly adding I915_GEM_DOMAIN_CPU
3227          */
3228         if (obj->page_cpu_valid == NULL) {
3229                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3230                                               GFP_KERNEL);
3231                 if (obj->page_cpu_valid == NULL)
3232                         return -ENOMEM;
3233         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3234                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3235
3236         /* Flush the cache on any pages that are still invalid from the CPU's
3237          * perspective.
3238          */
3239         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3240              i++) {
3241                 if (obj->page_cpu_valid[i])
3242                         continue;
3243
3244                 drm_clflush_pages(obj->pages + i, 1);
3245
3246                 obj->page_cpu_valid[i] = 1;
3247         }
3248
3249         /* It should now be out of any other write domains, and we can update
3250          * the domain values for our changes.
3251          */
3252         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3253
3254         old_read_domains = obj->base.read_domains;
3255         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3256
3257         trace_i915_gem_object_change_domain(obj,
3258                                             old_read_domains,
3259                                             obj->base.write_domain);
3260
3261         return 0;
3262 }
3263
3264 /* Throttle our rendering by waiting until the ring has completed our requests
3265  * emitted over 20 msec ago.
3266  *
3267  * Note that if we were to use the current jiffies each time around the loop,
3268  * we wouldn't escape the function with any frames outstanding if the time to
3269  * render a frame was over 20ms.
3270  *
3271  * This should get us reasonable parallelism between CPU and GPU but also
3272  * relatively low latency when blocking on a particular request to finish.
3273  */
3274 static int
3275 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3276 {
3277         struct drm_i915_private *dev_priv = dev->dev_private;
3278         struct drm_i915_file_private *file_priv = file->driver_priv;
3279         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3280         struct drm_i915_gem_request *request;
3281         struct intel_ring_buffer *ring = NULL;
3282         u32 seqno = 0;
3283         int ret;
3284
3285         if (atomic_read(&dev_priv->mm.wedged))
3286                 return -EIO;
3287
3288         spin_lock(&file_priv->mm.lock);
3289         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3290                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3291                         break;
3292
3293                 ring = request->ring;
3294                 seqno = request->seqno;
3295         }
3296         spin_unlock(&file_priv->mm.lock);
3297
3298         if (seqno == 0)
3299                 return 0;
3300
3301         ret = 0;
3302         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3303                 /* And wait for the seqno passing without holding any locks and
3304                  * causing extra latency for others. This is safe as the irq
3305                  * generation is designed to be run atomically and so is
3306                  * lockless.
3307                  */
3308                 if (ring->irq_get(ring)) {
3309                         ret = wait_event_interruptible(ring->irq_queue,
3310                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3311                                                        || atomic_read(&dev_priv->mm.wedged));
3312                         ring->irq_put(ring);
3313
3314                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3315                                 ret = -EIO;
3316                 }
3317         }
3318
3319         if (ret == 0)
3320                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3321
3322         return ret;
3323 }
3324
3325 int
3326 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3327                     uint32_t alignment,
3328                     bool map_and_fenceable)
3329 {
3330         struct drm_device *dev = obj->base.dev;
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         int ret;
3333
3334         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3335         WARN_ON(i915_verify_lists(dev));
3336
3337         if (obj->gtt_space != NULL) {
3338                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3339                     (map_and_fenceable && !obj->map_and_fenceable)) {
3340                         WARN(obj->pin_count,
3341                              "bo is already pinned with incorrect alignment:"
3342                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3343                              " obj->map_and_fenceable=%d\n",
3344                              obj->gtt_offset, alignment,
3345                              map_and_fenceable,
3346                              obj->map_and_fenceable);
3347                         ret = i915_gem_object_unbind(obj);
3348                         if (ret)
3349                                 return ret;
3350                 }
3351         }
3352
3353         if (obj->gtt_space == NULL) {
3354                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3355                                                   map_and_fenceable);
3356                 if (ret)
3357                         return ret;
3358         }
3359
3360         if (obj->pin_count++ == 0) {
3361                 if (!obj->active)
3362                         list_move_tail(&obj->mm_list,
3363                                        &dev_priv->mm.pinned_list);
3364         }
3365         obj->pin_mappable |= map_and_fenceable;
3366
3367         WARN_ON(i915_verify_lists(dev));
3368         return 0;
3369 }
3370
3371 void
3372 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3373 {
3374         struct drm_device *dev = obj->base.dev;
3375         drm_i915_private_t *dev_priv = dev->dev_private;
3376
3377         WARN_ON(i915_verify_lists(dev));
3378         BUG_ON(obj->pin_count == 0);
3379         BUG_ON(obj->gtt_space == NULL);
3380
3381         if (--obj->pin_count == 0) {
3382                 if (!obj->active)
3383                         list_move_tail(&obj->mm_list,
3384                                        &dev_priv->mm.inactive_list);
3385                 obj->pin_mappable = false;
3386         }
3387         WARN_ON(i915_verify_lists(dev));
3388 }
3389
3390 int
3391 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3392                    struct drm_file *file)
3393 {
3394         struct drm_i915_gem_pin *args = data;
3395         struct drm_i915_gem_object *obj;
3396         int ret;
3397
3398         ret = i915_mutex_lock_interruptible(dev);
3399         if (ret)
3400                 return ret;
3401
3402         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3403         if (&obj->base == NULL) {
3404                 ret = -ENOENT;
3405                 goto unlock;
3406         }
3407
3408         if (obj->madv != I915_MADV_WILLNEED) {
3409                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3410                 ret = -EINVAL;
3411                 goto out;
3412         }
3413
3414         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3415                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3416                           args->handle);
3417                 ret = -EINVAL;
3418                 goto out;
3419         }
3420
3421         obj->user_pin_count++;
3422         obj->pin_filp = file;
3423         if (obj->user_pin_count == 1) {
3424                 ret = i915_gem_object_pin(obj, args->alignment, true);
3425                 if (ret)
3426                         goto out;
3427         }
3428
3429         /* XXX - flush the CPU caches for pinned objects
3430          * as the X server doesn't manage domains yet
3431          */
3432         i915_gem_object_flush_cpu_write_domain(obj);
3433         args->offset = obj->gtt_offset;
3434 out:
3435         drm_gem_object_unreference(&obj->base);
3436 unlock:
3437         mutex_unlock(&dev->struct_mutex);
3438         return ret;
3439 }
3440
3441 int
3442 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3443                      struct drm_file *file)
3444 {
3445         struct drm_i915_gem_pin *args = data;
3446         struct drm_i915_gem_object *obj;
3447         int ret;
3448
3449         ret = i915_mutex_lock_interruptible(dev);
3450         if (ret)
3451                 return ret;
3452
3453         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3454         if (&obj->base == NULL) {
3455                 ret = -ENOENT;
3456                 goto unlock;
3457         }
3458
3459         if (obj->pin_filp != file) {
3460                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3461                           args->handle);
3462                 ret = -EINVAL;
3463                 goto out;
3464         }
3465         obj->user_pin_count--;
3466         if (obj->user_pin_count == 0) {
3467                 obj->pin_filp = NULL;
3468                 i915_gem_object_unpin(obj);
3469         }
3470
3471 out:
3472         drm_gem_object_unreference(&obj->base);
3473 unlock:
3474         mutex_unlock(&dev->struct_mutex);
3475         return ret;
3476 }
3477
3478 int
3479 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3480                     struct drm_file *file)
3481 {
3482         struct drm_i915_gem_busy *args = data;
3483         struct drm_i915_gem_object *obj;
3484         int ret;
3485
3486         ret = i915_mutex_lock_interruptible(dev);
3487         if (ret)
3488                 return ret;
3489
3490         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3491         if (&obj->base == NULL) {
3492                 ret = -ENOENT;
3493                 goto unlock;
3494         }
3495
3496         /* Count all active objects as busy, even if they are currently not used
3497          * by the gpu. Users of this interface expect objects to eventually
3498          * become non-busy without any further actions, therefore emit any
3499          * necessary flushes here.
3500          */
3501         args->busy = obj->active;
3502         if (args->busy) {
3503                 /* Unconditionally flush objects, even when the gpu still uses this
3504                  * object. Userspace calling this function indicates that it wants to
3505                  * use this buffer rather sooner than later, so issuing the required
3506                  * flush earlier is beneficial.
3507                  */
3508                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3509                         ret = i915_gem_flush_ring(obj->ring,
3510                                                   0, obj->base.write_domain);
3511                 } else if (obj->ring->outstanding_lazy_request ==
3512                            obj->last_rendering_seqno) {
3513                         struct drm_i915_gem_request *request;
3514
3515                         /* This ring is not being cleared by active usage,
3516                          * so emit a request to do so.
3517                          */
3518                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3519                         if (request)
3520                                 ret = i915_add_request(obj->ring, NULL, request);
3521                         else
3522                                 ret = -ENOMEM;
3523                 }
3524
3525                 /* Update the active list for the hardware's current position.
3526                  * Otherwise this only updates on a delayed timer or when irqs
3527                  * are actually unmasked, and our working set ends up being
3528                  * larger than required.
3529                  */
3530                 i915_gem_retire_requests_ring(obj->ring);
3531
3532                 args->busy = obj->active;
3533         }
3534
3535         drm_gem_object_unreference(&obj->base);
3536 unlock:
3537         mutex_unlock(&dev->struct_mutex);
3538         return ret;
3539 }
3540
3541 int
3542 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3543                         struct drm_file *file_priv)
3544 {
3545         return i915_gem_ring_throttle(dev, file_priv);
3546 }
3547
3548 int
3549 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3550                        struct drm_file *file_priv)
3551 {
3552         struct drm_i915_gem_madvise *args = data;
3553         struct drm_i915_gem_object *obj;
3554         int ret;
3555
3556         switch (args->madv) {
3557         case I915_MADV_DONTNEED:
3558         case I915_MADV_WILLNEED:
3559             break;
3560         default:
3561             return -EINVAL;
3562         }
3563
3564         ret = i915_mutex_lock_interruptible(dev);
3565         if (ret)
3566                 return ret;
3567
3568         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3569         if (&obj->base == NULL) {
3570                 ret = -ENOENT;
3571                 goto unlock;
3572         }
3573
3574         if (obj->pin_count) {
3575                 ret = -EINVAL;
3576                 goto out;
3577         }
3578
3579         if (obj->madv != __I915_MADV_PURGED)
3580                 obj->madv = args->madv;
3581
3582         /* if the object is no longer bound, discard its backing storage */
3583         if (i915_gem_object_is_purgeable(obj) &&
3584             obj->gtt_space == NULL)
3585                 i915_gem_object_truncate(obj);
3586
3587         args->retained = obj->madv != __I915_MADV_PURGED;
3588
3589 out:
3590         drm_gem_object_unreference(&obj->base);
3591 unlock:
3592         mutex_unlock(&dev->struct_mutex);
3593         return ret;
3594 }
3595
3596 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3597                                                   size_t size)
3598 {
3599         struct drm_i915_private *dev_priv = dev->dev_private;
3600         struct drm_i915_gem_object *obj;
3601         struct address_space *mapping;
3602
3603         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3604         if (obj == NULL)
3605                 return NULL;
3606
3607         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3608                 kfree(obj);
3609                 return NULL;
3610         }
3611
3612         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3613         mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3614
3615         i915_gem_info_add_obj(dev_priv, size);
3616
3617         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3618         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3619
3620         if (IS_GEN6(dev)) {
3621                 /* On Gen6, we can have the GPU use the LLC (the CPU
3622                  * cache) for about a 10% performance improvement
3623                  * compared to uncached.  Graphics requests other than
3624                  * display scanout are coherent with the CPU in
3625                  * accessing this cache.  This means in this mode we
3626                  * don't need to clflush on the CPU side, and on the
3627                  * GPU side we only need to flush internal caches to
3628                  * get data visible to the CPU.
3629                  *
3630                  * However, we maintain the display planes as UC, and so
3631                  * need to rebind when first used as such.
3632                  */
3633                 obj->cache_level = I915_CACHE_LLC;
3634         } else
3635                 obj->cache_level = I915_CACHE_NONE;
3636
3637         obj->base.driver_private = NULL;
3638         obj->fence_reg = I915_FENCE_REG_NONE;
3639         INIT_LIST_HEAD(&obj->mm_list);
3640         INIT_LIST_HEAD(&obj->gtt_list);
3641         INIT_LIST_HEAD(&obj->ring_list);
3642         INIT_LIST_HEAD(&obj->exec_list);
3643         INIT_LIST_HEAD(&obj->gpu_write_list);
3644         obj->madv = I915_MADV_WILLNEED;
3645         /* Avoid an unnecessary call to unbind on the first bind. */
3646         obj->map_and_fenceable = true;
3647
3648         return obj;
3649 }
3650
3651 int i915_gem_init_object(struct drm_gem_object *obj)
3652 {
3653         BUG();
3654
3655         return 0;
3656 }
3657
3658 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3659 {
3660         struct drm_device *dev = obj->base.dev;
3661         drm_i915_private_t *dev_priv = dev->dev_private;
3662         int ret;
3663
3664         ret = i915_gem_object_unbind(obj);
3665         if (ret == -ERESTARTSYS) {
3666                 list_move(&obj->mm_list,
3667                           &dev_priv->mm.deferred_free_list);
3668                 return;
3669         }
3670
3671         trace_i915_gem_object_destroy(obj);
3672
3673         if (obj->base.map_list.map)
3674                 drm_gem_free_mmap_offset(&obj->base);
3675
3676         drm_gem_object_release(&obj->base);
3677         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3678
3679         kfree(obj->page_cpu_valid);
3680         kfree(obj->bit_17);
3681         kfree(obj);
3682 }
3683
3684 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3685 {
3686         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3687         struct drm_device *dev = obj->base.dev;
3688
3689         while (obj->pin_count > 0)
3690                 i915_gem_object_unpin(obj);
3691
3692         if (obj->phys_obj)
3693                 i915_gem_detach_phys_object(dev, obj);
3694
3695         i915_gem_free_object_tail(obj);
3696 }
3697
3698 int
3699 i915_gem_idle(struct drm_device *dev)
3700 {
3701         drm_i915_private_t *dev_priv = dev->dev_private;
3702         int ret;
3703
3704         mutex_lock(&dev->struct_mutex);
3705
3706         if (dev_priv->mm.suspended) {
3707                 mutex_unlock(&dev->struct_mutex);
3708                 return 0;
3709         }
3710
3711         ret = i915_gpu_idle(dev);
3712         if (ret) {
3713                 mutex_unlock(&dev->struct_mutex);
3714                 return ret;
3715         }
3716
3717         /* Under UMS, be paranoid and evict. */
3718         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3719                 ret = i915_gem_evict_inactive(dev, false);
3720                 if (ret) {
3721                         mutex_unlock(&dev->struct_mutex);
3722                         return ret;
3723                 }
3724         }
3725
3726         i915_gem_reset_fences(dev);
3727
3728         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3729          * We need to replace this with a semaphore, or something.
3730          * And not confound mm.suspended!
3731          */
3732         dev_priv->mm.suspended = 1;
3733         del_timer_sync(&dev_priv->hangcheck_timer);
3734
3735         i915_kernel_lost_context(dev);
3736         i915_gem_cleanup_ringbuffer(dev);
3737
3738         mutex_unlock(&dev->struct_mutex);
3739
3740         /* Cancel the retire work handler, which should be idle now. */
3741         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3742
3743         return 0;
3744 }
3745
3746 int
3747 i915_gem_init_ringbuffer(struct drm_device *dev)
3748 {
3749         drm_i915_private_t *dev_priv = dev->dev_private;
3750         int ret;
3751
3752         ret = intel_init_render_ring_buffer(dev);
3753         if (ret)
3754                 return ret;
3755
3756         if (HAS_BSD(dev)) {
3757                 ret = intel_init_bsd_ring_buffer(dev);
3758                 if (ret)
3759                         goto cleanup_render_ring;
3760         }
3761
3762         if (HAS_BLT(dev)) {
3763                 ret = intel_init_blt_ring_buffer(dev);
3764                 if (ret)
3765                         goto cleanup_bsd_ring;
3766         }
3767
3768         dev_priv->next_seqno = 1;
3769
3770         return 0;
3771
3772 cleanup_bsd_ring:
3773         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3774 cleanup_render_ring:
3775         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3776         return ret;
3777 }
3778
3779 void
3780 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3781 {
3782         drm_i915_private_t *dev_priv = dev->dev_private;
3783         int i;
3784
3785         for (i = 0; i < I915_NUM_RINGS; i++)
3786                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3787 }
3788
3789 int
3790 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3791                        struct drm_file *file_priv)
3792 {
3793         drm_i915_private_t *dev_priv = dev->dev_private;
3794         int ret, i;
3795
3796         if (drm_core_check_feature(dev, DRIVER_MODESET))
3797                 return 0;
3798
3799         if (atomic_read(&dev_priv->mm.wedged)) {
3800                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3801                 atomic_set(&dev_priv->mm.wedged, 0);
3802         }
3803
3804         mutex_lock(&dev->struct_mutex);
3805         dev_priv->mm.suspended = 0;
3806
3807         ret = i915_gem_init_ringbuffer(dev);
3808         if (ret != 0) {
3809                 mutex_unlock(&dev->struct_mutex);
3810                 return ret;
3811         }
3812
3813         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3814         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3815         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3816         for (i = 0; i < I915_NUM_RINGS; i++) {
3817                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3818                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3819         }
3820         mutex_unlock(&dev->struct_mutex);
3821
3822         ret = drm_irq_install(dev);
3823         if (ret)
3824                 goto cleanup_ringbuffer;
3825
3826         return 0;
3827
3828 cleanup_ringbuffer:
3829         mutex_lock(&dev->struct_mutex);
3830         i915_gem_cleanup_ringbuffer(dev);
3831         dev_priv->mm.suspended = 1;
3832         mutex_unlock(&dev->struct_mutex);
3833
3834         return ret;
3835 }
3836
3837 int
3838 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3839                        struct drm_file *file_priv)
3840 {
3841         if (drm_core_check_feature(dev, DRIVER_MODESET))
3842                 return 0;
3843
3844         drm_irq_uninstall(dev);
3845         return i915_gem_idle(dev);
3846 }
3847
3848 void
3849 i915_gem_lastclose(struct drm_device *dev)
3850 {
3851         int ret;
3852
3853         if (drm_core_check_feature(dev, DRIVER_MODESET))
3854                 return;
3855
3856         ret = i915_gem_idle(dev);
3857         if (ret)
3858                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3859 }
3860
3861 static void
3862 init_ring_lists(struct intel_ring_buffer *ring)
3863 {
3864         INIT_LIST_HEAD(&ring->active_list);
3865         INIT_LIST_HEAD(&ring->request_list);
3866         INIT_LIST_HEAD(&ring->gpu_write_list);
3867 }
3868
3869 void
3870 i915_gem_load(struct drm_device *dev)
3871 {
3872         int i;
3873         drm_i915_private_t *dev_priv = dev->dev_private;
3874
3875         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3876         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3877         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3878         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3879         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3880         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3881         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3882         for (i = 0; i < I915_NUM_RINGS; i++)
3883                 init_ring_lists(&dev_priv->ring[i]);
3884         for (i = 0; i < 16; i++)
3885                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3886         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3887                           i915_gem_retire_work_handler);
3888         init_completion(&dev_priv->error_completion);
3889
3890         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3891         if (IS_GEN3(dev)) {
3892                 u32 tmp = I915_READ(MI_ARB_STATE);
3893                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3894                         /* arb state is a masked write, so set bit + bit in mask */
3895                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3896                         I915_WRITE(MI_ARB_STATE, tmp);
3897                 }
3898         }
3899
3900         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3901
3902         /* Old X drivers will take 0-2 for front, back, depth buffers */
3903         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3904                 dev_priv->fence_reg_start = 3;
3905
3906         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3907                 dev_priv->num_fence_regs = 16;
3908         else
3909                 dev_priv->num_fence_regs = 8;
3910
3911         /* Initialize fence registers to zero */
3912         for (i = 0; i < dev_priv->num_fence_regs; i++) {
3913                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3914         }
3915
3916         i915_gem_detect_bit_6_swizzle(dev);
3917         init_waitqueue_head(&dev_priv->pending_flip_queue);
3918
3919         dev_priv->mm.interruptible = true;
3920
3921         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3922         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3923         register_shrinker(&dev_priv->mm.inactive_shrinker);
3924 }
3925
3926 /*
3927  * Create a physically contiguous memory object for this object
3928  * e.g. for cursor + overlay regs
3929  */
3930 static int i915_gem_init_phys_object(struct drm_device *dev,
3931                                      int id, int size, int align)
3932 {
3933         drm_i915_private_t *dev_priv = dev->dev_private;
3934         struct drm_i915_gem_phys_object *phys_obj;
3935         int ret;
3936
3937         if (dev_priv->mm.phys_objs[id - 1] || !size)
3938                 return 0;
3939
3940         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3941         if (!phys_obj)
3942                 return -ENOMEM;
3943
3944         phys_obj->id = id;
3945
3946         phys_obj->handle = drm_pci_alloc(dev, size, align);
3947         if (!phys_obj->handle) {
3948                 ret = -ENOMEM;
3949                 goto kfree_obj;
3950         }
3951 #ifdef CONFIG_X86
3952         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3953 #endif
3954
3955         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3956
3957         return 0;
3958 kfree_obj:
3959         kfree(phys_obj);
3960         return ret;
3961 }
3962
3963 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3964 {
3965         drm_i915_private_t *dev_priv = dev->dev_private;
3966         struct drm_i915_gem_phys_object *phys_obj;
3967
3968         if (!dev_priv->mm.phys_objs[id - 1])
3969                 return;
3970
3971         phys_obj = dev_priv->mm.phys_objs[id - 1];
3972         if (phys_obj->cur_obj) {
3973                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3974         }
3975
3976 #ifdef CONFIG_X86
3977         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3978 #endif
3979         drm_pci_free(dev, phys_obj->handle);
3980         kfree(phys_obj);
3981         dev_priv->mm.phys_objs[id - 1] = NULL;
3982 }
3983
3984 void i915_gem_free_all_phys_object(struct drm_device *dev)
3985 {
3986         int i;
3987
3988         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3989                 i915_gem_free_phys_object(dev, i);
3990 }
3991
3992 void i915_gem_detach_phys_object(struct drm_device *dev,
3993                                  struct drm_i915_gem_object *obj)
3994 {
3995         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3996         char *vaddr;
3997         int i;
3998         int page_count;
3999
4000         if (!obj->phys_obj)
4001                 return;
4002         vaddr = obj->phys_obj->handle->vaddr;
4003
4004         page_count = obj->base.size / PAGE_SIZE;
4005         for (i = 0; i < page_count; i++) {
4006                 struct page *page = shmem_read_mapping_page(mapping, i);
4007                 if (!IS_ERR(page)) {
4008                         char *dst = kmap_atomic(page);
4009                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4010                         kunmap_atomic(dst);
4011
4012                         drm_clflush_pages(&page, 1);
4013
4014                         set_page_dirty(page);
4015                         mark_page_accessed(page);
4016                         page_cache_release(page);
4017                 }
4018         }
4019         intel_gtt_chipset_flush();
4020
4021         obj->phys_obj->cur_obj = NULL;
4022         obj->phys_obj = NULL;
4023 }
4024
4025 int
4026 i915_gem_attach_phys_object(struct drm_device *dev,
4027                             struct drm_i915_gem_object *obj,
4028                             int id,
4029                             int align)
4030 {
4031         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4032         drm_i915_private_t *dev_priv = dev->dev_private;
4033         int ret = 0;
4034         int page_count;
4035         int i;
4036
4037         if (id > I915_MAX_PHYS_OBJECT)
4038                 return -EINVAL;
4039
4040         if (obj->phys_obj) {
4041                 if (obj->phys_obj->id == id)
4042                         return 0;
4043                 i915_gem_detach_phys_object(dev, obj);
4044         }
4045
4046         /* create a new object */
4047         if (!dev_priv->mm.phys_objs[id - 1]) {
4048                 ret = i915_gem_init_phys_object(dev, id,
4049                                                 obj->base.size, align);
4050                 if (ret) {
4051                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4052                                   id, obj->base.size);
4053                         return ret;
4054                 }
4055         }
4056
4057         /* bind to the object */
4058         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4059         obj->phys_obj->cur_obj = obj;
4060
4061         page_count = obj->base.size / PAGE_SIZE;
4062
4063         for (i = 0; i < page_count; i++) {
4064                 struct page *page;
4065                 char *dst, *src;
4066
4067                 page = shmem_read_mapping_page(mapping, i);
4068                 if (IS_ERR(page))
4069                         return PTR_ERR(page);
4070
4071                 src = kmap_atomic(page);
4072                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4073                 memcpy(dst, src, PAGE_SIZE);
4074                 kunmap_atomic(src);
4075
4076                 mark_page_accessed(page);
4077                 page_cache_release(page);
4078         }
4079
4080         return 0;
4081 }
4082
4083 static int
4084 i915_gem_phys_pwrite(struct drm_device *dev,
4085                      struct drm_i915_gem_object *obj,
4086                      struct drm_i915_gem_pwrite *args,
4087                      struct drm_file *file_priv)
4088 {
4089         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4090         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4091
4092         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4093                 unsigned long unwritten;
4094
4095                 /* The physical object once assigned is fixed for the lifetime
4096                  * of the obj, so we can safely drop the lock and continue
4097                  * to access vaddr.
4098                  */
4099                 mutex_unlock(&dev->struct_mutex);
4100                 unwritten = copy_from_user(vaddr, user_data, args->size);
4101                 mutex_lock(&dev->struct_mutex);
4102                 if (unwritten)
4103                         return -EFAULT;
4104         }
4105
4106         intel_gtt_chipset_flush();
4107         return 0;
4108 }
4109
4110 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4111 {
4112         struct drm_i915_file_private *file_priv = file->driver_priv;
4113
4114         /* Clean up our request list when the client is going away, so that
4115          * later retire_requests won't dereference our soon-to-be-gone
4116          * file_priv.
4117          */
4118         spin_lock(&file_priv->mm.lock);
4119         while (!list_empty(&file_priv->mm.request_list)) {
4120                 struct drm_i915_gem_request *request;
4121
4122                 request = list_first_entry(&file_priv->mm.request_list,
4123                                            struct drm_i915_gem_request,
4124                                            client_list);
4125                 list_del(&request->client_list);
4126                 request->file_priv = NULL;
4127         }
4128         spin_unlock(&file_priv->mm.lock);
4129 }
4130
4131 static int
4132 i915_gpu_is_active(struct drm_device *dev)
4133 {
4134         drm_i915_private_t *dev_priv = dev->dev_private;
4135         int lists_empty;
4136
4137         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4138                       list_empty(&dev_priv->mm.active_list);
4139
4140         return !lists_empty;
4141 }
4142
4143 static int
4144 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4145 {
4146         struct drm_i915_private *dev_priv =
4147                 container_of(shrinker,
4148                              struct drm_i915_private,
4149                              mm.inactive_shrinker);
4150         struct drm_device *dev = dev_priv->dev;
4151         struct drm_i915_gem_object *obj, *next;
4152         int nr_to_scan = sc->nr_to_scan;
4153         int cnt;
4154
4155         if (!mutex_trylock(&dev->struct_mutex))
4156                 return 0;
4157
4158         /* "fast-path" to count number of available objects */
4159         if (nr_to_scan == 0) {
4160                 cnt = 0;
4161                 list_for_each_entry(obj,
4162                                     &dev_priv->mm.inactive_list,
4163                                     mm_list)
4164                         cnt++;
4165                 mutex_unlock(&dev->struct_mutex);
4166                 return cnt / 100 * sysctl_vfs_cache_pressure;
4167         }
4168
4169 rescan:
4170         /* first scan for clean buffers */
4171         i915_gem_retire_requests(dev);
4172
4173         list_for_each_entry_safe(obj, next,
4174                                  &dev_priv->mm.inactive_list,
4175                                  mm_list) {
4176                 if (i915_gem_object_is_purgeable(obj)) {
4177                         if (i915_gem_object_unbind(obj) == 0 &&
4178                             --nr_to_scan == 0)
4179                                 break;
4180                 }
4181         }
4182
4183         /* second pass, evict/count anything still on the inactive list */
4184         cnt = 0;
4185         list_for_each_entry_safe(obj, next,
4186                                  &dev_priv->mm.inactive_list,
4187                                  mm_list) {
4188                 if (nr_to_scan &&
4189                     i915_gem_object_unbind(obj) == 0)
4190                         nr_to_scan--;
4191                 else
4192                         cnt++;
4193         }
4194
4195         if (nr_to_scan && i915_gpu_is_active(dev)) {
4196                 /*
4197                  * We are desperate for pages, so as a last resort, wait
4198                  * for the GPU to finish and discard whatever we can.
4199                  * This has a dramatic impact to reduce the number of
4200                  * OOM-killer events whilst running the GPU aggressively.
4201                  */
4202                 if (i915_gpu_idle(dev) == 0)
4203                         goto rescan;
4204         }
4205         mutex_unlock(&dev->struct_mutex);
4206         return cnt / 100 * sysctl_vfs_cache_pressure;
4207 }