2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 bool map_and_fenceable,
46 static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
51 static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
57 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
60 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
61 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
63 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
66 i915_gem_release_mmap(obj);
68 /* As we do not have an associated fence register, we will force
69 * a tiling change if we ever need to acquire one.
71 obj->fence_dirty = false;
72 obj->fence_reg = I915_FENCE_REG_NONE;
75 /* some bookkeeping */
76 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
79 dev_priv->mm.object_count++;
80 dev_priv->mm.object_memory += size;
83 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
86 dev_priv->mm.object_count--;
87 dev_priv->mm.object_memory -= size;
91 i915_gem_wait_for_error(struct drm_device *dev)
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 struct completion *x = &dev_priv->error_completion;
98 if (!atomic_read(&dev_priv->mm.wedged))
102 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
103 * userspace. If it takes that long something really bad is going on and
104 * we should simply try to bail out and fail as gracefully as possible.
106 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
114 if (atomic_read(&dev_priv->mm.wedged)) {
115 /* GPU is hung, bump the completion count to account for
116 * the token we just consumed so that we never hit zero and
117 * end up waiting upon a subsequent completion event that
120 spin_lock_irqsave(&x->wait.lock, flags);
122 spin_unlock_irqrestore(&x->wait.lock, flags);
127 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 ret = i915_gem_wait_for_error(dev);
135 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 WARN_ON(i915_verify_lists(dev));
144 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
146 return obj->gtt_space && !obj->active;
150 i915_gem_init_ioctl(struct drm_device *dev, void *data,
151 struct drm_file *file)
153 struct drm_i915_gem_init *args = data;
155 if (drm_core_check_feature(dev, DRIVER_MODESET))
158 if (args->gtt_start >= args->gtt_end ||
159 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
162 /* GEM with user mode setting was never supported on ilk and later. */
163 if (INTEL_INFO(dev)->gen >= 5)
166 mutex_lock(&dev->struct_mutex);
167 i915_gem_init_global_gtt(dev, args->gtt_start,
168 args->gtt_end, args->gtt_end);
169 mutex_unlock(&dev->struct_mutex);
175 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
176 struct drm_file *file)
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct drm_i915_gem_get_aperture *args = data;
180 struct drm_i915_gem_object *obj;
184 mutex_lock(&dev->struct_mutex);
185 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
187 pinned += obj->gtt_space->size;
188 mutex_unlock(&dev->struct_mutex);
190 args->aper_size = dev_priv->mm.gtt_total;
191 args->aper_available_size = args->aper_size - pinned;
197 i915_gem_create(struct drm_file *file,
198 struct drm_device *dev,
202 struct drm_i915_gem_object *obj;
206 size = roundup(size, PAGE_SIZE);
210 /* Allocate the new object */
211 obj = i915_gem_alloc_object(dev, size);
215 ret = drm_gem_handle_create(file, &obj->base, &handle);
217 drm_gem_object_release(&obj->base);
218 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
223 /* drop reference from allocate - handle holds it now */
224 drm_gem_object_unreference(&obj->base);
225 trace_i915_gem_object_create(obj);
232 i915_gem_dumb_create(struct drm_file *file,
233 struct drm_device *dev,
234 struct drm_mode_create_dumb *args)
236 /* have to work out size/pitch and return them */
237 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
238 args->size = args->pitch * args->height;
239 return i915_gem_create(file, dev,
240 args->size, &args->handle);
243 int i915_gem_dumb_destroy(struct drm_file *file,
244 struct drm_device *dev,
247 return drm_gem_handle_delete(file, handle);
251 * Creates a new mm object and returns a handle to it.
254 i915_gem_create_ioctl(struct drm_device *dev, void *data,
255 struct drm_file *file)
257 struct drm_i915_gem_create *args = data;
259 return i915_gem_create(file, dev,
260 args->size, &args->handle);
263 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
265 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
267 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
268 obj->tiling_mode != I915_TILING_NONE;
272 __copy_to_user_swizzled(char __user *cpu_vaddr,
273 const char *gpu_vaddr, int gpu_offset,
276 int ret, cpu_offset = 0;
279 int cacheline_end = ALIGN(gpu_offset + 1, 64);
280 int this_length = min(cacheline_end - gpu_offset, length);
281 int swizzled_gpu_offset = gpu_offset ^ 64;
283 ret = __copy_to_user(cpu_vaddr + cpu_offset,
284 gpu_vaddr + swizzled_gpu_offset,
289 cpu_offset += this_length;
290 gpu_offset += this_length;
291 length -= this_length;
298 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
299 const char __user *cpu_vaddr,
302 int ret, cpu_offset = 0;
305 int cacheline_end = ALIGN(gpu_offset + 1, 64);
306 int this_length = min(cacheline_end - gpu_offset, length);
307 int swizzled_gpu_offset = gpu_offset ^ 64;
309 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
310 cpu_vaddr + cpu_offset,
315 cpu_offset += this_length;
316 gpu_offset += this_length;
317 length -= this_length;
323 /* Per-page copy function for the shmem pread fastpath.
324 * Flushes invalid cachelines before reading the target if
325 * needs_clflush is set. */
327 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
328 char __user *user_data,
329 bool page_do_bit17_swizzling, bool needs_clflush)
334 if (unlikely(page_do_bit17_swizzling))
337 vaddr = kmap_atomic(page);
339 drm_clflush_virt_range(vaddr + shmem_page_offset,
341 ret = __copy_to_user_inatomic(user_data,
342 vaddr + shmem_page_offset,
344 kunmap_atomic(vaddr);
350 shmem_clflush_swizzled_range(char *addr, unsigned long length,
353 if (unlikely(swizzled)) {
354 unsigned long start = (unsigned long) addr;
355 unsigned long end = (unsigned long) addr + length;
357 /* For swizzling simply ensure that we always flush both
358 * channels. Lame, but simple and it works. Swizzled
359 * pwrite/pread is far from a hotpath - current userspace
360 * doesn't use it at all. */
361 start = round_down(start, 128);
362 end = round_up(end, 128);
364 drm_clflush_virt_range((void *)start, end - start);
366 drm_clflush_virt_range(addr, length);
371 /* Only difference to the fast-path function is that this can handle bit17
372 * and uses non-atomic copy and kmap functions. */
374 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
375 char __user *user_data,
376 bool page_do_bit17_swizzling, bool needs_clflush)
383 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
385 page_do_bit17_swizzling);
387 if (page_do_bit17_swizzling)
388 ret = __copy_to_user_swizzled(user_data,
389 vaddr, shmem_page_offset,
392 ret = __copy_to_user(user_data,
393 vaddr + shmem_page_offset,
401 i915_gem_shmem_pread(struct drm_device *dev,
402 struct drm_i915_gem_object *obj,
403 struct drm_i915_gem_pread *args,
404 struct drm_file *file)
406 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
407 char __user *user_data;
410 int shmem_page_offset, page_length, ret = 0;
411 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
412 int hit_slowpath = 0;
414 int needs_clflush = 0;
417 user_data = (char __user *) (uintptr_t) args->data_ptr;
420 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
422 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
423 /* If we're not in the cpu read domain, set ourself into the gtt
424 * read domain and manually flush cachelines (if required). This
425 * optimizes for the case when the gpu will dirty the data
426 * anyway again before the next pread happens. */
427 if (obj->cache_level == I915_CACHE_NONE)
429 if (obj->gtt_space) {
430 ret = i915_gem_object_set_to_gtt_domain(obj, false);
436 offset = args->offset;
441 /* Operation in this page
443 * shmem_page_offset = offset within page in shmem file
444 * page_length = bytes to copy for this page
446 shmem_page_offset = offset_in_page(offset);
447 page_length = remain;
448 if ((shmem_page_offset + page_length) > PAGE_SIZE)
449 page_length = PAGE_SIZE - shmem_page_offset;
452 page = obj->pages[offset >> PAGE_SHIFT];
455 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
463 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
464 (page_to_phys(page) & (1 << 17)) != 0;
466 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
467 user_data, page_do_bit17_swizzling,
473 page_cache_get(page);
474 mutex_unlock(&dev->struct_mutex);
477 ret = fault_in_multipages_writeable(user_data, remain);
478 /* Userspace is tricking us, but we've already clobbered
479 * its pages with the prefault and promised to write the
480 * data up to the first fault. Hence ignore any errors
481 * and just continue. */
486 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
487 user_data, page_do_bit17_swizzling,
490 mutex_lock(&dev->struct_mutex);
491 page_cache_release(page);
493 mark_page_accessed(page);
495 page_cache_release(page);
502 remain -= page_length;
503 user_data += page_length;
504 offset += page_length;
509 /* Fixup: Kill any reinstated backing storage pages */
510 if (obj->madv == __I915_MADV_PURGED)
511 i915_gem_object_truncate(obj);
518 * Reads data from the object referenced by handle.
520 * On error, the contents of *data are undefined.
523 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
524 struct drm_file *file)
526 struct drm_i915_gem_pread *args = data;
527 struct drm_i915_gem_object *obj;
533 if (!access_ok(VERIFY_WRITE,
534 (char __user *)(uintptr_t)args->data_ptr,
538 ret = i915_mutex_lock_interruptible(dev);
542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
543 if (&obj->base == NULL) {
548 /* Bounds check source. */
549 if (args->offset > obj->base.size ||
550 args->size > obj->base.size - args->offset) {
555 /* prime objects have no backing filp to GEM pread/pwrite
558 if (!obj->base.filp) {
563 trace_i915_gem_object_pread(obj, args->offset, args->size);
565 ret = i915_gem_shmem_pread(dev, obj, args, file);
568 drm_gem_object_unreference(&obj->base);
570 mutex_unlock(&dev->struct_mutex);
574 /* This is the fast write path which cannot handle
575 * page faults in the source data
579 fast_user_write(struct io_mapping *mapping,
580 loff_t page_base, int page_offset,
581 char __user *user_data,
584 void __iomem *vaddr_atomic;
586 unsigned long unwritten;
588 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
589 /* We can use the cpu mem copy function because this is X86. */
590 vaddr = (void __force*)vaddr_atomic + page_offset;
591 unwritten = __copy_from_user_inatomic_nocache(vaddr,
593 io_mapping_unmap_atomic(vaddr_atomic);
598 * This is the fast pwrite path, where we copy the data directly from the
599 * user into the GTT, uncached.
602 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
603 struct drm_i915_gem_object *obj,
604 struct drm_i915_gem_pwrite *args,
605 struct drm_file *file)
607 drm_i915_private_t *dev_priv = dev->dev_private;
609 loff_t offset, page_base;
610 char __user *user_data;
611 int page_offset, page_length, ret;
613 ret = i915_gem_object_pin(obj, 0, true, true);
617 ret = i915_gem_object_set_to_gtt_domain(obj, true);
621 ret = i915_gem_object_put_fence(obj);
625 user_data = (char __user *) (uintptr_t) args->data_ptr;
628 offset = obj->gtt_offset + args->offset;
631 /* Operation in this page
633 * page_base = page offset within aperture
634 * page_offset = offset within page
635 * page_length = bytes to copy for this page
637 page_base = offset & PAGE_MASK;
638 page_offset = offset_in_page(offset);
639 page_length = remain;
640 if ((page_offset + remain) > PAGE_SIZE)
641 page_length = PAGE_SIZE - page_offset;
643 /* If we get a fault while copying data, then (presumably) our
644 * source page isn't available. Return the error and we'll
645 * retry in the slow path.
647 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
648 page_offset, user_data, page_length)) {
653 remain -= page_length;
654 user_data += page_length;
655 offset += page_length;
659 i915_gem_object_unpin(obj);
664 /* Per-page copy function for the shmem pwrite fastpath.
665 * Flushes invalid cachelines before writing to the target if
666 * needs_clflush_before is set and flushes out any written cachelines after
667 * writing if needs_clflush is set. */
669 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
670 char __user *user_data,
671 bool page_do_bit17_swizzling,
672 bool needs_clflush_before,
673 bool needs_clflush_after)
678 if (unlikely(page_do_bit17_swizzling))
681 vaddr = kmap_atomic(page);
682 if (needs_clflush_before)
683 drm_clflush_virt_range(vaddr + shmem_page_offset,
685 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
688 if (needs_clflush_after)
689 drm_clflush_virt_range(vaddr + shmem_page_offset,
691 kunmap_atomic(vaddr);
696 /* Only difference to the fast-path function is that this can handle bit17
697 * and uses non-atomic copy and kmap functions. */
699 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
700 char __user *user_data,
701 bool page_do_bit17_swizzling,
702 bool needs_clflush_before,
703 bool needs_clflush_after)
709 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
710 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
712 page_do_bit17_swizzling);
713 if (page_do_bit17_swizzling)
714 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
718 ret = __copy_from_user(vaddr + shmem_page_offset,
721 if (needs_clflush_after)
722 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
724 page_do_bit17_swizzling);
731 i915_gem_shmem_pwrite(struct drm_device *dev,
732 struct drm_i915_gem_object *obj,
733 struct drm_i915_gem_pwrite *args,
734 struct drm_file *file)
736 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
739 char __user *user_data;
740 int shmem_page_offset, page_length, ret = 0;
741 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
742 int hit_slowpath = 0;
743 int needs_clflush_after = 0;
744 int needs_clflush_before = 0;
747 user_data = (char __user *) (uintptr_t) args->data_ptr;
750 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
752 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
753 /* If we're not in the cpu write domain, set ourself into the gtt
754 * write domain and manually flush cachelines (if required). This
755 * optimizes for the case when the gpu will use the data
756 * right away and we therefore have to clflush anyway. */
757 if (obj->cache_level == I915_CACHE_NONE)
758 needs_clflush_after = 1;
759 if (obj->gtt_space) {
760 ret = i915_gem_object_set_to_gtt_domain(obj, true);
765 /* Same trick applies for invalidate partially written cachelines before
767 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
768 && obj->cache_level == I915_CACHE_NONE)
769 needs_clflush_before = 1;
771 offset = args->offset;
776 int partial_cacheline_write;
778 /* Operation in this page
780 * shmem_page_offset = offset within page in shmem file
781 * page_length = bytes to copy for this page
783 shmem_page_offset = offset_in_page(offset);
785 page_length = remain;
786 if ((shmem_page_offset + page_length) > PAGE_SIZE)
787 page_length = PAGE_SIZE - shmem_page_offset;
789 /* If we don't overwrite a cacheline completely we need to be
790 * careful to have up-to-date data by first clflushing. Don't
791 * overcomplicate things and flush the entire patch. */
792 partial_cacheline_write = needs_clflush_before &&
793 ((shmem_page_offset | page_length)
794 & (boot_cpu_data.x86_clflush_size - 1));
797 page = obj->pages[offset >> PAGE_SHIFT];
800 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
808 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
809 (page_to_phys(page) & (1 << 17)) != 0;
811 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
812 user_data, page_do_bit17_swizzling,
813 partial_cacheline_write,
814 needs_clflush_after);
819 page_cache_get(page);
820 mutex_unlock(&dev->struct_mutex);
822 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
823 user_data, page_do_bit17_swizzling,
824 partial_cacheline_write,
825 needs_clflush_after);
827 mutex_lock(&dev->struct_mutex);
828 page_cache_release(page);
830 set_page_dirty(page);
831 mark_page_accessed(page);
833 page_cache_release(page);
840 remain -= page_length;
841 user_data += page_length;
842 offset += page_length;
847 /* Fixup: Kill any reinstated backing storage pages */
848 if (obj->madv == __I915_MADV_PURGED)
849 i915_gem_object_truncate(obj);
850 /* and flush dirty cachelines in case the object isn't in the cpu write
852 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
853 i915_gem_clflush_object(obj);
854 intel_gtt_chipset_flush();
858 if (needs_clflush_after)
859 intel_gtt_chipset_flush();
865 * Writes data to the object referenced by handle.
867 * On error, the contents of the buffer that were to be modified are undefined.
870 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
871 struct drm_file *file)
873 struct drm_i915_gem_pwrite *args = data;
874 struct drm_i915_gem_object *obj;
880 if (!access_ok(VERIFY_READ,
881 (char __user *)(uintptr_t)args->data_ptr,
885 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
890 ret = i915_mutex_lock_interruptible(dev);
894 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
895 if (&obj->base == NULL) {
900 /* Bounds check destination. */
901 if (args->offset > obj->base.size ||
902 args->size > obj->base.size - args->offset) {
907 /* prime objects have no backing filp to GEM pread/pwrite
910 if (!obj->base.filp) {
915 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
918 /* We can only do the GTT pwrite on untiled buffers, as otherwise
919 * it would end up going through the fenced access, and we'll get
920 * different detiling behavior between reading and writing.
921 * pread/pwrite currently are reading and writing from the CPU
922 * perspective, requiring manual detiling by the client.
925 ret = i915_gem_phys_pwrite(dev, obj, args, file);
929 if (obj->cache_level == I915_CACHE_NONE &&
930 obj->tiling_mode == I915_TILING_NONE &&
931 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
932 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
933 /* Note that the gtt paths might fail with non-page-backed user
934 * pointers (e.g. gtt mappings when moving data between
935 * textures). Fallback to the shmem path in that case. */
938 if (ret == -EFAULT || ret == -ENOSPC)
939 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
942 drm_gem_object_unreference(&obj->base);
944 mutex_unlock(&dev->struct_mutex);
949 * Called when user space prepares to use an object with the CPU, either
950 * through the mmap ioctl's mapping or a GTT mapping.
953 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
954 struct drm_file *file)
956 struct drm_i915_gem_set_domain *args = data;
957 struct drm_i915_gem_object *obj;
958 uint32_t read_domains = args->read_domains;
959 uint32_t write_domain = args->write_domain;
962 /* Only handle setting domains to types used by the CPU. */
963 if (write_domain & I915_GEM_GPU_DOMAINS)
966 if (read_domains & I915_GEM_GPU_DOMAINS)
969 /* Having something in the write domain implies it's in the read
970 * domain, and only that read domain. Enforce that in the request.
972 if (write_domain != 0 && read_domains != write_domain)
975 ret = i915_mutex_lock_interruptible(dev);
979 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
980 if (&obj->base == NULL) {
985 if (read_domains & I915_GEM_DOMAIN_GTT) {
986 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
988 /* Silently promote "you're not bound, there was nothing to do"
989 * to success, since the client was just asking us to
990 * make sure everything was done.
995 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
998 drm_gem_object_unreference(&obj->base);
1000 mutex_unlock(&dev->struct_mutex);
1005 * Called when user space has done writes to this buffer
1008 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file)
1011 struct drm_i915_gem_sw_finish *args = data;
1012 struct drm_i915_gem_object *obj;
1015 ret = i915_mutex_lock_interruptible(dev);
1019 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1020 if (&obj->base == NULL) {
1025 /* Pinned buffers may be scanout, so flush the cache */
1027 i915_gem_object_flush_cpu_write_domain(obj);
1029 drm_gem_object_unreference(&obj->base);
1031 mutex_unlock(&dev->struct_mutex);
1036 * Maps the contents of an object, returning the address it is mapped
1039 * While the mapping holds a reference on the contents of the object, it doesn't
1040 * imply a ref on the object itself.
1043 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1044 struct drm_file *file)
1046 struct drm_i915_gem_mmap *args = data;
1047 struct drm_gem_object *obj;
1050 obj = drm_gem_object_lookup(dev, file, args->handle);
1054 /* prime objects have no backing filp to GEM mmap
1058 drm_gem_object_unreference_unlocked(obj);
1062 addr = vm_mmap(obj->filp, 0, args->size,
1063 PROT_READ | PROT_WRITE, MAP_SHARED,
1065 drm_gem_object_unreference_unlocked(obj);
1066 if (IS_ERR((void *)addr))
1069 args->addr_ptr = (uint64_t) addr;
1075 * i915_gem_fault - fault a page into the GTT
1076 * vma: VMA in question
1079 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1080 * from userspace. The fault handler takes care of binding the object to
1081 * the GTT (if needed), allocating and programming a fence register (again,
1082 * only if needed based on whether the old reg is still valid or the object
1083 * is tiled) and inserting a new PTE into the faulting process.
1085 * Note that the faulting process may involve evicting existing objects
1086 * from the GTT and/or fence registers to make room. So performance may
1087 * suffer if the GTT working set is large or there are few fence registers
1090 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1092 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1093 struct drm_device *dev = obj->base.dev;
1094 drm_i915_private_t *dev_priv = dev->dev_private;
1095 pgoff_t page_offset;
1098 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1100 /* We don't use vmf->pgoff since that has the fake offset */
1101 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1104 ret = i915_mutex_lock_interruptible(dev);
1108 trace_i915_gem_object_fault(obj, page_offset, true, write);
1110 /* Now bind it into the GTT if needed */
1111 if (!obj->map_and_fenceable) {
1112 ret = i915_gem_object_unbind(obj);
1116 if (!obj->gtt_space) {
1117 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1121 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1126 if (!obj->has_global_gtt_mapping)
1127 i915_gem_gtt_bind_object(obj, obj->cache_level);
1129 ret = i915_gem_object_get_fence(obj);
1133 if (i915_gem_object_is_inactive(obj))
1134 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1136 obj->fault_mappable = true;
1138 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1141 /* Finally, remap it using the new GTT offset */
1142 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1144 mutex_unlock(&dev->struct_mutex);
1148 /* If this -EIO is due to a gpu hang, give the reset code a
1149 * chance to clean up the mess. Otherwise return the proper
1151 if (!atomic_read(&dev_priv->mm.wedged))
1152 return VM_FAULT_SIGBUS;
1154 /* Give the error handler a chance to run and move the
1155 * objects off the GPU active list. Next time we service the
1156 * fault, we should be able to transition the page into the
1157 * GTT without touching the GPU (and so avoid further
1158 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1159 * with coherency, just lost writes.
1165 return VM_FAULT_NOPAGE;
1167 return VM_FAULT_OOM;
1169 return VM_FAULT_SIGBUS;
1174 * i915_gem_release_mmap - remove physical page mappings
1175 * @obj: obj in question
1177 * Preserve the reservation of the mmapping with the DRM core code, but
1178 * relinquish ownership of the pages back to the system.
1180 * It is vital that we remove the page mapping if we have mapped a tiled
1181 * object through the GTT and then lose the fence register due to
1182 * resource pressure. Similarly if the object has been moved out of the
1183 * aperture, than pages mapped into userspace must be revoked. Removing the
1184 * mapping will then trigger a page fault on the next user access, allowing
1185 * fixup by i915_gem_fault().
1188 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1190 if (!obj->fault_mappable)
1193 if (obj->base.dev->dev_mapping)
1194 unmap_mapping_range(obj->base.dev->dev_mapping,
1195 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1198 obj->fault_mappable = false;
1202 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1206 if (INTEL_INFO(dev)->gen >= 4 ||
1207 tiling_mode == I915_TILING_NONE)
1210 /* Previous chips need a power-of-two fence region when tiling */
1211 if (INTEL_INFO(dev)->gen == 3)
1212 gtt_size = 1024*1024;
1214 gtt_size = 512*1024;
1216 while (gtt_size < size)
1223 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1224 * @obj: object to check
1226 * Return the required GTT alignment for an object, taking into account
1227 * potential fence register mapping.
1230 i915_gem_get_gtt_alignment(struct drm_device *dev,
1235 * Minimum alignment is 4k (GTT page size), but might be greater
1236 * if a fence register is needed for the object.
1238 if (INTEL_INFO(dev)->gen >= 4 ||
1239 tiling_mode == I915_TILING_NONE)
1243 * Previous chips need to be aligned to the size of the smallest
1244 * fence register that can contain the object.
1246 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1250 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1253 * @size: size of the object
1254 * @tiling_mode: tiling mode of the object
1256 * Return the required GTT alignment for an object, only taking into account
1257 * unfenced tiled surface requirements.
1260 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1265 * Minimum alignment is 4k (GTT page size) for sane hw.
1267 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1268 tiling_mode == I915_TILING_NONE)
1271 /* Previous hardware however needs to be aligned to a power-of-two
1272 * tile height. The simplest method for determining this is to reuse
1273 * the power-of-tile object size.
1275 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1278 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1280 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1283 if (obj->base.map_list.map)
1286 ret = drm_gem_create_mmap_offset(&obj->base);
1290 /* Badly fragmented mmap space? The only way we can recover
1291 * space is by destroying unwanted objects. We can't randomly release
1292 * mmap_offsets as userspace expects them to be persistent for the
1293 * lifetime of the objects. The closest we can is to release the
1294 * offsets on purgeable objects by truncating it and marking it purged,
1295 * which prevents userspace from ever using that object again.
1297 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1298 ret = drm_gem_create_mmap_offset(&obj->base);
1302 i915_gem_shrink_all(dev_priv);
1303 return drm_gem_create_mmap_offset(&obj->base);
1306 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1308 if (!obj->base.map_list.map)
1311 drm_gem_free_mmap_offset(&obj->base);
1315 i915_gem_mmap_gtt(struct drm_file *file,
1316 struct drm_device *dev,
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 struct drm_i915_gem_object *obj;
1324 ret = i915_mutex_lock_interruptible(dev);
1328 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1329 if (&obj->base == NULL) {
1334 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1339 if (obj->madv != I915_MADV_WILLNEED) {
1340 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1345 ret = i915_gem_object_create_mmap_offset(obj);
1349 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1352 drm_gem_object_unreference(&obj->base);
1354 mutex_unlock(&dev->struct_mutex);
1359 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1361 * @data: GTT mapping ioctl data
1362 * @file: GEM object info
1364 * Simply returns the fake offset to userspace so it can mmap it.
1365 * The mmap call will end up in drm_gem_mmap(), which will set things
1366 * up so we can get faults in the handler above.
1368 * The fault handler will take care of binding the object into the GTT
1369 * (since it may have been evicted to make room for something), allocating
1370 * a fence register, and mapping the appropriate aperture address into
1374 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1375 struct drm_file *file)
1377 struct drm_i915_gem_mmap_gtt *args = data;
1379 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1382 /* Immediately discard the backing storage */
1384 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1386 struct inode *inode;
1388 i915_gem_object_free_mmap_offset(obj);
1390 if (obj->base.filp == NULL)
1393 /* Our goal here is to return as much of the memory as
1394 * is possible back to the system as we are called from OOM.
1395 * To do this we must instruct the shmfs to drop all of its
1396 * backing pages, *now*.
1398 inode = obj->base.filp->f_path.dentry->d_inode;
1399 shmem_truncate_range(inode, 0, (loff_t)-1);
1401 obj->madv = __I915_MADV_PURGED;
1405 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1407 return obj->madv == I915_MADV_DONTNEED;
1411 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1413 int page_count = obj->base.size / PAGE_SIZE;
1416 BUG_ON(obj->gtt_space);
1418 if (obj->pages == NULL)
1421 BUG_ON(obj->gtt_space);
1422 BUG_ON(obj->madv == __I915_MADV_PURGED);
1424 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1426 /* In the event of a disaster, abandon all caches and
1427 * hope for the best.
1429 WARN_ON(ret != -EIO);
1430 i915_gem_clflush_object(obj);
1431 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1434 if (i915_gem_object_needs_bit17_swizzle(obj))
1435 i915_gem_object_save_bit_17_swizzle(obj);
1437 if (obj->madv == I915_MADV_DONTNEED)
1440 for (i = 0; i < page_count; i++) {
1442 set_page_dirty(obj->pages[i]);
1444 if (obj->madv == I915_MADV_WILLNEED)
1445 mark_page_accessed(obj->pages[i]);
1447 page_cache_release(obj->pages[i]);
1451 drm_free_large(obj->pages);
1454 list_del(&obj->gtt_list);
1456 if (i915_gem_object_is_purgeable(obj))
1457 i915_gem_object_truncate(obj);
1463 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1465 struct drm_i915_gem_object *obj, *next;
1468 list_for_each_entry_safe(obj, next,
1469 &dev_priv->mm.unbound_list,
1471 if (i915_gem_object_is_purgeable(obj) &&
1472 i915_gem_object_put_pages_gtt(obj) == 0) {
1473 count += obj->base.size >> PAGE_SHIFT;
1474 if (count >= target)
1479 list_for_each_entry_safe(obj, next,
1480 &dev_priv->mm.inactive_list,
1482 if (i915_gem_object_is_purgeable(obj) &&
1483 i915_gem_object_unbind(obj) == 0 &&
1484 i915_gem_object_put_pages_gtt(obj) == 0) {
1485 count += obj->base.size >> PAGE_SHIFT;
1486 if (count >= target)
1495 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1497 struct drm_i915_gem_object *obj, *next;
1499 i915_gem_evict_everything(dev_priv->dev);
1501 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1502 i915_gem_object_put_pages_gtt(obj);
1506 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1508 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1510 struct address_space *mapping;
1514 if (obj->pages || obj->sg_table)
1517 /* Assert that the object is not currently in any GPU domain. As it
1518 * wasn't in the GTT, there shouldn't be any way it could have been in
1521 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1522 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1524 /* Get the list of pages out of our struct file. They'll be pinned
1525 * at this point until we release them.
1527 page_count = obj->base.size / PAGE_SIZE;
1528 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1529 if (obj->pages == NULL)
1532 /* Fail silently without starting the shrinker */
1533 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1534 gfp = mapping_gfp_mask(mapping);
1535 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1536 gfp &= ~(__GFP_IO | __GFP_WAIT);
1537 for (i = 0; i < page_count; i++) {
1538 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1540 i915_gem_purge(dev_priv, page_count);
1541 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1544 /* We've tried hard to allocate the memory by reaping
1545 * our own buffer, now let the real VM do its job and
1546 * go down in flames if truly OOM.
1548 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1549 gfp |= __GFP_IO | __GFP_WAIT;
1551 i915_gem_shrink_all(dev_priv);
1552 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1556 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1557 gfp &= ~(__GFP_IO | __GFP_WAIT);
1560 obj->pages[i] = page;
1563 if (i915_gem_object_needs_bit17_swizzle(obj))
1564 i915_gem_object_do_bit_17_swizzle(obj);
1566 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1571 page_cache_release(obj->pages[i]);
1573 drm_free_large(obj->pages);
1575 return PTR_ERR(page);
1579 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1580 struct intel_ring_buffer *ring,
1583 struct drm_device *dev = obj->base.dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1586 BUG_ON(ring == NULL);
1589 /* Add a reference if we're newly entering the active list. */
1591 drm_gem_object_reference(&obj->base);
1595 /* Move from whatever list we were on to the tail of execution. */
1596 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1597 list_move_tail(&obj->ring_list, &ring->active_list);
1599 obj->last_read_seqno = seqno;
1601 if (obj->fenced_gpu_access) {
1602 obj->last_fenced_seqno = seqno;
1604 /* Bump MRU to take account of the delayed flush */
1605 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1606 struct drm_i915_fence_reg *reg;
1608 reg = &dev_priv->fence_regs[obj->fence_reg];
1609 list_move_tail(®->lru_list,
1610 &dev_priv->mm.fence_list);
1616 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1618 struct drm_device *dev = obj->base.dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1621 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1622 BUG_ON(!obj->active);
1624 if (obj->pin_count) /* are we a framebuffer? */
1625 intel_mark_fb_idle(obj);
1627 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1629 list_del_init(&obj->ring_list);
1632 obj->last_read_seqno = 0;
1633 obj->last_write_seqno = 0;
1634 obj->base.write_domain = 0;
1636 obj->last_fenced_seqno = 0;
1637 obj->fenced_gpu_access = false;
1640 drm_gem_object_unreference(&obj->base);
1642 WARN_ON(i915_verify_lists(dev));
1646 i915_gem_get_seqno(struct drm_device *dev)
1648 drm_i915_private_t *dev_priv = dev->dev_private;
1649 u32 seqno = dev_priv->next_seqno;
1651 /* reserve 0 for non-seqno */
1652 if (++dev_priv->next_seqno == 0)
1653 dev_priv->next_seqno = 1;
1659 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1661 if (ring->outstanding_lazy_request == 0)
1662 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1664 return ring->outstanding_lazy_request;
1668 i915_add_request(struct intel_ring_buffer *ring,
1669 struct drm_file *file,
1670 struct drm_i915_gem_request *request)
1672 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1674 u32 request_ring_position;
1679 * Emit any outstanding flushes - execbuf can fail to emit the flush
1680 * after having emitted the batchbuffer command. Hence we need to fix
1681 * things up similar to emitting the lazy request. The difference here
1682 * is that the flush _must_ happen before the next request, no matter
1685 ret = intel_ring_flush_all_caches(ring);
1689 if (request == NULL) {
1690 request = kmalloc(sizeof(*request), GFP_KERNEL);
1691 if (request == NULL)
1695 seqno = i915_gem_next_request_seqno(ring);
1697 /* Record the position of the start of the request so that
1698 * should we detect the updated seqno part-way through the
1699 * GPU processing the request, we never over-estimate the
1700 * position of the head.
1702 request_ring_position = intel_ring_get_tail(ring);
1704 ret = ring->add_request(ring, &seqno);
1710 trace_i915_gem_request_add(ring, seqno);
1712 request->seqno = seqno;
1713 request->ring = ring;
1714 request->tail = request_ring_position;
1715 request->emitted_jiffies = jiffies;
1716 was_empty = list_empty(&ring->request_list);
1717 list_add_tail(&request->list, &ring->request_list);
1718 request->file_priv = NULL;
1721 struct drm_i915_file_private *file_priv = file->driver_priv;
1723 spin_lock(&file_priv->mm.lock);
1724 request->file_priv = file_priv;
1725 list_add_tail(&request->client_list,
1726 &file_priv->mm.request_list);
1727 spin_unlock(&file_priv->mm.lock);
1730 ring->outstanding_lazy_request = 0;
1732 if (!dev_priv->mm.suspended) {
1733 if (i915_enable_hangcheck) {
1734 mod_timer(&dev_priv->hangcheck_timer,
1736 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1739 queue_delayed_work(dev_priv->wq,
1740 &dev_priv->mm.retire_work, HZ);
1741 intel_mark_busy(dev_priv->dev);
1749 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1751 struct drm_i915_file_private *file_priv = request->file_priv;
1756 spin_lock(&file_priv->mm.lock);
1757 if (request->file_priv) {
1758 list_del(&request->client_list);
1759 request->file_priv = NULL;
1761 spin_unlock(&file_priv->mm.lock);
1764 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1765 struct intel_ring_buffer *ring)
1767 while (!list_empty(&ring->request_list)) {
1768 struct drm_i915_gem_request *request;
1770 request = list_first_entry(&ring->request_list,
1771 struct drm_i915_gem_request,
1774 list_del(&request->list);
1775 i915_gem_request_remove_from_client(request);
1779 while (!list_empty(&ring->active_list)) {
1780 struct drm_i915_gem_object *obj;
1782 obj = list_first_entry(&ring->active_list,
1783 struct drm_i915_gem_object,
1786 i915_gem_object_move_to_inactive(obj);
1790 static void i915_gem_reset_fences(struct drm_device *dev)
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1795 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1796 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1798 i915_gem_write_fence(dev, i, NULL);
1801 i915_gem_object_fence_lost(reg->obj);
1805 INIT_LIST_HEAD(®->lru_list);
1808 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1811 void i915_gem_reset(struct drm_device *dev)
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 struct drm_i915_gem_object *obj;
1815 struct intel_ring_buffer *ring;
1818 for_each_ring(ring, dev_priv, i)
1819 i915_gem_reset_ring_lists(dev_priv, ring);
1821 /* Move everything out of the GPU domains to ensure we do any
1822 * necessary invalidation upon reuse.
1824 list_for_each_entry(obj,
1825 &dev_priv->mm.inactive_list,
1828 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1832 /* The fence registers are invalidated so clear them out */
1833 i915_gem_reset_fences(dev);
1837 * This function clears the request list as sequence numbers are passed.
1840 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1845 if (list_empty(&ring->request_list))
1848 WARN_ON(i915_verify_lists(ring->dev));
1850 seqno = ring->get_seqno(ring, true);
1852 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1853 if (seqno >= ring->sync_seqno[i])
1854 ring->sync_seqno[i] = 0;
1856 while (!list_empty(&ring->request_list)) {
1857 struct drm_i915_gem_request *request;
1859 request = list_first_entry(&ring->request_list,
1860 struct drm_i915_gem_request,
1863 if (!i915_seqno_passed(seqno, request->seqno))
1866 trace_i915_gem_request_retire(ring, request->seqno);
1867 /* We know the GPU must have read the request to have
1868 * sent us the seqno + interrupt, so use the position
1869 * of tail of the request to update the last known position
1872 ring->last_retired_head = request->tail;
1874 list_del(&request->list);
1875 i915_gem_request_remove_from_client(request);
1879 /* Move any buffers on the active list that are no longer referenced
1880 * by the ringbuffer to the flushing/inactive lists as appropriate.
1882 while (!list_empty(&ring->active_list)) {
1883 struct drm_i915_gem_object *obj;
1885 obj = list_first_entry(&ring->active_list,
1886 struct drm_i915_gem_object,
1889 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1892 i915_gem_object_move_to_inactive(obj);
1895 if (unlikely(ring->trace_irq_seqno &&
1896 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1897 ring->irq_put(ring);
1898 ring->trace_irq_seqno = 0;
1901 WARN_ON(i915_verify_lists(ring->dev));
1905 i915_gem_retire_requests(struct drm_device *dev)
1907 drm_i915_private_t *dev_priv = dev->dev_private;
1908 struct intel_ring_buffer *ring;
1911 for_each_ring(ring, dev_priv, i)
1912 i915_gem_retire_requests_ring(ring);
1916 i915_gem_retire_work_handler(struct work_struct *work)
1918 drm_i915_private_t *dev_priv;
1919 struct drm_device *dev;
1920 struct intel_ring_buffer *ring;
1924 dev_priv = container_of(work, drm_i915_private_t,
1925 mm.retire_work.work);
1926 dev = dev_priv->dev;
1928 /* Come back later if the device is busy... */
1929 if (!mutex_trylock(&dev->struct_mutex)) {
1930 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1934 i915_gem_retire_requests(dev);
1936 /* Send a periodic flush down the ring so we don't hold onto GEM
1937 * objects indefinitely.
1940 for_each_ring(ring, dev_priv, i) {
1941 if (ring->gpu_caches_dirty)
1942 i915_add_request(ring, NULL, NULL);
1944 idle &= list_empty(&ring->request_list);
1947 if (!dev_priv->mm.suspended && !idle)
1948 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1950 intel_mark_idle(dev);
1952 mutex_unlock(&dev->struct_mutex);
1956 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1959 if (atomic_read(&dev_priv->mm.wedged)) {
1960 struct completion *x = &dev_priv->error_completion;
1961 bool recovery_complete;
1962 unsigned long flags;
1964 /* Give the error handler a chance to run. */
1965 spin_lock_irqsave(&x->wait.lock, flags);
1966 recovery_complete = x->done > 0;
1967 spin_unlock_irqrestore(&x->wait.lock, flags);
1969 /* Non-interruptible callers can't handle -EAGAIN, hence return
1970 * -EIO unconditionally for these. */
1974 /* Recovery complete, but still wedged means reset failure. */
1975 if (recovery_complete)
1985 * Compare seqno against outstanding lazy request. Emit a request if they are
1989 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1993 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1996 if (seqno == ring->outstanding_lazy_request)
1997 ret = i915_add_request(ring, NULL, NULL);
2003 * __wait_seqno - wait until execution of seqno has finished
2004 * @ring: the ring expected to report seqno
2006 * @interruptible: do an interruptible wait (normally yes)
2007 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
2009 * Returns 0 if the seqno was found within the alloted time. Else returns the
2010 * errno with remaining time filled in timeout argument.
2012 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
2013 bool interruptible, struct timespec *timeout)
2015 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2016 struct timespec before, now, wait_time={1,0};
2017 unsigned long timeout_jiffies;
2019 bool wait_forever = true;
2022 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
2025 trace_i915_gem_request_wait_begin(ring, seqno);
2027 if (timeout != NULL) {
2028 wait_time = *timeout;
2029 wait_forever = false;
2032 timeout_jiffies = timespec_to_jiffies(&wait_time);
2034 if (WARN_ON(!ring->irq_get(ring)))
2037 /* Record current time in case interrupted by signal, or wedged * */
2038 getrawmonotonic(&before);
2041 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
2042 atomic_read(&dev_priv->mm.wedged))
2045 end = wait_event_interruptible_timeout(ring->irq_queue,
2049 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
2052 ret = i915_gem_check_wedge(dev_priv, interruptible);
2055 } while (end == 0 && wait_forever);
2057 getrawmonotonic(&now);
2059 ring->irq_put(ring);
2060 trace_i915_gem_request_wait_end(ring, seqno);
2064 struct timespec sleep_time = timespec_sub(now, before);
2065 *timeout = timespec_sub(*timeout, sleep_time);
2070 case -EAGAIN: /* Wedged */
2071 case -ERESTARTSYS: /* Signal */
2073 case 0: /* Timeout */
2075 set_normalized_timespec(timeout, 0, 0);
2077 default: /* Completed */
2078 WARN_ON(end < 0); /* We're not aware of other errors */
2084 * Waits for a sequence number to be signaled, and cleans up the
2085 * request and object lists appropriately for that event.
2088 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
2090 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2095 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
2099 ret = i915_gem_check_olr(ring, seqno);
2103 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
2109 * Ensures that all rendering to the object has completed and the object is
2110 * safe to unbind from the GTT or access from the CPU.
2112 static __must_check int
2113 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2119 /* If there is rendering queued on the buffer being evicted, wait for
2123 seqno = obj->last_write_seqno;
2125 seqno = obj->last_read_seqno;
2129 ret = i915_wait_seqno(obj->ring, seqno);
2133 /* Manually manage the write flush as we may have not yet retired
2136 if (obj->last_write_seqno &&
2137 i915_seqno_passed(seqno, obj->last_write_seqno)) {
2138 obj->last_write_seqno = 0;
2139 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
2142 i915_gem_retire_requests_ring(obj->ring);
2147 * Ensures that an object will eventually get non-busy by flushing any required
2148 * write domains, emitting any outstanding lazy request and retiring and
2149 * completed requests.
2152 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2157 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2161 i915_gem_retire_requests_ring(obj->ring);
2168 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2169 * @DRM_IOCTL_ARGS: standard ioctl arguments
2171 * Returns 0 if successful, else an error is returned with the remaining time in
2172 * the timeout parameter.
2173 * -ETIME: object is still busy after timeout
2174 * -ERESTARTSYS: signal interrupted the wait
2175 * -ENONENT: object doesn't exist
2176 * Also possible, but rare:
2177 * -EAGAIN: GPU wedged
2179 * -ENODEV: Internal IRQ fail
2180 * -E?: The add request failed
2182 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2183 * non-zero timeout parameter the wait ioctl will wait for the given number of
2184 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2185 * without holding struct_mutex the object may become re-busied before this
2186 * function completes. A similar but shorter * race condition exists in the busy
2190 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2192 struct drm_i915_gem_wait *args = data;
2193 struct drm_i915_gem_object *obj;
2194 struct intel_ring_buffer *ring = NULL;
2195 struct timespec timeout_stack, *timeout = NULL;
2199 if (args->timeout_ns >= 0) {
2200 timeout_stack = ns_to_timespec(args->timeout_ns);
2201 timeout = &timeout_stack;
2204 ret = i915_mutex_lock_interruptible(dev);
2208 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2209 if (&obj->base == NULL) {
2210 mutex_unlock(&dev->struct_mutex);
2214 /* Need to make sure the object gets inactive eventually. */
2215 ret = i915_gem_object_flush_active(obj);
2220 seqno = obj->last_read_seqno;
2227 /* Do this after OLR check to make sure we make forward progress polling
2228 * on this IOCTL with a 0 timeout (like busy ioctl)
2230 if (!args->timeout_ns) {
2235 drm_gem_object_unreference(&obj->base);
2236 mutex_unlock(&dev->struct_mutex);
2238 ret = __wait_seqno(ring, seqno, true, timeout);
2240 WARN_ON(!timespec_valid(timeout));
2241 args->timeout_ns = timespec_to_ns(timeout);
2246 drm_gem_object_unreference(&obj->base);
2247 mutex_unlock(&dev->struct_mutex);
2252 * i915_gem_object_sync - sync an object to a ring.
2254 * @obj: object which may be in use on another ring.
2255 * @to: ring we wish to use the object on. May be NULL.
2257 * This code is meant to abstract object synchronization with the GPU.
2258 * Calling with NULL implies synchronizing the object with the CPU
2259 * rather than a particular GPU ring.
2261 * Returns 0 if successful, else propagates up the lower layer error.
2264 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2265 struct intel_ring_buffer *to)
2267 struct intel_ring_buffer *from = obj->ring;
2271 if (from == NULL || to == from)
2274 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2275 return i915_gem_object_wait_rendering(obj, false);
2277 idx = intel_ring_sync_index(from, to);
2279 seqno = obj->last_read_seqno;
2280 if (seqno <= from->sync_seqno[idx])
2283 ret = i915_gem_check_olr(obj->ring, seqno);
2287 ret = to->sync_to(to, from, seqno);
2289 from->sync_seqno[idx] = seqno;
2294 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2296 u32 old_write_domain, old_read_domains;
2298 /* Act a barrier for all accesses through the GTT */
2301 /* Force a pagefault for domain tracking on next user access */
2302 i915_gem_release_mmap(obj);
2304 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2307 old_read_domains = obj->base.read_domains;
2308 old_write_domain = obj->base.write_domain;
2310 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2311 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2313 trace_i915_gem_object_change_domain(obj,
2319 * Unbinds an object from the GTT aperture.
2322 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2324 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2327 if (obj->gtt_space == NULL)
2333 BUG_ON(obj->pages == NULL);
2335 ret = i915_gem_object_finish_gpu(obj);
2338 /* Continue on if we fail due to EIO, the GPU is hung so we
2339 * should be safe and we need to cleanup or else we might
2340 * cause memory corruption through use-after-free.
2343 i915_gem_object_finish_gtt(obj);
2345 /* release the fence reg _after_ flushing */
2346 ret = i915_gem_object_put_fence(obj);
2350 trace_i915_gem_object_unbind(obj);
2352 if (obj->has_global_gtt_mapping)
2353 i915_gem_gtt_unbind_object(obj);
2354 if (obj->has_aliasing_ppgtt_mapping) {
2355 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2356 obj->has_aliasing_ppgtt_mapping = 0;
2358 i915_gem_gtt_finish_object(obj);
2360 list_del(&obj->mm_list);
2361 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2362 /* Avoid an unnecessary call to unbind on rebind. */
2363 obj->map_and_fenceable = true;
2365 drm_mm_put_block(obj->gtt_space);
2366 obj->gtt_space = NULL;
2367 obj->gtt_offset = 0;
2372 static int i915_ring_idle(struct intel_ring_buffer *ring)
2374 if (list_empty(&ring->active_list))
2377 return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2380 int i915_gpu_idle(struct drm_device *dev)
2382 drm_i915_private_t *dev_priv = dev->dev_private;
2383 struct intel_ring_buffer *ring;
2386 /* Flush everything onto the inactive list. */
2387 for_each_ring(ring, dev_priv, i) {
2388 ret = i915_ring_idle(ring);
2392 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2400 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2401 struct drm_i915_gem_object *obj)
2403 drm_i915_private_t *dev_priv = dev->dev_private;
2407 u32 size = obj->gtt_space->size;
2409 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2411 val |= obj->gtt_offset & 0xfffff000;
2412 val |= (uint64_t)((obj->stride / 128) - 1) <<
2413 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2415 if (obj->tiling_mode == I915_TILING_Y)
2416 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2417 val |= I965_FENCE_REG_VALID;
2421 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2422 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2425 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2426 struct drm_i915_gem_object *obj)
2428 drm_i915_private_t *dev_priv = dev->dev_private;
2432 u32 size = obj->gtt_space->size;
2434 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2436 val |= obj->gtt_offset & 0xfffff000;
2437 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2438 if (obj->tiling_mode == I915_TILING_Y)
2439 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2440 val |= I965_FENCE_REG_VALID;
2444 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2445 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2448 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2449 struct drm_i915_gem_object *obj)
2451 drm_i915_private_t *dev_priv = dev->dev_private;
2455 u32 size = obj->gtt_space->size;
2459 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2460 (size & -size) != size ||
2461 (obj->gtt_offset & (size - 1)),
2462 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2463 obj->gtt_offset, obj->map_and_fenceable, size);
2465 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2470 /* Note: pitch better be a power of two tile widths */
2471 pitch_val = obj->stride / tile_width;
2472 pitch_val = ffs(pitch_val) - 1;
2474 val = obj->gtt_offset;
2475 if (obj->tiling_mode == I915_TILING_Y)
2476 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2477 val |= I915_FENCE_SIZE_BITS(size);
2478 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2479 val |= I830_FENCE_REG_VALID;
2484 reg = FENCE_REG_830_0 + reg * 4;
2486 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2488 I915_WRITE(reg, val);
2492 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2493 struct drm_i915_gem_object *obj)
2495 drm_i915_private_t *dev_priv = dev->dev_private;
2499 u32 size = obj->gtt_space->size;
2502 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2503 (size & -size) != size ||
2504 (obj->gtt_offset & (size - 1)),
2505 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2506 obj->gtt_offset, size);
2508 pitch_val = obj->stride / 128;
2509 pitch_val = ffs(pitch_val) - 1;
2511 val = obj->gtt_offset;
2512 if (obj->tiling_mode == I915_TILING_Y)
2513 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2514 val |= I830_FENCE_SIZE_BITS(size);
2515 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2516 val |= I830_FENCE_REG_VALID;
2520 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2521 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2524 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2525 struct drm_i915_gem_object *obj)
2527 switch (INTEL_INFO(dev)->gen) {
2529 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2531 case 4: i965_write_fence_reg(dev, reg, obj); break;
2532 case 3: i915_write_fence_reg(dev, reg, obj); break;
2533 case 2: i830_write_fence_reg(dev, reg, obj); break;
2538 static inline int fence_number(struct drm_i915_private *dev_priv,
2539 struct drm_i915_fence_reg *fence)
2541 return fence - dev_priv->fence_regs;
2544 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2545 struct drm_i915_fence_reg *fence,
2548 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2549 int reg = fence_number(dev_priv, fence);
2551 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2554 obj->fence_reg = reg;
2556 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2558 obj->fence_reg = I915_FENCE_REG_NONE;
2560 list_del_init(&fence->lru_list);
2565 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2567 if (obj->last_fenced_seqno) {
2568 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2572 obj->last_fenced_seqno = 0;
2575 /* Ensure that all CPU reads are completed before installing a fence
2576 * and all writes before removing the fence.
2578 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2581 obj->fenced_gpu_access = false;
2586 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2588 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2591 ret = i915_gem_object_flush_fence(obj);
2595 if (obj->fence_reg == I915_FENCE_REG_NONE)
2598 i915_gem_object_update_fence(obj,
2599 &dev_priv->fence_regs[obj->fence_reg],
2601 i915_gem_object_fence_lost(obj);
2606 static struct drm_i915_fence_reg *
2607 i915_find_fence_reg(struct drm_device *dev)
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610 struct drm_i915_fence_reg *reg, *avail;
2613 /* First try to find a free reg */
2615 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2616 reg = &dev_priv->fence_regs[i];
2620 if (!reg->pin_count)
2627 /* None available, try to steal one or wait for a user to finish */
2628 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2639 * i915_gem_object_get_fence - set up fencing for an object
2640 * @obj: object to map through a fence reg
2642 * When mapping objects through the GTT, userspace wants to be able to write
2643 * to them without having to worry about swizzling if the object is tiled.
2644 * This function walks the fence regs looking for a free one for @obj,
2645 * stealing one if it can't find any.
2647 * It then sets up the reg based on the object's properties: address, pitch
2648 * and tiling format.
2650 * For an untiled surface, this removes any existing fence.
2653 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2655 struct drm_device *dev = obj->base.dev;
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 bool enable = obj->tiling_mode != I915_TILING_NONE;
2658 struct drm_i915_fence_reg *reg;
2661 /* Have we updated the tiling parameters upon the object and so
2662 * will need to serialise the write to the associated fence register?
2664 if (obj->fence_dirty) {
2665 ret = i915_gem_object_flush_fence(obj);
2670 /* Just update our place in the LRU if our fence is getting reused. */
2671 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2672 reg = &dev_priv->fence_regs[obj->fence_reg];
2673 if (!obj->fence_dirty) {
2674 list_move_tail(®->lru_list,
2675 &dev_priv->mm.fence_list);
2678 } else if (enable) {
2679 reg = i915_find_fence_reg(dev);
2684 struct drm_i915_gem_object *old = reg->obj;
2686 ret = i915_gem_object_flush_fence(old);
2690 i915_gem_object_fence_lost(old);
2695 i915_gem_object_update_fence(obj, reg, enable);
2696 obj->fence_dirty = false;
2701 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2702 struct drm_mm_node *gtt_space,
2703 unsigned long cache_level)
2705 struct drm_mm_node *other;
2707 /* On non-LLC machines we have to be careful when putting differing
2708 * types of snoopable memory together to avoid the prefetcher
2709 * crossing memory domains and dieing.
2714 if (gtt_space == NULL)
2717 if (list_empty(>t_space->node_list))
2720 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2721 if (other->allocated && !other->hole_follows && other->color != cache_level)
2724 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2725 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2731 static void i915_gem_verify_gtt(struct drm_device *dev)
2734 struct drm_i915_private *dev_priv = dev->dev_private;
2735 struct drm_i915_gem_object *obj;
2738 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2739 if (obj->gtt_space == NULL) {
2740 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2745 if (obj->cache_level != obj->gtt_space->color) {
2746 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2747 obj->gtt_space->start,
2748 obj->gtt_space->start + obj->gtt_space->size,
2750 obj->gtt_space->color);
2755 if (!i915_gem_valid_gtt_space(dev,
2757 obj->cache_level)) {
2758 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2759 obj->gtt_space->start,
2760 obj->gtt_space->start + obj->gtt_space->size,
2772 * Finds free space in the GTT aperture and binds the object there.
2775 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2777 bool map_and_fenceable,
2780 struct drm_device *dev = obj->base.dev;
2781 drm_i915_private_t *dev_priv = dev->dev_private;
2782 struct drm_mm_node *free_space;
2783 u32 size, fence_size, fence_alignment, unfenced_alignment;
2784 bool mappable, fenceable;
2787 if (obj->madv != I915_MADV_WILLNEED) {
2788 DRM_ERROR("Attempting to bind a purgeable object\n");
2792 fence_size = i915_gem_get_gtt_size(dev,
2795 fence_alignment = i915_gem_get_gtt_alignment(dev,
2798 unfenced_alignment =
2799 i915_gem_get_unfenced_gtt_alignment(dev,
2804 alignment = map_and_fenceable ? fence_alignment :
2806 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2807 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2811 size = map_and_fenceable ? fence_size : obj->base.size;
2813 /* If the object is bigger than the entire aperture, reject it early
2814 * before evicting everything in a vain attempt to find space.
2816 if (obj->base.size >
2817 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2818 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2822 ret = i915_gem_object_get_pages_gtt(obj);
2827 if (map_and_fenceable)
2829 drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2830 size, alignment, obj->cache_level,
2831 0, dev_priv->mm.gtt_mappable_end,
2834 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2835 size, alignment, obj->cache_level,
2838 if (free_space != NULL) {
2839 if (map_and_fenceable)
2841 drm_mm_get_block_range_generic(free_space,
2842 size, alignment, obj->cache_level,
2843 0, dev_priv->mm.gtt_mappable_end,
2847 drm_mm_get_block_generic(free_space,
2848 size, alignment, obj->cache_level,
2851 if (obj->gtt_space == NULL) {
2852 ret = i915_gem_evict_something(dev, size, alignment,
2861 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2863 obj->cache_level))) {
2864 drm_mm_put_block(obj->gtt_space);
2865 obj->gtt_space = NULL;
2870 ret = i915_gem_gtt_prepare_object(obj);
2872 drm_mm_put_block(obj->gtt_space);
2873 obj->gtt_space = NULL;
2877 if (!dev_priv->mm.aliasing_ppgtt)
2878 i915_gem_gtt_bind_object(obj, obj->cache_level);
2880 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2881 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2883 obj->gtt_offset = obj->gtt_space->start;
2886 obj->gtt_space->size == fence_size &&
2887 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2890 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2892 obj->map_and_fenceable = mappable && fenceable;
2894 trace_i915_gem_object_bind(obj, map_and_fenceable);
2895 i915_gem_verify_gtt(dev);
2900 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2902 /* If we don't have a page list set up, then we're not pinned
2903 * to GPU, and we can ignore the cache flush because it'll happen
2904 * again at bind time.
2906 if (obj->pages == NULL)
2909 /* If the GPU is snooping the contents of the CPU cache,
2910 * we do not need to manually clear the CPU cache lines. However,
2911 * the caches are only snooped when the render cache is
2912 * flushed/invalidated. As we always have to emit invalidations
2913 * and flushes when moving into and out of the RENDER domain, correct
2914 * snooping behaviour occurs naturally as the result of our domain
2917 if (obj->cache_level != I915_CACHE_NONE)
2920 trace_i915_gem_object_clflush(obj);
2922 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2925 /** Flushes the GTT write domain for the object if it's dirty. */
2927 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2929 uint32_t old_write_domain;
2931 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2934 /* No actual flushing is required for the GTT write domain. Writes
2935 * to it immediately go to main memory as far as we know, so there's
2936 * no chipset flush. It also doesn't land in render cache.
2938 * However, we do have to enforce the order so that all writes through
2939 * the GTT land before any writes to the device, such as updates to
2944 old_write_domain = obj->base.write_domain;
2945 obj->base.write_domain = 0;
2947 trace_i915_gem_object_change_domain(obj,
2948 obj->base.read_domains,
2952 /** Flushes the CPU write domain for the object if it's dirty. */
2954 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2956 uint32_t old_write_domain;
2958 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2961 i915_gem_clflush_object(obj);
2962 intel_gtt_chipset_flush();
2963 old_write_domain = obj->base.write_domain;
2964 obj->base.write_domain = 0;
2966 trace_i915_gem_object_change_domain(obj,
2967 obj->base.read_domains,
2972 * Moves a single object to the GTT read, and possibly write domain.
2974 * This function returns when the move is complete, including waiting on
2978 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2980 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2981 uint32_t old_write_domain, old_read_domains;
2984 /* Not valid to be called on unbound objects. */
2985 if (obj->gtt_space == NULL)
2988 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2991 ret = i915_gem_object_wait_rendering(obj, !write);
2995 i915_gem_object_flush_cpu_write_domain(obj);
2997 old_write_domain = obj->base.write_domain;
2998 old_read_domains = obj->base.read_domains;
3000 /* It should now be out of any other write domains, and we can update
3001 * the domain values for our changes.
3003 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3004 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3006 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3007 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3011 trace_i915_gem_object_change_domain(obj,
3015 /* And bump the LRU for this access */
3016 if (i915_gem_object_is_inactive(obj))
3017 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3022 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3023 enum i915_cache_level cache_level)
3025 struct drm_device *dev = obj->base.dev;
3026 drm_i915_private_t *dev_priv = dev->dev_private;
3029 if (obj->cache_level == cache_level)
3032 if (obj->pin_count) {
3033 DRM_DEBUG("can not change the cache level of pinned objects\n");
3037 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3038 ret = i915_gem_object_unbind(obj);
3043 if (obj->gtt_space) {
3044 ret = i915_gem_object_finish_gpu(obj);
3048 i915_gem_object_finish_gtt(obj);
3050 /* Before SandyBridge, you could not use tiling or fence
3051 * registers with snooped memory, so relinquish any fences
3052 * currently pointing to our region in the aperture.
3054 if (INTEL_INFO(dev)->gen < 6) {
3055 ret = i915_gem_object_put_fence(obj);
3060 if (obj->has_global_gtt_mapping)
3061 i915_gem_gtt_bind_object(obj, cache_level);
3062 if (obj->has_aliasing_ppgtt_mapping)
3063 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3066 obj->gtt_space->color = cache_level;
3069 if (cache_level == I915_CACHE_NONE) {
3070 u32 old_read_domains, old_write_domain;
3072 /* If we're coming from LLC cached, then we haven't
3073 * actually been tracking whether the data is in the
3074 * CPU cache or not, since we only allow one bit set
3075 * in obj->write_domain and have been skipping the clflushes.
3076 * Just set it to the CPU cache for now.
3078 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3079 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3081 old_read_domains = obj->base.read_domains;
3082 old_write_domain = obj->base.write_domain;
3084 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3085 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3087 trace_i915_gem_object_change_domain(obj,
3092 obj->cache_level = cache_level;
3093 i915_gem_verify_gtt(dev);
3097 int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data,
3098 struct drm_file *file)
3100 struct drm_i915_gem_cacheing *args = data;
3101 struct drm_i915_gem_object *obj;
3104 ret = i915_mutex_lock_interruptible(dev);
3108 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3109 if (&obj->base == NULL) {
3114 args->cacheing = obj->cache_level != I915_CACHE_NONE;
3116 drm_gem_object_unreference(&obj->base);
3118 mutex_unlock(&dev->struct_mutex);
3122 int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data,
3123 struct drm_file *file)
3125 struct drm_i915_gem_cacheing *args = data;
3126 struct drm_i915_gem_object *obj;
3127 enum i915_cache_level level;
3130 ret = i915_mutex_lock_interruptible(dev);
3134 switch (args->cacheing) {
3135 case I915_CACHEING_NONE:
3136 level = I915_CACHE_NONE;
3138 case I915_CACHEING_CACHED:
3139 level = I915_CACHE_LLC;
3145 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3146 if (&obj->base == NULL) {
3151 ret = i915_gem_object_set_cache_level(obj, level);
3153 drm_gem_object_unreference(&obj->base);
3155 mutex_unlock(&dev->struct_mutex);
3160 * Prepare buffer for display plane (scanout, cursors, etc).
3161 * Can be called from an uninterruptible phase (modesetting) and allows
3162 * any flushes to be pipelined (for pageflips).
3165 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3167 struct intel_ring_buffer *pipelined)
3169 u32 old_read_domains, old_write_domain;
3172 if (pipelined != obj->ring) {
3173 ret = i915_gem_object_sync(obj, pipelined);
3178 /* The display engine is not coherent with the LLC cache on gen6. As
3179 * a result, we make sure that the pinning that is about to occur is
3180 * done with uncached PTEs. This is lowest common denominator for all
3183 * However for gen6+, we could do better by using the GFDT bit instead
3184 * of uncaching, which would allow us to flush all the LLC-cached data
3185 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3187 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3191 /* As the user may map the buffer once pinned in the display plane
3192 * (e.g. libkms for the bootup splash), we have to ensure that we
3193 * always use map_and_fenceable for all scanout buffers.
3195 ret = i915_gem_object_pin(obj, alignment, true, false);
3199 i915_gem_object_flush_cpu_write_domain(obj);
3201 old_write_domain = obj->base.write_domain;
3202 old_read_domains = obj->base.read_domains;
3204 /* It should now be out of any other write domains, and we can update
3205 * the domain values for our changes.
3207 obj->base.write_domain = 0;
3208 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3210 trace_i915_gem_object_change_domain(obj,
3218 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3222 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3225 ret = i915_gem_object_wait_rendering(obj, false);
3229 /* Ensure that we invalidate the GPU's caches and TLBs. */
3230 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3235 * Moves a single object to the CPU read, and possibly write domain.
3237 * This function returns when the move is complete, including waiting on
3241 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3243 uint32_t old_write_domain, old_read_domains;
3246 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3249 ret = i915_gem_object_wait_rendering(obj, !write);
3253 i915_gem_object_flush_gtt_write_domain(obj);
3255 old_write_domain = obj->base.write_domain;
3256 old_read_domains = obj->base.read_domains;
3258 /* Flush the CPU cache if it's still invalid. */
3259 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3260 i915_gem_clflush_object(obj);
3262 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3265 /* It should now be out of any other write domains, and we can update
3266 * the domain values for our changes.
3268 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3270 /* If we're writing through the CPU, then the GPU read domains will
3271 * need to be invalidated at next use.
3274 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3275 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3278 trace_i915_gem_object_change_domain(obj,
3285 /* Throttle our rendering by waiting until the ring has completed our requests
3286 * emitted over 20 msec ago.
3288 * Note that if we were to use the current jiffies each time around the loop,
3289 * we wouldn't escape the function with any frames outstanding if the time to
3290 * render a frame was over 20ms.
3292 * This should get us reasonable parallelism between CPU and GPU but also
3293 * relatively low latency when blocking on a particular request to finish.
3296 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 struct drm_i915_file_private *file_priv = file->driver_priv;
3300 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3301 struct drm_i915_gem_request *request;
3302 struct intel_ring_buffer *ring = NULL;
3306 if (atomic_read(&dev_priv->mm.wedged))
3309 spin_lock(&file_priv->mm.lock);
3310 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3311 if (time_after_eq(request->emitted_jiffies, recent_enough))
3314 ring = request->ring;
3315 seqno = request->seqno;
3317 spin_unlock(&file_priv->mm.lock);
3322 ret = __wait_seqno(ring, seqno, true, NULL);
3324 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3330 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3332 bool map_and_fenceable,
3337 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3339 if (obj->gtt_space != NULL) {
3340 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3341 (map_and_fenceable && !obj->map_and_fenceable)) {
3342 WARN(obj->pin_count,
3343 "bo is already pinned with incorrect alignment:"
3344 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3345 " obj->map_and_fenceable=%d\n",
3346 obj->gtt_offset, alignment,
3348 obj->map_and_fenceable);
3349 ret = i915_gem_object_unbind(obj);
3355 if (obj->gtt_space == NULL) {
3356 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3363 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3364 i915_gem_gtt_bind_object(obj, obj->cache_level);
3367 obj->pin_mappable |= map_and_fenceable;
3373 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3375 BUG_ON(obj->pin_count == 0);
3376 BUG_ON(obj->gtt_space == NULL);
3378 if (--obj->pin_count == 0)
3379 obj->pin_mappable = false;
3383 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3384 struct drm_file *file)
3386 struct drm_i915_gem_pin *args = data;
3387 struct drm_i915_gem_object *obj;
3390 ret = i915_mutex_lock_interruptible(dev);
3394 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3395 if (&obj->base == NULL) {
3400 if (obj->madv != I915_MADV_WILLNEED) {
3401 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3406 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3407 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3413 obj->user_pin_count++;
3414 obj->pin_filp = file;
3415 if (obj->user_pin_count == 1) {
3416 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3421 /* XXX - flush the CPU caches for pinned objects
3422 * as the X server doesn't manage domains yet
3424 i915_gem_object_flush_cpu_write_domain(obj);
3425 args->offset = obj->gtt_offset;
3427 drm_gem_object_unreference(&obj->base);
3429 mutex_unlock(&dev->struct_mutex);
3434 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3435 struct drm_file *file)
3437 struct drm_i915_gem_pin *args = data;
3438 struct drm_i915_gem_object *obj;
3441 ret = i915_mutex_lock_interruptible(dev);
3445 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3446 if (&obj->base == NULL) {
3451 if (obj->pin_filp != file) {
3452 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3457 obj->user_pin_count--;
3458 if (obj->user_pin_count == 0) {
3459 obj->pin_filp = NULL;
3460 i915_gem_object_unpin(obj);
3464 drm_gem_object_unreference(&obj->base);
3466 mutex_unlock(&dev->struct_mutex);
3471 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3472 struct drm_file *file)
3474 struct drm_i915_gem_busy *args = data;
3475 struct drm_i915_gem_object *obj;
3478 ret = i915_mutex_lock_interruptible(dev);
3482 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3483 if (&obj->base == NULL) {
3488 /* Count all active objects as busy, even if they are currently not used
3489 * by the gpu. Users of this interface expect objects to eventually
3490 * become non-busy without any further actions, therefore emit any
3491 * necessary flushes here.
3493 ret = i915_gem_object_flush_active(obj);
3495 args->busy = obj->active;
3497 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3498 args->busy |= intel_ring_flag(obj->ring) << 16;
3501 drm_gem_object_unreference(&obj->base);
3503 mutex_unlock(&dev->struct_mutex);
3508 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3509 struct drm_file *file_priv)
3511 return i915_gem_ring_throttle(dev, file_priv);
3515 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3516 struct drm_file *file_priv)
3518 struct drm_i915_gem_madvise *args = data;
3519 struct drm_i915_gem_object *obj;
3522 switch (args->madv) {
3523 case I915_MADV_DONTNEED:
3524 case I915_MADV_WILLNEED:
3530 ret = i915_mutex_lock_interruptible(dev);
3534 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3535 if (&obj->base == NULL) {
3540 if (obj->pin_count) {
3545 if (obj->madv != __I915_MADV_PURGED)
3546 obj->madv = args->madv;
3548 /* if the object is no longer attached, discard its backing storage */
3549 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3550 i915_gem_object_truncate(obj);
3552 args->retained = obj->madv != __I915_MADV_PURGED;
3555 drm_gem_object_unreference(&obj->base);
3557 mutex_unlock(&dev->struct_mutex);
3561 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct drm_i915_gem_object *obj;
3566 struct address_space *mapping;
3569 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3573 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3578 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3579 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3580 /* 965gm cannot relocate objects above 4GiB. */
3581 mask &= ~__GFP_HIGHMEM;
3582 mask |= __GFP_DMA32;
3585 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3586 mapping_set_gfp_mask(mapping, mask);
3588 i915_gem_info_add_obj(dev_priv, size);
3590 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3591 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3594 /* On some devices, we can have the GPU use the LLC (the CPU
3595 * cache) for about a 10% performance improvement
3596 * compared to uncached. Graphics requests other than
3597 * display scanout are coherent with the CPU in
3598 * accessing this cache. This means in this mode we
3599 * don't need to clflush on the CPU side, and on the
3600 * GPU side we only need to flush internal caches to
3601 * get data visible to the CPU.
3603 * However, we maintain the display planes as UC, and so
3604 * need to rebind when first used as such.
3606 obj->cache_level = I915_CACHE_LLC;
3608 obj->cache_level = I915_CACHE_NONE;
3610 obj->base.driver_private = NULL;
3611 obj->fence_reg = I915_FENCE_REG_NONE;
3612 INIT_LIST_HEAD(&obj->mm_list);
3613 INIT_LIST_HEAD(&obj->gtt_list);
3614 INIT_LIST_HEAD(&obj->ring_list);
3615 INIT_LIST_HEAD(&obj->exec_list);
3616 obj->madv = I915_MADV_WILLNEED;
3617 /* Avoid an unnecessary call to unbind on the first bind. */
3618 obj->map_and_fenceable = true;
3623 int i915_gem_init_object(struct drm_gem_object *obj)
3630 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3632 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3633 struct drm_device *dev = obj->base.dev;
3634 drm_i915_private_t *dev_priv = dev->dev_private;
3636 trace_i915_gem_object_destroy(obj);
3638 if (gem_obj->import_attach)
3639 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3642 i915_gem_detach_phys_object(dev, obj);
3645 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3646 bool was_interruptible;
3648 was_interruptible = dev_priv->mm.interruptible;
3649 dev_priv->mm.interruptible = false;
3651 WARN_ON(i915_gem_object_unbind(obj));
3653 dev_priv->mm.interruptible = was_interruptible;
3656 i915_gem_object_put_pages_gtt(obj);
3657 i915_gem_object_free_mmap_offset(obj);
3659 drm_gem_object_release(&obj->base);
3660 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3667 i915_gem_idle(struct drm_device *dev)
3669 drm_i915_private_t *dev_priv = dev->dev_private;
3672 mutex_lock(&dev->struct_mutex);
3674 if (dev_priv->mm.suspended) {
3675 mutex_unlock(&dev->struct_mutex);
3679 ret = i915_gpu_idle(dev);
3681 mutex_unlock(&dev->struct_mutex);
3684 i915_gem_retire_requests(dev);
3686 /* Under UMS, be paranoid and evict. */
3687 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3688 i915_gem_evict_everything(dev);
3690 i915_gem_reset_fences(dev);
3692 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3693 * We need to replace this with a semaphore, or something.
3694 * And not confound mm.suspended!
3696 dev_priv->mm.suspended = 1;
3697 del_timer_sync(&dev_priv->hangcheck_timer);
3699 i915_kernel_lost_context(dev);
3700 i915_gem_cleanup_ringbuffer(dev);
3702 mutex_unlock(&dev->struct_mutex);
3704 /* Cancel the retire work handler, which should be idle now. */
3705 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3710 void i915_gem_l3_remap(struct drm_device *dev)
3712 drm_i915_private_t *dev_priv = dev->dev_private;
3716 if (!IS_IVYBRIDGE(dev))
3719 if (!dev_priv->mm.l3_remap_info)
3722 misccpctl = I915_READ(GEN7_MISCCPCTL);
3723 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3724 POSTING_READ(GEN7_MISCCPCTL);
3726 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3727 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3728 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3729 DRM_DEBUG("0x%x was already programmed to %x\n",
3730 GEN7_L3LOG_BASE + i, remap);
3731 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3732 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3733 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3736 /* Make sure all the writes land before disabling dop clock gating */
3737 POSTING_READ(GEN7_L3LOG_BASE);
3739 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3742 void i915_gem_init_swizzling(struct drm_device *dev)
3744 drm_i915_private_t *dev_priv = dev->dev_private;
3746 if (INTEL_INFO(dev)->gen < 5 ||
3747 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3750 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3751 DISP_TILE_SURFACE_SWIZZLING);
3756 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3758 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3760 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3763 void i915_gem_init_ppgtt(struct drm_device *dev)
3765 drm_i915_private_t *dev_priv = dev->dev_private;
3767 struct intel_ring_buffer *ring;
3768 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3769 uint32_t __iomem *pd_addr;
3773 if (!dev_priv->mm.aliasing_ppgtt)
3777 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3778 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3781 if (dev_priv->mm.gtt->needs_dmar)
3782 pt_addr = ppgtt->pt_dma_addr[i];
3784 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3786 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3787 pd_entry |= GEN6_PDE_VALID;
3789 writel(pd_entry, pd_addr + i);
3793 pd_offset = ppgtt->pd_offset;
3794 pd_offset /= 64; /* in cachelines, */
3797 if (INTEL_INFO(dev)->gen == 6) {
3798 uint32_t ecochk, gab_ctl, ecobits;
3800 ecobits = I915_READ(GAC_ECO_BITS);
3801 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3803 gab_ctl = I915_READ(GAB_CTL);
3804 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3806 ecochk = I915_READ(GAM_ECOCHK);
3807 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3808 ECOCHK_PPGTT_CACHE64B);
3809 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3810 } else if (INTEL_INFO(dev)->gen >= 7) {
3811 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3812 /* GFX_MODE is per-ring on gen7+ */
3815 for_each_ring(ring, dev_priv, i) {
3816 if (INTEL_INFO(dev)->gen >= 7)
3817 I915_WRITE(RING_MODE_GEN7(ring),
3818 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3820 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3821 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3826 intel_enable_blt(struct drm_device *dev)
3831 /* The blitter was dysfunctional on early prototypes */
3832 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3833 DRM_INFO("BLT not supported on this pre-production hardware;"
3834 " graphics performance will be degraded.\n");
3842 i915_gem_init_hw(struct drm_device *dev)
3844 drm_i915_private_t *dev_priv = dev->dev_private;
3847 if (!intel_enable_gtt())
3850 i915_gem_l3_remap(dev);
3852 i915_gem_init_swizzling(dev);
3854 ret = intel_init_render_ring_buffer(dev);
3859 ret = intel_init_bsd_ring_buffer(dev);
3861 goto cleanup_render_ring;
3864 if (intel_enable_blt(dev)) {
3865 ret = intel_init_blt_ring_buffer(dev);
3867 goto cleanup_bsd_ring;
3870 dev_priv->next_seqno = 1;
3873 * XXX: There was some w/a described somewhere suggesting loading
3874 * contexts before PPGTT.
3876 i915_gem_context_init(dev);
3877 i915_gem_init_ppgtt(dev);
3882 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3883 cleanup_render_ring:
3884 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3889 intel_enable_ppgtt(struct drm_device *dev)
3891 if (i915_enable_ppgtt >= 0)
3892 return i915_enable_ppgtt;
3894 #ifdef CONFIG_INTEL_IOMMU
3895 /* Disable ppgtt on SNB if VT-d is on. */
3896 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3903 int i915_gem_init(struct drm_device *dev)
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 unsigned long gtt_size, mappable_size;
3909 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3910 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3912 mutex_lock(&dev->struct_mutex);
3913 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3914 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3915 * aperture accordingly when using aliasing ppgtt. */
3916 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3918 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3920 ret = i915_gem_init_aliasing_ppgtt(dev);
3922 mutex_unlock(&dev->struct_mutex);
3926 /* Let GEM Manage all of the aperture.
3928 * However, leave one page at the end still bound to the scratch
3929 * page. There are a number of places where the hardware
3930 * apparently prefetches past the end of the object, and we've
3931 * seen multiple hangs with the GPU head pointer stuck in a
3932 * batchbuffer bound at the last page of the aperture. One page
3933 * should be enough to keep any prefetching inside of the
3936 i915_gem_init_global_gtt(dev, 0, mappable_size,
3940 ret = i915_gem_init_hw(dev);
3941 mutex_unlock(&dev->struct_mutex);
3943 i915_gem_cleanup_aliasing_ppgtt(dev);
3947 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3948 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3949 dev_priv->dri1.allow_batchbuffer = 1;
3954 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3956 drm_i915_private_t *dev_priv = dev->dev_private;
3957 struct intel_ring_buffer *ring;
3960 for_each_ring(ring, dev_priv, i)
3961 intel_cleanup_ring_buffer(ring);
3965 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3966 struct drm_file *file_priv)
3968 drm_i915_private_t *dev_priv = dev->dev_private;
3971 if (drm_core_check_feature(dev, DRIVER_MODESET))
3974 if (atomic_read(&dev_priv->mm.wedged)) {
3975 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3976 atomic_set(&dev_priv->mm.wedged, 0);
3979 mutex_lock(&dev->struct_mutex);
3980 dev_priv->mm.suspended = 0;
3982 ret = i915_gem_init_hw(dev);
3984 mutex_unlock(&dev->struct_mutex);
3988 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3989 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3990 mutex_unlock(&dev->struct_mutex);
3992 ret = drm_irq_install(dev);
3994 goto cleanup_ringbuffer;
3999 mutex_lock(&dev->struct_mutex);
4000 i915_gem_cleanup_ringbuffer(dev);
4001 dev_priv->mm.suspended = 1;
4002 mutex_unlock(&dev->struct_mutex);
4008 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4009 struct drm_file *file_priv)
4011 if (drm_core_check_feature(dev, DRIVER_MODESET))
4014 drm_irq_uninstall(dev);
4015 return i915_gem_idle(dev);
4019 i915_gem_lastclose(struct drm_device *dev)
4023 if (drm_core_check_feature(dev, DRIVER_MODESET))
4026 ret = i915_gem_idle(dev);
4028 DRM_ERROR("failed to idle hardware: %d\n", ret);
4032 init_ring_lists(struct intel_ring_buffer *ring)
4034 INIT_LIST_HEAD(&ring->active_list);
4035 INIT_LIST_HEAD(&ring->request_list);
4039 i915_gem_load(struct drm_device *dev)
4042 drm_i915_private_t *dev_priv = dev->dev_private;
4044 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4045 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4046 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4047 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4048 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4049 for (i = 0; i < I915_NUM_RINGS; i++)
4050 init_ring_lists(&dev_priv->ring[i]);
4051 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4052 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4053 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4054 i915_gem_retire_work_handler);
4055 init_completion(&dev_priv->error_completion);
4057 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4059 I915_WRITE(MI_ARB_STATE,
4060 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4063 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4065 /* Old X drivers will take 0-2 for front, back, depth buffers */
4066 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4067 dev_priv->fence_reg_start = 3;
4069 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4070 dev_priv->num_fence_regs = 16;
4072 dev_priv->num_fence_regs = 8;
4074 /* Initialize fence registers to zero */
4075 i915_gem_reset_fences(dev);
4077 i915_gem_detect_bit_6_swizzle(dev);
4078 init_waitqueue_head(&dev_priv->pending_flip_queue);
4080 dev_priv->mm.interruptible = true;
4082 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4083 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4084 register_shrinker(&dev_priv->mm.inactive_shrinker);
4088 * Create a physically contiguous memory object for this object
4089 * e.g. for cursor + overlay regs
4091 static int i915_gem_init_phys_object(struct drm_device *dev,
4092 int id, int size, int align)
4094 drm_i915_private_t *dev_priv = dev->dev_private;
4095 struct drm_i915_gem_phys_object *phys_obj;
4098 if (dev_priv->mm.phys_objs[id - 1] || !size)
4101 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4107 phys_obj->handle = drm_pci_alloc(dev, size, align);
4108 if (!phys_obj->handle) {
4113 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4116 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4124 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4126 drm_i915_private_t *dev_priv = dev->dev_private;
4127 struct drm_i915_gem_phys_object *phys_obj;
4129 if (!dev_priv->mm.phys_objs[id - 1])
4132 phys_obj = dev_priv->mm.phys_objs[id - 1];
4133 if (phys_obj->cur_obj) {
4134 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4138 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4140 drm_pci_free(dev, phys_obj->handle);
4142 dev_priv->mm.phys_objs[id - 1] = NULL;
4145 void i915_gem_free_all_phys_object(struct drm_device *dev)
4149 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4150 i915_gem_free_phys_object(dev, i);
4153 void i915_gem_detach_phys_object(struct drm_device *dev,
4154 struct drm_i915_gem_object *obj)
4156 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4163 vaddr = obj->phys_obj->handle->vaddr;
4165 page_count = obj->base.size / PAGE_SIZE;
4166 for (i = 0; i < page_count; i++) {
4167 struct page *page = shmem_read_mapping_page(mapping, i);
4168 if (!IS_ERR(page)) {
4169 char *dst = kmap_atomic(page);
4170 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4173 drm_clflush_pages(&page, 1);
4175 set_page_dirty(page);
4176 mark_page_accessed(page);
4177 page_cache_release(page);
4180 intel_gtt_chipset_flush();
4182 obj->phys_obj->cur_obj = NULL;
4183 obj->phys_obj = NULL;
4187 i915_gem_attach_phys_object(struct drm_device *dev,
4188 struct drm_i915_gem_object *obj,
4192 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4193 drm_i915_private_t *dev_priv = dev->dev_private;
4198 if (id > I915_MAX_PHYS_OBJECT)
4201 if (obj->phys_obj) {
4202 if (obj->phys_obj->id == id)
4204 i915_gem_detach_phys_object(dev, obj);
4207 /* create a new object */
4208 if (!dev_priv->mm.phys_objs[id - 1]) {
4209 ret = i915_gem_init_phys_object(dev, id,
4210 obj->base.size, align);
4212 DRM_ERROR("failed to init phys object %d size: %zu\n",
4213 id, obj->base.size);
4218 /* bind to the object */
4219 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4220 obj->phys_obj->cur_obj = obj;
4222 page_count = obj->base.size / PAGE_SIZE;
4224 for (i = 0; i < page_count; i++) {
4228 page = shmem_read_mapping_page(mapping, i);
4230 return PTR_ERR(page);
4232 src = kmap_atomic(page);
4233 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4234 memcpy(dst, src, PAGE_SIZE);
4237 mark_page_accessed(page);
4238 page_cache_release(page);
4245 i915_gem_phys_pwrite(struct drm_device *dev,
4246 struct drm_i915_gem_object *obj,
4247 struct drm_i915_gem_pwrite *args,
4248 struct drm_file *file_priv)
4250 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4251 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4253 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4254 unsigned long unwritten;
4256 /* The physical object once assigned is fixed for the lifetime
4257 * of the obj, so we can safely drop the lock and continue
4260 mutex_unlock(&dev->struct_mutex);
4261 unwritten = copy_from_user(vaddr, user_data, args->size);
4262 mutex_lock(&dev->struct_mutex);
4267 intel_gtt_chipset_flush();
4271 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4273 struct drm_i915_file_private *file_priv = file->driver_priv;
4275 /* Clean up our request list when the client is going away, so that
4276 * later retire_requests won't dereference our soon-to-be-gone
4279 spin_lock(&file_priv->mm.lock);
4280 while (!list_empty(&file_priv->mm.request_list)) {
4281 struct drm_i915_gem_request *request;
4283 request = list_first_entry(&file_priv->mm.request_list,
4284 struct drm_i915_gem_request,
4286 list_del(&request->client_list);
4287 request->file_priv = NULL;
4289 spin_unlock(&file_priv->mm.lock);
4293 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4295 struct drm_i915_private *dev_priv =
4296 container_of(shrinker,
4297 struct drm_i915_private,
4298 mm.inactive_shrinker);
4299 struct drm_device *dev = dev_priv->dev;
4300 struct drm_i915_gem_object *obj;
4301 int nr_to_scan = sc->nr_to_scan;
4304 if (!mutex_trylock(&dev->struct_mutex))
4308 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4310 i915_gem_shrink_all(dev_priv);
4314 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4315 cnt += obj->base.size >> PAGE_SHIFT;
4316 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4317 if (obj->pin_count == 0)
4318 cnt += obj->base.size >> PAGE_SHIFT;
4320 mutex_unlock(&dev->struct_mutex);