2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 bool map_and_fenceable,
46 static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
51 static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
57 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
60 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
61 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
63 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
66 i915_gem_release_mmap(obj);
68 /* As we do not have an associated fence register, we will force
69 * a tiling change if we ever need to acquire one.
71 obj->fence_dirty = false;
72 obj->fence_reg = I915_FENCE_REG_NONE;
75 /* some bookkeeping */
76 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
79 dev_priv->mm.object_count++;
80 dev_priv->mm.object_memory += size;
83 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
86 dev_priv->mm.object_count--;
87 dev_priv->mm.object_memory -= size;
91 i915_gem_wait_for_error(struct drm_device *dev)
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 struct completion *x = &dev_priv->error_completion;
98 if (!atomic_read(&dev_priv->mm.wedged))
102 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
103 * userspace. If it takes that long something really bad is going on and
104 * we should simply try to bail out and fail as gracefully as possible.
106 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
114 if (atomic_read(&dev_priv->mm.wedged)) {
115 /* GPU is hung, bump the completion count to account for
116 * the token we just consumed so that we never hit zero and
117 * end up waiting upon a subsequent completion event that
120 spin_lock_irqsave(&x->wait.lock, flags);
122 spin_unlock_irqrestore(&x->wait.lock, flags);
127 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 ret = i915_gem_wait_for_error(dev);
135 ret = mutex_lock_interruptible(&dev->struct_mutex);
139 WARN_ON(i915_verify_lists(dev));
144 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
146 return obj->gtt_space && !obj->active;
150 i915_gem_init_ioctl(struct drm_device *dev, void *data,
151 struct drm_file *file)
153 struct drm_i915_gem_init *args = data;
155 if (drm_core_check_feature(dev, DRIVER_MODESET))
158 if (args->gtt_start >= args->gtt_end ||
159 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
162 /* GEM with user mode setting was never supported on ilk and later. */
163 if (INTEL_INFO(dev)->gen >= 5)
166 mutex_lock(&dev->struct_mutex);
167 i915_gem_init_global_gtt(dev, args->gtt_start,
168 args->gtt_end, args->gtt_end);
169 mutex_unlock(&dev->struct_mutex);
175 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
176 struct drm_file *file)
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 struct drm_i915_gem_get_aperture *args = data;
180 struct drm_i915_gem_object *obj;
184 mutex_lock(&dev->struct_mutex);
185 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
187 pinned += obj->gtt_space->size;
188 mutex_unlock(&dev->struct_mutex);
190 args->aper_size = dev_priv->mm.gtt_total;
191 args->aper_available_size = args->aper_size - pinned;
197 i915_gem_create(struct drm_file *file,
198 struct drm_device *dev,
202 struct drm_i915_gem_object *obj;
206 size = roundup(size, PAGE_SIZE);
210 /* Allocate the new object */
211 obj = i915_gem_alloc_object(dev, size);
215 ret = drm_gem_handle_create(file, &obj->base, &handle);
217 drm_gem_object_release(&obj->base);
218 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
223 /* drop reference from allocate - handle holds it now */
224 drm_gem_object_unreference(&obj->base);
225 trace_i915_gem_object_create(obj);
232 i915_gem_dumb_create(struct drm_file *file,
233 struct drm_device *dev,
234 struct drm_mode_create_dumb *args)
236 /* have to work out size/pitch and return them */
237 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
238 args->size = args->pitch * args->height;
239 return i915_gem_create(file, dev,
240 args->size, &args->handle);
243 int i915_gem_dumb_destroy(struct drm_file *file,
244 struct drm_device *dev,
247 return drm_gem_handle_delete(file, handle);
251 * Creates a new mm object and returns a handle to it.
254 i915_gem_create_ioctl(struct drm_device *dev, void *data,
255 struct drm_file *file)
257 struct drm_i915_gem_create *args = data;
259 return i915_gem_create(file, dev,
260 args->size, &args->handle);
263 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
265 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
267 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
268 obj->tiling_mode != I915_TILING_NONE;
272 __copy_to_user_swizzled(char __user *cpu_vaddr,
273 const char *gpu_vaddr, int gpu_offset,
276 int ret, cpu_offset = 0;
279 int cacheline_end = ALIGN(gpu_offset + 1, 64);
280 int this_length = min(cacheline_end - gpu_offset, length);
281 int swizzled_gpu_offset = gpu_offset ^ 64;
283 ret = __copy_to_user(cpu_vaddr + cpu_offset,
284 gpu_vaddr + swizzled_gpu_offset,
289 cpu_offset += this_length;
290 gpu_offset += this_length;
291 length -= this_length;
298 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
299 const char __user *cpu_vaddr,
302 int ret, cpu_offset = 0;
305 int cacheline_end = ALIGN(gpu_offset + 1, 64);
306 int this_length = min(cacheline_end - gpu_offset, length);
307 int swizzled_gpu_offset = gpu_offset ^ 64;
309 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
310 cpu_vaddr + cpu_offset,
315 cpu_offset += this_length;
316 gpu_offset += this_length;
317 length -= this_length;
323 /* Per-page copy function for the shmem pread fastpath.
324 * Flushes invalid cachelines before reading the target if
325 * needs_clflush is set. */
327 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
328 char __user *user_data,
329 bool page_do_bit17_swizzling, bool needs_clflush)
334 if (unlikely(page_do_bit17_swizzling))
337 vaddr = kmap_atomic(page);
339 drm_clflush_virt_range(vaddr + shmem_page_offset,
341 ret = __copy_to_user_inatomic(user_data,
342 vaddr + shmem_page_offset,
344 kunmap_atomic(vaddr);
350 shmem_clflush_swizzled_range(char *addr, unsigned long length,
353 if (unlikely(swizzled)) {
354 unsigned long start = (unsigned long) addr;
355 unsigned long end = (unsigned long) addr + length;
357 /* For swizzling simply ensure that we always flush both
358 * channels. Lame, but simple and it works. Swizzled
359 * pwrite/pread is far from a hotpath - current userspace
360 * doesn't use it at all. */
361 start = round_down(start, 128);
362 end = round_up(end, 128);
364 drm_clflush_virt_range((void *)start, end - start);
366 drm_clflush_virt_range(addr, length);
371 /* Only difference to the fast-path function is that this can handle bit17
372 * and uses non-atomic copy and kmap functions. */
374 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
375 char __user *user_data,
376 bool page_do_bit17_swizzling, bool needs_clflush)
383 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
385 page_do_bit17_swizzling);
387 if (page_do_bit17_swizzling)
388 ret = __copy_to_user_swizzled(user_data,
389 vaddr, shmem_page_offset,
392 ret = __copy_to_user(user_data,
393 vaddr + shmem_page_offset,
401 i915_gem_shmem_pread(struct drm_device *dev,
402 struct drm_i915_gem_object *obj,
403 struct drm_i915_gem_pread *args,
404 struct drm_file *file)
406 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
407 char __user *user_data;
410 int shmem_page_offset, page_length, ret = 0;
411 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
412 int hit_slowpath = 0;
414 int needs_clflush = 0;
417 user_data = (char __user *) (uintptr_t) args->data_ptr;
420 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
422 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
423 /* If we're not in the cpu read domain, set ourself into the gtt
424 * read domain and manually flush cachelines (if required). This
425 * optimizes for the case when the gpu will dirty the data
426 * anyway again before the next pread happens. */
427 if (obj->cache_level == I915_CACHE_NONE)
429 if (obj->gtt_space) {
430 ret = i915_gem_object_set_to_gtt_domain(obj, false);
436 offset = args->offset;
441 /* Operation in this page
443 * shmem_page_offset = offset within page in shmem file
444 * page_length = bytes to copy for this page
446 shmem_page_offset = offset_in_page(offset);
447 page_length = remain;
448 if ((shmem_page_offset + page_length) > PAGE_SIZE)
449 page_length = PAGE_SIZE - shmem_page_offset;
452 page = obj->pages[offset >> PAGE_SHIFT];
455 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
463 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
464 (page_to_phys(page) & (1 << 17)) != 0;
466 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
467 user_data, page_do_bit17_swizzling,
473 page_cache_get(page);
474 mutex_unlock(&dev->struct_mutex);
477 ret = fault_in_multipages_writeable(user_data, remain);
478 /* Userspace is tricking us, but we've already clobbered
479 * its pages with the prefault and promised to write the
480 * data up to the first fault. Hence ignore any errors
481 * and just continue. */
486 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
487 user_data, page_do_bit17_swizzling,
490 mutex_lock(&dev->struct_mutex);
491 page_cache_release(page);
493 mark_page_accessed(page);
495 page_cache_release(page);
502 remain -= page_length;
503 user_data += page_length;
504 offset += page_length;
509 /* Fixup: Kill any reinstated backing storage pages */
510 if (obj->madv == __I915_MADV_PURGED)
511 i915_gem_object_truncate(obj);
518 * Reads data from the object referenced by handle.
520 * On error, the contents of *data are undefined.
523 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
524 struct drm_file *file)
526 struct drm_i915_gem_pread *args = data;
527 struct drm_i915_gem_object *obj;
533 if (!access_ok(VERIFY_WRITE,
534 (char __user *)(uintptr_t)args->data_ptr,
538 ret = i915_mutex_lock_interruptible(dev);
542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
543 if (&obj->base == NULL) {
548 /* Bounds check source. */
549 if (args->offset > obj->base.size ||
550 args->size > obj->base.size - args->offset) {
555 /* prime objects have no backing filp to GEM pread/pwrite
558 if (!obj->base.filp) {
563 trace_i915_gem_object_pread(obj, args->offset, args->size);
565 ret = i915_gem_shmem_pread(dev, obj, args, file);
568 drm_gem_object_unreference(&obj->base);
570 mutex_unlock(&dev->struct_mutex);
574 /* This is the fast write path which cannot handle
575 * page faults in the source data
579 fast_user_write(struct io_mapping *mapping,
580 loff_t page_base, int page_offset,
581 char __user *user_data,
584 void __iomem *vaddr_atomic;
586 unsigned long unwritten;
588 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
589 /* We can use the cpu mem copy function because this is X86. */
590 vaddr = (void __force*)vaddr_atomic + page_offset;
591 unwritten = __copy_from_user_inatomic_nocache(vaddr,
593 io_mapping_unmap_atomic(vaddr_atomic);
598 * This is the fast pwrite path, where we copy the data directly from the
599 * user into the GTT, uncached.
602 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
603 struct drm_i915_gem_object *obj,
604 struct drm_i915_gem_pwrite *args,
605 struct drm_file *file)
607 drm_i915_private_t *dev_priv = dev->dev_private;
609 loff_t offset, page_base;
610 char __user *user_data;
611 int page_offset, page_length, ret;
613 ret = i915_gem_object_pin(obj, 0, true, true);
617 ret = i915_gem_object_set_to_gtt_domain(obj, true);
621 ret = i915_gem_object_put_fence(obj);
625 user_data = (char __user *) (uintptr_t) args->data_ptr;
628 offset = obj->gtt_offset + args->offset;
631 /* Operation in this page
633 * page_base = page offset within aperture
634 * page_offset = offset within page
635 * page_length = bytes to copy for this page
637 page_base = offset & PAGE_MASK;
638 page_offset = offset_in_page(offset);
639 page_length = remain;
640 if ((page_offset + remain) > PAGE_SIZE)
641 page_length = PAGE_SIZE - page_offset;
643 /* If we get a fault while copying data, then (presumably) our
644 * source page isn't available. Return the error and we'll
645 * retry in the slow path.
647 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
648 page_offset, user_data, page_length)) {
653 remain -= page_length;
654 user_data += page_length;
655 offset += page_length;
659 i915_gem_object_unpin(obj);
664 /* Per-page copy function for the shmem pwrite fastpath.
665 * Flushes invalid cachelines before writing to the target if
666 * needs_clflush_before is set and flushes out any written cachelines after
667 * writing if needs_clflush is set. */
669 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
670 char __user *user_data,
671 bool page_do_bit17_swizzling,
672 bool needs_clflush_before,
673 bool needs_clflush_after)
678 if (unlikely(page_do_bit17_swizzling))
681 vaddr = kmap_atomic(page);
682 if (needs_clflush_before)
683 drm_clflush_virt_range(vaddr + shmem_page_offset,
685 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
688 if (needs_clflush_after)
689 drm_clflush_virt_range(vaddr + shmem_page_offset,
691 kunmap_atomic(vaddr);
696 /* Only difference to the fast-path function is that this can handle bit17
697 * and uses non-atomic copy and kmap functions. */
699 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
700 char __user *user_data,
701 bool page_do_bit17_swizzling,
702 bool needs_clflush_before,
703 bool needs_clflush_after)
709 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
710 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
712 page_do_bit17_swizzling);
713 if (page_do_bit17_swizzling)
714 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
718 ret = __copy_from_user(vaddr + shmem_page_offset,
721 if (needs_clflush_after)
722 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
724 page_do_bit17_swizzling);
731 i915_gem_shmem_pwrite(struct drm_device *dev,
732 struct drm_i915_gem_object *obj,
733 struct drm_i915_gem_pwrite *args,
734 struct drm_file *file)
736 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
739 char __user *user_data;
740 int shmem_page_offset, page_length, ret = 0;
741 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
742 int hit_slowpath = 0;
743 int needs_clflush_after = 0;
744 int needs_clflush_before = 0;
747 user_data = (char __user *) (uintptr_t) args->data_ptr;
750 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
752 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
753 /* If we're not in the cpu write domain, set ourself into the gtt
754 * write domain and manually flush cachelines (if required). This
755 * optimizes for the case when the gpu will use the data
756 * right away and we therefore have to clflush anyway. */
757 if (obj->cache_level == I915_CACHE_NONE)
758 needs_clflush_after = 1;
759 if (obj->gtt_space) {
760 ret = i915_gem_object_set_to_gtt_domain(obj, true);
765 /* Same trick applies for invalidate partially written cachelines before
767 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
768 && obj->cache_level == I915_CACHE_NONE)
769 needs_clflush_before = 1;
771 offset = args->offset;
776 int partial_cacheline_write;
778 /* Operation in this page
780 * shmem_page_offset = offset within page in shmem file
781 * page_length = bytes to copy for this page
783 shmem_page_offset = offset_in_page(offset);
785 page_length = remain;
786 if ((shmem_page_offset + page_length) > PAGE_SIZE)
787 page_length = PAGE_SIZE - shmem_page_offset;
789 /* If we don't overwrite a cacheline completely we need to be
790 * careful to have up-to-date data by first clflushing. Don't
791 * overcomplicate things and flush the entire patch. */
792 partial_cacheline_write = needs_clflush_before &&
793 ((shmem_page_offset | page_length)
794 & (boot_cpu_data.x86_clflush_size - 1));
797 page = obj->pages[offset >> PAGE_SHIFT];
800 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
808 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
809 (page_to_phys(page) & (1 << 17)) != 0;
811 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
812 user_data, page_do_bit17_swizzling,
813 partial_cacheline_write,
814 needs_clflush_after);
819 page_cache_get(page);
820 mutex_unlock(&dev->struct_mutex);
822 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
823 user_data, page_do_bit17_swizzling,
824 partial_cacheline_write,
825 needs_clflush_after);
827 mutex_lock(&dev->struct_mutex);
828 page_cache_release(page);
830 set_page_dirty(page);
831 mark_page_accessed(page);
833 page_cache_release(page);
840 remain -= page_length;
841 user_data += page_length;
842 offset += page_length;
847 /* Fixup: Kill any reinstated backing storage pages */
848 if (obj->madv == __I915_MADV_PURGED)
849 i915_gem_object_truncate(obj);
850 /* and flush dirty cachelines in case the object isn't in the cpu write
852 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
853 i915_gem_clflush_object(obj);
854 intel_gtt_chipset_flush();
858 if (needs_clflush_after)
859 intel_gtt_chipset_flush();
865 * Writes data to the object referenced by handle.
867 * On error, the contents of the buffer that were to be modified are undefined.
870 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
871 struct drm_file *file)
873 struct drm_i915_gem_pwrite *args = data;
874 struct drm_i915_gem_object *obj;
880 if (!access_ok(VERIFY_READ,
881 (char __user *)(uintptr_t)args->data_ptr,
885 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
890 ret = i915_mutex_lock_interruptible(dev);
894 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
895 if (&obj->base == NULL) {
900 /* Bounds check destination. */
901 if (args->offset > obj->base.size ||
902 args->size > obj->base.size - args->offset) {
907 /* prime objects have no backing filp to GEM pread/pwrite
910 if (!obj->base.filp) {
915 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
918 /* We can only do the GTT pwrite on untiled buffers, as otherwise
919 * it would end up going through the fenced access, and we'll get
920 * different detiling behavior between reading and writing.
921 * pread/pwrite currently are reading and writing from the CPU
922 * perspective, requiring manual detiling by the client.
925 ret = i915_gem_phys_pwrite(dev, obj, args, file);
929 if (obj->cache_level == I915_CACHE_NONE &&
930 obj->tiling_mode == I915_TILING_NONE &&
931 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
932 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
933 /* Note that the gtt paths might fail with non-page-backed user
934 * pointers (e.g. gtt mappings when moving data between
935 * textures). Fallback to the shmem path in that case. */
938 if (ret == -EFAULT || ret == -ENOSPC)
939 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
942 drm_gem_object_unreference(&obj->base);
944 mutex_unlock(&dev->struct_mutex);
949 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
952 if (atomic_read(&dev_priv->mm.wedged)) {
953 struct completion *x = &dev_priv->error_completion;
954 bool recovery_complete;
957 /* Give the error handler a chance to run. */
958 spin_lock_irqsave(&x->wait.lock, flags);
959 recovery_complete = x->done > 0;
960 spin_unlock_irqrestore(&x->wait.lock, flags);
962 /* Non-interruptible callers can't handle -EAGAIN, hence return
963 * -EIO unconditionally for these. */
967 /* Recovery complete, but still wedged means reset failure. */
968 if (recovery_complete)
978 * Compare seqno against outstanding lazy request. Emit a request if they are
982 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
986 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
989 if (seqno == ring->outstanding_lazy_request)
990 ret = i915_add_request(ring, NULL, NULL);
996 * __wait_seqno - wait until execution of seqno has finished
997 * @ring: the ring expected to report seqno
999 * @interruptible: do an interruptible wait (normally yes)
1000 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1002 * Returns 0 if the seqno was found within the alloted time. Else returns the
1003 * errno with remaining time filled in timeout argument.
1005 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1006 bool interruptible, struct timespec *timeout)
1008 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1009 struct timespec before, now, wait_time={1,0};
1010 unsigned long timeout_jiffies;
1012 bool wait_forever = true;
1015 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1018 trace_i915_gem_request_wait_begin(ring, seqno);
1020 if (timeout != NULL) {
1021 wait_time = *timeout;
1022 wait_forever = false;
1025 timeout_jiffies = timespec_to_jiffies(&wait_time);
1027 if (WARN_ON(!ring->irq_get(ring)))
1030 /* Record current time in case interrupted by signal, or wedged * */
1031 getrawmonotonic(&before);
1034 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1035 atomic_read(&dev_priv->mm.wedged))
1038 end = wait_event_interruptible_timeout(ring->irq_queue,
1042 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1045 ret = i915_gem_check_wedge(dev_priv, interruptible);
1048 } while (end == 0 && wait_forever);
1050 getrawmonotonic(&now);
1052 ring->irq_put(ring);
1053 trace_i915_gem_request_wait_end(ring, seqno);
1057 struct timespec sleep_time = timespec_sub(now, before);
1058 *timeout = timespec_sub(*timeout, sleep_time);
1063 case -EAGAIN: /* Wedged */
1064 case -ERESTARTSYS: /* Signal */
1066 case 0: /* Timeout */
1068 set_normalized_timespec(timeout, 0, 0);
1070 default: /* Completed */
1071 WARN_ON(end < 0); /* We're not aware of other errors */
1077 * Waits for a sequence number to be signaled, and cleans up the
1078 * request and object lists appropriately for that event.
1081 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1083 struct drm_device *dev = ring->dev;
1084 struct drm_i915_private *dev_priv = dev->dev_private;
1085 bool interruptible = dev_priv->mm.interruptible;
1088 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1091 ret = i915_gem_check_wedge(dev_priv, interruptible);
1095 ret = i915_gem_check_olr(ring, seqno);
1099 return __wait_seqno(ring, seqno, interruptible, NULL);
1103 * Ensures that all rendering to the object has completed and the object is
1104 * safe to unbind from the GTT or access from the CPU.
1106 static __must_check int
1107 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1110 struct intel_ring_buffer *ring = obj->ring;
1114 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1118 ret = i915_wait_seqno(ring, seqno);
1122 i915_gem_retire_requests_ring(ring);
1124 /* Manually manage the write flush as we may have not yet
1125 * retired the buffer.
1127 if (obj->last_write_seqno &&
1128 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1129 obj->last_write_seqno = 0;
1130 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1136 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1137 * as the object state may change during this call.
1139 static __must_check int
1140 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1143 struct drm_device *dev = obj->base.dev;
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 struct intel_ring_buffer *ring = obj->ring;
1149 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1150 BUG_ON(!dev_priv->mm.interruptible);
1152 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1156 ret = i915_gem_check_wedge(dev_priv, true);
1160 ret = i915_gem_check_olr(ring, seqno);
1164 mutex_unlock(&dev->struct_mutex);
1165 ret = __wait_seqno(ring, seqno, true, NULL);
1166 mutex_lock(&dev->struct_mutex);
1168 i915_gem_retire_requests_ring(ring);
1170 /* Manually manage the write flush as we may have not yet
1171 * retired the buffer.
1173 if (obj->last_write_seqno &&
1174 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1175 obj->last_write_seqno = 0;
1176 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1183 * Called when user space prepares to use an object with the CPU, either
1184 * through the mmap ioctl's mapping or a GTT mapping.
1187 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *file)
1190 struct drm_i915_gem_set_domain *args = data;
1191 struct drm_i915_gem_object *obj;
1192 uint32_t read_domains = args->read_domains;
1193 uint32_t write_domain = args->write_domain;
1196 /* Only handle setting domains to types used by the CPU. */
1197 if (write_domain & I915_GEM_GPU_DOMAINS)
1200 if (read_domains & I915_GEM_GPU_DOMAINS)
1203 /* Having something in the write domain implies it's in the read
1204 * domain, and only that read domain. Enforce that in the request.
1206 if (write_domain != 0 && read_domains != write_domain)
1209 ret = i915_mutex_lock_interruptible(dev);
1213 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1214 if (&obj->base == NULL) {
1219 /* Try to flush the object off the GPU without holding the lock.
1220 * We will repeat the flush holding the lock in the normal manner
1221 * to catch cases where we are gazumped.
1223 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1227 if (read_domains & I915_GEM_DOMAIN_GTT) {
1228 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1230 /* Silently promote "you're not bound, there was nothing to do"
1231 * to success, since the client was just asking us to
1232 * make sure everything was done.
1237 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1241 drm_gem_object_unreference(&obj->base);
1243 mutex_unlock(&dev->struct_mutex);
1248 * Called when user space has done writes to this buffer
1251 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1252 struct drm_file *file)
1254 struct drm_i915_gem_sw_finish *args = data;
1255 struct drm_i915_gem_object *obj;
1258 ret = i915_mutex_lock_interruptible(dev);
1262 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1263 if (&obj->base == NULL) {
1268 /* Pinned buffers may be scanout, so flush the cache */
1270 i915_gem_object_flush_cpu_write_domain(obj);
1272 drm_gem_object_unreference(&obj->base);
1274 mutex_unlock(&dev->struct_mutex);
1279 * Maps the contents of an object, returning the address it is mapped
1282 * While the mapping holds a reference on the contents of the object, it doesn't
1283 * imply a ref on the object itself.
1286 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1287 struct drm_file *file)
1289 struct drm_i915_gem_mmap *args = data;
1290 struct drm_gem_object *obj;
1293 obj = drm_gem_object_lookup(dev, file, args->handle);
1297 /* prime objects have no backing filp to GEM mmap
1301 drm_gem_object_unreference_unlocked(obj);
1305 addr = vm_mmap(obj->filp, 0, args->size,
1306 PROT_READ | PROT_WRITE, MAP_SHARED,
1308 drm_gem_object_unreference_unlocked(obj);
1309 if (IS_ERR((void *)addr))
1312 args->addr_ptr = (uint64_t) addr;
1318 * i915_gem_fault - fault a page into the GTT
1319 * vma: VMA in question
1322 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1323 * from userspace. The fault handler takes care of binding the object to
1324 * the GTT (if needed), allocating and programming a fence register (again,
1325 * only if needed based on whether the old reg is still valid or the object
1326 * is tiled) and inserting a new PTE into the faulting process.
1328 * Note that the faulting process may involve evicting existing objects
1329 * from the GTT and/or fence registers to make room. So performance may
1330 * suffer if the GTT working set is large or there are few fence registers
1333 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1335 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1336 struct drm_device *dev = obj->base.dev;
1337 drm_i915_private_t *dev_priv = dev->dev_private;
1338 pgoff_t page_offset;
1341 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1343 /* We don't use vmf->pgoff since that has the fake offset */
1344 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1347 ret = i915_mutex_lock_interruptible(dev);
1351 trace_i915_gem_object_fault(obj, page_offset, true, write);
1353 /* Now bind it into the GTT if needed */
1354 if (!obj->map_and_fenceable) {
1355 ret = i915_gem_object_unbind(obj);
1359 if (!obj->gtt_space) {
1360 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1364 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1369 if (!obj->has_global_gtt_mapping)
1370 i915_gem_gtt_bind_object(obj, obj->cache_level);
1372 ret = i915_gem_object_get_fence(obj);
1376 if (i915_gem_object_is_inactive(obj))
1377 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1379 obj->fault_mappable = true;
1381 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1384 /* Finally, remap it using the new GTT offset */
1385 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1387 mutex_unlock(&dev->struct_mutex);
1391 /* If this -EIO is due to a gpu hang, give the reset code a
1392 * chance to clean up the mess. Otherwise return the proper
1394 if (!atomic_read(&dev_priv->mm.wedged))
1395 return VM_FAULT_SIGBUS;
1397 /* Give the error handler a chance to run and move the
1398 * objects off the GPU active list. Next time we service the
1399 * fault, we should be able to transition the page into the
1400 * GTT without touching the GPU (and so avoid further
1401 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1402 * with coherency, just lost writes.
1408 return VM_FAULT_NOPAGE;
1410 return VM_FAULT_OOM;
1412 return VM_FAULT_SIGBUS;
1417 * i915_gem_release_mmap - remove physical page mappings
1418 * @obj: obj in question
1420 * Preserve the reservation of the mmapping with the DRM core code, but
1421 * relinquish ownership of the pages back to the system.
1423 * It is vital that we remove the page mapping if we have mapped a tiled
1424 * object through the GTT and then lose the fence register due to
1425 * resource pressure. Similarly if the object has been moved out of the
1426 * aperture, than pages mapped into userspace must be revoked. Removing the
1427 * mapping will then trigger a page fault on the next user access, allowing
1428 * fixup by i915_gem_fault().
1431 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1433 if (!obj->fault_mappable)
1436 if (obj->base.dev->dev_mapping)
1437 unmap_mapping_range(obj->base.dev->dev_mapping,
1438 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1441 obj->fault_mappable = false;
1445 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1449 if (INTEL_INFO(dev)->gen >= 4 ||
1450 tiling_mode == I915_TILING_NONE)
1453 /* Previous chips need a power-of-two fence region when tiling */
1454 if (INTEL_INFO(dev)->gen == 3)
1455 gtt_size = 1024*1024;
1457 gtt_size = 512*1024;
1459 while (gtt_size < size)
1466 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1467 * @obj: object to check
1469 * Return the required GTT alignment for an object, taking into account
1470 * potential fence register mapping.
1473 i915_gem_get_gtt_alignment(struct drm_device *dev,
1478 * Minimum alignment is 4k (GTT page size), but might be greater
1479 * if a fence register is needed for the object.
1481 if (INTEL_INFO(dev)->gen >= 4 ||
1482 tiling_mode == I915_TILING_NONE)
1486 * Previous chips need to be aligned to the size of the smallest
1487 * fence register that can contain the object.
1489 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1493 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1496 * @size: size of the object
1497 * @tiling_mode: tiling mode of the object
1499 * Return the required GTT alignment for an object, only taking into account
1500 * unfenced tiled surface requirements.
1503 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1508 * Minimum alignment is 4k (GTT page size) for sane hw.
1510 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1511 tiling_mode == I915_TILING_NONE)
1514 /* Previous hardware however needs to be aligned to a power-of-two
1515 * tile height. The simplest method for determining this is to reuse
1516 * the power-of-tile object size.
1518 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1521 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1523 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1526 if (obj->base.map_list.map)
1529 ret = drm_gem_create_mmap_offset(&obj->base);
1533 /* Badly fragmented mmap space? The only way we can recover
1534 * space is by destroying unwanted objects. We can't randomly release
1535 * mmap_offsets as userspace expects them to be persistent for the
1536 * lifetime of the objects. The closest we can is to release the
1537 * offsets on purgeable objects by truncating it and marking it purged,
1538 * which prevents userspace from ever using that object again.
1540 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1541 ret = drm_gem_create_mmap_offset(&obj->base);
1545 i915_gem_shrink_all(dev_priv);
1546 return drm_gem_create_mmap_offset(&obj->base);
1549 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1551 if (!obj->base.map_list.map)
1554 drm_gem_free_mmap_offset(&obj->base);
1558 i915_gem_mmap_gtt(struct drm_file *file,
1559 struct drm_device *dev,
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj;
1567 ret = i915_mutex_lock_interruptible(dev);
1571 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1572 if (&obj->base == NULL) {
1577 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1582 if (obj->madv != I915_MADV_WILLNEED) {
1583 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1588 ret = i915_gem_object_create_mmap_offset(obj);
1592 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1595 drm_gem_object_unreference(&obj->base);
1597 mutex_unlock(&dev->struct_mutex);
1602 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1604 * @data: GTT mapping ioctl data
1605 * @file: GEM object info
1607 * Simply returns the fake offset to userspace so it can mmap it.
1608 * The mmap call will end up in drm_gem_mmap(), which will set things
1609 * up so we can get faults in the handler above.
1611 * The fault handler will take care of binding the object into the GTT
1612 * (since it may have been evicted to make room for something), allocating
1613 * a fence register, and mapping the appropriate aperture address into
1617 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1618 struct drm_file *file)
1620 struct drm_i915_gem_mmap_gtt *args = data;
1622 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1625 /* Immediately discard the backing storage */
1627 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1629 struct inode *inode;
1631 i915_gem_object_free_mmap_offset(obj);
1633 if (obj->base.filp == NULL)
1636 /* Our goal here is to return as much of the memory as
1637 * is possible back to the system as we are called from OOM.
1638 * To do this we must instruct the shmfs to drop all of its
1639 * backing pages, *now*.
1641 inode = obj->base.filp->f_path.dentry->d_inode;
1642 shmem_truncate_range(inode, 0, (loff_t)-1);
1644 obj->madv = __I915_MADV_PURGED;
1648 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1650 return obj->madv == I915_MADV_DONTNEED;
1654 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1656 int page_count = obj->base.size / PAGE_SIZE;
1659 BUG_ON(obj->madv == __I915_MADV_PURGED);
1661 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1663 /* In the event of a disaster, abandon all caches and
1664 * hope for the best.
1666 WARN_ON(ret != -EIO);
1667 i915_gem_clflush_object(obj);
1668 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1671 if (i915_gem_object_needs_bit17_swizzle(obj))
1672 i915_gem_object_save_bit_17_swizzle(obj);
1674 if (obj->madv == I915_MADV_DONTNEED)
1677 for (i = 0; i < page_count; i++) {
1679 set_page_dirty(obj->pages[i]);
1681 if (obj->madv == I915_MADV_WILLNEED)
1682 mark_page_accessed(obj->pages[i]);
1684 page_cache_release(obj->pages[i]);
1688 drm_free_large(obj->pages);
1693 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1695 const struct drm_i915_gem_object_ops *ops = obj->ops;
1697 if (obj->sg_table || obj->pages == NULL)
1700 BUG_ON(obj->gtt_space);
1702 if (obj->pages_pin_count)
1705 ops->put_pages(obj);
1707 list_del(&obj->gtt_list);
1708 if (i915_gem_object_is_purgeable(obj))
1709 i915_gem_object_truncate(obj);
1715 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1717 struct drm_i915_gem_object *obj, *next;
1720 list_for_each_entry_safe(obj, next,
1721 &dev_priv->mm.unbound_list,
1723 if (i915_gem_object_is_purgeable(obj) &&
1724 i915_gem_object_put_pages(obj) == 0) {
1725 count += obj->base.size >> PAGE_SHIFT;
1726 if (count >= target)
1731 list_for_each_entry_safe(obj, next,
1732 &dev_priv->mm.inactive_list,
1734 if (i915_gem_object_is_purgeable(obj) &&
1735 i915_gem_object_unbind(obj) == 0 &&
1736 i915_gem_object_put_pages(obj) == 0) {
1737 count += obj->base.size >> PAGE_SHIFT;
1738 if (count >= target)
1747 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1749 struct drm_i915_gem_object *obj, *next;
1751 i915_gem_evict_everything(dev_priv->dev);
1753 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1754 i915_gem_object_put_pages(obj);
1758 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1760 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1762 struct address_space *mapping;
1766 /* Assert that the object is not currently in any GPU domain. As it
1767 * wasn't in the GTT, there shouldn't be any way it could have been in
1770 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1771 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1773 /* Get the list of pages out of our struct file. They'll be pinned
1774 * at this point until we release them.
1776 page_count = obj->base.size / PAGE_SIZE;
1777 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1778 if (obj->pages == NULL)
1781 /* Fail silently without starting the shrinker */
1782 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1783 gfp = mapping_gfp_mask(mapping);
1784 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1785 gfp &= ~(__GFP_IO | __GFP_WAIT);
1786 for (i = 0; i < page_count; i++) {
1787 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1789 i915_gem_purge(dev_priv, page_count);
1790 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1793 /* We've tried hard to allocate the memory by reaping
1794 * our own buffer, now let the real VM do its job and
1795 * go down in flames if truly OOM.
1797 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1798 gfp |= __GFP_IO | __GFP_WAIT;
1800 i915_gem_shrink_all(dev_priv);
1801 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1805 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1806 gfp &= ~(__GFP_IO | __GFP_WAIT);
1809 obj->pages[i] = page;
1812 if (i915_gem_object_needs_bit17_swizzle(obj))
1813 i915_gem_object_do_bit_17_swizzle(obj);
1819 page_cache_release(obj->pages[i]);
1821 drm_free_large(obj->pages);
1823 return PTR_ERR(page);
1826 /* Ensure that the associated pages are gathered from the backing storage
1827 * and pinned into our object. i915_gem_object_get_pages() may be called
1828 * multiple times before they are released by a single call to
1829 * i915_gem_object_put_pages() - once the pages are no longer referenced
1830 * either as a result of memory pressure (reaping pages under the shrinker)
1831 * or as the object is itself released.
1834 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1836 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1837 const struct drm_i915_gem_object_ops *ops = obj->ops;
1840 if (obj->sg_table || obj->pages)
1843 BUG_ON(obj->pages_pin_count);
1845 ret = ops->get_pages(obj);
1849 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1854 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1855 struct intel_ring_buffer *ring,
1858 struct drm_device *dev = obj->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1861 BUG_ON(ring == NULL);
1864 /* Add a reference if we're newly entering the active list. */
1866 drm_gem_object_reference(&obj->base);
1870 /* Move from whatever list we were on to the tail of execution. */
1871 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1872 list_move_tail(&obj->ring_list, &ring->active_list);
1874 obj->last_read_seqno = seqno;
1876 if (obj->fenced_gpu_access) {
1877 obj->last_fenced_seqno = seqno;
1879 /* Bump MRU to take account of the delayed flush */
1880 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1881 struct drm_i915_fence_reg *reg;
1883 reg = &dev_priv->fence_regs[obj->fence_reg];
1884 list_move_tail(®->lru_list,
1885 &dev_priv->mm.fence_list);
1891 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1893 struct drm_device *dev = obj->base.dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1896 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1897 BUG_ON(!obj->active);
1899 if (obj->pin_count) /* are we a framebuffer? */
1900 intel_mark_fb_idle(obj);
1902 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1904 list_del_init(&obj->ring_list);
1907 obj->last_read_seqno = 0;
1908 obj->last_write_seqno = 0;
1909 obj->base.write_domain = 0;
1911 obj->last_fenced_seqno = 0;
1912 obj->fenced_gpu_access = false;
1915 drm_gem_object_unreference(&obj->base);
1917 WARN_ON(i915_verify_lists(dev));
1921 i915_gem_get_seqno(struct drm_device *dev)
1923 drm_i915_private_t *dev_priv = dev->dev_private;
1924 u32 seqno = dev_priv->next_seqno;
1926 /* reserve 0 for non-seqno */
1927 if (++dev_priv->next_seqno == 0)
1928 dev_priv->next_seqno = 1;
1934 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1936 if (ring->outstanding_lazy_request == 0)
1937 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1939 return ring->outstanding_lazy_request;
1943 i915_add_request(struct intel_ring_buffer *ring,
1944 struct drm_file *file,
1945 struct drm_i915_gem_request *request)
1947 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1949 u32 request_ring_position;
1954 * Emit any outstanding flushes - execbuf can fail to emit the flush
1955 * after having emitted the batchbuffer command. Hence we need to fix
1956 * things up similar to emitting the lazy request. The difference here
1957 * is that the flush _must_ happen before the next request, no matter
1960 ret = intel_ring_flush_all_caches(ring);
1964 if (request == NULL) {
1965 request = kmalloc(sizeof(*request), GFP_KERNEL);
1966 if (request == NULL)
1970 seqno = i915_gem_next_request_seqno(ring);
1972 /* Record the position of the start of the request so that
1973 * should we detect the updated seqno part-way through the
1974 * GPU processing the request, we never over-estimate the
1975 * position of the head.
1977 request_ring_position = intel_ring_get_tail(ring);
1979 ret = ring->add_request(ring, &seqno);
1985 trace_i915_gem_request_add(ring, seqno);
1987 request->seqno = seqno;
1988 request->ring = ring;
1989 request->tail = request_ring_position;
1990 request->emitted_jiffies = jiffies;
1991 was_empty = list_empty(&ring->request_list);
1992 list_add_tail(&request->list, &ring->request_list);
1993 request->file_priv = NULL;
1996 struct drm_i915_file_private *file_priv = file->driver_priv;
1998 spin_lock(&file_priv->mm.lock);
1999 request->file_priv = file_priv;
2000 list_add_tail(&request->client_list,
2001 &file_priv->mm.request_list);
2002 spin_unlock(&file_priv->mm.lock);
2005 ring->outstanding_lazy_request = 0;
2007 if (!dev_priv->mm.suspended) {
2008 if (i915_enable_hangcheck) {
2009 mod_timer(&dev_priv->hangcheck_timer,
2011 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
2014 queue_delayed_work(dev_priv->wq,
2015 &dev_priv->mm.retire_work, HZ);
2016 intel_mark_busy(dev_priv->dev);
2024 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2026 struct drm_i915_file_private *file_priv = request->file_priv;
2031 spin_lock(&file_priv->mm.lock);
2032 if (request->file_priv) {
2033 list_del(&request->client_list);
2034 request->file_priv = NULL;
2036 spin_unlock(&file_priv->mm.lock);
2039 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2040 struct intel_ring_buffer *ring)
2042 while (!list_empty(&ring->request_list)) {
2043 struct drm_i915_gem_request *request;
2045 request = list_first_entry(&ring->request_list,
2046 struct drm_i915_gem_request,
2049 list_del(&request->list);
2050 i915_gem_request_remove_from_client(request);
2054 while (!list_empty(&ring->active_list)) {
2055 struct drm_i915_gem_object *obj;
2057 obj = list_first_entry(&ring->active_list,
2058 struct drm_i915_gem_object,
2061 i915_gem_object_move_to_inactive(obj);
2065 static void i915_gem_reset_fences(struct drm_device *dev)
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2070 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2071 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2073 i915_gem_write_fence(dev, i, NULL);
2076 i915_gem_object_fence_lost(reg->obj);
2080 INIT_LIST_HEAD(®->lru_list);
2083 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2086 void i915_gem_reset(struct drm_device *dev)
2088 struct drm_i915_private *dev_priv = dev->dev_private;
2089 struct drm_i915_gem_object *obj;
2090 struct intel_ring_buffer *ring;
2093 for_each_ring(ring, dev_priv, i)
2094 i915_gem_reset_ring_lists(dev_priv, ring);
2096 /* Move everything out of the GPU domains to ensure we do any
2097 * necessary invalidation upon reuse.
2099 list_for_each_entry(obj,
2100 &dev_priv->mm.inactive_list,
2103 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2106 /* The fence registers are invalidated so clear them out */
2107 i915_gem_reset_fences(dev);
2111 * This function clears the request list as sequence numbers are passed.
2114 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2119 if (list_empty(&ring->request_list))
2122 WARN_ON(i915_verify_lists(ring->dev));
2124 seqno = ring->get_seqno(ring, true);
2126 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
2127 if (seqno >= ring->sync_seqno[i])
2128 ring->sync_seqno[i] = 0;
2130 while (!list_empty(&ring->request_list)) {
2131 struct drm_i915_gem_request *request;
2133 request = list_first_entry(&ring->request_list,
2134 struct drm_i915_gem_request,
2137 if (!i915_seqno_passed(seqno, request->seqno))
2140 trace_i915_gem_request_retire(ring, request->seqno);
2141 /* We know the GPU must have read the request to have
2142 * sent us the seqno + interrupt, so use the position
2143 * of tail of the request to update the last known position
2146 ring->last_retired_head = request->tail;
2148 list_del(&request->list);
2149 i915_gem_request_remove_from_client(request);
2153 /* Move any buffers on the active list that are no longer referenced
2154 * by the ringbuffer to the flushing/inactive lists as appropriate.
2156 while (!list_empty(&ring->active_list)) {
2157 struct drm_i915_gem_object *obj;
2159 obj = list_first_entry(&ring->active_list,
2160 struct drm_i915_gem_object,
2163 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2166 i915_gem_object_move_to_inactive(obj);
2169 if (unlikely(ring->trace_irq_seqno &&
2170 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2171 ring->irq_put(ring);
2172 ring->trace_irq_seqno = 0;
2175 WARN_ON(i915_verify_lists(ring->dev));
2179 i915_gem_retire_requests(struct drm_device *dev)
2181 drm_i915_private_t *dev_priv = dev->dev_private;
2182 struct intel_ring_buffer *ring;
2185 for_each_ring(ring, dev_priv, i)
2186 i915_gem_retire_requests_ring(ring);
2190 i915_gem_retire_work_handler(struct work_struct *work)
2192 drm_i915_private_t *dev_priv;
2193 struct drm_device *dev;
2194 struct intel_ring_buffer *ring;
2198 dev_priv = container_of(work, drm_i915_private_t,
2199 mm.retire_work.work);
2200 dev = dev_priv->dev;
2202 /* Come back later if the device is busy... */
2203 if (!mutex_trylock(&dev->struct_mutex)) {
2204 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2208 i915_gem_retire_requests(dev);
2210 /* Send a periodic flush down the ring so we don't hold onto GEM
2211 * objects indefinitely.
2214 for_each_ring(ring, dev_priv, i) {
2215 if (ring->gpu_caches_dirty)
2216 i915_add_request(ring, NULL, NULL);
2218 idle &= list_empty(&ring->request_list);
2221 if (!dev_priv->mm.suspended && !idle)
2222 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2224 intel_mark_idle(dev);
2226 mutex_unlock(&dev->struct_mutex);
2230 * Ensures that an object will eventually get non-busy by flushing any required
2231 * write domains, emitting any outstanding lazy request and retiring and
2232 * completed requests.
2235 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2240 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2244 i915_gem_retire_requests_ring(obj->ring);
2251 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2252 * @DRM_IOCTL_ARGS: standard ioctl arguments
2254 * Returns 0 if successful, else an error is returned with the remaining time in
2255 * the timeout parameter.
2256 * -ETIME: object is still busy after timeout
2257 * -ERESTARTSYS: signal interrupted the wait
2258 * -ENONENT: object doesn't exist
2259 * Also possible, but rare:
2260 * -EAGAIN: GPU wedged
2262 * -ENODEV: Internal IRQ fail
2263 * -E?: The add request failed
2265 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2266 * non-zero timeout parameter the wait ioctl will wait for the given number of
2267 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2268 * without holding struct_mutex the object may become re-busied before this
2269 * function completes. A similar but shorter * race condition exists in the busy
2273 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2275 struct drm_i915_gem_wait *args = data;
2276 struct drm_i915_gem_object *obj;
2277 struct intel_ring_buffer *ring = NULL;
2278 struct timespec timeout_stack, *timeout = NULL;
2282 if (args->timeout_ns >= 0) {
2283 timeout_stack = ns_to_timespec(args->timeout_ns);
2284 timeout = &timeout_stack;
2287 ret = i915_mutex_lock_interruptible(dev);
2291 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2292 if (&obj->base == NULL) {
2293 mutex_unlock(&dev->struct_mutex);
2297 /* Need to make sure the object gets inactive eventually. */
2298 ret = i915_gem_object_flush_active(obj);
2303 seqno = obj->last_read_seqno;
2310 /* Do this after OLR check to make sure we make forward progress polling
2311 * on this IOCTL with a 0 timeout (like busy ioctl)
2313 if (!args->timeout_ns) {
2318 drm_gem_object_unreference(&obj->base);
2319 mutex_unlock(&dev->struct_mutex);
2321 ret = __wait_seqno(ring, seqno, true, timeout);
2323 WARN_ON(!timespec_valid(timeout));
2324 args->timeout_ns = timespec_to_ns(timeout);
2329 drm_gem_object_unreference(&obj->base);
2330 mutex_unlock(&dev->struct_mutex);
2335 * i915_gem_object_sync - sync an object to a ring.
2337 * @obj: object which may be in use on another ring.
2338 * @to: ring we wish to use the object on. May be NULL.
2340 * This code is meant to abstract object synchronization with the GPU.
2341 * Calling with NULL implies synchronizing the object with the CPU
2342 * rather than a particular GPU ring.
2344 * Returns 0 if successful, else propagates up the lower layer error.
2347 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2348 struct intel_ring_buffer *to)
2350 struct intel_ring_buffer *from = obj->ring;
2354 if (from == NULL || to == from)
2357 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2358 return i915_gem_object_wait_rendering(obj, false);
2360 idx = intel_ring_sync_index(from, to);
2362 seqno = obj->last_read_seqno;
2363 if (seqno <= from->sync_seqno[idx])
2366 ret = i915_gem_check_olr(obj->ring, seqno);
2370 ret = to->sync_to(to, from, seqno);
2372 from->sync_seqno[idx] = seqno;
2377 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2379 u32 old_write_domain, old_read_domains;
2381 /* Act a barrier for all accesses through the GTT */
2384 /* Force a pagefault for domain tracking on next user access */
2385 i915_gem_release_mmap(obj);
2387 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2390 old_read_domains = obj->base.read_domains;
2391 old_write_domain = obj->base.write_domain;
2393 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2394 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2396 trace_i915_gem_object_change_domain(obj,
2402 * Unbinds an object from the GTT aperture.
2405 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2407 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2410 if (obj->gtt_space == NULL)
2416 BUG_ON(obj->pages == NULL);
2418 ret = i915_gem_object_finish_gpu(obj);
2421 /* Continue on if we fail due to EIO, the GPU is hung so we
2422 * should be safe and we need to cleanup or else we might
2423 * cause memory corruption through use-after-free.
2426 i915_gem_object_finish_gtt(obj);
2428 /* release the fence reg _after_ flushing */
2429 ret = i915_gem_object_put_fence(obj);
2433 trace_i915_gem_object_unbind(obj);
2435 if (obj->has_global_gtt_mapping)
2436 i915_gem_gtt_unbind_object(obj);
2437 if (obj->has_aliasing_ppgtt_mapping) {
2438 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2439 obj->has_aliasing_ppgtt_mapping = 0;
2441 i915_gem_gtt_finish_object(obj);
2443 list_del(&obj->mm_list);
2444 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2445 /* Avoid an unnecessary call to unbind on rebind. */
2446 obj->map_and_fenceable = true;
2448 drm_mm_put_block(obj->gtt_space);
2449 obj->gtt_space = NULL;
2450 obj->gtt_offset = 0;
2455 static int i915_ring_idle(struct intel_ring_buffer *ring)
2457 if (list_empty(&ring->active_list))
2460 return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2463 int i915_gpu_idle(struct drm_device *dev)
2465 drm_i915_private_t *dev_priv = dev->dev_private;
2466 struct intel_ring_buffer *ring;
2469 /* Flush everything onto the inactive list. */
2470 for_each_ring(ring, dev_priv, i) {
2471 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2475 ret = i915_ring_idle(ring);
2483 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2484 struct drm_i915_gem_object *obj)
2486 drm_i915_private_t *dev_priv = dev->dev_private;
2490 u32 size = obj->gtt_space->size;
2492 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2494 val |= obj->gtt_offset & 0xfffff000;
2495 val |= (uint64_t)((obj->stride / 128) - 1) <<
2496 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2498 if (obj->tiling_mode == I915_TILING_Y)
2499 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2500 val |= I965_FENCE_REG_VALID;
2504 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2505 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2508 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2509 struct drm_i915_gem_object *obj)
2511 drm_i915_private_t *dev_priv = dev->dev_private;
2515 u32 size = obj->gtt_space->size;
2517 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2519 val |= obj->gtt_offset & 0xfffff000;
2520 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2521 if (obj->tiling_mode == I915_TILING_Y)
2522 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2523 val |= I965_FENCE_REG_VALID;
2527 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2528 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2531 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2532 struct drm_i915_gem_object *obj)
2534 drm_i915_private_t *dev_priv = dev->dev_private;
2538 u32 size = obj->gtt_space->size;
2542 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2543 (size & -size) != size ||
2544 (obj->gtt_offset & (size - 1)),
2545 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2546 obj->gtt_offset, obj->map_and_fenceable, size);
2548 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2553 /* Note: pitch better be a power of two tile widths */
2554 pitch_val = obj->stride / tile_width;
2555 pitch_val = ffs(pitch_val) - 1;
2557 val = obj->gtt_offset;
2558 if (obj->tiling_mode == I915_TILING_Y)
2559 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2560 val |= I915_FENCE_SIZE_BITS(size);
2561 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2562 val |= I830_FENCE_REG_VALID;
2567 reg = FENCE_REG_830_0 + reg * 4;
2569 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2571 I915_WRITE(reg, val);
2575 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2576 struct drm_i915_gem_object *obj)
2578 drm_i915_private_t *dev_priv = dev->dev_private;
2582 u32 size = obj->gtt_space->size;
2585 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2586 (size & -size) != size ||
2587 (obj->gtt_offset & (size - 1)),
2588 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2589 obj->gtt_offset, size);
2591 pitch_val = obj->stride / 128;
2592 pitch_val = ffs(pitch_val) - 1;
2594 val = obj->gtt_offset;
2595 if (obj->tiling_mode == I915_TILING_Y)
2596 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2597 val |= I830_FENCE_SIZE_BITS(size);
2598 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2599 val |= I830_FENCE_REG_VALID;
2603 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2604 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2607 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2608 struct drm_i915_gem_object *obj)
2610 switch (INTEL_INFO(dev)->gen) {
2612 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2614 case 4: i965_write_fence_reg(dev, reg, obj); break;
2615 case 3: i915_write_fence_reg(dev, reg, obj); break;
2616 case 2: i830_write_fence_reg(dev, reg, obj); break;
2621 static inline int fence_number(struct drm_i915_private *dev_priv,
2622 struct drm_i915_fence_reg *fence)
2624 return fence - dev_priv->fence_regs;
2627 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2628 struct drm_i915_fence_reg *fence,
2631 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2632 int reg = fence_number(dev_priv, fence);
2634 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2637 obj->fence_reg = reg;
2639 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2641 obj->fence_reg = I915_FENCE_REG_NONE;
2643 list_del_init(&fence->lru_list);
2648 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2650 if (obj->last_fenced_seqno) {
2651 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2655 obj->last_fenced_seqno = 0;
2658 /* Ensure that all CPU reads are completed before installing a fence
2659 * and all writes before removing the fence.
2661 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2664 obj->fenced_gpu_access = false;
2669 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2671 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2674 ret = i915_gem_object_flush_fence(obj);
2678 if (obj->fence_reg == I915_FENCE_REG_NONE)
2681 i915_gem_object_update_fence(obj,
2682 &dev_priv->fence_regs[obj->fence_reg],
2684 i915_gem_object_fence_lost(obj);
2689 static struct drm_i915_fence_reg *
2690 i915_find_fence_reg(struct drm_device *dev)
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 struct drm_i915_fence_reg *reg, *avail;
2696 /* First try to find a free reg */
2698 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2699 reg = &dev_priv->fence_regs[i];
2703 if (!reg->pin_count)
2710 /* None available, try to steal one or wait for a user to finish */
2711 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2722 * i915_gem_object_get_fence - set up fencing for an object
2723 * @obj: object to map through a fence reg
2725 * When mapping objects through the GTT, userspace wants to be able to write
2726 * to them without having to worry about swizzling if the object is tiled.
2727 * This function walks the fence regs looking for a free one for @obj,
2728 * stealing one if it can't find any.
2730 * It then sets up the reg based on the object's properties: address, pitch
2731 * and tiling format.
2733 * For an untiled surface, this removes any existing fence.
2736 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2738 struct drm_device *dev = obj->base.dev;
2739 struct drm_i915_private *dev_priv = dev->dev_private;
2740 bool enable = obj->tiling_mode != I915_TILING_NONE;
2741 struct drm_i915_fence_reg *reg;
2744 /* Have we updated the tiling parameters upon the object and so
2745 * will need to serialise the write to the associated fence register?
2747 if (obj->fence_dirty) {
2748 ret = i915_gem_object_flush_fence(obj);
2753 /* Just update our place in the LRU if our fence is getting reused. */
2754 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2755 reg = &dev_priv->fence_regs[obj->fence_reg];
2756 if (!obj->fence_dirty) {
2757 list_move_tail(®->lru_list,
2758 &dev_priv->mm.fence_list);
2761 } else if (enable) {
2762 reg = i915_find_fence_reg(dev);
2767 struct drm_i915_gem_object *old = reg->obj;
2769 ret = i915_gem_object_flush_fence(old);
2773 i915_gem_object_fence_lost(old);
2778 i915_gem_object_update_fence(obj, reg, enable);
2779 obj->fence_dirty = false;
2784 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2785 struct drm_mm_node *gtt_space,
2786 unsigned long cache_level)
2788 struct drm_mm_node *other;
2790 /* On non-LLC machines we have to be careful when putting differing
2791 * types of snoopable memory together to avoid the prefetcher
2792 * crossing memory domains and dieing.
2797 if (gtt_space == NULL)
2800 if (list_empty(>t_space->node_list))
2803 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2804 if (other->allocated && !other->hole_follows && other->color != cache_level)
2807 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2808 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2814 static void i915_gem_verify_gtt(struct drm_device *dev)
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct drm_i915_gem_object *obj;
2821 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2822 if (obj->gtt_space == NULL) {
2823 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2828 if (obj->cache_level != obj->gtt_space->color) {
2829 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2830 obj->gtt_space->start,
2831 obj->gtt_space->start + obj->gtt_space->size,
2833 obj->gtt_space->color);
2838 if (!i915_gem_valid_gtt_space(dev,
2840 obj->cache_level)) {
2841 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2842 obj->gtt_space->start,
2843 obj->gtt_space->start + obj->gtt_space->size,
2855 * Finds free space in the GTT aperture and binds the object there.
2858 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2860 bool map_and_fenceable,
2863 struct drm_device *dev = obj->base.dev;
2864 drm_i915_private_t *dev_priv = dev->dev_private;
2865 struct drm_mm_node *free_space;
2866 u32 size, fence_size, fence_alignment, unfenced_alignment;
2867 bool mappable, fenceable;
2870 if (obj->madv != I915_MADV_WILLNEED) {
2871 DRM_ERROR("Attempting to bind a purgeable object\n");
2875 fence_size = i915_gem_get_gtt_size(dev,
2878 fence_alignment = i915_gem_get_gtt_alignment(dev,
2881 unfenced_alignment =
2882 i915_gem_get_unfenced_gtt_alignment(dev,
2887 alignment = map_and_fenceable ? fence_alignment :
2889 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2890 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2894 size = map_and_fenceable ? fence_size : obj->base.size;
2896 /* If the object is bigger than the entire aperture, reject it early
2897 * before evicting everything in a vain attempt to find space.
2899 if (obj->base.size >
2900 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2901 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2905 ret = i915_gem_object_get_pages(obj);
2910 if (map_and_fenceable)
2912 drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2913 size, alignment, obj->cache_level,
2914 0, dev_priv->mm.gtt_mappable_end,
2917 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2918 size, alignment, obj->cache_level,
2921 if (free_space != NULL) {
2922 if (map_and_fenceable)
2924 drm_mm_get_block_range_generic(free_space,
2925 size, alignment, obj->cache_level,
2926 0, dev_priv->mm.gtt_mappable_end,
2930 drm_mm_get_block_generic(free_space,
2931 size, alignment, obj->cache_level,
2934 if (obj->gtt_space == NULL) {
2935 ret = i915_gem_evict_something(dev, size, alignment,
2944 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2946 obj->cache_level))) {
2947 drm_mm_put_block(obj->gtt_space);
2948 obj->gtt_space = NULL;
2953 ret = i915_gem_gtt_prepare_object(obj);
2955 drm_mm_put_block(obj->gtt_space);
2956 obj->gtt_space = NULL;
2960 if (!dev_priv->mm.aliasing_ppgtt)
2961 i915_gem_gtt_bind_object(obj, obj->cache_level);
2963 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2964 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2966 obj->gtt_offset = obj->gtt_space->start;
2969 obj->gtt_space->size == fence_size &&
2970 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2973 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2975 obj->map_and_fenceable = mappable && fenceable;
2977 trace_i915_gem_object_bind(obj, map_and_fenceable);
2978 i915_gem_verify_gtt(dev);
2983 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2985 /* If we don't have a page list set up, then we're not pinned
2986 * to GPU, and we can ignore the cache flush because it'll happen
2987 * again at bind time.
2989 if (obj->pages == NULL)
2992 /* If the GPU is snooping the contents of the CPU cache,
2993 * we do not need to manually clear the CPU cache lines. However,
2994 * the caches are only snooped when the render cache is
2995 * flushed/invalidated. As we always have to emit invalidations
2996 * and flushes when moving into and out of the RENDER domain, correct
2997 * snooping behaviour occurs naturally as the result of our domain
3000 if (obj->cache_level != I915_CACHE_NONE)
3003 trace_i915_gem_object_clflush(obj);
3005 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3008 /** Flushes the GTT write domain for the object if it's dirty. */
3010 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3012 uint32_t old_write_domain;
3014 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3017 /* No actual flushing is required for the GTT write domain. Writes
3018 * to it immediately go to main memory as far as we know, so there's
3019 * no chipset flush. It also doesn't land in render cache.
3021 * However, we do have to enforce the order so that all writes through
3022 * the GTT land before any writes to the device, such as updates to
3027 old_write_domain = obj->base.write_domain;
3028 obj->base.write_domain = 0;
3030 trace_i915_gem_object_change_domain(obj,
3031 obj->base.read_domains,
3035 /** Flushes the CPU write domain for the object if it's dirty. */
3037 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3039 uint32_t old_write_domain;
3041 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3044 i915_gem_clflush_object(obj);
3045 intel_gtt_chipset_flush();
3046 old_write_domain = obj->base.write_domain;
3047 obj->base.write_domain = 0;
3049 trace_i915_gem_object_change_domain(obj,
3050 obj->base.read_domains,
3055 * Moves a single object to the GTT read, and possibly write domain.
3057 * This function returns when the move is complete, including waiting on
3061 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3063 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3064 uint32_t old_write_domain, old_read_domains;
3067 /* Not valid to be called on unbound objects. */
3068 if (obj->gtt_space == NULL)
3071 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3074 ret = i915_gem_object_wait_rendering(obj, !write);
3078 i915_gem_object_flush_cpu_write_domain(obj);
3080 old_write_domain = obj->base.write_domain;
3081 old_read_domains = obj->base.read_domains;
3083 /* It should now be out of any other write domains, and we can update
3084 * the domain values for our changes.
3086 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3087 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3089 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3090 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3094 trace_i915_gem_object_change_domain(obj,
3098 /* And bump the LRU for this access */
3099 if (i915_gem_object_is_inactive(obj))
3100 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3105 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3106 enum i915_cache_level cache_level)
3108 struct drm_device *dev = obj->base.dev;
3109 drm_i915_private_t *dev_priv = dev->dev_private;
3112 if (obj->cache_level == cache_level)
3115 if (obj->pin_count) {
3116 DRM_DEBUG("can not change the cache level of pinned objects\n");
3120 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3121 ret = i915_gem_object_unbind(obj);
3126 if (obj->gtt_space) {
3127 ret = i915_gem_object_finish_gpu(obj);
3131 i915_gem_object_finish_gtt(obj);
3133 /* Before SandyBridge, you could not use tiling or fence
3134 * registers with snooped memory, so relinquish any fences
3135 * currently pointing to our region in the aperture.
3137 if (INTEL_INFO(dev)->gen < 6) {
3138 ret = i915_gem_object_put_fence(obj);
3143 if (obj->has_global_gtt_mapping)
3144 i915_gem_gtt_bind_object(obj, cache_level);
3145 if (obj->has_aliasing_ppgtt_mapping)
3146 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3149 obj->gtt_space->color = cache_level;
3152 if (cache_level == I915_CACHE_NONE) {
3153 u32 old_read_domains, old_write_domain;
3155 /* If we're coming from LLC cached, then we haven't
3156 * actually been tracking whether the data is in the
3157 * CPU cache or not, since we only allow one bit set
3158 * in obj->write_domain and have been skipping the clflushes.
3159 * Just set it to the CPU cache for now.
3161 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3162 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3164 old_read_domains = obj->base.read_domains;
3165 old_write_domain = obj->base.write_domain;
3167 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3168 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3170 trace_i915_gem_object_change_domain(obj,
3175 obj->cache_level = cache_level;
3176 i915_gem_verify_gtt(dev);
3180 int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data,
3181 struct drm_file *file)
3183 struct drm_i915_gem_cacheing *args = data;
3184 struct drm_i915_gem_object *obj;
3187 ret = i915_mutex_lock_interruptible(dev);
3191 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3192 if (&obj->base == NULL) {
3197 args->cacheing = obj->cache_level != I915_CACHE_NONE;
3199 drm_gem_object_unreference(&obj->base);
3201 mutex_unlock(&dev->struct_mutex);
3205 int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data,
3206 struct drm_file *file)
3208 struct drm_i915_gem_cacheing *args = data;
3209 struct drm_i915_gem_object *obj;
3210 enum i915_cache_level level;
3213 ret = i915_mutex_lock_interruptible(dev);
3217 switch (args->cacheing) {
3218 case I915_CACHEING_NONE:
3219 level = I915_CACHE_NONE;
3221 case I915_CACHEING_CACHED:
3222 level = I915_CACHE_LLC;
3228 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3229 if (&obj->base == NULL) {
3234 ret = i915_gem_object_set_cache_level(obj, level);
3236 drm_gem_object_unreference(&obj->base);
3238 mutex_unlock(&dev->struct_mutex);
3243 * Prepare buffer for display plane (scanout, cursors, etc).
3244 * Can be called from an uninterruptible phase (modesetting) and allows
3245 * any flushes to be pipelined (for pageflips).
3248 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3250 struct intel_ring_buffer *pipelined)
3252 u32 old_read_domains, old_write_domain;
3255 if (pipelined != obj->ring) {
3256 ret = i915_gem_object_sync(obj, pipelined);
3261 /* The display engine is not coherent with the LLC cache on gen6. As
3262 * a result, we make sure that the pinning that is about to occur is
3263 * done with uncached PTEs. This is lowest common denominator for all
3266 * However for gen6+, we could do better by using the GFDT bit instead
3267 * of uncaching, which would allow us to flush all the LLC-cached data
3268 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3270 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3274 /* As the user may map the buffer once pinned in the display plane
3275 * (e.g. libkms for the bootup splash), we have to ensure that we
3276 * always use map_and_fenceable for all scanout buffers.
3278 ret = i915_gem_object_pin(obj, alignment, true, false);
3282 i915_gem_object_flush_cpu_write_domain(obj);
3284 old_write_domain = obj->base.write_domain;
3285 old_read_domains = obj->base.read_domains;
3287 /* It should now be out of any other write domains, and we can update
3288 * the domain values for our changes.
3290 obj->base.write_domain = 0;
3291 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3293 trace_i915_gem_object_change_domain(obj,
3301 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3305 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3308 ret = i915_gem_object_wait_rendering(obj, false);
3312 /* Ensure that we invalidate the GPU's caches and TLBs. */
3313 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3318 * Moves a single object to the CPU read, and possibly write domain.
3320 * This function returns when the move is complete, including waiting on
3324 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3326 uint32_t old_write_domain, old_read_domains;
3329 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3332 ret = i915_gem_object_wait_rendering(obj, !write);
3336 i915_gem_object_flush_gtt_write_domain(obj);
3338 old_write_domain = obj->base.write_domain;
3339 old_read_domains = obj->base.read_domains;
3341 /* Flush the CPU cache if it's still invalid. */
3342 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3343 i915_gem_clflush_object(obj);
3345 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3348 /* It should now be out of any other write domains, and we can update
3349 * the domain values for our changes.
3351 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3353 /* If we're writing through the CPU, then the GPU read domains will
3354 * need to be invalidated at next use.
3357 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3358 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3361 trace_i915_gem_object_change_domain(obj,
3368 /* Throttle our rendering by waiting until the ring has completed our requests
3369 * emitted over 20 msec ago.
3371 * Note that if we were to use the current jiffies each time around the loop,
3372 * we wouldn't escape the function with any frames outstanding if the time to
3373 * render a frame was over 20ms.
3375 * This should get us reasonable parallelism between CPU and GPU but also
3376 * relatively low latency when blocking on a particular request to finish.
3379 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct drm_i915_file_private *file_priv = file->driver_priv;
3383 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3384 struct drm_i915_gem_request *request;
3385 struct intel_ring_buffer *ring = NULL;
3389 if (atomic_read(&dev_priv->mm.wedged))
3392 spin_lock(&file_priv->mm.lock);
3393 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3394 if (time_after_eq(request->emitted_jiffies, recent_enough))
3397 ring = request->ring;
3398 seqno = request->seqno;
3400 spin_unlock(&file_priv->mm.lock);
3405 ret = __wait_seqno(ring, seqno, true, NULL);
3407 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3413 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3415 bool map_and_fenceable,
3420 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3422 if (obj->gtt_space != NULL) {
3423 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3424 (map_and_fenceable && !obj->map_and_fenceable)) {
3425 WARN(obj->pin_count,
3426 "bo is already pinned with incorrect alignment:"
3427 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3428 " obj->map_and_fenceable=%d\n",
3429 obj->gtt_offset, alignment,
3431 obj->map_and_fenceable);
3432 ret = i915_gem_object_unbind(obj);
3438 if (obj->gtt_space == NULL) {
3439 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3446 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3447 i915_gem_gtt_bind_object(obj, obj->cache_level);
3450 obj->pin_mappable |= map_and_fenceable;
3456 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3458 BUG_ON(obj->pin_count == 0);
3459 BUG_ON(obj->gtt_space == NULL);
3461 if (--obj->pin_count == 0)
3462 obj->pin_mappable = false;
3466 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3467 struct drm_file *file)
3469 struct drm_i915_gem_pin *args = data;
3470 struct drm_i915_gem_object *obj;
3473 ret = i915_mutex_lock_interruptible(dev);
3477 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3478 if (&obj->base == NULL) {
3483 if (obj->madv != I915_MADV_WILLNEED) {
3484 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3489 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3490 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3496 obj->user_pin_count++;
3497 obj->pin_filp = file;
3498 if (obj->user_pin_count == 1) {
3499 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3504 /* XXX - flush the CPU caches for pinned objects
3505 * as the X server doesn't manage domains yet
3507 i915_gem_object_flush_cpu_write_domain(obj);
3508 args->offset = obj->gtt_offset;
3510 drm_gem_object_unreference(&obj->base);
3512 mutex_unlock(&dev->struct_mutex);
3517 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3518 struct drm_file *file)
3520 struct drm_i915_gem_pin *args = data;
3521 struct drm_i915_gem_object *obj;
3524 ret = i915_mutex_lock_interruptible(dev);
3528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3529 if (&obj->base == NULL) {
3534 if (obj->pin_filp != file) {
3535 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3540 obj->user_pin_count--;
3541 if (obj->user_pin_count == 0) {
3542 obj->pin_filp = NULL;
3543 i915_gem_object_unpin(obj);
3547 drm_gem_object_unreference(&obj->base);
3549 mutex_unlock(&dev->struct_mutex);
3554 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3555 struct drm_file *file)
3557 struct drm_i915_gem_busy *args = data;
3558 struct drm_i915_gem_object *obj;
3561 ret = i915_mutex_lock_interruptible(dev);
3565 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3566 if (&obj->base == NULL) {
3571 /* Count all active objects as busy, even if they are currently not used
3572 * by the gpu. Users of this interface expect objects to eventually
3573 * become non-busy without any further actions, therefore emit any
3574 * necessary flushes here.
3576 ret = i915_gem_object_flush_active(obj);
3578 args->busy = obj->active;
3580 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3581 args->busy |= intel_ring_flag(obj->ring) << 16;
3584 drm_gem_object_unreference(&obj->base);
3586 mutex_unlock(&dev->struct_mutex);
3591 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3592 struct drm_file *file_priv)
3594 return i915_gem_ring_throttle(dev, file_priv);
3598 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3599 struct drm_file *file_priv)
3601 struct drm_i915_gem_madvise *args = data;
3602 struct drm_i915_gem_object *obj;
3605 switch (args->madv) {
3606 case I915_MADV_DONTNEED:
3607 case I915_MADV_WILLNEED:
3613 ret = i915_mutex_lock_interruptible(dev);
3617 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3618 if (&obj->base == NULL) {
3623 if (obj->pin_count) {
3628 if (obj->madv != __I915_MADV_PURGED)
3629 obj->madv = args->madv;
3631 /* if the object is no longer attached, discard its backing storage */
3632 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3633 i915_gem_object_truncate(obj);
3635 args->retained = obj->madv != __I915_MADV_PURGED;
3638 drm_gem_object_unreference(&obj->base);
3640 mutex_unlock(&dev->struct_mutex);
3644 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3645 const struct drm_i915_gem_object_ops *ops)
3647 INIT_LIST_HEAD(&obj->mm_list);
3648 INIT_LIST_HEAD(&obj->gtt_list);
3649 INIT_LIST_HEAD(&obj->ring_list);
3650 INIT_LIST_HEAD(&obj->exec_list);
3654 obj->fence_reg = I915_FENCE_REG_NONE;
3655 obj->madv = I915_MADV_WILLNEED;
3656 /* Avoid an unnecessary call to unbind on the first bind. */
3657 obj->map_and_fenceable = true;
3659 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3662 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3663 .get_pages = i915_gem_object_get_pages_gtt,
3664 .put_pages = i915_gem_object_put_pages_gtt,
3667 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3670 struct drm_i915_gem_object *obj;
3671 struct address_space *mapping;
3674 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3678 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3683 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3684 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3685 /* 965gm cannot relocate objects above 4GiB. */
3686 mask &= ~__GFP_HIGHMEM;
3687 mask |= __GFP_DMA32;
3690 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3691 mapping_set_gfp_mask(mapping, mask);
3693 i915_gem_object_init(obj, &i915_gem_object_ops);
3695 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3696 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3699 /* On some devices, we can have the GPU use the LLC (the CPU
3700 * cache) for about a 10% performance improvement
3701 * compared to uncached. Graphics requests other than
3702 * display scanout are coherent with the CPU in
3703 * accessing this cache. This means in this mode we
3704 * don't need to clflush on the CPU side, and on the
3705 * GPU side we only need to flush internal caches to
3706 * get data visible to the CPU.
3708 * However, we maintain the display planes as UC, and so
3709 * need to rebind when first used as such.
3711 obj->cache_level = I915_CACHE_LLC;
3713 obj->cache_level = I915_CACHE_NONE;
3718 int i915_gem_init_object(struct drm_gem_object *obj)
3725 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3727 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3728 struct drm_device *dev = obj->base.dev;
3729 drm_i915_private_t *dev_priv = dev->dev_private;
3731 trace_i915_gem_object_destroy(obj);
3733 if (gem_obj->import_attach)
3734 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3737 i915_gem_detach_phys_object(dev, obj);
3740 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3741 bool was_interruptible;
3743 was_interruptible = dev_priv->mm.interruptible;
3744 dev_priv->mm.interruptible = false;
3746 WARN_ON(i915_gem_object_unbind(obj));
3748 dev_priv->mm.interruptible = was_interruptible;
3751 obj->pages_pin_count = 0;
3752 i915_gem_object_put_pages(obj);
3753 i915_gem_object_free_mmap_offset(obj);
3755 drm_gem_object_release(&obj->base);
3756 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3763 i915_gem_idle(struct drm_device *dev)
3765 drm_i915_private_t *dev_priv = dev->dev_private;
3768 mutex_lock(&dev->struct_mutex);
3770 if (dev_priv->mm.suspended) {
3771 mutex_unlock(&dev->struct_mutex);
3775 ret = i915_gpu_idle(dev);
3777 mutex_unlock(&dev->struct_mutex);
3780 i915_gem_retire_requests(dev);
3782 /* Under UMS, be paranoid and evict. */
3783 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3784 i915_gem_evict_everything(dev);
3786 i915_gem_reset_fences(dev);
3788 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3789 * We need to replace this with a semaphore, or something.
3790 * And not confound mm.suspended!
3792 dev_priv->mm.suspended = 1;
3793 del_timer_sync(&dev_priv->hangcheck_timer);
3795 i915_kernel_lost_context(dev);
3796 i915_gem_cleanup_ringbuffer(dev);
3798 mutex_unlock(&dev->struct_mutex);
3800 /* Cancel the retire work handler, which should be idle now. */
3801 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3806 void i915_gem_l3_remap(struct drm_device *dev)
3808 drm_i915_private_t *dev_priv = dev->dev_private;
3812 if (!IS_IVYBRIDGE(dev))
3815 if (!dev_priv->mm.l3_remap_info)
3818 misccpctl = I915_READ(GEN7_MISCCPCTL);
3819 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3820 POSTING_READ(GEN7_MISCCPCTL);
3822 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3823 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3824 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3825 DRM_DEBUG("0x%x was already programmed to %x\n",
3826 GEN7_L3LOG_BASE + i, remap);
3827 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3828 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3829 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3832 /* Make sure all the writes land before disabling dop clock gating */
3833 POSTING_READ(GEN7_L3LOG_BASE);
3835 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3838 void i915_gem_init_swizzling(struct drm_device *dev)
3840 drm_i915_private_t *dev_priv = dev->dev_private;
3842 if (INTEL_INFO(dev)->gen < 5 ||
3843 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3846 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3847 DISP_TILE_SURFACE_SWIZZLING);
3852 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3854 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3856 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3859 void i915_gem_init_ppgtt(struct drm_device *dev)
3861 drm_i915_private_t *dev_priv = dev->dev_private;
3863 struct intel_ring_buffer *ring;
3864 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3865 uint32_t __iomem *pd_addr;
3869 if (!dev_priv->mm.aliasing_ppgtt)
3873 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3874 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3877 if (dev_priv->mm.gtt->needs_dmar)
3878 pt_addr = ppgtt->pt_dma_addr[i];
3880 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3882 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3883 pd_entry |= GEN6_PDE_VALID;
3885 writel(pd_entry, pd_addr + i);
3889 pd_offset = ppgtt->pd_offset;
3890 pd_offset /= 64; /* in cachelines, */
3893 if (INTEL_INFO(dev)->gen == 6) {
3894 uint32_t ecochk, gab_ctl, ecobits;
3896 ecobits = I915_READ(GAC_ECO_BITS);
3897 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3899 gab_ctl = I915_READ(GAB_CTL);
3900 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3902 ecochk = I915_READ(GAM_ECOCHK);
3903 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3904 ECOCHK_PPGTT_CACHE64B);
3905 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3906 } else if (INTEL_INFO(dev)->gen >= 7) {
3907 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3908 /* GFX_MODE is per-ring on gen7+ */
3911 for_each_ring(ring, dev_priv, i) {
3912 if (INTEL_INFO(dev)->gen >= 7)
3913 I915_WRITE(RING_MODE_GEN7(ring),
3914 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3916 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3917 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3922 intel_enable_blt(struct drm_device *dev)
3927 /* The blitter was dysfunctional on early prototypes */
3928 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3929 DRM_INFO("BLT not supported on this pre-production hardware;"
3930 " graphics performance will be degraded.\n");
3938 i915_gem_init_hw(struct drm_device *dev)
3940 drm_i915_private_t *dev_priv = dev->dev_private;
3943 if (!intel_enable_gtt())
3946 i915_gem_l3_remap(dev);
3948 i915_gem_init_swizzling(dev);
3950 ret = intel_init_render_ring_buffer(dev);
3955 ret = intel_init_bsd_ring_buffer(dev);
3957 goto cleanup_render_ring;
3960 if (intel_enable_blt(dev)) {
3961 ret = intel_init_blt_ring_buffer(dev);
3963 goto cleanup_bsd_ring;
3966 dev_priv->next_seqno = 1;
3969 * XXX: There was some w/a described somewhere suggesting loading
3970 * contexts before PPGTT.
3972 i915_gem_context_init(dev);
3973 i915_gem_init_ppgtt(dev);
3978 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3979 cleanup_render_ring:
3980 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3985 intel_enable_ppgtt(struct drm_device *dev)
3987 if (i915_enable_ppgtt >= 0)
3988 return i915_enable_ppgtt;
3990 #ifdef CONFIG_INTEL_IOMMU
3991 /* Disable ppgtt on SNB if VT-d is on. */
3992 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3999 int i915_gem_init(struct drm_device *dev)
4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002 unsigned long gtt_size, mappable_size;
4005 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
4006 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4008 mutex_lock(&dev->struct_mutex);
4009 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4010 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4011 * aperture accordingly when using aliasing ppgtt. */
4012 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4014 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4016 ret = i915_gem_init_aliasing_ppgtt(dev);
4018 mutex_unlock(&dev->struct_mutex);
4022 /* Let GEM Manage all of the aperture.
4024 * However, leave one page at the end still bound to the scratch
4025 * page. There are a number of places where the hardware
4026 * apparently prefetches past the end of the object, and we've
4027 * seen multiple hangs with the GPU head pointer stuck in a
4028 * batchbuffer bound at the last page of the aperture. One page
4029 * should be enough to keep any prefetching inside of the
4032 i915_gem_init_global_gtt(dev, 0, mappable_size,
4036 ret = i915_gem_init_hw(dev);
4037 mutex_unlock(&dev->struct_mutex);
4039 i915_gem_cleanup_aliasing_ppgtt(dev);
4043 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4044 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4045 dev_priv->dri1.allow_batchbuffer = 1;
4050 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4052 drm_i915_private_t *dev_priv = dev->dev_private;
4053 struct intel_ring_buffer *ring;
4056 for_each_ring(ring, dev_priv, i)
4057 intel_cleanup_ring_buffer(ring);
4061 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4062 struct drm_file *file_priv)
4064 drm_i915_private_t *dev_priv = dev->dev_private;
4067 if (drm_core_check_feature(dev, DRIVER_MODESET))
4070 if (atomic_read(&dev_priv->mm.wedged)) {
4071 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4072 atomic_set(&dev_priv->mm.wedged, 0);
4075 mutex_lock(&dev->struct_mutex);
4076 dev_priv->mm.suspended = 0;
4078 ret = i915_gem_init_hw(dev);
4080 mutex_unlock(&dev->struct_mutex);
4084 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4085 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4086 mutex_unlock(&dev->struct_mutex);
4088 ret = drm_irq_install(dev);
4090 goto cleanup_ringbuffer;
4095 mutex_lock(&dev->struct_mutex);
4096 i915_gem_cleanup_ringbuffer(dev);
4097 dev_priv->mm.suspended = 1;
4098 mutex_unlock(&dev->struct_mutex);
4104 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4105 struct drm_file *file_priv)
4107 if (drm_core_check_feature(dev, DRIVER_MODESET))
4110 drm_irq_uninstall(dev);
4111 return i915_gem_idle(dev);
4115 i915_gem_lastclose(struct drm_device *dev)
4119 if (drm_core_check_feature(dev, DRIVER_MODESET))
4122 ret = i915_gem_idle(dev);
4124 DRM_ERROR("failed to idle hardware: %d\n", ret);
4128 init_ring_lists(struct intel_ring_buffer *ring)
4130 INIT_LIST_HEAD(&ring->active_list);
4131 INIT_LIST_HEAD(&ring->request_list);
4135 i915_gem_load(struct drm_device *dev)
4138 drm_i915_private_t *dev_priv = dev->dev_private;
4140 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4141 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4142 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4143 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4144 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4145 for (i = 0; i < I915_NUM_RINGS; i++)
4146 init_ring_lists(&dev_priv->ring[i]);
4147 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4148 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4149 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4150 i915_gem_retire_work_handler);
4151 init_completion(&dev_priv->error_completion);
4153 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4155 I915_WRITE(MI_ARB_STATE,
4156 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4159 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4161 /* Old X drivers will take 0-2 for front, back, depth buffers */
4162 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4163 dev_priv->fence_reg_start = 3;
4165 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4166 dev_priv->num_fence_regs = 16;
4168 dev_priv->num_fence_regs = 8;
4170 /* Initialize fence registers to zero */
4171 i915_gem_reset_fences(dev);
4173 i915_gem_detect_bit_6_swizzle(dev);
4174 init_waitqueue_head(&dev_priv->pending_flip_queue);
4176 dev_priv->mm.interruptible = true;
4178 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4179 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4180 register_shrinker(&dev_priv->mm.inactive_shrinker);
4184 * Create a physically contiguous memory object for this object
4185 * e.g. for cursor + overlay regs
4187 static int i915_gem_init_phys_object(struct drm_device *dev,
4188 int id, int size, int align)
4190 drm_i915_private_t *dev_priv = dev->dev_private;
4191 struct drm_i915_gem_phys_object *phys_obj;
4194 if (dev_priv->mm.phys_objs[id - 1] || !size)
4197 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4203 phys_obj->handle = drm_pci_alloc(dev, size, align);
4204 if (!phys_obj->handle) {
4209 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4212 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4220 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4222 drm_i915_private_t *dev_priv = dev->dev_private;
4223 struct drm_i915_gem_phys_object *phys_obj;
4225 if (!dev_priv->mm.phys_objs[id - 1])
4228 phys_obj = dev_priv->mm.phys_objs[id - 1];
4229 if (phys_obj->cur_obj) {
4230 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4234 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4236 drm_pci_free(dev, phys_obj->handle);
4238 dev_priv->mm.phys_objs[id - 1] = NULL;
4241 void i915_gem_free_all_phys_object(struct drm_device *dev)
4245 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4246 i915_gem_free_phys_object(dev, i);
4249 void i915_gem_detach_phys_object(struct drm_device *dev,
4250 struct drm_i915_gem_object *obj)
4252 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4259 vaddr = obj->phys_obj->handle->vaddr;
4261 page_count = obj->base.size / PAGE_SIZE;
4262 for (i = 0; i < page_count; i++) {
4263 struct page *page = shmem_read_mapping_page(mapping, i);
4264 if (!IS_ERR(page)) {
4265 char *dst = kmap_atomic(page);
4266 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4269 drm_clflush_pages(&page, 1);
4271 set_page_dirty(page);
4272 mark_page_accessed(page);
4273 page_cache_release(page);
4276 intel_gtt_chipset_flush();
4278 obj->phys_obj->cur_obj = NULL;
4279 obj->phys_obj = NULL;
4283 i915_gem_attach_phys_object(struct drm_device *dev,
4284 struct drm_i915_gem_object *obj,
4288 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4289 drm_i915_private_t *dev_priv = dev->dev_private;
4294 if (id > I915_MAX_PHYS_OBJECT)
4297 if (obj->phys_obj) {
4298 if (obj->phys_obj->id == id)
4300 i915_gem_detach_phys_object(dev, obj);
4303 /* create a new object */
4304 if (!dev_priv->mm.phys_objs[id - 1]) {
4305 ret = i915_gem_init_phys_object(dev, id,
4306 obj->base.size, align);
4308 DRM_ERROR("failed to init phys object %d size: %zu\n",
4309 id, obj->base.size);
4314 /* bind to the object */
4315 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4316 obj->phys_obj->cur_obj = obj;
4318 page_count = obj->base.size / PAGE_SIZE;
4320 for (i = 0; i < page_count; i++) {
4324 page = shmem_read_mapping_page(mapping, i);
4326 return PTR_ERR(page);
4328 src = kmap_atomic(page);
4329 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4330 memcpy(dst, src, PAGE_SIZE);
4333 mark_page_accessed(page);
4334 page_cache_release(page);
4341 i915_gem_phys_pwrite(struct drm_device *dev,
4342 struct drm_i915_gem_object *obj,
4343 struct drm_i915_gem_pwrite *args,
4344 struct drm_file *file_priv)
4346 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4347 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4349 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4350 unsigned long unwritten;
4352 /* The physical object once assigned is fixed for the lifetime
4353 * of the obj, so we can safely drop the lock and continue
4356 mutex_unlock(&dev->struct_mutex);
4357 unwritten = copy_from_user(vaddr, user_data, args->size);
4358 mutex_lock(&dev->struct_mutex);
4363 intel_gtt_chipset_flush();
4367 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4369 struct drm_i915_file_private *file_priv = file->driver_priv;
4371 /* Clean up our request list when the client is going away, so that
4372 * later retire_requests won't dereference our soon-to-be-gone
4375 spin_lock(&file_priv->mm.lock);
4376 while (!list_empty(&file_priv->mm.request_list)) {
4377 struct drm_i915_gem_request *request;
4379 request = list_first_entry(&file_priv->mm.request_list,
4380 struct drm_i915_gem_request,
4382 list_del(&request->client_list);
4383 request->file_priv = NULL;
4385 spin_unlock(&file_priv->mm.lock);
4389 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4391 struct drm_i915_private *dev_priv =
4392 container_of(shrinker,
4393 struct drm_i915_private,
4394 mm.inactive_shrinker);
4395 struct drm_device *dev = dev_priv->dev;
4396 struct drm_i915_gem_object *obj;
4397 int nr_to_scan = sc->nr_to_scan;
4400 if (!mutex_trylock(&dev->struct_mutex))
4404 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4406 i915_gem_shrink_all(dev_priv);
4410 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4411 if (obj->pages_pin_count == 0)
4412 cnt += obj->base.size >> PAGE_SHIFT;
4413 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4414 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4415 cnt += obj->base.size >> PAGE_SHIFT;
4417 mutex_unlock(&dev->struct_mutex);