drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  65
  66 static bool cpu_cache_is_coherent(struct drm_device *dev,
  67                                   enum i915_cache_level level)
  68 {
  69         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  70 }
  71
  72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  73 {
  74         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  75                 return true;
  76
  77         return obj->pin_display;
  78 }
  79
  80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  81 {
  82         if (obj->tiling_mode)
  83                 i915_gem_release_mmap(obj);
  84
  85         /* As we do not have an associated fence register, we will force
  86          * a tiling change if we ever need to acquire one.
  87          */
  88         obj->fence_dirty = false;
  89         obj->fence_reg = I915_FENCE_REG_NONE;
  90 }
  91
  92 /* some bookkeeping */
  93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  94                                   size_t size)
  95 {
  96         spin_lock(&dev_priv->mm.object_stat_lock);
  97         dev_priv->mm.object_count++;
  98         dev_priv->mm.object_memory += size;
  99         spin_unlock(&dev_priv->mm.object_stat_lock);
 100 }
 101
 102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 103                                      size_t size)
 104 {
 105         spin_lock(&dev_priv->mm.object_stat_lock);
 106         dev_priv->mm.object_count--;
 107         dev_priv->mm.object_memory -= size;
 108         spin_unlock(&dev_priv->mm.object_stat_lock);
 109 }
 110
 111 static int
 112 i915_gem_wait_for_error(struct i915_gpu_error *error)
 113 {
 114         int ret;
 115
 116 #define EXIT_COND (!i915_reset_in_progress(error) || \
 117                    i915_terminally_wedged(error))
 118         if (EXIT_COND)
 119                 return 0;
 120
 121         /*
 122          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 123          * userspace. If it takes that long something really bad is going on and
 124          * we should simply try to bail out and fail as gracefully as possible.
 125          */
 126         ret = wait_event_interruptible_timeout(error->reset_queue,
 127                                                EXIT_COND,
 128                                                10*HZ);
 129         if (ret == 0) {
 130                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 131                 return -EIO;
 132         } else if (ret < 0) {
 133                 return ret;
 134         }
 135 #undef EXIT_COND
 136
 137         return 0;
 138 }
 139
 140 int i915_mutex_lock_interruptible(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         int ret;
 144
 145         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 146         if (ret)
 147                 return ret;
 148
 149         ret = mutex_lock_interruptible(&dev->struct_mutex);
 150         if (ret)
 151                 return ret;
 152
 153         WARN_ON(i915_verify_lists(dev));
 154         return 0;
 155 }
 156
 157 static inline bool
 158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 159 {
 160         return i915_gem_obj_bound_any(obj) && !obj->active;
 161 }
 162
 163 int
 164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 165                     struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_init *args = data;
 169
 170         if (drm_core_check_feature(dev, DRIVER_MODESET))
 171                 return -ENODEV;
 172
 173         if (args->gtt_start >= args->gtt_end ||
 174             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 175                 return -EINVAL;
 176
 177         /* GEM with user mode setting was never supported on ilk and later. */
 178         if (INTEL_INFO(dev)->gen >= 5)
 179                 return -ENODEV;
 180
 181         mutex_lock(&dev->struct_mutex);
 182         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 183                                   args->gtt_end);
 184         dev_priv->gtt.mappable_end = args->gtt_end;
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         return 0;
 188 }
 189
 190 int
 191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *file)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         struct drm_i915_gem_get_aperture *args = data;
 196         struct drm_i915_gem_object *obj;
 197         size_t pinned;
 198
 199         pinned = 0;
 200         mutex_lock(&dev->struct_mutex);
 201         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 202                 if (i915_gem_obj_is_pinned(obj))
 203                         pinned += i915_gem_obj_ggtt_size(obj);
 204         mutex_unlock(&dev->struct_mutex);
 205
 206         args->aper_size = dev_priv->gtt.base.total;
 207         args->aper_available_size = args->aper_size - pinned;
 208
 209         return 0;
 210 }
 211
 212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
 213 {
 214         drm_dma_handle_t *phys = obj->phys_handle;
 215
 216         if (!phys)
 217                 return;
 218
 219         if (obj->madv == I915_MADV_WILLNEED) {
 220                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 221                 char *vaddr = phys->vaddr;
 222                 int i;
 223
 224                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 225                         struct page *page = shmem_read_mapping_page(mapping, i);
 226                         if (!IS_ERR(page)) {
 227                                 char *dst = kmap_atomic(page);
 228                                 memcpy(dst, vaddr, PAGE_SIZE);
 229                                 drm_clflush_virt_range(dst, PAGE_SIZE);
 230                                 kunmap_atomic(dst);
 231
 232                                 set_page_dirty(page);
 233                                 mark_page_accessed(page);
 234                                 page_cache_release(page);
 235                         }
 236                         vaddr += PAGE_SIZE;
 237                 }
 238                 i915_gem_chipset_flush(obj->base.dev);
 239         }
 240
 241 #ifdef CONFIG_X86
 242         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 243 #endif
 244         drm_pci_free(obj->base.dev, phys);
 245         obj->phys_handle = NULL;
 246 }
 247
 248 int
 249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 250                             int align)
 251 {
 252         drm_dma_handle_t *phys;
 253         struct address_space *mapping;
 254         char *vaddr;
 255         int i;
 256
 257         if (obj->phys_handle) {
 258                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 259                         return -EBUSY;
 260
 261                 return 0;
 262         }
 263
 264         if (obj->madv != I915_MADV_WILLNEED)
 265                 return -EFAULT;
 266
 267         if (obj->base.filp == NULL)
 268                 return -EINVAL;
 269
 270         /* create a new object */
 271         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 272         if (!phys)
 273                 return -ENOMEM;
 274
 275         vaddr = phys->vaddr;
 276 #ifdef CONFIG_X86
 277         set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
 278 #endif
 279         mapping = file_inode(obj->base.filp)->i_mapping;
 280         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 281                 struct page *page;
 282                 char *src;
 283
 284                 page = shmem_read_mapping_page(mapping, i);
 285                 if (IS_ERR(page)) {
 286 #ifdef CONFIG_X86
 287                         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 288 #endif
 289                         drm_pci_free(obj->base.dev, phys);
 290                         return PTR_ERR(page);
 291                 }
 292
 293                 src = kmap_atomic(page);
 294                 memcpy(vaddr, src, PAGE_SIZE);
 295                 kunmap_atomic(src);
 296
 297                 mark_page_accessed(page);
 298                 page_cache_release(page);
 299
 300                 vaddr += PAGE_SIZE;
 301         }
 302
 303         obj->phys_handle = phys;
 304         return 0;
 305 }
 306
 307 static int
 308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 309                      struct drm_i915_gem_pwrite *args,
 310                      struct drm_file *file_priv)
 311 {
 312         struct drm_device *dev = obj->base.dev;
 313         void *vaddr = obj->phys_handle->vaddr + args->offset;
 314         char __user *user_data = to_user_ptr(args->data_ptr);
 315
 316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 317                 unsigned long unwritten;
 318
 319                 /* The physical object once assigned is fixed for the lifetime
 320                  * of the obj, so we can safely drop the lock and continue
 321                  * to access vaddr.
 322                  */
 323                 mutex_unlock(&dev->struct_mutex);
 324                 unwritten = copy_from_user(vaddr, user_data, args->size);
 325                 mutex_lock(&dev->struct_mutex);
 326                 if (unwritten)
 327                         return -EFAULT;
 328         }
 329
 330         i915_gem_chipset_flush(dev);
 331         return 0;
 332 }
 333
 334 void *i915_gem_object_alloc(struct drm_device *dev)
 335 {
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 338 }
 339
 340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 341 {
 342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 343         kmem_cache_free(dev_priv->slab, obj);
 344 }
 345
 346 static int
 347 i915_gem_create(struct drm_file *file,
 348                 struct drm_device *dev,
 349                 uint64_t size,
 350                 uint32_t *handle_p)
 351 {
 352         struct drm_i915_gem_object *obj;
 353         int ret;
 354         u32 handle;
 355
 356         size = roundup(size, PAGE_SIZE);
 357         if (size == 0)
 358                 return -EINVAL;
 359
 360         /* Allocate the new object */
 361         obj = i915_gem_alloc_object(dev, size);
 362         if (obj == NULL)
 363                 return -ENOMEM;
 364
 365         ret = drm_gem_handle_create(file, &obj->base, &handle);
 366         /* drop reference from allocate - handle holds it now */
 367         drm_gem_object_unreference_unlocked(&obj->base);
 368         if (ret)
 369                 return ret;
 370
 371         *handle_p = handle;
 372         return 0;
 373 }
 374
 375 int
 376 i915_gem_dumb_create(struct drm_file *file,
 377                      struct drm_device *dev,
 378                      struct drm_mode_create_dumb *args)
 379 {
 380         /* have to work out size/pitch and return them */
 381         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 382         args->size = args->pitch * args->height;
 383         return i915_gem_create(file, dev,
 384                                args->size, &args->handle);
 385 }
 386
 387 /**
 388  * Creates a new mm object and returns a handle to it.
 389  */
 390 int
 391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 392                       struct drm_file *file)
 393 {
 394         struct drm_i915_gem_create *args = data;
 395
 396         return i915_gem_create(file, dev,
 397                                args->size, &args->handle);
 398 }
 399
 400 static inline int
 401 __copy_to_user_swizzled(char __user *cpu_vaddr,
 402                         const char *gpu_vaddr, int gpu_offset,
 403                         int length)
 404 {
 405         int ret, cpu_offset = 0;
 406
 407         while (length > 0) {
 408                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 409                 int this_length = min(cacheline_end - gpu_offset, length);
 410                 int swizzled_gpu_offset = gpu_offset ^ 64;
 411
 412                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 413                                      gpu_vaddr + swizzled_gpu_offset,
 414                                      this_length);
 415                 if (ret)
 416                         return ret + length;
 417
 418                 cpu_offset += this_length;
 419                 gpu_offset += this_length;
 420                 length -= this_length;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static inline int
 427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 428                           const char __user *cpu_vaddr,
 429                           int length)
 430 {
 431         int ret, cpu_offset = 0;
 432
 433         while (length > 0) {
 434                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 435                 int this_length = min(cacheline_end - gpu_offset, length);
 436                 int swizzled_gpu_offset = gpu_offset ^ 64;
 437
 438                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 439                                        cpu_vaddr + cpu_offset,
 440                                        this_length);
 441                 if (ret)
 442                         return ret + length;
 443
 444                 cpu_offset += this_length;
 445                 gpu_offset += this_length;
 446                 length -= this_length;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * Pins the specified object's pages and synchronizes the object with
 454  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 455  * flush the object from the CPU cache.
 456  */
 457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 458                                     int *needs_clflush)
 459 {
 460         int ret;
 461
 462         *needs_clflush = 0;
 463
 464         if (!obj->base.filp)
 465                 return -EINVAL;
 466
 467         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 468                 /* If we're not in the cpu read domain, set ourself into the gtt
 469                  * read domain and manually flush cachelines (if required). This
 470                  * optimizes for the case when the gpu will dirty the data
 471                  * anyway again before the next pread happens. */
 472                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 473                                                         obj->cache_level);
 474                 ret = i915_gem_object_wait_rendering(obj, true);
 475                 if (ret)
 476                         return ret;
 477
 478                 i915_gem_object_retire(obj);
 479         }
 480
 481         ret = i915_gem_object_get_pages(obj);
 482         if (ret)
 483                 return ret;
 484
 485         i915_gem_object_pin_pages(obj);
 486
 487         return ret;
 488 }
 489
 490 /* Per-page copy function for the shmem pread fastpath.
 491  * Flushes invalid cachelines before reading the target if
 492  * needs_clflush is set. */
 493 static int
 494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 495                  char __user *user_data,
 496                  bool page_do_bit17_swizzling, bool needs_clflush)
 497 {
 498         char *vaddr;
 499         int ret;
 500
 501         if (unlikely(page_do_bit17_swizzling))
 502                 return -EINVAL;
 503
 504         vaddr = kmap_atomic(page);
 505         if (needs_clflush)
 506                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 507                                        page_length);
 508         ret = __copy_to_user_inatomic(user_data,
 509                                       vaddr + shmem_page_offset,
 510                                       page_length);
 511         kunmap_atomic(vaddr);
 512
 513         return ret ? -EFAULT : 0;
 514 }
 515
 516 static void
 517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 518                              bool swizzled)
 519 {
 520         if (unlikely(swizzled)) {
 521                 unsigned long start = (unsigned long) addr;
 522                 unsigned long end = (unsigned long) addr + length;
 523
 524                 /* For swizzling simply ensure that we always flush both
 525                  * channels. Lame, but simple and it works. Swizzled
 526                  * pwrite/pread is far from a hotpath - current userspace
 527                  * doesn't use it at all. */
 528                 start = round_down(start, 128);
 529                 end = round_up(end, 128);
 530
 531                 drm_clflush_virt_range((void *)start, end - start);
 532         } else {
 533                 drm_clflush_virt_range(addr, length);
 534         }
 535
 536 }
 537
 538 /* Only difference to the fast-path function is that this can handle bit17
 539  * and uses non-atomic copy and kmap functions. */
 540 static int
 541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         vaddr = kmap(page);
 549         if (needs_clflush)
 550                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 551                                              page_length,
 552                                              page_do_bit17_swizzling);
 553
 554         if (page_do_bit17_swizzling)
 555                 ret = __copy_to_user_swizzled(user_data,
 556                                               vaddr, shmem_page_offset,
 557                                               page_length);
 558         else
 559                 ret = __copy_to_user(user_data,
 560                                      vaddr + shmem_page_offset,
 561                                      page_length);
 562         kunmap(page);
 563
 564         return ret ? - EFAULT : 0;
 565 }
 566
 567 static int
 568 i915_gem_shmem_pread(struct drm_device *dev,
 569                      struct drm_i915_gem_object *obj,
 570                      struct drm_i915_gem_pread *args,
 571                      struct drm_file *file)
 572 {
 573         char __user *user_data;
 574         ssize_t remain;
 575         loff_t offset;
 576         int shmem_page_offset, page_length, ret = 0;
 577         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 578         int prefaulted = 0;
 579         int needs_clflush = 0;
 580         struct sg_page_iter sg_iter;
 581
 582         user_data = to_user_ptr(args->data_ptr);
 583         remain = args->size;
 584
 585         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 586
 587         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 588         if (ret)
 589                 return ret;
 590
 591         offset = args->offset;
 592
 593         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 594                          offset >> PAGE_SHIFT) {
 595                 struct page *page = sg_page_iter_page(&sg_iter);
 596
 597                 if (remain <= 0)
 598                         break;
 599
 600                 /* Operation in this page
 601                  *
 602                  * shmem_page_offset = offset within page in shmem file
 603                  * page_length = bytes to copy for this page
 604                  */
 605                 shmem_page_offset = offset_in_page(offset);
 606                 page_length = remain;
 607                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 608                         page_length = PAGE_SIZE - shmem_page_offset;
 609
 610                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 611                         (page_to_phys(page) & (1 << 17)) != 0;
 612
 613                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 614                                        user_data, page_do_bit17_swizzling,
 615                                        needs_clflush);
 616                 if (ret == 0)
 617                         goto next_page;
 618
 619                 mutex_unlock(&dev->struct_mutex);
 620
 621                 if (likely(!i915.prefault_disable) && !prefaulted) {
 622                         ret = fault_in_multipages_writeable(user_data, remain);
 623                         /* Userspace is tricking us, but we've already clobbered
 624                          * its pages with the prefault and promised to write the
 625                          * data up to the first fault. Hence ignore any errors
 626                          * and just continue. */
 627                         (void)ret;
 628                         prefaulted = 1;
 629                 }
 630
 631                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 632                                        user_data, page_do_bit17_swizzling,
 633                                        needs_clflush);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636
 637                 if (ret)
 638                         goto out;
 639
 640 next_page:
 641                 remain -= page_length;
 642                 user_data += page_length;
 643                 offset += page_length;
 644         }
 645
 646 out:
 647         i915_gem_object_unpin_pages(obj);
 648
 649         return ret;
 650 }
 651
 652 /**
 653  * Reads data from the object referenced by handle.
 654  *
 655  * On error, the contents of *data are undefined.
 656  */
 657 int
 658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 659                      struct drm_file *file)
 660 {
 661         struct drm_i915_gem_pread *args = data;
 662         struct drm_i915_gem_object *obj;
 663         int ret = 0;
 664
 665         if (args->size == 0)
 666                 return 0;
 667
 668         if (!access_ok(VERIFY_WRITE,
 669                        to_user_ptr(args->data_ptr),
 670                        args->size))
 671                 return -EFAULT;
 672
 673         ret = i915_mutex_lock_interruptible(dev);
 674         if (ret)
 675                 return ret;
 676
 677         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 678         if (&obj->base == NULL) {
 679                 ret = -ENOENT;
 680                 goto unlock;
 681         }
 682
 683         /* Bounds check source.  */
 684         if (args->offset > obj->base.size ||
 685             args->size > obj->base.size - args->offset) {
 686                 ret = -EINVAL;
 687                 goto out;
 688         }
 689
 690         /* prime objects have no backing filp to GEM pread/pwrite
 691          * pages from.
 692          */
 693         if (!obj->base.filp) {
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         trace_i915_gem_object_pread(obj, args->offset, args->size);
 699
 700         ret = i915_gem_shmem_pread(dev, obj, args, file);
 701
 702 out:
 703         drm_gem_object_unreference(&obj->base);
 704 unlock:
 705         mutex_unlock(&dev->struct_mutex);
 706         return ret;
 707 }
 708
 709 /* This is the fast write path which cannot handle
 710  * page faults in the source data
 711  */
 712
 713 static inline int
 714 fast_user_write(struct io_mapping *mapping,
 715                 loff_t page_base, int page_offset,
 716                 char __user *user_data,
 717                 int length)
 718 {
 719         void __iomem *vaddr_atomic;
 720         void *vaddr;
 721         unsigned long unwritten;
 722
 723         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 724         /* We can use the cpu mem copy function because this is X86. */
 725         vaddr = (void __force*)vaddr_atomic + page_offset;
 726         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 727                                                       user_data, length);
 728         io_mapping_unmap_atomic(vaddr_atomic);
 729         return unwritten;
 730 }
 731
 732 /**
 733  * This is the fast pwrite path, where we copy the data directly from the
 734  * user into the GTT, uncached.
 735  */
 736 static int
 737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 738                          struct drm_i915_gem_object *obj,
 739                          struct drm_i915_gem_pwrite *args,
 740                          struct drm_file *file)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         ssize_t remain;
 744         loff_t offset, page_base;
 745         char __user *user_data;
 746         int page_offset, page_length, ret;
 747
 748         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 749         if (ret)
 750                 goto out;
 751
 752         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 753         if (ret)
 754                 goto out_unpin;
 755
 756         ret = i915_gem_object_put_fence(obj);
 757         if (ret)
 758                 goto out_unpin;
 759
 760         user_data = to_user_ptr(args->data_ptr);
 761         remain = args->size;
 762
 763         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 764
 765         while (remain > 0) {
 766                 /* Operation in this page
 767                  *
 768                  * page_base = page offset within aperture
 769                  * page_offset = offset within page
 770                  * page_length = bytes to copy for this page
 771                  */
 772                 page_base = offset & PAGE_MASK;
 773                 page_offset = offset_in_page(offset);
 774                 page_length = remain;
 775                 if ((page_offset + remain) > PAGE_SIZE)
 776                         page_length = PAGE_SIZE - page_offset;
 777
 778                 /* If we get a fault while copying data, then (presumably) our
 779                  * source page isn't available.  Return the error and we'll
 780                  * retry in the slow path.
 781                  */
 782                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 783                                     page_offset, user_data, page_length)) {
 784                         ret = -EFAULT;
 785                         goto out_unpin;
 786                 }
 787
 788                 remain -= page_length;
 789                 user_data += page_length;
 790                 offset += page_length;
 791         }
 792
 793 out_unpin:
 794         i915_gem_object_ggtt_unpin(obj);
 795 out:
 796         return ret;
 797 }
 798
 799 /* Per-page copy function for the shmem pwrite fastpath.
 800  * Flushes invalid cachelines before writing to the target if
 801  * needs_clflush_before is set and flushes out any written cachelines after
 802  * writing if needs_clflush is set. */
 803 static int
 804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 805                   char __user *user_data,
 806                   bool page_do_bit17_swizzling,
 807                   bool needs_clflush_before,
 808                   bool needs_clflush_after)
 809 {
 810         char *vaddr;
 811         int ret;
 812
 813         if (unlikely(page_do_bit17_swizzling))
 814                 return -EINVAL;
 815
 816         vaddr = kmap_atomic(page);
 817         if (needs_clflush_before)
 818                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 819                                        page_length);
 820         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 821                                         user_data, page_length);
 822         if (needs_clflush_after)
 823                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 824                                        page_length);
 825         kunmap_atomic(vaddr);
 826
 827         return ret ? -EFAULT : 0;
 828 }
 829
 830 /* Only difference to the fast-path function is that this can handle bit17
 831  * and uses non-atomic copy and kmap functions. */
 832 static int
 833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 834                   char __user *user_data,
 835                   bool page_do_bit17_swizzling,
 836                   bool needs_clflush_before,
 837                   bool needs_clflush_after)
 838 {
 839         char *vaddr;
 840         int ret;
 841
 842         vaddr = kmap(page);
 843         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 844                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 845                                              page_length,
 846                                              page_do_bit17_swizzling);
 847         if (page_do_bit17_swizzling)
 848                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 849                                                 user_data,
 850                                                 page_length);
 851         else
 852                 ret = __copy_from_user(vaddr + shmem_page_offset,
 853                                        user_data,
 854                                        page_length);
 855         if (needs_clflush_after)
 856                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 857                                              page_length,
 858                                              page_do_bit17_swizzling);
 859         kunmap(page);
 860
 861         return ret ? -EFAULT : 0;
 862 }
 863
 864 static int
 865 i915_gem_shmem_pwrite(struct drm_device *dev,
 866                       struct drm_i915_gem_object *obj,
 867                       struct drm_i915_gem_pwrite *args,
 868                       struct drm_file *file)
 869 {
 870         ssize_t remain;
 871         loff_t offset;
 872         char __user *user_data;
 873         int shmem_page_offset, page_length, ret = 0;
 874         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 875         int hit_slowpath = 0;
 876         int needs_clflush_after = 0;
 877         int needs_clflush_before = 0;
 878         struct sg_page_iter sg_iter;
 879
 880         user_data = to_user_ptr(args->data_ptr);
 881         remain = args->size;
 882
 883         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 886                 /* If we're not in the cpu write domain, set ourself into the gtt
 887                  * write domain and manually flush cachelines (if required). This
 888                  * optimizes for the case when the gpu will use the data
 889                  * right away and we therefore have to clflush anyway. */
 890                 needs_clflush_after = cpu_write_needs_clflush(obj);
 891                 ret = i915_gem_object_wait_rendering(obj, false);
 892                 if (ret)
 893                         return ret;
 894
 895                 i915_gem_object_retire(obj);
 896         }
 897         /* Same trick applies to invalidate partially written cachelines read
 898          * before writing. */
 899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 900                 needs_clflush_before =
 901                         !cpu_cache_is_coherent(dev, obj->cache_level);
 902
 903         ret = i915_gem_object_get_pages(obj);
 904         if (ret)
 905                 return ret;
 906
 907         i915_gem_object_pin_pages(obj);
 908
 909         offset = args->offset;
 910         obj->dirty = 1;
 911
 912         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 913                          offset >> PAGE_SHIFT) {
 914                 struct page *page = sg_page_iter_page(&sg_iter);
 915                 int partial_cacheline_write;
 916
 917                 if (remain <= 0)
 918                         break;
 919
 920                 /* Operation in this page
 921                  *
 922                  * shmem_page_offset = offset within page in shmem file
 923                  * page_length = bytes to copy for this page
 924                  */
 925                 shmem_page_offset = offset_in_page(offset);
 926
 927                 page_length = remain;
 928                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 929                         page_length = PAGE_SIZE - shmem_page_offset;
 930
 931                 /* If we don't overwrite a cacheline completely we need to be
 932                  * careful to have up-to-date data by first clflushing. Don't
 933                  * overcomplicate things and flush the entire patch. */
 934                 partial_cacheline_write = needs_clflush_before &&
 935                         ((shmem_page_offset | page_length)
 936                                 & (boot_cpu_data.x86_clflush_size - 1));
 937
 938                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 939                         (page_to_phys(page) & (1 << 17)) != 0;
 940
 941                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 942                                         user_data, page_do_bit17_swizzling,
 943                                         partial_cacheline_write,
 944                                         needs_clflush_after);
 945                 if (ret == 0)
 946                         goto next_page;
 947
 948                 hit_slowpath = 1;
 949                 mutex_unlock(&dev->struct_mutex);
 950                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 951                                         user_data, page_do_bit17_swizzling,
 952                                         partial_cacheline_write,
 953                                         needs_clflush_after);
 954
 955                 mutex_lock(&dev->struct_mutex);
 956
 957                 if (ret)
 958                         goto out;
 959
 960 next_page:
 961                 remain -= page_length;
 962                 user_data += page_length;
 963                 offset += page_length;
 964         }
 965
 966 out:
 967         i915_gem_object_unpin_pages(obj);
 968
 969         if (hit_slowpath) {
 970                 /*
 971                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 972                  * cachelines in-line while writing and the object moved
 973                  * out of the cpu write domain while we've dropped the lock.
 974                  */
 975                 if (!needs_clflush_after &&
 976                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 977                         if (i915_gem_clflush_object(obj, obj->pin_display))
 978                                 i915_gem_chipset_flush(dev);
 979                 }
 980         }
 981
 982         if (needs_clflush_after)
 983                 i915_gem_chipset_flush(dev);
 984
 985         return ret;
 986 }
 987
 988 /**
 989  * Writes data to the object referenced by handle.
 990  *
 991  * On error, the contents of the buffer that were to be modified are undefined.
 992  */
 993 int
 994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 995                       struct drm_file *file)
 996 {
 997         struct drm_i915_gem_pwrite *args = data;
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         if (args->size == 0)
1002                 return 0;
1003
1004         if (!access_ok(VERIFY_READ,
1005                        to_user_ptr(args->data_ptr),
1006                        args->size))
1007                 return -EFAULT;
1008
1009         if (likely(!i915.prefault_disable)) {
1010                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1011                                                    args->size);
1012                 if (ret)
1013                         return -EFAULT;
1014         }
1015
1016         ret = i915_mutex_lock_interruptible(dev);
1017         if (ret)
1018                 return ret;
1019
1020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021         if (&obj->base == NULL) {
1022                 ret = -ENOENT;
1023                 goto unlock;
1024         }
1025
1026         /* Bounds check destination. */
1027         if (args->offset > obj->base.size ||
1028             args->size > obj->base.size - args->offset) {
1029                 ret = -EINVAL;
1030                 goto out;
1031         }
1032
1033         /* prime objects have no backing filp to GEM pread/pwrite
1034          * pages from.
1035          */
1036         if (!obj->base.filp) {
1037                 ret = -EINVAL;
1038                 goto out;
1039         }
1040
1041         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1042
1043         ret = -EFAULT;
1044         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045          * it would end up going through the fenced access, and we'll get
1046          * different detiling behavior between reading and writing.
1047          * pread/pwrite currently are reading and writing from the CPU
1048          * perspective, requiring manual detiling by the client.
1049          */
1050         if (obj->phys_handle) {
1051                 ret = i915_gem_phys_pwrite(obj, args, file);
1052                 goto out;
1053         }
1054
1055         if (obj->tiling_mode == I915_TILING_NONE &&
1056             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057             cpu_write_needs_clflush(obj)) {
1058                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059                 /* Note that the gtt paths might fail with non-page-backed user
1060                  * pointers (e.g. gtt mappings when moving data between
1061                  * textures). Fallback to the shmem path in that case. */
1062         }
1063
1064         if (ret == -EFAULT || ret == -ENOSPC)
1065                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1066
1067 out:
1068         drm_gem_object_unreference(&obj->base);
1069 unlock:
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 int
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1076                      bool interruptible)
1077 {
1078         if (i915_reset_in_progress(error)) {
1079                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080                  * -EIO unconditionally for these. */
1081                 if (!interruptible)
1082                         return -EIO;
1083
1084                 /* Recovery complete, but the reset failed ... */
1085                 if (i915_terminally_wedged(error))
1086                         return -EIO;
1087
1088                 return -EAGAIN;
1089         }
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Compare seqno against outstanding lazy request. Emit a request if they are
1096  * equal.
1097  */
1098 int
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 {
1101         int ret;
1102
1103         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1104
1105         ret = 0;
1106         if (seqno == ring->outstanding_lazy_seqno)
1107                 ret = i915_add_request(ring, NULL);
1108
1109         return ret;
1110 }
1111
1112 static void fake_irq(unsigned long data)
1113 {
1114         wake_up_process((struct task_struct *)data);
1115 }
1116
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118                        struct intel_engine_cs *ring)
1119 {
1120         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1121 }
1122
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1124 {
1125         if (file_priv == NULL)
1126                 return true;
1127
1128         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 }
1130
1131 /**
1132  * __wait_seqno - wait until execution of seqno has finished
1133  * @ring: the ring expected to report seqno
1134  * @seqno: duh!
1135  * @reset_counter: reset sequence associated with the given seqno
1136  * @interruptible: do an interruptible wait (normally yes)
1137  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1138  *
1139  * Note: It is of utmost importance that the passed in seqno and reset_counter
1140  * values have been read by the caller in an smp safe manner. Where read-side
1141  * locks are involved, it is sufficient to read the reset_counter before
1142  * unlocking the lock that protects the seqno. For lockless tricks, the
1143  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1144  * inserted.
1145  *
1146  * Returns 0 if the seqno was found within the alloted time. Else returns the
1147  * errno with remaining time filled in timeout argument.
1148  */
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150                         unsigned reset_counter,
1151                         bool interruptible,
1152                         s64 *timeout,
1153                         struct drm_i915_file_private *file_priv)
1154 {
1155         struct drm_device *dev = ring->dev;
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         const bool irq_test_in_progress =
1158                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1159         DEFINE_WAIT(wait);
1160         unsigned long timeout_expire;
1161         s64 before, now;
1162         int ret;
1163
1164         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1165
1166         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1167                 return 0;
1168
1169         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1170
1171         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1172                 gen6_rps_boost(dev_priv);
1173                 if (file_priv)
1174                         mod_delayed_work(dev_priv->wq,
1175                                          &file_priv->mm.idle_work,
1176                                          msecs_to_jiffies(100));
1177         }
1178
1179         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1180                 return -ENODEV;
1181
1182         /* Record current time in case interrupted by signal, or wedged */
1183         trace_i915_gem_request_wait_begin(ring, seqno);
1184         before = ktime_get_raw_ns();
1185         for (;;) {
1186                 struct timer_list timer;
1187
1188                 prepare_to_wait(&ring->irq_queue, &wait,
1189                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1190
1191                 /* We need to check whether any gpu reset happened in between
1192                  * the caller grabbing the seqno and now ... */
1193                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195                          * is truely gone. */
1196                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1197                         if (ret == 0)
1198                                 ret = -EAGAIN;
1199                         break;
1200                 }
1201
1202                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1203                         ret = 0;
1204                         break;
1205                 }
1206
1207                 if (interruptible && signal_pending(current)) {
1208                         ret = -ERESTARTSYS;
1209                         break;
1210                 }
1211
1212                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1213                         ret = -ETIME;
1214                         break;
1215                 }
1216
1217                 timer.function = NULL;
1218                 if (timeout || missed_irq(dev_priv, ring)) {
1219                         unsigned long expire;
1220
1221                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223                         mod_timer(&timer, expire);
1224                 }
1225
1226                 io_schedule();
1227
1228                 if (timer.function) {
1229                         del_singleshot_timer_sync(&timer);
1230                         destroy_timer_on_stack(&timer);
1231                 }
1232         }
1233         now = ktime_get_raw_ns();
1234         trace_i915_gem_request_wait_end(ring, seqno);
1235
1236         if (!irq_test_in_progress)
1237                 ring->irq_put(ring);
1238
1239         finish_wait(&ring->irq_queue, &wait);
1240
1241         if (timeout) {
1242                 s64 tres = *timeout - (now - before);
1243
1244                 *timeout = tres < 0 ? 0 : tres;
1245         }
1246
1247         return ret;
1248 }
1249
1250 /**
1251  * Waits for a sequence number to be signaled, and cleans up the
1252  * request and object lists appropriately for that event.
1253  */
1254 int
1255 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1256 {
1257         struct drm_device *dev = ring->dev;
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         bool interruptible = dev_priv->mm.interruptible;
1260         int ret;
1261
1262         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1263         BUG_ON(seqno == 0);
1264
1265         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1266         if (ret)
1267                 return ret;
1268
1269         ret = i915_gem_check_olr(ring, seqno);
1270         if (ret)
1271                 return ret;
1272
1273         return __wait_seqno(ring, seqno,
1274                             atomic_read(&dev_priv->gpu_error.reset_counter),
1275                             interruptible, NULL, NULL);
1276 }
1277
1278 static int
1279 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1280                                      struct intel_engine_cs *ring)
1281 {
1282         if (!obj->active)
1283                 return 0;
1284
1285         /* Manually manage the write flush as we may have not yet
1286          * retired the buffer.
1287          *
1288          * Note that the last_write_seqno is always the earlier of
1289          * the two (read/write) seqno, so if we haved successfully waited,
1290          * we know we have passed the last write.
1291          */
1292         obj->last_write_seqno = 0;
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * Ensures that all rendering to the object has completed and the object is
1299  * safe to unbind from the GTT or access from the CPU.
1300  */
1301 static __must_check int
1302 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1303                                bool readonly)
1304 {
1305         struct intel_engine_cs *ring = obj->ring;
1306         u32 seqno;
1307         int ret;
1308
1309         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1310         if (seqno == 0)
1311                 return 0;
1312
1313         ret = i915_wait_seqno(ring, seqno);
1314         if (ret)
1315                 return ret;
1316
1317         return i915_gem_object_wait_rendering__tail(obj, ring);
1318 }
1319
1320 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1321  * as the object state may change during this call.
1322  */
1323 static __must_check int
1324 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1325                                             struct drm_i915_file_private *file_priv,
1326                                             bool readonly)
1327 {
1328         struct drm_device *dev = obj->base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         struct intel_engine_cs *ring = obj->ring;
1331         unsigned reset_counter;
1332         u32 seqno;
1333         int ret;
1334
1335         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1336         BUG_ON(!dev_priv->mm.interruptible);
1337
1338         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1339         if (seqno == 0)
1340                 return 0;
1341
1342         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1343         if (ret)
1344                 return ret;
1345
1346         ret = i915_gem_check_olr(ring, seqno);
1347         if (ret)
1348                 return ret;
1349
1350         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1351         mutex_unlock(&dev->struct_mutex);
1352         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1353         mutex_lock(&dev->struct_mutex);
1354         if (ret)
1355                 return ret;
1356
1357         return i915_gem_object_wait_rendering__tail(obj, ring);
1358 }
1359
1360 /**
1361  * Called when user space prepares to use an object with the CPU, either
1362  * through the mmap ioctl's mapping or a GTT mapping.
1363  */
1364 int
1365 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1366                           struct drm_file *file)
1367 {
1368         struct drm_i915_gem_set_domain *args = data;
1369         struct drm_i915_gem_object *obj;
1370         uint32_t read_domains = args->read_domains;
1371         uint32_t write_domain = args->write_domain;
1372         int ret;
1373
1374         /* Only handle setting domains to types used by the CPU. */
1375         if (write_domain & I915_GEM_GPU_DOMAINS)
1376                 return -EINVAL;
1377
1378         if (read_domains & I915_GEM_GPU_DOMAINS)
1379                 return -EINVAL;
1380
1381         /* Having something in the write domain implies it's in the read
1382          * domain, and only that read domain.  Enforce that in the request.
1383          */
1384         if (write_domain != 0 && read_domains != write_domain)
1385                 return -EINVAL;
1386
1387         ret = i915_mutex_lock_interruptible(dev);
1388         if (ret)
1389                 return ret;
1390
1391         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1392         if (&obj->base == NULL) {
1393                 ret = -ENOENT;
1394                 goto unlock;
1395         }
1396
1397         /* Try to flush the object off the GPU without holding the lock.
1398          * We will repeat the flush holding the lock in the normal manner
1399          * to catch cases where we are gazumped.
1400          */
1401         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1402                                                           file->driver_priv,
1403                                                           !write_domain);
1404         if (ret)
1405                 goto unref;
1406
1407         if (read_domains & I915_GEM_DOMAIN_GTT) {
1408                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1409
1410                 /* Silently promote "you're not bound, there was nothing to do"
1411                  * to success, since the client was just asking us to
1412                  * make sure everything was done.
1413                  */
1414                 if (ret == -EINVAL)
1415                         ret = 0;
1416         } else {
1417                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1418         }
1419
1420 unref:
1421         drm_gem_object_unreference(&obj->base);
1422 unlock:
1423         mutex_unlock(&dev->struct_mutex);
1424         return ret;
1425 }
1426
1427 /**
1428  * Called when user space has done writes to this buffer
1429  */
1430 int
1431 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1432                          struct drm_file *file)
1433 {
1434         struct drm_i915_gem_sw_finish *args = data;
1435         struct drm_i915_gem_object *obj;
1436         int ret = 0;
1437
1438         ret = i915_mutex_lock_interruptible(dev);
1439         if (ret)
1440                 return ret;
1441
1442         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1443         if (&obj->base == NULL) {
1444                 ret = -ENOENT;
1445                 goto unlock;
1446         }
1447
1448         /* Pinned buffers may be scanout, so flush the cache */
1449         if (obj->pin_display)
1450                 i915_gem_object_flush_cpu_write_domain(obj, true);
1451
1452         drm_gem_object_unreference(&obj->base);
1453 unlock:
1454         mutex_unlock(&dev->struct_mutex);
1455         return ret;
1456 }
1457
1458 /**
1459  * Maps the contents of an object, returning the address it is mapped
1460  * into.
1461  *
1462  * While the mapping holds a reference on the contents of the object, it doesn't
1463  * imply a ref on the object itself.
1464  */
1465 int
1466 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1467                     struct drm_file *file)
1468 {
1469         struct drm_i915_gem_mmap *args = data;
1470         struct drm_gem_object *obj;
1471         unsigned long addr;
1472
1473         obj = drm_gem_object_lookup(dev, file, args->handle);
1474         if (obj == NULL)
1475                 return -ENOENT;
1476
1477         /* prime objects have no backing filp to GEM mmap
1478          * pages from.
1479          */
1480         if (!obj->filp) {
1481                 drm_gem_object_unreference_unlocked(obj);
1482                 return -EINVAL;
1483         }
1484
1485         addr = vm_mmap(obj->filp, 0, args->size,
1486                        PROT_READ | PROT_WRITE, MAP_SHARED,
1487                        args->offset);
1488         drm_gem_object_unreference_unlocked(obj);
1489         if (IS_ERR((void *)addr))
1490                 return addr;
1491
1492         args->addr_ptr = (uint64_t) addr;
1493
1494         return 0;
1495 }
1496
1497 /**
1498  * i915_gem_fault - fault a page into the GTT
1499  * vma: VMA in question
1500  * vmf: fault info
1501  *
1502  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1503  * from userspace.  The fault handler takes care of binding the object to
1504  * the GTT (if needed), allocating and programming a fence register (again,
1505  * only if needed based on whether the old reg is still valid or the object
1506  * is tiled) and inserting a new PTE into the faulting process.
1507  *
1508  * Note that the faulting process may involve evicting existing objects
1509  * from the GTT and/or fence registers to make room.  So performance may
1510  * suffer if the GTT working set is large or there are few fence registers
1511  * left.
1512  */
1513 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1514 {
1515         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1516         struct drm_device *dev = obj->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         pgoff_t page_offset;
1519         unsigned long pfn;
1520         int ret = 0;
1521         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1522
1523         intel_runtime_pm_get(dev_priv);
1524
1525         /* We don't use vmf->pgoff since that has the fake offset */
1526         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1527                 PAGE_SHIFT;
1528
1529         ret = i915_mutex_lock_interruptible(dev);
1530         if (ret)
1531                 goto out;
1532
1533         trace_i915_gem_object_fault(obj, page_offset, true, write);
1534
1535         /* Try to flush the object off the GPU first without holding the lock.
1536          * Upon reacquiring the lock, we will perform our sanity checks and then
1537          * repeat the flush holding the lock in the normal manner to catch cases
1538          * where we are gazumped.
1539          */
1540         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1541         if (ret)
1542                 goto unlock;
1543
1544         /* Access to snoopable pages through the GTT is incoherent. */
1545         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1546                 ret = -EFAULT;
1547                 goto unlock;
1548         }
1549
1550         /* Now bind it into the GTT if needed */
1551         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1552         if (ret)
1553                 goto unlock;
1554
1555         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1556         if (ret)
1557                 goto unpin;
1558
1559         ret = i915_gem_object_get_fence(obj);
1560         if (ret)
1561                 goto unpin;
1562
1563         /* Finally, remap it using the new GTT offset */
1564         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1565         pfn >>= PAGE_SHIFT;
1566
1567         if (!obj->fault_mappable) {
1568                 unsigned long size = min_t(unsigned long,
1569                                            vma->vm_end - vma->vm_start,
1570                                            obj->base.size);
1571                 int i;
1572
1573                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1574                         ret = vm_insert_pfn(vma,
1575                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1576                                             pfn + i);
1577                         if (ret)
1578                                 break;
1579                 }
1580
1581                 obj->fault_mappable = true;
1582         } else
1583                 ret = vm_insert_pfn(vma,
1584                                     (unsigned long)vmf->virtual_address,
1585                                     pfn + page_offset);
1586 unpin:
1587         i915_gem_object_ggtt_unpin(obj);
1588 unlock:
1589         mutex_unlock(&dev->struct_mutex);
1590 out:
1591         switch (ret) {
1592         case -EIO:
1593                 /* If this -EIO is due to a gpu hang, give the reset code a
1594                  * chance to clean up the mess. Otherwise return the proper
1595                  * SIGBUS. */
1596                 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1597                         ret = VM_FAULT_SIGBUS;
1598                         break;
1599                 }
1600         case -EAGAIN:
1601                 /*
1602                  * EAGAIN means the gpu is hung and we'll wait for the error
1603                  * handler to reset everything when re-faulting in
1604                  * i915_mutex_lock_interruptible.
1605                  */
1606         case 0:
1607         case -ERESTARTSYS:
1608         case -EINTR:
1609         case -EBUSY:
1610                 /*
1611                  * EBUSY is ok: this just means that another thread
1612                  * already did the job.
1613                  */
1614                 ret = VM_FAULT_NOPAGE;
1615                 break;
1616         case -ENOMEM:
1617                 ret = VM_FAULT_OOM;
1618                 break;
1619         case -ENOSPC:
1620         case -EFAULT:
1621                 ret = VM_FAULT_SIGBUS;
1622                 break;
1623         default:
1624                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1625                 ret = VM_FAULT_SIGBUS;
1626                 break;
1627         }
1628
1629         intel_runtime_pm_put(dev_priv);
1630         return ret;
1631 }
1632
1633 /**
1634  * i915_gem_release_mmap - remove physical page mappings
1635  * @obj: obj in question
1636  *
1637  * Preserve the reservation of the mmapping with the DRM core code, but
1638  * relinquish ownership of the pages back to the system.
1639  *
1640  * It is vital that we remove the page mapping if we have mapped a tiled
1641  * object through the GTT and then lose the fence register due to
1642  * resource pressure. Similarly if the object has been moved out of the
1643  * aperture, than pages mapped into userspace must be revoked. Removing the
1644  * mapping will then trigger a page fault on the next user access, allowing
1645  * fixup by i915_gem_fault().
1646  */
1647 void
1648 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1649 {
1650         if (!obj->fault_mappable)
1651                 return;
1652
1653         drm_vma_node_unmap(&obj->base.vma_node,
1654                            obj->base.dev->anon_inode->i_mapping);
1655         obj->fault_mappable = false;
1656 }
1657
1658 void
1659 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1660 {
1661         struct drm_i915_gem_object *obj;
1662
1663         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1664                 i915_gem_release_mmap(obj);
1665 }
1666
1667 uint32_t
1668 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1669 {
1670         uint32_t gtt_size;
1671
1672         if (INTEL_INFO(dev)->gen >= 4 ||
1673             tiling_mode == I915_TILING_NONE)
1674                 return size;
1675
1676         /* Previous chips need a power-of-two fence region when tiling */
1677         if (INTEL_INFO(dev)->gen == 3)
1678                 gtt_size = 1024*1024;
1679         else
1680                 gtt_size = 512*1024;
1681
1682         while (gtt_size < size)
1683                 gtt_size <<= 1;
1684
1685         return gtt_size;
1686 }
1687
1688 /**
1689  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1690  * @obj: object to check
1691  *
1692  * Return the required GTT alignment for an object, taking into account
1693  * potential fence register mapping.
1694  */
1695 uint32_t
1696 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1697                            int tiling_mode, bool fenced)
1698 {
1699         /*
1700          * Minimum alignment is 4k (GTT page size), but might be greater
1701          * if a fence register is needed for the object.
1702          */
1703         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1704             tiling_mode == I915_TILING_NONE)
1705                 return 4096;
1706
1707         /*
1708          * Previous chips need to be aligned to the size of the smallest
1709          * fence register that can contain the object.
1710          */
1711         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1712 }
1713
1714 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1715 {
1716         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1717         int ret;
1718
1719         if (drm_vma_node_has_offset(&obj->base.vma_node))
1720                 return 0;
1721
1722         dev_priv->mm.shrinker_no_lock_stealing = true;
1723
1724         ret = drm_gem_create_mmap_offset(&obj->base);
1725         if (ret != -ENOSPC)
1726                 goto out;
1727
1728         /* Badly fragmented mmap space? The only way we can recover
1729          * space is by destroying unwanted objects. We can't randomly release
1730          * mmap_offsets as userspace expects them to be persistent for the
1731          * lifetime of the objects. The closest we can is to release the
1732          * offsets on purgeable objects by truncating it and marking it purged,
1733          * which prevents userspace from ever using that object again.
1734          */
1735         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1736         ret = drm_gem_create_mmap_offset(&obj->base);
1737         if (ret != -ENOSPC)
1738                 goto out;
1739
1740         i915_gem_shrink_all(dev_priv);
1741         ret = drm_gem_create_mmap_offset(&obj->base);
1742 out:
1743         dev_priv->mm.shrinker_no_lock_stealing = false;
1744
1745         return ret;
1746 }
1747
1748 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1749 {
1750         drm_gem_free_mmap_offset(&obj->base);
1751 }
1752
1753 int
1754 i915_gem_mmap_gtt(struct drm_file *file,
1755                   struct drm_device *dev,
1756                   uint32_t handle,
1757                   uint64_t *offset)
1758 {
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         struct drm_i915_gem_object *obj;
1761         int ret;
1762
1763         ret = i915_mutex_lock_interruptible(dev);
1764         if (ret)
1765                 return ret;
1766
1767         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1768         if (&obj->base == NULL) {
1769                 ret = -ENOENT;
1770                 goto unlock;
1771         }
1772
1773         if (obj->base.size > dev_priv->gtt.mappable_end) {
1774                 ret = -E2BIG;
1775                 goto out;
1776         }
1777
1778         if (obj->madv != I915_MADV_WILLNEED) {
1779                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1780                 ret = -EFAULT;
1781                 goto out;
1782         }
1783
1784         ret = i915_gem_object_create_mmap_offset(obj);
1785         if (ret)
1786                 goto out;
1787
1788         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1789
1790 out:
1791         drm_gem_object_unreference(&obj->base);
1792 unlock:
1793         mutex_unlock(&dev->struct_mutex);
1794         return ret;
1795 }
1796
1797 /**
1798  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1799  * @dev: DRM device
1800  * @data: GTT mapping ioctl data
1801  * @file: GEM object info
1802  *
1803  * Simply returns the fake offset to userspace so it can mmap it.
1804  * The mmap call will end up in drm_gem_mmap(), which will set things
1805  * up so we can get faults in the handler above.
1806  *
1807  * The fault handler will take care of binding the object into the GTT
1808  * (since it may have been evicted to make room for something), allocating
1809  * a fence register, and mapping the appropriate aperture address into
1810  * userspace.
1811  */
1812 int
1813 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1814                         struct drm_file *file)
1815 {
1816         struct drm_i915_gem_mmap_gtt *args = data;
1817
1818         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1819 }
1820
1821 static inline int
1822 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1823 {
1824         return obj->madv == I915_MADV_DONTNEED;
1825 }
1826
1827 /* Immediately discard the backing storage */
1828 static void
1829 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1830 {
1831         i915_gem_object_free_mmap_offset(obj);
1832
1833         if (obj->base.filp == NULL)
1834                 return;
1835
1836         /* Our goal here is to return as much of the memory as
1837          * is possible back to the system as we are called from OOM.
1838          * To do this we must instruct the shmfs to drop all of its
1839          * backing pages, *now*.
1840          */
1841         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1842         obj->madv = __I915_MADV_PURGED;
1843 }
1844
1845 /* Try to discard unwanted pages */
1846 static void
1847 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1848 {
1849         struct address_space *mapping;
1850
1851         switch (obj->madv) {
1852         case I915_MADV_DONTNEED:
1853                 i915_gem_object_truncate(obj);
1854         case __I915_MADV_PURGED:
1855                 return;
1856         }
1857
1858         if (obj->base.filp == NULL)
1859                 return;
1860
1861         mapping = file_inode(obj->base.filp)->i_mapping,
1862         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1863 }
1864
1865 static void
1866 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1867 {
1868         struct sg_page_iter sg_iter;
1869         int ret;
1870
1871         BUG_ON(obj->madv == __I915_MADV_PURGED);
1872
1873         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1874         if (ret) {
1875                 /* In the event of a disaster, abandon all caches and
1876                  * hope for the best.
1877                  */
1878                 WARN_ON(ret != -EIO);
1879                 i915_gem_clflush_object(obj, true);
1880                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1881         }
1882
1883         if (i915_gem_object_needs_bit17_swizzle(obj))
1884                 i915_gem_object_save_bit_17_swizzle(obj);
1885
1886         if (obj->madv == I915_MADV_DONTNEED)
1887                 obj->dirty = 0;
1888
1889         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1890                 struct page *page = sg_page_iter_page(&sg_iter);
1891
1892                 if (obj->dirty)
1893                         set_page_dirty(page);
1894
1895                 if (obj->madv == I915_MADV_WILLNEED)
1896                         mark_page_accessed(page);
1897
1898                 page_cache_release(page);
1899         }
1900         obj->dirty = 0;
1901
1902         sg_free_table(obj->pages);
1903         kfree(obj->pages);
1904 }
1905
1906 int
1907 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1908 {
1909         const struct drm_i915_gem_object_ops *ops = obj->ops;
1910
1911         if (obj->pages == NULL)
1912                 return 0;
1913
1914         if (obj->pages_pin_count)
1915                 return -EBUSY;
1916
1917         BUG_ON(i915_gem_obj_bound_any(obj));
1918
1919         /* ->put_pages might need to allocate memory for the bit17 swizzle
1920          * array, hence protect them from being reaped by removing them from gtt
1921          * lists early. */
1922         list_del(&obj->global_list);
1923
1924         ops->put_pages(obj);
1925         obj->pages = NULL;
1926
1927         i915_gem_object_invalidate(obj);
1928
1929         return 0;
1930 }
1931
1932 static unsigned long
1933 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1934                   bool purgeable_only)
1935 {
1936         struct list_head still_in_list;
1937         struct drm_i915_gem_object *obj;
1938         unsigned long count = 0;
1939
1940         /*
1941          * As we may completely rewrite the (un)bound list whilst unbinding
1942          * (due to retiring requests) we have to strictly process only
1943          * one element of the list at the time, and recheck the list
1944          * on every iteration.
1945          *
1946          * In particular, we must hold a reference whilst removing the
1947          * object as we may end up waiting for and/or retiring the objects.
1948          * This might release the final reference (held by the active list)
1949          * and result in the object being freed from under us. This is
1950          * similar to the precautions the eviction code must take whilst
1951          * removing objects.
1952          *
1953          * Also note that although these lists do not hold a reference to
1954          * the object we can safely grab one here: The final object
1955          * unreferencing and the bound_list are both protected by the
1956          * dev->struct_mutex and so we won't ever be able to observe an
1957          * object on the bound_list with a reference count equals 0.
1958          */
1959         INIT_LIST_HEAD(&still_in_list);
1960         while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1961                 obj = list_first_entry(&dev_priv->mm.unbound_list,
1962                                        typeof(*obj), global_list);
1963                 list_move_tail(&obj->global_list, &still_in_list);
1964
1965                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1966                         continue;
1967
1968                 drm_gem_object_reference(&obj->base);
1969
1970                 if (i915_gem_object_put_pages(obj) == 0)
1971                         count += obj->base.size >> PAGE_SHIFT;
1972
1973                 drm_gem_object_unreference(&obj->base);
1974         }
1975         list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1976
1977         INIT_LIST_HEAD(&still_in_list);
1978         while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1979                 struct i915_vma *vma, *v;
1980
1981                 obj = list_first_entry(&dev_priv->mm.bound_list,
1982                                        typeof(*obj), global_list);
1983                 list_move_tail(&obj->global_list, &still_in_list);
1984
1985                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1986                         continue;
1987
1988                 drm_gem_object_reference(&obj->base);
1989
1990                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1991                         if (i915_vma_unbind(vma))
1992                                 break;
1993
1994                 if (i915_gem_object_put_pages(obj) == 0)
1995                         count += obj->base.size >> PAGE_SHIFT;
1996
1997                 drm_gem_object_unreference(&obj->base);
1998         }
1999         list_splice(&still_in_list, &dev_priv->mm.bound_list);
2000
2001         return count;
2002 }
2003
2004 static unsigned long
2005 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2006 {
2007         return __i915_gem_shrink(dev_priv, target, true);
2008 }
2009
2010 static unsigned long
2011 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2012 {
2013         i915_gem_evict_everything(dev_priv->dev);
2014         return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2015 }
2016
2017 static int
2018 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2019 {
2020         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2021         int page_count, i;
2022         struct address_space *mapping;
2023         struct sg_table *st;
2024         struct scatterlist *sg;
2025         struct sg_page_iter sg_iter;
2026         struct page *page;
2027         unsigned long last_pfn = 0;     /* suppress gcc warning */
2028         gfp_t gfp;
2029
2030         /* Assert that the object is not currently in any GPU domain. As it
2031          * wasn't in the GTT, there shouldn't be any way it could have been in
2032          * a GPU cache
2033          */
2034         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2035         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2036
2037         st = kmalloc(sizeof(*st), GFP_KERNEL);
2038         if (st == NULL)
2039                 return -ENOMEM;
2040
2041         page_count = obj->base.size / PAGE_SIZE;
2042         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2043                 kfree(st);
2044                 return -ENOMEM;
2045         }
2046
2047         /* Get the list of pages out of our struct file.  They'll be pinned
2048          * at this point until we release them.
2049          *
2050          * Fail silently without starting the shrinker
2051          */
2052         mapping = file_inode(obj->base.filp)->i_mapping;
2053         gfp = mapping_gfp_mask(mapping);
2054         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2055         gfp &= ~(__GFP_IO | __GFP_WAIT);
2056         sg = st->sgl;
2057         st->nents = 0;
2058         for (i = 0; i < page_count; i++) {
2059                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2060                 if (IS_ERR(page)) {
2061                         i915_gem_purge(dev_priv, page_count);
2062                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2063                 }
2064                 if (IS_ERR(page)) {
2065                         /* We've tried hard to allocate the memory by reaping
2066                          * our own buffer, now let the real VM do its job and
2067                          * go down in flames if truly OOM.
2068                          */
2069                         i915_gem_shrink_all(dev_priv);
2070                         page = shmem_read_mapping_page(mapping, i);
2071                         if (IS_ERR(page))
2072                                 goto err_pages;
2073                 }
2074 #ifdef CONFIG_SWIOTLB
2075                 if (swiotlb_nr_tbl()) {
2076                         st->nents++;
2077                         sg_set_page(sg, page, PAGE_SIZE, 0);
2078                         sg = sg_next(sg);
2079                         continue;
2080                 }
2081 #endif
2082                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2083                         if (i)
2084                                 sg = sg_next(sg);
2085                         st->nents++;
2086                         sg_set_page(sg, page, PAGE_SIZE, 0);
2087                 } else {
2088                         sg->length += PAGE_SIZE;
2089                 }
2090                 last_pfn = page_to_pfn(page);
2091
2092                 /* Check that the i965g/gm workaround works. */
2093                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2094         }
2095 #ifdef CONFIG_SWIOTLB
2096         if (!swiotlb_nr_tbl())
2097 #endif
2098                 sg_mark_end(sg);
2099         obj->pages = st;
2100
2101         if (i915_gem_object_needs_bit17_swizzle(obj))
2102                 i915_gem_object_do_bit_17_swizzle(obj);
2103
2104         return 0;
2105
2106 err_pages:
2107         sg_mark_end(sg);
2108         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2109                 page_cache_release(sg_page_iter_page(&sg_iter));
2110         sg_free_table(st);
2111         kfree(st);
2112
2113         /* shmemfs first checks if there is enough memory to allocate the page
2114          * and reports ENOSPC should there be insufficient, along with the usual
2115          * ENOMEM for a genuine allocation failure.
2116          *
2117          * We use ENOSPC in our driver to mean that we have run out of aperture
2118          * space and so want to translate the error from shmemfs back to our
2119          * usual understanding of ENOMEM.
2120          */
2121         if (PTR_ERR(page) == -ENOSPC)
2122                 return -ENOMEM;
2123         else
2124                 return PTR_ERR(page);
2125 }
2126
2127 /* Ensure that the associated pages are gathered from the backing storage
2128  * and pinned into our object. i915_gem_object_get_pages() may be called
2129  * multiple times before they are released by a single call to
2130  * i915_gem_object_put_pages() - once the pages are no longer referenced
2131  * either as a result of memory pressure (reaping pages under the shrinker)
2132  * or as the object is itself released.
2133  */
2134 int
2135 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2136 {
2137         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2138         const struct drm_i915_gem_object_ops *ops = obj->ops;
2139         int ret;
2140
2141         if (obj->pages)
2142                 return 0;
2143
2144         if (obj->madv != I915_MADV_WILLNEED) {
2145                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2146                 return -EFAULT;
2147         }
2148
2149         BUG_ON(obj->pages_pin_count);
2150
2151         ret = ops->get_pages(obj);
2152         if (ret)
2153                 return ret;
2154
2155         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2156         return 0;
2157 }
2158
2159 static void
2160 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2161                                struct intel_engine_cs *ring)
2162 {
2163         struct drm_device *dev = obj->base.dev;
2164         struct drm_i915_private *dev_priv = dev->dev_private;
2165         u32 seqno = intel_ring_get_seqno(ring);
2166
2167         BUG_ON(ring == NULL);
2168         if (obj->ring != ring && obj->last_write_seqno) {
2169                 /* Keep the seqno relative to the current ring */
2170                 obj->last_write_seqno = seqno;
2171         }
2172         obj->ring = ring;
2173
2174         /* Add a reference if we're newly entering the active list. */
2175         if (!obj->active) {
2176                 drm_gem_object_reference(&obj->base);
2177                 obj->active = 1;
2178         }
2179
2180         list_move_tail(&obj->ring_list, &ring->active_list);
2181
2182         obj->last_read_seqno = seqno;
2183
2184         if (obj->fenced_gpu_access) {
2185                 obj->last_fenced_seqno = seqno;
2186
2187                 /* Bump MRU to take account of the delayed flush */
2188                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2189                         struct drm_i915_fence_reg *reg;
2190
2191                         reg = &dev_priv->fence_regs[obj->fence_reg];
2192                         list_move_tail(&reg->lru_list,
2193                                        &dev_priv->mm.fence_list);
2194                 }
2195         }
2196 }
2197
2198 void i915_vma_move_to_active(struct i915_vma *vma,
2199                              struct intel_engine_cs *ring)
2200 {
2201         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2202         return i915_gem_object_move_to_active(vma->obj, ring);
2203 }
2204
2205 static void
2206 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2207 {
2208         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2209         struct i915_address_space *vm;
2210         struct i915_vma *vma;
2211
2212         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2213         BUG_ON(!obj->active);
2214
2215         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2216                 vma = i915_gem_obj_to_vma(obj, vm);
2217                 if (vma && !list_empty(&vma->mm_list))
2218                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2219         }
2220
2221         intel_fb_obj_flush(obj, true);
2222
2223         list_del_init(&obj->ring_list);
2224         obj->ring = NULL;
2225
2226         obj->last_read_seqno = 0;
2227         obj->last_write_seqno = 0;
2228         obj->base.write_domain = 0;
2229
2230         obj->last_fenced_seqno = 0;
2231         obj->fenced_gpu_access = false;
2232
2233         obj->active = 0;
2234         drm_gem_object_unreference(&obj->base);
2235
2236         WARN_ON(i915_verify_lists(dev));
2237 }
2238
2239 static void
2240 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2241 {
2242         struct intel_engine_cs *ring = obj->ring;
2243
2244         if (ring == NULL)
2245                 return;
2246
2247         if (i915_seqno_passed(ring->get_seqno(ring, true),
2248                               obj->last_read_seqno))
2249                 i915_gem_object_move_to_inactive(obj);
2250 }
2251
2252 static int
2253 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2254 {
2255         struct drm_i915_private *dev_priv = dev->dev_private;
2256         struct intel_engine_cs *ring;
2257         int ret, i, j;
2258
2259         /* Carefully retire all requests without writing to the rings */
2260         for_each_ring(ring, dev_priv, i) {
2261                 ret = intel_ring_idle(ring);
2262                 if (ret)
2263                         return ret;
2264         }
2265         i915_gem_retire_requests(dev);
2266
2267         /* Finally reset hw state */
2268         for_each_ring(ring, dev_priv, i) {
2269                 intel_ring_init_seqno(ring, seqno);
2270
2271                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2272                         ring->semaphore.sync_seqno[j] = 0;
2273         }
2274
2275         return 0;
2276 }
2277
2278 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2279 {
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         int ret;
2282
2283         if (seqno == 0)
2284                 return -EINVAL;
2285
2286         /* HWS page needs to be set less than what we
2287          * will inject to ring
2288          */
2289         ret = i915_gem_init_seqno(dev, seqno - 1);
2290         if (ret)
2291                 return ret;
2292
2293         /* Carefully set the last_seqno value so that wrap
2294          * detection still works
2295          */
2296         dev_priv->next_seqno = seqno;
2297         dev_priv->last_seqno = seqno - 1;
2298         if (dev_priv->last_seqno == 0)
2299                 dev_priv->last_seqno--;
2300
2301         return 0;
2302 }
2303
2304 int
2305 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2306 {
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308
2309         /* reserve 0 for non-seqno */
2310         if (dev_priv->next_seqno == 0) {
2311                 int ret = i915_gem_init_seqno(dev, 0);
2312                 if (ret)
2313                         return ret;
2314
2315                 dev_priv->next_seqno = 1;
2316         }
2317
2318         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2319         return 0;
2320 }
2321
2322 int __i915_add_request(struct intel_engine_cs *ring,
2323                        struct drm_file *file,
2324                        struct drm_i915_gem_object *obj,
2325                        u32 *out_seqno)
2326 {
2327         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2328         struct drm_i915_gem_request *request;
2329         u32 request_ring_position, request_start;
2330         int ret;
2331
2332         request_start = intel_ring_get_tail(ring->buffer);
2333         /*
2334          * Emit any outstanding flushes - execbuf can fail to emit the flush
2335          * after having emitted the batchbuffer command. Hence we need to fix
2336          * things up similar to emitting the lazy request. The difference here
2337          * is that the flush _must_ happen before the next request, no matter
2338          * what.
2339          */
2340         ret = intel_ring_flush_all_caches(ring);
2341         if (ret)
2342                 return ret;
2343
2344         request = ring->preallocated_lazy_request;
2345         if (WARN_ON(request == NULL))
2346                 return -ENOMEM;
2347
2348         /* Record the position of the start of the request so that
2349          * should we detect the updated seqno part-way through the
2350          * GPU processing the request, we never over-estimate the
2351          * position of the head.
2352          */
2353         request_ring_position = intel_ring_get_tail(ring->buffer);
2354
2355         ret = ring->add_request(ring);
2356         if (ret)
2357                 return ret;
2358
2359         request->seqno = intel_ring_get_seqno(ring);
2360         request->ring = ring;
2361         request->head = request_start;
2362         request->tail = request_ring_position;
2363
2364         /* Whilst this request exists, batch_obj will be on the
2365          * active_list, and so will hold the active reference. Only when this
2366          * request is retired will the the batch_obj be moved onto the
2367          * inactive_list and lose its active reference. Hence we do not need
2368          * to explicitly hold another reference here.
2369          */
2370         request->batch_obj = obj;
2371
2372         /* Hold a reference to the current context so that we can inspect
2373          * it later in case a hangcheck error event fires.
2374          */
2375         request->ctx = ring->last_context;
2376         if (request->ctx)
2377                 i915_gem_context_reference(request->ctx);
2378
2379         request->emitted_jiffies = jiffies;
2380         list_add_tail(&request->list, &ring->request_list);
2381         request->file_priv = NULL;
2382
2383         if (file) {
2384                 struct drm_i915_file_private *file_priv = file->driver_priv;
2385
2386                 spin_lock(&file_priv->mm.lock);
2387                 request->file_priv = file_priv;
2388                 list_add_tail(&request->client_list,
2389                               &file_priv->mm.request_list);
2390                 spin_unlock(&file_priv->mm.lock);
2391         }
2392
2393         trace_i915_gem_request_add(ring, request->seqno);
2394         ring->outstanding_lazy_seqno = 0;
2395         ring->preallocated_lazy_request = NULL;
2396
2397         if (!dev_priv->ums.mm_suspended) {
2398                 i915_queue_hangcheck(ring->dev);
2399
2400                 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2401                 queue_delayed_work(dev_priv->wq,
2402                                    &dev_priv->mm.retire_work,
2403                                    round_jiffies_up_relative(HZ));
2404                 intel_mark_busy(dev_priv->dev);
2405         }
2406
2407         if (out_seqno)
2408                 *out_seqno = request->seqno;
2409         return 0;
2410 }
2411
2412 static inline void
2413 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2414 {
2415         struct drm_i915_file_private *file_priv = request->file_priv;
2416
2417         if (!file_priv)
2418                 return;
2419
2420         spin_lock(&file_priv->mm.lock);
2421         list_del(&request->client_list);
2422         request->file_priv = NULL;
2423         spin_unlock(&file_priv->mm.lock);
2424 }
2425
2426 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2427                                    const struct intel_context *ctx)
2428 {
2429         unsigned long elapsed;
2430
2431         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2432
2433         if (ctx->hang_stats.banned)
2434                 return true;
2435
2436         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2437                 if (!i915_gem_context_is_default(ctx)) {
2438                         DRM_DEBUG("context hanging too fast, banning!\n");
2439                         return true;
2440                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2441                         if (i915_stop_ring_allow_warn(dev_priv))
2442                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2443                         return true;
2444                 }
2445         }
2446
2447         return false;
2448 }
2449
2450 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2451                                   struct intel_context *ctx,
2452                                   const bool guilty)
2453 {
2454         struct i915_ctx_hang_stats *hs;
2455
2456         if (WARN_ON(!ctx))
2457                 return;
2458
2459         hs = &ctx->hang_stats;
2460
2461         if (guilty) {
2462                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2463                 hs->batch_active++;
2464                 hs->guilty_ts = get_seconds();
2465         } else {
2466                 hs->batch_pending++;
2467         }
2468 }
2469
2470 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2471 {
2472         list_del(&request->list);
2473         i915_gem_request_remove_from_client(request);
2474
2475         if (request->ctx)
2476                 i915_gem_context_unreference(request->ctx);
2477
2478         kfree(request);
2479 }
2480
2481 struct drm_i915_gem_request *
2482 i915_gem_find_active_request(struct intel_engine_cs *ring)
2483 {
2484         struct drm_i915_gem_request *request;
2485         u32 completed_seqno;
2486
2487         completed_seqno = ring->get_seqno(ring, false);
2488
2489         list_for_each_entry(request, &ring->request_list, list) {
2490                 if (i915_seqno_passed(completed_seqno, request->seqno))
2491                         continue;
2492
2493                 return request;
2494         }
2495
2496         return NULL;
2497 }
2498
2499 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2500                                        struct intel_engine_cs *ring)
2501 {
2502         struct drm_i915_gem_request *request;
2503         bool ring_hung;
2504
2505         request = i915_gem_find_active_request(ring);
2506
2507         if (request == NULL)
2508                 return;
2509
2510         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2511
2512         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2513
2514         list_for_each_entry_continue(request, &ring->request_list, list)
2515                 i915_set_reset_status(dev_priv, request->ctx, false);
2516 }
2517
2518 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2519                                         struct intel_engine_cs *ring)
2520 {
2521         while (!list_empty(&ring->active_list)) {
2522                 struct drm_i915_gem_object *obj;
2523
2524                 obj = list_first_entry(&ring->active_list,
2525                                        struct drm_i915_gem_object,
2526                                        ring_list);
2527
2528                 i915_gem_object_move_to_inactive(obj);
2529         }
2530
2531         /*
2532          * We must free the requests after all the corresponding objects have
2533          * been moved off active lists. Which is the same order as the normal
2534          * retire_requests function does. This is important if object hold
2535          * implicit references on things like e.g. ppgtt address spaces through
2536          * the request.
2537          */
2538         while (!list_empty(&ring->request_list)) {
2539                 struct drm_i915_gem_request *request;
2540
2541                 request = list_first_entry(&ring->request_list,
2542                                            struct drm_i915_gem_request,
2543                                            list);
2544
2545                 i915_gem_free_request(request);
2546         }
2547
2548         /* These may not have been flush before the reset, do so now */
2549         kfree(ring->preallocated_lazy_request);
2550         ring->preallocated_lazy_request = NULL;
2551         ring->outstanding_lazy_seqno = 0;
2552 }
2553
2554 void i915_gem_restore_fences(struct drm_device *dev)
2555 {
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         int i;
2558
2559         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2560                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2561
2562                 /*
2563                  * Commit delayed tiling changes if we have an object still
2564                  * attached to the fence, otherwise just clear the fence.
2565                  */
2566                 if (reg->obj) {
2567                         i915_gem_object_update_fence(reg->obj, reg,
2568                                                      reg->obj->tiling_mode);
2569                 } else {
2570                         i915_gem_write_fence(dev, i, NULL);
2571                 }
2572         }
2573 }
2574
2575 void i915_gem_reset(struct drm_device *dev)
2576 {
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         struct intel_engine_cs *ring;
2579         int i;
2580
2581         /*
2582          * Before we free the objects from the requests, we need to inspect
2583          * them for finding the guilty party. As the requests only borrow
2584          * their reference to the objects, the inspection must be done first.
2585          */
2586         for_each_ring(ring, dev_priv, i)
2587                 i915_gem_reset_ring_status(dev_priv, ring);
2588
2589         for_each_ring(ring, dev_priv, i)
2590                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2591
2592         i915_gem_context_reset(dev);
2593
2594         i915_gem_restore_fences(dev);
2595 }
2596
2597 /**
2598  * This function clears the request list as sequence numbers are passed.
2599  */
2600 void
2601 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2602 {
2603         uint32_t seqno;
2604
2605         if (list_empty(&ring->request_list))
2606                 return;
2607
2608         WARN_ON(i915_verify_lists(ring->dev));
2609
2610         seqno = ring->get_seqno(ring, true);
2611
2612         /* Move any buffers on the active list that are no longer referenced
2613          * by the ringbuffer to the flushing/inactive lists as appropriate,
2614          * before we free the context associated with the requests.
2615          */
2616         while (!list_empty(&ring->active_list)) {
2617                 struct drm_i915_gem_object *obj;
2618
2619                 obj = list_first_entry(&ring->active_list,
2620                                       struct drm_i915_gem_object,
2621                                       ring_list);
2622
2623                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2624                         break;
2625
2626                 i915_gem_object_move_to_inactive(obj);
2627         }
2628
2629
2630         while (!list_empty(&ring->request_list)) {
2631                 struct drm_i915_gem_request *request;
2632
2633                 request = list_first_entry(&ring->request_list,
2634                                            struct drm_i915_gem_request,
2635                                            list);
2636
2637                 if (!i915_seqno_passed(seqno, request->seqno))
2638                         break;
2639
2640                 trace_i915_gem_request_retire(ring, request->seqno);
2641                 /* We know the GPU must have read the request to have
2642                  * sent us the seqno + interrupt, so use the position
2643                  * of tail of the request to update the last known position
2644                  * of the GPU head.
2645                  */
2646                 ring->buffer->last_retired_head = request->tail;
2647
2648                 i915_gem_free_request(request);
2649         }
2650
2651         if (unlikely(ring->trace_irq_seqno &&
2652                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2653                 ring->irq_put(ring);
2654                 ring->trace_irq_seqno = 0;
2655         }
2656
2657         WARN_ON(i915_verify_lists(ring->dev));
2658 }
2659
2660 bool
2661 i915_gem_retire_requests(struct drm_device *dev)
2662 {
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_engine_cs *ring;
2665         bool idle = true;
2666         int i;
2667
2668         for_each_ring(ring, dev_priv, i) {
2669                 i915_gem_retire_requests_ring(ring);
2670                 idle &= list_empty(&ring->request_list);
2671         }
2672
2673         if (idle)
2674                 mod_delayed_work(dev_priv->wq,
2675                                    &dev_priv->mm.idle_work,
2676                                    msecs_to_jiffies(100));
2677
2678         return idle;
2679 }
2680
2681 static void
2682 i915_gem_retire_work_handler(struct work_struct *work)
2683 {
2684         struct drm_i915_private *dev_priv =
2685                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2686         struct drm_device *dev = dev_priv->dev;
2687         bool idle;
2688
2689         /* Come back later if the device is busy... */
2690         idle = false;
2691         if (mutex_trylock(&dev->struct_mutex)) {
2692                 idle = i915_gem_retire_requests(dev);
2693                 mutex_unlock(&dev->struct_mutex);
2694         }
2695         if (!idle)
2696                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2697                                    round_jiffies_up_relative(HZ));
2698 }
2699
2700 static void
2701 i915_gem_idle_work_handler(struct work_struct *work)
2702 {
2703         struct drm_i915_private *dev_priv =
2704                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2705
2706         intel_mark_idle(dev_priv->dev);
2707 }
2708
2709 /**
2710  * Ensures that an object will eventually get non-busy by flushing any required
2711  * write domains, emitting any outstanding lazy request and retiring and
2712  * completed requests.
2713  */
2714 static int
2715 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2716 {
2717         int ret;
2718
2719         if (obj->active) {
2720                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2721                 if (ret)
2722                         return ret;
2723
2724                 i915_gem_retire_requests_ring(obj->ring);
2725         }
2726
2727         return 0;
2728 }
2729
2730 /**
2731  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2732  * @DRM_IOCTL_ARGS: standard ioctl arguments
2733  *
2734  * Returns 0 if successful, else an error is returned with the remaining time in
2735  * the timeout parameter.
2736  *  -ETIME: object is still busy after timeout
2737  *  -ERESTARTSYS: signal interrupted the wait
2738  *  -ENONENT: object doesn't exist
2739  * Also possible, but rare:
2740  *  -EAGAIN: GPU wedged
2741  *  -ENOMEM: damn
2742  *  -ENODEV: Internal IRQ fail
2743  *  -E?: The add request failed
2744  *
2745  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2746  * non-zero timeout parameter the wait ioctl will wait for the given number of
2747  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2748  * without holding struct_mutex the object may become re-busied before this
2749  * function completes. A similar but shorter * race condition exists in the busy
2750  * ioctl
2751  */
2752 int
2753 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2754 {
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct drm_i915_gem_wait *args = data;
2757         struct drm_i915_gem_object *obj;
2758         struct intel_engine_cs *ring = NULL;
2759         unsigned reset_counter;
2760         u32 seqno = 0;
2761         int ret = 0;
2762
2763         ret = i915_mutex_lock_interruptible(dev);
2764         if (ret)
2765                 return ret;
2766
2767         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2768         if (&obj->base == NULL) {
2769                 mutex_unlock(&dev->struct_mutex);
2770                 return -ENOENT;
2771         }
2772
2773         /* Need to make sure the object gets inactive eventually. */
2774         ret = i915_gem_object_flush_active(obj);
2775         if (ret)
2776                 goto out;
2777
2778         if (obj->active) {
2779                 seqno = obj->last_read_seqno;
2780                 ring = obj->ring;
2781         }
2782
2783         if (seqno == 0)
2784                  goto out;
2785
2786         /* Do this after OLR check to make sure we make forward progress polling
2787          * on this IOCTL with a timeout <=0 (like busy ioctl)
2788          */
2789         if (args->timeout_ns <= 0) {
2790                 ret = -ETIME;
2791                 goto out;
2792         }
2793
2794         drm_gem_object_unreference(&obj->base);
2795         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2796         mutex_unlock(&dev->struct_mutex);
2797
2798         return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
2799                             file->driver_priv);
2800
2801 out:
2802         drm_gem_object_unreference(&obj->base);
2803         mutex_unlock(&dev->struct_mutex);
2804         return ret;
2805 }
2806
2807 /**
2808  * i915_gem_object_sync - sync an object to a ring.
2809  *
2810  * @obj: object which may be in use on another ring.
2811  * @to: ring we wish to use the object on. May be NULL.
2812  *
2813  * This code is meant to abstract object synchronization with the GPU.
2814  * Calling with NULL implies synchronizing the object with the CPU
2815  * rather than a particular GPU ring.
2816  *
2817  * Returns 0 if successful, else propagates up the lower layer error.
2818  */
2819 int
2820 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2821                      struct intel_engine_cs *to)
2822 {
2823         struct intel_engine_cs *from = obj->ring;
2824         u32 seqno;
2825         int ret, idx;
2826
2827         if (from == NULL || to == from)
2828                 return 0;
2829
2830         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2831                 return i915_gem_object_wait_rendering(obj, false);
2832
2833         idx = intel_ring_sync_index(from, to);
2834
2835         seqno = obj->last_read_seqno;
2836         /* Optimization: Avoid semaphore sync when we are sure we already
2837          * waited for an object with higher seqno */
2838         if (seqno <= from->semaphore.sync_seqno[idx])
2839                 return 0;
2840
2841         ret = i915_gem_check_olr(obj->ring, seqno);
2842         if (ret)
2843                 return ret;
2844
2845         trace_i915_gem_ring_sync_to(from, to, seqno);
2846         ret = to->semaphore.sync_to(to, from, seqno);
2847         if (!ret)
2848                 /* We use last_read_seqno because sync_to()
2849                  * might have just caused seqno wrap under
2850                  * the radar.
2851                  */
2852                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2853
2854         return ret;
2855 }
2856
2857 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2858 {
2859         u32 old_write_domain, old_read_domains;
2860
2861         /* Force a pagefault for domain tracking on next user access */
2862         i915_gem_release_mmap(obj);
2863
2864         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2865                 return;
2866
2867         /* Wait for any direct GTT access to complete */
2868         mb();
2869
2870         old_read_domains = obj->base.read_domains;
2871         old_write_domain = obj->base.write_domain;
2872
2873         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2874         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2875
2876         trace_i915_gem_object_change_domain(obj,
2877                                             old_read_domains,
2878                                             old_write_domain);
2879 }
2880
2881 int i915_vma_unbind(struct i915_vma *vma)
2882 {
2883         struct drm_i915_gem_object *obj = vma->obj;
2884         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2885         int ret;
2886
2887         if (list_empty(&vma->vma_link))
2888                 return 0;
2889
2890         if (!drm_mm_node_allocated(&vma->node)) {
2891                 i915_gem_vma_destroy(vma);
2892                 return 0;
2893         }
2894
2895         if (vma->pin_count)
2896                 return -EBUSY;
2897
2898         BUG_ON(obj->pages == NULL);
2899
2900         ret = i915_gem_object_finish_gpu(obj);
2901         if (ret)
2902                 return ret;
2903         /* Continue on if we fail due to EIO, the GPU is hung so we
2904          * should be safe and we need to cleanup or else we might
2905          * cause memory corruption through use-after-free.
2906          */
2907
2908         if (i915_is_ggtt(vma->vm)) {
2909                 i915_gem_object_finish_gtt(obj);
2910
2911                 /* release the fence reg _after_ flushing */
2912                 ret = i915_gem_object_put_fence(obj);
2913                 if (ret)
2914                         return ret;
2915         }
2916
2917         trace_i915_vma_unbind(vma);
2918
2919         vma->unbind_vma(vma);
2920
2921         list_del_init(&vma->mm_list);
2922         /* Avoid an unnecessary call to unbind on rebind. */
2923         if (i915_is_ggtt(vma->vm))
2924                 obj->map_and_fenceable = true;
2925
2926         drm_mm_remove_node(&vma->node);
2927         i915_gem_vma_destroy(vma);
2928
2929         /* Since the unbound list is global, only move to that list if
2930          * no more VMAs exist. */
2931         if (list_empty(&obj->vma_list)) {
2932                 i915_gem_gtt_finish_object(obj);
2933                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2934         }
2935
2936         /* And finally now the object is completely decoupled from this vma,
2937          * we can drop its hold on the backing storage and allow it to be
2938          * reaped by the shrinker.
2939          */
2940         i915_gem_object_unpin_pages(obj);
2941
2942         return 0;
2943 }
2944
2945 int i915_gpu_idle(struct drm_device *dev)
2946 {
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948         struct intel_engine_cs *ring;
2949         int ret, i;
2950
2951         /* Flush everything onto the inactive list. */
2952         for_each_ring(ring, dev_priv, i) {
2953                 ret = i915_switch_context(ring, ring->default_context);
2954                 if (ret)
2955                         return ret;
2956
2957                 ret = intel_ring_idle(ring);
2958                 if (ret)
2959                         return ret;
2960         }
2961
2962         return 0;
2963 }
2964
2965 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2966                                  struct drm_i915_gem_object *obj)
2967 {
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         int fence_reg;
2970         int fence_pitch_shift;
2971
2972         if (INTEL_INFO(dev)->gen >= 6) {
2973                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2974                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2975         } else {
2976                 fence_reg = FENCE_REG_965_0;
2977                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2978         }
2979
2980         fence_reg += reg * 8;
2981
2982         /* To w/a incoherency with non-atomic 64-bit register updates,
2983          * we split the 64-bit update into two 32-bit writes. In order
2984          * for a partial fence not to be evaluated between writes, we
2985          * precede the update with write to turn off the fence register,
2986          * and only enable the fence as the last step.
2987          *
2988          * For extra levels of paranoia, we make sure each step lands
2989          * before applying the next step.
2990          */
2991         I915_WRITE(fence_reg, 0);
2992         POSTING_READ(fence_reg);
2993
2994         if (obj) {
2995                 u32 size = i915_gem_obj_ggtt_size(obj);
2996                 uint64_t val;
2997
2998                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2999                                  0xfffff000) << 32;
3000                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3001                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3002                 if (obj->tiling_mode == I915_TILING_Y)
3003                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3004                 val |= I965_FENCE_REG_VALID;
3005
3006                 I915_WRITE(fence_reg + 4, val >> 32);
3007                 POSTING_READ(fence_reg + 4);
3008
3009                 I915_WRITE(fence_reg + 0, val);
3010                 POSTING_READ(fence_reg);
3011         } else {
3012                 I915_WRITE(fence_reg + 4, 0);
3013                 POSTING_READ(fence_reg + 4);
3014         }
3015 }
3016
3017 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3018                                  struct drm_i915_gem_object *obj)
3019 {
3020         struct drm_i915_private *dev_priv = dev->dev_private;
3021         u32 val;
3022
3023         if (obj) {
3024                 u32 size = i915_gem_obj_ggtt_size(obj);
3025                 int pitch_val;
3026                 int tile_width;
3027
3028                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3029                      (size & -size) != size ||
3030                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3031                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3032                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3033
3034                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3035                         tile_width = 128;
3036                 else
3037                         tile_width = 512;
3038
3039                 /* Note: pitch better be a power of two tile widths */
3040                 pitch_val = obj->stride / tile_width;
3041                 pitch_val = ffs(pitch_val) - 1;
3042
3043                 val = i915_gem_obj_ggtt_offset(obj);
3044                 if (obj->tiling_mode == I915_TILING_Y)
3045                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3046                 val |= I915_FENCE_SIZE_BITS(size);
3047                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3048                 val |= I830_FENCE_REG_VALID;
3049         } else
3050                 val = 0;
3051
3052         if (reg < 8)
3053                 reg = FENCE_REG_830_0 + reg * 4;
3054         else
3055                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3056
3057         I915_WRITE(reg, val);
3058         POSTING_READ(reg);
3059 }
3060
3061 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3062                                 struct drm_i915_gem_object *obj)
3063 {
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         uint32_t val;
3066
3067         if (obj) {
3068                 u32 size = i915_gem_obj_ggtt_size(obj);
3069                 uint32_t pitch_val;
3070
3071                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3072                      (size & -size) != size ||
3073                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3074                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3075                      i915_gem_obj_ggtt_offset(obj), size);
3076
3077                 pitch_val = obj->stride / 128;
3078                 pitch_val = ffs(pitch_val) - 1;
3079
3080                 val = i915_gem_obj_ggtt_offset(obj);
3081                 if (obj->tiling_mode == I915_TILING_Y)
3082                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3083                 val |= I830_FENCE_SIZE_BITS(size);
3084                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3085                 val |= I830_FENCE_REG_VALID;
3086         } else
3087                 val = 0;
3088
3089         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3090         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3091 }
3092
3093 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3094 {
3095         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3096 }
3097
3098 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3099                                  struct drm_i915_gem_object *obj)
3100 {
3101         struct drm_i915_private *dev_priv = dev->dev_private;
3102
3103         /* Ensure that all CPU reads are completed before installing a fence
3104          * and all writes before removing the fence.
3105          */
3106         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3107                 mb();
3108
3109         WARN(obj && (!obj->stride || !obj->tiling_mode),
3110              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3111              obj->stride, obj->tiling_mode);
3112
3113         switch (INTEL_INFO(dev)->gen) {
3114         case 8:
3115         case 7:
3116         case 6:
3117         case 5:
3118         case 4: i965_write_fence_reg(dev, reg, obj); break;
3119         case 3: i915_write_fence_reg(dev, reg, obj); break;
3120         case 2: i830_write_fence_reg(dev, reg, obj); break;
3121         default: BUG();
3122         }
3123
3124         /* And similarly be paranoid that no direct access to this region
3125          * is reordered to before the fence is installed.
3126          */
3127         if (i915_gem_object_needs_mb(obj))
3128                 mb();
3129 }
3130
3131 static inline int fence_number(struct drm_i915_private *dev_priv,
3132                                struct drm_i915_fence_reg *fence)
3133 {
3134         return fence - dev_priv->fence_regs;
3135 }
3136
3137 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3138                                          struct drm_i915_fence_reg *fence,
3139                                          bool enable)
3140 {
3141         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3142         int reg = fence_number(dev_priv, fence);
3143
3144         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3145
3146         if (enable) {
3147                 obj->fence_reg = reg;
3148                 fence->obj = obj;
3149                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3150         } else {
3151                 obj->fence_reg = I915_FENCE_REG_NONE;
3152                 fence->obj = NULL;
3153                 list_del_init(&fence->lru_list);
3154         }
3155         obj->fence_dirty = false;
3156 }
3157
3158 static int
3159 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3160 {
3161         if (obj->last_fenced_seqno) {
3162                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3163                 if (ret)
3164                         return ret;
3165
3166                 obj->last_fenced_seqno = 0;
3167         }
3168
3169         obj->fenced_gpu_access = false;
3170         return 0;
3171 }
3172
3173 int
3174 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3175 {
3176         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3177         struct drm_i915_fence_reg *fence;
3178         int ret;
3179
3180         ret = i915_gem_object_wait_fence(obj);
3181         if (ret)
3182                 return ret;
3183
3184         if (obj->fence_reg == I915_FENCE_REG_NONE)
3185                 return 0;
3186
3187         fence = &dev_priv->fence_regs[obj->fence_reg];
3188
3189         if (WARN_ON(fence->pin_count))
3190                 return -EBUSY;
3191
3192         i915_gem_object_fence_lost(obj);
3193         i915_gem_object_update_fence(obj, fence, false);
3194
3195         return 0;
3196 }
3197
3198 static struct drm_i915_fence_reg *
3199 i915_find_fence_reg(struct drm_device *dev)
3200 {
3201         struct drm_i915_private *dev_priv = dev->dev_private;
3202         struct drm_i915_fence_reg *reg, *avail;
3203         int i;
3204
3205         /* First try to find a free reg */
3206         avail = NULL;
3207         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3208                 reg = &dev_priv->fence_regs[i];
3209                 if (!reg->obj)
3210                         return reg;
3211
3212                 if (!reg->pin_count)
3213                         avail = reg;
3214         }
3215
3216         if (avail == NULL)
3217                 goto deadlock;
3218
3219         /* None available, try to steal one or wait for a user to finish */
3220         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3221                 if (reg->pin_count)
3222                         continue;
3223
3224                 return reg;
3225         }
3226
3227 deadlock:
3228         /* Wait for completion of pending flips which consume fences */
3229         if (intel_has_pending_fb_unpin(dev))
3230                 return ERR_PTR(-EAGAIN);
3231
3232         return ERR_PTR(-EDEADLK);
3233 }
3234
3235 /**
3236  * i915_gem_object_get_fence - set up fencing for an object
3237  * @obj: object to map through a fence reg
3238  *
3239  * When mapping objects through the GTT, userspace wants to be able to write
3240  * to them without having to worry about swizzling if the object is tiled.
3241  * This function walks the fence regs looking for a free one for @obj,
3242  * stealing one if it can't find any.
3243  *
3244  * It then sets up the reg based on the object's properties: address, pitch
3245  * and tiling format.
3246  *
3247  * For an untiled surface, this removes any existing fence.
3248  */
3249 int
3250 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3251 {
3252         struct drm_device *dev = obj->base.dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         bool enable = obj->tiling_mode != I915_TILING_NONE;
3255         struct drm_i915_fence_reg *reg;
3256         int ret;
3257
3258         /* Have we updated the tiling parameters upon the object and so
3259          * will need to serialise the write to the associated fence register?
3260          */
3261         if (obj->fence_dirty) {
3262                 ret = i915_gem_object_wait_fence(obj);
3263                 if (ret)
3264                         return ret;
3265         }
3266
3267         /* Just update our place in the LRU if our fence is getting reused. */
3268         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3269                 reg = &dev_priv->fence_regs[obj->fence_reg];
3270                 if (!obj->fence_dirty) {
3271                         list_move_tail(&reg->lru_list,
3272                                        &dev_priv->mm.fence_list);
3273                         return 0;
3274                 }
3275         } else if (enable) {
3276                 reg = i915_find_fence_reg(dev);
3277                 if (IS_ERR(reg))
3278                         return PTR_ERR(reg);
3279
3280                 if (reg->obj) {
3281                         struct drm_i915_gem_object *old = reg->obj;
3282
3283                         ret = i915_gem_object_wait_fence(old);
3284                         if (ret)
3285                                 return ret;
3286
3287                         i915_gem_object_fence_lost(old);
3288                 }
3289         } else
3290                 return 0;
3291
3292         i915_gem_object_update_fence(obj, reg, enable);
3293
3294         return 0;
3295 }
3296
3297 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3298                                      struct drm_mm_node *gtt_space,
3299                                      unsigned long cache_level)
3300 {
3301         struct drm_mm_node *other;
3302
3303         /* On non-LLC machines we have to be careful when putting differing
3304          * types of snoopable memory together to avoid the prefetcher
3305          * crossing memory domains and dying.
3306          */
3307         if (HAS_LLC(dev))
3308                 return true;
3309
3310         if (!drm_mm_node_allocated(gtt_space))
3311                 return true;
3312
3313         if (list_empty(&gtt_space->node_list))
3314                 return true;
3315
3316         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3317         if (other->allocated && !other->hole_follows && other->color != cache_level)
3318                 return false;
3319
3320         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3321         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3322                 return false;
3323
3324         return true;
3325 }
3326
3327 static void i915_gem_verify_gtt(struct drm_device *dev)
3328 {
3329 #if WATCH_GTT
3330         struct drm_i915_private *dev_priv = dev->dev_private;
3331         struct drm_i915_gem_object *obj;
3332         int err = 0;
3333
3334         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3335                 if (obj->gtt_space == NULL) {
3336                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3337                         err++;
3338                         continue;
3339                 }
3340
3341                 if (obj->cache_level != obj->gtt_space->color) {
3342                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3343                                i915_gem_obj_ggtt_offset(obj),
3344                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3345                                obj->cache_level,
3346                                obj->gtt_space->color);
3347                         err++;
3348                         continue;
3349                 }
3350
3351                 if (!i915_gem_valid_gtt_space(dev,
3352                                               obj->gtt_space,
3353                                               obj->cache_level)) {
3354                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3355                                i915_gem_obj_ggtt_offset(obj),
3356                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3357                                obj->cache_level);
3358                         err++;
3359                         continue;
3360                 }
3361         }
3362
3363         WARN_ON(err);
3364 #endif
3365 }
3366
3367 /**
3368  * Finds free space in the GTT aperture and binds the object there.
3369  */
3370 static struct i915_vma *
3371 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3372                            struct i915_address_space *vm,
3373                            unsigned alignment,
3374                            uint64_t flags)
3375 {
3376         struct drm_device *dev = obj->base.dev;
3377         struct drm_i915_private *dev_priv = dev->dev_private;
3378         u32 size, fence_size, fence_alignment, unfenced_alignment;
3379         unsigned long start =
3380                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3381         unsigned long end =
3382                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3383         struct i915_vma *vma;
3384         int ret;
3385
3386         fence_size = i915_gem_get_gtt_size(dev,
3387                                            obj->base.size,
3388                                            obj->tiling_mode);
3389         fence_alignment = i915_gem_get_gtt_alignment(dev,
3390                                                      obj->base.size,
3391                                                      obj->tiling_mode, true);
3392         unfenced_alignment =
3393                 i915_gem_get_gtt_alignment(dev,
3394                                            obj->base.size,
3395                                            obj->tiling_mode, false);
3396
3397         if (alignment == 0)
3398                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3399                                                 unfenced_alignment;
3400         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3401                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3402                 return ERR_PTR(-EINVAL);
3403         }
3404
3405         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3406
3407         /* If the object is bigger than the entire aperture, reject it early
3408          * before evicting everything in a vain attempt to find space.
3409          */
3410         if (obj->base.size > end) {
3411                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3412                           obj->base.size,
3413                           flags & PIN_MAPPABLE ? "mappable" : "total",
3414                           end);
3415                 return ERR_PTR(-E2BIG);
3416         }
3417
3418         ret = i915_gem_object_get_pages(obj);
3419         if (ret)
3420                 return ERR_PTR(ret);
3421
3422         i915_gem_object_pin_pages(obj);
3423
3424         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3425         if (IS_ERR(vma))
3426                 goto err_unpin;
3427
3428 search_free:
3429         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3430                                                   size, alignment,
3431                                                   obj->cache_level,
3432                                                   start, end,
3433                                                   DRM_MM_SEARCH_DEFAULT,
3434                                                   DRM_MM_CREATE_DEFAULT);
3435         if (ret) {
3436                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3437                                                obj->cache_level,
3438                                                start, end,
3439                                                flags);
3440                 if (ret == 0)
3441                         goto search_free;
3442
3443                 goto err_free_vma;
3444         }
3445         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3446                                               obj->cache_level))) {
3447                 ret = -EINVAL;
3448                 goto err_remove_node;
3449         }
3450
3451         ret = i915_gem_gtt_prepare_object(obj);
3452         if (ret)
3453                 goto err_remove_node;
3454
3455         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3456         list_add_tail(&vma->mm_list, &vm->inactive_list);
3457
3458         if (i915_is_ggtt(vm)) {
3459                 bool mappable, fenceable;
3460
3461                 fenceable = (vma->node.size == fence_size &&
3462                              (vma->node.start & (fence_alignment - 1)) == 0);
3463
3464                 mappable = (vma->node.start + obj->base.size <=
3465                             dev_priv->gtt.mappable_end);
3466
3467                 obj->map_and_fenceable = mappable && fenceable;
3468         }
3469
3470         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3471
3472         trace_i915_vma_bind(vma, flags);
3473         vma->bind_vma(vma, obj->cache_level,
3474                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3475
3476         i915_gem_verify_gtt(dev);
3477         return vma;
3478
3479 err_remove_node:
3480         drm_mm_remove_node(&vma->node);
3481 err_free_vma:
3482         i915_gem_vma_destroy(vma);
3483         vma = ERR_PTR(ret);
3484 err_unpin:
3485         i915_gem_object_unpin_pages(obj);
3486         return vma;
3487 }
3488
3489 bool
3490 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3491                         bool force)
3492 {
3493         /* If we don't have a page list set up, then we're not pinned
3494          * to GPU, and we can ignore the cache flush because it'll happen
3495          * again at bind time.
3496          */
3497         if (obj->pages == NULL)
3498                 return false;
3499
3500         /*
3501          * Stolen memory is always coherent with the GPU as it is explicitly
3502          * marked as wc by the system, or the system is cache-coherent.
3503          */
3504         if (obj->stolen)
3505                 return false;
3506
3507         /* If the GPU is snooping the contents of the CPU cache,
3508          * we do not need to manually clear the CPU cache lines.  However,
3509          * the caches are only snooped when the render cache is
3510          * flushed/invalidated.  As we always have to emit invalidations
3511          * and flushes when moving into and out of the RENDER domain, correct
3512          * snooping behaviour occurs naturally as the result of our domain
3513          * tracking.
3514          */
3515         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3516                 return false;
3517
3518         trace_i915_gem_object_clflush(obj);
3519         drm_clflush_sg(obj->pages);
3520
3521         return true;
3522 }
3523
3524 /** Flushes the GTT write domain for the object if it's dirty. */
3525 static void
3526 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3527 {
3528         uint32_t old_write_domain;
3529
3530         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3531                 return;
3532
3533         /* No actual flushing is required for the GTT write domain.  Writes
3534          * to it immediately go to main memory as far as we know, so there's
3535          * no chipset flush.  It also doesn't land in render cache.
3536          *
3537          * However, we do have to enforce the order so that all writes through
3538          * the GTT land before any writes to the device, such as updates to
3539          * the GATT itself.
3540          */
3541         wmb();
3542
3543         old_write_domain = obj->base.write_domain;
3544         obj->base.write_domain = 0;
3545
3546         intel_fb_obj_flush(obj, false);
3547
3548         trace_i915_gem_object_change_domain(obj,
3549                                             obj->base.read_domains,
3550                                             old_write_domain);
3551 }
3552
3553 /** Flushes the CPU write domain for the object if it's dirty. */
3554 static void
3555 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3556                                        bool force)
3557 {
3558         uint32_t old_write_domain;
3559
3560         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3561                 return;
3562
3563         if (i915_gem_clflush_object(obj, force))
3564                 i915_gem_chipset_flush(obj->base.dev);
3565
3566         old_write_domain = obj->base.write_domain;
3567         obj->base.write_domain = 0;
3568
3569         intel_fb_obj_flush(obj, false);
3570
3571         trace_i915_gem_object_change_domain(obj,
3572                                             obj->base.read_domains,
3573                                             old_write_domain);
3574 }
3575
3576 /**
3577  * Moves a single object to the GTT read, and possibly write domain.
3578  *
3579  * This function returns when the move is complete, including waiting on
3580  * flushes to occur.
3581  */
3582 int
3583 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3584 {
3585         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3586         uint32_t old_write_domain, old_read_domains;
3587         int ret;
3588
3589         /* Not valid to be called on unbound objects. */
3590         if (!i915_gem_obj_bound_any(obj))
3591                 return -EINVAL;
3592
3593         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3594                 return 0;
3595
3596         ret = i915_gem_object_wait_rendering(obj, !write);
3597         if (ret)
3598                 return ret;
3599
3600         i915_gem_object_retire(obj);
3601         i915_gem_object_flush_cpu_write_domain(obj, false);
3602
3603         /* Serialise direct access to this object with the barriers for
3604          * coherent writes from the GPU, by effectively invalidating the
3605          * GTT domain upon first access.
3606          */
3607         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3608                 mb();
3609
3610         old_write_domain = obj->base.write_domain;
3611         old_read_domains = obj->base.read_domains;
3612
3613         /* It should now be out of any other write domains, and we can update
3614          * the domain values for our changes.
3615          */
3616         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3617         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3618         if (write) {
3619                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3620                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3621                 obj->dirty = 1;
3622         }
3623
3624         if (write)
3625                 intel_fb_obj_invalidate(obj, NULL);
3626
3627         trace_i915_gem_object_change_domain(obj,
3628                                             old_read_domains,
3629                                             old_write_domain);
3630
3631         /* And bump the LRU for this access */
3632         if (i915_gem_object_is_inactive(obj)) {
3633                 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3634                 if (vma)
3635                         list_move_tail(&vma->mm_list,
3636                                        &dev_priv->gtt.base.inactive_list);
3637
3638         }
3639
3640         return 0;
3641 }
3642
3643 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3644                                     enum i915_cache_level cache_level)
3645 {
3646         struct drm_device *dev = obj->base.dev;
3647         struct i915_vma *vma, *next;
3648         int ret;
3649
3650         if (obj->cache_level == cache_level)
3651                 return 0;
3652
3653         if (i915_gem_obj_is_pinned(obj)) {
3654                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3655                 return -EBUSY;
3656         }
3657
3658         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3659                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3660                         ret = i915_vma_unbind(vma);
3661                         if (ret)
3662                                 return ret;
3663                 }
3664         }
3665
3666         if (i915_gem_obj_bound_any(obj)) {
3667                 ret = i915_gem_object_finish_gpu(obj);
3668                 if (ret)
3669                         return ret;
3670
3671                 i915_gem_object_finish_gtt(obj);
3672
3673                 /* Before SandyBridge, you could not use tiling or fence
3674                  * registers with snooped memory, so relinquish any fences
3675                  * currently pointing to our region in the aperture.
3676                  */
3677                 if (INTEL_INFO(dev)->gen < 6) {
3678                         ret = i915_gem_object_put_fence(obj);
3679                         if (ret)
3680                                 return ret;
3681                 }
3682
3683                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3684                         if (drm_mm_node_allocated(&vma->node))
3685                                 vma->bind_vma(vma, cache_level,
3686                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3687         }
3688
3689         list_for_each_entry(vma, &obj->vma_list, vma_link)
3690                 vma->node.color = cache_level;
3691         obj->cache_level = cache_level;
3692
3693         if (cpu_write_needs_clflush(obj)) {
3694                 u32 old_read_domains, old_write_domain;
3695
3696                 /* If we're coming from LLC cached, then we haven't
3697                  * actually been tracking whether the data is in the
3698                  * CPU cache or not, since we only allow one bit set
3699                  * in obj->write_domain and have been skipping the clflushes.
3700                  * Just set it to the CPU cache for now.
3701                  */
3702                 i915_gem_object_retire(obj);
3703                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3704
3705                 old_read_domains = obj->base.read_domains;
3706                 old_write_domain = obj->base.write_domain;
3707
3708                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3709                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3710
3711                 trace_i915_gem_object_change_domain(obj,
3712                                                     old_read_domains,
3713                                                     old_write_domain);
3714         }
3715
3716         i915_gem_verify_gtt(dev);
3717         return 0;
3718 }
3719
3720 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3721                                struct drm_file *file)
3722 {
3723         struct drm_i915_gem_caching *args = data;
3724         struct drm_i915_gem_object *obj;
3725         int ret;
3726
3727         ret = i915_mutex_lock_interruptible(dev);
3728         if (ret)
3729                 return ret;
3730
3731         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3732         if (&obj->base == NULL) {
3733                 ret = -ENOENT;
3734                 goto unlock;
3735         }
3736
3737         switch (obj->cache_level) {
3738         case I915_CACHE_LLC:
3739         case I915_CACHE_L3_LLC:
3740                 args->caching = I915_CACHING_CACHED;
3741                 break;
3742
3743         case I915_CACHE_WT:
3744                 args->caching = I915_CACHING_DISPLAY;
3745                 break;
3746
3747         default:
3748                 args->caching = I915_CACHING_NONE;
3749                 break;
3750         }
3751
3752         drm_gem_object_unreference(&obj->base);
3753 unlock:
3754         mutex_unlock(&dev->struct_mutex);
3755         return ret;
3756 }
3757
3758 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3759                                struct drm_file *file)
3760 {
3761         struct drm_i915_gem_caching *args = data;
3762         struct drm_i915_gem_object *obj;
3763         enum i915_cache_level level;
3764         int ret;
3765
3766         switch (args->caching) {
3767         case I915_CACHING_NONE:
3768                 level = I915_CACHE_NONE;
3769                 break;
3770         case I915_CACHING_CACHED:
3771                 level = I915_CACHE_LLC;
3772                 break;
3773         case I915_CACHING_DISPLAY:
3774                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3775                 break;
3776         default:
3777                 return -EINVAL;
3778         }
3779
3780         ret = i915_mutex_lock_interruptible(dev);
3781         if (ret)
3782                 return ret;
3783
3784         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3785         if (&obj->base == NULL) {
3786                 ret = -ENOENT;
3787                 goto unlock;
3788         }
3789
3790         ret = i915_gem_object_set_cache_level(obj, level);
3791
3792         drm_gem_object_unreference(&obj->base);
3793 unlock:
3794         mutex_unlock(&dev->struct_mutex);
3795         return ret;
3796 }
3797
3798 static bool is_pin_display(struct drm_i915_gem_object *obj)
3799 {
3800         struct i915_vma *vma;
3801
3802         if (list_empty(&obj->vma_list))
3803                 return false;
3804
3805         vma = i915_gem_obj_to_ggtt(obj);
3806         if (!vma)
3807                 return false;
3808
3809         /* There are 3 sources that pin objects:
3810          *   1. The display engine (scanouts, sprites, cursors);
3811          *   2. Reservations for execbuffer;
3812          *   3. The user.
3813          *
3814          * We can ignore reservations as we hold the struct_mutex and
3815          * are only called outside of the reservation path.  The user
3816          * can only increment pin_count once, and so if after
3817          * subtracting the potential reference by the user, any pin_count
3818          * remains, it must be due to another use by the display engine.
3819          */
3820         return vma->pin_count - !!obj->user_pin_count;
3821 }
3822
3823 /*
3824  * Prepare buffer for display plane (scanout, cursors, etc).
3825  * Can be called from an uninterruptible phase (modesetting) and allows
3826  * any flushes to be pipelined (for pageflips).
3827  */
3828 int
3829 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3830                                      u32 alignment,
3831                                      struct intel_engine_cs *pipelined)
3832 {
3833         u32 old_read_domains, old_write_domain;
3834         bool was_pin_display;
3835         int ret;
3836
3837         if (pipelined != obj->ring) {
3838                 ret = i915_gem_object_sync(obj, pipelined);
3839                 if (ret)
3840                         return ret;
3841         }
3842
3843         /* Mark the pin_display early so that we account for the
3844          * display coherency whilst setting up the cache domains.
3845          */
3846         was_pin_display = obj->pin_display;
3847         obj->pin_display = true;
3848
3849         /* The display engine is not coherent with the LLC cache on gen6.  As
3850          * a result, we make sure that the pinning that is about to occur is
3851          * done with uncached PTEs. This is lowest common denominator for all
3852          * chipsets.
3853          *
3854          * However for gen6+, we could do better by using the GFDT bit instead
3855          * of uncaching, which would allow us to flush all the LLC-cached data
3856          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3857          */
3858         ret = i915_gem_object_set_cache_level(obj,
3859                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3860         if (ret)
3861                 goto err_unpin_display;
3862
3863         /* As the user may map the buffer once pinned in the display plane
3864          * (e.g. libkms for the bootup splash), we have to ensure that we
3865          * always use map_and_fenceable for all scanout buffers.
3866          */
3867         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3868         if (ret)
3869                 goto err_unpin_display;
3870
3871         i915_gem_object_flush_cpu_write_domain(obj, true);
3872
3873         old_write_domain = obj->base.write_domain;
3874         old_read_domains = obj->base.read_domains;
3875
3876         /* It should now be out of any other write domains, and we can update
3877          * the domain values for our changes.
3878          */
3879         obj->base.write_domain = 0;
3880         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3881
3882         trace_i915_gem_object_change_domain(obj,
3883                                             old_read_domains,
3884                                             old_write_domain);
3885
3886         return 0;
3887
3888 err_unpin_display:
3889         WARN_ON(was_pin_display != is_pin_display(obj));
3890         obj->pin_display = was_pin_display;
3891         return ret;
3892 }
3893
3894 void
3895 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3896 {
3897         i915_gem_object_ggtt_unpin(obj);
3898         obj->pin_display = is_pin_display(obj);
3899 }
3900
3901 int
3902 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3903 {
3904         int ret;
3905
3906         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3907                 return 0;
3908
3909         ret = i915_gem_object_wait_rendering(obj, false);
3910         if (ret)
3911                 return ret;
3912
3913         /* Ensure that we invalidate the GPU's caches and TLBs. */
3914         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3915         return 0;
3916 }
3917
3918 /**
3919  * Moves a single object to the CPU read, and possibly write domain.
3920  *
3921  * This function returns when the move is complete, including waiting on
3922  * flushes to occur.
3923  */
3924 int
3925 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3926 {
3927         uint32_t old_write_domain, old_read_domains;
3928         int ret;
3929
3930         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3931                 return 0;
3932
3933         ret = i915_gem_object_wait_rendering(obj, !write);
3934         if (ret)
3935                 return ret;
3936
3937         i915_gem_object_retire(obj);
3938         i915_gem_object_flush_gtt_write_domain(obj);
3939
3940         old_write_domain = obj->base.write_domain;
3941         old_read_domains = obj->base.read_domains;
3942
3943         /* Flush the CPU cache if it's still invalid. */
3944         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3945                 i915_gem_clflush_object(obj, false);
3946
3947                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3948         }
3949
3950         /* It should now be out of any other write domains, and we can update
3951          * the domain values for our changes.
3952          */
3953         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3954
3955         /* If we're writing through the CPU, then the GPU read domains will
3956          * need to be invalidated at next use.
3957          */
3958         if (write) {
3959                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3960                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3961         }
3962
3963         if (write)
3964                 intel_fb_obj_invalidate(obj, NULL);
3965
3966         trace_i915_gem_object_change_domain(obj,
3967                                             old_read_domains,
3968                                             old_write_domain);
3969
3970         return 0;
3971 }
3972
3973 /* Throttle our rendering by waiting until the ring has completed our requests
3974  * emitted over 20 msec ago.
3975  *
3976  * Note that if we were to use the current jiffies each time around the loop,
3977  * we wouldn't escape the function with any frames outstanding if the time to
3978  * render a frame was over 20ms.
3979  *
3980  * This should get us reasonable parallelism between CPU and GPU but also
3981  * relatively low latency when blocking on a particular request to finish.
3982  */
3983 static int
3984 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3985 {
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         struct drm_i915_file_private *file_priv = file->driver_priv;
3988         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3989         struct drm_i915_gem_request *request;
3990         struct intel_engine_cs *ring = NULL;
3991         unsigned reset_counter;
3992         u32 seqno = 0;
3993         int ret;
3994
3995         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3996         if (ret)
3997                 return ret;
3998
3999         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4000         if (ret)
4001                 return ret;
4002
4003         spin_lock(&file_priv->mm.lock);
4004         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4005                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4006                         break;
4007
4008                 ring = request->ring;
4009                 seqno = request->seqno;
4010         }
4011         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4012         spin_unlock(&file_priv->mm.lock);
4013
4014         if (seqno == 0)
4015                 return 0;
4016
4017         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4018         if (ret == 0)
4019                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4020
4021         return ret;
4022 }
4023
4024 static bool
4025 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4026 {
4027         struct drm_i915_gem_object *obj = vma->obj;
4028
4029         if (alignment &&
4030             vma->node.start & (alignment - 1))
4031                 return true;
4032
4033         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4034                 return true;
4035
4036         if (flags & PIN_OFFSET_BIAS &&
4037             vma->node.start < (flags & PIN_OFFSET_MASK))
4038                 return true;
4039
4040         return false;
4041 }
4042
4043 int
4044 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4045                     struct i915_address_space *vm,
4046                     uint32_t alignment,
4047                     uint64_t flags)
4048 {
4049         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4050         struct i915_vma *vma;
4051         int ret;
4052
4053         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4054                 return -ENODEV;
4055
4056         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4057                 return -EINVAL;
4058
4059         vma = i915_gem_obj_to_vma(obj, vm);
4060         if (vma) {
4061                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4062                         return -EBUSY;
4063
4064                 if (i915_vma_misplaced(vma, alignment, flags)) {
4065                         WARN(vma->pin_count,
4066                              "bo is already pinned with incorrect alignment:"
4067                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4068                              " obj->map_and_fenceable=%d\n",
4069                              i915_gem_obj_offset(obj, vm), alignment,
4070                              !!(flags & PIN_MAPPABLE),
4071                              obj->map_and_fenceable);
4072                         ret = i915_vma_unbind(vma);
4073                         if (ret)
4074                                 return ret;
4075
4076                         vma = NULL;
4077                 }
4078         }
4079
4080         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4081                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4082                 if (IS_ERR(vma))
4083                         return PTR_ERR(vma);
4084         }
4085
4086         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4087                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4088
4089         vma->pin_count++;
4090         if (flags & PIN_MAPPABLE)
4091                 obj->pin_mappable |= true;
4092
4093         return 0;
4094 }
4095
4096 void
4097 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4098 {
4099         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4100
4101         BUG_ON(!vma);
4102         BUG_ON(vma->pin_count == 0);
4103         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4104
4105         if (--vma->pin_count == 0)
4106                 obj->pin_mappable = false;
4107 }
4108
4109 bool
4110 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4111 {
4112         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4113                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4114                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4115
4116                 WARN_ON(!ggtt_vma ||
4117                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4118                         ggtt_vma->pin_count);
4119                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4120                 return true;
4121         } else
4122                 return false;
4123 }
4124
4125 void
4126 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4127 {
4128         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4129                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4130                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4131                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4132         }
4133 }
4134
4135 int
4136 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4137                    struct drm_file *file)
4138 {
4139         struct drm_i915_gem_pin *args = data;
4140         struct drm_i915_gem_object *obj;
4141         int ret;
4142
4143         if (INTEL_INFO(dev)->gen >= 6)
4144                 return -ENODEV;
4145
4146         ret = i915_mutex_lock_interruptible(dev);
4147         if (ret)
4148                 return ret;
4149
4150         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4151         if (&obj->base == NULL) {
4152                 ret = -ENOENT;
4153                 goto unlock;
4154         }
4155
4156         if (obj->madv != I915_MADV_WILLNEED) {
4157                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4158                 ret = -EFAULT;
4159                 goto out;
4160         }
4161
4162         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4163                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4164                           args->handle);
4165                 ret = -EINVAL;
4166                 goto out;
4167         }
4168
4169         if (obj->user_pin_count == ULONG_MAX) {
4170                 ret = -EBUSY;
4171                 goto out;
4172         }
4173
4174         if (obj->user_pin_count == 0) {
4175                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4176                 if (ret)
4177                         goto out;
4178         }
4179
4180         obj->user_pin_count++;
4181         obj->pin_filp = file;
4182
4183         args->offset = i915_gem_obj_ggtt_offset(obj);
4184 out:
4185         drm_gem_object_unreference(&obj->base);
4186 unlock:
4187         mutex_unlock(&dev->struct_mutex);
4188         return ret;
4189 }
4190
4191 int
4192 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4193                      struct drm_file *file)
4194 {
4195         struct drm_i915_gem_pin *args = data;
4196         struct drm_i915_gem_object *obj;
4197         int ret;
4198
4199         ret = i915_mutex_lock_interruptible(dev);
4200         if (ret)
4201                 return ret;
4202
4203         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4204         if (&obj->base == NULL) {
4205                 ret = -ENOENT;
4206                 goto unlock;
4207         }
4208
4209         if (obj->pin_filp != file) {
4210                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4211                           args->handle);
4212                 ret = -EINVAL;
4213                 goto out;
4214         }
4215         obj->user_pin_count--;
4216         if (obj->user_pin_count == 0) {
4217                 obj->pin_filp = NULL;
4218                 i915_gem_object_ggtt_unpin(obj);
4219         }
4220
4221 out:
4222         drm_gem_object_unreference(&obj->base);
4223 unlock:
4224         mutex_unlock(&dev->struct_mutex);
4225         return ret;
4226 }
4227
4228 int
4229 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4230                     struct drm_file *file)
4231 {
4232         struct drm_i915_gem_busy *args = data;
4233         struct drm_i915_gem_object *obj;
4234         int ret;
4235
4236         ret = i915_mutex_lock_interruptible(dev);
4237         if (ret)
4238                 return ret;
4239
4240         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4241         if (&obj->base == NULL) {
4242                 ret = -ENOENT;
4243                 goto unlock;
4244         }
4245
4246         /* Count all active objects as busy, even if they are currently not used
4247          * by the gpu. Users of this interface expect objects to eventually
4248          * become non-busy without any further actions, therefore emit any
4249          * necessary flushes here.
4250          */
4251         ret = i915_gem_object_flush_active(obj);
4252
4253         args->busy = obj->active;
4254         if (obj->ring) {
4255                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4256                 args->busy |= intel_ring_flag(obj->ring) << 16;
4257         }
4258
4259         drm_gem_object_unreference(&obj->base);
4260 unlock:
4261         mutex_unlock(&dev->struct_mutex);
4262         return ret;
4263 }
4264
4265 int
4266 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4267                         struct drm_file *file_priv)
4268 {
4269         return i915_gem_ring_throttle(dev, file_priv);
4270 }
4271
4272 int
4273 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4274                        struct drm_file *file_priv)
4275 {
4276         struct drm_i915_gem_madvise *args = data;
4277         struct drm_i915_gem_object *obj;
4278         int ret;
4279
4280         switch (args->madv) {
4281         case I915_MADV_DONTNEED:
4282         case I915_MADV_WILLNEED:
4283             break;
4284         default:
4285             return -EINVAL;
4286         }
4287
4288         ret = i915_mutex_lock_interruptible(dev);
4289         if (ret)
4290                 return ret;
4291
4292         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4293         if (&obj->base == NULL) {
4294                 ret = -ENOENT;
4295                 goto unlock;
4296         }
4297
4298         if (i915_gem_obj_is_pinned(obj)) {
4299                 ret = -EINVAL;
4300                 goto out;
4301         }
4302
4303         if (obj->madv != __I915_MADV_PURGED)
4304                 obj->madv = args->madv;
4305
4306         /* if the object is no longer attached, discard its backing storage */
4307         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4308                 i915_gem_object_truncate(obj);
4309
4310         args->retained = obj->madv != __I915_MADV_PURGED;
4311
4312 out:
4313         drm_gem_object_unreference(&obj->base);
4314 unlock:
4315         mutex_unlock(&dev->struct_mutex);
4316         return ret;
4317 }
4318
4319 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4320                           const struct drm_i915_gem_object_ops *ops)
4321 {
4322         INIT_LIST_HEAD(&obj->global_list);
4323         INIT_LIST_HEAD(&obj->ring_list);
4324         INIT_LIST_HEAD(&obj->obj_exec_link);
4325         INIT_LIST_HEAD(&obj->vma_list);
4326
4327         obj->ops = ops;
4328
4329         obj->fence_reg = I915_FENCE_REG_NONE;
4330         obj->madv = I915_MADV_WILLNEED;
4331         /* Avoid an unnecessary call to unbind on the first bind. */
4332         obj->map_and_fenceable = true;
4333
4334         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4335 }
4336
4337 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4338         .get_pages = i915_gem_object_get_pages_gtt,
4339         .put_pages = i915_gem_object_put_pages_gtt,
4340 };
4341
4342 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4343                                                   size_t size)
4344 {
4345         struct drm_i915_gem_object *obj;
4346         struct address_space *mapping;
4347         gfp_t mask;
4348
4349         obj = i915_gem_object_alloc(dev);
4350         if (obj == NULL)
4351                 return NULL;
4352
4353         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4354                 i915_gem_object_free(obj);
4355                 return NULL;
4356         }
4357
4358         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4359         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4360                 /* 965gm cannot relocate objects above 4GiB. */
4361                 mask &= ~__GFP_HIGHMEM;
4362                 mask |= __GFP_DMA32;
4363         }
4364
4365         mapping = file_inode(obj->base.filp)->i_mapping;
4366         mapping_set_gfp_mask(mapping, mask);
4367
4368         i915_gem_object_init(obj, &i915_gem_object_ops);
4369
4370         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4371         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4372
4373         if (HAS_LLC(dev)) {
4374                 /* On some devices, we can have the GPU use the LLC (the CPU
4375                  * cache) for about a 10% performance improvement
4376                  * compared to uncached.  Graphics requests other than
4377                  * display scanout are coherent with the CPU in
4378                  * accessing this cache.  This means in this mode we
4379                  * don't need to clflush on the CPU side, and on the
4380                  * GPU side we only need to flush internal caches to
4381                  * get data visible to the CPU.
4382                  *
4383                  * However, we maintain the display planes as UC, and so
4384                  * need to rebind when first used as such.
4385                  */
4386                 obj->cache_level = I915_CACHE_LLC;
4387         } else
4388                 obj->cache_level = I915_CACHE_NONE;
4389
4390         trace_i915_gem_object_create(obj);
4391
4392         return obj;
4393 }
4394
4395 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4396 {
4397         /* If we are the last user of the backing storage (be it shmemfs
4398          * pages or stolen etc), we know that the pages are going to be
4399          * immediately released. In this case, we can then skip copying
4400          * back the contents from the GPU.
4401          */
4402
4403         if (obj->madv != I915_MADV_WILLNEED)
4404                 return false;
4405
4406         if (obj->base.filp == NULL)
4407                 return true;
4408
4409         /* At first glance, this looks racy, but then again so would be
4410          * userspace racing mmap against close. However, the first external
4411          * reference to the filp can only be obtained through the
4412          * i915_gem_mmap_ioctl() which safeguards us against the user
4413          * acquiring such a reference whilst we are in the middle of
4414          * freeing the object.
4415          */
4416         return atomic_long_read(&obj->base.filp->f_count) == 1;
4417 }
4418
4419 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4420 {
4421         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4422         struct drm_device *dev = obj->base.dev;
4423         struct drm_i915_private *dev_priv = dev->dev_private;
4424         struct i915_vma *vma, *next;
4425
4426         intel_runtime_pm_get(dev_priv);
4427
4428         trace_i915_gem_object_destroy(obj);
4429
4430         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4431                 int ret;
4432
4433                 vma->pin_count = 0;
4434                 ret = i915_vma_unbind(vma);
4435                 if (WARN_ON(ret == -ERESTARTSYS)) {
4436                         bool was_interruptible;
4437
4438                         was_interruptible = dev_priv->mm.interruptible;
4439                         dev_priv->mm.interruptible = false;
4440
4441                         WARN_ON(i915_vma_unbind(vma));
4442
4443                         dev_priv->mm.interruptible = was_interruptible;
4444                 }
4445         }
4446
4447         i915_gem_object_detach_phys(obj);
4448
4449         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4450          * before progressing. */
4451         if (obj->stolen)
4452                 i915_gem_object_unpin_pages(obj);
4453
4454         WARN_ON(obj->frontbuffer_bits);
4455
4456         if (WARN_ON(obj->pages_pin_count))
4457                 obj->pages_pin_count = 0;
4458         if (discard_backing_storage(obj))
4459                 obj->madv = I915_MADV_DONTNEED;
4460         i915_gem_object_put_pages(obj);
4461         i915_gem_object_free_mmap_offset(obj);
4462
4463         BUG_ON(obj->pages);
4464
4465         if (obj->base.import_attach)
4466                 drm_prime_gem_destroy(&obj->base, NULL);
4467
4468         if (obj->ops->release)
4469                 obj->ops->release(obj);
4470
4471         drm_gem_object_release(&obj->base);
4472         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4473
4474         kfree(obj->bit_17);
4475         i915_gem_object_free(obj);
4476
4477         intel_runtime_pm_put(dev_priv);
4478 }
4479
4480 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4481                                      struct i915_address_space *vm)
4482 {
4483         struct i915_vma *vma;
4484         list_for_each_entry(vma, &obj->vma_list, vma_link)
4485                 if (vma->vm == vm)
4486                         return vma;
4487
4488         return NULL;
4489 }
4490
4491 void i915_gem_vma_destroy(struct i915_vma *vma)
4492 {
4493         WARN_ON(vma->node.allocated);
4494
4495         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4496         if (!list_empty(&vma->exec_list))
4497                 return;
4498
4499         list_del(&vma->vma_link);
4500
4501         kfree(vma);
4502 }
4503
4504 static void
4505 i915_gem_stop_ringbuffers(struct drm_device *dev)
4506 {
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_engine_cs *ring;
4509         int i;
4510
4511         for_each_ring(ring, dev_priv, i)
4512                 intel_stop_ring_buffer(ring);
4513 }
4514
4515 int
4516 i915_gem_suspend(struct drm_device *dev)
4517 {
4518         struct drm_i915_private *dev_priv = dev->dev_private;
4519         int ret = 0;
4520
4521         mutex_lock(&dev->struct_mutex);
4522         if (dev_priv->ums.mm_suspended)
4523                 goto err;
4524
4525         ret = i915_gpu_idle(dev);
4526         if (ret)
4527                 goto err;
4528
4529         i915_gem_retire_requests(dev);
4530
4531         /* Under UMS, be paranoid and evict. */
4532         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4533                 i915_gem_evict_everything(dev);
4534
4535         i915_kernel_lost_context(dev);
4536         i915_gem_stop_ringbuffers(dev);
4537
4538         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4539          * We need to replace this with a semaphore, or something.
4540          * And not confound ums.mm_suspended!
4541          */
4542         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4543                                                              DRIVER_MODESET);
4544         mutex_unlock(&dev->struct_mutex);
4545
4546         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4547         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4548         flush_delayed_work(&dev_priv->mm.idle_work);
4549
4550         return 0;
4551
4552 err:
4553         mutex_unlock(&dev->struct_mutex);
4554         return ret;
4555 }
4556
4557 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4558 {
4559         struct drm_device *dev = ring->dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4562         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4563         int i, ret;
4564
4565         if (!HAS_L3_DPF(dev) || !remap_info)
4566                 return 0;
4567
4568         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4569         if (ret)
4570                 return ret;
4571
4572         /*
4573          * Note: We do not worry about the concurrent register cacheline hang
4574          * here because no other code should access these registers other than
4575          * at initialization time.
4576          */
4577         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4578                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4579                 intel_ring_emit(ring, reg_base + i);
4580                 intel_ring_emit(ring, remap_info[i/4]);
4581         }
4582
4583         intel_ring_advance(ring);
4584
4585         return ret;
4586 }
4587
4588 void i915_gem_init_swizzling(struct drm_device *dev)
4589 {
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591
4592         if (INTEL_INFO(dev)->gen < 5 ||
4593             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4594                 return;
4595
4596         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4597                                  DISP_TILE_SURFACE_SWIZZLING);
4598
4599         if (IS_GEN5(dev))
4600                 return;
4601
4602         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4603         if (IS_GEN6(dev))
4604                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4605         else if (IS_GEN7(dev))
4606                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4607         else if (IS_GEN8(dev))
4608                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4609         else
4610                 BUG();
4611 }
4612
4613 static bool
4614 intel_enable_blt(struct drm_device *dev)
4615 {
4616         if (!HAS_BLT(dev))
4617                 return false;
4618
4619         /* The blitter was dysfunctional on early prototypes */
4620         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4621                 DRM_INFO("BLT not supported on this pre-production hardware;"
4622                          " graphics performance will be degraded.\n");
4623                 return false;
4624         }
4625
4626         return true;
4627 }
4628
4629 static int i915_gem_init_rings(struct drm_device *dev)
4630 {
4631         struct drm_i915_private *dev_priv = dev->dev_private;
4632         int ret;
4633
4634         ret = intel_init_render_ring_buffer(dev);
4635         if (ret)
4636                 return ret;
4637
4638         if (HAS_BSD(dev)) {
4639                 ret = intel_init_bsd_ring_buffer(dev);
4640                 if (ret)
4641                         goto cleanup_render_ring;
4642         }
4643
4644         if (intel_enable_blt(dev)) {
4645                 ret = intel_init_blt_ring_buffer(dev);
4646                 if (ret)
4647                         goto cleanup_bsd_ring;
4648         }
4649
4650         if (HAS_VEBOX(dev)) {
4651                 ret = intel_init_vebox_ring_buffer(dev);
4652                 if (ret)
4653                         goto cleanup_blt_ring;
4654         }
4655
4656         if (HAS_BSD2(dev)) {
4657                 ret = intel_init_bsd2_ring_buffer(dev);
4658                 if (ret)
4659                         goto cleanup_vebox_ring;
4660         }
4661
4662         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4663         if (ret)
4664                 goto cleanup_bsd2_ring;
4665
4666         return 0;
4667
4668 cleanup_bsd2_ring:
4669         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4670 cleanup_vebox_ring:
4671         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4672 cleanup_blt_ring:
4673         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4674 cleanup_bsd_ring:
4675         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4676 cleanup_render_ring:
4677         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4678
4679         return ret;
4680 }
4681
4682 int
4683 i915_gem_init_hw(struct drm_device *dev)
4684 {
4685         struct drm_i915_private *dev_priv = dev->dev_private;
4686         int ret, i;
4687
4688         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4689                 return -EIO;
4690
4691         if (dev_priv->ellc_size)
4692                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4693
4694         if (IS_HASWELL(dev))
4695                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4696                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4697
4698         if (HAS_PCH_NOP(dev)) {
4699                 if (IS_IVYBRIDGE(dev)) {
4700                         u32 temp = I915_READ(GEN7_MSG_CTL);
4701                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4702                         I915_WRITE(GEN7_MSG_CTL, temp);
4703                 } else if (INTEL_INFO(dev)->gen >= 7) {
4704                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4705                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4706                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4707                 }
4708         }
4709
4710         i915_gem_init_swizzling(dev);
4711
4712         ret = i915_gem_init_rings(dev);
4713         if (ret)
4714                 return ret;
4715
4716         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4717                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4718
4719         /*
4720          * XXX: Contexts should only be initialized once. Doing a switch to the
4721          * default context switch however is something we'd like to do after
4722          * reset or thaw (the latter may not actually be necessary for HW, but
4723          * goes with our code better). Context switching requires rings (for
4724          * the do_switch), but before enabling PPGTT. So don't move this.
4725          */
4726         ret = i915_gem_context_enable(dev_priv);
4727         if (ret && ret != -EIO) {
4728                 DRM_ERROR("Context enable failed %d\n", ret);
4729                 i915_gem_cleanup_ringbuffer(dev);
4730         }
4731
4732         return ret;
4733 }
4734
4735 int i915_gem_init(struct drm_device *dev)
4736 {
4737         struct drm_i915_private *dev_priv = dev->dev_private;
4738         int ret;
4739
4740         mutex_lock(&dev->struct_mutex);
4741
4742         if (IS_VALLEYVIEW(dev)) {
4743                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4744                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4745                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4746                               VLV_GTLC_ALLOWWAKEACK), 10))
4747                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4748         }
4749
4750         i915_gem_init_userptr(dev);
4751         i915_gem_init_global_gtt(dev);
4752
4753         ret = i915_gem_context_init(dev);
4754         if (ret) {
4755                 mutex_unlock(&dev->struct_mutex);
4756                 return ret;
4757         }
4758
4759         ret = i915_gem_init_hw(dev);
4760         if (ret == -EIO) {
4761                 /* Allow ring initialisation to fail by marking the GPU as
4762                  * wedged. But we only want to do this where the GPU is angry,
4763                  * for all other failure, such as an allocation failure, bail.
4764                  */
4765                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4766                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4767                 ret = 0;
4768         }
4769         mutex_unlock(&dev->struct_mutex);
4770
4771         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4772         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4773                 dev_priv->dri1.allow_batchbuffer = 1;
4774         return ret;
4775 }
4776
4777 void
4778 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4779 {
4780         struct drm_i915_private *dev_priv = dev->dev_private;
4781         struct intel_engine_cs *ring;
4782         int i;
4783
4784         for_each_ring(ring, dev_priv, i)
4785                 intel_cleanup_ring_buffer(ring);
4786 }
4787
4788 int
4789 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4790                        struct drm_file *file_priv)
4791 {
4792         struct drm_i915_private *dev_priv = dev->dev_private;
4793         int ret;
4794
4795         if (drm_core_check_feature(dev, DRIVER_MODESET))
4796                 return 0;
4797
4798         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4799                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4800                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4801         }
4802
4803         mutex_lock(&dev->struct_mutex);
4804         dev_priv->ums.mm_suspended = 0;
4805
4806         ret = i915_gem_init_hw(dev);
4807         if (ret != 0) {
4808                 mutex_unlock(&dev->struct_mutex);
4809                 return ret;
4810         }
4811
4812         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4813
4814         ret = drm_irq_install(dev, dev->pdev->irq);
4815         if (ret)
4816                 goto cleanup_ringbuffer;
4817         mutex_unlock(&dev->struct_mutex);
4818
4819         return 0;
4820
4821 cleanup_ringbuffer:
4822         i915_gem_cleanup_ringbuffer(dev);
4823         dev_priv->ums.mm_suspended = 1;
4824         mutex_unlock(&dev->struct_mutex);
4825
4826         return ret;
4827 }
4828
4829 int
4830 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4831                        struct drm_file *file_priv)
4832 {
4833         if (drm_core_check_feature(dev, DRIVER_MODESET))
4834                 return 0;
4835
4836         mutex_lock(&dev->struct_mutex);
4837         drm_irq_uninstall(dev);
4838         mutex_unlock(&dev->struct_mutex);
4839
4840         return i915_gem_suspend(dev);
4841 }
4842
4843 void
4844 i915_gem_lastclose(struct drm_device *dev)
4845 {
4846         int ret;
4847
4848         if (drm_core_check_feature(dev, DRIVER_MODESET))
4849                 return;
4850
4851         ret = i915_gem_suspend(dev);
4852         if (ret)
4853                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4854 }
4855
4856 static void
4857 init_ring_lists(struct intel_engine_cs *ring)
4858 {
4859         INIT_LIST_HEAD(&ring->active_list);
4860         INIT_LIST_HEAD(&ring->request_list);
4861 }
4862
4863 void i915_init_vm(struct drm_i915_private *dev_priv,
4864                   struct i915_address_space *vm)
4865 {
4866         if (!i915_is_ggtt(vm))
4867                 drm_mm_init(&vm->mm, vm->start, vm->total);
4868         vm->dev = dev_priv->dev;
4869         INIT_LIST_HEAD(&vm->active_list);
4870         INIT_LIST_HEAD(&vm->inactive_list);
4871         INIT_LIST_HEAD(&vm->global_link);
4872         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4873 }
4874
4875 void
4876 i915_gem_load(struct drm_device *dev)
4877 {
4878         struct drm_i915_private *dev_priv = dev->dev_private;
4879         int i;
4880
4881         dev_priv->slab =
4882                 kmem_cache_create("i915_gem_object",
4883                                   sizeof(struct drm_i915_gem_object), 0,
4884                                   SLAB_HWCACHE_ALIGN,
4885                                   NULL);
4886
4887         INIT_LIST_HEAD(&dev_priv->vm_list);
4888         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4889
4890         INIT_LIST_HEAD(&dev_priv->context_list);
4891         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4892         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4893         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4894         for (i = 0; i < I915_NUM_RINGS; i++)
4895                 init_ring_lists(&dev_priv->ring[i]);
4896         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4897                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4898         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4899                           i915_gem_retire_work_handler);
4900         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4901                           i915_gem_idle_work_handler);
4902         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4903
4904         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4905         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4906                 I915_WRITE(MI_ARB_STATE,
4907                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4908         }
4909
4910         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4911
4912         /* Old X drivers will take 0-2 for front, back, depth buffers */
4913         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4914                 dev_priv->fence_reg_start = 3;
4915
4916         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4917                 dev_priv->num_fence_regs = 32;
4918         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4919                 dev_priv->num_fence_regs = 16;
4920         else
4921                 dev_priv->num_fence_regs = 8;
4922
4923         /* Initialize fence registers to zero */
4924         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4925         i915_gem_restore_fences(dev);
4926
4927         i915_gem_detect_bit_6_swizzle(dev);
4928         init_waitqueue_head(&dev_priv->pending_flip_queue);
4929
4930         dev_priv->mm.interruptible = true;
4931
4932         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4933         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4934         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4935         register_shrinker(&dev_priv->mm.shrinker);
4936
4937         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4938         register_oom_notifier(&dev_priv->mm.oom_notifier);
4939
4940         mutex_init(&dev_priv->fb_tracking.lock);
4941 }
4942
4943 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4944 {
4945         struct drm_i915_file_private *file_priv = file->driver_priv;
4946
4947         cancel_delayed_work_sync(&file_priv->mm.idle_work);
4948
4949         /* Clean up our request list when the client is going away, so that
4950          * later retire_requests won't dereference our soon-to-be-gone
4951          * file_priv.
4952          */
4953         spin_lock(&file_priv->mm.lock);
4954         while (!list_empty(&file_priv->mm.request_list)) {
4955                 struct drm_i915_gem_request *request;
4956
4957                 request = list_first_entry(&file_priv->mm.request_list,
4958                                            struct drm_i915_gem_request,
4959                                            client_list);
4960                 list_del(&request->client_list);
4961                 request->file_priv = NULL;
4962         }
4963         spin_unlock(&file_priv->mm.lock);
4964 }
4965
4966 static void
4967 i915_gem_file_idle_work_handler(struct work_struct *work)
4968 {
4969         struct drm_i915_file_private *file_priv =
4970                 container_of(work, typeof(*file_priv), mm.idle_work.work);
4971
4972         atomic_set(&file_priv->rps_wait_boost, false);
4973 }
4974
4975 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4976 {
4977         struct drm_i915_file_private *file_priv;
4978         int ret;
4979
4980         DRM_DEBUG_DRIVER("\n");
4981
4982         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4983         if (!file_priv)
4984                 return -ENOMEM;
4985
4986         file->driver_priv = file_priv;
4987         file_priv->dev_priv = dev->dev_private;
4988         file_priv->file = file;
4989
4990         spin_lock_init(&file_priv->mm.lock);
4991         INIT_LIST_HEAD(&file_priv->mm.request_list);
4992         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4993                           i915_gem_file_idle_work_handler);
4994
4995         ret = i915_gem_context_open(dev, file);
4996         if (ret)
4997                 kfree(file_priv);
4998
4999         return ret;
5000 }
5001
5002 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5003                        struct drm_i915_gem_object *new,
5004                        unsigned frontbuffer_bits)
5005 {
5006         if (old) {
5007                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5008                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5009                 old->frontbuffer_bits &= ~frontbuffer_bits;
5010         }
5011
5012         if (new) {
5013                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5014                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5015                 new->frontbuffer_bits |= frontbuffer_bits;
5016         }
5017 }
5018
5019 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5020 {
5021         if (!mutex_is_locked(mutex))
5022                 return false;
5023
5024 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5025         return mutex->owner == task;
5026 #else
5027         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5028         return false;
5029 #endif
5030 }
5031
5032 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5033 {
5034         if (!mutex_trylock(&dev->struct_mutex)) {
5035                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5036                         return false;
5037
5038                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5039                         return false;
5040
5041                 *unlock = false;
5042         } else
5043                 *unlock = true;
5044
5045         return true;
5046 }
5047
5048 static int num_vma_bound(struct drm_i915_gem_object *obj)
5049 {
5050         struct i915_vma *vma;
5051         int count = 0;
5052
5053         list_for_each_entry(vma, &obj->vma_list, vma_link)
5054                 if (drm_mm_node_allocated(&vma->node))
5055                         count++;
5056
5057         return count;
5058 }
5059
5060 static unsigned long
5061 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5062 {
5063         struct drm_i915_private *dev_priv =
5064                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5065         struct drm_device *dev = dev_priv->dev;
5066         struct drm_i915_gem_object *obj;
5067         unsigned long count;
5068         bool unlock;
5069
5070         if (!i915_gem_shrinker_lock(dev, &unlock))
5071                 return 0;
5072
5073         count = 0;
5074         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5075                 if (obj->pages_pin_count == 0)
5076                         count += obj->base.size >> PAGE_SHIFT;
5077
5078         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5079                 if (!i915_gem_obj_is_pinned(obj) &&
5080                     obj->pages_pin_count == num_vma_bound(obj))
5081                         count += obj->base.size >> PAGE_SHIFT;
5082         }
5083
5084         if (unlock)
5085                 mutex_unlock(&dev->struct_mutex);
5086
5087         return count;
5088 }
5089
5090 /* All the new VM stuff */
5091 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5092                                   struct i915_address_space *vm)
5093 {
5094         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5095         struct i915_vma *vma;
5096
5097         if (!dev_priv->mm.aliasing_ppgtt ||
5098             vm == &dev_priv->mm.aliasing_ppgtt->base)
5099                 vm = &dev_priv->gtt.base;
5100
5101         list_for_each_entry(vma, &o->vma_list, vma_link) {
5102                 if (vma->vm == vm)
5103                         return vma->node.start;
5104
5105         }
5106         WARN(1, "%s vma for this object not found.\n",
5107              i915_is_ggtt(vm) ? "global" : "ppgtt");
5108         return -1;
5109 }
5110
5111 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5112                         struct i915_address_space *vm)
5113 {
5114         struct i915_vma *vma;
5115
5116         list_for_each_entry(vma, &o->vma_list, vma_link)
5117                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5118                         return true;
5119
5120         return false;
5121 }
5122
5123 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5124 {
5125         struct i915_vma *vma;
5126
5127         list_for_each_entry(vma, &o->vma_list, vma_link)
5128                 if (drm_mm_node_allocated(&vma->node))
5129                         return true;
5130
5131         return false;
5132 }
5133
5134 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5135                                 struct i915_address_space *vm)
5136 {
5137         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5138         struct i915_vma *vma;
5139
5140         if (!dev_priv->mm.aliasing_ppgtt ||
5141             vm == &dev_priv->mm.aliasing_ppgtt->base)
5142                 vm = &dev_priv->gtt.base;
5143
5144         BUG_ON(list_empty(&o->vma_list));
5145
5146         list_for_each_entry(vma, &o->vma_list, vma_link)
5147                 if (vma->vm == vm)
5148                         return vma->node.size;
5149
5150         return 0;
5151 }
5152
5153 static unsigned long
5154 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5155 {
5156         struct drm_i915_private *dev_priv =
5157                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5158         struct drm_device *dev = dev_priv->dev;
5159         unsigned long freed;
5160         bool unlock;
5161
5162         if (!i915_gem_shrinker_lock(dev, &unlock))
5163                 return SHRINK_STOP;
5164
5165         freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5166         if (freed < sc->nr_to_scan)
5167                 freed += __i915_gem_shrink(dev_priv,
5168                                            sc->nr_to_scan - freed,
5169                                            false);
5170         if (unlock)
5171                 mutex_unlock(&dev->struct_mutex);
5172
5173         return freed;
5174 }
5175
5176 static int
5177 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5178 {
5179         struct drm_i915_private *dev_priv =
5180                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5181         struct drm_device *dev = dev_priv->dev;
5182         struct drm_i915_gem_object *obj;
5183         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5184         unsigned long pinned, bound, unbound, freed;
5185         bool was_interruptible;
5186         bool unlock;
5187
5188         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5189                 schedule_timeout_killable(1);
5190                 if (fatal_signal_pending(current))
5191                         return NOTIFY_DONE;
5192         }
5193         if (timeout == 0) {
5194                 pr_err("Unable to purge GPU memory due lock contention.\n");
5195                 return NOTIFY_DONE;
5196         }
5197
5198         was_interruptible = dev_priv->mm.interruptible;
5199         dev_priv->mm.interruptible = false;
5200
5201         freed = i915_gem_shrink_all(dev_priv);
5202
5203         dev_priv->mm.interruptible = was_interruptible;
5204
5205         /* Because we may be allocating inside our own driver, we cannot
5206          * assert that there are no objects with pinned pages that are not
5207          * being pointed to by hardware.
5208          */
5209         unbound = bound = pinned = 0;
5210         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5211                 if (!obj->base.filp) /* not backed by a freeable object */
5212                         continue;
5213
5214                 if (obj->pages_pin_count)
5215                         pinned += obj->base.size;
5216                 else
5217                         unbound += obj->base.size;
5218         }
5219         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5220                 if (!obj->base.filp)
5221                         continue;
5222
5223                 if (obj->pages_pin_count)
5224                         pinned += obj->base.size;
5225                 else
5226                         bound += obj->base.size;
5227         }
5228
5229         if (unlock)
5230                 mutex_unlock(&dev->struct_mutex);
5231
5232         pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5233                 freed, pinned);
5234         if (unbound || bound)
5235                 pr_err("%lu and %lu bytes still available in the "
5236                        "bound and unbound GPU page lists.\n",
5237                        bound, unbound);
5238
5239         *(unsigned long *)ptr += freed;
5240         return NOTIFY_DONE;
5241 }
5242
5243 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5244 {
5245         struct i915_vma *vma;
5246
5247         /* This WARN has probably outlived its usefulness (callers already
5248          * WARN if they don't find the GGTT vma they expect). When removing,
5249          * remember to remove the pre-check in is_pin_display() as well */
5250         if (WARN_ON(list_empty(&obj->vma_list)))
5251                 return NULL;
5252
5253         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5254         if (vma->vm != obj_to_ggtt(obj))
5255                 return NULL;
5256
5257         return vma;
5258 }