1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_i915_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay;
118 struct intel_overlay_error_state;
120 struct drm_i915_master_private {
121 drm_local_map_t *sarea;
122 struct _drm_i915_sarea *sarea_priv;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg {
127 struct list_head lru_list;
128 struct drm_i915_gem_object *obj;
129 uint32_t setup_seqno;
132 struct sdvo_device_mapping {
142 struct intel_display_error_state;
144 struct drm_i915_error_state {
153 u32 error; /* gen6+ */
154 u32 bcs_acthd; /* gen6+ blt engine */
159 u32 vcs_acthd; /* gen6+ bsd engine */
171 struct drm_i915_error_object {
175 } *ringbuffer, *batchbuffer[2];
176 struct drm_i915_error_buffer {
189 } *active_bo, *pinned_bo;
190 u32 active_bo_count, pinned_bo_count;
191 struct intel_overlay_error_state *overlay;
192 struct intel_display_error_state *display;
195 struct drm_i915_display_funcs {
196 void (*dpms)(struct drm_crtc *crtc, int mode);
197 bool (*fbc_enabled)(struct drm_device *dev);
198 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
199 void (*disable_fbc)(struct drm_device *dev);
200 int (*get_display_clock_speed)(struct drm_device *dev);
201 int (*get_fifo_size)(struct drm_device *dev, int plane);
202 void (*update_wm)(struct drm_device *dev, int planea_clock,
203 int planeb_clock, int sr_hdisplay, int sr_htotal,
205 /* clock updates for mode set */
207 /* render clock increase/decrease */
208 /* display clock increase/decrease */
209 /* pll clock increase/decrease */
210 /* clock gating init */
213 struct intel_device_info {
223 u8 is_broadwater : 1;
226 u8 has_pipe_cxsr : 1;
228 u8 cursor_needs_physical : 1;
230 u8 overlay_needs_physical : 1;
237 FBC_NO_OUTPUT, /* no outputs enabled to compress */
238 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
239 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
240 FBC_MODE_TOO_LARGE, /* mode too large for compression */
241 FBC_BAD_PLANE, /* fbc not supported on plane */
242 FBC_NOT_TILED, /* buffer not tiled */
243 FBC_MULTIPLE_PIPES, /* more than one pipe active */
247 PCH_IBX, /* Ibexpeak PCH */
248 PCH_CPT, /* Cougarpoint PCH */
251 #define QUIRK_PIPEA_FORCE (1<<0)
255 typedef struct drm_i915_private {
256 struct drm_device *dev;
258 const struct intel_device_info *info;
261 int relative_constants_mode;
266 struct i2c_adapter adapter;
267 struct i2c_adapter *force_bit;
271 struct pci_dev *bridge_dev;
272 struct intel_ring_buffer ring[I915_NUM_RINGS];
275 drm_dma_handle_t *status_page_dmah;
276 dma_addr_t dma_status_page;
278 drm_local_map_t hws_map;
279 struct drm_i915_gem_object *pwrctx;
280 struct drm_i915_gem_object *renderctx;
282 struct resource mch_res;
290 atomic_t irq_received;
293 /* protects the irq masks */
295 /** Cached value of IMR to avoid reads in updating the bitfield */
301 u32 hotplug_supported_mask;
302 struct work_struct hotplug_work;
304 int tex_lru_log_granularity;
305 int allow_batchbuffer;
306 struct mem_block *agp_heap;
307 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
311 /* For hangcheck timer */
312 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
313 struct timer_list hangcheck_timer;
316 uint32_t last_instdone;
317 uint32_t last_instdone1;
319 unsigned long cfb_size;
320 unsigned long cfb_pitch;
321 unsigned long cfb_offset;
328 struct intel_opregion opregion;
331 struct intel_overlay *overlay;
334 int backlight_level; /* restore backlight to this value */
335 struct drm_display_mode *panel_fixed_mode;
336 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
337 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
339 /* Feature bits from the VBIOS */
340 unsigned int int_tv_support:1;
341 unsigned int lvds_dither:1;
342 unsigned int lvds_vbt:1;
343 unsigned int int_crt_support:1;
344 unsigned int lvds_use_ssc:1;
355 struct edp_power_seq pps;
357 bool no_aux_handshake;
359 struct notifier_block lid_notifier;
362 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
363 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
364 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
366 unsigned int fsb_freq, mem_freq, is_ddr3;
368 spinlock_t error_lock;
369 struct drm_i915_error_state *first_error;
370 struct work_struct error_work;
371 struct completion error_completion;
372 struct workqueue_struct *wq;
374 /* Display functions */
375 struct drm_i915_display_funcs display;
377 /* PCH chipset type */
378 enum intel_pch pch_type;
380 unsigned long quirks;
405 u32 saveTRANS_HTOTAL_A;
406 u32 saveTRANS_HBLANK_A;
407 u32 saveTRANS_HSYNC_A;
408 u32 saveTRANS_VTOTAL_A;
409 u32 saveTRANS_VBLANK_A;
410 u32 saveTRANS_VSYNC_A;
418 u32 savePFIT_PGM_RATIOS;
419 u32 saveBLC_HIST_CTL;
421 u32 saveBLC_PWM_CTL2;
422 u32 saveBLC_CPU_PWM_CTL;
423 u32 saveBLC_CPU_PWM_CTL2;
436 u32 saveTRANS_HTOTAL_B;
437 u32 saveTRANS_HBLANK_B;
438 u32 saveTRANS_HSYNC_B;
439 u32 saveTRANS_VTOTAL_B;
440 u32 saveTRANS_VBLANK_B;
441 u32 saveTRANS_VSYNC_B;
455 u32 savePP_ON_DELAYS;
456 u32 savePP_OFF_DELAYS;
464 u32 savePFIT_CONTROL;
465 u32 save_palette_a[256];
466 u32 save_palette_b[256];
467 u32 saveDPFC_CB_BASE;
468 u32 saveFBC_CFB_BASE;
471 u32 saveFBC_CONTROL2;
481 u32 saveCACHE_MODE_0;
482 u32 saveMI_ARB_STATE;
493 uint64_t saveFENCE[16];
504 u32 savePIPEA_GMCH_DATA_M;
505 u32 savePIPEB_GMCH_DATA_M;
506 u32 savePIPEA_GMCH_DATA_N;
507 u32 savePIPEB_GMCH_DATA_N;
508 u32 savePIPEA_DP_LINK_M;
509 u32 savePIPEB_DP_LINK_M;
510 u32 savePIPEA_DP_LINK_N;
511 u32 savePIPEB_DP_LINK_N;
522 u32 savePCH_DREF_CONTROL;
523 u32 saveDISP_ARB_CTL;
524 u32 savePIPEA_DATA_M1;
525 u32 savePIPEA_DATA_N1;
526 u32 savePIPEA_LINK_M1;
527 u32 savePIPEA_LINK_N1;
528 u32 savePIPEB_DATA_M1;
529 u32 savePIPEB_DATA_N1;
530 u32 savePIPEB_LINK_M1;
531 u32 savePIPEB_LINK_N1;
532 u32 saveMCHBAR_RENDER_STANDBY;
535 /** Bridge to intel-gtt-ko */
536 const struct intel_gtt *gtt;
537 /** Memory allocator for GTT stolen memory */
538 struct drm_mm stolen;
539 /** Memory allocator for GTT */
540 struct drm_mm gtt_space;
541 /** List of all objects in gtt_space. Used to restore gtt
542 * mappings on resume */
543 struct list_head gtt_list;
544 /** End of mappable part of GTT */
545 unsigned long gtt_mappable_end;
547 struct io_mapping *gtt_mapping;
550 struct shrinker inactive_shrinker;
553 * List of objects currently involved in rendering.
555 * Includes buffers having the contents of their GPU caches
556 * flushed, not necessarily primitives. last_rendering_seqno
557 * represents when the rendering involved will be completed.
559 * A reference is held on the buffer while on this list.
561 struct list_head active_list;
564 * List of objects which are not in the ringbuffer but which
565 * still have a write_domain which needs to be flushed before
568 * last_rendering_seqno is 0 while an object is in this list.
570 * A reference is held on the buffer while on this list.
572 struct list_head flushing_list;
575 * LRU list of objects which are not in the ringbuffer and
576 * are ready to unbind, but are still in the GTT.
578 * last_rendering_seqno is 0 while an object is in this list.
580 * A reference is not held on the buffer while on this list,
581 * as merely being GTT-bound shouldn't prevent its being
582 * freed, and we'll pull it off the list in the free path.
584 struct list_head inactive_list;
587 * LRU list of objects which are not in the ringbuffer but
588 * are still pinned in the GTT.
590 struct list_head pinned_list;
592 /** LRU list of objects with fence regs on them. */
593 struct list_head fence_list;
596 * List of objects currently pending being freed.
598 * These objects are no longer in use, but due to a signal
599 * we were prevented from freeing them at the appointed time.
601 struct list_head deferred_free_list;
604 * We leave the user IRQ off as much as possible,
605 * but this means that requests will finish and never
606 * be retired once the system goes idle. Set a timer to
607 * fire periodically while the ring is running. When it
608 * fires, go retire requests.
610 struct delayed_work retire_work;
613 * Flag if the X Server, and thus DRM, is not currently in
614 * control of the device.
616 * This is set between LeaveVT and EnterVT. It needs to be
617 * replaced with a semaphore. It also needs to be
618 * transitioned away from for kernel modesetting.
623 * Flag if the hardware appears to be wedged.
625 * This is set when attempts to idle the device timeout.
626 * It prevents command submission from occuring and makes
627 * every pending request fail
631 /** Bit 6 swizzling required for X tiling */
632 uint32_t bit_6_swizzle_x;
633 /** Bit 6 swizzling required for Y tiling */
634 uint32_t bit_6_swizzle_y;
636 /* storage for physical objects */
637 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
639 /* accounting, useful for userland debugging */
641 size_t mappable_gtt_total;
642 size_t object_memory;
645 struct sdvo_device_mapping sdvo_mappings[2];
646 /* indicate whether the LVDS_BORDER should be enabled or not */
647 unsigned int lvds_border_bits;
648 /* Panel fitter placement and size for Ironlake+ */
649 u32 pch_pf_pos, pch_pf_size;
651 struct drm_crtc *plane_to_crtc_mapping[2];
652 struct drm_crtc *pipe_to_crtc_mapping[2];
653 wait_queue_head_t pending_flip_queue;
654 bool flip_pending_is_done;
656 /* Reclocking support */
657 bool render_reclock_avail;
658 bool lvds_downclock_avail;
659 /* indicates the reduced downclock for LVDS*/
661 struct work_struct idle_work;
662 struct timer_list idle_timer;
666 struct child_device_config *child_dev;
667 struct drm_connector *int_lvds_connector;
669 bool mchbar_need_disable;
678 unsigned long last_time1;
680 struct timespec last_time2;
681 unsigned long gfx_power;
685 spinlock_t *mchdev_lock;
687 enum no_fbc_reason no_fbc_reason;
689 struct drm_mm_node *compressed_fb;
690 struct drm_mm_node *compressed_llb;
692 unsigned long last_gpu_reset;
694 /* list of fbdev register on this device */
695 struct intel_fbdev *fbdev;
696 } drm_i915_private_t;
698 struct drm_i915_gem_object {
699 struct drm_gem_object base;
701 /** Current space allocated to this object in the GTT, if any. */
702 struct drm_mm_node *gtt_space;
703 struct list_head gtt_list;
705 /** This object's place on the active/flushing/inactive lists */
706 struct list_head ring_list;
707 struct list_head mm_list;
708 /** This object's place on GPU write list */
709 struct list_head gpu_write_list;
710 /** This object's place in the batchbuffer or on the eviction list */
711 struct list_head exec_list;
714 * This is set if the object is on the active or flushing lists
715 * (has pending rendering), and is not set if it's on inactive (ready
718 unsigned int active : 1;
721 * This is set if the object has been written to since last bound
724 unsigned int dirty : 1;
727 * This is set if the object has been written to since the last
730 unsigned int pending_gpu_write : 1;
733 * Fence register bits (if any) for this object. Will be set
734 * as needed when mapped into the GTT.
735 * Protected by dev->struct_mutex.
737 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
739 signed int fence_reg : 5;
742 * Advice: are the backing pages purgeable?
744 unsigned int madv : 2;
747 * Current tiling mode for the object.
749 unsigned int tiling_mode : 2;
750 unsigned int tiling_changed : 1;
752 /** How many users have pinned this object in GTT space. The following
753 * users can each hold at most one reference: pwrite/pread, pin_ioctl
754 * (via user_pin_count), execbuffer (objects are not allowed multiple
755 * times for the same batchbuffer), and the framebuffer code. When
756 * switching/pageflipping, the framebuffer code has at most two buffers
759 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
760 * bits with absolutely no headroom. So use 4 bits. */
761 unsigned int pin_count : 4;
762 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
765 * Is the object at the current location in the gtt mappable and
766 * fenceable? Used to avoid costly recalculations.
768 unsigned int map_and_fenceable : 1;
771 * Whether the current gtt mapping needs to be mappable (and isn't just
772 * mappable by accident). Track pin and fault separate for a more
773 * accurate mappable working set.
775 unsigned int fault_mappable : 1;
776 unsigned int pin_mappable : 1;
779 * Is the GPU currently using a fence to access this buffer,
781 unsigned int pending_fenced_gpu_access:1;
782 unsigned int fenced_gpu_access:1;
789 struct scatterlist *sg_list;
793 * Used for performing relocations during execbuffer insertion.
795 struct hlist_node exec_node;
796 unsigned long exec_handle;
799 * Current offset of the object in GTT space.
801 * This is the same as gtt_space->start
805 /** Breadcrumb of last rendering to the buffer. */
806 uint32_t last_rendering_seqno;
807 struct intel_ring_buffer *ring;
809 /** Breadcrumb of last fenced GPU access to the buffer. */
810 uint32_t last_fenced_seqno;
811 struct intel_ring_buffer *last_fenced_ring;
813 /** Current tiling stride for the object, if it's tiled. */
816 /** Record of address bit 17 of each page at last unbind. */
817 unsigned long *bit_17;
819 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
823 * If present, while GEM_DOMAIN_CPU is in the read domain this array
824 * flags which individual pages are valid.
826 uint8_t *page_cpu_valid;
828 /** User space pin count and filp owning the pin */
829 uint32_t user_pin_count;
830 struct drm_file *pin_filp;
832 /** for phy allocated objects */
833 struct drm_i915_gem_phys_object *phys_obj;
836 * Number of crtcs where this object is currently the fb, but
837 * will be page flipped away on the next vblank. When it
838 * reaches 0, dev_priv->pending_flip_queue will be woken up.
840 atomic_t pending_flip;
843 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
846 * Request queue structure.
848 * The request queue allows us to note sequence numbers that have been emitted
849 * and may be associated with active buffers to be retired.
851 * By keeping this list, we can avoid having to do questionable
852 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
853 * an emission time with seqnos for tracking how far ahead of the GPU we are.
855 struct drm_i915_gem_request {
856 /** On Which ring this request was generated */
857 struct intel_ring_buffer *ring;
859 /** GEM sequence number associated with this request. */
862 /** Time at which this request was emitted, in jiffies. */
863 unsigned long emitted_jiffies;
865 /** global list entry for this request */
866 struct list_head list;
868 struct drm_i915_file_private *file_priv;
869 /** file_priv list entry for this request */
870 struct list_head client_list;
873 struct drm_i915_file_private {
875 struct spinlock lock;
876 struct list_head request_list;
880 enum intel_chip_family {
887 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
889 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
890 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
891 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
892 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
893 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
894 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
895 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
896 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
897 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
898 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
899 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
900 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
901 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
902 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
903 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
904 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
905 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
906 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
907 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
909 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
910 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
911 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
912 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
913 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
915 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
916 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
917 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
919 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
920 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
922 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
923 * rows, which changed the alignment requirements and fence programming.
925 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
927 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
928 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
929 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
930 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
931 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
932 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
933 /* dsparb controlled by hw only */
934 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
936 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
937 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
938 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
940 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
941 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
943 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
944 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
945 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
947 #include "i915_trace.h"
949 extern struct drm_ioctl_desc i915_ioctls[];
950 extern int i915_max_ioctl;
951 extern unsigned int i915_fbpercrtc;
952 extern unsigned int i915_powersave;
953 extern unsigned int i915_lvds_downclock;
955 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
956 extern int i915_resume(struct drm_device *dev);
957 extern void i915_save_display(struct drm_device *dev);
958 extern void i915_restore_display(struct drm_device *dev);
959 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
960 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
963 extern void i915_kernel_lost_context(struct drm_device * dev);
964 extern int i915_driver_load(struct drm_device *, unsigned long flags);
965 extern int i915_driver_unload(struct drm_device *);
966 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
967 extern void i915_driver_lastclose(struct drm_device * dev);
968 extern void i915_driver_preclose(struct drm_device *dev,
969 struct drm_file *file_priv);
970 extern void i915_driver_postclose(struct drm_device *dev,
971 struct drm_file *file_priv);
972 extern int i915_driver_device_is_agp(struct drm_device * dev);
973 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
975 extern int i915_emit_box(struct drm_device *dev,
976 struct drm_clip_rect *box,
978 extern int i915_reset(struct drm_device *dev, u8 flags);
979 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
980 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
981 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
982 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
986 void i915_hangcheck_elapsed(unsigned long data);
987 void i915_handle_error(struct drm_device *dev, bool wedged);
988 extern int i915_irq_emit(struct drm_device *dev, void *data,
989 struct drm_file *file_priv);
990 extern int i915_irq_wait(struct drm_device *dev, void *data,
991 struct drm_file *file_priv);
992 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
993 extern void i915_enable_interrupt (struct drm_device *dev);
995 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
996 extern void i915_driver_irq_preinstall(struct drm_device * dev);
997 extern int i915_driver_irq_postinstall(struct drm_device *dev);
998 extern void i915_driver_irq_uninstall(struct drm_device * dev);
999 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1000 struct drm_file *file_priv);
1001 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1002 struct drm_file *file_priv);
1003 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1004 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1005 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1006 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1007 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv);
1009 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1010 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
1011 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
1013 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
1017 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1020 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1022 void intel_enable_asle (struct drm_device *dev);
1023 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1025 struct timeval *vblank_time,
1028 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1029 int *vpos, int *hpos);
1031 #ifdef CONFIG_DEBUG_FS
1032 extern void i915_destroy_error_state(struct drm_device *dev);
1034 #define i915_destroy_error_state(x)
1039 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1040 struct drm_file *file_priv);
1041 extern int i915_mem_free(struct drm_device *dev, void *data,
1042 struct drm_file *file_priv);
1043 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1044 struct drm_file *file_priv);
1045 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1046 struct drm_file *file_priv);
1047 extern void i915_mem_takedown(struct mem_block **heap);
1048 extern void i915_mem_release(struct drm_device * dev,
1049 struct drm_file *file_priv, struct mem_block *heap);
1051 int i915_gem_check_is_wedged(struct drm_device *dev);
1052 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1053 struct drm_file *file_priv);
1054 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv);
1056 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1057 struct drm_file *file_priv);
1058 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1059 struct drm_file *file_priv);
1060 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1061 struct drm_file *file_priv);
1062 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1063 struct drm_file *file_priv);
1064 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1065 struct drm_file *file_priv);
1066 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv);
1068 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv);
1070 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1071 struct drm_file *file_priv);
1072 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1073 struct drm_file *file_priv);
1074 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv);
1076 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv);
1080 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1084 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1085 struct drm_file *file_priv);
1086 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092 void i915_gem_load(struct drm_device *dev);
1093 int i915_gem_init_object(struct drm_gem_object *obj);
1094 void i915_gem_flush_ring(struct drm_device *dev,
1095 struct intel_ring_buffer *ring,
1096 uint32_t invalidate_domains,
1097 uint32_t flush_domains);
1098 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1100 void i915_gem_free_object(struct drm_gem_object *obj);
1101 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1103 bool map_and_fenceable);
1104 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1105 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1106 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1107 void i915_gem_lastclose(struct drm_device *dev);
1109 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1110 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1111 bool interruptible);
1112 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1113 struct intel_ring_buffer *ring,
1117 * Returns true if seq1 is later than seq2.
1120 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1122 return (int32_t)(seq1 - seq2) >= 0;
1126 i915_gem_next_request_seqno(struct drm_device *dev,
1127 struct intel_ring_buffer *ring)
1129 drm_i915_private_t *dev_priv = dev->dev_private;
1130 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1133 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1134 struct intel_ring_buffer *pipelined,
1135 bool interruptible);
1136 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1138 void i915_gem_retire_requests(struct drm_device *dev);
1139 void i915_gem_reset(struct drm_device *dev);
1140 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1141 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1142 uint32_t read_domains,
1143 uint32_t write_domain);
1144 int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1145 bool interruptible);
1146 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1147 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1148 void i915_gem_do_init(struct drm_device *dev,
1149 unsigned long start,
1150 unsigned long mappable_end,
1152 int __must_check i915_gpu_idle(struct drm_device *dev);
1153 int __must_check i915_gem_idle(struct drm_device *dev);
1154 int __must_check i915_add_request(struct drm_device *dev,
1155 struct drm_file *file_priv,
1156 struct drm_i915_gem_request *request,
1157 struct intel_ring_buffer *ring);
1158 int __must_check i915_do_wait_request(struct drm_device *dev,
1161 struct intel_ring_buffer *ring);
1162 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1164 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1167 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1168 struct intel_ring_buffer *pipelined);
1169 int i915_gem_attach_phys_object(struct drm_device *dev,
1170 struct drm_i915_gem_object *obj,
1173 void i915_gem_detach_phys_object(struct drm_device *dev,
1174 struct drm_i915_gem_object *obj);
1175 void i915_gem_free_all_phys_object(struct drm_device *dev);
1176 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1178 /* i915_gem_gtt.c */
1179 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1180 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1181 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1183 /* i915_gem_evict.c */
1184 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1185 unsigned alignment, bool mappable);
1186 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1187 bool purgeable_only);
1188 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1189 bool purgeable_only);
1191 /* i915_gem_tiling.c */
1192 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1193 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1194 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1196 /* i915_gem_debug.c */
1197 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1198 const char *where, uint32_t mark);
1200 int i915_verify_lists(struct drm_device *dev);
1202 #define i915_verify_lists(dev) 0
1204 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1206 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1207 const char *where, uint32_t mark);
1209 /* i915_debugfs.c */
1210 int i915_debugfs_init(struct drm_minor *minor);
1211 void i915_debugfs_cleanup(struct drm_minor *minor);
1213 /* i915_suspend.c */
1214 extern int i915_save_state(struct drm_device *dev);
1215 extern int i915_restore_state(struct drm_device *dev);
1217 /* i915_suspend.c */
1218 extern int i915_save_state(struct drm_device *dev);
1219 extern int i915_restore_state(struct drm_device *dev);
1222 extern int intel_setup_gmbus(struct drm_device *dev);
1223 extern void intel_teardown_gmbus(struct drm_device *dev);
1224 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1225 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1226 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1228 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1230 extern void intel_i2c_reset(struct drm_device *dev);
1232 /* intel_opregion.c */
1233 extern int intel_opregion_setup(struct drm_device *dev);
1235 extern void intel_opregion_init(struct drm_device *dev);
1236 extern void intel_opregion_fini(struct drm_device *dev);
1237 extern void intel_opregion_asle_intr(struct drm_device *dev);
1238 extern void intel_opregion_gse_intr(struct drm_device *dev);
1239 extern void intel_opregion_enable_asle(struct drm_device *dev);
1241 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1242 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1243 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1244 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1245 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1250 extern void intel_register_dsm_handler(void);
1251 extern void intel_unregister_dsm_handler(void);
1253 static inline void intel_register_dsm_handler(void) { return; }
1254 static inline void intel_unregister_dsm_handler(void) { return; }
1255 #endif /* CONFIG_ACPI */
1258 extern void intel_modeset_init(struct drm_device *dev);
1259 extern void intel_modeset_cleanup(struct drm_device *dev);
1260 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1261 extern void i8xx_disable_fbc(struct drm_device *dev);
1262 extern void g4x_disable_fbc(struct drm_device *dev);
1263 extern void ironlake_disable_fbc(struct drm_device *dev);
1264 extern void intel_disable_fbc(struct drm_device *dev);
1265 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1266 extern bool intel_fbc_enabled(struct drm_device *dev);
1267 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1268 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1269 extern void intel_detect_pch (struct drm_device *dev);
1270 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1273 #ifdef CONFIG_DEBUG_FS
1274 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1275 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1277 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1278 extern void intel_display_print_error_state(struct seq_file *m,
1279 struct drm_device *dev,
1280 struct intel_display_error_state *error);
1283 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1285 #define BEGIN_LP_RING(n) \
1286 intel_ring_begin(LP_RING(dev_priv), (n))
1288 #define OUT_RING(x) \
1289 intel_ring_emit(LP_RING(dev_priv), x)
1291 #define ADVANCE_LP_RING() \
1292 intel_ring_advance(LP_RING(dev_priv))
1295 * Lock test for when it's just for synchronization of ring access.
1297 * In that case, we don't need to do it when GEM is initialized as nobody else
1298 * has access to the ring.
1300 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1301 if (LP_RING(dev->dev_private)->obj == NULL) \
1302 LOCK_TEST_WITH_RETURN(dev, file); \
1306 #define __i915_read(x, y) \
1307 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1308 u##x val = read##y(dev_priv->regs + reg); \
1309 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1318 #define __i915_write(x, y) \
1319 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1320 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1321 write##y(val, dev_priv->regs + reg); \
1329 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1330 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1332 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1333 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1334 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1335 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1337 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1338 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1339 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1340 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1342 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1343 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1345 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1346 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1349 /* On SNB platform, before reading ring registers forcewake bit
1350 * must be set to prevent GT core from power down and stale values being
1353 void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
1354 void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
1355 static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1359 if (dev_priv->info->gen >= 6) {
1360 __gen6_force_wake_get(dev_priv);
1361 val = I915_READ(reg);
1362 __gen6_force_wake_put(dev_priv);
1364 val = I915_READ(reg);
1370 i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1372 /* Trace down the write operation before the real write */
1373 trace_i915_reg_rw('W', reg, val, len);
1376 writeq(val, dev_priv->regs + reg);
1379 writel(val, dev_priv->regs + reg);
1382 writew(val, dev_priv->regs + reg);
1385 writeb(val, dev_priv->regs + reg);
1391 * Reads a dword out of the status page, which is written to from the command
1392 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1393 * MI_STORE_DATA_IMM.
1395 * The following dwords have a reserved meaning:
1396 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1397 * 0x04: ring 0 head pointer
1398 * 0x05: ring 1 head pointer (915-class)
1399 * 0x06: ring 2 head pointer (915-class)
1400 * 0x10-0x1b: Context status DWords (GM45)
1401 * 0x1f: Last written status offset. (GM45)
1403 * The area from dword 0x20 to 0x3ff is available for driver usage.
1405 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1406 (LP_RING(dev_priv)->status_page.page_addr))[reg])
1407 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1408 #define I915_GEM_HWS_INDEX 0x20
1409 #define I915_BREADCRUMB_INDEX 0x21