1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_i915_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay;
118 struct intel_overlay_error_state;
120 struct drm_i915_master_private {
121 drm_local_map_t *sarea;
122 struct _drm_i915_sarea *sarea_priv;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg {
127 struct list_head lru_list;
128 struct drm_i915_gem_object *obj;
129 uint32_t setup_seqno;
132 struct sdvo_device_mapping {
142 struct intel_display_error_state;
144 struct drm_i915_error_state {
153 u32 error; /* gen6+ */
154 u32 bcs_acthd; /* gen6+ blt engine */
159 u32 vcs_acthd; /* gen6+ bsd engine */
171 struct drm_i915_error_object {
175 } *ringbuffer, *batchbuffer[2];
176 struct drm_i915_error_buffer {
189 } *active_bo, *pinned_bo;
190 u32 active_bo_count, pinned_bo_count;
191 struct intel_overlay_error_state *overlay;
192 struct intel_display_error_state *display;
195 struct drm_i915_display_funcs {
196 void (*dpms)(struct drm_crtc *crtc, int mode);
197 bool (*fbc_enabled)(struct drm_device *dev);
198 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
199 void (*disable_fbc)(struct drm_device *dev);
200 int (*get_display_clock_speed)(struct drm_device *dev);
201 int (*get_fifo_size)(struct drm_device *dev, int plane);
202 void (*update_wm)(struct drm_device *dev, int planea_clock,
203 int planeb_clock, int sr_hdisplay, int sr_htotal,
205 /* clock updates for mode set */
207 /* render clock increase/decrease */
208 /* display clock increase/decrease */
209 /* pll clock increase/decrease */
210 /* clock gating init */
213 struct intel_device_info {
223 u8 is_broadwater : 1;
226 u8 has_pipe_cxsr : 1;
228 u8 cursor_needs_physical : 1;
230 u8 overlay_needs_physical : 1;
237 FBC_NO_OUTPUT, /* no outputs enabled to compress */
238 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
239 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
240 FBC_MODE_TOO_LARGE, /* mode too large for compression */
241 FBC_BAD_PLANE, /* fbc not supported on plane */
242 FBC_NOT_TILED, /* buffer not tiled */
243 FBC_MULTIPLE_PIPES, /* more than one pipe active */
247 PCH_IBX, /* Ibexpeak PCH */
248 PCH_CPT, /* Cougarpoint PCH */
251 #define QUIRK_PIPEA_FORCE (1<<0)
255 typedef struct drm_i915_private {
256 struct drm_device *dev;
258 const struct intel_device_info *info;
261 int relative_constants_mode;
266 struct i2c_adapter adapter;
267 struct i2c_adapter *force_bit;
271 struct pci_dev *bridge_dev;
272 struct intel_ring_buffer ring[I915_NUM_RINGS];
275 drm_dma_handle_t *status_page_dmah;
276 dma_addr_t dma_status_page;
278 drm_local_map_t hws_map;
279 struct drm_i915_gem_object *pwrctx;
280 struct drm_i915_gem_object *renderctx;
282 struct resource mch_res;
290 atomic_t irq_received;
293 /* protects the irq masks */
295 /** Cached value of IMR to avoid reads in updating the bitfield */
301 u32 hotplug_supported_mask;
302 struct work_struct hotplug_work;
304 int tex_lru_log_granularity;
305 int allow_batchbuffer;
306 struct mem_block *agp_heap;
307 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
311 /* For hangcheck timer */
312 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
313 struct timer_list hangcheck_timer;
316 uint32_t last_instdone;
317 uint32_t last_instdone1;
319 unsigned long cfb_size;
320 unsigned long cfb_pitch;
321 unsigned long cfb_offset;
328 struct intel_opregion opregion;
331 struct intel_overlay *overlay;
334 int backlight_level; /* restore backlight to this value */
335 bool backlight_enabled;
336 struct drm_display_mode *panel_fixed_mode;
337 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
338 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
340 /* Feature bits from the VBIOS */
341 unsigned int int_tv_support:1;
342 unsigned int lvds_dither:1;
343 unsigned int lvds_vbt:1;
344 unsigned int int_crt_support:1;
345 unsigned int lvds_use_ssc:1;
356 struct edp_power_seq pps;
358 bool no_aux_handshake;
360 struct notifier_block lid_notifier;
363 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
364 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
365 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
367 unsigned int fsb_freq, mem_freq, is_ddr3;
369 spinlock_t error_lock;
370 struct drm_i915_error_state *first_error;
371 struct work_struct error_work;
372 struct completion error_completion;
373 struct workqueue_struct *wq;
375 /* Display functions */
376 struct drm_i915_display_funcs display;
378 /* PCH chipset type */
379 enum intel_pch pch_type;
381 unsigned long quirks;
406 u32 saveTRANS_HTOTAL_A;
407 u32 saveTRANS_HBLANK_A;
408 u32 saveTRANS_HSYNC_A;
409 u32 saveTRANS_VTOTAL_A;
410 u32 saveTRANS_VBLANK_A;
411 u32 saveTRANS_VSYNC_A;
419 u32 savePFIT_PGM_RATIOS;
420 u32 saveBLC_HIST_CTL;
422 u32 saveBLC_PWM_CTL2;
423 u32 saveBLC_CPU_PWM_CTL;
424 u32 saveBLC_CPU_PWM_CTL2;
437 u32 saveTRANS_HTOTAL_B;
438 u32 saveTRANS_HBLANK_B;
439 u32 saveTRANS_HSYNC_B;
440 u32 saveTRANS_VTOTAL_B;
441 u32 saveTRANS_VBLANK_B;
442 u32 saveTRANS_VSYNC_B;
456 u32 savePP_ON_DELAYS;
457 u32 savePP_OFF_DELAYS;
465 u32 savePFIT_CONTROL;
466 u32 save_palette_a[256];
467 u32 save_palette_b[256];
468 u32 saveDPFC_CB_BASE;
469 u32 saveFBC_CFB_BASE;
472 u32 saveFBC_CONTROL2;
482 u32 saveCACHE_MODE_0;
483 u32 saveMI_ARB_STATE;
494 uint64_t saveFENCE[16];
505 u32 savePIPEA_GMCH_DATA_M;
506 u32 savePIPEB_GMCH_DATA_M;
507 u32 savePIPEA_GMCH_DATA_N;
508 u32 savePIPEB_GMCH_DATA_N;
509 u32 savePIPEA_DP_LINK_M;
510 u32 savePIPEB_DP_LINK_M;
511 u32 savePIPEA_DP_LINK_N;
512 u32 savePIPEB_DP_LINK_N;
523 u32 savePCH_DREF_CONTROL;
524 u32 saveDISP_ARB_CTL;
525 u32 savePIPEA_DATA_M1;
526 u32 savePIPEA_DATA_N1;
527 u32 savePIPEA_LINK_M1;
528 u32 savePIPEA_LINK_N1;
529 u32 savePIPEB_DATA_M1;
530 u32 savePIPEB_DATA_N1;
531 u32 savePIPEB_LINK_M1;
532 u32 savePIPEB_LINK_N1;
533 u32 saveMCHBAR_RENDER_STANDBY;
536 /** Bridge to intel-gtt-ko */
537 const struct intel_gtt *gtt;
538 /** Memory allocator for GTT stolen memory */
539 struct drm_mm stolen;
540 /** Memory allocator for GTT */
541 struct drm_mm gtt_space;
542 /** List of all objects in gtt_space. Used to restore gtt
543 * mappings on resume */
544 struct list_head gtt_list;
545 /** End of mappable part of GTT */
546 unsigned long gtt_mappable_end;
548 struct io_mapping *gtt_mapping;
551 struct shrinker inactive_shrinker;
554 * List of objects currently involved in rendering.
556 * Includes buffers having the contents of their GPU caches
557 * flushed, not necessarily primitives. last_rendering_seqno
558 * represents when the rendering involved will be completed.
560 * A reference is held on the buffer while on this list.
562 struct list_head active_list;
565 * List of objects which are not in the ringbuffer but which
566 * still have a write_domain which needs to be flushed before
569 * last_rendering_seqno is 0 while an object is in this list.
571 * A reference is held on the buffer while on this list.
573 struct list_head flushing_list;
576 * LRU list of objects which are not in the ringbuffer and
577 * are ready to unbind, but are still in the GTT.
579 * last_rendering_seqno is 0 while an object is in this list.
581 * A reference is not held on the buffer while on this list,
582 * as merely being GTT-bound shouldn't prevent its being
583 * freed, and we'll pull it off the list in the free path.
585 struct list_head inactive_list;
588 * LRU list of objects which are not in the ringbuffer but
589 * are still pinned in the GTT.
591 struct list_head pinned_list;
593 /** LRU list of objects with fence regs on them. */
594 struct list_head fence_list;
597 * List of objects currently pending being freed.
599 * These objects are no longer in use, but due to a signal
600 * we were prevented from freeing them at the appointed time.
602 struct list_head deferred_free_list;
605 * We leave the user IRQ off as much as possible,
606 * but this means that requests will finish and never
607 * be retired once the system goes idle. Set a timer to
608 * fire periodically while the ring is running. When it
609 * fires, go retire requests.
611 struct delayed_work retire_work;
614 * Flag if the X Server, and thus DRM, is not currently in
615 * control of the device.
617 * This is set between LeaveVT and EnterVT. It needs to be
618 * replaced with a semaphore. It also needs to be
619 * transitioned away from for kernel modesetting.
624 * Flag if the hardware appears to be wedged.
626 * This is set when attempts to idle the device timeout.
627 * It prevents command submission from occuring and makes
628 * every pending request fail
632 /** Bit 6 swizzling required for X tiling */
633 uint32_t bit_6_swizzle_x;
634 /** Bit 6 swizzling required for Y tiling */
635 uint32_t bit_6_swizzle_y;
637 /* storage for physical objects */
638 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
640 /* accounting, useful for userland debugging */
642 size_t mappable_gtt_total;
643 size_t object_memory;
646 struct sdvo_device_mapping sdvo_mappings[2];
647 /* indicate whether the LVDS_BORDER should be enabled or not */
648 unsigned int lvds_border_bits;
649 /* Panel fitter placement and size for Ironlake+ */
650 u32 pch_pf_pos, pch_pf_size;
652 struct drm_crtc *plane_to_crtc_mapping[2];
653 struct drm_crtc *pipe_to_crtc_mapping[2];
654 wait_queue_head_t pending_flip_queue;
655 bool flip_pending_is_done;
657 /* Reclocking support */
658 bool render_reclock_avail;
659 bool lvds_downclock_avail;
660 /* indicates the reduced downclock for LVDS*/
662 struct work_struct idle_work;
663 struct timer_list idle_timer;
667 struct child_device_config *child_dev;
668 struct drm_connector *int_lvds_connector;
670 bool mchbar_need_disable;
679 unsigned long last_time1;
681 struct timespec last_time2;
682 unsigned long gfx_power;
686 spinlock_t *mchdev_lock;
688 enum no_fbc_reason no_fbc_reason;
690 struct drm_mm_node *compressed_fb;
691 struct drm_mm_node *compressed_llb;
693 unsigned long last_gpu_reset;
695 /* list of fbdev register on this device */
696 struct intel_fbdev *fbdev;
697 } drm_i915_private_t;
699 struct drm_i915_gem_object {
700 struct drm_gem_object base;
702 /** Current space allocated to this object in the GTT, if any. */
703 struct drm_mm_node *gtt_space;
704 struct list_head gtt_list;
706 /** This object's place on the active/flushing/inactive lists */
707 struct list_head ring_list;
708 struct list_head mm_list;
709 /** This object's place on GPU write list */
710 struct list_head gpu_write_list;
711 /** This object's place in the batchbuffer or on the eviction list */
712 struct list_head exec_list;
715 * This is set if the object is on the active or flushing lists
716 * (has pending rendering), and is not set if it's on inactive (ready
719 unsigned int active : 1;
722 * This is set if the object has been written to since last bound
725 unsigned int dirty : 1;
728 * This is set if the object has been written to since the last
731 unsigned int pending_gpu_write : 1;
734 * Fence register bits (if any) for this object. Will be set
735 * as needed when mapped into the GTT.
736 * Protected by dev->struct_mutex.
738 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
740 signed int fence_reg : 5;
743 * Advice: are the backing pages purgeable?
745 unsigned int madv : 2;
748 * Current tiling mode for the object.
750 unsigned int tiling_mode : 2;
751 unsigned int tiling_changed : 1;
753 /** How many users have pinned this object in GTT space. The following
754 * users can each hold at most one reference: pwrite/pread, pin_ioctl
755 * (via user_pin_count), execbuffer (objects are not allowed multiple
756 * times for the same batchbuffer), and the framebuffer code. When
757 * switching/pageflipping, the framebuffer code has at most two buffers
760 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
761 * bits with absolutely no headroom. So use 4 bits. */
762 unsigned int pin_count : 4;
763 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
766 * Is the object at the current location in the gtt mappable and
767 * fenceable? Used to avoid costly recalculations.
769 unsigned int map_and_fenceable : 1;
772 * Whether the current gtt mapping needs to be mappable (and isn't just
773 * mappable by accident). Track pin and fault separate for a more
774 * accurate mappable working set.
776 unsigned int fault_mappable : 1;
777 unsigned int pin_mappable : 1;
780 * Is the GPU currently using a fence to access this buffer,
782 unsigned int pending_fenced_gpu_access:1;
783 unsigned int fenced_gpu_access:1;
790 struct scatterlist *sg_list;
794 * Used for performing relocations during execbuffer insertion.
796 struct hlist_node exec_node;
797 unsigned long exec_handle;
800 * Current offset of the object in GTT space.
802 * This is the same as gtt_space->start
806 /** Breadcrumb of last rendering to the buffer. */
807 uint32_t last_rendering_seqno;
808 struct intel_ring_buffer *ring;
810 /** Breadcrumb of last fenced GPU access to the buffer. */
811 uint32_t last_fenced_seqno;
812 struct intel_ring_buffer *last_fenced_ring;
814 /** Current tiling stride for the object, if it's tiled. */
817 /** Record of address bit 17 of each page at last unbind. */
818 unsigned long *bit_17;
820 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
824 * If present, while GEM_DOMAIN_CPU is in the read domain this array
825 * flags which individual pages are valid.
827 uint8_t *page_cpu_valid;
829 /** User space pin count and filp owning the pin */
830 uint32_t user_pin_count;
831 struct drm_file *pin_filp;
833 /** for phy allocated objects */
834 struct drm_i915_gem_phys_object *phys_obj;
837 * Number of crtcs where this object is currently the fb, but
838 * will be page flipped away on the next vblank. When it
839 * reaches 0, dev_priv->pending_flip_queue will be woken up.
841 atomic_t pending_flip;
844 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
847 * Request queue structure.
849 * The request queue allows us to note sequence numbers that have been emitted
850 * and may be associated with active buffers to be retired.
852 * By keeping this list, we can avoid having to do questionable
853 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
854 * an emission time with seqnos for tracking how far ahead of the GPU we are.
856 struct drm_i915_gem_request {
857 /** On Which ring this request was generated */
858 struct intel_ring_buffer *ring;
860 /** GEM sequence number associated with this request. */
863 /** Time at which this request was emitted, in jiffies. */
864 unsigned long emitted_jiffies;
866 /** global list entry for this request */
867 struct list_head list;
869 struct drm_i915_file_private *file_priv;
870 /** file_priv list entry for this request */
871 struct list_head client_list;
874 struct drm_i915_file_private {
876 struct spinlock lock;
877 struct list_head request_list;
881 enum intel_chip_family {
888 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
890 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
891 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
892 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
893 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
894 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
895 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
896 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
897 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
898 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
899 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
900 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
901 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
902 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
903 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
904 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
905 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
906 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
907 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
908 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
910 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
911 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
912 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
913 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
914 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
916 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
917 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
918 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
920 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
921 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
923 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
924 * rows, which changed the alignment requirements and fence programming.
926 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
928 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
929 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
930 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
931 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
932 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
933 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
934 /* dsparb controlled by hw only */
935 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
937 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
938 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
939 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
941 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
942 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
944 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
945 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
946 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
948 #include "i915_trace.h"
950 extern struct drm_ioctl_desc i915_ioctls[];
951 extern int i915_max_ioctl;
952 extern unsigned int i915_fbpercrtc;
953 extern unsigned int i915_powersave;
954 extern unsigned int i915_lvds_downclock;
956 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
957 extern int i915_resume(struct drm_device *dev);
958 extern void i915_save_display(struct drm_device *dev);
959 extern void i915_restore_display(struct drm_device *dev);
960 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
961 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
964 extern void i915_kernel_lost_context(struct drm_device * dev);
965 extern int i915_driver_load(struct drm_device *, unsigned long flags);
966 extern int i915_driver_unload(struct drm_device *);
967 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
968 extern void i915_driver_lastclose(struct drm_device * dev);
969 extern void i915_driver_preclose(struct drm_device *dev,
970 struct drm_file *file_priv);
971 extern void i915_driver_postclose(struct drm_device *dev,
972 struct drm_file *file_priv);
973 extern int i915_driver_device_is_agp(struct drm_device * dev);
974 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
976 extern int i915_emit_box(struct drm_device *dev,
977 struct drm_clip_rect *box,
979 extern int i915_reset(struct drm_device *dev, u8 flags);
980 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
981 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
982 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
983 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
987 void i915_hangcheck_elapsed(unsigned long data);
988 void i915_handle_error(struct drm_device *dev, bool wedged);
989 extern int i915_irq_emit(struct drm_device *dev, void *data,
990 struct drm_file *file_priv);
991 extern int i915_irq_wait(struct drm_device *dev, void *data,
992 struct drm_file *file_priv);
993 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
994 extern void i915_enable_interrupt (struct drm_device *dev);
996 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
997 extern void i915_driver_irq_preinstall(struct drm_device * dev);
998 extern int i915_driver_irq_postinstall(struct drm_device *dev);
999 extern void i915_driver_irq_uninstall(struct drm_device * dev);
1000 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1001 struct drm_file *file_priv);
1002 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1003 struct drm_file *file_priv);
1004 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1005 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1006 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1007 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1008 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1011 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
1012 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
1014 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
1018 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1021 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1023 void intel_enable_asle (struct drm_device *dev);
1024 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1026 struct timeval *vblank_time,
1029 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1030 int *vpos, int *hpos);
1032 #ifdef CONFIG_DEBUG_FS
1033 extern void i915_destroy_error_state(struct drm_device *dev);
1035 #define i915_destroy_error_state(x)
1040 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1041 struct drm_file *file_priv);
1042 extern int i915_mem_free(struct drm_device *dev, void *data,
1043 struct drm_file *file_priv);
1044 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1045 struct drm_file *file_priv);
1046 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1048 extern void i915_mem_takedown(struct mem_block **heap);
1049 extern void i915_mem_release(struct drm_device * dev,
1050 struct drm_file *file_priv, struct mem_block *heap);
1052 int i915_gem_check_is_wedged(struct drm_device *dev);
1053 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv);
1055 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1056 struct drm_file *file_priv);
1057 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1058 struct drm_file *file_priv);
1059 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1060 struct drm_file *file_priv);
1061 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1062 struct drm_file *file_priv);
1063 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1064 struct drm_file *file_priv);
1065 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1066 struct drm_file *file_priv);
1067 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *file_priv);
1069 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1070 struct drm_file *file_priv);
1071 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1072 struct drm_file *file_priv);
1073 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1074 struct drm_file *file_priv);
1075 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv);
1077 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv);
1079 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1080 struct drm_file *file_priv);
1081 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1082 struct drm_file *file_priv);
1083 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1084 struct drm_file *file_priv);
1085 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1086 struct drm_file *file_priv);
1087 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1088 struct drm_file *file_priv);
1089 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv);
1091 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1092 struct drm_file *file_priv);
1093 void i915_gem_load(struct drm_device *dev);
1094 int i915_gem_init_object(struct drm_gem_object *obj);
1095 void i915_gem_flush_ring(struct drm_device *dev,
1096 struct intel_ring_buffer *ring,
1097 uint32_t invalidate_domains,
1098 uint32_t flush_domains);
1099 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1101 void i915_gem_free_object(struct drm_gem_object *obj);
1102 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1104 bool map_and_fenceable);
1105 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1106 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1107 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1108 void i915_gem_lastclose(struct drm_device *dev);
1110 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1111 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1112 bool interruptible);
1113 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1114 struct intel_ring_buffer *ring,
1118 * Returns true if seq1 is later than seq2.
1121 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1123 return (int32_t)(seq1 - seq2) >= 0;
1127 i915_gem_next_request_seqno(struct drm_device *dev,
1128 struct intel_ring_buffer *ring)
1130 drm_i915_private_t *dev_priv = dev->dev_private;
1131 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1134 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1135 struct intel_ring_buffer *pipelined,
1136 bool interruptible);
1137 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1139 void i915_gem_retire_requests(struct drm_device *dev);
1140 void i915_gem_reset(struct drm_device *dev);
1141 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1142 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1143 uint32_t read_domains,
1144 uint32_t write_domain);
1145 int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1146 bool interruptible);
1147 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1148 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1149 void i915_gem_do_init(struct drm_device *dev,
1150 unsigned long start,
1151 unsigned long mappable_end,
1153 int __must_check i915_gpu_idle(struct drm_device *dev);
1154 int __must_check i915_gem_idle(struct drm_device *dev);
1155 int __must_check i915_add_request(struct drm_device *dev,
1156 struct drm_file *file_priv,
1157 struct drm_i915_gem_request *request,
1158 struct intel_ring_buffer *ring);
1159 int __must_check i915_do_wait_request(struct drm_device *dev,
1162 struct intel_ring_buffer *ring);
1163 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1165 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1168 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1169 struct intel_ring_buffer *pipelined);
1170 int i915_gem_attach_phys_object(struct drm_device *dev,
1171 struct drm_i915_gem_object *obj,
1174 void i915_gem_detach_phys_object(struct drm_device *dev,
1175 struct drm_i915_gem_object *obj);
1176 void i915_gem_free_all_phys_object(struct drm_device *dev);
1177 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1179 /* i915_gem_gtt.c */
1180 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1181 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1182 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1184 /* i915_gem_evict.c */
1185 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1186 unsigned alignment, bool mappable);
1187 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1188 bool purgeable_only);
1189 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1190 bool purgeable_only);
1192 /* i915_gem_tiling.c */
1193 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1194 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1195 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1197 /* i915_gem_debug.c */
1198 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1199 const char *where, uint32_t mark);
1201 int i915_verify_lists(struct drm_device *dev);
1203 #define i915_verify_lists(dev) 0
1205 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1207 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1208 const char *where, uint32_t mark);
1210 /* i915_debugfs.c */
1211 int i915_debugfs_init(struct drm_minor *minor);
1212 void i915_debugfs_cleanup(struct drm_minor *minor);
1214 /* i915_suspend.c */
1215 extern int i915_save_state(struct drm_device *dev);
1216 extern int i915_restore_state(struct drm_device *dev);
1218 /* i915_suspend.c */
1219 extern int i915_save_state(struct drm_device *dev);
1220 extern int i915_restore_state(struct drm_device *dev);
1223 extern int intel_setup_gmbus(struct drm_device *dev);
1224 extern void intel_teardown_gmbus(struct drm_device *dev);
1225 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1226 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1227 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1229 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1231 extern void intel_i2c_reset(struct drm_device *dev);
1233 /* intel_opregion.c */
1234 extern int intel_opregion_setup(struct drm_device *dev);
1236 extern void intel_opregion_init(struct drm_device *dev);
1237 extern void intel_opregion_fini(struct drm_device *dev);
1238 extern void intel_opregion_asle_intr(struct drm_device *dev);
1239 extern void intel_opregion_gse_intr(struct drm_device *dev);
1240 extern void intel_opregion_enable_asle(struct drm_device *dev);
1242 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1243 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1244 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1245 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1246 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1251 extern void intel_register_dsm_handler(void);
1252 extern void intel_unregister_dsm_handler(void);
1254 static inline void intel_register_dsm_handler(void) { return; }
1255 static inline void intel_unregister_dsm_handler(void) { return; }
1256 #endif /* CONFIG_ACPI */
1259 extern void intel_modeset_init(struct drm_device *dev);
1260 extern void intel_modeset_cleanup(struct drm_device *dev);
1261 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1262 extern void i8xx_disable_fbc(struct drm_device *dev);
1263 extern void g4x_disable_fbc(struct drm_device *dev);
1264 extern void ironlake_disable_fbc(struct drm_device *dev);
1265 extern void intel_disable_fbc(struct drm_device *dev);
1266 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1267 extern bool intel_fbc_enabled(struct drm_device *dev);
1268 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1269 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1270 extern void intel_detect_pch (struct drm_device *dev);
1271 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1274 #ifdef CONFIG_DEBUG_FS
1275 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1276 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1278 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1279 extern void intel_display_print_error_state(struct seq_file *m,
1280 struct drm_device *dev,
1281 struct intel_display_error_state *error);
1284 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1286 #define BEGIN_LP_RING(n) \
1287 intel_ring_begin(LP_RING(dev_priv), (n))
1289 #define OUT_RING(x) \
1290 intel_ring_emit(LP_RING(dev_priv), x)
1292 #define ADVANCE_LP_RING() \
1293 intel_ring_advance(LP_RING(dev_priv))
1296 * Lock test for when it's just for synchronization of ring access.
1298 * In that case, we don't need to do it when GEM is initialized as nobody else
1299 * has access to the ring.
1301 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1302 if (LP_RING(dev->dev_private)->obj == NULL) \
1303 LOCK_TEST_WITH_RETURN(dev, file); \
1307 #define __i915_read(x, y) \
1308 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1309 u##x val = read##y(dev_priv->regs + reg); \
1310 trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1319 #define __i915_write(x, y) \
1320 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1321 trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1322 write##y(val, dev_priv->regs + reg); \
1330 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1331 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1333 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1334 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1335 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1336 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1338 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1339 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1340 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1341 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1343 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1344 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1346 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1347 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1350 /* On SNB platform, before reading ring registers forcewake bit
1351 * must be set to prevent GT core from power down and stale values being
1354 void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
1355 void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
1356 static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1360 if (dev_priv->info->gen >= 6) {
1361 __gen6_force_wake_get(dev_priv);
1362 val = I915_READ(reg);
1363 __gen6_force_wake_put(dev_priv);
1365 val = I915_READ(reg);
1371 i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1373 /* Trace down the write operation before the real write */
1374 trace_i915_reg_rw('W', reg, val, len);
1377 writeq(val, dev_priv->regs + reg);
1380 writel(val, dev_priv->regs + reg);
1383 writew(val, dev_priv->regs + reg);
1386 writeb(val, dev_priv->regs + reg);
1392 * Reads a dword out of the status page, which is written to from the command
1393 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1394 * MI_STORE_DATA_IMM.
1396 * The following dwords have a reserved meaning:
1397 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1398 * 0x04: ring 0 head pointer
1399 * 0x05: ring 1 head pointer (915-class)
1400 * 0x06: ring 2 head pointer (915-class)
1401 * 0x10-0x1b: Context status DWords (GM45)
1402 * 0x1f: Last written status offset. (GM45)
1404 * The area from dword 0x20 to 0x3ff is available for driver usage.
1406 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1407 (LP_RING(dev_priv)->status_page.page_addr))[reg])
1408 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1409 #define I915_GEM_HWS_INDEX 0x20
1410 #define I915_BREADCRUMB_INDEX 0x21